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maciejbocianskimaciejbocianski
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astyle fixes on QSPI API/driver/tests
1 parent ad49388 commit 883ea2f

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6 files changed

+72
-74
lines changed

6 files changed

+72
-74
lines changed

‎TESTS/mbed_hal/qspi/main.cpp

Lines changed: 12 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -99,12 +99,11 @@ static void _qspi_write_read_test(Qspi &qspi, qspi_bus_width_t write_inst_width,
9999
int erase_time = 0, write_time = 0, read_time = 0;
100100
size_t buf_len = data_size;
101101

102-
for (uint32_t tc = 0; tc < test_count; tc++)
103-
{
102+
for (uint32_t tc = 0; tc < test_count; tc++) {
104103
qspi.cmd.configure(MODE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8);
105104

106-
srand (ticker_read(get_us_ticker_data()));
107-
for(uint32_t i = 0; i < data_size; i++) {
105+
srand(ticker_read(get_us_ticker_data()));
106+
for (uint32_t i = 0; i < data_size; i++) {
108107
tx_buf[i] = (uint8_t)(rand() & 0xFF);
109108
}
110109

@@ -127,8 +126,7 @@ static void _qspi_write_read_test(Qspi &qspi, qspi_bus_width_t write_inst_width,
127126
}
128127

129128
const uint32_t write_size = data_size / write_count;
130-
for (uint32_t wc = 0, write_start = flash_addr; wc < write_count; wc++, write_start += write_size)
131-
{
129+
for (uint32_t wc = 0, write_start = flash_addr; wc < write_count; wc++, write_start += write_size) {
132130
ret = write_enable(qspi);
133131
TEST_ASSERT_EQUAL(QSPI_STATUS_OK, ret);
134132

@@ -157,8 +155,7 @@ static void _qspi_write_read_test(Qspi &qspi, qspi_bus_width_t write_inst_width,
157155
memset(rx_buf, 0, sizeof(rx_buf));
158156
const uint32_t read_size = data_size / read_count;
159157
qspi.cmd.configure(read_inst_width, read_addr_width, read_data_width, read_alt_width, read_addr_size, read_alt_size, read_dummy_cycles);
160-
for (uint32_t rc = 0, read_start = flash_addr; rc < read_count; rc++, read_start += read_size)
161-
{
158+
for (uint32_t rc = 0, read_start = flash_addr; rc < read_count; rc++, read_start += read_size) {
162159
timer.reset();
163160
timer.start();
164161

@@ -226,14 +223,14 @@ void qspi_write_read_test(void)
226223
flash_init(qspi);
227224

228225
if (is_dual_cmd(write_inst_width, write_addr_width, write_data_width) ||
229-
is_dual_cmd(read_inst_width, read_addr_width, read_data_width)) {
226+
is_dual_cmd(read_inst_width, read_addr_width, read_data_width)) {
230227
ret = dual_enable(qspi);
231228
TEST_ASSERT_EQUAL(QSPI_STATUS_OK, ret);
232229
WAIT_FOR(WRSR_MAX_TIME, qspi);
233230
}
234231

235232
if (is_quad_cmd(write_inst_width, write_addr_width, write_data_width) ||
236-
is_quad_cmd(read_inst_width, read_addr_width, read_data_width)) {
233+
is_quad_cmd(read_inst_width, read_addr_width, read_data_width)) {
237234
ret = quad_enable(qspi);
238235
TEST_ASSERT_EQUAL(QSPI_STATUS_OK, ret);
239236
WAIT_FOR(WRSR_MAX_TIME, qspi);
@@ -270,14 +267,14 @@ void qspi_write_read_test(void)
270267
qspi.cmd.configure(MODE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8);
271268

272269
if (is_dual_cmd(write_inst_width, write_addr_width, write_data_width) ||
273-
is_dual_cmd(read_inst_width, read_addr_width, read_data_width)) {
270+
is_dual_cmd(read_inst_width, read_addr_width, read_data_width)) {
274271
ret = dual_disable(qspi);
275272
TEST_ASSERT_EQUAL(QSPI_STATUS_OK, ret);
276273
WAIT_FOR(WRSR_MAX_TIME, qspi);
277274
}
278275

279276
if (is_quad_cmd(write_inst_width, write_addr_width, write_data_width) ||
280-
is_quad_cmd(read_inst_width, read_addr_width, read_data_width)) {
277+
is_quad_cmd(read_inst_width, read_addr_width, read_data_width)) {
281278
ret = quad_disable(qspi);
282279
TEST_ASSERT_EQUAL(QSPI_STATUS_OK, ret);
283280
WAIT_FOR(WRSR_MAX_TIME, qspi);
@@ -352,21 +349,21 @@ void qspi_frequency_test(void)
352349
flash_init(qspi);
353350
_qspi_write_read_test(qspi, WRITE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_NONE, WRITE_SINGLE, READ_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_NONE, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS);
354351

355-
ret = qspi_frequency(&qspi.handle, QSPI_COMMON_MAX_FREQUENCY/2);
352+
ret = qspi_frequency(&qspi.handle, QSPI_COMMON_MAX_FREQUENCY / 2);
356353
TEST_ASSERT_EQUAL(QSPI_STATUS_OK, ret);
357354
// check if the memory is working properly
358355
qspi.cmd.configure(MODE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8);
359356
flash_init(qspi);
360357
_qspi_write_read_test(qspi, WRITE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_NONE, WRITE_SINGLE, READ_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_NONE, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS);
361358

362-
ret = qspi_frequency(&qspi.handle, QSPI_COMMON_MAX_FREQUENCY/4);
359+
ret = qspi_frequency(&qspi.handle, QSPI_COMMON_MAX_FREQUENCY / 4);
363360
TEST_ASSERT_EQUAL(QSPI_STATUS_OK, ret);
364361
// check if the memory is working properly
365362
qspi.cmd.configure(MODE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8);
366363
flash_init(qspi);
367364
_qspi_write_read_test(qspi, WRITE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_NONE, WRITE_SINGLE, READ_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_NONE, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS);
368365

369-
ret = qspi_frequency(&qspi.handle, QSPI_COMMON_MAX_FREQUENCY/8);
366+
ret = qspi_frequency(&qspi.handle, QSPI_COMMON_MAX_FREQUENCY / 8);
370367
TEST_ASSERT_EQUAL(QSPI_STATUS_OK, ret);
371368
// check if the memory is working properly
372369
qspi.cmd.configure(MODE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8);

‎TESTS/mbed_hal/qspi/qspi_test_utils.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -32,7 +32,7 @@ void QspiCommand::configure(qspi_bus_width_t inst_width, qspi_bus_width_t addr_w
3232
qspi_address_size_t addr_size, qspi_alt_size_t alt_size,
3333
int dummy_cycles)
3434
{
35-
memset(&_cmd, 0, sizeof(qspi_command_t) );
35+
memset(&_cmd, 0, sizeof(qspi_command_t));
3636
_cmd.instruction.disabled = _cmd.address.disabled = _cmd.alt.disabled = true;
3737

3838
_cmd.instruction.bus_width = inst_width;
@@ -62,7 +62,7 @@ void QspiCommand::build(int instruction, int address, int alt)
6262
}
6363
}
6464

65-
qspi_command_t* QspiCommand::get()
65+
qspi_command_t *QspiCommand::get()
6666
{
6767
return &_cmd;
6868
}
@@ -175,7 +175,7 @@ void log_register(uint32_t cmd, uint32_t reg_size, Qspi &qspi, const char *str)
175175

176176
for (uint32_t j = 0; j < reg_size; j++) {
177177
utest_printf("%s byte %u (MSB first): ", str != NULL ? str : "", j);
178-
for(int i = 0; i < 8; i++) {
178+
for (int i = 0; i < 8; i++) {
179179
utest_printf("%s ", ((reg[j] & (1 << (7 - i))) & 0xFF) == 0 ? "0" : "1");
180180
}
181181
utest_printf("\r\n");

‎TESTS/mbed_hal/qspi/qspi_test_utils.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -36,7 +36,7 @@ class QspiCommand {
3636

3737
void build(int instruction, int address = QSPI_NONE, int alt = QSPI_NONE);
3838

39-
qspi_command_t * get();
39+
qspi_command_t *get();
4040

4141
private:
4242
qspi_command_t _cmd;

‎drivers/QSPI.cpp

Lines changed: 28 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -22,10 +22,10 @@
2222

2323
namespace mbed {
2424

25-
QSPI* QSPI::_owner = NULL;
25+
QSPI *QSPI::_owner = NULL;
2626
SingletonPtr<PlatformMutex> QSPI::_mutex;
2727

28-
QSPI::QSPI(PinName io0, PinName io1, PinName io2, PinName io3, PinName sclk, PinName ssel, int mode) : _qspi()
28+
QSPI::QSPI(PinName io0, PinName io1, PinName io2, PinName io3, PinName sclk, PinName ssel, int mode) : _qspi()
2929
{
3030
_qspi_io0 = io0;
3131
_qspi_io1 = io1;
@@ -67,7 +67,7 @@ qspi_status_t QSPI::configure_format(qspi_bus_width_t inst_width, qspi_bus_width
6767
return ret_status;
6868
}
6969

70-
qspi_status_t QSPI::set_frequency(int hz)
70+
qspi_status_t QSPI::set_frequency(int hz)
7171
{
7272
qspi_status_t ret_status = QSPI_STATUS_OK;
7373

@@ -91,7 +91,7 @@ qspi_status_t QSPI::set_frequency(int hz)
9191
return ret_status;
9292
}
9393

94-
qspi_status_t QSPI::read(unsigned int address, char *rx_buffer, size_t *rx_length)
94+
qspi_status_t QSPI::read(unsigned int address, char *rx_buffer, size_t *rx_length)
9595
{
9696
qspi_status_t ret_status = QSPI_STATUS_ERROR;
9797

@@ -115,10 +115,10 @@ qspi_status_t QSPI::read(unsigned int address, char *rx_buffer, size_t *rx_lengt
115115
return ret_status;
116116
}
117117

118-
qspi_status_t QSPI::write(unsigned int address, const char *tx_buffer, size_t *tx_length)
118+
qspi_status_t QSPI::write(unsigned int address, const char *tx_buffer, size_t *tx_length)
119119
{
120120
qspi_status_t ret_status = QSPI_STATUS_ERROR;
121-
121+
122122
if (_initialized) {
123123
if ((tx_length != NULL) && (tx_buffer != NULL)) {
124124
if (*tx_length != 0) {
@@ -139,15 +139,15 @@ qspi_status_t QSPI::write(unsigned int address, const char *tx_buffer, size_t *t
139139
return ret_status;
140140
}
141141

142-
qspi_status_t QSPI::read(unsigned int instruction, unsigned int alt, unsigned int address, char *rx_buffer, size_t *rx_length)
142+
qspi_status_t QSPI::read(unsigned int instruction, unsigned int alt, unsigned int address, char *rx_buffer, size_t *rx_length)
143143
{
144144
qspi_status_t ret_status = QSPI_STATUS_ERROR;
145145

146146
if (_initialized) {
147-
if ( (rx_length != NULL) && (rx_buffer != NULL) ) {
147+
if ((rx_length != NULL) && (rx_buffer != NULL)) {
148148
if (*rx_length != 0) {
149149
lock();
150-
if ( true == _acquire()) {
150+
if (true == _acquire()) {
151151
_build_qspi_command(instruction, address, alt);
152152
if (QSPI_STATUS_OK == qspi_read(&_qspi, &_qspi_command, rx_buffer, rx_length)) {
153153
ret_status = QSPI_STATUS_OK;
@@ -159,16 +159,16 @@ qspi_status_t QSPI::read(unsigned int instruction, unsigned int alt, unsigned in
159159
ret_status = QSPI_STATUS_INVALID_PARAMETER;
160160
}
161161
}
162-
162+
163163
return ret_status;
164164
}
165165

166-
qspi_status_t QSPI::write(unsigned int instruction, unsigned int alt, unsigned int address, const char *tx_buffer, size_t *tx_length)
166+
qspi_status_t QSPI::write(unsigned int instruction, unsigned int alt, unsigned int address, const char *tx_buffer, size_t *tx_length)
167167
{
168168
qspi_status_t ret_status = QSPI_STATUS_ERROR;
169-
169+
170170
if (_initialized) {
171-
if ( (tx_length != NULL) && (tx_buffer != NULL) ) {
171+
if ((tx_length != NULL) && (tx_buffer != NULL)) {
172172
if (*tx_length != 0) {
173173
lock();
174174
if (true == _acquire()) {
@@ -183,71 +183,71 @@ qspi_status_t QSPI::write(unsigned int instruction, unsigned int alt, unsigned i
183183
ret_status = QSPI_STATUS_INVALID_PARAMETER;
184184
}
185185
}
186-
186+
187187
return ret_status;
188188
}
189189

190-
qspi_status_t QSPI::command_transfer(unsigned int instruction, int address, const char *tx_buffer, size_t tx_length, const char *rx_buffer, size_t rx_length)
190+
qspi_status_t QSPI::command_transfer(unsigned int instruction, int address, const char *tx_buffer, size_t tx_length, const char *rx_buffer, size_t rx_length)
191191
{
192192
qspi_status_t ret_status = QSPI_STATUS_ERROR;
193-
193+
194194
if (_initialized) {
195195
lock();
196196
if (true == _acquire()) {
197197
_build_qspi_command(instruction, address, -1); //We just need the command
198198
if (QSPI_STATUS_OK == qspi_command_transfer(&_qspi, &_qspi_command, (const void *)tx_buffer, tx_length, (void *)rx_buffer, rx_length)) {
199199
ret_status = QSPI_STATUS_OK;
200200
}
201-
}
201+
}
202202
unlock();
203203
}
204-
204+
205205
return ret_status;
206206
}
207207

208-
void QSPI::lock()
208+
void QSPI::lock()
209209
{
210210
_mutex->lock();
211211
}
212212

213-
void QSPI::unlock()
213+
void QSPI::unlock()
214214
{
215215
_mutex->unlock();
216216
}
217217

218218
// Note: Private helper function to initialize qspi HAL
219-
bool QSPI::_initialize()
219+
bool QSPI::_initialize()
220220
{
221221
if (_mode != 0 && _mode != 1) {
222222
_initialized = false;
223223
return _initialized;
224224
}
225225

226-
qspi_status_t ret = qspi_init(&_qspi, _qspi_io0, _qspi_io1, _qspi_io2, _qspi_io3, _qspi_clk, _qspi_cs, _hz, _mode );
226+
qspi_status_t ret = qspi_init(&_qspi, _qspi_io0, _qspi_io1, _qspi_io2, _qspi_io3, _qspi_clk, _qspi_cs, _hz, _mode);
227227
if (QSPI_STATUS_OK == ret) {
228228
_initialized = true;
229229
} else {
230230
_initialized = false;
231231
}
232-
232+
233233
return _initialized;
234234
}
235235

236236
// Note: Private function with no locking
237-
bool QSPI::_acquire()
237+
bool QSPI::_acquire()
238238
{
239239
if (_owner != this) {
240240
//This will set freq as well
241241
_initialize();
242242
_owner = this;
243243
}
244-
244+
245245
return _initialized;
246246
}
247247

248-
void QSPI::_build_qspi_command(int instruction, int address, int alt)
248+
void QSPI::_build_qspi_command(int instruction, int address, int alt)
249249
{
250-
memset( &_qspi_command, 0, sizeof(qspi_command_t) );
250+
memset(&_qspi_command, 0, sizeof(qspi_command_t));
251251
//Set up instruction phase parameters
252252
_qspi_command.instruction.bus_width = _inst_width;
253253
if (instruction != -1) {
@@ -271,7 +271,7 @@ void QSPI::_build_qspi_command(int instruction, int address, int alt)
271271
_qspi_command.alt.bus_width = _alt_width;
272272
_qspi_command.alt.size = _alt_size;
273273
if (alt != -1) {
274-
_qspi_command.alt.value = alt;
274+
_qspi_command.alt.value = alt;
275275
_qspi_command.alt.disabled = false;
276276
} else {
277277
_qspi_command.alt.disabled = true;

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