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Cruz Monrreal
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Merge pull request #7825 from SiliconLabs/siliconlabs-qspi
Silicon Labs QSPI HAL implementation
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‎TESTS/mbed_hal/qspi/flash_configs/MX25R3235F_config.h

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/* mbed Microcontroller Library
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* Copyright (c) 2018-2018 ARM Limited
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef MBED_QSPI_FLASH_MX25R3235F_H
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#define MBED_QSPI_FLASH_MX25R3235F_H
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#define QSPI_FLASH_CHIP_STRING "macronix MX25R3235F"
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// Command for reading status register
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#define QSPI_CMD_RDSR 0x05
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// Command for reading configuration register
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#define QSPI_CMD_RDCR0 0x15
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// Command for writing status/configuration register
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#define QSPI_CMD_WRSR 0x01
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// Command for reading security register
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#define QSPI_CMD_RDSCUR 0x2B
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// Command for setting Reset Enable
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#define QSPI_CMD_RSTEN 0x66
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// Command for setting Reset
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#define QSPI_CMD_RST 0x99
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// Command for setting write enable
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#define QSPI_CMD_WREN 0x06
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// Command for setting write disable
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#define QSPI_CMD_WRDI 0x04
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// WRSR operations max time [us] (datasheet max time + 15%)
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#define QSPI_WRSR_MAX_TIME 34500 // 30ms
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// general wait max time [us]
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#define QSPI_WAIT_MAX_TIME 100000 // 100ms
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// Commands for writing (page programming)
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#define QSPI_CMD_WRITE_1IO 0x02 // 1-1-1 mode
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#define QSPI_CMD_WRITE_4IO 0x38 // 1-4-4 mode
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// write operations max time [us] (datasheet max time + 15%)
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#define QSPI_PAGE_PROG_MAX_TIME 11500 // 10ms
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#define QSPI_PAGE_SIZE 256 // 256B
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// Commands for reading
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#define QSPI_CMD_READ_1IO_FAST 0x0B // 1-1-1 mode
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#define QSPI_CMD_READ_1IO 0x03 // 1-1-1 mode
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#define QSPI_CMD_READ_2IO 0xBB // 1-2-2 mode
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#define QSPI_CMD_READ_1I2O 0x3B // 1-1-2 mode
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#define QSPI_CMD_READ_4IO 0xEB // 1-4-4 mode
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#define QSPI_CMD_READ_1I4O 0x6B // 1-1-4 mode
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#define QSPI_READ_1IO_DUMMY_CYCLE 0
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#define QSPI_READ_FAST_DUMMY_CYCLE 8
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#define QSPI_READ_2IO_DUMMY_CYCLE 4
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#define QSPI_READ_1I2O_DUMMY_CYCLE 8
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#define QSPI_READ_4IO_DUMMY_CYCLE 6
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#define QSPI_READ_1I4O_DUMMY_CYCLE 8
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// Commands for erasing
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#define QSPI_CMD_ERASE_SECTOR 0x20 // 4kB
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#define QSPI_CMD_ERASE_BLOCK_32 0x52 // 32kB
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#define QSPI_CMD_ERASE_BLOCK_64 0xD8 // 64kB
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#define QSPI_CMD_ERASE_CHIP 0x60 // or 0xC7
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// erase operations max time [us] (datasheet max time + 15%)
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#define QSPI_ERASE_SECTOR_MAX_TIME 276000 // 240 ms
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#define QSPI_ERASE_BLOCK_32_MAX_TIME 3450000 // 3s
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#define QSPI_ERASE_BLOCK_64_MAX_TIME 4025000 // 3.5s
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// max frequency for basic rw operation
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#define QSPI_COMMON_MAX_FREQUENCY 32000000
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#define QSPI_STATUS_REG_SIZE 1
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#define QSPI_CONFIG_REG_0_SIZE 2
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#define QSPI_SECURITY_REG_SIZE 1
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#define QSPI_MAX_REG_SIZE 2
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// status register
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#define STATUS_BIT_WIP (1 << 0) // write in progress bit
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#define STATUS_BIT_WEL (1 << 1) // write enable latch
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#define STATUS_BIT_BP0 (1 << 2) //
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#define STATUS_BIT_BP1 (1 << 3) //
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#define STATUS_BIT_BP2 (1 << 4) //
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#define STATUS_BIT_BP3 (1 << 5) //
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#define STATUS_BIT_QE (1 << 6) // Quad Enable
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#define STATUS_BIT_SRWD (1 << 7) // status register write protect
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// configuration register 0
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// bit 0, 1, 2, 4, 5, 7 reserved
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#define CONFIG0_BIT_TB (1 << 3) // Top/Bottom area protect
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#define CONFIG0_BIT_DC (1 << 6) // Dummy Cycle
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// configuration register 1
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// bit 0, 2, 3, 4, 5, 6, 7 reserved
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#define CONFIG1_BIT_LH (1 << 1) // 0 = Ultra Low power mode, 1 = High performance mode
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// single quad enable flag for both dual and quad mode
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#define QUAD_ENABLE() \
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\
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uint8_t reg_data[QSPI_STATUS_REG_SIZE]; \
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\
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if (write_enable(qspi) != QSPI_STATUS_OK) { \
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return QSPI_STATUS_ERROR; \
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} \
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WAIT_FOR(WRSR_MAX_TIME, qspi); \
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\
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reg_data[0] = STATUS_BIT_QE; \
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qspi.cmd.build(QSPI_CMD_WRSR); \
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\
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if (qspi_command_transfer(&qspi.handle, qspi.cmd.get(), \
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reg_data, QSPI_STATUS_REG_SIZE, NULL, 0) != QSPI_STATUS_OK) { \
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return QSPI_STATUS_ERROR; \
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} \
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WAIT_FOR(WRSR_MAX_TIME, qspi); \
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\
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memset(reg_data, 0, QSPI_STATUS_REG_SIZE); \
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if (read_register(STATUS_REG, reg_data, \
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QSPI_STATUS_REG_SIZE, qspi) != QSPI_STATUS_OK) { \
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return QSPI_STATUS_ERROR; \
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} \
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\
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return ((reg_data[0] & STATUS_BIT_QE) != 0 ? \
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QSPI_STATUS_OK : QSPI_STATUS_ERROR)
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#define QUAD_DISABLE() \
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\
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uint8_t reg_data[QSPI_STATUS_REG_SIZE]; \
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\
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if (write_enable(qspi) != QSPI_STATUS_OK) { \
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return QSPI_STATUS_ERROR; \
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} \
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WAIT_FOR(WRSR_MAX_TIME, qspi); \
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\
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reg_data[0] = 0; \
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qspi.cmd.build(QSPI_CMD_WRSR); \
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\
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if (qspi_command_transfer(&qspi.handle, qspi.cmd.get(), \
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reg_data, QSPI_STATUS_REG_SIZE, NULL, 0) != QSPI_STATUS_OK) { \
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return QSPI_STATUS_ERROR; \
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} \
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WAIT_FOR(WRSR_MAX_TIME, qspi); \
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\
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reg_data[0] = 0; \
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if (read_register(STATUS_REG, reg_data, \
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QSPI_STATUS_REG_SIZE, qspi) != QSPI_STATUS_OK) { \
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return QSPI_STATUS_ERROR; \
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} \
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\
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return ((reg_data[0] & STATUS_BIT_QE) == 0 ? \
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QSPI_STATUS_OK : QSPI_STATUS_ERROR)
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#define FAST_MODE_ENABLE() \
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\
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qspi_status_t ret; \
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const int32_t reg_size = QSPI_STATUS_REG_SIZE + QSPI_CONFIG_REG_0_SIZE; \
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uint8_t reg_data[reg_size]; \
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\
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if (read_register(STATUS_REG, reg_data, \
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QSPI_STATUS_REG_SIZE, qspi) != QSPI_STATUS_OK) { \
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return QSPI_STATUS_ERROR; \
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} \
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if (read_register(CONFIG_REG0, reg_data + QSPI_STATUS_REG_SIZE, \
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QSPI_CONFIG_REG_0_SIZE, qspi) != QSPI_STATUS_OK) { \
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return QSPI_STATUS_ERROR; \
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} \
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\
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reg_data[2] |= CONFIG1_BIT_LH; \
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qspi.cmd.build(QSPI_CMD_WRSR); \
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\
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return qspi_command_transfer(&qspi.handle, qspi.cmd.get(), \
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reg_data, reg_size, NULL, 0)
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#endif // MBED_QSPI_FLASH_MX25R3235F_H

‎TESTS/mbed_hal/qspi/flash_configs/SiliconLabs/EFM32GG11_STK3701/flash_config.h

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/* mbed Microcontroller Library
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* Copyright (c) 2018-2018 ARM Limited
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef MBED_QSPI_FLASH_CONFIG_H
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#define MBED_QSPI_FLASH_CONFIG_H
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#include "../../MX25R3235F_config.h"
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#endif // MBED_QSPI_FLASH_CONFIG_H

‎TESTS/mbed_hal/qspi/flash_configs/flash_configs.h

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#include "NORDIC/NRF52840_DK/flash_config.h"
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#elif defined(TARGET_DISCO_F413ZH)
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#include "STM/DISCO_F413ZH/flash_config.h"
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#elif defined(TARGET_EFM32GG11_STK3701)
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#include "SiliconLabs/EFM32GG11_STK3701/flash_config.h"
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#endif
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#endif // MBED_FLASH_CONFIGS_H

‎targets/TARGET_Silicon_Labs/TARGET_EFM32/PeripheralNames.h

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@@ -136,6 +136,14 @@ typedef enum {
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} UARTName;
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#endif
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#if DEVICE_QSPI
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typedef enum {
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#ifdef QSPI0_BASE
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QSPI_0 = QSPI0_BASE,
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#endif
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} QSPIName;
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#endif
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#ifdef __cplusplus
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}
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#endif

‎targets/TARGET_Silicon_Labs/TARGET_EFM32/PeripheralPins.h

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@@ -68,5 +68,15 @@ extern const PinMap PinMap_CAN_TX[];
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extern const PinMap PinMap_CAN_RX[];
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#endif
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#if DEVICE_QSPI
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/************QSPI**************/
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extern const PinMap PinMap_QSPI_DQ0[];
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extern const PinMap PinMap_QSPI_DQ1[];
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extern const PinMap PinMap_QSPI_DQ2[];
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extern const PinMap PinMap_QSPI_DQ3[];
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extern const PinMap PinMap_QSPI_SCLK[];
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extern const PinMap PinMap_QSPI_CS0[];
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#endif
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#endif
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‎targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG11/PeripheralPins.c

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@@ -579,3 +579,53 @@ MBED_WEAK const PinMap PinMap_CAN_RX[] = {
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#endif
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};
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#endif
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#if DEVICE_QSPI
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MBED_WEAK const PinMap PinMap_QSPI_DQ0[] = {
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#ifdef QSPI0_BASE
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{PD9, QSPI_0, 0},
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{PA2, QSPI_0, 1},
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{PG1, QSPI_0, 2},
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#endif
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};
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MBED_WEAK const PinMap PinMap_QSPI_DQ1[] = {
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#ifdef QSPI0_BASE
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{PD10, QSPI_0, 0},
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{PA3, QSPI_0, 1},
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{PG2, QSPI_0, 2},
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#endif
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};
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MBED_WEAK const PinMap PinMap_QSPI_DQ2[] = {
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#ifdef QSPI0_BASE
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{PD11, QSPI_0, 0},
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{PA4, QSPI_0, 1},
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{PG3, QSPI_0, 2},
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#endif
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};
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MBED_WEAK const PinMap PinMap_QSPI_DQ3[] = {
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#ifdef QSPI0_BASE
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{PD12, QSPI_0, 0},
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{PA5, QSPI_0, 1},
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{PG4, QSPI_0, 2},
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#endif
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};
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MBED_WEAK const PinMap PinMap_QSPI_SCLK[] = {
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#ifdef QSPI0_BASE
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{PF6, QSPI_0, 0},
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{PE14, QSPI_0, 1},
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{PG0, QSPI_0, 2},
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#endif
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};
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MBED_WEAK const PinMap PinMap_QSPI_CS0[] = {
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#ifdef QSPI0_BASE
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{PF7, QSPI_0, 0},
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{PA0, QSPI_0, 1},
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{PG9, QSPI_0, 2},
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#endif
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};
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#endif

‎targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG11/TARGET_EFM32GG11_STK3701/PinNames.h

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@@ -76,7 +76,16 @@ typedef enum {
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/* Board Controller */
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STDIO_UART_TX = USBTX,
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STDIO_UART_RX = USBRX
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STDIO_UART_RX = USBRX,
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/* On-board MX25R3235F */
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QSPI_FLASH1_IO0 = PG1,
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QSPI_FLASH1_IO1 = PG2,
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QSPI_FLASH1_IO2 = PG3,
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QSPI_FLASH1_IO3 = PG4,
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QSPI_FLASH1_SCK = PG0,
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QSPI_FLASH1_CSN = PG9,
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} PinName;
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#ifdef __cplusplus

‎targets/TARGET_Silicon_Labs/TARGET_EFM32/common/objects.h

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};
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#endif
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#if DEVICE_QSPI
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struct qspi_s {
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QSPI_TypeDef *instance;
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PinName io0;
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PinName io1;
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PinName io2;
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PinName io3;
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PinName sclk;
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PinName ssel;
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};
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#endif
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#ifdef __cplusplus
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}
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#endif

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