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Commit 97445fd

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jeromecoutanthallard
authored andcommitted
B_U585I_IOT02A supports OSPI
1 parent 29ca1a4 commit 97445fd

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3 files changed

+52
-13
lines changed

3 files changed

+52
-13
lines changed

targets/TARGET_STM/TARGET_STM32U5/TARGET_STM32U585xI/TARGET_B_U585I_IOT02A/PinNames.h

+21
Original file line numberDiff line numberDiff line change
@@ -402,6 +402,27 @@ typedef enum {
402402
SYS_PWR_WKUP8_ALT0 = PA_7,
403403
SYS_PWR_WKUP8_ALT1 = PB_10,
404404

405+
/**** OSPI FLASH pins ****/
406+
OSPI_FLASH1_IO0 = PF_0,
407+
OSPI_FLASH1_IO1 = PF_1,
408+
OSPI_FLASH1_IO2 = PF_2,
409+
OSPI_FLASH1_IO3 = PF_3,
410+
OSPI_FLASH1_IO4 = PH_9,
411+
OSPI_FLASH1_IO5 = PH_10,
412+
OSPI_FLASH1_IO6 = PH_11,
413+
OSPI_FLASH1_IO7 = PH_12,
414+
OSPI_FLASH1_DQS = PF_12,
415+
OSPI_FLASH1_SCK = PF_4,
416+
OSPI_FLASH1_CSN = PI_5,
417+
418+
/**** QSPI FLASH pins ****/
419+
QSPI_FLASH1_IO0 = OSPI_FLASH1_IO0,
420+
QSPI_FLASH1_IO1 = OSPI_FLASH1_IO1,
421+
QSPI_FLASH1_IO2 = OSPI_FLASH1_IO2,
422+
QSPI_FLASH1_IO3 = OSPI_FLASH1_IO3,
423+
QSPI_FLASH1_SCK = OSPI_FLASH1_SCK,
424+
QSPI_FLASH1_CSN = OSPI_FLASH1_CSN,
425+
405426
// Not connected
406427
NC = (int)0xFFFFFFFF
407428
} PinName;

targets/TARGET_STM/ospi_api.c

+21-13
Original file line numberDiff line numberDiff line change
@@ -55,7 +55,7 @@ static uint32_t get_alt_bytes_size(const uint32_t num_bytes)
5555

5656
ospi_status_t ospi_prepare_command(const ospi_command_t *command, OSPI_RegularCmdTypeDef *st_command)
5757
{
58-
debug_if(ospi_api_c_debug, "ospi_prepare_command In: instruction.value %x dummy_count %x address.bus_width %x address.disabled %x address.value %x address.size %x\n",
58+
debug_if(ospi_api_c_debug, "ospi_prepare_command In: instruction.value %x dummy_count %u address.bus_width %x address.disabled %x address.value %x address.size %x\n",
5959
command->instruction.value, command->dummy_count, command->address.bus_width, command->address.disabled, command->address.value, command->address.size);
6060

6161
st_command->FlashId = HAL_OSPI_FLASH_ID_1;
@@ -255,18 +255,21 @@ static ospi_status_t _ospi_init_direct(ospi_t *obj, const ospi_pinmap_t *pinmap,
255255
obj->handle.Init.DeviceSize = 32;
256256
obj->handle.Init.ChipSelectHighTime = 3;
257257
obj->handle.Init.FreeRunningClock = HAL_OSPI_FREERUNCLK_DISABLE;
258-
#if defined(HAL_OSPI_WRAP_NOT_SUPPORTED) // removed in STM32L4
258+
#if defined(HAL_OSPI_WRAP_NOT_SUPPORTED)
259259
obj->handle.Init.WrapSize = HAL_OSPI_WRAP_NOT_SUPPORTED;
260260
#endif
261261
obj->handle.Init.ClockMode = mode == 0 ? HAL_OSPI_CLOCK_MODE_0 : HAL_OSPI_CLOCK_MODE_3;
262262
obj->handle.Init.DelayHoldQuarterCycle = HAL_OSPI_DHQC_ENABLE;
263263
obj->handle.Init.ChipSelectBoundary = 0;
264-
#if defined(HAL_OSPI_DELAY_BLOCK_USED) // STM32L5
264+
#if defined(HAL_OSPI_DELAY_BLOCK_USED)
265265
obj->handle.Init.DelayBlockBypass = HAL_OSPI_DELAY_BLOCK_USED;
266266
#endif
267-
#if defined(TARGET_STM32L5)
267+
#if defined(TARGET_STM32L5) || defined(TARGET_STM32U5)
268268
obj->handle.Init.Refresh = 0;
269269
#endif
270+
#if defined(OCTOSPI_DCR3_MAXTRAN)
271+
obj->handle.Init.MaxTran = 0;
272+
#endif
270273

271274
// tested all combinations, take first
272275
obj->ospi = pinmap->peripheral;
@@ -371,13 +374,13 @@ ospi_status_t ospi_init(ospi_t *obj, PinName io0, PinName io1, PinName io2, PinN
371374
OSPIName ospiio1name = (OSPIName)pinmap_peripheral(io1, PinMap_OSPI_DATA1);
372375
OSPIName ospiio2name = (OSPIName)pinmap_peripheral(io2, PinMap_OSPI_DATA2);
373376
OSPIName ospiio3name = (OSPIName)pinmap_peripheral(io3, PinMap_OSPI_DATA3);
374-
OSPIName ospiio4name = (OSPIName)pinmap_peripheral(io4, PinMap_OSPI_DATA4);
375-
OSPIName ospiio5name = (OSPIName)pinmap_peripheral(io5, PinMap_OSPI_DATA5);
376-
OSPIName ospiio6name = (OSPIName)pinmap_peripheral(io6, PinMap_OSPI_DATA6);
377-
OSPIName ospiio7name = (OSPIName)pinmap_peripheral(io7, PinMap_OSPI_DATA7);
377+
// OSPIName ospiio4name = (OSPIName)pinmap_peripheral(io4, PinMap_OSPI_DATA4); // IO4 pin not checked
378+
// OSPIName ospiio5name = (OSPIName)pinmap_peripheral(io5, PinMap_OSPI_DATA5); // IO5 pin not checked
379+
// OSPIName ospiio6name = (OSPIName)pinmap_peripheral(io6, PinMap_OSPI_DATA6); // IO6 pin not checked
380+
// OSPIName ospiio7name = (OSPIName)pinmap_peripheral(io7, PinMap_OSPI_DATA7); // IO7 pin not checked
378381
OSPIName ospiclkname = (OSPIName)pinmap_peripheral(sclk, PinMap_OSPI_SCLK);
379382
OSPIName ospisselname = (OSPIName)pinmap_peripheral(ssel, PinMap_OSPI_SSEL);
380-
OSPIName ospidqsname = (OSPIName)pinmap_peripheral(dqs, PinMap_OSPI_DQS);
383+
// OSPIName ospidqsname = (OSPIName)pinmap_peripheral(dqs, PinMap_OSPI_DQS); // DQS pin not checked
381384

382385
OSPIName ospi_data_first = (OSPIName)pinmap_merge(ospiio0name, ospiio1name);
383386
OSPIName ospi_data_second = (OSPIName)pinmap_merge(ospiio2name, ospiio3name);
@@ -451,24 +454,29 @@ ospi_status_t ospi_free(ospi_t *obj)
451454

452455
ospi_status_t ospi_frequency(ospi_t *obj, int hz)
453456
{
454-
tr_debug("ospi_frequency hz %d", hz);
455457
ospi_status_t status = OSPI_STATUS_OK;
456458

457-
/* HCLK drives OSPI. OSPI clock depends on prescaler value:
459+
/* OSPI clock depends on prescaler value:
458460
* 0: Freq = HCLK
459461
* 1: Freq = HCLK/2
460462
* ...
461463
* 255: Freq = HCLK/256 (minimum value)
462464
*/
463465

464-
int div = HAL_RCC_GetHCLKFreq() / hz;
466+
#if defined(TARGET_STM32L5)
467+
uint32_t OSPI_clock_source = HAL_RCC_GetSysClockFreq();
468+
#else
469+
uint32_t OSPI_clock_source = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_OSPI);
470+
#endif
471+
int div = OSPI_clock_source / hz;
465472
if (div > 255) {
466473
div = 255;
467474
} else {
468-
if (div == 1) {
475+
if (OSPI_clock_source % hz != 0) {
469476
div = div + 1;
470477
}
471478
}
479+
tr_debug("ospi_frequency hz %d source %d Prescaler %d", hz, OSPI_clock_source, div);
472480

473481
obj->handle.Init.ClockPrescaler = div;
474482

targets/targets.json

+10
Original file line numberDiff line numberDiff line change
@@ -4631,6 +4631,16 @@
46314631
"ARDUINO_UNO"
46324632
],
46334633
"device_name": "STM32U585AIIx",
4634+
"extra_labels_add": [
4635+
"MX25LM51245G"
4636+
],
4637+
"components_add": [
4638+
"OSPIF"
4639+
],
4640+
"device_has_add": [
4641+
"QSPI",
4642+
"OSPI"
4643+
],
46344644
"components_add": ["EMW3080B"],
46354645
"overrides": {
46364646
"network-default-interface-type": "WIFI"

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