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| 1 | +/* mbed Microcontroller Library |
| 2 | + * Copyright (c) 2018-2018 ARM Limited |
| 3 | + * |
| 4 | + * Licensed under the Apache License, Version 2.0 (the "License"); |
| 5 | + * you may not use this file except in compliance with the License. |
| 6 | + * You may obtain a copy of the License at |
| 7 | + * |
| 8 | + * http://www.apache.org/licenses/LICENSE-2.0 |
| 9 | + * |
| 10 | + * Unless required by applicable law or agreed to in writing, software |
| 11 | + * distributed under the License is distributed on an "AS IS" BASIS, |
| 12 | + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 13 | + * See the License for the specific language governing permissions and |
| 14 | + * limitations under the License. |
| 15 | + */ |
| 16 | +#ifndef MBED_QSPI_FLASH_CONFIG_H |
| 17 | +#define MBED_QSPI_FLASH_CONFIG_H |
| 18 | + |
| 19 | +#include "../../MX25RXX35F_config.h" |
| 20 | + |
| 21 | +/* Fast mode not supported in MX25L12845G */ |
| 22 | +#undef FAST_MODE_ENABLE |
| 23 | +#undef FAST_MODE_DISABLE |
| 24 | + |
| 25 | +#ifdef QSPI_SECTOR_COUNT |
| 26 | +#undef QSPI_SECTOR_COUNT |
| 27 | +#define QSPI_SECTOR_COUNT 4096 // for MX25L12845G |
| 28 | +#endif |
| 29 | + |
| 30 | +/* The values for MX25U3235F are different, specify this here */ |
| 31 | +#undef QSPI_COMMON_MAX_FREQUENCY |
| 32 | +#undef QSPI_WRSR_MAX_TIME |
| 33 | +#undef QSPI_PAGE_PROG_MAX_TIME |
| 34 | +#undef QSPI_ERASE_SECTOR_MAX_TIME |
| 35 | +#undef QSPI_ERASE_BLOCK_32_MAX_TIME |
| 36 | +#undef QSPI_ERASE_BLOCK_64_MAX_TIME |
| 37 | + |
| 38 | +/* Implementation of these macros are slightly different for MX25L12845G */ |
| 39 | +#undef EXTENDED_SPI_ENABLE |
| 40 | +#undef EXTENDED_SPI_DISABLE |
| 41 | + |
| 42 | +/* Max frequency for basic rw operation based on max bus frequency of 24MHz */ |
| 43 | +#define QSPI_COMMON_MAX_FREQUENCY 23000000 |
| 44 | + |
| 45 | +/* WRSR operations max time [us] (datasheet max time + 15%) */ |
| 46 | +#define QSPI_WRSR_MAX_TIME 46000 // 40ms |
| 47 | + |
| 48 | +/* Write operations max time [us] (datasheet max time + 15%) */ |
| 49 | +#define QSPI_PAGE_PROG_MAX_TIME 1000 // 0.75ms |
| 50 | + |
| 51 | +/* erase operations max time [us] (datasheet max time + 15%) */ |
| 52 | +#define QSPI_ERASE_SECTOR_MAX_TIME 460000 // 400 ms |
| 53 | +#define QSPI_ERASE_BLOCK_32_MAX_TIME 1150000 // 1s |
| 54 | +#define QSPI_ERASE_BLOCK_64_MAX_TIME 2300000 // 2s |
| 55 | + |
| 56 | +#define EXTENDED_SPI_ENABLE() \ |
| 57 | + \ |
| 58 | + const int32_t reg_size = QSPI_STATUS_REG_SIZE; \ |
| 59 | + uint8_t reg_data[reg_size] = { 0 }; \ |
| 60 | + \ |
| 61 | + if (read_register(STATUS_REG, reg_data, \ |
| 62 | + QSPI_STATUS_REG_SIZE, qspi) != QSPI_STATUS_OK) { \ |
| 63 | + return QSPI_STATUS_ERROR; \ |
| 64 | + } \ |
| 65 | + if (write_enable(qspi) != QSPI_STATUS_OK) { \ |
| 66 | + return QSPI_STATUS_ERROR; \ |
| 67 | + } \ |
| 68 | + \ |
| 69 | + reg_data[0] = STATUS_BIT_QE; \ |
| 70 | + if (write_register(QSPI_CMD_WRSR, reg_data, \ |
| 71 | + reg_size, qspi) != QSPI_STATUS_OK) { \ |
| 72 | + return QSPI_STATUS_ERROR; \ |
| 73 | + } \ |
| 74 | + WAIT_FOR(WRSR_MAX_TIME, qspi); \ |
| 75 | + \ |
| 76 | + memset(reg_data, 0, QSPI_STATUS_REG_SIZE); \ |
| 77 | + if (read_register(STATUS_REG, reg_data, \ |
| 78 | + QSPI_STATUS_REG_SIZE, qspi) != QSPI_STATUS_OK) { \ |
| 79 | + return QSPI_STATUS_ERROR; \ |
| 80 | + } \ |
| 81 | + \ |
| 82 | + return ((reg_data[0] & STATUS_BIT_QE) != 0 ? \ |
| 83 | + QSPI_STATUS_OK : QSPI_STATUS_ERROR) |
| 84 | + |
| 85 | + |
| 86 | + |
| 87 | +#define EXTENDED_SPI_DISABLE() \ |
| 88 | + \ |
| 89 | + const int32_t reg_size = QSPI_STATUS_REG_SIZE; \ |
| 90 | + uint8_t reg_data[reg_size] = { 0 }; \ |
| 91 | + \ |
| 92 | + if (read_register(STATUS_REG, reg_data, \ |
| 93 | + QSPI_STATUS_REG_SIZE, qspi) != QSPI_STATUS_OK) { \ |
| 94 | + return QSPI_STATUS_ERROR; \ |
| 95 | + } \ |
| 96 | + \ |
| 97 | + if (write_enable(qspi) != QSPI_STATUS_OK) { \ |
| 98 | + return QSPI_STATUS_ERROR; \ |
| 99 | + } \ |
| 100 | + \ |
| 101 | + reg_data[0] &= ~(STATUS_BIT_QE); \ |
| 102 | + \ |
| 103 | + if (write_register(QSPI_CMD_WRSR, reg_data, \ |
| 104 | + reg_size, qspi) != QSPI_STATUS_OK) { \ |
| 105 | + return QSPI_STATUS_ERROR; \ |
| 106 | + } \ |
| 107 | + WAIT_FOR(WRSR_MAX_TIME, qspi); \ |
| 108 | + \ |
| 109 | + reg_data[0] = 0; \ |
| 110 | + if (read_register(STATUS_REG, reg_data, \ |
| 111 | + QSPI_STATUS_REG_SIZE, qspi) != QSPI_STATUS_OK) { \ |
| 112 | + return QSPI_STATUS_ERROR; \ |
| 113 | + } \ |
| 114 | + \ |
| 115 | + return ((reg_data[0] & STATUS_BIT_QE) == 0 ? \ |
| 116 | + QSPI_STATUS_OK : QSPI_STATUS_ERROR) |
| 117 | + |
| 118 | +#endif // MBED_QSPI_FLASH_CONFIG_H |
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