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Merge pull request #12754 from artokin/nanostack_patch_to_mbedos6
Nanostack release for Mbed OS 6
2 parents 68f1ef2 + 152c103 commit c1048c6

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‎components/802.15.4_RF/atmel-rf-driver/atmel-rf-driver/NanostackRfPhyAtmel.h

+46
Original file line numberDiff line numberDiff line change
@@ -24,6 +24,9 @@
2424

2525
#include "NanostackRfPhy.h"
2626

27+
// Uncomment to use testing gpios attached to TX/RX processes
28+
// #define TEST_GPIOS_ENABLED
29+
2730
// Arduino pin defaults for convenience
2831
#if !defined(ATMEL_SPI_MOSI)
2932
#define ATMEL_SPI_MOSI D11
@@ -52,8 +55,24 @@
5255
#if !defined(ATMEL_I2C_SCL)
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#define ATMEL_I2C_SCL D15
5457
#endif
58+
#if !defined(TEST_PIN_TX)
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#define TEST_PIN_TX D6
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#endif
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#if !defined(TEST_PIN_RX)
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#define TEST_PIN_RX D3
63+
#endif
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#if !defined(TEST_PIN_CSMA)
65+
#define TEST_PIN_CSMA D4
66+
#endif
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#if !defined(TEST_PIN_SPARE_1)
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#define TEST_PIN_SPARE_1 D2
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#endif
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#if !defined(TEST_PIN_SPARE_2)
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#define TEST_PIN_SPARE_2 D8
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#endif
5573

5674
class RFBits;
75+
class TestPins;
5776

5877
class NanostackRfPhyAtmel : public NanostackRfPhy {
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public:
@@ -70,6 +89,7 @@ class NanostackRfPhyAtmel : public NanostackRfPhy {
7089
AT24Mac _mac;
7190
uint8_t _mac_addr[8];
7291
RFBits *_rf;
92+
TestPins *_test_pins;
7393
bool _mac_set;
7494

7595
const PinName _spi_mosi;
@@ -81,5 +101,31 @@ class NanostackRfPhyAtmel : public NanostackRfPhy {
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const PinName _spi_irq;
82102
};
83103

104+
#ifdef TEST_GPIOS_ENABLED
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#define TEST_TX_STARTED test_pins->TEST1 = 1;
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#define TEST_TX_DONE test_pins->TEST1 = 0;
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#define TEST_RX_STARTED test_pins->TEST2 = 1;
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#define TEST_RX_DONE test_pins->TEST2 = 0;
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#define TEST_CSMA_STARTED test_pins->TEST3 = 1;
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#define TEST_CSMA_DONE test_pins->TEST3 = 0;
111+
#define TEST_SPARE_1_ON test_pins->TEST4 = 1;
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#define TEST_SPARE_1_OFF test_pins->TEST4 = 0;
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#define TEST_SPARE_2_ON test_pins->TEST5 = 1;
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#define TEST_SPARE_2_OFF test_pins->TEST5 = 0;
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extern void (*fhss_uc_switch)(void);
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extern void (*fhss_bc_switch)(void);
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#else
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#define TEST_TX_STARTED
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#define TEST_TX_DONE
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#define TEST_RX_STARTED
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#define TEST_RX_DONE
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#define TEST_CSMA_STARTED
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#define TEST_CSMA_DONE
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#define TEST_SPARE_1_ON
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#define TEST_SPARE_1_OFF
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#define TEST_SPARE_2_ON
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#define TEST_SPARE_2_OFF
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#endif //TEST_GPIOS_ENABLED
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84130
#endif /* MBED_CONF_NANOSTACK_CONFIGURATION */
85131
#endif /* NANOSTACK_RF_PHY_ATMEL_H_ */

‎components/802.15.4_RF/atmel-rf-driver/source/AT86RF215Reg.h

+262
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,262 @@
1+
/*
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* Copyright (c) 2020 ARM Limited. All rights reserved.
3+
* SPDX-License-Identifier: Apache-2.0
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* Licensed under the Apache License, Version 2.0 (the License); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
11+
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
14+
* limitations under the License.
15+
*/
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17+
#ifndef AT86RF215REG_H_
18+
#define AT86RF215REG_H_
19+
#ifdef __cplusplus
20+
extern "C" {
21+
#endif
22+
23+
24+
/*Register addresses*/
25+
#define RF09_IRQS 0x00
26+
#define RF24_IRQS 0x01
27+
#define BBC0_IRQS 0x02
28+
#define BBC1_IRQS 0x03
29+
#define RF_CFG 0x06
30+
#define RF_IQIFC1 0x0B
31+
#define RF_PN 0x0D
32+
#define RF_VN 0x0E
33+
#define RF_IRQM 0x00
34+
#define RF_STATE 0x02
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#define RF_CMD 0x03
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#define RF_CS 0x04
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#define RF_CCF0L 0x05
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#define RF_CCF0H 0x06
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#define RF_CNL 0x07
40+
#define RF_CNM 0x08
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#define RF_RXBWC 0x09
42+
#define RF_RXDFE 0x0A
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#define RF_AGCC 0x0B
44+
#define RF_AGCS 0x0C
45+
#define RF_RSSI 0x0D
46+
#define RF_EDC 0x0E
47+
#define RF_EDV 0x10
48+
#define RF_TXCUTC 0x12
49+
#define RF_TXDFE 0x13
50+
#define BBC_IRQM 0x00
51+
#define BBC_PC 0x01
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#define BBC_RXFLL 0x04
53+
#define BBC_RXFLH 0x05
54+
#define BBC_TXFLL 0x06
55+
#define BBC_TXFLH 0x07
56+
#define BBC_FBLL 0x08
57+
#define BBC_FBLH 0x09
58+
#define BBC_OQPSKC0 0x10
59+
#define BBC_OQPSKC1 0x11
60+
#define BBC_OQPSKC2 0x12
61+
#define BBC_OQPSKC3 0x13
62+
#define BBC_OQPSKPHRTX 0x14
63+
#define BBC_OQPSKPHRRX 0x15
64+
#define BBC_AFC0 0x20
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#define BBC_AFFTM 0x22
66+
#define BBC_MACEA0 0x25
67+
#define BBC_MACPID0F0 0x2D
68+
#define BBC_MACSHA0F0 0x2F
69+
#define BBC_AMCS 0x40
70+
#define BBC_AMEDT 0x41
71+
#define BBC_AMAACKTL 0x43
72+
#define BBC_AMAACKTH 0x44
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#define BBC_FSKC0 0x60
74+
#define BBC_FSKC1 0x61
75+
#define BBC_FSKC2 0x62
76+
#define BBC_FSKC3 0x63
77+
#define BBC_FSKPLL 0x65
78+
#define BBC_FSKPHRTX 0x6A
79+
#define BBC_FSKPHRRX 0x6B
80+
#define BBC0_FBRXS 0x2000
81+
#define BBC0_FBTXS 0x2800
82+
#define BBC1_FBRXS 0x3000
83+
#define BBC1_FBTXS 0x3800
84+
85+
// RF_AGCC
86+
#define AGCI (1 << 6)
87+
#define AVGS 0x30
88+
#define AVGS_8_SAMPLES (0 << 4)
89+
90+
// RF_AGCS
91+
#define TGT 0xE0
92+
#define TGT_1 (1 << 5)
93+
94+
95+
// RF_RXBWC
96+
#define BW 0x0F
97+
#define RF_BW2000KHZ_IF2000KHZ (11 << 0)
98+
#define RF_BW1600KHZ_IF2000KHZ (10 << 0)
99+
#define RF_BW1250KHZ_IF2000KHZ (9 << 0)
100+
#define RF_BW1000KHZ_IF1000KHZ (8 << 0)
101+
#define RF_BW800KHZ_IF1000KHZ (7 << 0)
102+
#define RF_BW630KHZ_IF1000KHZ (6 << 0)
103+
#define RF_BW500KHZ_IF500KHZ (5 << 0)
104+
#define RF_BW400KHZ_IF500KHZ (4 << 0)
105+
#define RF_BW320KHZ_IF500KHZ (3 << 0)
106+
#define RF_BW250KHZ_IF250KHZ (2 << 0)
107+
#define RF_BW200KHZ_IF250KHZ (1 << 0)
108+
#define RF_BW160KHZ_IF250KHZ (0 << 0)
109+
#define IFS (1 << 4)
110+
111+
// RF_TXCUTC
112+
#define PARAMP 0xC0
113+
#define RF_PARAMP32U (3 << 6)
114+
#define RF_PARAMP16U (2 << 6)
115+
#define RF_PARAMP8U (1 << 6)
116+
#define RF_PARAMP4U (0 << 6)
117+
#define LPFCUT 0x0F
118+
#define RF_FLC80KHZ (0 << 0)
119+
#define RF_FLC100KHZ (1 << 0)
120+
#define RF_FLC125KHZ (2 << 0)
121+
#define RF_FLC160KHZ (3 << 0)
122+
#define RF_FLC200KHZ (4 << 0)
123+
#define RF_FLC250KHZ (5 << 0)
124+
#define RF_FLC315KHZ (6 << 0)
125+
#define RF_FLC400KHZ (7 << 0)
126+
#define RF_FLC500KHZ (8 << 0)
127+
#define RF_FLC625KHZ (9 << 0)
128+
#define RF_FLC800KHZ (10 << 0)
129+
#define RF_FLC1000KHZ (11 << 0)
130+
131+
// RF_TXDFE, RF_RXDFE
132+
#define RCUT 0xE0
133+
#define RCUT_4 (4 << 5)
134+
#define RCUT_2 (2 << 5)
135+
#define RCUT_1 (1 << 5)
136+
#define RCUT_0 (0 << 5)
137+
#define SR 0x0F
138+
#define SR_10 (10 << 0)
139+
#define SR_8 (8 << 0)
140+
#define SR_6 (6 << 0)
141+
#define SR_5 (5 << 0)
142+
#define SR_4 (4 << 0)
143+
#define SR_3 (3 << 0)
144+
#define SR_2 (2 << 0)
145+
#define SR_1 (1 << 0)
146+
147+
// BBC_FSKC0
148+
#define BT 0xC0
149+
#define BT_20 (3 << 6)
150+
#define BT_10 (1 << 6)
151+
#define MIDXS 0x30
152+
#define MIDXS_0 (0 << 4)
153+
#define MIDX 0x0E
154+
#define MIDX_10 (3 << 1)
155+
#define MIDX_075 (2 << 1)
156+
#define MIDX_05 (1 << 1)
157+
#define MIDX_0375 (0 << 1)
158+
159+
// BBC_FSKC1
160+
#define SRATE 0x0F
161+
#define SRATE_400KHZ (5 << 0)
162+
#define SRATE_300KHZ (4 << 0)
163+
#define SRATE_200KHZ (3 << 0)
164+
#define SRATE_150KHZ (2 << 0)
165+
#define SRATE_100KHZ (1 << 0)
166+
#define SRATE_50KHZ (0 << 0)
167+
168+
// BBC_FSKC2
169+
#define RXO 0x60
170+
#define RXO_DIS (0 << 5)
171+
#define FECIE (1 << 0)
172+
173+
// BBC_FSKC3
174+
#define SFDT 0xF0
175+
#define PDT 0x0F
176+
#define PDT_6 (6 << 0)
177+
178+
// BBC_AFFTM
179+
#define TYPE_2 (1 << 2)
180+
181+
// BBC_AFC0
182+
#define PM (1 << 4)
183+
#define AFEN3 (1 << 3)
184+
#define AFEN2 (1 << 2)
185+
#define AFEN1 (1 << 1)
186+
#define AFEN0 (1 << 0)
187+
188+
// BBC_OQPSKPHRTX
189+
#define LEG (1 << 0)
190+
191+
// BBC_OQPSKC0
192+
#define FCHIP 0x03
193+
#define BB_FCHIP100 (0 << 0)
194+
#define BB_FCHIP200 (1 << 0)
195+
#define BB_FCHIP1000 (2 << 0)
196+
#define BB_FCHIP2000 (3 << 0)
197+
198+
// BBC_OQPSKC2
199+
#define FCSTLEG 0x04
200+
#define RXM 0x03
201+
#define FCS_16 (1 << 2)
202+
#define RXM_2 (2 << 0)
203+
204+
// BBC_IRQS, BBC_IRQM
205+
#define FBLI (1 << 7)
206+
#define AGCR (1 << 6)
207+
#define AGCH (1 << 5)
208+
#define TXFE (1 << 4)
209+
#define RXEM (1 << 3)
210+
#define RXAM (1 << 2)
211+
#define RXFE (1 << 1)
212+
#define RXFS (1 << 0)
213+
214+
//BBC_PC
215+
#define BBEN (1 << 2)
216+
#define PT 0x03
217+
#define BB_PHYOFF (0 << 0)
218+
#define BB_MRFSK (1 << 0)
219+
#define BB_MROFDM (2 << 0)
220+
#define BB_MROQPSK (3 << 0)
221+
#define FCSOK (1 << 5)
222+
#define TXAFCS (1 << 4)
223+
#define FCST (1 << 3)
224+
#define FCSFE (1 << 6)
225+
226+
//BBC_AMCS
227+
#define AACKFT (1 << 7)
228+
#define AACK (1 << 3)
229+
#define CCAED (1 << 2)
230+
231+
// RF_IQIFC1
232+
#define CHPM 0x70
233+
#define RF_MODE_BBRF (0 << 4)
234+
#define RF_MODE_RF (1 << 4)
235+
#define RF_MODE_BBRF09 (4 << 4)
236+
#define RF_MODE_BBRF24 (5 << 4)
237+
238+
/*RF_CFG bits*/
239+
#define IRQMM 0x08
240+
#define IRQP 0x04
241+
242+
/*RFn_IRQM bits*/
243+
#define TRXRDY (1 << 1)
244+
#define EDC (1 << 2)
245+
246+
/*RFn_EDC bits*/
247+
#define EDM 0x03
248+
#define RF_EDAUTO (0 << 0)
249+
#define RF_EDSINGLE (1 << 0)
250+
#define RF_EDCONT (2 << 0)
251+
#define RF_EDOFF (3 << 0)
252+
253+
/*Masks*/
254+
#define CNH 0x01
255+
#define EDM 0x03
256+
#define CHPM 0x70
257+
258+
#ifdef __cplusplus
259+
}
260+
#endif
261+
262+
#endif /* AT86RF215REG_H_ */

‎components/802.15.4_RF/atmel-rf-driver/source/AT86RFReg.h

+1
Original file line numberDiff line numberDiff line change
@@ -47,6 +47,7 @@ extern "C" {
4747
#define PART_AT86RF231 0x03
4848
#define PART_AT86RF212 0x07
4949
#define PART_AT86RF233 0x0B
50+
#define PART_AT86RF215 0x34
5051
#define VERSION_AT86RF212 0x01
5152
#define VERSION_AT86RF212B 0x03
5253

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