From b53d40b269219709f1ce5889cd845be05bdd87e3 Mon Sep 17 00:00:00 2001 From: Gavin Liu Date: Thu, 2 Apr 2020 21:45:41 +0800 Subject: [PATCH 1/5] targets:MIMXRT1050: Add QSPI Flash boot support NXP MIMXRT1050 EVK can support Hyper Flash or QSPI Flash with small hardware reworks. Modify the XIP file to support boot from the two kinds of Flash device. The Hyper Flash should be the default device and defined in tartgets.json with the macro "HYPERFLASH_BOOT". To select the QSPI Flash, just remove the macro with the below line in any overriding json file. "target.macros_remove" : ["HYPERFLASH_BOOT"] Signed-off-by: Gavin Liu --- .../xip/evkbimxrt1050_flexspi_nor_config.c | 71 +++++++++++++------ targets/targets.json | 1 + 2 files changed, 49 insertions(+), 23 deletions(-) diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/xip/evkbimxrt1050_flexspi_nor_config.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/xip/evkbimxrt1050_flexspi_nor_config.c index 1193ad7f377..104479ff825 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/xip/evkbimxrt1050_flexspi_nor_config.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/xip/evkbimxrt1050_flexspi_nor_config.c @@ -22,34 +22,59 @@ __attribute__((section(".boot_hdr.conf"), used)) #pragma location = ".boot_hdr.conf" #endif +#ifdef HYPERFLASH_BOOT const flexspi_nor_config_t hyperflash_config = { - .memConfig = - { - .tag = FLEXSPI_CFG_BLK_TAG, - .version = FLEXSPI_CFG_BLK_VERSION, - .readSampleClkSrc = kFlexSPIReadSampleClk_ExternalInputFromDqsPad, - .csHoldTime = 3u, - .csSetupTime = 3u, - .columnAddressWidth = 3u, - // Enable DDR mode, Wordaddassable, Safe configuration, Differential clock - .controllerMiscOption = - (1u << kFlexSpiMiscOffset_DdrModeEnable) | (1u << kFlexSpiMiscOffset_WordAddressableEnable) | - (1u << kFlexSpiMiscOffset_SafeConfigFreqEnable) | (1u << kFlexSpiMiscOffset_DiffClkEnable), - .sflashPadType = kSerialFlash_8Pads, - .serialClkFreq = kFlexSpiSerialClk_133MHz, - .sflashA1Size = 64u * 1024u * 1024u, - .dataValidTime = {16u, 16u}, - .lookupTable = - { - // Read LUTs - FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0xA0, RADDR_DDR, FLEXSPI_8PAD, 0x18), - FLEXSPI_LUT_SEQ(CADDR_DDR, FLEXSPI_8PAD, 0x10, DUMMY_DDR, FLEXSPI_8PAD, 0x06), - FLEXSPI_LUT_SEQ(READ_DDR, FLEXSPI_8PAD, 0x04, STOP, FLEXSPI_1PAD, 0x0), - }, + .memConfig = { + .tag = FLEXSPI_CFG_BLK_TAG, + .version = FLEXSPI_CFG_BLK_VERSION, + .readSampleClkSrc = kFlexSPIReadSampleClk_ExternalInputFromDqsPad, + .csHoldTime = 3u, + .csSetupTime = 3u, + .columnAddressWidth = 3u, + // Enable DDR mode, Wordaddassable, Safe configuration, Differential clock + .controllerMiscOption = + (1u << kFlexSpiMiscOffset_DdrModeEnable) | (1u << kFlexSpiMiscOffset_WordAddressableEnable) | + (1u << kFlexSpiMiscOffset_SafeConfigFreqEnable) | (1u << kFlexSpiMiscOffset_DiffClkEnable), + .sflashPadType = kSerialFlash_8Pads, + .serialClkFreq = kFlexSpiSerialClk_133MHz, + .sflashA1Size = 64u * 1024u * 1024u, + .dataValidTime = {16u, 16u}, + .lookupTable = { + // Read LUTs + FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0xA0, RADDR_DDR, FLEXSPI_8PAD, 0x18), + FLEXSPI_LUT_SEQ(CADDR_DDR, FLEXSPI_8PAD, 0x10, DUMMY_DDR, FLEXSPI_8PAD, 0x06), + FLEXSPI_LUT_SEQ(READ_DDR, FLEXSPI_8PAD, 0x04, STOP, FLEXSPI_1PAD, 0x0), }, + }, .pageSize = 512u, .sectorSize = 256u * 1024u, .blockSize = 256u * 1024u, .isUniformBlockSize = true, }; +#else +const flexspi_nor_config_t qspiflash_config = { + .memConfig = { + .tag = FLEXSPI_CFG_BLK_TAG, + .version = FLEXSPI_CFG_BLK_VERSION, + .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad, + .csHoldTime = 3u, + .csSetupTime = 3u, + .columnAddressWidth = 0u, + .configCmdEnable = 0u, + .controllerMiscOption = 0u, + .deviceType = kFlexSpiDeviceType_SerialNOR, + .sflashPadType = kSerialFlash_4Pads, + .serialClkFreq = kFlexSpiSerialClk_133MHz, + .lutCustomSeqEnable = 0u, + .sflashA1Size = 0x00800000u, /* 8MB/64Mbit */ + .lookupTable = { + // Fast read sequence + [0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18), + [1] = FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x02), + [2] = FLEXSPI_LUT_SEQ(STOP, 0, 0, STOP, 0, 0), + [3] = FLEXSPI_LUT_SEQ(STOP, 0, 0, STOP, 0, 0), + }, + }, +}; +#endif #endif /* XIP_BOOT_HEADER_ENABLE */ diff --git a/targets/targets.json b/targets/targets.json index f51b33039d1..8343ef6193d 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -2890,6 +2890,7 @@ "XIP_BOOT_HEADER_ENABLE=1", "XIP_EXTERNAL_FLASH=1", "XIP_BOOT_HEADER_DCD_ENABLE=1", + "HYPERFLASH_BOOT", "FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE=1", "SKIP_SYSCLK_INIT", "FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE", From f8a8401a13218aed54cfc8d24a980ddb3810beda Mon Sep 17 00:00:00 2001 From: Gavin Liu Date: Thu, 2 Apr 2020 15:52:12 +0800 Subject: [PATCH 2/5] targets:TARGET_IMX: Fix the flash init risk The flash access may fail when implementing flash initialization. So there is risk for interrupt handler which linked in flash space. Add the critical section to avoid the risk. Signed-off-by: Gavin Liu --- .../TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_IMX/flash_api.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_IMX/flash_api.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_IMX/flash_api.c index cc0fa885f30..69e50b29b14 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_IMX/flash_api.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_IMX/flash_api.c @@ -278,7 +278,9 @@ void flexspi_nor_flash_read_data_ram(uint32_t addr, uint32_t *buffer, uint32_t s int32_t flash_init(flash_t *obj) { + core_util_critical_section_enter(); flexspi_update_lut_ram(); + core_util_critical_section_exit(); return 0; } From 2be0790c4a7b59c9a4bfad42039340f6c57cf90c Mon Sep 17 00:00:00 2001 From: Gavin Liu Date: Thu, 2 Apr 2020 16:58:44 +0800 Subject: [PATCH 3/5] targets:TARGET_IMX: Fix the memset issue for FLASHIAP The memset function from c library will be linked in flash space, it's risk for FLASHIAP. So I wrote flexspi_memset to replace the memset for IMX FLASHIAP, and put the function into targets/.../TARGET_IMX/flash_api.c file. All IMX Soc platforms can declare it as extern and use in their Soc flexspi driver files. Signed-off-by: Gavin Liu --- .../TARGET_IMX/flash_api.c | 55 +++++++++++++++++-- .../TARGET_MIMXRT1050/drivers/fsl_flexspi.c | 4 +- .../TARGET_MIMXRT1050/drivers/fsl_flexspi.h | 8 +++ 3 files changed, 60 insertions(+), 7 deletions(-) diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_IMX/flash_api.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_IMX/flash_api.c index 69e50b29b14..1241af4959b 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_IMX/flash_api.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_IMX/flash_api.c @@ -37,12 +37,57 @@ AT_QUICKACCESS_SECTION_CODE(status_t flexspi_nor_flash_page_program_ram(uint32_t AT_QUICKACCESS_SECTION_CODE(void flexspi_nor_flash_read_data_ram(uint32_t addr, uint32_t *buffer, uint32_t size)); +AT_QUICKACCESS_SECTION_CODE(void *flexspi_memset(void *buf, int c, size_t n)); +/** + * @brief Set bytes in memory. If put this code in SRAM, Make sure this code + * does not call functions in Flash. + * + * @return pointer to start of buffer + */ +void *flexspi_memset(void *buf, int c, size_t n) +{ + /* do byte-sized initialization until word-aligned or finished */ + unsigned char *d_byte = (unsigned char *)buf; + unsigned char c_byte = (unsigned char)c; + + while (((unsigned int)d_byte) & 0x3) { + if (n == 0) { + return buf; + } + *(d_byte++) = c_byte; + n--; + }; + + /* do word-sized initialization as long as possible */ + + unsigned int *d_word = (unsigned int *)d_byte; + unsigned int c_word = (unsigned int)(unsigned char)c; + + c_word |= c_word << 8; + c_word |= c_word << 16; + + while (n >= sizeof(unsigned int)) { + *(d_word++) = c_word; + n -= sizeof(unsigned int); + } + + /* do byte-sized initialization until finished */ + + d_byte = (unsigned char *)d_word; + + while (n > 0) { + *(d_byte++) = c_byte; + n--; + } + + return buf; +} void flexspi_update_lut_ram(void) { flexspi_config_t config; - memset(&config, 0, sizeof(config)); + flexspi_memset(&config, 0, sizeof(config)); /*Get FLEXSPI default settings and configure the flexspi. */ FLEXSPI_GetDefaultConfig(&config); @@ -77,7 +122,7 @@ status_t flexspi_nor_write_enable_ram(uint32_t baseAddr) flexspi_transfer_t flashXfer; status_t status = kStatus_Success; - memset(&flashXfer, 0, sizeof(flashXfer)); + flexspi_memset(&flashXfer, 0, sizeof(flashXfer)); /* Write enable */ flashXfer.deviceAddress = baseAddr; @@ -99,7 +144,7 @@ status_t flexspi_nor_wait_bus_busy_ram(void) status_t status = kStatus_Success; flexspi_transfer_t flashXfer; - memset(&flashXfer, 0, sizeof(flashXfer)); + flexspi_memset(&flashXfer, 0, sizeof(flashXfer)); flashXfer.deviceAddress = 0; flashXfer.port = kFLEXSPI_PortA1; @@ -138,7 +183,7 @@ status_t flexspi_nor_flash_erase_sector_ram(uint32_t address) status_t status = kStatus_Success; flexspi_transfer_t flashXfer; - memset(&flashXfer, 0, sizeof(flashXfer)); + flexspi_memset(&flashXfer, 0, sizeof(flashXfer)); /* Write enable */ status = flexspi_nor_write_enable_ram(address); @@ -229,7 +274,7 @@ status_t flexspi_nor_flash_page_program_ram(uint32_t address, const uint32_t *sr flexspi_transfer_t flashXfer; uint32_t offset = 0; - memset(&flashXfer, 0, sizeof(flashXfer)); + flexspi_memset(&flashXfer, 0, sizeof(flashXfer)); flexspi_lower_clock_ram(); diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexspi.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexspi.c index c925526dc48..ad2f3fd683b 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexspi.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexspi.c @@ -337,7 +337,7 @@ void FLEXSPI_Init(FLEXSPI_Type *base, const flexspi_config_t *config) void FLEXSPI_GetDefaultConfig(flexspi_config_t *config) { /* Initializes the configure structure to zero. */ - (void)memset(config, 0, sizeof(*config)); + (void)flexspi_memset(config, 0, sizeof(*config)); config->rxSampleClock = kFLEXSPI_ReadSampleClkLoopbackInternally; config->enableSckFreeRunning = false; @@ -359,7 +359,7 @@ void FLEXSPI_GetDefaultConfig(flexspi_config_t *config) config->ahbConfig.ahbGrantTimeoutCycle = 0xFFU; config->ahbConfig.ahbBusTimeoutCycle = 0xFFFFU; config->ahbConfig.resumeWaitCycle = 0x20U; - (void)memset(config->ahbConfig.buffer, 0, sizeof(config->ahbConfig.buffer)); + (void)flexspi_memset(config->ahbConfig.buffer, 0, sizeof(config->ahbConfig.buffer)); for (uint8_t i = 0; i < (uint32_t)FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNT; i++) { config->ahbConfig.buffer[i].enablePrefetch = true; /* Default enable AHB prefetch. */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexspi.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexspi.h index 2b1e7ac2fef..eb05a4b9723 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexspi.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexspi.h @@ -333,6 +333,14 @@ struct _flexspi_handle extern "C" { #endif /*_cplusplus. */ +/** + * @brief Set bytes in memory. If put this code in SRAM, Make sure this code + * does not call functions in Flash. + * + * @return pointer to start of buffer + */ +extern void *flexspi_memset(void *buf, int c, size_t n); + /*! * @name Initialization and deinitialization * @{ From 1d1e69a4a2a9c5ed866059f7c4fd8442d5dbb744 Mon Sep 17 00:00:00 2001 From: Gavin Liu Date: Fri, 3 Apr 2020 17:46:55 +0800 Subject: [PATCH 4/5] targets:MIMXRT1050: Add QSPI Flash FLASHIAP support Update the flash driver to support both Hyper Flash and QSPI Flash. In addition, the static function cannot be linked to SRAM even defined by AT_QUICKACCESS_SECTION_CODE macro. So remove all "static" modifier for the FLASHIAP functions. Signed-off-by: Gavin Liu --- .../TARGET_IMX/flash_api.c | 231 +++++++++++++++++- .../TARGET_MIMXRT1050/TARGET_EVK/device.h | 18 +- .../TARGET_EVK/flash_defines.h | 196 +++++++++++---- .../TARGET_MIMXRT1050/drivers/fsl_flexspi.c | 4 +- 4 files changed, 394 insertions(+), 55 deletions(-) diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_IMX/flash_api.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_IMX/flash_api.c index 1241af4959b..3cc763d6226 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_IMX/flash_api.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_IMX/flash_api.c @@ -29,8 +29,6 @@ AT_QUICKACCESS_SECTION_CODE(void flexspi_update_lut_ram(void)); AT_QUICKACCESS_SECTION_CODE(status_t flexspi_nor_write_enable_ram(uint32_t baseAddr)); AT_QUICKACCESS_SECTION_CODE(status_t flexspi_nor_wait_bus_busy_ram(void)); AT_QUICKACCESS_SECTION_CODE(status_t flexspi_nor_flash_erase_sector_ram(uint32_t address)); -AT_QUICKACCESS_SECTION_CODE(static void flexspi_lower_clock_ram(void)); -AT_QUICKACCESS_SECTION_CODE(static void flexspi_clock_update_ram(void)); AT_QUICKACCESS_SECTION_CODE(status_t flexspi_nor_flash_page_program_ram(uint32_t address, const uint32_t *src, uint32_t size)); @@ -83,6 +81,9 @@ void *flexspi_memset(void *buf, int c, size_t n) return buf; } +#ifdef HYPERFLASH_BOOT +AT_QUICKACCESS_SECTION_CODE(void flexspi_lower_clock_ram(void)); +AT_QUICKACCESS_SECTION_CODE(void flexspi_clock_update_ram(void)); void flexspi_update_lut_ram(void) { flexspi_config_t config; @@ -210,7 +211,7 @@ status_t flexspi_nor_flash_erase_sector_ram(uint32_t address) return status; } -static void flexspi_lower_clock_ram(void) +void flexspi_lower_clock_ram(void) { unsigned int reg = 0; @@ -242,7 +243,7 @@ static void flexspi_lower_clock_ram(void) } } -static void flexspi_clock_update_ram(void) +void flexspi_clock_update_ram(void) { /* Program finished, speed the clock to 133M. */ /* Wait for bus idle before change flash configuration. */ @@ -316,6 +317,224 @@ status_t flexspi_nor_flash_page_program_ram(uint32_t address, const uint32_t *sr return status; } +#else +AT_QUICKACCESS_SECTION_CODE(status_t flexspi_nor_enable_quad_mode_ram(void)); +status_t flexspi_nor_enable_quad_mode_ram(void) +{ + flexspi_transfer_t flashXfer; + uint32_t writeValue = FLASH_QUAD_ENABLE; + status_t status = kStatus_Success; + + flexspi_memset(&flashXfer, 0, sizeof(flashXfer)); + /* Write enable */ + status = flexspi_nor_write_enable_ram(0); + + if (status != kStatus_Success) { + return status; + } + + /* Enable quad mode. */ + flashXfer.deviceAddress = 0; + flashXfer.port = kFLEXSPI_PortA1; + flashXfer.cmdType = kFLEXSPI_Write; + flashXfer.SeqNumber = 1; + flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_WRITESTATUSREG; + flashXfer.data = &writeValue; + flashXfer.dataSize = 1; + + status = FLEXSPI_TransferBlocking(FLEXSPI, &flashXfer); + if (status != kStatus_Success) { + return status; + } + + status = flexspi_nor_wait_bus_busy_ram(); + + /* Do software reset. */ + FLEXSPI_SoftwareReset(FLEXSPI); + + return status; +} + +void flexspi_update_lut_ram(void) +{ + flexspi_config_t config; + + flexspi_memset(&config, 0, sizeof(config)); + + /*Get FLEXSPI default settings and configure the flexspi. */ + FLEXSPI_GetDefaultConfig(&config); + + /*Set AHB buffer size for reading data through AHB bus. */ + config.ahbConfig.enableAHBPrefetch = true; + config.ahbConfig.enableAHBBufferable = true; + config.ahbConfig.enableReadAddressOpt = true; + config.ahbConfig.enableAHBCachable = true; + config.rxSampleClock = kFLEXSPI_ReadSampleClkLoopbackFromDqsPad; + FLEXSPI_Init(FLEXSPI, &config); + + /* Configure flash settings according to serial flash feature. */ + FLEXSPI_SetFlashConfig(FLEXSPI, &deviceconfig, kFLEXSPI_PortA1); + + /* Update LUT table. */ + FLEXSPI_UpdateLUT(FLEXSPI, 0, customLUT, CUSTOM_LUT_LENGTH); + + /* Do software reset. */ + FLEXSPI_SoftwareReset(FLEXSPI); + /* Wait for bus idle. */ + while (!FLEXSPI_GetBusIdleStatus(FLEXSPI)) { + } + flexspi_nor_enable_quad_mode_ram(); +} + +status_t flexspi_nor_write_enable_ram(uint32_t baseAddr) +{ + flexspi_transfer_t flashXfer; + status_t status = kStatus_Success; + + flexspi_memset(&flashXfer, 0, sizeof(flashXfer)); + /* Write enable */ + flashXfer.deviceAddress = baseAddr; + flashXfer.port = kFLEXSPI_PortA1; + flashXfer.cmdType = kFLEXSPI_Command; + flashXfer.SeqNumber = 1; + flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_WRITEENABLE; + + status = FLEXSPI_TransferBlocking(FLEXSPI, &flashXfer); + + return status; +} + +status_t flexspi_nor_wait_bus_busy_ram(void) +{ + /* Wait status ready. */ + bool isBusy; + uint32_t readValue; + status_t status = kStatus_Success; + flexspi_transfer_t flashXfer; + + flexspi_memset(&flashXfer, 0, sizeof(flashXfer)); + + flashXfer.deviceAddress = 0; + flashXfer.port = kFLEXSPI_PortA1; + flashXfer.cmdType = kFLEXSPI_Read; + flashXfer.SeqNumber = 1; + flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_READSTATUSREG; + flashXfer.data = &readValue; + flashXfer.dataSize = 1; + + do { + status = FLEXSPI_TransferBlocking(FLEXSPI, &flashXfer); + + if (status != kStatus_Success) { + return status; + } + if (FLASH_BUSY_STATUS_POL) { + if (readValue & (1U << FLASH_BUSY_STATUS_OFFSET)) { + isBusy = true; + } else { + isBusy = false; + } + } else { + if (readValue & (1U << FLASH_BUSY_STATUS_OFFSET)) { + isBusy = false; + } else { + isBusy = true; + } + } + + } while (isBusy); + + return status; +} + + +status_t flexspi_nor_flash_erase_sector_ram(uint32_t address) +{ + flexspi_transfer_t flashXfer; + status_t status = kStatus_Success; + + flexspi_memset(&flashXfer, 0, sizeof(flashXfer)); + + /* Write enable */ + flashXfer.deviceAddress = address; + flashXfer.port = kFLEXSPI_PortA1; + flashXfer.cmdType = kFLEXSPI_Command; + flashXfer.SeqNumber = 1; + flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_WRITEENABLE; + + status = FLEXSPI_TransferBlocking(FLEXSPI, &flashXfer); + + if (status != kStatus_Success) { + return status; + } + + flashXfer.deviceAddress = address; + flashXfer.port = kFLEXSPI_PortA1; + flashXfer.cmdType = kFLEXSPI_Command; + flashXfer.SeqNumber = 1; + flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_ERASESECTOR; + status = FLEXSPI_TransferBlocking(FLEXSPI, &flashXfer); + + if (status != kStatus_Success) { + return status; + } + + status = flexspi_nor_wait_bus_busy_ram(); + + /* Do software reset. */ + FLEXSPI_SoftwareReset(FLEXSPI); + + return status; +} + +status_t flexspi_nor_flash_page_program_ram(uint32_t address, const uint32_t *src, uint32_t size) +{ + flexspi_transfer_t flashXfer; + status_t status = kStatus_Success; + uint32_t offset = 0; + + flexspi_memset(&flashXfer, 0, sizeof(flashXfer)); + + while (size > 0) { + /* Write enable */ + status = flexspi_nor_write_enable_ram(address + offset); + + if (status != kStatus_Success) { + return status; + } + + /* Prepare page program command */ + flashXfer.deviceAddress = address + offset; + flashXfer.port = kFLEXSPI_PortA1; + flashXfer.cmdType = kFLEXSPI_Write; + flashXfer.SeqNumber = 1; + flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_QUAD; + flashXfer.data = (uint32_t *)(src + offset); + flashXfer.dataSize = BOARD_FLASH_PAGE_SIZE; + + status = FLEXSPI_TransferBlocking(FLEXSPI, &flashXfer); + + if (status != kStatus_Success) { + return status; + } + + status = flexspi_nor_wait_bus_busy_ram(); + + if (status != kStatus_Success) { + return status; + } + + size -= BOARD_FLASH_PAGE_SIZE; + offset += BOARD_FLASH_PAGE_SIZE; + } + + /* Do software reset. */ + FLEXSPI_SoftwareReset(FLEXSPI); + + return status; +} + +#endif void flexspi_nor_flash_read_data_ram(uint32_t addr, uint32_t *buffer, uint32_t size) { memcpy(buffer, (void *)addr, size); @@ -402,12 +621,12 @@ uint32_t flash_get_page_size(const flash_t *obj) uint32_t flash_get_start_address(const flash_t *obj) { - return BOARD_FLASH_START_ADDR; + return BOARD_FLASHIAP_START_ADDR; } uint32_t flash_get_size(const flash_t *obj) { - return BOARD_FLASH_SIZE; + return BOARD_FLASHIAP_SIZE; } uint8_t flash_get_erase_value(const flash_t *obj) diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/device.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/device.h index c9a7eb2b483..d2a7b696b08 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/device.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/device.h @@ -19,12 +19,24 @@ #define MBED_DEVICE_H #define DEVICE_ID_LENGTH 24 -/* 4MB reserved for mbed-os */ -#define BOARD_FLASH_SIZE (0x3C00000U) -#define BOARD_FLASH_START_ADDR (0x60400000U) +#ifdef HYPERFLASH_BOOT +/* 64MB HyperFlash, 4MB reserved for mbed-os */ +#define BOARD_FLASH_SIZE (0x4000000U) +#define BOARD_FLASH_START_ADDR (0x60000000U) +#define BOARD_FLASHIAP_SIZE (0x3C00000U) +#define BOARD_FLASHIAP_START_ADDR (0x60400000U) #define BOARD_FLASH_PAGE_SIZE (512) #define BOARD_FLASH_SECTOR_SIZE (262144) +#else +/* 8MB QSPI Flash, 64KB reserved for mbed_bootloader */ +#define BOARD_FLASH_SIZE (0x800000U) +#define BOARD_FLASH_START_ADDR (0x60000000U) +#define BOARD_FLASHIAP_SIZE (0x7F0000U) +#define BOARD_FLASHIAP_START_ADDR (0x60010000U) +#define BOARD_FLASH_PAGE_SIZE (256) +#define BOARD_FLASH_SECTOR_SIZE (4096) +#endif #define BOARD_ENET_PHY_ADDR (2) diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/flash_defines.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/flash_defines.h index b3e6ec30bb1..6f4db492117 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/flash_defines.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/flash_defines.h @@ -19,6 +19,7 @@ #include "fsl_common.h" +#ifdef HYPERFLASH_BOOT /* 64MB Hyperflash */ #define HYPERFLASH_CMD_LUT_SEQ_IDX_READDATA 0 #define HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEDATA 1 #define HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS 2 @@ -31,137 +32,137 @@ static uint32_t customLUT[CUSTOM_LUT_LENGTH] = { /* Read Data */ [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READDATA] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xA0, kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x18), + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xA0, kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x18), [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READDATA + 1] = FLEXSPI_LUT_SEQ( kFLEXSPI_Command_CADDR_DDR, kFLEXSPI_8PAD, 0x10, kFLEXSPI_Command_READ_DDR, kFLEXSPI_8PAD, 0x04), /* Write Data */ [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEDATA] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x20, kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x18), + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x20, kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x18), [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEDATA + 1] = FLEXSPI_LUT_SEQ( kFLEXSPI_Command_CADDR_DDR, kFLEXSPI_8PAD, 0x10, kFLEXSPI_Command_WRITE_DDR, kFLEXSPI_8PAD, 0x02), /* Read Status */ [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00), + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00), [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS + 1] = FLEXSPI_LUT_SEQ( kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA), // ADDR 0x555 [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS + 2] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05), + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05), [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS + 3] = FLEXSPI_LUT_SEQ( kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x70), // DATA 0x70 [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS + 4] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xA0, kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x18), + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xA0, kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x18), [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS + 5] = FLEXSPI_LUT_SEQ( kFLEXSPI_Command_CADDR_DDR, kFLEXSPI_8PAD, 0x10, kFLEXSPI_Command_DUMMY_RWDS_DDR, kFLEXSPI_8PAD, 0x0B), [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS + 6] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_READ_DDR, kFLEXSPI_8PAD, 0x04, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x0), + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_READ_DDR, kFLEXSPI_8PAD, 0x04, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x0), /* Write Enable */ [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00), + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00), [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE + 1] = FLEXSPI_LUT_SEQ( kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA), // ADDR 0x555 [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE + 2] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05), + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05), [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE + 3] = FLEXSPI_LUT_SEQ( kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA), // DATA 0xAA [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE + 4] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00), + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00), [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE + 5] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x55), + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x55), [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE + 6] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x02), + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x02), [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE + 7] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x55), + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x55), /* Erase Sector */ [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00), + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00), [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 1] = FLEXSPI_LUT_SEQ( kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA), // ADDR 0x555 [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 2] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05), + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05), [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 3] = FLEXSPI_LUT_SEQ( kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x80), // DATA 0x80 [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 4] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00), + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00), [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 5] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA), + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA), [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 6] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05), + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05), [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 7] = FLEXSPI_LUT_SEQ( kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA), // ADDR 0x555 [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 8] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00), + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00), [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 9] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x55), + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x55), [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 10] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x02), + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x02), [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 11] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x55), + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x55), [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 12] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x18), + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x18), [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 13] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_CADDR_DDR, kFLEXSPI_8PAD, 0x10, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00), + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_CADDR_DDR, kFLEXSPI_8PAD, 0x10, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00), [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 14] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x30, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x00), + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x30, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x00), /* program page */ [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00), + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00), [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM + 1] = FLEXSPI_LUT_SEQ( kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA), // ADDR 0x555 [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM + 2] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05), + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05), [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM + 3] = FLEXSPI_LUT_SEQ( kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xA0), // DATA 0xA0 [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM + 4] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x18), + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x18), [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM + 5] = FLEXSPI_LUT_SEQ( kFLEXSPI_Command_CADDR_DDR, kFLEXSPI_8PAD, 0x10, kFLEXSPI_Command_WRITE_DDR, kFLEXSPI_8PAD, 0x80), /* Erase chip */ [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00), + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00), [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 1] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA), + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA), [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 2] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05), + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05), [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 3] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x80), + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x80), // 1 [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 4] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00), + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00), [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 5] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA), + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA), [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 6] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05), + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05), [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 7] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA), + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA), // 2 [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 8] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00), + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00), [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 9] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x55), + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x55), [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 10] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x02), + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x02), [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 11] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x55), + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x55), // 3 [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 12] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00), + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00), [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 13] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA), + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA), [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 14] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05), + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05), [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 15] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x10), + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x10), }; flexspi_device_config_t deviceconfig = { .flexspiRootClk = 42000000, /* 42MHZ SPI serial clock */ .isSck2Enabled = false, - .flashSize = BOARD_FLASH_SIZE, + .flashSize = (BOARD_FLASH_SIZE/1024), .CSIntervalUnit = kFLEXSPI_CsIntervalUnit1SckCycle, .CSInterval = 2, .CSHoldTime = 0, @@ -176,5 +177,112 @@ flexspi_device_config_t deviceconfig = { .AHBWriteWaitUnit = kFLEXSPI_AhbWriteWaitUnit2AhbCycle, .AHBWriteWaitInterval = 20, }; +#else /* 8MB QSPI flash */ +#define NOR_CMD_LUT_SEQ_IDX_READ_NORMAL 7 +#define NOR_CMD_LUT_SEQ_IDX_READ_FAST 13 +#define NOR_CMD_LUT_SEQ_IDX_READ_FAST_QUAD 0 +#define NOR_CMD_LUT_SEQ_IDX_READSTATUS 1 +#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE 2 +#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 3 +#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_SINGLE 6 +#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_QUAD 4 +#define NOR_CMD_LUT_SEQ_IDX_READID 8 +#define NOR_CMD_LUT_SEQ_IDX_WRITESTATUSREG 9 +#define NOR_CMD_LUT_SEQ_IDX_ENTERQPI 10 +#define NOR_CMD_LUT_SEQ_IDX_EXITQPI 11 +#define NOR_CMD_LUT_SEQ_IDX_READSTATUSREG 12 +#define NOR_CMD_LUT_SEQ_IDX_ERASECHIP 5 +#define CUSTOM_LUT_LENGTH 60 +#define FLASH_QUAD_ENABLE 0x40 +#define FLASH_BUSY_STATUS_POL 1 +#define FLASH_BUSY_STATUS_OFFSET 0 + +static uint32_t customLUT[CUSTOM_LUT_LENGTH] = { + /* Normal read mode -SDR */ + [4 * NOR_CMD_LUT_SEQ_IDX_READ_NORMAL] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x03, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x18), + [4 * NOR_CMD_LUT_SEQ_IDX_READ_NORMAL + 1] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x04, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0), + + /* Fast read mode - SDR */ + [4 * NOR_CMD_LUT_SEQ_IDX_READ_FAST] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x0B, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x18), + [4 * NOR_CMD_LUT_SEQ_IDX_READ_FAST + 1] = FLEXSPI_LUT_SEQ( + kFLEXSPI_Command_DUMMY_SDR, kFLEXSPI_1PAD, 0x08, kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x04), + + /* Fast read quad mode - SDR */ + [4 * NOR_CMD_LUT_SEQ_IDX_READ_FAST_QUAD] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0xEB, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_4PAD, 0x18), + [4 * NOR_CMD_LUT_SEQ_IDX_READ_FAST_QUAD + 1] = FLEXSPI_LUT_SEQ( + kFLEXSPI_Command_DUMMY_SDR, kFLEXSPI_4PAD, 0x06, kFLEXSPI_Command_READ_SDR, kFLEXSPI_4PAD, 0x04), + + /* Read extend parameters */ + [4 * NOR_CMD_LUT_SEQ_IDX_READSTATUS] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x81, kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x04), + + /* Write Enable */ + [4 * NOR_CMD_LUT_SEQ_IDX_WRITEENABLE] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x06, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0), + + /* Erase Sector */ + [4 * NOR_CMD_LUT_SEQ_IDX_ERASESECTOR] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0xD7, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x18), + + /* Page Program - single mode */ + [4 * NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_SINGLE] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x02, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x18), + [4 * NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_SINGLE + 1] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_1PAD, 0x04, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0), + + /* Page Program - quad mode */ + [4 * NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_QUAD] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x32, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x18), + [4 * NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_QUAD + 1] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_4PAD, 0x04, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0), + + /* Read ID */ + [4 * NOR_CMD_LUT_SEQ_IDX_READID] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x9F, kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x04), + + /* Enable Quad mode */ + [4 * NOR_CMD_LUT_SEQ_IDX_WRITESTATUSREG] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x01, kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_1PAD, 0x04), + + /* Enter QPI mode */ + [4 * NOR_CMD_LUT_SEQ_IDX_ENTERQPI] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x35, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0), + + /* Exit QPI mode */ + [4 * NOR_CMD_LUT_SEQ_IDX_EXITQPI] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_4PAD, 0xF5, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0), + + /* Read status register */ + [4 * NOR_CMD_LUT_SEQ_IDX_READSTATUSREG] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x05, kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x04), + + /* Erase whole chip */ + [4 * NOR_CMD_LUT_SEQ_IDX_ERASECHIP] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0xC7, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0), +}; + +flexspi_device_config_t deviceconfig = { + .flexspiRootClk = 120000000, + .flashSize = (BOARD_FLASH_SIZE/1024), + .CSIntervalUnit = kFLEXSPI_CsIntervalUnit1SckCycle, + .CSInterval = 2, + .CSHoldTime = 3, + .CSSetupTime = 3, + .dataValidTime = 0, + .columnspace = 0, + .enableWordAddress = 0, + .AWRSeqIndex = 0, + .AWRSeqNumber = 0, + .ARDSeqIndex = NOR_CMD_LUT_SEQ_IDX_READ_FAST_QUAD, + .ARDSeqNumber = 1, + .AHBWriteWaitUnit = kFLEXSPI_AhbWriteWaitUnit2AhbCycle, + .AHBWriteWaitInterval = 0, +}; + +#endif /* HYPERFLASH_BOOT */ #endif /* _NXP_FLASH_DEFINES_H_ */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexspi.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexspi.c index ad2f3fd683b..ec1e6382002 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexspi.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexspi.c @@ -78,7 +78,7 @@ uint32_t FLEXSPI_GetInstance(FLEXSPI_Type *base); * @param base FLEXSPI base pointer. * @param config Flash configuration parameters. */ -AT_QUICKACCESS_SECTION_CODE(static uint32_t FLEXSPI_ConfigureDll(FLEXSPI_Type *base, flexspi_device_config_t *config)); +AT_QUICKACCESS_SECTION_CODE(uint32_t FLEXSPI_ConfigureDll(FLEXSPI_Type *base, flexspi_device_config_t *config)); /*! * @brief Check and clear IP command execution errors. @@ -138,7 +138,7 @@ uint32_t FLEXSPI_GetInstance(FLEXSPI_Type *base) return instance; } -static uint32_t FLEXSPI_ConfigureDll(FLEXSPI_Type *base, flexspi_device_config_t *config) +uint32_t FLEXSPI_ConfigureDll(FLEXSPI_Type *base, flexspi_device_config_t *config) { bool isUnifiedConfig = true; uint32_t flexspiDllValue; From 288946a226b60f23213cfc9c2e764c87c0718ade Mon Sep 17 00:00:00 2001 From: Gavin Liu Date: Sun, 29 Mar 2020 14:59:33 +0800 Subject: [PATCH 5/5] targets:MIMXRT1050: Update link file for application For the application(firmware) booted by bootloader(OTA), the image doesn't need the "flash_config" and "ivt" header. So update the link file to support both kinds of application (firmware) booted by bootROM and bootloader. In default, the compilation will get the image with "flash_config" and "ivt" header, for example the bootloader compiling. When compiling the OTA application image, please add the line as below in the mbed_app.json file. "target.macros_add" : ["MBED_APP_COMPILE"] This will remove the "flash_config" and "ivt" header in the final image. Signed-off-by: Gavin Liu --- .../TOOLCHAIN_ARM_STD/MIMXRT1052xxxxx.sct | 12 +++++- .../TOOLCHAIN_GCC_ARM/MIMXRT1052xxxxx.ld | 8 +++- .../device/TOOLCHAIN_IAR/MIMXRT1052xxxxx.icf | 38 ++++++++++++------- 3 files changed, 43 insertions(+), 15 deletions(-) diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/TOOLCHAIN_ARM_STD/MIMXRT1052xxxxx.sct b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/TOOLCHAIN_ARM_STD/MIMXRT1052xxxxx.sct index 7efd3421aac..632f0e1079d 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/TOOLCHAIN_ARM_STD/MIMXRT1052xxxxx.sct +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/TOOLCHAIN_ARM_STD/MIMXRT1052xxxxx.sct @@ -42,6 +42,7 @@ #define MBED_APP_SIZE 0x400000 #endif +#if !defined(MBED_APP_COMPILE) #define m_flash_config_start MBED_APP_START #define m_flash_config_size 0x00001000 @@ -53,6 +54,13 @@ #define m_text_start MBED_APP_START + 0x2400 #define m_text_size MBED_APP_SIZE - 0x2400 +#else +#define m_interrupts_start MBED_APP_START +#define m_interrupts_size 0x00000400 + +#define m_text_start MBED_APP_START + 0x400 +#define m_text_size MBED_APP_SIZE - 0x400 +#endif #define m_text2_start 0x00000000 #define m_text2_size 0x00020000 @@ -90,7 +98,8 @@ #define Heap_Size 0x0400 #endif -LR_IROM1 m_flash_config_start m_text_start+m_text_size-m_flash_config_start { ; load region size_region +LR_IROM1 MBED_APP_START m_text_start+m_text_size-MBED_APP_START { ; load region size_region +#if !defined(MBED_APP_COMPILE) RW_m_config_text m_flash_config_start FIXED m_flash_config_size { ; load address = execution address * (.boot_hdr.conf, +FIRST) } @@ -100,6 +109,7 @@ LR_IROM1 m_flash_config_start m_text_start+m_text_size-m_flash_config_start { * (.boot_hdr.boot_data) * (.boot_hdr.dcd_data) } +#endif VECTOR_ROM m_interrupts_start FIXED m_interrupts_size { ; load address = execution address * (RESET,+FIRST) } diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/TOOLCHAIN_GCC_ARM/MIMXRT1052xxxxx.ld b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/TOOLCHAIN_GCC_ARM/MIMXRT1052xxxxx.ld index fb6f6eca23a..338edf26cff 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/TOOLCHAIN_GCC_ARM/MIMXRT1052xxxxx.ld +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/TOOLCHAIN_GCC_ARM/MIMXRT1052xxxxx.ld @@ -50,10 +50,15 @@ M_VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x0400 : 0x0; /* Specify the memory areas */ MEMORY { +#if !defined(MBED_APP_COMPILE) m_flash_config (RX) : ORIGIN = MBED_APP_START, LENGTH = 0x00001000 m_ivt (RX) : ORIGIN = MBED_APP_START + 0x1000, LENGTH = 0x00001000 m_interrupts (RX) : ORIGIN = MBED_APP_START + 0x2000, LENGTH = 0x00000400 m_text (RX) : ORIGIN = MBED_APP_START + 0x2400, LENGTH = MBED_APP_SIZE - 0x2400 +#else + m_interrupts (RX) : ORIGIN = MBED_APP_START, LENGTH = 0x00000400 + m_text (RX) : ORIGIN = MBED_APP_START + 0x400, LENGTH = MBED_APP_SIZE - 0x400 +#endif m_text2 (RX) : ORIGIN = 0x00000000, LENGTH = 0x00020000 m_data (RW) : ORIGIN = 0x80000000, LENGTH = 0x01E00000 m_ncache (RW) : ORIGIN = 0x81E00000, LENGTH = 0x00200000 @@ -64,6 +69,7 @@ MEMORY /* Define output sections */ SECTIONS { +#if !defined(MBED_APP_COMPILE) .flash_config : { . = ALIGN(8); @@ -82,7 +88,7 @@ SECTIONS KEEP(* (.boot_hdr.dcd_data)) /* dcd section */ . = ALIGN(8); } > m_ivt - +#endif /* The startup code goes first into internal RAM */ .interrupts : { diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/TOOLCHAIN_IAR/MIMXRT1052xxxxx.icf b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/TOOLCHAIN_IAR/MIMXRT1052xxxxx.icf index c078c999431..aa0a3adfd0c 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/TOOLCHAIN_IAR/MIMXRT1052xxxxx.icf +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/TOOLCHAIN_IAR/MIMXRT1052xxxxx.icf @@ -46,11 +46,19 @@ define symbol __heap_size__=0x10000; define symbol __ram_vector_table_size__ = isdefinedsymbol(__ram_vector_table__) ? 0x00000400 : 0; define symbol __ram_vector_table_offset__ = isdefinedsymbol(__ram_vector_table__) ? 0x000003FF : 0; -define symbol m_interrupts_start = MBED_APP_START + 0x2000; -define symbol m_interrupts_end = MBED_APP_START + 0x23FF; +if (!isdefinedsymbol(MBED_APP_COMPILE)) { + define symbol m_interrupts_start = MBED_APP_START + 0x2000; + define symbol m_interrupts_end = MBED_APP_START + 0x23FF; -define symbol m_text_start = MBED_APP_START + 0x2400; -define symbol m_text_end = MBED_APP_START + MBED_APP_SIZE - 1; + define symbol m_text_start = MBED_APP_START + 0x2400; + define symbol m_text_end = MBED_APP_START + MBED_APP_SIZE - 1; +} else { + define symbol m_interrupts_start = MBED_APP_START; + define symbol m_interrupts_end = MBED_APP_START + 0x3FF; + + define symbol m_text_start = MBED_APP_START + 0x400; + define symbol m_text_end = MBED_APP_START + MBED_APP_SIZE - 1; +} define symbol m_text2_start = 0x00000000; define symbol m_text2_end = 0x0001FFFF; @@ -70,10 +78,12 @@ define symbol m_data3_end = 0x81DFFFFF; define symbol m_ncache_start = 0x81E00000; define symbol m_ncache_end = 0x81FFFFFF; -define exported symbol m_boot_hdr_conf_start = MBED_APP_START; -define symbol m_boot_hdr_ivt_start = MBED_APP_START + 0x1000; -define symbol m_boot_hdr_boot_data_start = MBED_APP_START + 0x1020; -define symbol m_boot_hdr_dcd_data_start = MBED_APP_START + 0x1030; +if (!isdefinedsymbol(MBED_APP_COMPILE)) { + define exported symbol m_boot_hdr_conf_start = MBED_APP_START; + define symbol m_boot_hdr_ivt_start = MBED_APP_START + 0x1000; + define symbol m_boot_hdr_boot_data_start = MBED_APP_START + 0x1020; + define symbol m_boot_hdr_dcd_data_start = MBED_APP_START + 0x1030; +} /* Sizes */ if (isdefinedsymbol(__stack_size__)) { @@ -117,12 +127,14 @@ do not initialize { section .noinit }; place at address mem: m_interrupts_start { readonly section .intvec }; -place at address mem:m_boot_hdr_conf_start { section .boot_hdr.conf }; -place at address mem:m_boot_hdr_ivt_start { section .boot_hdr.ivt }; -place at address mem:m_boot_hdr_boot_data_start { readonly section .boot_hdr.boot_data }; -place at address mem:m_boot_hdr_dcd_data_start { readonly section .boot_hdr.dcd_data }; +if (!isdefinedsymbol(MBED_APP_COMPILE)) { + place at address mem:m_boot_hdr_conf_start { section .boot_hdr.conf }; + place at address mem:m_boot_hdr_ivt_start { section .boot_hdr.ivt }; + place at address mem:m_boot_hdr_boot_data_start { readonly section .boot_hdr.boot_data }; + place at address mem:m_boot_hdr_dcd_data_start { readonly section .boot_hdr.dcd_data }; + keep{ section .boot_hdr.conf, section .boot_hdr.ivt, section .boot_hdr.boot_data, section .boot_hdr.dcd_data }; +} -keep{ section .boot_hdr.conf, section .boot_hdr.ivt, section .boot_hdr.boot_data, section .boot_hdr.dcd_data }; place in TEXT_region { readonly }; place in DATA3_region { block RW };