diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_IMX/flash_api.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_IMX/flash_api.c index 3cc763d6226..352529c0571 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_IMX/flash_api.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_IMX/flash_api.c @@ -293,7 +293,7 @@ status_t flexspi_nor_flash_page_program_ram(uint32_t address, const uint32_t *sr flashXfer.cmdType = kFLEXSPI_Write; flashXfer.SeqNumber = 2; flashXfer.seqIndex = HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM; - flashXfer.data = (uint32_t *)(src + offset); + flashXfer.data = (uint32_t *)((uint32_t)src + offset); flashXfer.dataSize = BOARD_FLASH_PAGE_SIZE; status = FLEXSPI_TransferBlocking(FLEXSPI, &flashXfer); @@ -509,7 +509,7 @@ status_t flexspi_nor_flash_page_program_ram(uint32_t address, const uint32_t *sr flashXfer.cmdType = kFLEXSPI_Write; flashXfer.SeqNumber = 1; flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_QUAD; - flashXfer.data = (uint32_t *)(src + offset); + flashXfer.data = (uint32_t *)((uint32_t)src + offset); flashXfer.dataSize = BOARD_FLASH_PAGE_SIZE; status = FLEXSPI_TransferBlocking(FLEXSPI, &flashXfer); diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_IMX/spi_api.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_IMX/spi_api.c index 5463cd693c8..5ad86970767 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_IMX/spi_api.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_IMX/spi_api.c @@ -124,16 +124,21 @@ int spi_master_write(spi_t *obj, int value) int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length, char write_fill) { int total = (tx_length > rx_length) ? tx_length : rx_length; + int ret; // Default write is done in each and every call, in future can create HAL API instead LPSPI_SetDummyData(spi_address[obj->instance], write_fill); - LPSPI_MasterTransferBlocking(spi_address[obj->instance], &(lpspi_transfer_t){ - .txData = (uint8_t *)tx_buffer, - .rxData = (uint8_t *)rx_buffer, - .dataSize = total, - .configFlags = kLPSPI_MasterPcs0 | kLPSPI_MasterPcsContinuous | kLPSPI_SlaveByteSwap, - }); + do + { + ret = LPSPI_MasterTransferBlocking(spi_address[obj->instance], &(lpspi_transfer_t){ + .txData = (uint8_t *)tx_buffer, + .rxData = (uint8_t *)rx_buffer, + .dataSize = total, + .configFlags = kLPSPI_MasterPcs0 | kLPSPI_MasterPcsContinuous | kLPSPI_SlaveByteSwap, + }); + + } while((ret == kStatus_LPSPI_Busy)); return total; } diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/PeripheralNames.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/PeripheralNames.h index 996940c64b5..9cd8dedf9a2 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/PeripheralNames.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/PeripheralNames.h @@ -132,6 +132,7 @@ typedef enum { SPI_1 = 1, SPI_2 = 2, SPI_3 = 3, + SPI_4 = 4, } SPIName; #ifdef __cplusplus diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/PeripheralPins.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/PeripheralPins.c index ed8a4731eee..522ac5064fd 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/PeripheralPins.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/PeripheralPins.c @@ -52,11 +52,13 @@ const PinMap PinMap_I2C_SCL[] = { /************UART***************/ const PinMap PinMap_UART_TX[] = { {GPIO_AD_B0_12, UART_1, 2}, + {GPIO_AD_B1_06, UART_3, 2}, {NC , NC , 0} }; const PinMap PinMap_UART_RX[] = { {GPIO_AD_B0_13, UART_1, 2}, + {GPIO_AD_B1_07, UART_3, 2}, {NC , NC , 0} }; @@ -64,24 +66,28 @@ const PinMap PinMap_UART_RX[] = { const PinMap PinMap_SPI_SCLK[] = { {GPIO_SD_B0_00, SPI_1, ((1U << DAISY_REG_VALUE_SHIFT) | (0x4F0 << DAISY_REG_SHIFT) | 4)}, {GPIO_AD_B0_00, SPI_3, ((0U << DAISY_REG_VALUE_SHIFT) | (0x510 << DAISY_REG_SHIFT) | 7)}, + {GPIO_B0_03, SPI_4, ((0U << DAISY_REG_VALUE_SHIFT) | (0x520 << DAISY_REG_SHIFT) | 3)}, {NC , NC , 0} }; const PinMap PinMap_SPI_MOSI[] = { {GPIO_SD_B0_02, SPI_1, ((1U << DAISY_REG_VALUE_SHIFT) | (0x4F8 << DAISY_REG_SHIFT) | 4)}, {GPIO_AD_B0_01, SPI_3, ((0U << DAISY_REG_VALUE_SHIFT) | (0x518 << DAISY_REG_SHIFT) | 7)}, + {GPIO_B0_02, SPI_4, ((0U << DAISY_REG_VALUE_SHIFT) | (0x528 << DAISY_REG_SHIFT) | 3)}, {NC , NC , 0} }; const PinMap PinMap_SPI_MISO[] = { {GPIO_SD_B0_03, SPI_1, ((1U << DAISY_REG_VALUE_SHIFT) | (0x4F4 << DAISY_REG_SHIFT) | 4)}, {GPIO_AD_B0_02, SPI_3, ((0U << DAISY_REG_VALUE_SHIFT) | (0x514 << DAISY_REG_SHIFT) | 7)}, + {GPIO_B0_01, SPI_4, ((0U << DAISY_REG_VALUE_SHIFT) | (0x524 << DAISY_REG_SHIFT) | 3)}, {NC , NC , 0} }; const PinMap PinMap_SPI_SSEL[] = { {GPIO_SD_B0_01, SPI_1, ((0U << DAISY_REG_VALUE_SHIFT) | (0x4EC << DAISY_REG_SHIFT) | 4)}, {GPIO_AD_B0_03, SPI_3, ((0U << DAISY_REG_VALUE_SHIFT) | (0x50C << DAISY_REG_SHIFT) | 7)}, + {GPIO_B0_00, SPI_4, ((0U << DAISY_REG_VALUE_SHIFT) | (0x51C << DAISY_REG_SHIFT) | 3)}, {NC , NC , 0} }; diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/flash_defines.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/flash_defines.h index 6f4db492117..656b80d7f50 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/flash_defines.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/flash_defines.h @@ -227,7 +227,7 @@ static uint32_t customLUT[CUSTOM_LUT_LENGTH] = { /* Erase Sector */ [4 * NOR_CMD_LUT_SEQ_IDX_ERASESECTOR] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0xD7, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x18), + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x20, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x18), /* Page Program - single mode */ [4 * NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_SINGLE] = diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/fsl_clock_config.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/fsl_clock_config.c index 316eaa9d08d..d9a1fb3c93e 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/fsl_clock_config.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/fsl_clock_config.c @@ -139,7 +139,7 @@ called_from_default_init: true * Variables for BOARD_BootClockRUN configuration ******************************************************************************/ const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN = { - .loopDivider = 100, /* PLL loop divider, Fout = Fin * 50 */ + .loopDivider = 88, /* PLL loop divider, Fout = Fin * 44 */ .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ }; const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN = { @@ -467,5 +467,5 @@ void BOARD_BootClockRUN(void) /* Set GPT2 High frequency reference clock source. */ IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK; /* Set SystemCoreClock variable. */ - SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK; + SystemCoreClock = CLOCK_GetCpuClkFreq(); } diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/specific.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/specific.c index 8d7464ca321..5abd97c2b17 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/specific.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/specific.c @@ -75,7 +75,11 @@ void SwitchSystemClocks(lpm_power_mode_t power_mode) case LPM_PowerModeLowSpeedRun: case LPM_PowerModeSysIdle: CLOCK_SET_DIV(kCLOCK_SemcDiv, 3); // SEMC CLK should not exceed 166MHz +#ifdef HYPERFLASH_BOOT CLOCK_SET_DIV(kCLOCK_FlexspiDiv, 1); // FLEXSPI in DDR mode +#else + CLOCK_SET_DIV(kCLOCK_FlexspiDiv, 3); // FLEXSPI in SDR mode +#endif CLOCK_SET_MUX(kCLOCK_FlexspiMux, 2); // FLEXSPI mux to PLL2 PFD2 /* CORE CLK to 132MHz and AHB, IPG, PERCLK to 33MHz */ CLOCK_SET_DIV(kCLOCK_PerclkDiv, 0); @@ -108,6 +112,7 @@ void SwitchSystemClocks(lpm_power_mode_t power_mode) /* Enable clock gate of flexspi. */ CCM->CCGR6 |= (CCM_CCGR6_CG5_MASK); +#ifdef HYPERFLASH_BOOT if ((LPM_PowerModeLowPowerRun == power_mode) || (LPM_PowerModeLPIdle == power_mode)) { FLEXSPI_INST->DLLCR[0] = FLEXSPI_DLLCR_OVRDEN(1) | FLEXSPI_DLLCR_OVRDVAL(19); @@ -116,7 +121,8 @@ void SwitchSystemClocks(lpm_power_mode_t power_mode) { FLEXSPI_INST->DLLCR[0] = FLEXSPI_DLLCR_DLLEN(1) | FLEXSPI_DLLCR_SLVDLYTARGET(15); } - +#endif + FLEXSPI_INST->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK; FLEXSPI_INST->MCR0 |= FLEXSPI_MCR0_SWRESET_MASK; while (FLEXSPI_INST->MCR0 & FLEXSPI_MCR0_SWRESET_MASK) diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/xip/evkbimxrt1050_sdram_ini_dcd.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/xip/evkbimxrt1050_sdram_ini_dcd.c index 50ba9a82145..a2c02676993 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/xip/evkbimxrt1050_sdram_ini_dcd.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/xip/evkbimxrt1050_sdram_ini_dcd.c @@ -239,9 +239,9 @@ const uint8_t dcd_data[] = { /* #1.95, command: write_value, address: SEMC_MCR, value: 0x10000004, size: 4 */ 0x40, 0x2F, 0x00, 0x00, 0x10, 0x00, 0x00, 0x04, /* #1.96, command: write_value, address: SEMC_BMCR0, value: 0x30524, size: 4 */ - 0x40, 0x2F, 0x00, 0x08, 0x00, 0x03, 0x05, 0x24, + 0x40, 0x2F, 0x00, 0x08, 0x00, 0x00, 0x00, 0x81, /* #1.97, command: write_value, address: SEMC_BMCR1, value: 0x6030524, size: 4 */ - 0x40, 0x2F, 0x00, 0x0C, 0x06, 0x03, 0x05, 0x24, + 0x40, 0x2F, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x81, /* #1.98, command: write_value, address: SEMC_BR0, value: 0x8000001B, size: 4 */ 0x40, 0x2F, 0x00, 0x10, 0x80, 0x00, 0x00, 0x1B, /* #1.99, command: write_value, address: SEMC_BR1, value: 0x8200001B, size: 4 */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_lpspi.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_lpspi.c index dbfbe38c980..13b902877a8 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_lpspi.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_lpspi.c @@ -258,9 +258,9 @@ void LPSPI_MasterGetDefaultConfig(lpspi_master_config_t *masterConfig) masterConfig->cpha = kLPSPI_ClockPhaseFirstEdge; masterConfig->direction = kLPSPI_MsbFirst; - masterConfig->pcsToSckDelayInNanoSec = 1000000000 / masterConfig->baudRate * 2; - masterConfig->lastSckToPcsDelayInNanoSec = 1000000000 / masterConfig->baudRate * 2; - masterConfig->betweenTransferDelayInNanoSec = 1000000000 / masterConfig->baudRate * 2; + masterConfig->pcsToSckDelayInNanoSec = 80; + masterConfig->lastSckToPcsDelayInNanoSec = 60; + masterConfig->betweenTransferDelayInNanoSec = 160; masterConfig->whichPcs = kLPSPI_Pcs0; masterConfig->pcsActiveHighOrLow = kLPSPI_PcsActiveLow; @@ -871,14 +871,18 @@ status_t LPSPI_MasterTransferBlocking(LPSPI_Type *base, lpspi_transfer_t *transf { } - if (txData) + /* To prevent rxfifo overflow, ensure transmitting and receiving are executed in parallel */ + if(((NULL == rxData) || (rxRemainingByteCount - txRemainingByteCount)/bytesEachRead < fifoSize)) { - wordToSend = LPSPI_CombineWriteData(txData, bytesEachWrite, isByteSwap); - txData += bytesEachWrite; - } + if (txData) + { + wordToSend = LPSPI_CombineWriteData(txData, bytesEachWrite, isByteSwap); + txData += bytesEachWrite; + } - LPSPI_WriteData(base, wordToSend); - txRemainingByteCount -= bytesEachWrite; + LPSPI_WriteData(base, wordToSend); + txRemainingByteCount -= bytesEachWrite; + } /*Check whether there is RX data in RX FIFO . Read out the RX data so that the RX FIFO would not overrun.*/ if (rxData)