diff --git a/components/storage/blockdevice/COMPONENT_FLASHIAP/mbed_lib.json b/components/storage/blockdevice/COMPONENT_FLASHIAP/mbed_lib.json
index a3ad9ada1e0..9496782e163 100644
--- a/components/storage/blockdevice/COMPONENT_FLASHIAP/mbed_lib.json
+++ b/components/storage/blockdevice/COMPONENT_FLASHIAP/mbed_lib.json
@@ -22,6 +22,10 @@
         "S5JS100": {
             "base-address": "0x40EF5000",
             "size": "0x80000"
+        },
+        "MIMXRT1050_EVK": {
+            "base-address": "0x60400000",
+            "size": "0x3C00000"
         }
     }
 }
diff --git a/features/netsocket/emac-drivers/TARGET_NXP_EMAC/TARGET_IMX/TARGET_MIMXRT1050_EVK/hardware_init.c b/features/netsocket/emac-drivers/TARGET_NXP_EMAC/TARGET_IMX/TARGET_MIMXRT1050_EVK/hardware_init.c
index a48c7ce637f..2f6e27f9d43 100644
--- a/features/netsocket/emac-drivers/TARGET_NXP_EMAC/TARGET_IMX/TARGET_MIMXRT1050_EVK/hardware_init.c
+++ b/features/netsocket/emac-drivers/TARGET_NXP_EMAC/TARGET_IMX/TARGET_MIMXRT1050_EVK/hardware_init.c
@@ -215,7 +215,7 @@ void kinetis_init_eth_hardware(void)
     /* pull up the ENET_INT before RESET. */
     GPIO_WritePinOutput(GPIO1, 10, 1);
     GPIO_WritePinOutput(GPIO1, 9, 0);
-    wait_ms(1);
+    wait_us(1 * 1000);
     GPIO_WritePinOutput(GPIO1, 9, 1);
 }
 
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_IMX/flash_api.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_IMX/flash_api.c
new file mode 100644
index 00000000000..352529c0571
--- /dev/null
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_IMX/flash_api.c
@@ -0,0 +1,640 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2019 ARM Limited
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "flash_api.h"
+#include "mbed_toolchain.h"
+#include "mbed_critical.h"
+
+#if DEVICE_FLASH
+
+#include "fsl_flexspi.h"
+#include "fsl_cache.h"
+#include "flash_defines.h"
+
+AT_QUICKACCESS_SECTION_CODE(void flexspi_update_lut_ram(void));
+AT_QUICKACCESS_SECTION_CODE(status_t flexspi_nor_write_enable_ram(uint32_t baseAddr));
+AT_QUICKACCESS_SECTION_CODE(status_t flexspi_nor_wait_bus_busy_ram(void));
+AT_QUICKACCESS_SECTION_CODE(status_t flexspi_nor_flash_erase_sector_ram(uint32_t address));
+AT_QUICKACCESS_SECTION_CODE(status_t flexspi_nor_flash_page_program_ram(uint32_t address,
+                                                                        const uint32_t *src,
+                                                                        uint32_t size));
+AT_QUICKACCESS_SECTION_CODE(void flexspi_nor_flash_read_data_ram(uint32_t addr,
+                                                                 uint32_t *buffer,
+                                                                 uint32_t size));
+AT_QUICKACCESS_SECTION_CODE(void *flexspi_memset(void *buf, int c, size_t n));
+/**
+ * @brief Set bytes in memory. If put this code in SRAM, Make sure this code
+ * does not call functions in Flash.
+ *
+ * @return pointer to start of buffer
+ */
+void *flexspi_memset(void *buf, int c, size_t n)
+{
+    /* do byte-sized initialization until word-aligned or finished */
+    unsigned char *d_byte = (unsigned char *)buf;
+    unsigned char c_byte = (unsigned char)c;
+
+    while (((unsigned int)d_byte) & 0x3) {
+        if (n == 0) {
+            return buf;
+        }
+        *(d_byte++) = c_byte;
+        n--;
+    };
+
+    /* do word-sized initialization as long as possible */
+
+    unsigned int *d_word = (unsigned int *)d_byte;
+    unsigned int c_word = (unsigned int)(unsigned char)c;
+
+    c_word |= c_word << 8;
+    c_word |= c_word << 16;
+
+    while (n >= sizeof(unsigned int)) {
+        *(d_word++) = c_word;
+        n -= sizeof(unsigned int);
+    }
+
+    /* do byte-sized initialization until finished */
+
+    d_byte = (unsigned char *)d_word;
+
+    while (n > 0) {
+        *(d_byte++) = c_byte;
+        n--;
+    }
+
+    return buf;
+}
+
+#ifdef HYPERFLASH_BOOT
+AT_QUICKACCESS_SECTION_CODE(void flexspi_lower_clock_ram(void));
+AT_QUICKACCESS_SECTION_CODE(void flexspi_clock_update_ram(void));
+void flexspi_update_lut_ram(void)
+{
+    flexspi_config_t config;
+
+    flexspi_memset(&config, 0, sizeof(config));
+
+    /*Get FLEXSPI default settings and configure the flexspi. */
+    FLEXSPI_GetDefaultConfig(&config);
+
+    /*Set AHB buffer size for reading data through AHB bus. */
+    config.ahbConfig.enableAHBPrefetch = true;
+    /*Allow AHB read start address do not follow the alignment requirement. */
+    config.ahbConfig.enableReadAddressOpt = true;
+    config.ahbConfig.enableAHBBufferable  = true;
+    config.ahbConfig.enableAHBCachable    = true;
+    /* enable diff clock and DQS */
+    config.enableSckBDiffOpt = true;
+    config.rxSampleClock     = kFLEXSPI_ReadSampleClkExternalInputFromDqsPad;
+    config.enableCombination = true;
+    FLEXSPI_Init(FLEXSPI, &config);
+
+    /* Configure flash settings according to serial flash feature. */
+    FLEXSPI_SetFlashConfig(FLEXSPI, &deviceconfig, kFLEXSPI_PortA1);
+
+    /* Update LUT table. */
+    FLEXSPI_UpdateLUT(FLEXSPI, 0, customLUT, CUSTOM_LUT_LENGTH);
+
+    FLEXSPI_SoftwareReset(FLEXSPI);
+
+    /* Wait for bus idle. */
+    while (!FLEXSPI_GetBusIdleStatus(FLEXSPI)) {
+    }
+}
+
+status_t flexspi_nor_write_enable_ram(uint32_t baseAddr)
+{
+    flexspi_transfer_t flashXfer;
+    status_t status = kStatus_Success;
+
+    flexspi_memset(&flashXfer, 0, sizeof(flashXfer));
+
+    /* Write enable */
+    flashXfer.deviceAddress = baseAddr;
+    flashXfer.port          = kFLEXSPI_PortA1;
+    flashXfer.cmdType       = kFLEXSPI_Command;
+    flashXfer.SeqNumber     = 2;
+    flashXfer.seqIndex      = HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE;
+
+    status = FLEXSPI_TransferBlocking(FLEXSPI, &flashXfer);
+
+    return status;
+}
+
+status_t flexspi_nor_wait_bus_busy_ram(void)
+{
+    /* Wait status ready. */
+    bool isBusy = false;
+    uint32_t readValue = 0;
+    status_t status = kStatus_Success;
+    flexspi_transfer_t flashXfer;
+
+    flexspi_memset(&flashXfer, 0, sizeof(flashXfer));
+
+    flashXfer.deviceAddress = 0;
+    flashXfer.port          = kFLEXSPI_PortA1;
+    flashXfer.cmdType       = kFLEXSPI_Read;
+    flashXfer.SeqNumber     = 2;
+    flashXfer.seqIndex      = HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS;
+    flashXfer.data          = &readValue;
+    flashXfer.dataSize      = 2;
+
+    do {
+        status = FLEXSPI_TransferBlocking(FLEXSPI, &flashXfer);
+
+        if (status != kStatus_Success) {
+            return status;
+        }
+
+        if (readValue & 0x8000) {
+            isBusy = false;
+        } else {
+            isBusy = true;
+        }
+
+        if (readValue & 0x3200) {
+            status = kStatus_Fail;
+            break;
+        }
+
+    } while (isBusy);
+
+    return status;
+
+}
+
+status_t flexspi_nor_flash_erase_sector_ram(uint32_t address)
+{
+    status_t status = kStatus_Success;
+    flexspi_transfer_t flashXfer;
+
+    flexspi_memset(&flashXfer, 0, sizeof(flashXfer));
+
+    /* Write enable */
+    status = flexspi_nor_write_enable_ram(address);
+    if (status != kStatus_Success) {
+        return status;
+    }
+
+    flashXfer.deviceAddress = address;
+    flashXfer.port          = kFLEXSPI_PortA1;
+    flashXfer.cmdType       = kFLEXSPI_Command;
+    flashXfer.SeqNumber     = 4;
+    flashXfer.seqIndex      = HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR;
+
+    status = FLEXSPI_TransferBlocking(FLEXSPI, &flashXfer);
+    if (status != kStatus_Success) {
+        return status;
+    }
+
+    status = flexspi_nor_wait_bus_busy_ram();
+
+    /* Do software reset. */
+    FLEXSPI_SoftwareReset(FLEXSPI);
+
+    return status;
+}
+
+void flexspi_lower_clock_ram(void)
+{
+    unsigned int reg = 0;
+
+    /* Wait for bus idle. */
+    while (!FLEXSPI_GetBusIdleStatus(FLEXSPI)) {
+    }
+
+    FLEXSPI_Enable(FLEXSPI, false);
+
+    /* Disable FlexSPI clock */
+    CCM->CCGR6 &= ~CCM_CCGR6_CG5_MASK;
+
+    /* flexspi clock 66M, DDR mode, internal clock 33M. */
+    reg = CCM->CSCMR1;
+    reg &= ~CCM_CSCMR1_FLEXSPI_PODF_MASK;
+    reg |= CCM_CSCMR1_FLEXSPI_PODF(3);
+    CCM->CSCMR1 = reg;
+
+    /* Enable FlexSPI clock */
+    CCM->CCGR6 |= CCM_CCGR6_CG5_MASK;
+
+    FLEXSPI_Enable(FLEXSPI, true);
+
+    /* Do software reset. */
+    FLEXSPI_SoftwareReset(FLEXSPI);
+
+    /* Wait for bus idle. */
+    while (!FLEXSPI_GetBusIdleStatus(FLEXSPI)) {
+    }
+}
+
+void flexspi_clock_update_ram(void)
+{
+    /* Program finished, speed the clock to 133M. */
+    /* Wait for bus idle before change flash configuration. */
+    while (!FLEXSPI_GetBusIdleStatus(FLEXSPI)) {
+    }
+    FLEXSPI_Enable(FLEXSPI, false);
+    /* Disable FlexSPI clock */
+    CCM->CCGR6 &= ~CCM_CCGR6_CG5_MASK;
+
+    /* flexspi clock 260M, DDR mode, internal clock 130M. */
+    CCM->CSCMR1 &= ~CCM_CSCMR1_FLEXSPI_PODF_MASK;
+
+    /* Enable FlexSPI clock */
+    CCM->CCGR6 |= CCM_CCGR6_CG5_MASK;
+
+    FLEXSPI_Enable(FLEXSPI, true);
+
+    /* Do software reset. */
+    FLEXSPI_SoftwareReset(FLEXSPI);
+
+    /* Wait for bus idle. */
+    while (!FLEXSPI_GetBusIdleStatus(FLEXSPI)) {
+    }
+}
+
+status_t flexspi_nor_flash_page_program_ram(uint32_t address, const uint32_t *src, uint32_t size)
+{
+    status_t status = kStatus_Success;
+    flexspi_transfer_t flashXfer;
+    uint32_t offset = 0;
+
+    flexspi_memset(&flashXfer, 0, sizeof(flashXfer));
+
+    flexspi_lower_clock_ram();
+
+    while (size > 0) {
+        /* Write enable */
+        status = flexspi_nor_write_enable_ram(address + offset);
+
+        if (status != kStatus_Success) {
+            return status;
+        }
+
+        /* Prepare page program command */
+        flashXfer.deviceAddress = address + offset;
+        flashXfer.port          = kFLEXSPI_PortA1;
+        flashXfer.cmdType       = kFLEXSPI_Write;
+        flashXfer.SeqNumber     = 2;
+        flashXfer.seqIndex      = HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM;
+        flashXfer.data          = (uint32_t *)((uint32_t)src + offset);
+        flashXfer.dataSize      = BOARD_FLASH_PAGE_SIZE;
+
+        status = FLEXSPI_TransferBlocking(FLEXSPI, &flashXfer);
+
+        if (status != kStatus_Success) {
+            return status;
+        }
+
+        status = flexspi_nor_wait_bus_busy_ram();
+
+        if (status != kStatus_Success) {
+            return status;
+        }
+
+        size -= BOARD_FLASH_PAGE_SIZE;
+        offset += BOARD_FLASH_PAGE_SIZE;
+    }
+
+    flexspi_clock_update_ram();
+
+    return status;
+}
+
+#else
+AT_QUICKACCESS_SECTION_CODE(status_t flexspi_nor_enable_quad_mode_ram(void));
+status_t flexspi_nor_enable_quad_mode_ram(void)
+{
+    flexspi_transfer_t flashXfer;
+    uint32_t writeValue = FLASH_QUAD_ENABLE;
+    status_t status = kStatus_Success;
+
+    flexspi_memset(&flashXfer, 0, sizeof(flashXfer));
+    /* Write enable */
+    status = flexspi_nor_write_enable_ram(0);
+
+    if (status != kStatus_Success) {
+        return status;
+    }
+
+    /* Enable quad mode. */
+    flashXfer.deviceAddress = 0;
+    flashXfer.port          = kFLEXSPI_PortA1;
+    flashXfer.cmdType       = kFLEXSPI_Write;
+    flashXfer.SeqNumber     = 1;
+    flashXfer.seqIndex      = NOR_CMD_LUT_SEQ_IDX_WRITESTATUSREG;
+    flashXfer.data          = &writeValue;
+    flashXfer.dataSize      = 1;
+
+    status = FLEXSPI_TransferBlocking(FLEXSPI, &flashXfer);
+    if (status != kStatus_Success) {
+        return status;
+    }
+
+    status = flexspi_nor_wait_bus_busy_ram();
+
+    /* Do software reset. */
+    FLEXSPI_SoftwareReset(FLEXSPI);
+
+    return status;
+}
+
+void flexspi_update_lut_ram(void)
+{
+    flexspi_config_t config;
+
+    flexspi_memset(&config, 0, sizeof(config));
+
+    /*Get FLEXSPI default settings and configure the flexspi. */
+    FLEXSPI_GetDefaultConfig(&config);
+
+    /*Set AHB buffer size for reading data through AHB bus. */
+    config.ahbConfig.enableAHBPrefetch    = true;
+    config.ahbConfig.enableAHBBufferable  = true;
+    config.ahbConfig.enableReadAddressOpt = true;
+    config.ahbConfig.enableAHBCachable    = true;
+    config.rxSampleClock                  = kFLEXSPI_ReadSampleClkLoopbackFromDqsPad;
+    FLEXSPI_Init(FLEXSPI, &config);
+
+    /* Configure flash settings according to serial flash feature. */
+    FLEXSPI_SetFlashConfig(FLEXSPI, &deviceconfig, kFLEXSPI_PortA1);
+
+    /* Update LUT table. */
+    FLEXSPI_UpdateLUT(FLEXSPI, 0, customLUT, CUSTOM_LUT_LENGTH);
+
+    /* Do software reset. */
+    FLEXSPI_SoftwareReset(FLEXSPI);
+    /* Wait for bus idle. */
+    while (!FLEXSPI_GetBusIdleStatus(FLEXSPI)) {
+    }
+    flexspi_nor_enable_quad_mode_ram();
+}
+
+status_t flexspi_nor_write_enable_ram(uint32_t baseAddr)
+{
+    flexspi_transfer_t flashXfer;
+    status_t status = kStatus_Success;
+
+    flexspi_memset(&flashXfer, 0, sizeof(flashXfer));
+    /* Write enable */
+    flashXfer.deviceAddress = baseAddr;
+    flashXfer.port          = kFLEXSPI_PortA1;
+    flashXfer.cmdType       = kFLEXSPI_Command;
+    flashXfer.SeqNumber     = 1;
+    flashXfer.seqIndex      = NOR_CMD_LUT_SEQ_IDX_WRITEENABLE;
+
+    status = FLEXSPI_TransferBlocking(FLEXSPI, &flashXfer);
+
+    return status;
+}
+
+status_t flexspi_nor_wait_bus_busy_ram(void)
+{
+    /* Wait status ready. */
+    bool isBusy;
+    uint32_t readValue;
+    status_t status = kStatus_Success;
+    flexspi_transfer_t flashXfer;
+
+    flexspi_memset(&flashXfer, 0, sizeof(flashXfer));
+
+    flashXfer.deviceAddress = 0;
+    flashXfer.port          = kFLEXSPI_PortA1;
+    flashXfer.cmdType       = kFLEXSPI_Read;
+    flashXfer.SeqNumber     = 1;
+    flashXfer.seqIndex      = NOR_CMD_LUT_SEQ_IDX_READSTATUSREG;
+    flashXfer.data          = &readValue;
+    flashXfer.dataSize      = 1;
+
+    do {
+        status = FLEXSPI_TransferBlocking(FLEXSPI, &flashXfer);
+
+        if (status != kStatus_Success) {
+            return status;
+        }
+        if (FLASH_BUSY_STATUS_POL) {
+            if (readValue & (1U << FLASH_BUSY_STATUS_OFFSET)) {
+                isBusy = true;
+            } else {
+                isBusy = false;
+            }
+        } else {
+            if (readValue & (1U << FLASH_BUSY_STATUS_OFFSET)) {
+                isBusy = false;
+            } else {
+                isBusy = true;
+            }
+        }
+
+    } while (isBusy);
+
+    return status;
+}
+
+
+status_t flexspi_nor_flash_erase_sector_ram(uint32_t address)
+{
+    flexspi_transfer_t flashXfer;
+    status_t status = kStatus_Success;
+
+    flexspi_memset(&flashXfer, 0, sizeof(flashXfer));
+
+    /* Write enable */
+    flashXfer.deviceAddress = address;
+    flashXfer.port          = kFLEXSPI_PortA1;
+    flashXfer.cmdType       = kFLEXSPI_Command;
+    flashXfer.SeqNumber     = 1;
+    flashXfer.seqIndex      = NOR_CMD_LUT_SEQ_IDX_WRITEENABLE;
+
+    status = FLEXSPI_TransferBlocking(FLEXSPI, &flashXfer);
+
+    if (status != kStatus_Success) {
+        return status;
+    }
+
+    flashXfer.deviceAddress = address;
+    flashXfer.port          = kFLEXSPI_PortA1;
+    flashXfer.cmdType       = kFLEXSPI_Command;
+    flashXfer.SeqNumber     = 1;
+    flashXfer.seqIndex      = NOR_CMD_LUT_SEQ_IDX_ERASESECTOR;
+    status                  = FLEXSPI_TransferBlocking(FLEXSPI, &flashXfer);
+
+    if (status != kStatus_Success) {
+        return status;
+    }
+
+    status = flexspi_nor_wait_bus_busy_ram();
+
+    /* Do software reset. */
+    FLEXSPI_SoftwareReset(FLEXSPI);
+
+    return status;
+}
+
+status_t flexspi_nor_flash_page_program_ram(uint32_t address, const uint32_t *src, uint32_t size)
+{
+    flexspi_transfer_t flashXfer;
+    status_t status = kStatus_Success;
+    uint32_t offset = 0;
+
+    flexspi_memset(&flashXfer, 0, sizeof(flashXfer));
+
+    while (size > 0) {
+        /* Write enable */
+        status = flexspi_nor_write_enable_ram(address + offset);
+
+        if (status != kStatus_Success) {
+            return status;
+        }
+
+        /* Prepare page program command */
+        flashXfer.deviceAddress = address + offset;
+        flashXfer.port          = kFLEXSPI_PortA1;
+        flashXfer.cmdType       = kFLEXSPI_Write;
+        flashXfer.SeqNumber     = 1;
+        flashXfer.seqIndex      = NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_QUAD;
+        flashXfer.data          = (uint32_t *)((uint32_t)src + offset);
+        flashXfer.dataSize      = BOARD_FLASH_PAGE_SIZE;
+
+        status = FLEXSPI_TransferBlocking(FLEXSPI, &flashXfer);
+
+        if (status != kStatus_Success) {
+            return status;
+        }
+
+        status = flexspi_nor_wait_bus_busy_ram();
+
+        if (status != kStatus_Success) {
+            return status;
+        }
+
+        size -= BOARD_FLASH_PAGE_SIZE;
+        offset += BOARD_FLASH_PAGE_SIZE;
+    }
+
+    /* Do software reset. */
+    FLEXSPI_SoftwareReset(FLEXSPI);
+
+    return status;
+}
+
+#endif
+void flexspi_nor_flash_read_data_ram(uint32_t addr, uint32_t *buffer, uint32_t size)
+{
+    memcpy(buffer, (void *)addr, size);
+}
+
+int32_t flash_init(flash_t *obj)
+{
+    core_util_critical_section_enter();
+    flexspi_update_lut_ram();
+    core_util_critical_section_exit();
+
+    return 0;
+}
+
+int32_t flash_erase_sector(flash_t *obj, uint32_t address)
+{
+    status_t status = kStatus_Success;
+    int32_t ret = 0;
+
+    core_util_critical_section_enter();
+
+    status = flexspi_nor_flash_erase_sector_ram(address - FlexSPI_AMBA_BASE);
+
+    if (status != kStatus_Success) {
+        ret = -1;
+    } else {
+        DCACHE_InvalidateByRange(address, BOARD_FLASH_SECTOR_SIZE);
+    }
+
+    core_util_critical_section_exit();
+
+    return ret;
+}
+
+int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data, uint32_t size)
+{
+    status_t status = kStatus_Success;
+    int32_t ret = 0;
+
+    core_util_critical_section_enter();
+
+    status = flexspi_nor_flash_page_program_ram(address - FlexSPI_AMBA_BASE, (uint32_t *)data, size);
+
+    if (status != kStatus_Success) {
+        ret = -1;
+    } else {
+        DCACHE_InvalidateByRange(address, size);
+    }
+
+    core_util_critical_section_exit();
+
+    return ret;
+}
+
+int32_t flash_read(flash_t *obj, uint32_t address, uint8_t *data, uint32_t size)
+{
+    flexspi_nor_flash_read_data_ram(address, (uint32_t *)data, size);
+
+    return 0;
+}
+
+int32_t flash_free(flash_t *obj)
+{
+    return 0;
+}
+
+uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address)
+{
+    uint32_t sectorsize = MBED_FLASH_INVALID_SIZE;
+    uint32_t devicesize = BOARD_FLASH_SIZE;
+    uint32_t startaddr = BOARD_FLASH_START_ADDR;
+
+    if ((address >= startaddr) && (address < (startaddr + devicesize))) {
+        sectorsize = BOARD_FLASH_SECTOR_SIZE;
+    }
+
+    return sectorsize;
+}
+
+uint32_t flash_get_page_size(const flash_t *obj)
+{
+    return BOARD_FLASH_PAGE_SIZE;
+}
+
+uint32_t flash_get_start_address(const flash_t *obj)
+{
+    return BOARD_FLASHIAP_START_ADDR;
+}
+
+uint32_t flash_get_size(const flash_t *obj)
+{
+    return BOARD_FLASHIAP_SIZE;
+}
+
+uint8_t flash_get_erase_value(const flash_t *obj)
+{
+    (void)obj;
+
+    return 0xFF;
+}
+
+#endif //DEVICE_FLASH
+
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_IMX/gpio_irq_api.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_IMX/gpio_irq_api.c
index 0d87dc44f01..f8fe706d630 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_IMX/gpio_irq_api.c
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_IMX/gpio_irq_api.c
@@ -38,7 +38,8 @@ static gpio_irq_handler irq_handler;
 static GPIO_Type * const gpio_addrs[] = GPIO_BASE_PTRS;
 
 /* Array of PORT IRQ number. */
-static const IRQn_Type gpio_irqs[] = GPIO_COMBINED_IRQS;
+static const IRQn_Type gpio_low_irqs[] = GPIO_COMBINED_LOW_IRQS;
+static const IRQn_Type gpio_high_irqs[] = GPIO_COMBINED_HIGH_IRQS;
 
 static void handle_interrupt_in(PortName port, int ch_base)
 {
@@ -117,8 +118,6 @@ void gpio5_irq(void)
 
 int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id)
 {
-    uint32_t int_index;
-
     if (pin == NC) {
         return -1;
     }
@@ -156,14 +155,14 @@ int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32
             break;
     }
 
-    int_index = 2 * obj->port;
     if (obj->pin > 15) {
-        int_index -= 1;
+        NVIC_SetVector(gpio_high_irqs[obj->port], vector);
+        NVIC_EnableIRQ(gpio_high_irqs[obj->port]);
+    } else {
+        NVIC_SetVector(gpio_low_irqs[obj->port], vector);
+        NVIC_EnableIRQ(gpio_low_irqs[obj->port]);
     }
 
-    NVIC_SetVector(gpio_irqs[int_index], vector);
-    NVIC_EnableIRQ(gpio_irqs[int_index]);
-
     obj->ch = ch_base + obj->pin;
     channel_ids[obj->ch] = id;
 
@@ -243,12 +242,20 @@ void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable)
 
 void gpio_irq_enable(gpio_irq_t *obj)
 {
-    NVIC_EnableIRQ(gpio_irqs[obj->port]);
+    if (obj->pin > 15) {
+        NVIC_EnableIRQ(gpio_high_irqs[obj->port]);
+    } else {
+        NVIC_EnableIRQ(gpio_low_irqs[obj->port]);
+    }
 }
 
 void gpio_irq_disable(gpio_irq_t *obj)
 {
-    NVIC_DisableIRQ(gpio_irqs[obj->port]);
+    if (obj->pin > 15) {
+        NVIC_DisableIRQ(gpio_high_irqs[obj->port]);
+    } else {
+        NVIC_DisableIRQ(gpio_low_irqs[obj->port]);
+    }
 }
 
 #endif
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_IMX/lp_ticker.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_IMX/lp_ticker.c
index e4f79853e7d..57001798df3 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_IMX/lp_ticker.c
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_IMX/lp_ticker.c
@@ -52,6 +52,7 @@ void lp_ticker_init(void)
         gptConfig.clockSource = kGPT_ClockSource_LowFreq;
         gptConfig.enableFreeRun = true;
         gptConfig.enableMode = false;
+        gptConfig.enableRunInDoze = true;
 
         GPT_Init(GPT2, &gptConfig);
         GPT_EnableInterrupts(GPT2, kGPT_OutputCompare1InterruptEnable);
@@ -114,7 +115,8 @@ void lp_ticker_clear_interrupt(void)
 
 void lp_ticker_free(void)
 {
-
+    GPT_DisableInterrupts(GPT2, kGPT_OutputCompare1InterruptEnable);
+    NVIC_DisableIRQ(GPT2_IRQn);
 }
 
 #endif /* DEVICE_LPTICKER */
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_IMX/objects.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_IMX/objects.h
index f451465d4de..419199b9028 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_IMX/objects.h
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_IMX/objects.h
@@ -66,6 +66,12 @@ struct trng_s {
     uint8_t dummy;
 };
 
+#if DEVICE_FLASH
+struct flash_s {
+    uint8_t dummy;
+};
+#endif
+
 #include "gpio_object.h"
 
 #ifdef __cplusplus
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_IMX/serial_api.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_IMX/serial_api.c
index 0fc649eb18b..32199ca8f5c 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_IMX/serial_api.c
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_IMX/serial_api.c
@@ -29,7 +29,8 @@
 #include "PeripheralPins.h"
 #include "fsl_clock_config.h"
 
-static uint32_t serial_irq_ids[FSL_FEATURE_SOC_LPUART_COUNT] = {0};
+/* LPUART starts from index 1 */
+static uint32_t serial_irq_ids[FSL_FEATURE_SOC_LPUART_COUNT + 1] = {0};
 static uart_irq_handler irq_handler;
 /* Array of UART peripheral base address. */
 static LPUART_Type *const uart_addrs[] = LPUART_BASE_PTRS;
@@ -320,28 +321,28 @@ static int serial_is_enabled(uint32_t uart_index)
 {
     int clock_enabled = 0;
     switch (uart_index) {
-        case 0:
+        case 1:
             clock_enabled = (CCM->CCGR5 & CCM_CCGR5_CG12_MASK) >> CCM_CCGR5_CG12_SHIFT;
             break;
-        case 1:
+        case 2:
             clock_enabled = (CCM->CCGR0 & CCM_CCGR0_CG14_MASK) >> CCM_CCGR0_CG14_SHIFT;
             break;
-        case 2:
+        case 3:
             clock_enabled = (CCM->CCGR0 & CCM_CCGR0_CG6_MASK) >> CCM_CCGR0_CG6_SHIFT;
             break;
-        case 3:
+        case 4:
             clock_enabled = (CCM->CCGR1 & CCM_CCGR1_CG12_MASK) >> CCM_CCGR1_CG12_SHIFT;
             break;
-        case 4:
+        case 5:
             clock_enabled = (CCM->CCGR3 & CCM_CCGR3_CG1_MASK) >> CCM_CCGR3_CG1_SHIFT;
             break;
-        case 5:
+        case 6:
             clock_enabled = (CCM->CCGR3 & CCM_CCGR3_CG3_MASK) >> CCM_CCGR3_CG3_SHIFT;
             break;
-        case 6:
+        case 7:
             clock_enabled = (CCM->CCGR5 & CCM_CCGR5_CG13_MASK) >> CCM_CCGR5_CG13_SHIFT;
             break;
-        case 7:
+        case 8:
             clock_enabled = (CCM->CCGR6 & CCM_CCGR6_CG7_MASK) >> CCM_CCGR6_CG7_SHIFT;
             break;
         default:
@@ -357,7 +358,8 @@ bool serial_check_tx_ongoing()
     int i;
     bool uart_tx_ongoing = false;
 
-    for (i = 0; i < FSL_FEATURE_SOC_LPUART_COUNT; i++) {
+    /* The first LPUART instance number is 1 */
+    for (i = 1; i <= FSL_FEATURE_SOC_LPUART_COUNT; i++) {
         /* First check if UART is enabled */
         if (!serial_is_enabled(i)) {
             /* UART is not enabled, check the next instance */
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_IMX/sleep.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_IMX/sleep.c
index 86e9ee45006..310e96086e9 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_IMX/sleep.c
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_IMX/sleep.c
@@ -23,13 +23,9 @@ extern bool serial_check_tx_ongoing();
 
 void hal_sleep(void)
 {
-    vPortPRE_SLEEP_PROCESSING(kCLOCK_ModeWait);
-
     __DSB();
     __WFI();
     __ISB();
-
-    vPortPOST_SLEEP_PROCESSING(kCLOCK_ModeWait);
 }
 
 void hal_deepsleep(void)
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_IMX/spi_api.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_IMX/spi_api.c
old mode 100644
new mode 100755
index 0d7a7921137..69417e0b055
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_IMX/spi_api.c
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_IMX/spi_api.c
@@ -123,16 +123,21 @@ int spi_master_write(spi_t *obj, int value)
 int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length,
                            char *rx_buffer, int rx_length, char write_fill) {
     int total = (tx_length > rx_length) ? tx_length : rx_length;
+    int ret;
 
     // Default write is done in each and every call, in future can create HAL API instead
     LPSPI_SetDummyData(spi_address[obj->instance], write_fill);
 
-    LPSPI_MasterTransferBlocking(spi_address[obj->instance], &(lpspi_transfer_t){
-          .txData = (uint8_t *)tx_buffer,
-          .rxData = (uint8_t *)rx_buffer,
-          .dataSize = total,
-          .configFlags = kLPSPI_MasterPcs0 | kLPSPI_MasterPcsContinuous | kLPSPI_SlaveByteSwap,
-    });
+    do
+    {
+        ret = LPSPI_MasterTransferBlocking(spi_address[obj->instance], &(lpspi_transfer_t){
+                .txData = (uint8_t *)tx_buffer,
+                .rxData = (uint8_t *)rx_buffer,
+                .dataSize = total,
+                .configFlags = kLPSPI_MasterPcs0 | kLPSPI_MasterPcsContinuous | kLPSPI_SlaveByteSwap,
+        });
+
+    } while((ret == kStatus_LPSPI_Busy));
 
     return total;
 }
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_IMX/us_ticker.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_IMX/us_ticker.c
index 7341fcee108..66620b9805d 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_IMX/us_ticker.c
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_IMX/us_ticker.c
@@ -50,18 +50,18 @@ void us_ticker_init(void)
 {
     /* Common for ticker/timer. */
     uint32_t busClock;
-    /* Structure to initialize PIT. */
-    pit_config_t pitConfig;
 
     us_ticker_setup_clock();
 
-    PIT_GetDefaultConfig(&pitConfig);
-    PIT_Init(PIT, &pitConfig);
-
     busClock = us_ticker_get_clock();
 
     /* Let the timer to count if re-init. */
     if (!us_ticker_inited) {
+        /* Structure to initialize PIT. */
+        pit_config_t pitConfig;
+
+        PIT_GetDefaultConfig(&pitConfig);
+        PIT_Init(PIT, &pitConfig);
 
         PIT_SetTimerPeriod(PIT, kPIT_Chnl_0, busClock / 1000000 - 1);
         PIT_SetTimerPeriod(PIT, kPIT_Chnl_1, 0xFFFFFFFF);
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_IMX/watchdog_api.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_IMX/watchdog_api.c
new file mode 100644
index 00000000000..390b0b332d8
--- /dev/null
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_IMX/watchdog_api.c
@@ -0,0 +1,90 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2020 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "watchdog_api.h"
+
+#if DEVICE_WATCHDOG
+
+#include "reset_reason_api.h"
+#include "fsl_rtwdog.h"
+#include "fsl_clock.h"
+#include "platform/mbed_wait_api.h"
+
+// Platform specific watchdog definitions
+#define LPO_CLOCK_FREQUENCY 32768
+#define MAX_TIMEOUT         0xFFFFUL
+#define DELAY_TIME          100000U
+
+// Number of decrements in the timeout register per millisecond
+#define TICKS_PER_MS ((LPO_CLOCK_FREQUENCY) / 1000)
+
+// Maximum timeout that can be specified in milliseconds
+#define MAX_TIMEOUT_MS ((MAX_TIMEOUT) / (TICKS_PER_MS))
+
+watchdog_status_t hal_watchdog_init(const watchdog_config_t *config)
+{
+    uint32_t temp;
+    rtwdog_config_t cfg;
+
+    /* When system is boot up, WDOG32 is disabled. We must wait for at least 2.5
+     * periods of wdog32 clock to reconfigure wodg32. So Delay a while to wait for
+     * the previous configuration taking effect. */
+    for (temp = 0; temp < DELAY_TIME; temp++) {
+        __NOP();
+    }
+
+    RTWDOG_GetDefaultConfig(&cfg);
+
+    cfg.workMode.enableStop = true;
+    cfg.workMode.enableDebug = true;
+    cfg.timeoutValue = (TICKS_PER_MS * config->timeout_ms);
+
+    RTWDOG_Init(RTWDOG, &cfg);
+
+    return WATCHDOG_STATUS_OK;
+}
+
+void hal_watchdog_kick(void)
+{
+    RTWDOG_Refresh(RTWDOG);
+}
+
+watchdog_status_t hal_watchdog_stop(void)
+{
+    RTWDOG_Deinit(RTWDOG);
+
+    return WATCHDOG_STATUS_OK;
+}
+
+uint32_t hal_watchdog_get_reload_value(void)
+{
+    const uint32_t timeout = RTWDOG->TOVAL;
+
+    return (timeout / TICKS_PER_MS);
+}
+
+watchdog_features_t hal_watchdog_get_platform_features(void)
+{
+    watchdog_features_t features;
+    features.max_timeout = MAX_TIMEOUT_MS;
+    features.update_config = true;
+    features.disable_watchdog = true;
+    features.clock_typical_frequency = 32000;
+    features.clock_max_frequency = 32768;
+
+    return features;
+}
+
+#endif // DEVICE_WATCHDOG
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/PeripheralNames.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/PeripheralNames.h
index 93dce23ac97..ab35ab2f6d7 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/PeripheralNames.h
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/PeripheralNames.h
@@ -131,6 +131,7 @@ typedef enum {
     SPI_1 = 1,
     SPI_2 = 2,
     SPI_3 = 3,
+    SPI_4 = 4,
 } SPIName;
 
 #ifdef __cplusplus
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/PeripheralPins.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/PeripheralPins.c
index e1550413660..113e9b0d3cb 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/PeripheralPins.c
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/PeripheralPins.c
@@ -51,11 +51,13 @@ const PinMap PinMap_I2C_SCL[] = {
 /************UART***************/
 const PinMap PinMap_UART_TX[] = {
     {GPIO_AD_B0_12, UART_1, 2},
+    {GPIO_AD_B1_06, UART_3, 2},
     {NC  ,  NC    , 0}
 };
 
 const PinMap PinMap_UART_RX[] = {
     {GPIO_AD_B0_13, UART_1, 2},
+    {GPIO_AD_B1_07, UART_3, 2},
     {NC  ,  NC    , 0}
 };
 
@@ -63,24 +65,28 @@ const PinMap PinMap_UART_RX[] = {
 const PinMap PinMap_SPI_SCLK[] = {
     {GPIO_SD_B0_00, SPI_1, ((1U << DAISY_REG_VALUE_SHIFT) | (0x4F0 << DAISY_REG_SHIFT) | 4)},
     {GPIO_AD_B0_00, SPI_3, ((0U << DAISY_REG_VALUE_SHIFT) | (0x510 << DAISY_REG_SHIFT) | 7)},
+    {GPIO_B0_03,    SPI_4, ((0U << DAISY_REG_VALUE_SHIFT) | (0x520 << DAISY_REG_SHIFT) | 3)},
     {NC   , NC   , 0}
 };
 
 const PinMap PinMap_SPI_MOSI[] = {
     {GPIO_SD_B0_02, SPI_1, ((1U << DAISY_REG_VALUE_SHIFT) | (0x4F8 << DAISY_REG_SHIFT) | 4)},
     {GPIO_AD_B0_01, SPI_3, ((0U << DAISY_REG_VALUE_SHIFT) | (0x518 << DAISY_REG_SHIFT) | 7)},
+    {GPIO_B0_02,    SPI_4, ((0U << DAISY_REG_VALUE_SHIFT) | (0x528 << DAISY_REG_SHIFT) | 3)},
     {NC   , NC   , 0}
 };
 
 const PinMap PinMap_SPI_MISO[] = {
     {GPIO_SD_B0_03, SPI_1, ((1U << DAISY_REG_VALUE_SHIFT) | (0x4F4 << DAISY_REG_SHIFT) | 4)},
     {GPIO_AD_B0_02, SPI_3, ((0U << DAISY_REG_VALUE_SHIFT) | (0x514 << DAISY_REG_SHIFT) | 7)},
+    {GPIO_B0_01,    SPI_4, ((0U << DAISY_REG_VALUE_SHIFT) | (0x524 << DAISY_REG_SHIFT) | 3)},
     {NC   , NC   , 0}
 };
 
 const PinMap PinMap_SPI_SSEL[] = {
     {GPIO_SD_B0_01, SPI_1, ((0U << DAISY_REG_VALUE_SHIFT) | (0x4EC << DAISY_REG_SHIFT) | 4)},
     {GPIO_AD_B0_03, SPI_3, ((0U << DAISY_REG_VALUE_SHIFT) | (0x50C << DAISY_REG_SHIFT) | 7)},
+    {GPIO_B0_00,    SPI_4, ((0U << DAISY_REG_VALUE_SHIFT) | (0x51C << DAISY_REG_SHIFT) | 3)},
     {NC   , NC   , 0}
 };
 
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/PinNames.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/PinNames.h
index 8422b634a0e..69ab20bb190 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/PinNames.h
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/PinNames.h
@@ -205,7 +205,7 @@ typedef enum {
 
     I2C_SCL = A5,
     I2C_SDA = A4,
-	
+
     // Not connected
     NC = (int)0xFFFFFFFF
 } PinName;
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/device.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/device.h
index 1ef61d14a3b..d2a7b696b08 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/device.h
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/device.h
@@ -19,7 +19,25 @@
 #define MBED_DEVICE_H
 
 #define DEVICE_ID_LENGTH       24
-#define BOARD_FLASH_SIZE       (0x4000000U)
+
+#ifdef HYPERFLASH_BOOT
+/* 64MB HyperFlash, 4MB reserved for mbed-os */
+#define BOARD_FLASH_SIZE             (0x4000000U)
+#define BOARD_FLASH_START_ADDR       (0x60000000U)
+#define BOARD_FLASHIAP_SIZE          (0x3C00000U)
+#define BOARD_FLASHIAP_START_ADDR    (0x60400000U)
+#define BOARD_FLASH_PAGE_SIZE        (512)
+#define BOARD_FLASH_SECTOR_SIZE      (262144)
+#else
+/* 8MB QSPI Flash, 64KB reserved for mbed_bootloader */
+#define BOARD_FLASH_SIZE             (0x800000U)
+#define BOARD_FLASH_START_ADDR       (0x60000000U)
+#define BOARD_FLASHIAP_SIZE          (0x7F0000U)
+#define BOARD_FLASHIAP_START_ADDR    (0x60010000U)
+#define BOARD_FLASH_PAGE_SIZE        (256)
+#define BOARD_FLASH_SECTOR_SIZE      (4096)
+#endif
+
 #define BOARD_ENET_PHY_ADDR    (2)
 
 #include "objects.h"
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/flash_defines.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/flash_defines.h
new file mode 100644
index 00000000000..656b80d7f50
--- /dev/null
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/flash_defines.h
@@ -0,0 +1,288 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2019 ARM Limited
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef _NXP_FLASH_DEFINES_H_
+#define _NXP_FLASH_DEFINES_H_
+
+#include "fsl_common.h"
+
+#ifdef HYPERFLASH_BOOT /* 64MB Hyperflash */
+#define HYPERFLASH_CMD_LUT_SEQ_IDX_READDATA 0
+#define HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEDATA 1
+#define HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS 2
+#define HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE 4
+#define HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR 6
+#define HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM 10
+#define HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP 12
+#define CUSTOM_LUT_LENGTH 64
+
+static uint32_t customLUT[CUSTOM_LUT_LENGTH] = {
+    /* Read Data */
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READDATA] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xA0, kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x18),
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READDATA + 1] = FLEXSPI_LUT_SEQ(
+        kFLEXSPI_Command_CADDR_DDR, kFLEXSPI_8PAD, 0x10, kFLEXSPI_Command_READ_DDR, kFLEXSPI_8PAD, 0x04),
+
+    /* Write Data */
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEDATA] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x20, kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x18),
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEDATA + 1] = FLEXSPI_LUT_SEQ(
+        kFLEXSPI_Command_CADDR_DDR, kFLEXSPI_8PAD, 0x10, kFLEXSPI_Command_WRITE_DDR, kFLEXSPI_8PAD, 0x02),
+    /* Read Status */
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00),
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS + 1] = FLEXSPI_LUT_SEQ(
+        kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA), // ADDR 0x555
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS + 2] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05),
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS + 3] = FLEXSPI_LUT_SEQ(
+        kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x70), // DATA 0x70
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS + 4] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xA0, kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x18),
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS + 5] = FLEXSPI_LUT_SEQ(
+        kFLEXSPI_Command_CADDR_DDR, kFLEXSPI_8PAD, 0x10, kFLEXSPI_Command_DUMMY_RWDS_DDR, kFLEXSPI_8PAD, 0x0B),
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS + 6] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_READ_DDR, kFLEXSPI_8PAD, 0x04, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x0),
+
+    /* Write Enable */
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00),
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE + 1] = FLEXSPI_LUT_SEQ(
+        kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA), // ADDR 0x555
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE + 2] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05),
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE + 3] = FLEXSPI_LUT_SEQ(
+        kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA), // DATA 0xAA
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE + 4] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00),
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE + 5] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x55),
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE + 6] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x02),
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE + 7] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x55),
+
+    /* Erase Sector  */
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00),
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 1] = FLEXSPI_LUT_SEQ(
+        kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA), // ADDR 0x555
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 2] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05),
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 3] = FLEXSPI_LUT_SEQ(
+        kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x80), // DATA 0x80
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 4] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00),
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 5] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA),
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 6] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05),
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 7] = FLEXSPI_LUT_SEQ(
+        kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA), // ADDR 0x555
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 8] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00),
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 9] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x55),
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 10] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x02),
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 11] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x55),
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 12] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x18),
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 13] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_CADDR_DDR, kFLEXSPI_8PAD, 0x10, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00),
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 14] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x30, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x00),
+
+    /* program page */
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00),
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM + 1] = FLEXSPI_LUT_SEQ(
+        kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA), // ADDR 0x555
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM + 2] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05),
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM + 3] = FLEXSPI_LUT_SEQ(
+        kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xA0), // DATA 0xA0
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM + 4] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x18),
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM + 5] = FLEXSPI_LUT_SEQ(
+        kFLEXSPI_Command_CADDR_DDR, kFLEXSPI_8PAD, 0x10, kFLEXSPI_Command_WRITE_DDR, kFLEXSPI_8PAD, 0x80),
+
+    /* Erase chip */
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00),
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 1] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA),
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 2] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05),
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 3] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x80),
+    // 1
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 4] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00),
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 5] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA),
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 6] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05),
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 7] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA),
+    // 2
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 8] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00),
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 9] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x55),
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 10] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x02),
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 11] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x55),
+    // 3
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 12] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00),
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 13] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA),
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 14] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05),
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 15] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x10),
+};
+
+flexspi_device_config_t deviceconfig = {
+    .flexspiRootClk       = 42000000, /* 42MHZ SPI serial clock */
+    .isSck2Enabled        = false,
+    .flashSize            = (BOARD_FLASH_SIZE/1024),
+    .CSIntervalUnit       = kFLEXSPI_CsIntervalUnit1SckCycle,
+    .CSInterval           = 2,
+    .CSHoldTime           = 0,
+    .CSSetupTime          = 3,
+    .dataValidTime        = 1,
+    .columnspace          = 3,
+    .enableWordAddress    = true,
+    .AWRSeqIndex          = HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEDATA,
+    .AWRSeqNumber         = 1,
+    .ARDSeqIndex          = HYPERFLASH_CMD_LUT_SEQ_IDX_READDATA,
+    .ARDSeqNumber         = 1,
+    .AHBWriteWaitUnit     = kFLEXSPI_AhbWriteWaitUnit2AhbCycle,
+    .AHBWriteWaitInterval = 20,
+};
+#else /* 8MB QSPI flash */
+
+#define NOR_CMD_LUT_SEQ_IDX_READ_NORMAL 7
+#define NOR_CMD_LUT_SEQ_IDX_READ_FAST 13
+#define NOR_CMD_LUT_SEQ_IDX_READ_FAST_QUAD 0
+#define NOR_CMD_LUT_SEQ_IDX_READSTATUS 1
+#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE 2
+#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 3
+#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_SINGLE 6
+#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_QUAD 4
+#define NOR_CMD_LUT_SEQ_IDX_READID 8
+#define NOR_CMD_LUT_SEQ_IDX_WRITESTATUSREG 9
+#define NOR_CMD_LUT_SEQ_IDX_ENTERQPI 10
+#define NOR_CMD_LUT_SEQ_IDX_EXITQPI 11
+#define NOR_CMD_LUT_SEQ_IDX_READSTATUSREG 12
+#define NOR_CMD_LUT_SEQ_IDX_ERASECHIP 5
+#define CUSTOM_LUT_LENGTH 60
+#define FLASH_QUAD_ENABLE 0x40
+#define FLASH_BUSY_STATUS_POL 1
+#define FLASH_BUSY_STATUS_OFFSET 0
+
+static uint32_t customLUT[CUSTOM_LUT_LENGTH] = {
+    /* Normal read mode -SDR */
+    [4 * NOR_CMD_LUT_SEQ_IDX_READ_NORMAL] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x03, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x18),
+    [4 * NOR_CMD_LUT_SEQ_IDX_READ_NORMAL + 1] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x04, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0),
+
+    /* Fast read mode - SDR */
+    [4 * NOR_CMD_LUT_SEQ_IDX_READ_FAST] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x0B, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x18),
+    [4 * NOR_CMD_LUT_SEQ_IDX_READ_FAST + 1] = FLEXSPI_LUT_SEQ(
+        kFLEXSPI_Command_DUMMY_SDR, kFLEXSPI_1PAD, 0x08, kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x04),
+
+    /* Fast read quad mode - SDR */
+    [4 * NOR_CMD_LUT_SEQ_IDX_READ_FAST_QUAD] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0xEB, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_4PAD, 0x18),
+    [4 * NOR_CMD_LUT_SEQ_IDX_READ_FAST_QUAD + 1] = FLEXSPI_LUT_SEQ(
+        kFLEXSPI_Command_DUMMY_SDR, kFLEXSPI_4PAD, 0x06, kFLEXSPI_Command_READ_SDR, kFLEXSPI_4PAD, 0x04),
+
+    /* Read extend parameters */
+    [4 * NOR_CMD_LUT_SEQ_IDX_READSTATUS] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x81, kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x04),
+
+    /* Write Enable */
+    [4 * NOR_CMD_LUT_SEQ_IDX_WRITEENABLE] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x06, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0),
+
+    /* Erase Sector  */
+    [4 * NOR_CMD_LUT_SEQ_IDX_ERASESECTOR] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x20, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x18),
+
+    /* Page Program - single mode */
+    [4 * NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_SINGLE] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x02, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x18),
+    [4 * NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_SINGLE + 1] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_1PAD, 0x04, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0),
+
+    /* Page Program - quad mode */
+    [4 * NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_QUAD] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x32, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x18),
+    [4 * NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_QUAD + 1] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_4PAD, 0x04, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0),
+
+    /* Read ID */
+    [4 * NOR_CMD_LUT_SEQ_IDX_READID] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x9F, kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x04),
+
+    /* Enable Quad mode */
+    [4 * NOR_CMD_LUT_SEQ_IDX_WRITESTATUSREG] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x01, kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_1PAD, 0x04),
+
+    /* Enter QPI mode */
+    [4 * NOR_CMD_LUT_SEQ_IDX_ENTERQPI] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x35, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0),
+
+    /* Exit QPI mode */
+    [4 * NOR_CMD_LUT_SEQ_IDX_EXITQPI] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_4PAD, 0xF5, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0),
+
+    /* Read status register */
+    [4 * NOR_CMD_LUT_SEQ_IDX_READSTATUSREG] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x05, kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x04),
+
+    /* Erase whole chip */
+    [4 * NOR_CMD_LUT_SEQ_IDX_ERASECHIP] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0xC7, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0),
+};
+
+flexspi_device_config_t deviceconfig = {
+    .flexspiRootClk       = 120000000,
+    .flashSize            = (BOARD_FLASH_SIZE/1024),
+    .CSIntervalUnit       = kFLEXSPI_CsIntervalUnit1SckCycle,
+    .CSInterval           = 2,
+    .CSHoldTime           = 3,
+    .CSSetupTime          = 3,
+    .dataValidTime        = 0,
+    .columnspace          = 0,
+    .enableWordAddress    = 0,
+    .AWRSeqIndex          = 0,
+    .AWRSeqNumber         = 0,
+    .ARDSeqIndex          = NOR_CMD_LUT_SEQ_IDX_READ_FAST_QUAD,
+    .ARDSeqNumber         = 1,
+    .AHBWriteWaitUnit     = kFLEXSPI_AhbWriteWaitUnit2AhbCycle,
+    .AHBWriteWaitInterval = 0,
+};
+
+#endif /* HYPERFLASH_BOOT */
+#endif /* _NXP_FLASH_DEFINES_H_ */
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/fsl_clock_config.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/fsl_clock_config.c
index 743522f0a47..d9a1fb3c93e 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/fsl_clock_config.c
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/fsl_clock_config.c
@@ -1,35 +1,10 @@
 /*
- * The Clear BSD License
- * Copyright 2017 NXP
+ * Copyright 2017-2019 NXP
  * All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
+
 /*
  * How to setup clock using clock driver functions:
  *
@@ -47,7 +22,7 @@
 
 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
 !!GlobalInfo
-product: Clocks v4.1
+product: Clocks v5.0
 processor: MIMXRT1052xxxxB
 package_id: MIMXRT1052DVL6B
 mcu_data: ksdk2_0
@@ -56,6 +31,7 @@ board: IMXRT1050-EVKB
  * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
 
 #include "fsl_clock_config.h"
+#include "fsl_iomuxc.h"
 
 /*******************************************************************************
  * Definitions
@@ -87,22 +63,34 @@ called_from_default_init: true
 - {id: CAN_CLK_ROOT.outFreq, value: 40 MHz}
 - {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz}
 - {id: CLK_1M.outFreq, value: 1 MHz}
+- {id: CLK_24M.outFreq, value: 24 MHz}
 - {id: CSI_CLK_ROOT.outFreq, value: 12 MHz}
+- {id: ENET1_TX_CLK.outFreq, value: 2.4 MHz}
 - {id: ENET_125M_CLK.outFreq, value: 2.4 MHz}
 - {id: ENET_25M_REF_CLK.outFreq, value: 1.2 MHz}
 - {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz}
 - {id: FLEXIO2_CLK_ROOT.outFreq, value: 30 MHz}
-- {id: FLEXSPI_CLK_ROOT.outFreq, value: 37.5 MHz}
+- {id: FLEXSPI_CLK_ROOT.outFreq, value: 160 MHz}
+- {id: GPT1_ipg_clk_highfreq.outFreq, value: 75 MHz}
+- {id: GPT2_ipg_clk_highfreq.outFreq, value: 75 MHz}
 - {id: IPG_CLK_ROOT.outFreq, value: 150 MHz}
 - {id: LCDIF_CLK_ROOT.outFreq, value: 67.5 MHz}
 - {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz}
 - {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz}
 - {id: LVDS1_CLK.outFreq, value: 1.2 GHz}
+- {id: MQS_MCLK.outFreq, value: 1080/17 MHz}
 - {id: PERCLK_CLK_ROOT.outFreq, value: 75 MHz}
 - {id: PLL7_MAIN_CLK.outFreq, value: 24 MHz}
 - {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz}
+- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz}
+- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz}
+- {id: SAI1_MCLK3.outFreq, value: 30 MHz}
 - {id: SAI2_CLK_ROOT.outFreq, value: 1080/17 MHz}
+- {id: SAI2_MCLK1.outFreq, value: 1080/17 MHz}
+- {id: SAI2_MCLK3.outFreq, value: 30 MHz}
 - {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz}
+- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz}
+- {id: SAI3_MCLK3.outFreq, value: 30 MHz}
 - {id: SEMC_CLK_ROOT.outFreq, value: 75 MHz}
 - {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz}
 - {id: TRACE_CLK_ROOT.outFreq, value: 352/3 MHz}
@@ -112,6 +100,8 @@ called_from_default_init: true
 settings:
 - {id: CCM.AHB_PODF.scale, value: '1', locked: true}
 - {id: CCM.ARM_PODF.scale, value: '2', locked: true}
+- {id: CCM.FLEXSPI_PODF.scale, value: '3', locked: true}
+- {id: CCM.FLEXSPI_SEL.sel, value: CCM.PLL3_SW_CLK_SEL}
 - {id: CCM.LPSPI_PODF.scale, value: '5', locked: true}
 - {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
 - {id: CCM.SEMC_PODF.scale, value: '8'}
@@ -128,6 +118,8 @@ called_from_default_init: true
 - {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3}
 - {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3}
 - {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0}
+- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '33', locked: true}
+- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true}
 - {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1}
 - {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2}
 - {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3}
@@ -136,6 +128,7 @@ called_from_default_init: true
 - {id: CCM_ANALOG.PLL5.denom, value: '1'}
 - {id: CCM_ANALOG.PLL5.div, value: '40'}
 - {id: CCM_ANALOG.PLL5.num, value: '0'}
+- {id: CCM_ANALOG_PLL_ENET_POWERDOWN_CFG, value: 'Yes'}
 - {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'}
 sources:
 - {id: XTALOSC24M.OSC.outFreq, value: 24 MHz, enabled: true}
@@ -146,15 +139,18 @@ called_from_default_init: true
  * Variables for BOARD_BootClockRUN configuration
  ******************************************************************************/
 const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN = {
-    .loopDivider = 100, /* PLL loop divider, Fout = Fin * 50 */
+    .loopDivider = 88, /* PLL loop divider, Fout = Fin * 44 */
+    .src         = 0,   /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
 };
 const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN = {
-    .loopDivider = 1,                         /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
-    .numerator = 0,                           /* 30 bit numerator of fractional loop divider */
-    .denominator = 1,                         /* 30 bit denominator of fractional loop divider */
+    .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
+    .numerator   = 0, /* 30 bit numerator of fractional loop divider */
+    .denominator = 1, /* 30 bit denominator of fractional loop divider */
+    .src         = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
 };
 const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN = {
     .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */
+    .src         = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
 };
 /*******************************************************************************
  * Code for BOARD_BootClockRUN configuration
@@ -163,61 +159,70 @@ void BOARD_BootClockRUN(void)
 {
     /* Init RTC OSC clock frequency. */
     CLOCK_SetRtcXtalFreq(32768U);
+    /* Enable 1MHz clock output. */
+    XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK;
+    /* Use free 1MHz clock output. */
+    XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK;
     /* Set XTAL 24MHz clock frequency. */
     CLOCK_SetXtalFreq(24000000U);
+    /* Enable XTAL 24MHz clock source. */
+    CLOCK_InitExternalClk(0);
+    /* Enable internal RC. */
+    CLOCK_InitRcOsc24M();
+    /* Switch clock source to external OSC. */
+    CLOCK_SwitchOsc(kCLOCK_XtalOsc);
+    /* Set Oscillator ready counter value. */
+    CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127);
     /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */
     CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */
     CLOCK_SetMux(kCLOCK_PeriphMux, 1);     /* Set PERIPH_CLK MUX to PERIPH_CLK2 */
-    /* Setting the VDD_SOC to 1.5V. It is necessary to config AHB to 600Mhz. */
-    DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x12);
+    /* Setting the VDD_SOC to 1.275V. It is necessary to config AHB to 600Mhz. */
+    DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x13);
     /* Waiting for DCDC_STS_DC_OK bit is asserted */
     while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0))
     {
     }
-    /* Init ARM PLL. */
-    CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN);
-    /* Init System PLL. */
-#ifndef SKIP_SYSCLK_INIT
-    CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN);
-#endif
-    /* Init Usb1 PLL. */
-#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
-    CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN);
-#endif
-    /* Enbale Audio PLL output. */
-    CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
-    /* Enbale Video PLL output. */
-    CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_ENABLE_MASK;
-    /* Enable ENET PLL output. */
-    CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENABLE_MASK;
-    CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK;
-    /* Set PERIPH_CLK2_PODF. */
-    CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0);
-    /* Set periph clock2 clock source. */
-    CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
-    /* Set periph clock source. */
-    CLOCK_SetMux(kCLOCK_PeriphMux, 0);
     /* Set AHB_PODF. */
     CLOCK_SetDiv(kCLOCK_AhbDiv, 0);
+    /* Disable IPG clock gate. */
+    CLOCK_DisableClock(kCLOCK_Adc1);
+    CLOCK_DisableClock(kCLOCK_Adc2);
+    CLOCK_DisableClock(kCLOCK_Xbar1);
+    CLOCK_DisableClock(kCLOCK_Xbar2);
+    CLOCK_DisableClock(kCLOCK_Xbar3);
     /* Set IPG_PODF. */
     CLOCK_SetDiv(kCLOCK_IpgDiv, 3);
     /* Set ARM_PODF. */
     CLOCK_SetDiv(kCLOCK_ArmDiv, 1);
-    /* Set preperiph clock source. */
-    CLOCK_SetMux(kCLOCK_PrePeriphMux, 3);
+    /* Set PERIPH_CLK2_PODF. */
+    CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0);
+    /* Disable PERCLK clock gate. */
+    CLOCK_DisableClock(kCLOCK_Gpt1);
+    CLOCK_DisableClock(kCLOCK_Gpt1S);
+    CLOCK_DisableClock(kCLOCK_Gpt2);
+    CLOCK_DisableClock(kCLOCK_Gpt2S);
+    CLOCK_DisableClock(kCLOCK_Pit);
     /* Set PERCLK_PODF. */
     CLOCK_SetDiv(kCLOCK_PerclkDiv, 1);
-    /* Set per clock source. */
-    CLOCK_SetMux(kCLOCK_PerclkMux, 0);
+    /* Disable USDHC1 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Usdhc1);
     /* Set USDHC1_PODF. */
     CLOCK_SetDiv(kCLOCK_Usdhc1Div, 1);
     /* Set Usdhc1 clock source. */
     CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0);
+    /* Disable USDHC2 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Usdhc2);
     /* Set USDHC2_PODF. */
     CLOCK_SetDiv(kCLOCK_Usdhc2Div, 1);
     /* Set Usdhc2 clock source. */
     CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0);
+/* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
+ * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left
+ * unchanged.
+ * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
 #ifndef SKIP_SYSCLK_INIT
+    /* Disable Semc clock gate. */
+    CLOCK_DisableClock(kCLOCK_Semc);
     /* Set SEMC_PODF. */
     CLOCK_SetDiv(kCLOCK_SemcDiv, 7);
     /* Set Semc alt clock source. */
@@ -225,72 +230,119 @@ void BOARD_BootClockRUN(void)
     /* Set Semc clock source. */
     CLOCK_SetMux(kCLOCK_SemcMux, 0);
 #endif
+/* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
+ * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left
+ * unchanged.
+ * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
 #if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
+    /* Disable Flexspi clock gate. */
+    CLOCK_DisableClock(kCLOCK_FlexSpi);
     /* Set FLEXSPI_PODF. */
-    CLOCK_SetDiv(kCLOCK_FlexspiDiv, 1);
+    CLOCK_SetDiv(kCLOCK_FlexspiDiv, 2);
     /* Set Flexspi clock source. */
-    CLOCK_SetMux(kCLOCK_FlexspiMux, 0);
+    CLOCK_SetMux(kCLOCK_FlexspiMux, 1);
 #endif
+    /* Disable CSI clock gate. */
+    CLOCK_DisableClock(kCLOCK_Csi);
     /* Set CSI_PODF. */
     CLOCK_SetDiv(kCLOCK_CsiDiv, 1);
     /* Set Csi clock source. */
     CLOCK_SetMux(kCLOCK_CsiMux, 0);
+    /* Disable LPSPI clock gate. */
+    CLOCK_DisableClock(kCLOCK_Lpspi1);
+    CLOCK_DisableClock(kCLOCK_Lpspi2);
+    CLOCK_DisableClock(kCLOCK_Lpspi3);
+    CLOCK_DisableClock(kCLOCK_Lpspi4);
     /* Set LPSPI_PODF. */
     CLOCK_SetDiv(kCLOCK_LpspiDiv, 4);
     /* Set Lpspi clock source. */
     CLOCK_SetMux(kCLOCK_LpspiMux, 2);
+    /* Disable TRACE clock gate. */
+    CLOCK_DisableClock(kCLOCK_Trace);
     /* Set TRACE_PODF. */
     CLOCK_SetDiv(kCLOCK_TraceDiv, 2);
     /* Set Trace clock source. */
     CLOCK_SetMux(kCLOCK_TraceMux, 2);
+    /* Disable SAI1 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Sai1);
     /* Set SAI1_CLK_PRED. */
     CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3);
     /* Set SAI1_CLK_PODF. */
     CLOCK_SetDiv(kCLOCK_Sai1Div, 1);
     /* Set Sai1 clock source. */
     CLOCK_SetMux(kCLOCK_Sai1Mux, 0);
+    /* Disable SAI2 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Sai2);
     /* Set SAI2_CLK_PRED. */
     CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3);
     /* Set SAI2_CLK_PODF. */
     CLOCK_SetDiv(kCLOCK_Sai2Div, 1);
     /* Set Sai2 clock source. */
     CLOCK_SetMux(kCLOCK_Sai2Mux, 0);
+    /* Disable SAI3 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Sai3);
     /* Set SAI3_CLK_PRED. */
     CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3);
     /* Set SAI3_CLK_PODF. */
     CLOCK_SetDiv(kCLOCK_Sai3Div, 1);
     /* Set Sai3 clock source. */
     CLOCK_SetMux(kCLOCK_Sai3Mux, 0);
+    /* Disable Lpi2c clock gate. */
+    CLOCK_DisableClock(kCLOCK_Lpi2c1);
+    CLOCK_DisableClock(kCLOCK_Lpi2c2);
+    CLOCK_DisableClock(kCLOCK_Lpi2c3);
     /* Set LPI2C_CLK_PODF. */
     CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0);
     /* Set Lpi2c clock source. */
     CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
+    /* Disable CAN clock gate. */
+    CLOCK_DisableClock(kCLOCK_Can1);
+    CLOCK_DisableClock(kCLOCK_Can2);
+    CLOCK_DisableClock(kCLOCK_Can1S);
+    CLOCK_DisableClock(kCLOCK_Can2S);
     /* Set CAN_CLK_PODF. */
     CLOCK_SetDiv(kCLOCK_CanDiv, 1);
     /* Set Can clock source. */
     CLOCK_SetMux(kCLOCK_CanMux, 2);
+    /* Disable UART clock gate. */
+    CLOCK_DisableClock(kCLOCK_Lpuart1);
+    CLOCK_DisableClock(kCLOCK_Lpuart2);
+    CLOCK_DisableClock(kCLOCK_Lpuart3);
+    CLOCK_DisableClock(kCLOCK_Lpuart4);
+    CLOCK_DisableClock(kCLOCK_Lpuart5);
+    CLOCK_DisableClock(kCLOCK_Lpuart6);
+    CLOCK_DisableClock(kCLOCK_Lpuart7);
+    CLOCK_DisableClock(kCLOCK_Lpuart8);
     /* Set UART_CLK_PODF. */
     CLOCK_SetDiv(kCLOCK_UartDiv, 0);
     /* Set Uart clock source. */
     CLOCK_SetMux(kCLOCK_UartMux, 0);
+    /* Disable LCDIF clock gate. */
+    CLOCK_DisableClock(kCLOCK_LcdPixel);
     /* Set LCDIF_PRED. */
     CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 1);
     /* Set LCDIF_CLK_PODF. */
     CLOCK_SetDiv(kCLOCK_LcdifDiv, 3);
     /* Set Lcdif pre clock source. */
     CLOCK_SetMux(kCLOCK_LcdifPreMux, 5);
+    /* Disable SPDIF clock gate. */
+    CLOCK_DisableClock(kCLOCK_Spdif);
     /* Set SPDIF0_CLK_PRED. */
     CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1);
     /* Set SPDIF0_CLK_PODF. */
     CLOCK_SetDiv(kCLOCK_Spdif0Div, 7);
     /* Set Spdif clock source. */
     CLOCK_SetMux(kCLOCK_SpdifMux, 3);
+    /* Disable Flexio1 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Flexio1);
     /* Set FLEXIO1_CLK_PRED. */
     CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1);
     /* Set FLEXIO1_CLK_PODF. */
     CLOCK_SetDiv(kCLOCK_Flexio1Div, 7);
     /* Set Flexio1 clock source. */
     CLOCK_SetMux(kCLOCK_Flexio1Mux, 3);
+    /* Disable Flexio2 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Flexio2);
     /* Set FLEXIO2_CLK_PRED. */
     CLOCK_SetDiv(kCLOCK_Flexio2PreDiv, 1);
     /* Set FLEXIO2_CLK_PODF. */
@@ -299,9 +351,121 @@ void BOARD_BootClockRUN(void)
     CLOCK_SetMux(kCLOCK_Flexio2Mux, 3);
     /* Set Pll3 sw clock source. */
     CLOCK_SetMux(kCLOCK_Pll3SwMux, 0);
+    /* Init ARM PLL. */
+    CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN);
+    /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
+     * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left
+     * unchanged. Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as
+     * well.*/
+#ifndef SKIP_SYSCLK_INIT
+    /* Init System PLL. */
+    CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN);
+    /* Init System pfd0. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd0, 27);
+    /* Init System pfd1. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd1, 16);
+    /* Init System pfd2. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd2, 24);
+    /* Init System pfd3. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd3, 16);
+    /* Disable pfd offset. */
+    CCM_ANALOG->PLL_SYS &= ~CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN_MASK;
+#endif
+    /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
+     * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left
+     * unchanged. Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as
+     * well.*/
+#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
+    /* Init Usb1 PLL. */
+    CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN);
+    /* Init Usb1 pfd0. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 33);
+    /* Init Usb1 pfd1. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16);
+    /* Init Usb1 pfd2. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17);
+    /* Init Usb1 pfd3. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 19);
+    /* Disable Usb1 PLL output for USBPHY1. */
+    CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK;
+#endif
+    /* DeInit Audio PLL. */
+    CLOCK_DeinitAudioPll();
+    /* Bypass Audio PLL. */
+    CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1);
+    /* Set divider for Audio PLL. */
+    CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK;
+    CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK;
+    /* Enable Audio PLL output. */
+    CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
+    /* DeInit Video PLL. */
+    CLOCK_DeinitVideoPll();
+    /* Bypass Video PLL. */
+    CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_BYPASS_MASK;
+    /* Set divider for Video PLL. */
+    CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(0);
+    /* Enable Video PLL output. */
+    CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_ENABLE_MASK;
+    /* DeInit Enet PLL. */
+    CLOCK_DeinitEnetPll();
+    /* Bypass Enet PLL. */
+    CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllEnet, 1);
+    /* Set Enet output divider. */
+    CCM_ANALOG->PLL_ENET =
+        (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_DIV_SELECT(1);
+    /* Enable Enet output. */
+    CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENABLE_MASK;
+    /* Enable Enet25M output. */
+    CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK;
+    /* DeInit Usb2 PLL. */
+    CLOCK_DeinitUsb2Pll();
+    /* Bypass Usb2 PLL. */
+    CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllUsb2, 1);
+    /* Enable Usb2 PLL output. */
+    CCM_ANALOG->PLL_USB2 |= CCM_ANALOG_PLL_USB2_ENABLE_MASK;
+    /* Set preperiph clock source. */
+    CLOCK_SetMux(kCLOCK_PrePeriphMux, 3);
+    /* Set periph clock source. */
+    CLOCK_SetMux(kCLOCK_PeriphMux, 0);
+    /* Set periph clock2 clock source. */
+    CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
+    /* Set per clock source. */
+    CLOCK_SetMux(kCLOCK_PerclkMux, 0);
     /* Set lvds1 clock source. */
     CCM_ANALOG->MISC1 =
         (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0);
+    /* Set clock out1 divider. */
+    CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0);
+    /* Set clock out1 source. */
+    CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1);
+    /* Set clock out2 divider. */
+    CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0);
+    /* Set clock out2 source. */
+    CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18);
+    /* Set clock out1 drives clock out1. */
+    CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK;
+    /* Disable clock out1. */
+    CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK;
+    /* Disable clock out2. */
+    CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK;
+    /* Set SAI1 MCLK1 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
+    /* Set SAI1 MCLK2 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0);
+    /* Set SAI1 MCLK3 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
+    /* Set SAI2 MCLK3 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0);
+    /* Set SAI3 MCLK3 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
+    /* Set MQS configuration. */
+    IOMUXC_MQSConfig(IOMUXC_GPR, kIOMUXC_MqsPwmOverSampleRate32, 0);
+    /* Set ENET Tx clock source. */
+    IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1RefClkMode, false);
+    /* Set GPT1 High frequency reference clock source. */
+    IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK;
+    /* Set GPT2 High frequency reference clock source. */
+    IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK;
     /* Set SystemCoreClock variable. */
-    SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
+    SystemCoreClock = CLOCK_GetCpuClkFreq();
 }
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/fsl_clock_config.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/fsl_clock_config.h
index ba3e33d0c0f..f213ac7e238 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/fsl_clock_config.h
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/fsl_clock_config.h
@@ -1,35 +1,10 @@
 /*
- * The Clear BSD License
- * Copyright 2017 NXP
+ * Copyright 2017-2019 NXP
  * All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
+
 #ifndef _CLOCK_CONFIG_H_
 #define _CLOCK_CONFIG_H_
 
@@ -38,9 +13,9 @@
 /*******************************************************************************
  * Definitions
  ******************************************************************************/
-#define BOARD_XTAL0_CLK_HZ                         24000000U  /*!< Board xtal0 frequency in Hz */
+#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */
 
-#define BOARD_XTAL32K_CLK_HZ                          32768U  /*!< Board xtal32k frequency in Hz */
+#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */
 /*******************************************************************************
  ************************ BOARD_InitBootClocks function ************************
  ******************************************************************************/
@@ -65,17 +40,64 @@ void BOARD_InitBootClocks(void);
 /*******************************************************************************
  * Definitions for BOARD_BootClockRUN configuration
  ******************************************************************************/
-#define BOARD_BOOTCLOCKRUN_CORE_CLOCK             600000000U  /*!< Core clock frequency: 600000000Hz */
+#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 600000000U /*!< Core clock frequency: 600000000Hz */
+
+/* Clock outputs (values are in Hz): */
+#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT 600000000UL
+#define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT 40000000UL
+#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL
+#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL
+#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL
+#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL
+#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL
+#define BOARD_BOOTCLOCKRUN_CSI_CLK_ROOT 12000000UL
+#define BOARD_BOOTCLOCKRUN_ENET1_TX_CLK 2400000UL
+#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK 2400000UL
+#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK 1200000UL
+#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL
+#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT 30000000UL
+#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 160000000UL
+#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 75000000UL
+#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 75000000UL
+#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 150000000UL
+#define BOARD_BOOTCLOCKRUN_LCDIF_CLK_ROOT 9642857UL
+#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL
+#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL
+#define BOARD_BOOTCLOCKRUN_LVDS1_CLK 1200000000UL
+#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL
+#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 75000000UL
+#define BOARD_BOOTCLOCKRUN_PLL7_MAIN_CLK 24000000UL
+#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL
+#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL
+#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 30000000UL
+#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL
+#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 75000000UL
+#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL
+#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL
+#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 117333333UL
+#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL
+#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK 0UL
+#define BOARD_BOOTCLOCKRUN_USBPHY2_CLK 0UL
+#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 198000000UL
+#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 198000000UL
 
 /*! @brief Arm PLL set for BOARD_BootClockRUN configuration.
  */
-extern const clock_arm_pll_config_t g_armPllConfig_BOARD_BootClockRUN;
+extern const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN;
 /*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration.
  */
-extern const clock_usb_pll_config_t g_usb1PllConfig_BOARD_BootClockRUN;
+extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN;
 /*! @brief Sys PLL for BOARD_BootClockRUN configuration.
  */
-extern const clock_sys_pll_config_t g_sysPllConfig_BOARD_BootClockRUN;
+extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN;
 
 /*******************************************************************************
  * API for BOARD_BootClockRUN configuration
@@ -95,4 +117,3 @@ void BOARD_BootClockRUN(void);
 #endif /* __cplusplus*/
 
 #endif /* _CLOCK_CONFIG_H_ */
-
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/fsl_phy.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/fsl_phy.c
index bbf37d84595..3b09963b5a2 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/fsl_phy.c
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/fsl_phy.c
@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
+ * Copyright 2016-2018 NXP
  * All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include "fsl_phy.h"
@@ -38,7 +12,7 @@
  ******************************************************************************/
 
 /*! @brief Defines the timeout macro. */
-#define PHY_TIMEOUT_COUNT 0x3FFFFFFU
+#define PHY_TIMEOUT_COUNT 100000
 
 /*******************************************************************************
  * Prototypes
@@ -82,7 +56,7 @@ status_t PHY_Init(ENET_Type *base, uint32_t phyAddr, uint32_t srcClock_Hz)
     while ((idReg != PHY_CONTROL_ID1) && (counter != 0))
     {
         PHY_Read(base, phyAddr, PHY_ID1_REG, &idReg);
-        counter --;
+        counter--;
     }
 
     if (!counter)
@@ -94,11 +68,10 @@ status_t PHY_Init(ENET_Type *base, uint32_t phyAddr, uint32_t srcClock_Hz)
     result = PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, PHY_BCTL_RESET_MASK);
     if (result == kStatus_Success)
     {
-
 #if defined(FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE)
         uint32_t data = 0;
         result = PHY_Read(base, phyAddr, PHY_CONTROL2_REG, &data);
-        if ( result != kStatus_Success)
+        if (result != kStatus_Success)
         {
             return result;
         }
@@ -131,16 +104,16 @@ status_t PHY_AutoNegotiation(ENET_Type *base, uint32_t phyAddr)
         if (result == kStatus_Success)
         {
             /* Check auto negotiation complete. */
-            while (counter --)
+            while (counter--)
             {
                 result = PHY_Read(base, phyAddr, PHY_BASICSTATUS_REG, &bssReg);
-                if ( result == kStatus_Success)
+                if (result == kStatus_Success)
                 {
                     PHY_Read(base, phyAddr, PHY_CONTROL1_REG, &ctlReg);
                     if (((bssReg & PHY_BSTATUS_AUTONEGCOMP_MASK) != 0) && (ctlReg & PHY_LINK_READY_MASK))
                     {
                         /* Wait a moment for Phy status stable. */
-                        for (timeDelay = 0; timeDelay < PHY_TIMEOUT_COUNT; timeDelay ++)
+                        for (timeDelay = 0; timeDelay < PHY_TIMEOUT_COUNT; timeDelay++)
                         {
                             __ASM("nop");
                         }
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/fsl_phy.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/fsl_phy.h
index 027a3453667..d4342bddb2d 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/fsl_phy.h
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/fsl_phy.h
@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
  * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
  *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 #ifndef _FSL_PHY_H_
 #define _FSL_PHY_H_
@@ -70,16 +44,16 @@
 
 /*!@brief Defines the mask flag of operation mode in control two register*/
 #define PHY_CTL2_REMOTELOOP_MASK 0x0004U    /*!< The PHY remote loopback mask. */
-#define PHY_CTL2_REFCLK_SELECT_MASK 0x0080U /*!< The PHY RMII reference clock select. */ 
+#define PHY_CTL2_REFCLK_SELECT_MASK 0x0080U /*!< The PHY RMII reference clock select. */
 #define PHY_CTL1_10HALFDUPLEX_MASK 0x0001U  /*!< The PHY 10M half duplex mask. */
 #define PHY_CTL1_100HALFDUPLEX_MASK 0x0002U /*!< The PHY 100M half duplex mask. */
 #define PHY_CTL1_10FULLDUPLEX_MASK 0x0005U  /*!< The PHY 10M full duplex mask. */
 #define PHY_CTL1_100FULLDUPLEX_MASK 0x0006U /*!< The PHY 100M full duplex mask. */
 #define PHY_CTL1_SPEEDUPLX_MASK 0x0007U     /*!< The PHY speed and duplex mask. */
 #define PHY_CTL1_ENERGYDETECT_MASK 0x10U    /*!< The PHY signal present on rx differential pair. */
-#define PHY_CTL1_LINKUP_MASK 0x100U         /*!< The PHY link up. */        
+#define PHY_CTL1_LINKUP_MASK 0x100U         /*!< The PHY link up. */
 #define PHY_LINK_READY_MASK (PHY_CTL1_ENERGYDETECT_MASK | PHY_CTL1_LINKUP_MASK)
-   
+
 /*! @brief Defines the mask flag in basic status register. */
 #define PHY_BSTATUS_LINKSTATUS_MASK 0x0004U  /*!< The PHY link status mask. */
 #define PHY_BSTATUS_AUTONEGABLE_MASK 0x0008U /*!< The PHY auto-negotiation ability mask. */
@@ -138,7 +112,7 @@ extern "C" {
  *
  *  This function initialize the SMI interface and initialize PHY.
  *  The SMI is the MII management interface between PHY and MAC, which should be
- *  firstly initialized before any other operation for PHY. The PHY initialize with auto-negotiation. 
+ *  firstly initialized before any other operation for PHY. The PHY initialize with auto-negotiation.
  *
  * @param base       ENET peripheral base address.
  * @param phyAddr    The PHY address.
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/lpm.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/lpm.c
index 35d2d4ede9a..420f15d6644 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/lpm.c
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/lpm.c
@@ -1,626 +1,449 @@
 /*
- * The Clear BSD License
  * Copyright 2017 NXP
  * All rights reserved.
  *
  *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include "lpm.h"
 #include "fsl_gpc.h"
 #include "fsl_dcdc.h"
 #include "fsl_gpt.h"
-#include "fsl_lpuart.h"
-#include "fsl_iomuxc.h"
 #include "fsl_clock_config.h"
-#include "serial_api.h"
 #include "mbed_critical.h"
 #include "cmsis.h"
+#include "specific.h"
 
 /*******************************************************************************
  * Definitions
  ******************************************************************************/
 #define LPM_GPC_IMR_NUM (sizeof(GPC->IMR) / sizeof(GPC->IMR[0]))
 
-typedef struct _lpm_clock_context
-{
-    uint32_t armDiv;
-    uint32_t ahbDiv;
-    uint32_t ipgDiv;
-    uint32_t perDiv;
-    uint32_t perSel;
-    uint32_t periphSel;
-    uint32_t preperiphSel;
-    uint32_t pfd480;
-    uint32_t pfd528;
-    uint32_t pllArm_loopdiv;
-    uint32_t pllArm;
-    uint32_t pllSys;
-    uint32_t pllUsb1;
-    uint32_t pllUsb2;
-    uint32_t pllAudio;
-    uint32_t pllVideo;
-    uint32_t pllEnet;
-    uint32_t is_valid;
-} lpm_clock_context_t;
-
 /*******************************************************************************
  * Variables
  ******************************************************************************/
 
-static lpm_clock_context_t s_clockContext;
-static uint32_t s_DllBackupValue = 0;
+uint32_t g_savedPrimask;
+GPT_Type *vPortGetGptBase(void);
+IRQn_Type vPortGetGptIrqn(void);
 
 /*******************************************************************************
  * Code
  ******************************************************************************/
-
-void BOARD_SetLPClockGate(void)
-{
-    CCM->CCGR0 = 0x0F4000C5U;
-    CCM->CCGR1 = 0x541C0000U;
-    CCM->CCGR2 = 0x00150010U;
-    CCM->CCGR3 = 0x50040130U;
-    CCM->CCGR4 = 0x00005514U;
-    CCM->CCGR5 = 0x51001105U;
-    CCM->CCGR6 = 0x005405C0U;
-}
-
-void BOARD_ResetLPClockGate(void)
+void EnableRegularLDO(void)
 {
-    CCM->CCGR0 = 0xFFFFFFFFU;
-    CCM->CCGR1 = 0xFFFFFFFFU;
-    CCM->CCGR2 = 0xFFFFFFFFU;
-    CCM->CCGR3 = 0xFFFFFFFFU;
-    CCM->CCGR4 = 0xFFFFFFFFU;
-    CCM->CCGR5 = 0xFFFFFFFFU;
-    CCM->CCGR6 = 0xFFFFFFFFU;
+    /* Enable Regular LDO 2P5 and 1P1 */
+    PMU->REG_2P5_SET = PMU_REG_2P5_ENABLE_LINREG_MASK;
+    PMU->REG_1P1_SET = PMU_REG_1P1_ENABLE_LINREG_MASK;
 }
 
-void LPM_SwitchToRcOSC(void)
+void DisableRegularLDO(void)
 {
-    /* Switch to RC-OSC */
-    XTALOSC24M->LOWPWR_CTRL_SET = XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_MASK;
-    /* Turn off XTAL-OSC */
-    CCM_ANALOG->MISC0_SET = CCM_ANALOG_MISC0_XTAL_24M_PWD_MASK; /* Power down */
-
-    /* Wait CCM operation finishes */
-    CLOCK_CCM_HANDSHAKE_WAIT();
-    /* Take some delay */
-    LPM_DELAY(40);
+    /* Disable Regular LDO 2P5 and 1P1 */
+    PMU->REG_2P5_CLR = PMU_REG_2P5_ENABLE_LINREG_MASK;
+    PMU->REG_1P1_CLR = PMU_REG_1P1_ENABLE_LINREG_MASK;
 }
 
-void LPM_SwitchToXtalOSC(void)
+void EnableWeakLDO(void)
 {
-    /* Restore XTAL-OSC and enable detector */
-    CCM_ANALOG->MISC0_CLR = CCM_ANALOG_MISC0_XTAL_24M_PWD_MASK; /* Power up */
-    while ((XTALOSC24M->LOWPWR_CTRL & XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_MASK) == 0)
-    {
-    }
-    CCM_ANALOG->MISC0_SET = CCM_ANALOG_MISC0_OSC_XTALOK_EN_MASK; /* detect freq */
-    while ((CCM_ANALOG->MISC0 & CCM_ANALOG_MISC0_OSC_XTALOK_MASK) == 0)
-    {
-    }
-    CCM_ANALOG->MISC0_CLR = CCM_ANALOG_MISC0_OSC_XTALOK_EN_MASK;
-
-    /* Switch to XTAL-OSC */
-    XTALOSC24M->LOWPWR_CTRL_CLR = XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_MASK;
-    /* Turn off XTAL-OSC detector */
-    CCM_ANALOG->MISC0_CLR = CCM_ANALOG_MISC0_OSC_XTALOK_EN_MASK;
+    /* Enable Weak LDO 2P5 and 1P1 */
+    PMU->REG_2P5_SET = PMU_REG_2P5_ENABLE_WEAK_LINREG_MASK;
+    PMU->REG_1P1_SET = PMU_REG_1P1_ENABLE_WEAK_LINREG_MASK;
 
-    /* Wait CCM operation finishes */
-    CLOCK_CCM_HANDSHAKE_WAIT();
-    /* Take some delay */
-    LPM_DELAY(40);
+    SDK_DelayAtLeastUs(40);
 }
 
-void LPM_SwitchBandgap(void)
+void DisableWeakLDO(void)
 {
-    /* Switch bandgap */
-    PMU->MISC0_SET = 0x00000004;
-    XTALOSC24M->LOWPWR_CTRL_SET = XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_MASK;
-    PMU->MISC0_SET = CCM_ANALOG_MISC0_REFTOP_PWD_MASK;
-
-    /* Wait CCM operation finishes */
-    CLOCK_CCM_HANDSHAKE_WAIT();
-    /* Take some delay */
-    LPM_DELAY(40);
+    /* Disable Weak LDO 2P5 and 1P1 */
+    PMU->REG_2P5_CLR = PMU_REG_2P5_ENABLE_WEAK_LINREG_MASK;
+    PMU->REG_1P1_CLR = PMU_REG_1P1_ENABLE_WEAK_LINREG_MASK;
 }
 
-void LPM_RestoreBandgap(void)
+void BandgapOn(void)
 {
-    /* Restore bandgap */
     /* Turn on regular bandgap and wait for stable */
-    PMU->MISC0_CLR = CCM_ANALOG_MISC0_REFTOP_PWD_MASK;
+    PMU->MISC0_CLR = PMU_MISC0_REFTOP_PWD_MASK;
     while ((PMU->MISC0 & PMU_MISC0_REFTOP_VBGUP_MASK) == 0)
     {
     }
     /* Low power band gap disable */
     XTALOSC24M->LOWPWR_CTRL_CLR = XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_MASK;
-    PMU->MISC0_CLR = 0x00000004;
-
-    /* Wait CCM operation finishes */
-    CLOCK_CCM_HANDSHAKE_WAIT();
-    /* Take some delay */
-    LPM_DELAY(40);
-}
-
-void LPM_EnableWakeupSource(uint32_t irq)
-{
-    GPC_EnableIRQ(GPC, irq);
 }
 
-void LPM_DisableWakeupSource(uint32_t irq)
+void BandgapOff(void)
 {
-    GPC_DisableIRQ(GPC, irq);
+    XTALOSC24M->LOWPWR_CTRL_SET = XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_MASK;
+    PMU->MISC0_SET              = PMU_MISC0_REFTOP_PWD_MASK;
 }
 
-/*
- * ERR007265: CCM: When improper low-power sequence is used,
- * the SoC enters low power mode before the ARM core executes WFI.
+/*!
+ * @brief Set CCM MUX node to certain value.
  *
- * Software workaround:
- * 1) Software should trigger IRQ #41 (GPR_IRQ) to be always pending
- *    by setting IOMUX_GPR1_GINT.
- * 2) Software should then unmask IRQ #41 in GPC before setting CCM
- *    Low-Power mode.
- * 3) Software should mask IRQ #41 right after CCM Low-Power mode
- *    is set (set bits 0-1 of CCM_CLPCR).
+ * @param mux   Which mux node to set, see \ref clock_mux_t.
+ * @param value Clock mux value to set, different mux has different value range.
  */
-static void LPM_SetClockMode(clock_mode_t mode, uint32_t clpcr)
+void CLOCK_SET_MUX(clock_mux_t mux, uint32_t value)
 {
-    switch (mode)
-    {
-        case kCLOCK_ModeRun:
-            CCM->CLPCR = clpcr;
-            break;
-        default:
-            LPM_EnableWakeupSource(GPR_IRQ_IRQn);
-            CCM->CLPCR = clpcr;
-            LPM_DisableWakeupSource(GPR_IRQ_IRQn);
-            break;
-    }
-}
+    uint32_t busyShift;
 
-void LPM_SwitchFlexspiClock(clock_mode_t powermode)
-{
-    while (!((FLEXSPI->STS0 & FLEXSPI_STS0_ARBIDLE_MASK) && (FLEXSPI->STS0 & FLEXSPI_STS0_SEQIDLE_MASK)))
-    {
-        ;
-    }
-    FLEXSPI->MCR0 |= FLEXSPI_MCR0_MDIS_MASK;
-    /* Disable clock gate of flexspi. */
-    CCM->CCGR6 &= (~CCM_CCGR6_CG5_MASK);
+    busyShift               = CCM_TUPLE_BUSY_SHIFT(mux);
+    CCM_TUPLE_REG(CCM, mux) = (CCM_TUPLE_REG(CCM, mux) & (~CCM_TUPLE_MASK(mux))) |
+                              (((uint32_t)((value) << CCM_TUPLE_SHIFT(mux))) & CCM_TUPLE_MASK(mux));
 
-    /* Periph_clk output will be used as SEMC clock root */
-    CLOCK_SET_MUX(kCLOCK_SemcMux, 0x0);
-    /* Set post divider for SEMC clock as 0. */
-    CLOCK_SET_DIV(kCLOCK_SemcDiv, 0x0);
+    //assert(busyShift <= CCM_NO_BUSY_WAIT);
 
-    /* Wait CCM operation finishes */
-    while (CCM->CDHIPR != 0)
+    /* Clock switch need Handshake? */
+    if (CCM_NO_BUSY_WAIT != busyShift)
+    {
+        /* Wait until CCM internal handshake finish. */
+        while (CCM->CDHIPR & (1U << busyShift))
     {
     }
-
-    /* Semc_clk_root_pre will be used as flexspi clock. */
-    CLOCK_SET_MUX(kCLOCK_FlexspiMux, 0x0);
-    /* Set divider for flexspi clock root 0. */
-    CLOCK_SET_DIV(kCLOCK_FlexspiDiv, 0x0);
-
-    /* Enable clock gate of flexspi. */
-    CCM->CCGR6 |= (CCM_CCGR6_CG5_MASK);
-
-    if (kCLOCK_ModeStop == powermode) {
-        FLEXSPI->DLLCR[0] = FLEXSPI_DLLCR_OVRDEN(1) | FLEXSPI_DLLCR_OVRDVAL(19);
-    } else {
-        FLEXSPI->DLLCR[0] = 0x79;
     }
-    FLEXSPI->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK;
-    FLEXSPI->MCR0 |= FLEXSPI_MCR0_SWRESET_MASK;
+}
 
-    while (FLEXSPI->MCR0 & FLEXSPI_MCR0_SWRESET_MASK) {
-    }
+/*!
+ * @brief Set CCM DIV node to certain value.
+ *
+ * @param divider Which div node to set, see \ref clock_div_t.
+ * @param value   Clock div value to set, different divider has different value range.
+ */
+void CLOCK_SET_DIV(clock_div_t divider, uint32_t value)
+{
+    uint32_t busyShift;
 
-    while (!((FLEXSPI->STS0 & FLEXSPI_STS0_ARBIDLE_MASK) && (FLEXSPI->STS0 & FLEXSPI_STS0_SEQIDLE_MASK))) {
-    }
+    busyShift                   = CCM_TUPLE_BUSY_SHIFT(divider);
+    CCM_TUPLE_REG(CCM, divider) = (CCM_TUPLE_REG(CCM, divider) & (~CCM_TUPLE_MASK(divider))) |
+                                  (((uint32_t)((value) << CCM_TUPLE_SHIFT(divider))) & CCM_TUPLE_MASK(divider));
 
-    /* Take some delay */
-    LPM_DELAY(40);
-}
+    //assert(busyShift <= CCM_NO_BUSY_WAIT);
 
-void LPM_RestoreFlexspiClock(void)
-{
-    while (!((FLEXSPI->STS0 & FLEXSPI_STS0_ARBIDLE_MASK) && (FLEXSPI->STS0 & FLEXSPI_STS0_SEQIDLE_MASK)))
+    /* Clock switch need Handshake? */
+    if (CCM_NO_BUSY_WAIT != busyShift)
     {
-        ;
+        /* Wait until CCM internal handshake finish. */
+        while (CCM->CDHIPR & (1U << busyShift))
+        {
+        }
     }
-    FLEXSPI->MCR0 |= FLEXSPI_MCR0_MDIS_MASK;
-    /* Disable clock gate of flexspi. */
-    CCM->CCGR6 &= (~CCM_CCGR6_CG5_MASK);
+}
 
-    /* PLL3 PFD0 will be used as flexspi clock. */
-    CLOCK_SET_MUX(kCLOCK_FlexspiMux, 0x3);
-    /* Set divider for flexspi clock root 0. */
-    CLOCK_SET_DIV(kCLOCK_FlexspiDiv, 0x0);
+void ClockSelectXtalOsc(void)
+{
+    /* Switch clock source to external OSC. */
+    CLOCK_SwitchOsc(kCLOCK_XtalOsc);
+}
 
-    /* Enable clock gate of flexspi. */
-    CCM->CCGR6 |= (CCM_CCGR6_CG5_MASK);
+void ClockSelectRcOsc(void)
+{
+    /* Switch clock source to internal RC. */
+    XTALOSC24M->LOWPWR_CTRL_SET = XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_MASK;
+}
 
-    /* PLL2 PFD2 output will be used as SEMC clock root */
-    CLOCK_SET_MUX(kCLOCK_SemcMux, 0x1);
-    /* Set post divider for SEMC clock as 1. */
-    CLOCK_SET_DIV(kCLOCK_SemcDiv, 0x1);
+void LPM_SetRunModeConfig(void)
+{
+    CCM->CLPCR &= ~(CCM_CLPCR_LPM_MASK | CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK);
+}
 
-    /* Wait CCM operation finishes */
-    while (CCM->CDHIPR != 0)
-    {
-    }
+void LPM_SetWaitModeConfig(void)
+{
+    uint32_t clpcr;
 
-    FLEXSPI->DLLCR[0] = s_DllBackupValue;
-    FLEXSPI->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK;
-    FLEXSPI->MCR0 |= FLEXSPI_MCR0_SWRESET_MASK;
-    while (FLEXSPI->MCR0 & FLEXSPI_MCR0_SWRESET_MASK)
-    {
-    }
-    while (!((FLEXSPI->STS0 & FLEXSPI_STS0_ARBIDLE_MASK) && (FLEXSPI->STS0 & FLEXSPI_STS0_SEQIDLE_MASK)))
-    {
-        ;
-    }
-    /* Take some delay */
-    LPM_DELAY(40);
+    /*
+     * ERR007265: CCM: When improper low-power sequence is used,
+     * the SoC enters low power mode before the ARM core executes WFI.
+     *
+     * Software workaround:
+     * 1) Software should trigger IRQ #41 (GPR_IRQ) to be always pending
+     *      by setting IOMUXC_GPR_GPR1_GINT.
+     * 2) Software should then unmask IRQ #41 in GPC before setting CCM
+     *      Low-Power mode.
+     * 3) Software should mask IRQ #41 right after CCM Low-Power mode
+     *      is set (set bits 0-1 of CCM_CLPCR).
+     */
+    GPC_EnableIRQ(GPC, GPR_IRQ_IRQn);
+    clpcr      = CCM->CLPCR & (~(CCM_CLPCR_LPM_MASK | CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK));
+    CCM->CLPCR = clpcr | CCM_CLPCR_LPM(kCLOCK_ModeWait) | CCM_CLPCR_MASK_SCU_IDLE_MASK | CCM_CLPCR_MASK_L2CC_IDLE_MASK |
+                 CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK | CCM_CLPCR_STBY_COUNT_MASK | CCM_CLPCR_BYPASS_LPM_HS0_MASK |
+                 CCM_CLPCR_BYPASS_LPM_HS1_MASK;
+    GPC_DisableIRQ(GPC, GPR_IRQ_IRQn);
 }
 
-void LPM_DisablePLLs(clock_mode_t powermode)
+void LPM_SetStopModeConfig(void)
 {
-    s_clockContext.pfd480 = CCM_ANALOG->PFD_480;
-    s_clockContext.pfd528 = CCM_ANALOG->PFD_528;
-    s_clockContext.pllSys = CCM_ANALOG->PLL_SYS;
-    s_clockContext.pllUsb1 = CCM_ANALOG->PLL_USB1;
-    s_clockContext.pllUsb2 = CCM_ANALOG->PLL_USB2;
-    s_clockContext.pllAudio = CCM_ANALOG->PLL_AUDIO;
-    s_clockContext.pllVideo = CCM_ANALOG->PLL_VIDEO;
-    s_clockContext.pllEnet = CCM_ANALOG->PLL_ENET;
-    s_clockContext.pllArm_loopdiv =
-        (CCM_ANALOG->PLL_ARM & CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK) >> CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT;
-    s_clockContext.pllArm = CCM_ANALOG->PLL_ARM;
-    s_clockContext.periphSel = CLOCK_GetMux(kCLOCK_PeriphMux);
-    s_clockContext.ipgDiv = CLOCK_GetDiv(kCLOCK_IpgDiv);
-    s_clockContext.ahbDiv = CLOCK_GetDiv(kCLOCK_AhbDiv);
-    s_clockContext.perSel = CLOCK_GetMux(kCLOCK_PerclkMux);
-    s_clockContext.perDiv = CLOCK_GetDiv(kCLOCK_PerclkDiv);
-    s_clockContext.preperiphSel = CLOCK_GetMux(kCLOCK_PrePeriphMux);
-    s_clockContext.armDiv = CLOCK_GetDiv(kCLOCK_ArmDiv);
-    s_clockContext.is_valid = 1;
-
-    /* Power off USB2 PLL */
-    CCM_ANALOG->PLL_USB2_SET = CCM_ANALOG_PLL_USB2_BYPASS_MASK;
-    CCM_ANALOG->PLL_USB2_CLR = CCM_ANALOG_PLL_USB2_POWER_MASK;
-    /* Power off AUDIO PLL */
-    CCM_ANALOG->PLL_AUDIO_SET = CCM_ANALOG_PLL_AUDIO_BYPASS_MASK;
-    CCM_ANALOG->PLL_AUDIO_SET = CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK;
-    /* Power off VIDEO PLL */
-    CCM_ANALOG->PLL_VIDEO_SET = CCM_ANALOG_PLL_VIDEO_BYPASS_MASK;
-    CCM_ANALOG->PLL_VIDEO_SET = CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK;
-    /* Power off ENET PLL */
-    CCM_ANALOG->PLL_ENET_SET = CCM_ANALOG_PLL_ENET_BYPASS_MASK;
-    CCM_ANALOG->PLL_ENET_SET = CCM_ANALOG_PLL_ENET_POWERDOWN_MASK;
-
-    if (kCLOCK_ModeWait == powermode) {
-        CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1);
-        CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0);
-        CLOCK_SetMux(kCLOCK_PeriphMux, 1);
-        CLOCK_SetDiv(kCLOCK_IpgDiv, 0);
-        CLOCK_SetDiv(kCLOCK_AhbDiv, 0);
-
-        /*ARM PLL as clksource*/
-        /* 24 * 88 / 2 / 8 = 132MHz */
-        CCM_ANALOG->PLL_ARM_CLR = CCM_ANALOG_PLL_ARM_POWERDOWN_MASK;
-        CCM_ANALOG->PLL_ARM_SET = CCM_ANALOG_PLL_ARM_ENABLE_MASK | CCM_ANALOG_PLL_ARM_BYPASS_MASK;
-        CCM_ANALOG->PLL_ARM_CLR = CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK;
-        CCM_ANALOG->PLL_ARM_SET = CCM_ANALOG_PLL_ARM_DIV_SELECT(88);
-        CLOCK_SetDiv(kCLOCK_ArmDiv, 7);
-        CCM_ANALOG->PLL_ARM_CLR = CCM_ANALOG_PLL_ARM_BYPASS_MASK;
-
-        /*Select ARM_PLL for pre_periph_clock */
-        CLOCK_SetMux(kCLOCK_PrePeriphMux, 3);
-        CLOCK_SetMux(kCLOCK_PeriphMux, 0);
-
-        /* SET AHB, IPG to 33MHz */
-        CLOCK_SetDiv(kCLOCK_IpgDiv, 0);
-        CLOCK_SetDiv(kCLOCK_AhbDiv, 3);
-
-        /*Set PERCLK to 33MHz*/
-        //CLOCK_SetMux(kCLOCK_PerclkMux, 0);
-        //CLOCK_SetDiv(kCLOCK_PerclkDiv, 0);
-    } else {
-        CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1);
-        CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0);
-        CLOCK_SetMux(kCLOCK_PeriphMux, 1);
-        CLOCK_SetDiv(kCLOCK_IpgDiv, 0);
-        CLOCK_SetDiv(kCLOCK_AhbDiv, 0);
-
-        /*ARM PLL as clksource*/
-        CCM_ANALOG->PLL_ARM |= CCM_ANALOG_PLL_ARM_ENABLE_MASK | CCM_ANALOG_PLL_ARM_BYPASS_MASK;
-        /* Power off ARM PLL */
-        CCM_ANALOG->PLL_ARM_SET = CCM_ANALOG_PLL_ARM_POWERDOWN_MASK;
-
-        /*Select ARM_PLL for pre_periph_clock */
-        CLOCK_SetDiv(kCLOCK_ArmDiv, 0x0);
-        CLOCK_SetMux(kCLOCK_PrePeriphMux, 0x3);
-        CLOCK_SetMux(kCLOCK_PeriphMux, 0x0);
-
-        /* SET AHB, IPG to 12MHz */
-        CLOCK_SetDiv(kCLOCK_IpgDiv, 0);
-        CLOCK_SetDiv(kCLOCK_AhbDiv, 1);
-
-        /*Set PERCLK to 12Mhz*/
-        //CLOCK_SetMux(kCLOCK_PerclkMux, 0x0);
-        //CLOCK_SetDiv(kCLOCK_PerclkDiv, 0x0);
-    }
+    uint32_t clpcr;
 
-    core_util_critical_section_enter();
-    LPM_SwitchFlexspiClock(powermode);
-    core_util_critical_section_exit();
+    /*
+     * ERR007265: CCM: When improper low-power sequence is used,
+     * the SoC enters low power mode before the ARM core executes WFI.
+     *
+     * Software workaround:
+     * 1) Software should trigger IRQ #41 (GPR_IRQ) to be always pending
+     *      by setting IOMUXC_GPR_GPR1_GINT.
+     * 2) Software should then unmask IRQ #41 in GPC before setting CCM
+     *      Low-Power mode.
+     * 3) Software should mask IRQ #41 right after CCM Low-Power mode
+     *      is set (set bits 0-1 of CCM_CLPCR).
+     */
+    GPC_EnableIRQ(GPC, GPR_IRQ_IRQn);
+    clpcr      = CCM->CLPCR & (~(CCM_CLPCR_LPM_MASK | CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK));
+    CCM->CLPCR = clpcr | CCM_CLPCR_LPM(kCLOCK_ModeStop) | CCM_CLPCR_MASK_L2CC_IDLE_MASK | CCM_CLPCR_MASK_SCU_IDLE_MASK |
+                 CCM_CLPCR_VSTBY_MASK | CCM_CLPCR_STBY_COUNT_MASK | CCM_CLPCR_SBYOS_MASK |
+                 CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK | CCM_CLPCR_BYPASS_LPM_HS0_MASK | CCM_CLPCR_BYPASS_LPM_HS1_MASK;
+    GPC_DisableIRQ(GPC, GPR_IRQ_IRQn);
+}
 
-    CLOCK_DeinitUsb1Pfd(kCLOCK_Pfd0);
-    CLOCK_DeinitUsb1Pfd(kCLOCK_Pfd1);
-    CLOCK_DeinitUsb1Pfd(kCLOCK_Pfd2);
-    CLOCK_DeinitUsb1Pfd(kCLOCK_Pfd3);
+void LPM_OverDriveRun(void)
+{
+    /* CCM Mode */
+    DCDC_BootIntoCCM(DCDC);
+    /* Connect internal the load resistor */
+    DCDC->REG1 |= DCDC_REG1_REG_RLOAD_SW_MASK;
+    /* Adjust SOC voltage to 1.275V */
+    DCDC_AdjustTargetVoltage(DCDC, 0x13, 0x1);
 
-    /* Power off USB1 PLL */
-    CCM_ANALOG->PLL_USB1_SET = CCM_ANALOG_PLL_USB1_BYPASS_MASK;
-    CCM_ANALOG->PLL_USB1_CLR = CCM_ANALOG_PLL_USB1_POWER_MASK;
+    /* Disable FET ODRIVE */
+    PMU->REG_CORE_CLR = PMU_REG_CORE_FET_ODRIVE_MASK;
+    /* Connect vdd_high_in and connect vdd_snvs_in */
+    PMU->MISC0_CLR = PMU_MISC0_DISCON_HIGH_SNVS_MASK;
 
-    CLOCK_DeinitSysPfd(kCLOCK_Pfd0);
-    CLOCK_DeinitSysPfd(kCLOCK_Pfd1);
-    CLOCK_DeinitSysPfd(kCLOCK_Pfd2);
-    CLOCK_DeinitSysPfd(kCLOCK_Pfd3);
+    BandgapOn();
+    EnableRegularLDO();
+    DisableWeakLDO();
 
-    /* When need to close PLL, we need to use bypass clock first and then power it down. */
-    /* Power off SYS PLL */
-    CCM_ANALOG->PLL_SYS_SET = CCM_ANALOG_PLL_SYS_BYPASS_MASK;
-    CCM_ANALOG->PLL_SYS_SET = CCM_ANALOG_PLL_SYS_POWERDOWN_MASK;
+    ClockSetToOverDriveRun();
+    SetRestoreClockGate();
 }
 
-void LPM_RestorePLLs(void)
+void LPM_FullSpeedRun(void)
 {
-    if (s_clockContext.is_valid)
-    {
-        /* Bypass PLL first */
-        CCM_ANALOG->PLL_USB1 = (CCM_ANALOG->PLL_USB1 & (~CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK)) |
-                               CCM_ANALOG_PLL_USB1_BYPASS_MASK;
+    /* CCM Mode */
+    DCDC_BootIntoCCM(DCDC);
+    /* Connect internal the load resistor */
+    DCDC->REG1 |= DCDC_REG1_REG_RLOAD_SW_MASK;
+    /* Adjust SOC voltage to 1.275V */
+    DCDC_AdjustTargetVoltage(DCDC, 0x13, 0x1);
 
-        CCM_ANALOG->PLL_USB1 = (CCM_ANALOG->PLL_USB1 & (~CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK)) |
-                               CCM_ANALOG_PLL_USB1_ENABLE_MASK | CCM_ANALOG_PLL_USB1_POWER_MASK |
-                               CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK;
+    /* Disable FET ODRIVE */
+    PMU->REG_CORE_CLR = PMU_REG_CORE_FET_ODRIVE_MASK;
+    /* Connect vdd_high_in and connect vdd_snvs_in */
+    PMU->MISC0_CLR = PMU_MISC0_DISCON_HIGH_SNVS_MASK;
 
-        while ((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_LOCK_MASK) == 0)
-        {
-        }
+    BandgapOn();
+    EnableRegularLDO();
+    DisableWeakLDO();
 
-        /* Disable Bypass */
-        CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_BYPASS_MASK;
+    ClockSetToFullSpeedRun();
 
-        /* Restore USB1 PLL PFD */
-        CCM_ANALOG->PFD_480 = s_clockContext.pfd480;
-        CCM_ANALOG->PFD_480_CLR = CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK;
+    /* Adjust SOC voltage to 1.15V */
+    DCDC_AdjustTargetVoltage(DCDC, 0xe, 0x1);
+}
 
-        /* Disable Usb1 PLL output for USBPHY1. */
-        CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK;
+void LPM_LowSpeedRun(void)
+{
+    /* CCM Mode */
+    DCDC_BootIntoCCM(DCDC);
+    /* Connect internal the load resistor */
+    DCDC->REG1 |= DCDC_REG1_REG_RLOAD_SW_MASK;
+    /* Adjust SOC voltage to 1.275V */
+    DCDC_AdjustTargetVoltage(DCDC, 0x13, 0x1);
 
-        /* When need to enable PLL, we need to use bypass clock first and then switch pll back. */
-        /* Power on SYS PLL and wait for locked */
-        CCM_ANALOG->PLL_SYS_SET = CCM_ANALOG_PLL_SYS_BYPASS_MASK;
-        CCM_ANALOG->PLL_SYS_CLR = CCM_ANALOG_PLL_SYS_POWERDOWN_MASK;
-        CCM_ANALOG->PLL_SYS = s_clockContext.pllSys;
+    /* Disable FET ODRIVE */
+    PMU->REG_CORE_CLR = PMU_REG_CORE_FET_ODRIVE_MASK;
+    /* Connect vdd_high_in and connect vdd_snvs_in */
+    PMU->MISC0_CLR = PMU_MISC0_DISCON_HIGH_SNVS_MASK;
 
-        while ((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_LOCK_MASK) == 0)
-        {
-        }
+    BandgapOn();
+    EnableRegularLDO();
+    DisableWeakLDO();
 
-        /* Restore SYS PLL PFD */
-        CCM_ANALOG->PFD_528 = s_clockContext.pfd528;
-        CCM_ANALOG->PFD_528_CLR = CCM_ANALOG_PFD_528_PFD2_CLKGATE_MASK;
+    ClockSetToLowSpeedRun();
 
-        core_util_critical_section_enter();
-        LPM_RestoreFlexspiClock();
-        core_util_critical_section_exit();
-    } else {
-        return;
-    }
+    /* Adjust SOC voltage to 1.15V */
+    DCDC_AdjustTargetVoltage(DCDC, 0xe, 0x1);
+}
 
-    CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
-    CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0);
-    CLOCK_SetMux(kCLOCK_PeriphMux, 1);
-    CLOCK_SetDiv(kCLOCK_IpgDiv, 0x3);
-    CLOCK_SetDiv(kCLOCK_AhbDiv, 0x0);
+void LPM_LowPowerRun(void)
+{
+    ClockSetToLowPowerRun();
 
-    /* ARM PLL as clksource*/
-    CCM_ANALOG->PLL_ARM_CLR = CCM_ANALOG_PLL_ARM_POWERDOWN_MASK;
-    CCM_ANALOG->PLL_ARM_SET = CCM_ANALOG_PLL_ARM_ENABLE_MASK | CCM_ANALOG_PLL_ARM_BYPASS_MASK;
+    /* Power down USBPHY */
+    PowerDownUSBPHY();
 
-    CLOCK_SetDiv(kCLOCK_ArmDiv, s_clockContext.armDiv);
-    CCM_ANALOG->PLL_ARM_CLR = CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK;
-    CCM_ANALOG->PLL_ARM_SET = CCM_ANALOG_PLL_ARM_DIV_SELECT(s_clockContext.pllArm_loopdiv);
-    if ((s_clockContext.pllArm & CCM_ANALOG_PLL_ARM_BYPASS_MASK) == 0)
-    {
-        while ((CCM_ANALOG->PLL_ARM & CCM_ANALOG_PLL_ARM_LOCK_MASK) == 0)
-        {
-        }
-    }
-    if ((s_clockContext.pllArm & CCM_ANALOG_PLL_ARM_BYPASS_MASK) == 0)
-    {
-        CCM_ANALOG->PLL_ARM_CLR = CCM_ANALOG_PLL_ARM_BYPASS_MASK;
-    }
+    /* Adjust SOC voltage to 0.95V */
+    DCDC_AdjustTargetVoltage(DCDC, 0x6, 0x1);
+    /* DCM Mode */
+    DCDC_BootIntoDCM(DCDC);
+    /* Disconnect internal the load resistor */
+    DCDC->REG1 &= ~DCDC_REG1_REG_RLOAD_SW_MASK;
+    /* Power Down output range comparator */
+    DCDC->REG0 |= DCDC_REG0_PWD_CMP_OFFSET_MASK;
 
-    /* Restore AHB and IPG div */
-    CCM->CBCDR = (CCM->CBCDR & ~(CCM_CBCDR_AHB_PODF_MASK | CCM_CBCDR_IPG_PODF_MASK | CCM_CBCDR_PERIPH_CLK_SEL_MASK)) |
-                 CCM_CBCDR_AHB_PODF(s_clockContext.ahbDiv) | CCM_CBCDR_IPG_PODF(s_clockContext.ipgDiv) |
-                 CCM_CBCDR_PERIPH_CLK_SEL(s_clockContext.periphSel);
+    /* Enable FET ODRIVE */
+    PMU->REG_CORE_SET = PMU_REG_CORE_FET_ODRIVE_MASK;
+    /* Connect vdd_high_in and connect vdd_snvs_in */
+    PMU->MISC0_CLR = PMU_MISC0_DISCON_HIGH_SNVS_MASK;
 
-    /* Restore Periphral clock */
-    CCM->CSCMR1 = (CCM->CSCMR1 & ~CCM_CSCMR1_PERCLK_PODF_MASK) | CCM_CSCMR1_PERCLK_PODF(s_clockContext.perDiv) |
-                  CCM_CSCMR1_PERCLK_CLK_SEL(s_clockContext.perSel);
+    EnableWeakLDO();
+    DisableRegularLDO();
+    BandgapOff();
+}
 
-    /* Switch clocks back */
-    CCM->CBCMR =
-        (CCM->CBCMR & ~CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK) | CCM_CBCMR_PRE_PERIPH_CLK_SEL(s_clockContext.preperiphSel);
+void LPM_EnterSystemIdle(void)
+{
+    LPM_SetWaitModeConfig();
+    SetLowPowerClockGate();
 
-    /* Wait CCM operation finishes */
-    while (CCM->CDHIPR != 0)
-    {
-    }
+    ClockSetToSystemIdle();
 
-    /* Restore USB2 PLL */
-    CCM_ANALOG->PLL_USB2_SET = CCM_ANALOG_PLL_USB2_BYPASS_MASK;
-    CCM_ANALOG->PLL_USB2_SET = CCM_ANALOG_PLL_USB2_POWER_MASK;
-    CCM_ANALOG->PLL_USB2 = s_clockContext.pllUsb2;
-    if ((CCM_ANALOG->PLL_USB2 & CCM_ANALOG_PLL_USB2_POWER_MASK) != 0)
-    {
-        while ((CCM_ANALOG->PLL_USB2 & CCM_ANALOG_PLL_USB2_LOCK_MASK) == 0)
-        {
-        }
-    }
+    /* Power down USBPHY */
+    PowerDownUSBPHY();
 
-    /* Restore AUDIO PLL */
-    CCM_ANALOG->PLL_AUDIO_SET = CCM_ANALOG_PLL_AUDIO_BYPASS_MASK;
-    CCM_ANALOG->PLL_AUDIO_CLR = CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK;
-    CCM_ANALOG->PLL_AUDIO = s_clockContext.pllAudio;
-    if ((CCM_ANALOG->PLL_AUDIO & CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK) == 0)
-    {
-        while ((CCM_ANALOG->PLL_AUDIO & CCM_ANALOG_PLL_AUDIO_LOCK_MASK) == 0)
-        {
-        }
-    }
+    /* DCDC to 1.15V */
+    DCDC_AdjustTargetVoltage(DCDC, 0xe, 0x1);
+    /* DCM Mode */
+    DCDC_BootIntoDCM(DCDC);
+    /* Disconnect internal the load resistor */
+    DCDC->REG1 &= ~DCDC_REG1_REG_RLOAD_SW_MASK;
+    /* Power Down output range comparator */
+    DCDC->REG0 |= DCDC_REG0_PWD_CMP_OFFSET_MASK;
 
-    /* Restore VIDEO PLL */
-    CCM_ANALOG->PLL_VIDEO_SET = CCM_ANALOG_PLL_VIDEO_BYPASS_MASK;
-    CCM_ANALOG->PLL_VIDEO_CLR = CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK;
-    CCM_ANALOG->PLL_VIDEO = s_clockContext.pllVideo;
-    if ((CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK) == 0)
-    {
-        while ((CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) == 0)
-        {
-        }
-    }
+    /* Enable FET ODRIVE */
+    PMU->REG_CORE_SET = PMU_REG_CORE_FET_ODRIVE_MASK;
+    /* Connect vdd_high_in and connect vdd_snvs_in */
+    PMU->MISC0_CLR = PMU_MISC0_DISCON_HIGH_SNVS_MASK;
 
-    /* Restore ENET PLL */
-    CCM_ANALOG->PLL_ENET_SET = CCM_ANALOG_PLL_ENET_BYPASS_MASK;
-    CCM_ANALOG->PLL_ENET_SET = CCM_ANALOG_PLL_ENET_POWERDOWN_MASK;
-    CCM_ANALOG->PLL_ENET = s_clockContext.pllEnet;
-    if ((CCM_ANALOG->PLL_ENET & CCM_ANALOG_PLL_ENET_POWERDOWN_MASK) == 0)
-    {
-        while ((CCM_ANALOG->PLL_ENET & CCM_ANALOG_PLL_ENET_LOCK_MASK) == 0)
-        {
-        }
-    }
+    EnableRegularLDO();
+    DisableWeakLDO();
+    BandgapOn();
 
-    s_clockContext.is_valid = 0;
+    PeripheralEnterDozeMode();
 }
 
-static void LPM_SystemIdle(clock_mode_t powermode)
+void LPM_ExitSystemIdle(void)
 {
-    /* Switch DCDC to use DCDC internal OSC */
-    DCDC_SetClockSource(DCDC, kDCDC_ClockInternalOsc);
-
-    /* Power down USBPHY */
-    USBPHY1->CTRL = 0xFFFFFFFF;
-    USBPHY2->CTRL = 0xFFFFFFFF;
+    PeripheralExitDozeMode();
+    LPM_SetRunModeConfig();
+}
 
-    LPM_DisablePLLs(powermode);
+void LPM_EnterLowPowerIdle(void)
+{
+    LPM_SetWaitModeConfig();
+    SetLowPowerClockGate();
 
-    /* Enable weak 2P5 and turn off regular 2P5 */
-    PMU->REG_2P5 &= ~PMU_REG_2P5_ENABLE_LINREG_MASK;
-    PMU->REG_2P5 |= PMU_REG_2P5_ENABLE_WEAK_LINREG_MASK;
+    ClockSetToLowPowerIdle();
 
-    /* Enable weak 1P1 and turn off regular 1P1 */
-    PMU->REG_1P1 &= ~PMU_REG_1P1_ENABLE_LINREG_MASK;
-    PMU->REG_1P1 |= PMU_REG_1P1_ENABLE_WEAK_LINREG_MASK;
+    /* Power down USBPHY */
+    PowerDownUSBPHY();
 
-    core_util_critical_section_enter();
-    LPM_SwitchToRcOSC();
-    core_util_critical_section_exit();
+    /* Adjust SOC voltage to 0.95V */
+    DCDC_AdjustTargetVoltage(DCDC, 0x6, 0x1);
+    /* DCM Mode */
+    DCDC_BootIntoDCM(DCDC);
+    /* Disconnect internal the load resistor */
+    DCDC->REG1 &= ~DCDC_REG1_REG_RLOAD_SW_MASK;
+    /* Power Down output range comparator */
+    DCDC->REG0 |= DCDC_REG0_PWD_CMP_OFFSET_MASK;
 
-    /* Lower OSC current by 37.5% */
-    CCM_ANALOG->MISC0_SET = CCM_ANALOG_MISC0_OSC_I_MASK;
     /* Enable FET ODRIVE */
     PMU->REG_CORE_SET = PMU_REG_CORE_FET_ODRIVE_MASK;
-    /* Disconnect vdd_high_in and connect vdd_snvs_in */
-    CCM_ANALOG->MISC0_SET = CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_MASK;
+    /* Connect vdd_high_in and connect vdd_snvs_in */
+    PMU->MISC0_CLR = PMU_MISC0_DISCON_HIGH_SNVS_MASK;
 
-    DCDC_AdjustTargetVoltage(DCDC, 0x6, 0x1);
+    EnableWeakLDO();
+    DisableRegularLDO();
+    BandgapOff();
 
-    core_util_critical_section_enter();
-    LPM_SwitchBandgap();
-    core_util_critical_section_exit();
+    PeripheralEnterDozeMode();
+}
 
-    /* RBC = 0; Enable COSC, OSC COUNT = 0xAF */
-    CCM->CCR = (CCM_CCR_COSC_EN_MASK | CCM_CCR_OSCNT(0xAF));
+void LPM_ExitLowPowerIdle(void)
+{
+    PeripheralExitDozeMode();
+    LPM_SetRunModeConfig();
 }
 
-void LPM_SystemRestoreIdle(void)
+void LPM_EnterSuspend(void)
 {
-    DCDC_AdjustTargetVoltage(DCDC, 0x12, 0x1);
+    uint32_t i;
+    uint32_t gpcIMR[LPM_GPC_IMR_NUM];
 
-    /* Switch DCDC to use DCDC internal OSC */
-    DCDC_SetClockSource(DCDC, kDCDC_ClockExternalOsc);
+    LPM_SetStopModeConfig();
+    SetLowPowerClockGate();
 
-    /* Disconnect vdd_snvs_in and connect vdd_high_in */
-    CCM_ANALOG->MISC0_CLR = CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_MASK;
-    /* Increase OSC current to normal */
-    CCM_ANALOG->MISC0_CLR = CCM_ANALOG_MISC0_OSC_I_MASK;
+    /* Disconnect internal the load resistor */
+    DCDC->REG1 &= ~DCDC_REG1_REG_RLOAD_SW_MASK;
 
-    core_util_critical_section_enter();
-    LPM_SwitchToXtalOSC();
-    LPM_RestoreBandgap();
-    core_util_critical_section_exit();
+    /* Turn off FlexRAM0 */
+    GPC->CNTR |= GPC_CNTR_PDRAM0_PGE_MASK;
+    /* Turn off FlexRAM1 */
+    PGC->MEGA_CTRL |= PGC_MEGA_CTRL_PCR_MASK;
 
-    /* Disable FET ODRIVE */
-    PMU->REG_CORE_CLR = PMU_REG_CORE_FET_ODRIVE_MASK;
+    /* Clean and disable data cache to make sure context is saved into RAM */
+    SCB_CleanDCache();
+    SCB_DisableDCache();
 
-    /* Enable regular 2P5 and wait for stable */
-    PMU->REG_2P5_SET = PMU_REG_2P5_ENABLE_LINREG_MASK;
-    while ((PMU->REG_2P5 & PMU_REG_2P5_OK_VDD2P5_MASK) == 0)
+    /* Adjust LP voltage to 0.925V */
+    DCDC_AdjustTargetVoltage(DCDC, 0x13, 0x1);
+    /* Switch DCDC to use DCDC internal OSC */
+    DCDC_SetClockSource(DCDC, kDCDC_ClockInternalOsc);
+
+    /* Power down USBPHY */
+    PowerDownUSBPHY();
+
+    /* Power down CPU when requested */
+    PGC->CPU_CTRL = PGC_CPU_CTRL_PCR_MASK;
+
+    /* Enable FET ODRIVE */
+    PMU->REG_CORE_SET = PMU_REG_CORE_FET_ODRIVE_MASK;
+    /* Connect vdd_high_in and connect vdd_snvs_in */
+    PMU->MISC0_CLR = PMU_MISC0_DISCON_HIGH_SNVS_MASK;
+    /* STOP_MODE config, turn off all analog except RTC in stop mode */
+    PMU->MISC0_CLR = PMU_MISC0_STOP_MODE_CONFIG_MASK;
+
+    /* Mask all GPC interrupts before enabling the RBC counters to
+     * avoid the counter starting too early if an interupt is already
+     * pending.
+     */
+    for (i = 0; i < LPM_GPC_IMR_NUM; i++)
     {
+        gpcIMR[i]   = GPC->IMR[i];
+        GPC->IMR[i] = 0xFFFFFFFFU;
     }
-    /* Turn off weak 2P5 */
-    PMU->REG_2P5_CLR = PMU_REG_2P5_ENABLE_WEAK_LINREG_MASK;
 
-    /* Enable regular 1P1 and wait for stable */
-    PMU->REG_1P1_SET = PMU_REG_1P1_ENABLE_LINREG_MASK;
-    while ((PMU->REG_1P1 & PMU_REG_1P1_OK_VDD1P1_MASK) == 0)
+    /*
+     * ERR006223: CCM: Failure to resuem from wait/stop mode with power gating
+     *   Configure REG_BYPASS_COUNTER to 2
+     *   Enable the RBC bypass counter here to hold off the interrupts. RBC counter
+     *  needs to be no less than 2.
+     */
+    CCM->CCR = (CCM->CCR & ~CCM_CCR_REG_BYPASS_COUNT_MASK) | CCM_CCR_REG_BYPASS_COUNT(2);
+    CCM->CCR |= (CCM_CCR_OSCNT(0xAF) | CCM_CCR_COSC_EN_MASK | CCM_CCR_RBC_EN_MASK);
+
+    /* Now delay for a short while (3usec) at this point
+     * so a short loop should be enough. This delay is required to ensure that
+     * the RBC counter can start counting in case an interrupt is already pending
+     * or in case an interrupt arrives just as ARM is about to assert DSM_request.
+     */
+    SDK_DelayAtLeastUs(3);
+
+    /* Recover all the GPC interrupts. */
+    for (i = 0; i < LPM_GPC_IMR_NUM; i++)
     {
+        GPC->IMR[i] = gpcIMR[i];
     }
-    /* Turn off weak 1P1 */
-    PMU->REG_1P1_CLR = PMU_REG_1P1_ENABLE_WEAK_LINREG_MASK;
 
-    LPM_RestorePLLs();
+    PeripheralEnterStopMode();
+}
+
+void LPM_EnterSNVS(void)
+{
+    SNVS->LPCR |= SNVS_LPCR_TOP_MASK;
+    while (1) /* Shutdown */
+    {
+    }
 }
 
 bool LPM_Init(void)
@@ -640,7 +463,7 @@ bool LPM_Init(void)
                               XTALOSC24M_OSC_CONFIG0_ENABLE_MASK;
     XTALOSC24M->OSC_CONFIG1 = XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR(0x40) | XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG(0x2DC);
     /* Take some delay */
-    LPM_DELAY(40);
+    SDK_DelayAtLeastUs(4000);
     /* Add some hysteresis */
     tmp_reg = XTALOSC24M->OSC_CONFIG0;
     tmp_reg &= ~(XTALOSC24M_OSC_CONFIG0_HYST_PLUS_MASK | XTALOSC24M_OSC_CONFIG0_HYST_MINUS_MASK);
@@ -655,13 +478,12 @@ bool LPM_Init(void)
     tmp_reg = XTALOSC24M->OSC_CONFIG1;
     XTALOSC24M->OSC_CONFIG1 = tmp_reg;
 
-    s_DllBackupValue = FLEXSPI->DLLCR[0];
-
     /* ERR007265 */
     IOMUXC_GPR->GPR1 |= IOMUXC_GPR_GPR1_GINT_MASK;
 
     /* Initialize GPC to mask all IRQs */
-    for (i = 0; i < LPM_GPC_IMR_NUM; i++) {
+    for (i = 0; i < LPM_GPC_IMR_NUM; i++)
+    {
         GPC->IMR[i] = 0xFFFFFFFFU;
     }
 
@@ -674,80 +496,39 @@ void LPM_Deinit(void)
     IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_GINT_MASK;
 }
 
-void vPortPRE_SLEEP_PROCESSING(clock_mode_t powermode)
+void LPM_EnableWakeupSource(uint32_t irq)
 {
-    uint32_t clpcr;
+    GPC_EnableIRQ(GPC, irq);
+}
 
-    clpcr = CCM->CLPCR & (~(CCM_CLPCR_LPM_MASK | CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK));
+void LPM_DisableWakeupSource(uint32_t irq)
+{
+    GPC_DisableIRQ(GPC, irq);
+}
 
-    switch (powermode)
-    {
-        case kCLOCK_ModeWait:
-#if 0
-            LPM_EnableWakeupSource(PIT_IRQn);
-
-            LPM_SetClockMode(kCLOCK_ModeWait, clpcr | CCM_CLPCR_LPM(kCLOCK_ModeWait) |
-                                              CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK | CCM_CLPCR_STBY_COUNT_MASK | 0x1C |
-                                              0x08280000);
-            IOMUXC_GPR->GPR8 = 0xaaaaaaaa;
-            IOMUXC_GPR->GPR12 = 0x0000000a;
-#endif
-            break;
-        case kCLOCK_ModeStop:
-            LPM_EnableWakeupSource(GPT2_IRQn);
-
-            LPM_SetClockMode(kCLOCK_ModeWait, clpcr | CCM_CLPCR_LPM(kCLOCK_ModeWait) |
-                                              CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK | CCM_CLPCR_STBY_COUNT_MASK | 0x1C |
-                                              0x08280000);
-            BOARD_SetLPClockGate();
-            LPM_SystemIdle(powermode);
-            IOMUXC_GPR->GPR8 = 0xaaaaaaaa;
-            IOMUXC_GPR->GPR12 = 0x0000000a;
-            break;
-        default:
-            assert(false);
-            break;
-    }
+GPT_Type *vPortGetGptBase(void)
+{
+    return GPT2;
+}
+
+IRQn_Type vPortGetGptIrqn(void)
+{
+    return GPT2_IRQn;
+}
+
+void vPortPRE_SLEEP_PROCESSING(clock_mode_t powermode)
+{
+    LPM_EnableWakeupSource(vPortGetGptIrqn());
+
+    LPM_EnterLowPowerIdle();
 }
 
 void vPortPOST_SLEEP_PROCESSING(clock_mode_t powermode)
 {
-    uint32_t clpcr;
+    LPM_ExitLowPowerIdle();
 
-    clpcr = CCM->CLPCR & (~(CCM_CLPCR_LPM_MASK | CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK));
+    LPM_OverDriveRun();
 
-    switch (powermode)
-    {
-        case kCLOCK_ModeWait:
-#if 0
-
-            IOMUXC_GPR->GPR8 = 0x00000000;
-            IOMUXC_GPR->GPR12 = 0x00000000;
-            LPM_SetClockMode(kCLOCK_ModeRun, clpcr);
-
-            LPM_DisableWakeupSource(PIT_IRQn);
-#endif
-
-            break;
-        case kCLOCK_ModeStop:
-            __NOP();
-            __NOP();
-            __NOP();
-            __NOP();
-            IOMUXC_GPR->GPR8 = 0x00000000;
-            IOMUXC_GPR->GPR12 = 0x00000000;
-            /* Interrupt occurs before system idle */
-            LPM_SystemRestoreIdle();
-            BOARD_ResetLPClockGate();
-
-            LPM_SetClockMode(kCLOCK_ModeRun, clpcr);
-
-            LPM_DisableWakeupSource(GPT2_IRQn);
-
-            break;
-        default:
-            assert(false);
-            break;
-    }
+    LPM_DisableWakeupSource(vPortGetGptIrqn());
 }
 
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/lpm.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/lpm.h
index c1b9a787447..ea20400ceec 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/lpm.h
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/lpm.h
@@ -1,127 +1,100 @@
 /*
- * The Clear BSD License
  * Copyright 2017 NXP
  * All rights reserved.
  *
  *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #ifndef _LPM_H_
 #define _LPM_H_
 
 #include "fsl_clock.h"
+#include <stdint.h>
 
 /*******************************************************************************
  * Definitions
  ******************************************************************************/
 extern void vPortGPTIsr(void);
+extern uint32_t g_savedPrimask;
 
 #define vPortGptIsr GPT1_IRQHandler
 
-#define CLOCK_SET_MUX(mux, value)                                                                        \
-    \
-do                                                                                                \
-    {                                                                                                    \
-        CCM_TUPLE_REG(CCM, mux) = (CCM_TUPLE_REG(CCM, mux) & (~CCM_TUPLE_MASK(mux))) |                   \
-                                  (((uint32_t)((value) << CCM_TUPLE_SHIFT(mux))) & CCM_TUPLE_MASK(mux)); \
-        while (CCM->CDHIPR != 0)                                                                         \
-        {                                                                                                \
-        }                                                                                                \
-    \
-}                                                                                                 \
-    while (0)
-
-#define CLOCK_SET_DIV(divider, value)                                                                                \
-    \
-do                                                                                                            \
-    {                                                                                                                \
-        CCM_TUPLE_REG(CCM, divider) = (CCM_TUPLE_REG(CCM, divider) & (~CCM_TUPLE_MASK(divider))) |                   \
-                                      (((uint32_t)((value) << CCM_TUPLE_SHIFT(divider))) & CCM_TUPLE_MASK(divider)); \
-        while (CCM->CDHIPR != 0)                                                                                     \
-        {                                                                                                            \
-        }                                                                                                            \
-    \
-}                                                                                                             \
-    while (0)
-
 #define CLOCK_CCM_HANDSHAKE_WAIT() \
-    \
-do                          \
+                                   \
+    do                             \
     {                              \
         while (CCM->CDHIPR != 0)   \
         {                          \
         }                          \
-    \
-}                           \
-    while (0)
-
-#define LPM_DELAY(value)                         \
-    \
-do                                        \
-    {                                            \
-        for (uint32_t i = 0; i < 5 * value; i++) \
-        {                                        \
-            __NOP();                             \
-        }                                        \
-    \
-}                                         \
-    while (0)
-
-#define ROM_CODE_ENTRY_ADDR (0x200000U)
-
-/*! @name Time sensitive region */
-/* @{ */
+                                   \
+    } while (0)
+
 #if defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)
-#if (defined(__ICCARM__))
-#define AT_QUICKACCESS_SECTION_CODE(func) __ramfunc func
-#elif(defined(__ARMCC_VERSION))
-#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("RamFunction"))) func
-#elif defined(__MCUXPRESSO)
-#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section(".ramfunc.$SRAM_ITC"))) func
-#elif(defined(__GNUC__))
-#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("RamFunction"))) func
-#else
-#error Toolchain not supported.
-#endif /* defined(__ICCARM__) */
-#else
-#if (defined(__ICCARM__))
-#define AT_QUICKACCESS_SECTION_CODE(func) func
-#elif(defined(__ARMCC_VERSION))
-#define AT_QUICKACCESS_SECTION_CODE(func) func
-#elif(defined(__MCUXPRESSO))
-#define AT_QUICKACCESS_SECTION_CODE(func) func
-#elif(defined(__GNUC__))
-#define AT_QUICKACCESS_SECTION_CODE(func) func
+#define LPM_EnterCritical()                        \
+                                                   \
+    do                                             \
+    {                                              \
+        g_savedPrimask = DisableGlobalIRQ();       \
+        SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; \
+                                                   \
+    } while (0)
+
+#define LPM_ExitCritical()                        \
+                                                  \
+    do                                            \
+    {                                             \
+        EnableGlobalIRQ(g_savedPrimask);          \
+        SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk; \
+                                                  \
+    } while (0)
+
 #else
-#error Toolchain not supported.
+#define LPM_EnterCritical()
+#define LPM_ExitCritical()
 #endif
-#endif /* __FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE */
+
+/* Power mode definition of low power management.
+ * Waken up duration Off > Dsm > Idle > Wait > Run.
+ */
+typedef enum _lpm_power_mode
+{
+    LPM_PowerModeOverRun = 0, /* Over RUN mode, CPU won't stop running */
+
+    LPM_PowerModeFullRun, /* Full RUN mode, CPU won't stop running */
+
+    LPM_PowerModeLowSpeedRun,
+
+    LPM_PowerModeLowPowerRun,
+
+    LPM_PowerModeRunEnd = LPM_PowerModeLowPowerRun,
+    /* In system wait mode, cpu clock is gated.
+     * All peripheral can remain active, clock gating decided by CCGR setting.
+     * DRAM enters auto-refresh mode when there is no access.
+     */
+    LPM_PowerModeSysIdle, /* System WAIT mode, also system low speed idle */
+
+    /* In low power idle mode, all PLL/PFD is off, cpu power is off.
+     * Analog modules running in low power mode.
+     * All high-speed peripherals are power gated
+     * Low speed peripherals can remain running at low frequency
+     * DRAM in self-refresh.
+     */
+    LPM_PowerModeLPIdle, /* Low Power Idle mode */
+
+    /* In deep sleep mode, all PLL/PFD is off, XTAL is off, cpu power is off.
+     * All clocks are shut off except 32K RTC clock
+     * All high-speed peripherals are power gated
+     * Low speed peripherals are clock gated
+     * DRAM in self-refresh.
+     * If RTOS is used, systick will be disabled in DSM
+     */
+    LPM_PowerModeSuspend, /* Deep Sleep mode, suspend. */
+
+    LPM_PowerModeSNVS, /* Power off mode, or shutdown mode */
+
+    LPM_PowerModeEnd = LPM_PowerModeSNVS
+} lpm_power_mode_t;
 
 /*******************************************************************************
  * API
@@ -131,8 +104,8 @@ do                                        \
 extern "C" {
 #endif /* __cplusplus*/
 
-AT_QUICKACCESS_SECTION_CODE(void LPM_SwitchFlexspiClock(clock_mode_t powermode));
-AT_QUICKACCESS_SECTION_CODE(void LPM_RestoreFlexspiClock(void));
+AT_QUICKACCESS_SECTION_CODE(void CLOCK_SET_MUX(clock_mux_t mux, uint32_t value));
+AT_QUICKACCESS_SECTION_CODE(void CLOCK_SET_DIV(clock_div_t divider, uint32_t value));
 
 /* Initialize the Low Power Management */
 bool LPM_Init(void);
@@ -146,6 +119,25 @@ void LPM_EnableWakeupSource(uint32_t irq);
 /* Disable wakeup source in low power mode */
 void LPM_DisableWakeupSource(uint32_t irq);
 
+void ClockSelectXtalOsc(void);
+void ClockSelectRcOsc(void);
+void LPM_EnableWakeupSource(uint32_t irq);
+void LPM_DisableWakeupSource(uint32_t irq);
+void LPM_PreEnterWaitMode(void);
+void LPM_PostExitWaitMode(void);
+void LPM_PreEnterStopMode(void);
+void LPM_PostExitStopMode(void);
+void LPM_OverDriveRun(void);
+void LPM_FullSpeedRun(void);
+void LPM_LowSpeedRun(void);
+void LPM_LowPowerRun(void);
+void LPM_EnterSystemIdle(void);
+void LPM_ExitSystemIdle(void);
+void LPM_EnterLowPowerIdle(void);
+void LPM_ExitLowPowerIdle(void);
+void LPM_EnterSuspend(void);
+void LPM_EnterSNVS(void);
+
 #if defined(__cplusplus)
 }
 #endif /* __cplusplus*/
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/mbed_overrides.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/mbed_overrides.c
index 5456d49098d..63fd85d1f65 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/mbed_overrides.c
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/mbed_overrides.c
@@ -17,6 +17,8 @@
 #include "fsl_clock_config.h"
 #include "fsl_clock.h"
 #include "fsl_xbara.h"
+#include "fsl_iomuxc.h"
+#include "fsl_gpio.h"
 #include "lpm.h"
 
 #define LPSPI_CLOCK_SOURCE_DIVIDER (7U)
@@ -40,10 +42,10 @@ void BOARD_ConfigMPU(void)
 
     /* MPU configure:
      * Use ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size)
-     * API in core_cm7.h.
+     * API in mpu_armv7.h.
      * param DisableExec       Instruction access (XN) disable bit,0=instruction fetches enabled, 1=instruction fetches disabled.
      * param AccessPermission  Data access permissions, allows you to configure read/write access for User and Privileged mode.
-     *      Use MACROS defined in core_cm7.h: ARM_MPU_AP_NONE/ARM_MPU_AP_PRIV/ARM_MPU_AP_URO/ARM_MPU_AP_FULL/ARM_MPU_AP_PRO/ARM_MPU_AP_RO
+     *      Use MACROS defined in mpu_armv7.h: ARM_MPU_AP_NONE/ARM_MPU_AP_PRIV/ARM_MPU_AP_URO/ARM_MPU_AP_FULL/ARM_MPU_AP_PRO/ARM_MPU_AP_RO
      * Combine TypeExtField/IsShareable/IsCacheable/IsBufferable to configure MPU memory access attributes.
      *  TypeExtField  IsShareable  IsCacheable  IsBufferable   Memory Attribtue    Shareability        Cache
      *     0             x           0           0             Strongly Ordered    shareable
@@ -60,26 +62,22 @@ void BOARD_ConfigMPU(void)
      *  Above are normal use settings, if your want to see more details or want to config different inner/outter cache policy.
      *  please refer to Table 4-55 /4-56 in arm cortex-M7 generic user guide <dui0646b_cortex_m7_dgug.pdf>
      * param SubRegionDisable  Sub-region disable field. 0=sub-region is enabled, 1=sub-region is disabled.
-     * param Size              Region size of the region to be configured. use ARM_MPU_REGION_SIZE_xxx MACRO in core_cm7.h.
+     * param Size              Region size of the region to be configured. use ARM_MPU_REGION_SIZE_xxx MACRO in mpu_armv7.h.
      */
 
     /* Region 0 setting: Memory with Device type, not shareable, non-cacheable. */
-    MPU->RBAR = ARM_MPU_RBAR(0, 0xC0000000U);
+    MPU->RBAR = ARM_MPU_RBAR(0, 0x80000000U);
     MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
 
     /* Region 1 setting: Memory with Device type, not shareable,  non-cacheable. */
-    MPU->RBAR = ARM_MPU_RBAR(1, 0x80000000U);
-    MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);
+    MPU->RBAR = ARM_MPU_RBAR(1, 0x60000000U);
+    MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
 
-    /* Region 2 setting */
+/* Region 2 setting */
 #if defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)
     /* Setting Memory with Normal type, not shareable, outer/inner write back. */
     MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U);
-    MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_512MB);
-#else
-    /* Setting Memory with Device type, not shareable, non-cacheable. */
-    MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U);
-    MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
+    MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_RO, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_64MB);
 #endif
 
     /* Region 3 setting: Memory with Device type, not shareable, non-cacheable. */
@@ -98,9 +96,9 @@ void BOARD_ConfigMPU(void)
     MPU->RBAR = ARM_MPU_RBAR(6, 0x20200000U);
     MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB);
 
-    /* The define sets the cacheable memory to shareable,
-     * this suggestion is referred from chapter 2.2.1 Memory regions,
-     * types and attributes in Cortex-M7 Devices, Generic User Guide */
+/* The define sets the cacheable memory to shareable,
+ * this suggestion is referred from chapter 2.2.1 Memory regions,
+ * types and attributes in Cortex-M7 Devices, Generic User Guide */
 #if defined(SDRAM_IS_SHAREABLE)
     /* Region 7 setting: Memory with Normal type, shareable, outer/inner write back, write/read allocate */
     MPU->RBAR = ARM_MPU_RBAR(7, 0x80000000U);
@@ -125,38 +123,44 @@ void BOARD_ConfigMPU(void)
     SCB_EnableICache();
 }
 
-#if defined(TOOLCHAIN_GCC_ARM)
-extern uint32_t __ram_function_flash_start[];
-#define __RAM_FUNCTION_FLASH_START __ram_function_flash_start
-extern uint32_t __ram_function_ram_start[];
-#define __RAM_FUNCTION_RAM_START __ram_function_ram_start
-extern uint32_t __ram_function_size[];
-#define __RAM_FUNCTION_SIZE __ram_function_size
-void Board_CopyToRam()
-{
-    unsigned char *source;
-    unsigned char *destiny;
-    unsigned int size;
-
-    source = (unsigned char *)(__RAM_FUNCTION_FLASH_START);
-    destiny = (unsigned char *)(__RAM_FUNCTION_RAM_START);
-    size = (unsigned long)(__RAM_FUNCTION_SIZE);
-
-    while (size--)
-    {
-        *destiny++ = *source++;
-    }
+void BOARD_Init_PMIC_STBY_REQ(void) {
+    CLOCK_EnableClock(kCLOCK_IomuxcSnvs);       /* iomuxc_snvs clock (iomuxc_snvs_clk_enable): 0x03U */
+
+    /* GPIO configuration of PERI_PWREN on PMIC_STBY_REQ (pin L7) */
+    gpio_pin_config_t PERI_PWREN_config = {
+        .direction = kGPIO_DigitalOutput,
+        .outputLogic = 0U,
+        .interruptMode = kGPIO_NoIntmode
+    };
+    /* Initialize GPIO functionality on PMIC_STBY_REQ (pin L7) */
+    GPIO_PinInit(GPIO5, 2U, &PERI_PWREN_config);
+
+    IOMUXC_SetPinMux(
+        IOMUXC_SNVS_PMIC_STBY_REQ_GPIO5_IO02,   /* PMIC_STBY_REQ is configured as GPIO5_IO02 */
+        0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+    IOMUXC_SetPinConfig(
+        IOMUXC_SNVS_PMIC_STBY_REQ_GPIO5_IO02,   /* PMIC_STBY_REQ PAD functional properties : */
+        0x10B0U);                               /* Slew Rate Field: Slow Slew Rate
+                                                   Drive Strength Field: R0/6
+                                                   Speed Field: medium(100MHz)
+                                                   Open Drain Enable Field: Open Drain Disabled
+                                                   Pull / Keep Enable Field: Pull/Keeper Enabled
+                                                   Pull / Keep Select Field: Keeper
+                                                   Pull Up / Down Config. Field: 100K Ohm Pull Down
+                                                   Hyst. Enable Field: Hysteresis Disabled */
 }
-#endif
 
 // called before main
 void mbed_sdk_init()
 {
     BOARD_ConfigMPU();
     BOARD_BootClockRUN();
-#if defined(TOOLCHAIN_GCC_ARM)
-    Board_CopyToRam();
-#endif
+
+    /* Since SNVS_PMIC_STBY_REQ_GPIO5_IO02 will output a high-level signal under Stop Mode(Suspend Mode) and this pin is
+     * connected to LCD power switch circuit. So it needs to be configured as a low-level output GPIO to reduce the
+     * current. */
+    BOARD_Init_PMIC_STBY_REQ();
+
     LPM_Init();
 }
 
@@ -187,16 +191,15 @@ uint32_t us_ticker_get_clock()
 
 void serial_setup_clock(void)
 {
-    /* We assume default PLL and divider settings */
+    /* Configure UART divider to default */
+    CLOCK_SetMux(kCLOCK_UartMux, 1); /* Set UART source to OSC 24M */
+    CLOCK_SetDiv(kCLOCK_UartDiv, 0); /* Set UART divider to 1 */
 }
 
 uint32_t serial_get_clock(void)
 {
     uint32_t clock_freq;
 
-    /* We assume default PLL and divider settings, and the only variable
-     * from application is use PLL3 source or OSC source
-     */
     if (CLOCK_GetMux(kCLOCK_UartMux) == 0) /* PLL3 div6 80M */ {
         clock_freq = (CLOCK_GetPllFreq(kCLOCK_PllUsb1) / 6U) / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U);
     } else {
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/specific.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/specific.c
new file mode 100644
index 00000000000..5abd97c2b17
--- /dev/null
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/specific.c
@@ -0,0 +1,615 @@
+/*
+ * Copyright 2019 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "specific.h"
+#include "fsl_common.h"
+#include "fsl_clock.h"
+#include "lpm.h"
+#include "fsl_iomuxc.h"
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+const clock_arm_pll_config_t armPllConfig_PowerMode = {
+    .loopDivider = 100, /* PLL loop divider, Fout = Fin * 50 */
+    .src         = 0,   /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+};
+const clock_sys_pll_config_t sysPllConfig_PowerMode = {
+    .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
+    .numerator   = 0, /* 30 bit numerator of fractional loop divider */
+    .denominator = 1, /* 30 bit denominator of fractional loop divider */
+    .src         = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+};
+const clock_usb_pll_config_t usb1PllConfig_PowerMode = {
+    .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */
+    .src         = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+};
+
+AT_QUICKACCESS_SECTION_CODE(void SwitchSystemClocks(lpm_power_mode_t power_mode));
+
+#define NUMBER_OF_CCM_GATE_REGS   7
+static uint32_t clock_gate_values[NUMBER_OF_CCM_GATE_REGS];
+
+void SwitchSystemClocks(lpm_power_mode_t power_mode)
+{
+#if (defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
+    while (!((FLEXSPI_INST->STS0 & FLEXSPI_STS0_ARBIDLE_MASK) && (FLEXSPI_INST->STS0 & FLEXSPI_STS0_SEQIDLE_MASK)))
+    {
+    }
+    FLEXSPI_INST->MCR0 |= FLEXSPI_MCR0_MDIS_MASK;
+
+    /* Disable clock gate of flexspi. */
+    CCM->CCGR6 &= (~CCM_CCGR6_CG5_MASK);
+#endif
+    switch (power_mode)
+    {
+        case LPM_PowerModeOverRun:
+            CLOCK_SET_DIV(kCLOCK_SemcDiv, 3);    // SEMC CLK should not exceed 166MHz
+            CLOCK_SET_DIV(kCLOCK_FlexspiDiv, 0); // FLEXSPI in DDR mode
+            CLOCK_SET_MUX(kCLOCK_FlexspiMux, 3); // FLEXSPI mux to PLL3 PFD0
+            /* CORE CLK to 600MHz, AHB, IPG to 150MHz, PERCLK to 75MHz */
+            //CLOCK_SET_DIV(kCLOCK_PerclkDiv, 1);
+            CLOCK_SET_DIV(kCLOCK_IpgDiv, 3);
+            CLOCK_SET_DIV(kCLOCK_AhbDiv, 0);
+            //CLOCK_SET_MUX(kCLOCK_PerclkMux, 0);    // PERCLK mux to IPG CLK
+            CLOCK_SET_MUX(kCLOCK_PrePeriphMux, 3); // PRE_PERIPH_CLK mux to ARM PLL
+            CLOCK_SET_MUX(kCLOCK_PeriphMux, 0);    // PERIPH_CLK mux to PRE_PERIPH_CLK
+            break;
+        case LPM_PowerModeFullRun:
+            CLOCK_SET_DIV(kCLOCK_SemcDiv, 3);    // SEMC CLK should not exceed 166MHz
+            CLOCK_SET_DIV(kCLOCK_FlexspiDiv, 0); // FLEXSPI in DDR mode
+            CLOCK_SET_MUX(kCLOCK_FlexspiMux, 3); // FLEXSPI mux to PLL3 PFD0
+            /* CORE CLK to 528MHz, AHB, IPG to 132MHz, PERCLK to 66MHz */
+            CLOCK_SET_DIV(kCLOCK_PerclkDiv, 1);
+            CLOCK_SET_DIV(kCLOCK_IpgDiv, 3);
+            CLOCK_SET_DIV(kCLOCK_AhbDiv, 0);
+            CLOCK_SET_MUX(kCLOCK_PerclkMux, 0);    // PERCLK mux to IPG CLK
+            CLOCK_SET_MUX(kCLOCK_PrePeriphMux, 0); // PRE_PERIPH_CLK mux to SYS PLL
+            CLOCK_SET_MUX(kCLOCK_PeriphMux, 0);    // PERIPH_CLK mux to PRE_PERIPH_CLK
+            break;
+        case LPM_PowerModeLowSpeedRun:
+        case LPM_PowerModeSysIdle:
+            CLOCK_SET_DIV(kCLOCK_SemcDiv, 3);    // SEMC CLK should not exceed 166MHz
+#ifdef HYPERFLASH_BOOT
+            CLOCK_SET_DIV(kCLOCK_FlexspiDiv, 1); // FLEXSPI in DDR mode
+#else
+            CLOCK_SET_DIV(kCLOCK_FlexspiDiv, 3); // FLEXSPI in SDR mode
+#endif
+            CLOCK_SET_MUX(kCLOCK_FlexspiMux, 2); // FLEXSPI mux to PLL2 PFD2
+            /* CORE CLK to 132MHz and AHB, IPG, PERCLK to 33MHz */
+            CLOCK_SET_DIV(kCLOCK_PerclkDiv, 0);
+            CLOCK_SET_DIV(kCLOCK_IpgDiv, 3);
+            CLOCK_SET_DIV(kCLOCK_AhbDiv, 3);
+            CLOCK_SET_MUX(kCLOCK_PerclkMux, 0);    // PERCLK mux to IPG CLK
+            CLOCK_SET_MUX(kCLOCK_PrePeriphMux, 0); // Switch PRE_PERIPH_CLK to SYS PLL
+            CLOCK_SET_MUX(kCLOCK_PeriphMux, 0);    // Switch PERIPH_CLK to PRE_PERIPH_CLK
+            break;
+        case LPM_PowerModeLowPowerRun:
+        case LPM_PowerModeLPIdle:
+            CLOCK_SET_DIV(kCLOCK_PeriphClk2Div, 0);
+            CLOCK_SET_MUX(kCLOCK_PeriphClk2Mux, 1); // PERIPH_CLK2 mux to OSC
+            CLOCK_SET_MUX(kCLOCK_PeriphMux, 1);     // PERIPH_CLK mux to PERIPH_CLK2
+            CLOCK_SET_DIV(kCLOCK_SemcDiv, 0);
+            CLOCK_SET_MUX(kCLOCK_SemcMux, 0);    // SEMC mux to PERIPH_CLK
+            CLOCK_SET_DIV(kCLOCK_FlexspiDiv, 0); // FLEXSPI in DDR mode
+            CLOCK_SET_MUX(kCLOCK_FlexspiMux, 0); // FLEXSPI mux to semc_clk_root_pre
+            /* CORE CLK to 24MHz and AHB, IPG, PERCLK to 12MHz */
+            //CLOCK_SET_DIV(kCLOCK_PerclkDiv, 0);
+            CLOCK_SET_DIV(kCLOCK_IpgDiv, 1);
+            CLOCK_SET_DIV(kCLOCK_AhbDiv, 0);
+            //CLOCK_SET_MUX(kCLOCK_PerclkMux, 0); // PERCLK mux to IPG CLK
+            break;
+        default:
+            break;
+    }
+
+#if (defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
+    /* Enable clock gate of flexspi. */
+    CCM->CCGR6 |= (CCM_CCGR6_CG5_MASK);
+
+#ifdef HYPERFLASH_BOOT
+    if ((LPM_PowerModeLowPowerRun == power_mode) || (LPM_PowerModeLPIdle == power_mode))
+    {
+        FLEXSPI_INST->DLLCR[0] = FLEXSPI_DLLCR_OVRDEN(1) | FLEXSPI_DLLCR_OVRDVAL(19);
+    }
+    else
+    {
+        FLEXSPI_INST->DLLCR[0] = FLEXSPI_DLLCR_DLLEN(1) | FLEXSPI_DLLCR_SLVDLYTARGET(15);
+    }
+#endif
+    
+    FLEXSPI_INST->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK;
+    FLEXSPI_INST->MCR0 |= FLEXSPI_MCR0_SWRESET_MASK;
+    while (FLEXSPI_INST->MCR0 & FLEXSPI_MCR0_SWRESET_MASK)
+    {
+    }
+    while (!((FLEXSPI_INST->STS0 & FLEXSPI_STS0_ARBIDLE_MASK) && (FLEXSPI_INST->STS0 & FLEXSPI_STS0_SEQIDLE_MASK)))
+    {
+    }
+#endif
+}
+
+void ClockSetToOverDriveRun(void)
+{
+    // CORE CLK mux to 24M before reconfigure PLLs
+    LPM_EnterCritical();
+    SwitchSystemClocks(LPM_PowerModeLowPowerRun);
+    LPM_ExitCritical();
+    //ClockSelectXtalOsc();
+
+    /* Init ARM PLL */
+    CLOCK_SetDiv(kCLOCK_ArmDiv, 1);
+    CLOCK_InitArmPll(&armPllConfig_PowerMode);
+
+    /* Init SYS PLL*/
+    CLOCK_InitSysPll(&sysPllConfig_PowerMode);
+    /* Init System pfd0. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd0, 27);
+    /* Init System pfd1. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd1, 16);
+    /* Init System pfd2. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd2, 24);
+    /* Init System pfd3. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd3, 16);
+
+    /* Init USB1 PLL. */
+    CLOCK_InitUsb1Pll(&usb1PllConfig_PowerMode);
+    /* Init Usb1 pfd0. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 33);
+    /* Init Usb1 pfd1. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16);
+    /* Init Usb1 pfd2. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17);
+    /* Init Usb1 pfd3. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 19);
+    /* Disable Usb1 PLL output for USBPHY1. */
+    CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK;
+
+    /* Init USB2 PLL*/
+    CCM_ANALOG->PLL_USB2_SET = CCM_ANALOG_PLL_USB2_BYPASS_MASK;
+    CCM_ANALOG->PLL_USB2_SET = CCM_ANALOG_PLL_USB2_ENABLE_MASK;
+    CCM_ANALOG->PLL_USB2_SET = CCM_ANALOG_PLL_USB2_POWER_MASK;
+    while ((CCM_ANALOG->PLL_USB2 & CCM_ANALOG_PLL_USB2_LOCK_MASK) == 0)
+    {
+    }
+    CCM_ANALOG->PLL_USB2_CLR = CCM_ANALOG_PLL_USB2_BYPASS_MASK;
+
+    /* Init AUDIO PLL */
+    CCM_ANALOG->PLL_AUDIO_SET = CCM_ANALOG_PLL_AUDIO_BYPASS_MASK;
+    CCM_ANALOG->PLL_AUDIO_CLR = CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK;
+    CCM_ANALOG->PLL_AUDIO_SET = CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
+    while ((CCM_ANALOG->PLL_AUDIO & CCM_ANALOG_PLL_AUDIO_LOCK_MASK) == 0)
+    {
+    }
+    CCM_ANALOG->PLL_AUDIO_CLR = CCM_ANALOG_PLL_AUDIO_BYPASS_MASK;
+
+    /* Init VIDEO PLL */
+    CCM_ANALOG->PLL_VIDEO_SET = CCM_ANALOG_PLL_VIDEO_BYPASS_MASK;
+    CCM_ANALOG->PLL_VIDEO_CLR = CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK;
+    CCM_ANALOG->PLL_VIDEO_SET = CCM_ANALOG_PLL_VIDEO_ENABLE_MASK;
+    while ((CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) == 0)
+    {
+    }
+    CCM_ANALOG->PLL_VIDEO_CLR = CCM_ANALOG_PLL_VIDEO_BYPASS_MASK;
+
+    /* Init ENET PLL */
+    CCM_ANALOG->PLL_ENET_SET = CCM_ANALOG_PLL_ENET_BYPASS_MASK;
+    CCM_ANALOG->PLL_ENET_CLR = CCM_ANALOG_PLL_ENET_POWERDOWN_MASK;
+    CCM_ANALOG->PLL_ENET_SET = CCM_ANALOG_PLL_ENET_ENABLE_MASK;
+    CCM_ANALOG->PLL_ENET_SET = CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK;
+    while ((CCM_ANALOG->PLL_ENET & CCM_ANALOG_PLL_ENET_LOCK_MASK) == 0)
+    {
+    }
+    CCM_ANALOG->PLL_ENET_CLR = CCM_ANALOG_PLL_ENET_BYPASS_MASK;
+
+    LPM_EnterCritical();
+    SwitchSystemClocks(LPM_PowerModeOverRun);
+    LPM_ExitCritical();
+}
+
+void ClockSetToFullSpeedRun(void)
+{
+    // CORE CLK mux to 24M before reconfigure PLLs
+    LPM_EnterCritical();
+    SwitchSystemClocks(LPM_PowerModeLowPowerRun);
+    LPM_ExitCritical();
+    ClockSelectXtalOsc();
+
+    /* Init ARM PLL */
+    CLOCK_SetDiv(kCLOCK_ArmDiv, 1);
+    CLOCK_InitArmPll(&armPllConfig_PowerMode);
+
+    /* Init SYS PLL. */
+    CLOCK_InitSysPll(&sysPllConfig_PowerMode);
+    /* Init System pfd0. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd0, 27);
+    /* Init System pfd1. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd1, 16);
+    /* Init System pfd2. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd2, 24);
+    /* Init System pfd3. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd3, 16);
+
+    /* Init USB1 PLL. */
+    CLOCK_InitUsb1Pll(&usb1PllConfig_PowerMode);
+    /* Init Usb1 pfd0. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 33);
+    /* Init Usb1 pfd1. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16);
+    /* Init Usb1 pfd2. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17);
+    /* Init Usb1 pfd3. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 19);
+    /* Disable Usb1 PLL output for USBPHY1. */
+    CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK;
+
+    /* Init USB2 PLL*/
+    CCM_ANALOG->PLL_USB2_SET = CCM_ANALOG_PLL_USB2_BYPASS_MASK;
+    CCM_ANALOG->PLL_USB2_SET = CCM_ANALOG_PLL_USB2_ENABLE_MASK;
+    CCM_ANALOG->PLL_USB2_SET = CCM_ANALOG_PLL_USB2_POWER_MASK;
+    while ((CCM_ANALOG->PLL_USB2 & CCM_ANALOG_PLL_USB2_LOCK_MASK) == 0)
+    {
+    }
+    CCM_ANALOG->PLL_USB2_CLR = CCM_ANALOG_PLL_USB2_BYPASS_MASK;
+
+    /* Init AUDIO PLL */
+    CCM_ANALOG->PLL_AUDIO_SET = CCM_ANALOG_PLL_AUDIO_BYPASS_MASK;
+    CCM_ANALOG->PLL_AUDIO_CLR = CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK;
+    CCM_ANALOG->PLL_AUDIO_SET = CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
+    while ((CCM_ANALOG->PLL_AUDIO & CCM_ANALOG_PLL_AUDIO_LOCK_MASK) == 0)
+    {
+    }
+    CCM_ANALOG->PLL_AUDIO_CLR = CCM_ANALOG_PLL_AUDIO_BYPASS_MASK;
+
+    /* Init VIDEO PLL */
+    CCM_ANALOG->PLL_VIDEO_SET = CCM_ANALOG_PLL_VIDEO_BYPASS_MASK;
+    CCM_ANALOG->PLL_VIDEO_CLR = CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK;
+    CCM_ANALOG->PLL_VIDEO_SET = CCM_ANALOG_PLL_VIDEO_ENABLE_MASK;
+    while ((CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) == 0)
+    {
+    }
+    CCM_ANALOG->PLL_VIDEO_CLR = CCM_ANALOG_PLL_VIDEO_BYPASS_MASK;
+
+    /* Init ENET PLL */
+    CCM_ANALOG->PLL_ENET_SET = CCM_ANALOG_PLL_ENET_BYPASS_MASK;
+    CCM_ANALOG->PLL_ENET_CLR = CCM_ANALOG_PLL_ENET_POWERDOWN_MASK;
+    CCM_ANALOG->PLL_ENET_SET = CCM_ANALOG_PLL_ENET_ENABLE_MASK;
+    CCM_ANALOG->PLL_ENET_SET = CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK;
+    while ((CCM_ANALOG->PLL_ENET & CCM_ANALOG_PLL_ENET_LOCK_MASK) == 0)
+    {
+    }
+    CCM_ANALOG->PLL_ENET_CLR = CCM_ANALOG_PLL_ENET_BYPASS_MASK;
+
+    LPM_EnterCritical();
+    SwitchSystemClocks(LPM_PowerModeFullRun);
+    LPM_ExitCritical();
+}
+
+void ClockSetToLowSpeedRun(void)
+{
+    // CORE CLK mux to 24M before reconfigure PLLs
+    LPM_EnterCritical();
+    SwitchSystemClocks(LPM_PowerModeLowPowerRun);
+    LPM_ExitCritical();
+    ClockSelectXtalOsc();
+
+    /* Deinit ARM PLL */
+    CLOCK_DeinitArmPll();
+
+    /* Init SYS PLL */
+    CLOCK_InitSysPll(&sysPllConfig_PowerMode);
+
+    /* Deinit SYS PLL PFD 0 1 3 */
+    CLOCK_DeinitSysPfd(kCLOCK_Pfd0);
+    CLOCK_DeinitSysPfd(kCLOCK_Pfd1);
+    /* Init System pfd2. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd2, 18);
+    CLOCK_DeinitSysPfd(kCLOCK_Pfd3);
+
+    /* Deinit USB1 PLL */
+    CLOCK_DeinitUsb1Pll();
+
+    /* Deinit USB1 PLL PFD 0 1 2 3 */
+    CLOCK_DeinitUsb1Pfd(kCLOCK_Pfd0);
+    CLOCK_DeinitUsb1Pfd(kCLOCK_Pfd1);
+    CLOCK_DeinitUsb1Pfd(kCLOCK_Pfd2);
+    CLOCK_DeinitUsb1Pfd(kCLOCK_Pfd3);
+
+    /* Deinit USB2 PLL */
+    CLOCK_DeinitUsb2Pll();
+
+    /* Deinit AUDIO PLL */
+    CLOCK_DeinitAudioPll();
+
+    /* Deinit VIDEO PLL */
+    CLOCK_DeinitVideoPll();
+
+    /* Deinit ENET PLL */
+    CLOCK_DeinitEnetPll();
+
+    LPM_EnterCritical();
+    SwitchSystemClocks(LPM_PowerModeLowSpeedRun);
+    LPM_ExitCritical();
+}
+
+void ClockSetToLowPowerRun(void)
+{
+    // CORE CLK mux to 24M before reconfigure PLLs
+    LPM_EnterCritical();
+    SwitchSystemClocks(LPM_PowerModeLowPowerRun);
+    LPM_ExitCritical();
+    ClockSelectRcOsc();
+
+    /* Deinit ARM PLL */
+    CLOCK_DeinitArmPll();
+
+    /* Deinit SYS PLL */
+    CLOCK_DeinitSysPll();
+
+    /* Deinit SYS PLL PFD 0 1 2 3 */
+    CLOCK_DeinitSysPfd(kCLOCK_Pfd0);
+    CLOCK_DeinitSysPfd(kCLOCK_Pfd1);
+    CLOCK_DeinitSysPfd(kCLOCK_Pfd2);
+    CLOCK_DeinitSysPfd(kCLOCK_Pfd3);
+
+    /* Power Down USB1 PLL */
+    CCM_ANALOG->PLL_USB1_SET = CCM_ANALOG_PLL_USB1_BYPASS_MASK;
+    CCM_ANALOG->PLL_USB1_CLR = CCM_ANALOG_PLL_USB1_POWER_MASK;
+    CCM_ANALOG->PLL_USB1_CLR = CCM_ANALOG_PLL_USB1_ENABLE_MASK;
+
+    /* Deinit USB1 PLL PFD 0 1 2 3 */
+    CLOCK_DeinitUsb1Pfd(kCLOCK_Pfd0);
+    CLOCK_DeinitUsb1Pfd(kCLOCK_Pfd1);
+    CLOCK_DeinitUsb1Pfd(kCLOCK_Pfd2);
+    CLOCK_DeinitUsb1Pfd(kCLOCK_Pfd3);
+
+    /* Deinit USB2 PLL */
+    CLOCK_DeinitUsb2Pll();
+
+    /* Deinit AUDIO PLL */
+    CLOCK_DeinitAudioPll();
+
+    /* Deinit VIDEO PLL */
+    CLOCK_DeinitVideoPll();
+
+    /* Deinit ENET PLL */
+    CLOCK_DeinitEnetPll();
+}
+
+void ClockSetToSystemIdle(void)
+{
+    // CORE CLK mux to 24M before reconfigure PLLs
+    LPM_EnterCritical();
+    SwitchSystemClocks(LPM_PowerModeLowPowerRun);
+    LPM_ExitCritical();
+    ClockSelectXtalOsc();
+
+    /* Deinit ARM PLL */
+    CLOCK_DeinitArmPll();
+
+    /* Init SYS PLL */
+    CLOCK_InitSysPll(&sysPllConfig_PowerMode);
+
+    /* Deinit SYS PLL PFD 0 1 3 */
+    CLOCK_DeinitSysPfd(kCLOCK_Pfd0);
+    CLOCK_DeinitSysPfd(kCLOCK_Pfd1);
+    /* Init System pfd2. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd2, 18);
+    CLOCK_DeinitSysPfd(kCLOCK_Pfd3);
+
+    /* Deinit USB1 PLL */
+    CLOCK_DeinitUsb1Pll();
+
+    /* Deinit USB1 PLL PFD 0 1 2 3 */
+    CLOCK_DeinitUsb1Pfd(kCLOCK_Pfd0);
+    CLOCK_DeinitUsb1Pfd(kCLOCK_Pfd1);
+    CLOCK_DeinitUsb1Pfd(kCLOCK_Pfd2);
+    CLOCK_DeinitUsb1Pfd(kCLOCK_Pfd3);
+
+    /* Deinit USB2 PLL */
+    CLOCK_DeinitUsb2Pll();
+
+    /* Deinit AUDIO PLL */
+    CLOCK_DeinitAudioPll();
+
+    /* Deinit VIDEO PLL */
+    CLOCK_DeinitVideoPll();
+
+    /* Deinit ENET PLL */
+    CLOCK_DeinitEnetPll();
+
+    LPM_EnterCritical();
+    SwitchSystemClocks(LPM_PowerModeSysIdle);
+    LPM_ExitCritical();
+}
+
+void ClockSetToLowPowerIdle(void)
+{
+    // CORE CLK mux to 24M before reconfigure PLLs
+    LPM_EnterCritical();
+    SwitchSystemClocks(LPM_PowerModeLowPowerRun);
+    LPM_ExitCritical();
+    //ClockSelectRcOsc();
+
+    /* Deinit ARM PLL */
+    CLOCK_DeinitArmPll();
+
+    /* Deinit SYS PLL */
+    CLOCK_DeinitSysPll();
+
+    /* Deinit SYS PLL PFD 0 1 2 3 */
+    CLOCK_DeinitSysPfd(kCLOCK_Pfd0);
+    CLOCK_DeinitSysPfd(kCLOCK_Pfd1);
+    CLOCK_DeinitSysPfd(kCLOCK_Pfd2);
+    CLOCK_DeinitSysPfd(kCLOCK_Pfd3);
+
+    /* Deinit USB1 PLL */
+    CLOCK_DeinitUsb1Pll();
+
+    /* Deinit USB1 PLL PFD 0 1 2 3 */
+    CLOCK_DeinitUsb1Pfd(kCLOCK_Pfd0);
+    CLOCK_DeinitUsb1Pfd(kCLOCK_Pfd1);
+    CLOCK_DeinitUsb1Pfd(kCLOCK_Pfd2);
+    CLOCK_DeinitUsb1Pfd(kCLOCK_Pfd3);
+
+    /* Deinit USB2 PLL */
+    CLOCK_DeinitUsb2Pll();
+
+    /* Deinit AUDIO PLL */
+    CLOCK_DeinitAudioPll();
+
+    /* Deinit VIDEO PLL */
+    CLOCK_DeinitVideoPll();
+
+    /* Deinit ENET PLL */
+    CLOCK_DeinitEnetPll();
+
+    LPM_EnterCritical();
+    SwitchSystemClocks(LPM_PowerModeLPIdle);
+    LPM_ExitCritical();
+}
+
+void SetLowPowerClockGate(void)
+{
+    /* Save of the clock gate registers */
+    clock_gate_values[0] = CCM->CCGR0;
+    clock_gate_values[1] = CCM->CCGR1;
+    clock_gate_values[2] = CCM->CCGR2;
+    clock_gate_values[3] = CCM->CCGR3;
+    clock_gate_values[4] = CCM->CCGR4;
+    clock_gate_values[5] = CCM->CCGR5;
+    clock_gate_values[6] = CCM->CCGR6;
+
+    /* Set low power gate values */
+    CCM->CCGR0 = CCM_CCGR0_CG0(1) | CCM_CCGR0_CG1(1) | CCM_CCGR0_CG3(3) | CCM_CCGR0_CG11(1) | CCM_CCGR0_CG12(1);
+    CCM->CCGR1 = CCM_CCGR1_CG9(3) | CCM_CCGR1_CG10(1) | CCM_CCGR1_CG13(1) | CCM_CCGR1_CG14(1) | CCM_CCGR1_CG15(1);
+    CCM->CCGR2 = CCM_CCGR2_CG2(1) | CCM_CCGR2_CG8(1) | CCM_CCGR2_CG9(1) | CCM_CCGR2_CG10(1);
+    CCM->CCGR3 = CCM_CCGR3_CG2(1) | CCM_CCGR3_CG4(1) | CCM_CCGR3_CG9(1) | CCM_CCGR3_CG14(3) | CCM_CCGR3_CG15(1);
+    CCM->CCGR4 =
+        CCM_CCGR4_CG1(1) | CCM_CCGR4_CG2(1) | CCM_CCGR4_CG4(1) | CCM_CCGR4_CG5(1) | CCM_CCGR4_CG6(1) | CCM_CCGR4_CG7(1);
+    CCM->CCGR5 = CCM_CCGR5_CG0(1) | CCM_CCGR5_CG1(1) | CCM_CCGR5_CG4(1) | CCM_CCGR5_CG6(1) | CCM_CCGR5_CG12(1) |
+                 CCM_CCGR5_CG14(1) | CCM_CCGR5_CG15(1);
+    /* We can enable DCDC when need to config it and close it after configuration */
+    CCM->CCGR6 = CCM_CCGR6_CG3(1) | CCM_CCGR6_CG4(1) | CCM_CCGR6_CG5(1) | CCM_CCGR6_CG9(1) | CCM_CCGR6_CG10(1) |
+                 CCM_CCGR6_CG11(1);
+}
+
+void SetRestoreClockGate(void)
+{
+    CCM->CCGR0 = clock_gate_values[0];
+    CCM->CCGR1 = clock_gate_values[1];
+    CCM->CCGR2 = clock_gate_values[2];
+    CCM->CCGR3 = clock_gate_values[3];
+    CCM->CCGR4 = clock_gate_values[4];
+    CCM->CCGR5 = clock_gate_values[5];
+    CCM->CCGR6 = clock_gate_values[6];
+}
+
+void PowerDownUSBPHY(void)
+{
+    USBPHY1->CTRL = 0xFFFFFFFF;
+    USBPHY2->CTRL = 0xFFFFFFFF;
+}
+
+void ConfigUartRxPinToGpio(void)
+{
+    IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_13_GPIO1_IO13, 0);
+    IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_13_GPIO1_IO13,
+                        IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(2) | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK);
+}
+
+void ReConfigUartRxPin(void)
+{
+    IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_13_LPUART1_RX, 0);
+    IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_13_LPUART1_RX, IOMUXC_SW_PAD_CTL_PAD_SPEED(2));
+}
+
+#define GPR4_STOP_REQ_BITS                                                                                          \
+    (IOMUXC_GPR_GPR4_ENET_STOP_REQ_MASK | IOMUXC_GPR_GPR4_SAI1_STOP_REQ_MASK | IOMUXC_GPR_GPR4_SAI2_STOP_REQ_MASK | \
+     IOMUXC_GPR_GPR4_SAI3_STOP_REQ_MASK | IOMUXC_GPR_GPR4_SEMC_STOP_REQ_MASK | IOMUXC_GPR_GPR4_PIT_STOP_REQ_MASK |  \
+     IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_MASK | IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ_MASK)
+
+#define GPR4_STOP_ACK_BITS                                                                                          \
+    (IOMUXC_GPR_GPR4_ENET_STOP_ACK_MASK | IOMUXC_GPR_GPR4_SAI1_STOP_ACK_MASK | IOMUXC_GPR_GPR4_SAI2_STOP_ACK_MASK | \
+     IOMUXC_GPR_GPR4_SAI3_STOP_ACK_MASK | IOMUXC_GPR_GPR4_SEMC_STOP_ACK_MASK | IOMUXC_GPR_GPR4_PIT_STOP_ACK_MASK |  \
+     IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_MASK | IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK_MASK)
+
+#define GPR7_STOP_REQ_BITS                                                           \
+    (IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_MASK | IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_MASK |   \
+     IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_MASK | IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_MASK |   \
+     IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_MASK | IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_MASK |   \
+     IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_MASK | IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_MASK |   \
+     IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_MASK | IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_MASK | \
+     IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_MASK | IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_MASK | \
+     IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_MASK | IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_MASK | \
+     IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_MASK | IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_MASK)
+
+#define GPR7_STOP_ACK_BITS                                                           \
+    (IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_MASK | IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_MASK |   \
+     IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_MASK | IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_MASK |   \
+     IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_MASK | IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_MASK |   \
+     IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_MASK | IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_MASK |   \
+     IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_MASK | IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_MASK | \
+     IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_MASK | IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_MASK | \
+     IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_MASK | IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_MASK | \
+     IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_MASK | IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_MASK)
+
+#define GPR8_DOZE_BITS                                                               \
+    (IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_MASK | IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_MASK |   \
+     IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_MASK | IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_MASK |   \
+     IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_MASK | IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_MASK |   \
+     IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_MASK | IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_MASK |   \
+     IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_MASK | IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_MASK | \
+     IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_MASK | IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_MASK | \
+     IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_MASK | IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_MASK | \
+     IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_MASK | IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_MASK)
+
+#define GPR8_STOP_MODE_BITS                                                                    \
+    (IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_MASK | IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_MASK |   \
+     IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_MASK | IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_MASK |   \
+     IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_MASK | IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_MASK |   \
+     IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_MASK | IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_MASK |   \
+     IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_MASK | IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_MASK | \
+     IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_MASK | IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_MASK | \
+     IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_MASK | IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_MASK | \
+     IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_MASK)
+
+#define GPR12_DOZE_BITS (IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_MASK | IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE_MASK)
+
+#define GPR12_STOP_MODE_BITS (IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_MASK | IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE_MASK)
+
+void PeripheralEnterDozeMode(void)
+{
+    IOMUXC_GPR->GPR8  = GPR8_DOZE_BITS;
+    IOMUXC_GPR->GPR12 = GPR12_DOZE_BITS;
+}
+
+void PeripheralExitDozeMode(void)
+{
+    IOMUXC_GPR->GPR8  = 0x00000000;
+    IOMUXC_GPR->GPR12 = 0x00000000;
+}
+
+void PeripheralEnterStopMode(void)
+{
+    IOMUXC_GPR->GPR4 = IOMUXC_GPR_GPR4_ENET_STOP_REQ_MASK;
+    while ((IOMUXC_GPR->GPR4 & IOMUXC_GPR_GPR4_ENET_STOP_ACK_MASK) != IOMUXC_GPR_GPR4_ENET_STOP_ACK_MASK)
+    {
+    }
+    IOMUXC_GPR->GPR4  = GPR4_STOP_REQ_BITS;
+    IOMUXC_GPR->GPR7  = GPR7_STOP_REQ_BITS;
+    IOMUXC_GPR->GPR8  = GPR8_DOZE_BITS | GPR8_STOP_MODE_BITS;
+    IOMUXC_GPR->GPR12 = GPR12_DOZE_BITS | GPR12_STOP_MODE_BITS;
+    while ((IOMUXC_GPR->GPR4 & GPR4_STOP_ACK_BITS) != GPR4_STOP_ACK_BITS)
+    {
+    }
+    while ((IOMUXC_GPR->GPR7 & GPR7_STOP_ACK_BITS) != GPR7_STOP_ACK_BITS)
+    {
+    }
+}
+
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/specific.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/specific.h
new file mode 100644
index 00000000000..cc384b4fa4f
--- /dev/null
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/specific.h
@@ -0,0 +1,49 @@
+/*
+ * Copyright 2018-2019 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _SPECIFIC_H_
+#define _SPECIFIC_H_
+
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+#define FLEXSPI_INST FLEXSPI
+#define HAS_WAKEUP_PIN (1)
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+void ClockSetToOverDriveRun(void);
+void ClockSetToFullSpeedRun(void);
+void ClockSetToLowSpeedRun(void);
+void ClockSetToLowPowerRun(void);
+void ClockSetToSystemIdle(void);
+void ClockSetToLowPowerIdle(void);
+
+void SetLowPowerClockGate(void);
+void SetRestoreClockGate(void);
+void PowerDownUSBPHY(void);
+void ConfigUartRxPinToGpio(void);
+void ReConfigUartRxPin(void);
+void PeripheralEnterDozeMode(void);
+void PeripheralExitDozeMode(void);
+void PeripheralEnterStopMode(void);
+void APP_PrintRunFrequency(int32_t run_freq_only);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _SPECIFIC_H_ */
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/xip/evkbimxrt1050_flexspi_nor_config.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/xip/evkbimxrt1050_flexspi_nor_config.c
index d1e47245316..2ecb40f30c9 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/xip/evkbimxrt1050_flexspi_nor_config.c
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/xip/evkbimxrt1050_flexspi_nor_config.c
@@ -1,38 +1,17 @@
 /*
- * The Clear BSD License
  * Copyright 2017 NXP
  * All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- * that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include "evkbimxrt1050_flexspi_nor_config.h"
 
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.xip_board"
+#endif
+
 /*******************************************************************************
  * Code
  ******************************************************************************/
@@ -43,34 +22,59 @@ __attribute__((section(".boot_hdr.conf")))
 #pragma location = ".boot_hdr.conf"
 #endif
 
+#ifdef HYPERFLASH_BOOT
 const flexspi_nor_config_t hyperflash_config = {
-    .memConfig =
-        {
-            .tag = FLEXSPI_CFG_BLK_TAG,
-            .version = FLEXSPI_CFG_BLK_VERSION,
-            .readSampleClkSrc = kFlexSPIReadSampleClk_ExternalInputFromDqsPad,
-            .csHoldTime = 3u,
-            .csSetupTime = 3u,
-            .columnAddressWidth = 3u,
-            // Enable DDR mode, Wordaddassable, Safe configuration, Differential clock
-            .controllerMiscOption =
-                (1u << kFlexSpiMiscOffset_DdrModeEnable) | (1u << kFlexSpiMiscOffset_WordAddressableEnable) |
-                (1u << kFlexSpiMiscOffset_SafeConfigFreqEnable) | (1u << kFlexSpiMiscOffset_DiffClkEnable),
-            .sflashPadType = kSerialFlash_8Pads,
-            .serialClkFreq = kFlexSpiSerialClk_133MHz,
-            .sflashA1Size = 64u * 1024u * 1024u,
-            .dataValidTime = {16u, 16u},
-            .lookupTable =
-                {
-                    // Read LUTs
-                    FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0xA0, RADDR_DDR, FLEXSPI_8PAD, 0x18),
-                    FLEXSPI_LUT_SEQ(CADDR_DDR, FLEXSPI_8PAD, 0x10, DUMMY_DDR, FLEXSPI_8PAD, 0x06),
-                    FLEXSPI_LUT_SEQ(READ_DDR, FLEXSPI_8PAD, 0x04, STOP, FLEXSPI_1PAD, 0x0),
-                },
+    .memConfig = {
+        .tag = FLEXSPI_CFG_BLK_TAG,
+        .version = FLEXSPI_CFG_BLK_VERSION,
+        .readSampleClkSrc = kFlexSPIReadSampleClk_ExternalInputFromDqsPad,
+        .csHoldTime = 3u,
+        .csSetupTime = 3u,
+        .columnAddressWidth = 3u,
+        // Enable DDR mode, Wordaddassable, Safe configuration, Differential clock
+        .controllerMiscOption =
+        (1u << kFlexSpiMiscOffset_DdrModeEnable) | (1u << kFlexSpiMiscOffset_WordAddressableEnable) |
+        (1u << kFlexSpiMiscOffset_SafeConfigFreqEnable) | (1u << kFlexSpiMiscOffset_DiffClkEnable),
+        .sflashPadType = kSerialFlash_8Pads,
+        .serialClkFreq = kFlexSpiSerialClk_133MHz,
+        .sflashA1Size = 64u * 1024u * 1024u,
+        .dataValidTime = {16u, 16u},
+        .lookupTable = {
+            // Read LUTs
+            FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0xA0, RADDR_DDR, FLEXSPI_8PAD, 0x18),
+            FLEXSPI_LUT_SEQ(CADDR_DDR, FLEXSPI_8PAD, 0x10, DUMMY_DDR, FLEXSPI_8PAD, 0x06),
+            FLEXSPI_LUT_SEQ(READ_DDR, FLEXSPI_8PAD, 0x04, STOP, FLEXSPI_1PAD, 0x0),
         },
+    },
     .pageSize = 512u,
     .sectorSize = 256u * 1024u,
     .blockSize = 256u * 1024u,
     .isUniformBlockSize = true,
 };
+#else
+const flexspi_nor_config_t qspiflash_config = {
+    .memConfig = {
+        .tag = FLEXSPI_CFG_BLK_TAG,
+        .version = FLEXSPI_CFG_BLK_VERSION,
+        .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad,
+        .csHoldTime = 3u,
+        .csSetupTime = 3u,
+        .columnAddressWidth = 0u,
+        .configCmdEnable = 0u,
+        .controllerMiscOption = 0u,
+        .deviceType = kFlexSpiDeviceType_SerialNOR,
+        .sflashPadType = kSerialFlash_4Pads,
+        .serialClkFreq = kFlexSpiSerialClk_133MHz,
+        .lutCustomSeqEnable = 0u,
+        .sflashA1Size = 0x00800000u, /* 8MB/64Mbit */
+        .lookupTable = {
+            // Fast read sequence
+            [0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18),
+            [1] = FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x02),
+            [2] = FLEXSPI_LUT_SEQ(STOP, 0, 0, STOP, 0, 0),
+            [3] = FLEXSPI_LUT_SEQ(STOP, 0, 0, STOP, 0, 0),
+        },
+    },
+};
+#endif
 #endif /* XIP_BOOT_HEADER_ENABLE */
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/xip/evkbimxrt1050_flexspi_nor_config.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/xip/evkbimxrt1050_flexspi_nor_config.h
index 67e93b39205..7b422d01b91 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/xip/evkbimxrt1050_flexspi_nor_config.h
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/xip/evkbimxrt1050_flexspi_nor_config.h
@@ -1,42 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2016, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
  * All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without
- * modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- * that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this
- * list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice,
- * this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #ifndef __EVKBIMXRT1050_FLEXSPI_NOR_CONFIG__
@@ -46,6 +13,12 @@
 #include <stdbool.h>
 #include "fsl_common.h"
 
+/*! @name Driver version */
+/*@{*/
+/*! @brief XIP_BOARD driver version 2.0.0. */
+#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*@}*/
+
 /* FLEXSPI memory config block related defintions */
 #define FLEXSPI_CFG_BLK_TAG (0x42464346UL)     // ascii "FCFB" Big Endian
 #define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/xip/evkbimxrt1050_sdram_ini_dcd.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/xip/evkbimxrt1050_sdram_ini_dcd.c
index 4ca8326c9b1..a2c02676993 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/xip/evkbimxrt1050_sdram_ini_dcd.c
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/xip/evkbimxrt1050_sdram_ini_dcd.c
@@ -1,38 +1,22 @@
 /*
- * The Clear BSD License
- * Copyright 2017 NXP
+ * Copyright 2017-2019 NXP
  * All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- * that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
 #include "evkbimxrt1050_sdram_ini_dcd.h"
 
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.xip_board"
+#endif
+
 #if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
 #if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
 #if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
@@ -40,1087 +24,297 @@ __attribute__((section(".boot_hdr.dcd_data")))
 #elif defined(__ICCARM__)
 #pragma location = ".boot_hdr.dcd_data"
 #endif
-/*************************************
- *  DCD Data
- *************************************/
+
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: DCDx V2.0
+processor: MIMXRT1052xxxxB
+mcu_data: ksdk2_0
+processor_version: 0.0.19
+output_format: c_array
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* COMMENTS BELOW ARE USED AS SETTINGS FOR DCD DATA */
 const uint8_t dcd_data[] = {
-    /*0000*/ DCD_TAG_HEADER,
-    0x04,
-    0x30,
+    /* HEADER */
+    /* Tag */
+    0xD2,
+    /* Image Length */
+    0x04, 0x30,
+    /* Version */
     0x41,
-    0xCC,
-    0x03,
-    0xAC,
-    0x04,
-    0x40,
-    0x0F,
-    0xC0,
-    0x68,
-    0xFF,
-    0xFF,
-    0xFF,
-    0xFF,
-    /*0010*/ 0x40,
-    0x0F,
-    0xC0,
-    0x6C,
-    0xFF,
-    0xFF,
-    0xFF,
-    0xFF,
-    0x40,
-    0x0F,
-    0xC0,
-    0x70,
-    0xFF,
-    0xFF,
-    0xFF,
-    0xFF,
-    /*0020*/ 0x40,
-    0x0F,
-    0xC0,
-    0x74,
-    0xFF,
-    0xFF,
-    0xFF,
-    0xFF,
-    0x40,
-    0x0F,
-    0xC0,
-    0x78,
-    0xFF,
-    0xFF,
-    0xFF,
-    0xFF,
-    /*0030*/ 0x40,
-    0x0F,
-    0xC0,
-    0x7C,
-    0xFF,
-    0xFF,
-    0xFF,
-    0xFF,
-    0x40,
-    0x0F,
-    0xC0,
-    0x80,
-    0xFF,
-    0xFF,
-    0xFF,
-    0xFF,
-    /*0040*/ 0x40,
-    0x0D,
-    0x80,
-    0x30,
-    0x00,
-    0x00,
-    0x20,
-    0x01,
-    0x40,
-    0x0D,
-    0x81,
-    0x00,
-    0x00,
-    0x1D,
-    0x00,
-    0x00,
-    /*0050*/ 0x40,
-    0x0F,
-    0xC0,
-    0x14,
-    0x00,
-    0x01,
-    0x0D,
-    0x40,
-    0x40,
-    0x1F,
-    0x80,
-    0x14,
-    0x00,
-    0x00,
-    0x00,
-    0x00,
-    /*0060*/ 0x40,
-    0x1F,
-    0x80,
-    0x18,
-    0x00,
-    0x00,
-    0x00,
-    0x00,
-    0x40,
-    0x1F,
-    0x80,
-    0x1C,
-    0x00,
-    0x00,
-    0x00,
-    0x00,
-    /*0070*/ 0x40,
-    0x1F,
-    0x80,
-    0x20,
-    0x00,
-    0x00,
-    0x00,
-    0x00,
-    0x40,
-    0x1F,
-    0x80,
-    0x24,
-    0x00,
-    0x00,
-    0x00,
-    0x00,
-    /*0080*/ 0x40,
-    0x1F,
-    0x80,
-    0x28,
-    0x00,
-    0x00,
-    0x00,
-    0x00,
-    0x40,
-    0x1F,
-    0x80,
-    0x2C,
-    0x00,
-    0x00,
-    0x00,
-    0x00,
-    /*0090*/ 0x40,
-    0x1F,
-    0x80,
-    0x30,
-    0x00,
-    0x00,
-    0x00,
-    0x00,
-    0x40,
-    0x1F,
-    0x80,
-    0x34,
-    0x00,
-    0x00,
-    0x00,
-    0x00,
-    /*00a0*/ 0x40,
-    0x1F,
-    0x80,
-    0x38,
-    0x00,
-    0x00,
-    0x00,
-    0x00,
-    0x40,
-    0x1F,
-    0x80,
-    0x3C,
-    0x00,
-    0x00,
-    0x00,
-    0x00,
-    /*00b0*/ 0x40,
-    0x1F,
-    0x80,
-    0x40,
-    0x00,
-    0x00,
-    0x00,
-    0x00,
-    0x40,
-    0x1F,
-    0x80,
-    0x44,
-    0x00,
-    0x00,
-    0x00,
-    0x00,
-    /*00c0*/ 0x40,
-    0x1F,
-    0x80,
-    0x48,
-    0x00,
-    0x00,
-    0x00,
-    0x00,
-    0x40,
-    0x1F,
-    0x80,
-    0x4C,
-    0x00,
-    0x00,
-    0x00,
-    0x00,
-    /*00d0*/ 0x40,
-    0x1F,
-    0x80,
-    0x50,
-    0x00,
-    0x00,
-    0x00,
-    0x00,
-    0x40,
-    0x1F,
-    0x80,
-    0x54,
-    0x00,
-    0x00,
-    0x00,
-    0x00,
-    /*00e0*/ 0x40,
-    0x1F,
-    0x80,
-    0x58,
-    0x00,
-    0x00,
-    0x00,
-    0x00,
-    0x40,
-    0x1F,
-    0x80,
-    0x5C,
-    0x00,
-    0x00,
-    0x00,
-    0x00,
-    /*00f0*/ 0x40,
-    0x1F,
-    0x80,
-    0x60,
-    0x00,
-    0x00,
-    0x00,
-    0x00,
-    0x40,
-    0x1F,
-    0x80,
-    0x64,
-    0x00,
-    0x00,
-    0x00,
-    0x00,
-    /*0100*/ 0x40,
-    0x1F,
-    0x80,
-    0x68,
-    0x00,
-    0x00,
-    0x00,
-    0x00,
-    0x40,
-    0x1F,
-    0x80,
-    0x6C,
-    0x00,
-    0x00,
-    0x00,
-    0x00,
-    /*0110*/ 0x40,
-    0x1F,
-    0x80,
-    0x70,
-    0x00,
-    0x00,
-    0x00,
-    0x00,
-    0x40,
-    0x1F,
-    0x80,
-    0x74,
-    0x00,
-    0x00,
-    0x00,
-    0x00,
-    /*0120*/ 0x40,
-    0x1F,
-    0x80,
-    0x78,
-    0x00,
-    0x00,
-    0x00,
-    0x00,
-    0x40,
-    0x1F,
-    0x80,
-    0x7C,
-    0x00,
-    0x00,
-    0x00,
-    0x00,
-    /*0130*/ 0x40,
-    0x1F,
-    0x80,
-    0x80,
-    0x00,
-    0x00,
-    0x00,
-    0x00,
-    0x40,
-    0x1F,
-    0x80,
-    0x84,
-    0x00,
-    0x00,
-    0x00,
-    0x00,
-    /*0140*/ 0x40,
-    0x1F,
-    0x80,
-    0x88,
-    0x00,
-    0x00,
-    0x00,
-    0x00,
-    0x40,
-    0x1F,
-    0x80,
-    0x8C,
-    0x00,
-    0x00,
-    0x00,
-    0x00,
-    /*0150*/ 0x40,
-    0x1F,
-    0x80,
-    0x90,
-    0x00,
-    0x00,
-    0x00,
-    0x00,
-    0x40,
-    0x1F,
-    0x80,
-    0x94,
-    0x00,
-    0x00,
-    0x00,
-    0x00,
-    /*0160*/ 0x40,
-    0x1F,
-    0x80,
-    0x98,
-    0x00,
-    0x00,
-    0x00,
-    0x00,
-    0x40,
-    0x1F,
-    0x80,
-    0x9C,
-    0x00,
-    0x00,
-    0x00,
-    0x00,
-    /*0170*/ 0x40,
-    0x1F,
-    0x80,
-    0xA0,
-    0x00,
-    0x00,
-    0x00,
-    0x00,
-    0x40,
-    0x1F,
-    0x80,
-    0xA4,
-    0x00,
-    0x00,
-    0x00,
-    0x00,
-    /*0180*/ 0x40,
-    0x1F,
-    0x80,
-    0xA8,
-    0x00,
-    0x00,
-    0x00,
-    0x00,
-    0x40,
-    0x1F,
-    0x80,
-    0xAC,
-    0x00,
-    0x00,
-    0x00,
-    0x00,
-    /*0190*/ 0x40,
-    0x1F,
-    0x80,
-    0xB0,
-    0x00,
-    0x00,
-    0x00,
-    0x10,
-    0x40,
-    0x1F,
-    0x80,
-    0xB4,
-    0x00,
-    0x00,
-    0x00,
-    0x00,
-    /*01a0*/ 0x40,
-    0x1F,
-    0x80,
-    0xB8,
-    0x00,
-    0x00,
-    0x00,
-    0x00,
-    0x40,
-    0x1F,
-    0x82,
-    0x04,
-    0x00,
-    0x01,
-    0x10,
-    0xF9,
-    /*01b0*/ 0x40,
-    0x1F,
-    0x82,
-    0x08,
-    0x00,
-    0x01,
-    0x10,
-    0xF9,
-    0x40,
-    0x1F,
-    0x82,
-    0x0C,
-    0x00,
-    0x01,
-    0x10,
-    0xF9,
-    /*01c0*/ 0x40,
-    0x1F,
-    0x82,
-    0x10,
-    0x00,
-    0x01,
-    0x10,
-    0xF9,
-    0x40,
-    0x1F,
-    0x82,
-    0x14,
-    0x00,
-    0x01,
-    0x10,
-    0xF9,
-    /*01d0*/ 0x40,
-    0x1F,
-    0x82,
-    0x18,
-    0x00,
-    0x01,
-    0x10,
-    0xF9,
-    0x40,
-    0x1F,
-    0x82,
-    0x1C,
-    0x00,
-    0x01,
-    0x10,
-    0xF9,
-    /*01e0*/ 0x40,
-    0x1F,
-    0x82,
-    0x20,
-    0x00,
-    0x01,
-    0x10,
-    0xF9,
-    0x40,
-    0x1F,
-    0x82,
-    0x24,
-    0x00,
-    0x01,
-    0x10,
-    0xF9,
-    /*01f0*/ 0x40,
-    0x1F,
-    0x82,
-    0x28,
-    0x00,
-    0x01,
-    0x10,
-    0xF9,
-    0x40,
-    0x1F,
-    0x82,
-    0x2C,
-    0x00,
-    0x01,
-    0x10,
-    0xF9,
-    /*0200*/ 0x40,
-    0x1F,
-    0x82,
-    0x30,
-    0x00,
-    0x01,
-    0x10,
-    0xF9,
-    0x40,
-    0x1F,
-    0x82,
-    0x34,
-    0x00,
-    0x01,
-    0x10,
-    0xF9,
-    /*0210*/ 0x40,
-    0x1F,
-    0x82,
-    0x38,
-    0x00,
-    0x01,
-    0x10,
-    0xF9,
-    0x40,
-    0x1F,
-    0x82,
-    0x3C,
-    0x00,
-    0x01,
-    0x10,
-    0xF9,
-    /*0220*/ 0x40,
-    0x1F,
-    0x82,
-    0x40,
-    0x00,
-    0x01,
-    0x10,
-    0xF9,
-    0x40,
-    0x1F,
-    0x82,
-    0x44,
-    0x00,
-    0x01,
-    0x10,
-    0xF9,
-    /*0230*/ 0x40,
-    0x1F,
-    0x82,
-    0x48,
-    0x00,
-    0x01,
-    0x10,
-    0xF9,
-    0x40,
-    0x1F,
-    0x82,
-    0x4C,
-    0x00,
-    0x01,
-    0x10,
-    0xF9,
-    /*0240*/ 0x40,
-    0x1F,
-    0x82,
-    0x50,
-    0x00,
-    0x01,
-    0x10,
-    0xF9,
-    0x40,
-    0x1F,
-    0x82,
-    0x54,
-    0x00,
-    0x01,
-    0x10,
-    0xF9,
-    /*0250*/ 0x40,
-    0x1F,
-    0x82,
-    0x58,
-    0x00,
-    0x01,
-    0x10,
-    0xF9,
-    0x40,
-    0x1F,
-    0x82,
-    0x5C,
-    0x00,
-    0x01,
-    0x10,
-    0xF9,
-    /*0260*/ 0x40,
-    0x1F,
-    0x82,
-    0x60,
-    0x00,
-    0x01,
-    0x10,
-    0xF9,
-    0x40,
-    0x1F,
-    0x82,
-    0x64,
-    0x00,
-    0x01,
-    0x10,
-    0xF9,
-    /*0270*/ 0x40,
-    0x1F,
-    0x82,
-    0x68,
-    0x00,
-    0x01,
-    0x10,
-    0xF9,
-    0x40,
-    0x1F,
-    0x82,
-    0x6C,
-    0x00,
-    0x01,
-    0x10,
-    0xF9,
-    /*0280*/ 0x40,
-    0x1F,
-    0x82,
-    0x70,
-    0x00,
-    0x01,
-    0x10,
-    0xF9,
-    0x40,
-    0x1F,
-    0x82,
-    0x74,
-    0x00,
-    0x01,
-    0x10,
-    0xF9,
-    /*0290*/ 0x40,
-    0x1F,
-    0x82,
-    0x78,
-    0x00,
-    0x01,
-    0x10,
-    0xF9,
-    0x40,
-    0x1F,
-    0x82,
-    0x7C,
-    0x00,
-    0x01,
-    0x10,
-    0xF9,
-    /*02a0*/ 0x40,
-    0x1F,
-    0x82,
-    0x80,
-    0x00,
-    0x01,
-    0x10,
-    0xF9,
-    0x40,
-    0x1F,
-    0x82,
-    0x84,
-    0x00,
-    0x01,
-    0x10,
-    0xF9,
-    /*02b0*/ 0x40,
-    0x1F,
-    0x82,
-    0x88,
-    0x00,
-    0x01,
-    0x10,
-    0xF9,
-    0x40,
-    0x1F,
-    0x82,
-    0x8C,
-    0x00,
-    0x01,
-    0x10,
-    0xF9,
-    /*02c0*/ 0x40,
-    0x1F,
-    0x82,
-    0x90,
-    0x00,
-    0x01,
-    0x10,
-    0xF9,
-    0x40,
-    0x1F,
-    0x82,
-    0x94,
-    0x00,
-    0x01,
-    0x10,
-    0xF9,
-    /*02d0*/ 0x40,
-    0x1F,
-    0x82,
-    0x98,
-    0x00,
-    0x01,
-    0x10,
-    0xF9,
-    0x40,
-    0x1F,
-    0x82,
-    0x9C,
-    0x00,
-    0x01,
-    0x10,
-    0xF9,
-    /*02e0*/ 0x40,
-    0x1F,
-    0x82,
-    0xA0,
-    0x00,
-    0x01,
-    0x10,
-    0xF9,
-    0x40,
-    0x1F,
-    0x82,
-    0xA4,
-    0x00,
-    0x01,
-    0x10,
-    0xF9,
-    /*02f0*/ 0x40,
-    0x1F,
-    0x82,
-    0xA8,
-    0x00,
-    0x01,
-    0x10,
-    0xF9,
-    0x40,
-    0x2F,
-    0x00,
-    0x00,
-    0x10,
-    0x00,
-    0x00,
-    0x04,
-    /*0300*/ 0x40,
-    0x2F,
-    0x00,
-    0x08,
-    0x00,
-    0x03,
-    0x05,
-    0x24,
-    0x40,
-    0x2F,
-    0x00,
-    0x0C,
-    0x06,
-    0x03,
-    0x05,
-    0x24,
-    /*0310*/ 0x40,
-    0x2F,
-    0x00,
-    0x10,
-    0x80,
-    0x00,
-    0x00,
-    0x1B,
-    0x40,
-    0x2F,
-    0x00,
-    0x14,
-    0x82,
-    0x00,
-    0x00,
-    0x1B,
-    /*0320*/ 0x40,
-    0x2F,
-    0x00,
-    0x18,
-    0x84,
-    0x00,
-    0x00,
-    0x1B,
-    0x40,
-    0x2F,
-    0x00,
-    0x1C,
-    0x86,
-    0x00,
-    0x00,
-    0x1B,
-    /*0330*/ 0x40,
-    0x2F,
-    0x00,
-    0x20,
-    0x90,
-    0x00,
-    0x00,
-    0x21,
-    0x40,
-    0x2F,
-    0x00,
-    0x24,
-    0xA0,
-    0x00,
-    0x00,
-    0x19,
-    /*0340*/ 0x40,
-    0x2F,
-    0x00,
-    0x28,
-    0xA8,
-    0x00,
-    0x00,
-    0x17,
-    0x40,
-    0x2F,
-    0x00,
-    0x2C,
-    0xA9,
-    0x00,
-    0x00,
-    0x1B,
-    /*0350*/ 0x40,
-    0x2F,
-    0x00,
-    0x30,
-    0x00,
-    0x00,
-    0x00,
-    0x21,
-    0x40,
-    0x2F,
-    0x00,
-    0x04,
-    0x00,
-    0x00,
-    0x79,
-    0xA8,
-    /*0360*/ 0x40,
-    0x2F,
-    0x00,
-    0x40,
-    0x00,
-    0x00,
-    0x0F,
-    0x31,
-    0x40,
-    0x2F,
-    0x00,
-    0x44,
-    0x00,
-    0x65,
-    0x29,
-    0x22,
-    /*0370*/ 0x40,
-    0x2F,
-    0x00,
-    0x48,
-    0x00,
-    0x01,
-    0x09,
-    0x20,
-    0x40,
-    0x2F,
-    0x00,
-    0x4C,
-    0x50,
-    0x21,
-    0x0A,
-    0x08,
-    /*0380*/ 0x40,
-    0x2F,
-    0x00,
-    0x80,
-    0x00,
-    0x00,
-    0x00,
-    0x21,
-    0x40,
-    0x2F,
-    0x00,
-    0x84,
-    0x00,
-    0x88,
-    0x88,
-    0x88,
-    /*0390*/ 0x40,
-    0x2F,
-    0x00,
-    0x94,
-    0x00,
-    0x00,
-    0x00,
-    0x02,
-    0x40,
-    0x2F,
-    0x00,
-    0x98,
-    0x00,
-    0x00,
-    0x00,
-    0x00,
-    /*03a0*/ 0x40,
-    0x2F,
-    0x00,
-    0x90,
-    0x80,
-    0x00,
-    0x00,
-    0x00,
-    0x40,
-    0x2F,
-    0x00,
-    0x9C,
-    0xA5,
-    0x5A,
-    0x00,
-    0x0F,
-    /*03b0*/ 0xCF,
-    0x00,
-    0x0C,
-    0x1C,
-    0x40,
-    0x2F,
-    0x00,
-    0x3C,
-    0x00,
-    0x00,
-    0x00,
-    0x01,
-    0xCC,
-    0x00,
-    0x14,
-    0x04,
-    /*03c0*/ 0x40,
-    0x2F,
-    0x00,
-    0x90,
-    0x80,
-    0x00,
-    0x00,
-    0x00,
-    0x40,
-    0x2F,
-    0x00,
-    0x9C,
-    0xA5,
-    0x5A,
-    0x00,
-    0x0C,
-    /*03d0*/ 0xCF,
-    0x00,
-    0x0C,
-    0x1C,
-    0x40,
-    0x2F,
-    0x00,
-    0x3C,
-    0x00,
-    0x00,
-    0x00,
-    0x01,
-    0xCC,
-    0x00,
-    0x14,
-    0x04,
-    /*03e0*/ 0x40,
-    0x2F,
-    0x00,
-    0x90,
-    0x80,
-    0x00,
-    0x00,
-    0x00,
-    0x40,
-    0x2F,
-    0x00,
-    0x9C,
-    0xA5,
-    0x5A,
-    0x00,
-    0x0C,
-    /*03f0*/ 0xCF,
-    0x00,
-    0x0C,
-    0x1C,
-    0x40,
-    0x2F,
-    0x00,
-    0x3C,
-    0x00,
-    0x00,
-    0x00,
-    0x01,
-    0xCC,
-    0x00,
-    0x1C,
-    0x04,
-    /*0400*/ 0x40,
-    0x2F,
-    0x00,
-    0xA0,
-    0x00,
-    0x00,
-    0x00,
-    0x33,
-    0x40,
-    0x2F,
-    0x00,
-    0x90,
-    0x80,
-    0x00,
-    0x00,
-    0x00,
-    /*0410*/ 0x40,
-    0x2F,
-    0x00,
-    0x9C,
-    0xA5,
-    0x5A,
-    0x00,
-    0x0A,
-    0xCF,
-    0x00,
-    0x0C,
-    0x1C,
-    0x40,
-    0x2F,
-    0x00,
-    0x3C,
-    /*0420*/ 0x00,
-    0x00,
-    0x00,
-    0x01,
-    0xCC,
-    0x00,
-    0x0C,
-    0x04,
-    0x40,
-    0x2F,
-    0x00,
-    0x4C,
-    0x50,
-    0x21,
-    0x0A,
-    0x09,
-};
+
+    /* COMMANDS */
+
+    /* group: 'Imported Commands' */
+    /* #1.1-117, command header bytes for merged 'Write - value' command */
+    0xCC, 0x03, 0xAC, 0x04,
+    /* #1.1, command: write_value, address: CCM_CCGR0, value: 0xFFFFFFFF, size: 4 */
+    0x40, 0x0F, 0xC0, 0x68, 0xFF, 0xFF, 0xFF, 0xFF,
+    /* #1.2, command: write_value, address: CCM_CCGR1, value: 0xFFFFFFFF, size: 4 */
+    0x40, 0x0F, 0xC0, 0x6C, 0xFF, 0xFF, 0xFF, 0xFF,
+    /* #1.3, command: write_value, address: CCM_CCGR2, value: 0xFFFFFFFF, size: 4 */
+    0x40, 0x0F, 0xC0, 0x70, 0xFF, 0xFF, 0xFF, 0xFF,
+    /* #1.4, command: write_value, address: CCM_CCGR3, value: 0xFFFFFFFF, size: 4 */
+    0x40, 0x0F, 0xC0, 0x74, 0xFF, 0xFF, 0xFF, 0xFF,
+    /* #1.5, command: write_value, address: CCM_CCGR4, value: 0xFFFFFFFF, size: 4 */
+    0x40, 0x0F, 0xC0, 0x78, 0xFF, 0xFF, 0xFF, 0xFF,
+    /* #1.6, command: write_value, address: CCM_CCGR5, value: 0xFFFFFFFF, size: 4 */
+    0x40, 0x0F, 0xC0, 0x7C, 0xFF, 0xFF, 0xFF, 0xFF,
+    /* #1.7, command: write_value, address: CCM_CCGR6, value: 0xFFFFFFFF, size: 4 */
+    0x40, 0x0F, 0xC0, 0x80, 0xFF, 0xFF, 0xFF, 0xFF,
+    /* #1.8, command: write_value, address: CCM_ANALOG_PLL_SYS, value: 0x2001, size: 4 */
+    0x40, 0x0D, 0x80, 0x30, 0x00, 0x00, 0x20, 0x01,
+    /* #1.9, command: write_value, address: CCM_ANALOG_PFD_528, value: 0x1D0000, size: 4 */
+    0x40, 0x0D, 0x81, 0x00, 0x00, 0x1D, 0x00, 0x00,
+    /* #1.10, command: write_value, address: CCM_CBCDR, value: 0x10D40, size: 4 */
+    0x40, 0x0F, 0xC0, 0x14, 0x00, 0x01, 0x0D, 0x40,
+    /* #1.11, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_00, value: 0x00, size: 4 */
+    0x40, 0x1F, 0x80, 0x14, 0x00, 0x00, 0x00, 0x00,
+    /* #1.12, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_01, value: 0x00, size: 4 */
+    0x40, 0x1F, 0x80, 0x18, 0x00, 0x00, 0x00, 0x00,
+    /* #1.13, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_02, value: 0x00, size: 4 */
+    0x40, 0x1F, 0x80, 0x1C, 0x00, 0x00, 0x00, 0x00,
+    /* #1.14, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_03, value: 0x00, size: 4 */
+    0x40, 0x1F, 0x80, 0x20, 0x00, 0x00, 0x00, 0x00,
+    /* #1.15, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04, value: 0x00, size: 4 */
+    0x40, 0x1F, 0x80, 0x24, 0x00, 0x00, 0x00, 0x00,
+    /* #1.16, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05, value: 0x00, size: 4 */
+    0x40, 0x1F, 0x80, 0x28, 0x00, 0x00, 0x00, 0x00,
+    /* #1.17, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06, value: 0x00, size: 4 */
+    0x40, 0x1F, 0x80, 0x2C, 0x00, 0x00, 0x00, 0x00,
+    /* #1.18, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_07, value: 0x00, size: 4 */
+    0x40, 0x1F, 0x80, 0x30, 0x00, 0x00, 0x00, 0x00,
+    /* #1.19, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_08, value: 0x00, size: 4 */
+    0x40, 0x1F, 0x80, 0x34, 0x00, 0x00, 0x00, 0x00,
+    /* #1.20, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_09, value: 0x00, size: 4 */
+    0x40, 0x1F, 0x80, 0x38, 0x00, 0x00, 0x00, 0x00,
+    /* #1.21, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_10, value: 0x00, size: 4 */
+    0x40, 0x1F, 0x80, 0x3C, 0x00, 0x00, 0x00, 0x00,
+    /* #1.22, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_11, value: 0x00, size: 4 */
+    0x40, 0x1F, 0x80, 0x40, 0x00, 0x00, 0x00, 0x00,
+    /* #1.23, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_12, value: 0x00, size: 4 */
+    0x40, 0x1F, 0x80, 0x44, 0x00, 0x00, 0x00, 0x00,
+    /* #1.24, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_13, value: 0x00, size: 4 */
+    0x40, 0x1F, 0x80, 0x48, 0x00, 0x00, 0x00, 0x00,
+    /* #1.25, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_14, value: 0x00, size: 4 */
+    0x40, 0x1F, 0x80, 0x4C, 0x00, 0x00, 0x00, 0x00,
+    /* #1.26, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_15, value: 0x00, size: 4 */
+    0x40, 0x1F, 0x80, 0x50, 0x00, 0x00, 0x00, 0x00,
+    /* #1.27, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_16, value: 0x00, size: 4 */
+    0x40, 0x1F, 0x80, 0x54, 0x00, 0x00, 0x00, 0x00,
+    /* #1.28, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_17, value: 0x00, size: 4 */
+    0x40, 0x1F, 0x80, 0x58, 0x00, 0x00, 0x00, 0x00,
+    /* #1.29, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_18, value: 0x00, size: 4 */
+    0x40, 0x1F, 0x80, 0x5C, 0x00, 0x00, 0x00, 0x00,
+    /* #1.30, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_19, value: 0x00, size: 4 */
+    0x40, 0x1F, 0x80, 0x60, 0x00, 0x00, 0x00, 0x00,
+    /* #1.31, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_20, value: 0x00, size: 4 */
+    0x40, 0x1F, 0x80, 0x64, 0x00, 0x00, 0x00, 0x00,
+    /* #1.32, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_21, value: 0x00, size: 4 */
+    0x40, 0x1F, 0x80, 0x68, 0x00, 0x00, 0x00, 0x00,
+    /* #1.33, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_22, value: 0x00, size: 4 */
+    0x40, 0x1F, 0x80, 0x6C, 0x00, 0x00, 0x00, 0x00,
+    /* #1.34, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_23, value: 0x00, size: 4 */
+    0x40, 0x1F, 0x80, 0x70, 0x00, 0x00, 0x00, 0x00,
+    /* #1.35, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_24, value: 0x00, size: 4 */
+    0x40, 0x1F, 0x80, 0x74, 0x00, 0x00, 0x00, 0x00,
+    /* #1.36, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_25, value: 0x00, size: 4 */
+    0x40, 0x1F, 0x80, 0x78, 0x00, 0x00, 0x00, 0x00,
+    /* #1.37, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_26, value: 0x00, size: 4 */
+    0x40, 0x1F, 0x80, 0x7C, 0x00, 0x00, 0x00, 0x00,
+    /* #1.38, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_27, value: 0x00, size: 4 */
+    0x40, 0x1F, 0x80, 0x80, 0x00, 0x00, 0x00, 0x00,
+    /* #1.39, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_28, value: 0x00, size: 4 */
+    0x40, 0x1F, 0x80, 0x84, 0x00, 0x00, 0x00, 0x00,
+    /* #1.40, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_29, value: 0x00, size: 4 */
+    0x40, 0x1F, 0x80, 0x88, 0x00, 0x00, 0x00, 0x00,
+    /* #1.41, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_30, value: 0x00, size: 4 */
+    0x40, 0x1F, 0x80, 0x8C, 0x00, 0x00, 0x00, 0x00,
+    /* #1.42, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_31, value: 0x00, size: 4 */
+    0x40, 0x1F, 0x80, 0x90, 0x00, 0x00, 0x00, 0x00,
+    /* #1.43, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32, value: 0x00, size: 4 */
+    0x40, 0x1F, 0x80, 0x94, 0x00, 0x00, 0x00, 0x00,
+    /* #1.44, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_33, value: 0x00, size: 4 */
+    0x40, 0x1F, 0x80, 0x98, 0x00, 0x00, 0x00, 0x00,
+    /* #1.45, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_34, value: 0x00, size: 4 */
+    0x40, 0x1F, 0x80, 0x9C, 0x00, 0x00, 0x00, 0x00,
+    /* #1.46, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_35, value: 0x00, size: 4 */
+    0x40, 0x1F, 0x80, 0xA0, 0x00, 0x00, 0x00, 0x00,
+    /* #1.47, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_36, value: 0x00, size: 4 */
+    0x40, 0x1F, 0x80, 0xA4, 0x00, 0x00, 0x00, 0x00,
+    /* #1.48, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_37, value: 0x00, size: 4 */
+    0x40, 0x1F, 0x80, 0xA8, 0x00, 0x00, 0x00, 0x00,
+    /* #1.49, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_38, value: 0x00, size: 4 */
+    0x40, 0x1F, 0x80, 0xAC, 0x00, 0x00, 0x00, 0x00,
+    /* #1.50, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_39, value: 0x10, size: 4 */
+    0x40, 0x1F, 0x80, 0xB0, 0x00, 0x00, 0x00, 0x10,
+    /* #1.51, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_40, value: 0x00, size: 4 */
+    0x40, 0x1F, 0x80, 0xB4, 0x00, 0x00, 0x00, 0x00,
+    /* #1.52, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_41, value: 0x00, size: 4 */
+    0x40, 0x1F, 0x80, 0xB8, 0x00, 0x00, 0x00, 0x00,
+    /* #1.53, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_00, value: 0x110F9, size: 4 */
+    0x40, 0x1F, 0x82, 0x04, 0x00, 0x01, 0x10, 0xF9,
+    /* #1.54, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_01, value: 0x110F9, size: 4 */
+    0x40, 0x1F, 0x82, 0x08, 0x00, 0x01, 0x10, 0xF9,
+    /* #1.55, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_02, value: 0x110F9, size: 4 */
+    0x40, 0x1F, 0x82, 0x0C, 0x00, 0x01, 0x10, 0xF9,
+    /* #1.56, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_03, value: 0x110F9, size: 4 */
+    0x40, 0x1F, 0x82, 0x10, 0x00, 0x01, 0x10, 0xF9,
+    /* #1.57, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_04, value: 0x110F9, size: 4 */
+    0x40, 0x1F, 0x82, 0x14, 0x00, 0x01, 0x10, 0xF9,
+    /* #1.58, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_05, value: 0x110F9, size: 4 */
+    0x40, 0x1F, 0x82, 0x18, 0x00, 0x01, 0x10, 0xF9,
+    /* #1.59, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_06, value: 0x110F9, size: 4 */
+    0x40, 0x1F, 0x82, 0x1C, 0x00, 0x01, 0x10, 0xF9,
+    /* #1.60, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_07, value: 0x110F9, size: 4 */
+    0x40, 0x1F, 0x82, 0x20, 0x00, 0x01, 0x10, 0xF9,
+    /* #1.61, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_08, value: 0x110F9, size: 4 */
+    0x40, 0x1F, 0x82, 0x24, 0x00, 0x01, 0x10, 0xF9,
+    /* #1.62, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_09, value: 0x110F9, size: 4 */
+    0x40, 0x1F, 0x82, 0x28, 0x00, 0x01, 0x10, 0xF9,
+    /* #1.63, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_10, value: 0x110F9, size: 4 */
+    0x40, 0x1F, 0x82, 0x2C, 0x00, 0x01, 0x10, 0xF9,
+    /* #1.64, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_11, value: 0x110F9, size: 4 */
+    0x40, 0x1F, 0x82, 0x30, 0x00, 0x01, 0x10, 0xF9,
+    /* #1.65, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_12, value: 0x110F9, size: 4 */
+    0x40, 0x1F, 0x82, 0x34, 0x00, 0x01, 0x10, 0xF9,
+    /* #1.66, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_13, value: 0x110F9, size: 4 */
+    0x40, 0x1F, 0x82, 0x38, 0x00, 0x01, 0x10, 0xF9,
+    /* #1.67, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_14, value: 0x110F9, size: 4 */
+    0x40, 0x1F, 0x82, 0x3C, 0x00, 0x01, 0x10, 0xF9,
+    /* #1.68, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_15, value: 0x110F9, size: 4 */
+    0x40, 0x1F, 0x82, 0x40, 0x00, 0x01, 0x10, 0xF9,
+    /* #1.69, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_16, value: 0x110F9, size: 4 */
+    0x40, 0x1F, 0x82, 0x44, 0x00, 0x01, 0x10, 0xF9,
+    /* #1.70, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_17, value: 0x110F9, size: 4 */
+    0x40, 0x1F, 0x82, 0x48, 0x00, 0x01, 0x10, 0xF9,
+    /* #1.71, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_18, value: 0x110F9, size: 4 */
+    0x40, 0x1F, 0x82, 0x4C, 0x00, 0x01, 0x10, 0xF9,
+    /* #1.72, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_19, value: 0x110F9, size: 4 */
+    0x40, 0x1F, 0x82, 0x50, 0x00, 0x01, 0x10, 0xF9,
+    /* #1.73, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_20, value: 0x110F9, size: 4 */
+    0x40, 0x1F, 0x82, 0x54, 0x00, 0x01, 0x10, 0xF9,
+    /* #1.74, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_21, value: 0x110F9, size: 4 */
+    0x40, 0x1F, 0x82, 0x58, 0x00, 0x01, 0x10, 0xF9,
+    /* #1.75, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_22, value: 0x110F9, size: 4 */
+    0x40, 0x1F, 0x82, 0x5C, 0x00, 0x01, 0x10, 0xF9,
+    /* #1.76, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_23, value: 0x110F9, size: 4 */
+    0x40, 0x1F, 0x82, 0x60, 0x00, 0x01, 0x10, 0xF9,
+    /* #1.77, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_24, value: 0x110F9, size: 4 */
+    0x40, 0x1F, 0x82, 0x64, 0x00, 0x01, 0x10, 0xF9,
+    /* #1.78, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_25, value: 0x110F9, size: 4 */
+    0x40, 0x1F, 0x82, 0x68, 0x00, 0x01, 0x10, 0xF9,
+    /* #1.79, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_26, value: 0x110F9, size: 4 */
+    0x40, 0x1F, 0x82, 0x6C, 0x00, 0x01, 0x10, 0xF9,
+    /* #1.80, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_27, value: 0x110F9, size: 4 */
+    0x40, 0x1F, 0x82, 0x70, 0x00, 0x01, 0x10, 0xF9,
+    /* #1.81, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_28, value: 0x110F9, size: 4 */
+    0x40, 0x1F, 0x82, 0x74, 0x00, 0x01, 0x10, 0xF9,
+    /* #1.82, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_29, value: 0x110F9, size: 4 */
+    0x40, 0x1F, 0x82, 0x78, 0x00, 0x01, 0x10, 0xF9,
+    /* #1.83, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_30, value: 0x110F9, size: 4 */
+    0x40, 0x1F, 0x82, 0x7C, 0x00, 0x01, 0x10, 0xF9,
+    /* #1.84, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_31, value: 0x110F9, size: 4 */
+    0x40, 0x1F, 0x82, 0x80, 0x00, 0x01, 0x10, 0xF9,
+    /* #1.85, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_32, value: 0x110F9, size: 4 */
+    0x40, 0x1F, 0x82, 0x84, 0x00, 0x01, 0x10, 0xF9,
+    /* #1.86, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_33, value: 0x110F9, size: 4 */
+    0x40, 0x1F, 0x82, 0x88, 0x00, 0x01, 0x10, 0xF9,
+    /* #1.87, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_34, value: 0x110F9, size: 4 */
+    0x40, 0x1F, 0x82, 0x8C, 0x00, 0x01, 0x10, 0xF9,
+    /* #1.88, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_35, value: 0x110F9, size: 4 */
+    0x40, 0x1F, 0x82, 0x90, 0x00, 0x01, 0x10, 0xF9,
+    /* #1.89, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_36, value: 0x110F9, size: 4 */
+    0x40, 0x1F, 0x82, 0x94, 0x00, 0x01, 0x10, 0xF9,
+    /* #1.90, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_37, value: 0x110F9, size: 4 */
+    0x40, 0x1F, 0x82, 0x98, 0x00, 0x01, 0x10, 0xF9,
+    /* #1.91, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_38, value: 0x110F9, size: 4 */
+    0x40, 0x1F, 0x82, 0x9C, 0x00, 0x01, 0x10, 0xF9,
+    /* #1.92, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_39, value: 0x110F9, size: 4 */
+    0x40, 0x1F, 0x82, 0xA0, 0x00, 0x01, 0x10, 0xF9,
+    /* #1.93, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_40, value: 0x110F9, size: 4 */
+    0x40, 0x1F, 0x82, 0xA4, 0x00, 0x01, 0x10, 0xF9,
+    /* #1.94, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_41, value: 0x110F9, size: 4 */
+    0x40, 0x1F, 0x82, 0xA8, 0x00, 0x01, 0x10, 0xF9,
+    /* #1.95, command: write_value, address: SEMC_MCR, value: 0x10000004, size: 4 */
+    0x40, 0x2F, 0x00, 0x00, 0x10, 0x00, 0x00, 0x04,
+    /* #1.96, command: write_value, address: SEMC_BMCR0, value: 0x30524, size: 4 */
+    0x40, 0x2F, 0x00, 0x08, 0x00, 0x00, 0x00, 0x81,
+    /* #1.97, command: write_value, address: SEMC_BMCR1, value: 0x6030524, size: 4 */
+    0x40, 0x2F, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x81,
+    /* #1.98, command: write_value, address: SEMC_BR0, value: 0x8000001B, size: 4 */
+    0x40, 0x2F, 0x00, 0x10, 0x80, 0x00, 0x00, 0x1B,
+    /* #1.99, command: write_value, address: SEMC_BR1, value: 0x8200001B, size: 4 */
+    0x40, 0x2F, 0x00, 0x14, 0x82, 0x00, 0x00, 0x1B,
+    /* #1.100, command: write_value, address: SEMC_BR2, value: 0x8400001B, size: 4 */
+    0x40, 0x2F, 0x00, 0x18, 0x84, 0x00, 0x00, 0x1B,
+    /* #1.101, command: write_value, address: SEMC_BR3, value: 0x8600001B, size: 4 */
+    0x40, 0x2F, 0x00, 0x1C, 0x86, 0x00, 0x00, 0x1B,
+    /* #1.102, command: write_value, address: SEMC_BR4, value: 0x90000021, size: 4 */
+    0x40, 0x2F, 0x00, 0x20, 0x90, 0x00, 0x00, 0x21,
+    /* #1.103, command: write_value, address: SEMC_BR5, value: 0xA0000019, size: 4 */
+    0x40, 0x2F, 0x00, 0x24, 0xA0, 0x00, 0x00, 0x19,
+    /* #1.104, command: write_value, address: SEMC_BR6, value: 0xA8000017, size: 4 */
+    0x40, 0x2F, 0x00, 0x28, 0xA8, 0x00, 0x00, 0x17,
+    /* #1.105, command: write_value, address: SEMC_BR7, value: 0xA900001B, size: 4 */
+    0x40, 0x2F, 0x00, 0x2C, 0xA9, 0x00, 0x00, 0x1B,
+    /* #1.106, command: write_value, address: SEMC_BR8, value: 0x21, size: 4 */
+    0x40, 0x2F, 0x00, 0x30, 0x00, 0x00, 0x00, 0x21,
+    /* #1.107, command: write_value, address: SEMC_IOCR, value: 0x79A8, size: 4 */
+    0x40, 0x2F, 0x00, 0x04, 0x00, 0x00, 0x79, 0xA8,
+    /* #1.108, command: write_value, address: SEMC_SDRAMCR0, value: 0xF31, size: 4 */
+    0x40, 0x2F, 0x00, 0x40, 0x00, 0x00, 0x0F, 0x31,
+    /* #1.109, command: write_value, address: SEMC_SDRAMCR1, value: 0x652922, size: 4 */
+    0x40, 0x2F, 0x00, 0x44, 0x00, 0x65, 0x29, 0x22,
+    /* #1.110, command: write_value, address: SEMC_SDRAMCR2, value: 0x10920, size: 4 */
+    0x40, 0x2F, 0x00, 0x48, 0x00, 0x01, 0x09, 0x20,
+    /* #1.111, command: write_value, address: SEMC_SDRAMCR3, value: 0x50210A08, size: 4 */
+    0x40, 0x2F, 0x00, 0x4C, 0x50, 0x21, 0x0A, 0x08,
+    /* #1.112, command: write_value, address: SEMC_DBICR0, value: 0x21, size: 4 */
+    0x40, 0x2F, 0x00, 0x80, 0x00, 0x00, 0x00, 0x21,
+    /* #1.113, command: write_value, address: SEMC_DBICR1, value: 0x888888, size: 4 */
+    0x40, 0x2F, 0x00, 0x84, 0x00, 0x88, 0x88, 0x88,
+    /* #1.114, command: write_value, address: SEMC_IPCR1, value: 0x02, size: 4 */
+    0x40, 0x2F, 0x00, 0x94, 0x00, 0x00, 0x00, 0x02,
+    /* #1.115, command: write_value, address: SEMC_IPCR2, value: 0x00, size: 4 */
+    0x40, 0x2F, 0x00, 0x98, 0x00, 0x00, 0x00, 0x00,
+    /* #1.116, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */
+    0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00,
+    /* #1.117, command: write_value, address: SEMC_IPCMD, value: 0xA55A000F, size: 4 */
+    0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0F,
+    /* #2, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */
+    0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01,
+    /* #3.1-2, command header bytes for merged 'Write - value' command */
+    0xCC, 0x00, 0x14, 0x04,
+    /* #3.1, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */
+    0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00,
+    /* #3.2, command: write_value, address: SEMC_IPCMD, value: 0xA55A000C, size: 4 */
+    0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0C,
+    /* #4, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */
+    0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01,
+    /* #5.1-2, command header bytes for merged 'Write - value' command */
+    0xCC, 0x00, 0x14, 0x04,
+    /* #5.1, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */
+    0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00,
+    /* #5.2, command: write_value, address: SEMC_IPCMD, value: 0xA55A000C, size: 4 */
+    0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0C,
+    /* #6, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */
+    0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01,
+    /* #7.1-3, command header bytes for merged 'Write - value' command */
+    0xCC, 0x00, 0x1C, 0x04,
+    /* #7.1, command: write_value, address: SEMC_IPTXDAT, value: 0x33, size: 4 */
+    0x40, 0x2F, 0x00, 0xA0, 0x00, 0x00, 0x00, 0x33,
+    /* #7.2, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */
+    0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00,
+    /* #7.3, command: write_value, address: SEMC_IPCMD, value: 0xA55A000A, size: 4 */
+    0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0A,
+    /* #8, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */
+    0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01,
+    /* #9, command: write_value, address: SEMC_SDRAMCR3, value: 0x50210A09, size: 4 */
+    0xCC, 0x00, 0x0C, 0x04, 0x40, 0x2F, 0x00, 0x4C, 0x50, 0x21, 0x0A, 0x09};
+/* BE CAREFUL MODIFYING THIS SETTINGS - IT IS YAML SETTINGS FOR TOOLS */
+
 #else
-/*************************************
- *  DCD Data
- *************************************/
 const uint8_t dcd_data[] = {0x00};
 #endif /* XIP_BOOT_HEADER_DCD_ENABLE */
 #endif /* XIP_BOOT_HEADER_ENABLE */
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/xip/evkbimxrt1050_sdram_ini_dcd.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/xip/evkbimxrt1050_sdram_ini_dcd.h
index 51fa34e5991..7f57e7c1d7b 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/xip/evkbimxrt1050_sdram_ini_dcd.h
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/xip/evkbimxrt1050_sdram_ini_dcd.h
@@ -1,47 +1,32 @@
 /*
- * The Clear BSD License
- * Copyright 2017 NXP
+ * Copyright 2017-2019 NXP
  * All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- * that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef __EVKBIMXRT1050_DCD_SDRAM_INIT__
-#define __EVKBIMXRT1050_DCD_SDRAM_INIT__
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+#ifndef __EVKBIMXRT1050_SDRAM_INI_DCD__
+#define __EVKBIMXRT1050_SDRAM_INI_DCD__
 
 #include <stdint.h>
 
+/*! @name Driver version */
+/*@{*/
+/*! @brief XIP_BOARD driver version 2.0.0. */
+#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*@}*/
+
 /*************************************
  *  DCD Data
  *************************************/
 #define DCD_TAG_HEADER (0xD2)
+#define DCD_VERSION (0x41)
 #define DCD_TAG_HEADER_SHIFT (24)
-#define DCD_VERSION (0x40)
 #define DCD_ARRAY_SIZE 1
 
-#endif /* __EVKBIMXRT1050_DCD_SDRAM_INIT__ */
+#endif /* __EVKBIMXRT1050_SDRAM_INI_DCD__ */
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/MIMXRT1052.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/MIMXRT1052.h
index 0399bc70709..bfb48c9b9e9 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/MIMXRT1052.h
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/MIMXRT1052.h
@@ -5,52 +5,24 @@
 **                          MIMXRT1052DVJ6B
 **                          MIMXRT1052DVL6B
 **
-**     Compilers:           Keil ARM C/C++ Compiler
-**                          Freescale C/C++ for Embedded ARM
+**     Compilers:           Freescale C/C++ for Embedded ARM
 **                          GNU C Compiler
 **                          IAR ANSI C/C++ Compiler for ARM
+**                          Keil ARM C/C++ Compiler
 **                          MCUXpresso Compiler
 **
-**     Reference manual:    IMXRT1050RM Rev.1, 03/2018
-**     Version:             rev. 0.1, 2017-01-10
-**     Build:               b180509
+**     Reference manual:    IMXRT1050RM Rev.2.1, 12/2018 | IMXRT1050SRM Rev.2
+**     Version:             rev. 1.3, 2019-04-29
+**     Build:               b190429
 **
 **     Abstract:
 **         CMSIS Peripheral Access Layer for MIMXRT1052
 **
-**     The Clear BSD License
 **     Copyright 1997-2016 Freescale Semiconductor, Inc.
-**     Copyright 2016-2018 NXP
+**     Copyright 2016-2019 NXP
 **     All rights reserved.
 **
-**     Redistribution and use in source and binary forms, with or without
-**     modification, are permitted (subject to the limitations in the
-**     disclaimer below) provided that the following conditions are met:
-**
-**     * Redistributions of source code must retain the above copyright
-**       notice, this list of conditions and the following disclaimer.
-**
-**     * Redistributions in binary form must reproduce the above copyright
-**       notice, this list of conditions and the following disclaimer in the
-**       documentation and/or other materials provided with the distribution.
-**
-**     * Neither the name of the copyright holder nor the names of its
-**       contributors may be used to endorse or promote products derived from
-**       this software without specific prior written permission.
-**
-**     NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
-**     GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
-**     HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
-**     WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-**     MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-**     LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-**     CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-**     SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
-**     BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-**     WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
-**     OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
-**     IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**     SPDX-License-Identifier: BSD-3-Clause
 **
 **     http:                 www.nxp.com
 **     mail:                 support@nxp.com
@@ -58,14 +30,24 @@
 **     Revisions:
 **     - rev. 0.1 (2017-01-10)
 **         Initial version.
+**     - rev. 1.0 (2018-09-21)
+**         Update interrupt vector table and dma request source.
+**         Update register BEE_ADDR_OFFSET1's bitfield name to ADDR_OFFSET1.
+**         Split GPIO_COMBINED_IRQS to GPIO_COMBINED_LOW_IRQS and GPIO_COMBINED_HIGH_IRQS.
+**     - rev. 1.1 (2018-11-16)
+**         Update header files to align with IMXRT1050RM Rev.1.
+**     - rev. 1.2 (2018-11-27)
+**         Update header files to align with IMXRT1050RM Rev.2.1.
+**     - rev. 1.3 (2019-04-29)
+**         Add SET/CLR/TOG register group to register CTRL, STAT, CHANNELCTRL, CH0STAT, CH0OPTS, CH1STAT, CH1OPTS, CH2STAT, CH2OPTS, CH3STAT, CH3OPTS of DCP module.
 **
 ** ###################################################################
 */
 
 /*!
  * @file MIMXRT1052.h
- * @version 0.1
- * @date 2017-01-10
+ * @version 1.3
+ * @date 2019-04-29
  * @brief CMSIS Peripheral Access Layer for MIMXRT1052
  *
  * CMSIS Peripheral Access Layer for MIMXRT1052
@@ -76,9 +58,9 @@
 
 /** Memory map major version (memory maps with equal major version number are
  * compatible) */
-#define MCU_MEM_MAP_VERSION 0x0000U
+#define MCU_MEM_MAP_VERSION 0x0100U
 /** Memory map minor version */
-#define MCU_MEM_MAP_VERSION_MINOR 0x0001U
+#define MCU_MEM_MAP_VERSION_MINOR 0x0003U
 
 
 /* ----------------------------------------------------------------------------
@@ -91,7 +73,7 @@
  */
 
 /** Interrupt Number Definitions */
-#define NUMBER_OF_INT_VECTORS 176                /**< Number of interrupts in the Vector table */
+#define NUMBER_OF_INT_VECTORS 168                /**< Number of interrupts in the Vector table */
 
 typedef enum IRQn {
   /* Auxiliary constants */
@@ -170,10 +152,10 @@ typedef enum IRQn {
   SAI3_RX_IRQn                 = 58,               /**< SAI3 interrupt */
   SAI3_TX_IRQn                 = 59,               /**< SAI3 interrupt */
   SPDIF_IRQn                   = 60,               /**< SPDIF interrupt */
-  ANATOP_EVENT0_IRQn           = 61,               /**< ANATOP interrupt */
-  ANATOP_EVENT1_IRQn           = 62,               /**< ANATOP interrupt */
-  ANATOP_TAMP_LOW_HIGH_IRQn    = 63,               /**< ANATOP interrupt */
-  ANATOP_TEMP_PANIC_IRQn       = 64,               /**< ANATOP interrupt */
+  PMU_EVENT_IRQn               = 61,               /**< Brown-out event interrupt */
+  Reserved78_IRQn              = 62,               /**< Reserved interrupt */
+  TEMP_LOW_HIGH_IRQn           = 63,               /**< TempSensor low/high interrupt */
+  TEMP_PANIC_IRQn              = 64,               /**< TempSensor panic interrupt */
   USB_PHY1_IRQn                = 65,               /**< USBPHY (UTMI0), Interrupt */
   USB_PHY2_IRQn                = 66,               /**< USBPHY (UTMI0), Interrupt */
   ADC1_IRQn                    = 67,               /**< ADC1 interrupt */
@@ -260,15 +242,7 @@ typedef enum IRQn {
   PWM4_1_IRQn                  = 148,              /**< PWM4 capture 1, compare 1, or reload 0 interrupt */
   PWM4_2_IRQn                  = 149,              /**< PWM4 capture 2, compare 2, or reload 0 interrupt */
   PWM4_3_IRQn                  = 150,              /**< PWM4 capture 3, compare 3, or reload 0 interrupt */
-  PWM4_FAULT_IRQn              = 151,              /**< PWM4 fault or reload error interrupt */
-  Reserved168_IRQn             = 152,              /**< Reserved interrupt */
-  Reserved169_IRQn             = 153,              /**< Reserved interrupt */
-  Reserved170_IRQn             = 154,              /**< Reserved interrupt */
-  Reserved171_IRQn             = 155,              /**< Reserved interrupt */
-  Reserved172_IRQn             = 156,              /**< Reserved interrupt */
-  Reserved173_IRQn             = 157,              /**< Reserved interrupt */
-  SJC_ARM_DEBUG_IRQn           = 158,              /**< SJC ARM debug interrupt */
-  NMI_WAKEUP_IRQn              = 159               /**< NMI wake up */
+  PWM4_FAULT_IRQn              = 151               /**< PWM4 fault or reload error interrupt */
 } IRQn_Type;
 
 /*!
@@ -313,21 +287,24 @@ typedef enum IRQn {
 /** Mapping Information */
 /*!
  * @addtogroup edma_request
- * @{ */
+ * @{
+ */
 
 /*******************************************************************************
  * Definitions
-*******************************************************************************/
+ ******************************************************************************/
 
 /*!
- * @brief Enumeration for the DMA0 hardware request
+ * @brief Structure for the DMA hardware request
  *
- * Defines the enumeration for the DMA0 hardware request collections.
+ * Defines the structure for the DMA hardware request collections. The user can configure the
+ * hardware request into DMAMUX to trigger the DMA transfer accordingly. The index
+ * of the hardware request varies according  to the to SoC.
  */
 typedef enum _dma_request_source
 {
-    kDmaRequestMuxFlexIO1Request0Request1 = 0|0x100U, /**< FlexIO1 */
-    kDmaRequestMuxFlexIO2Request0Request1 = 1|0x100U, /**< FlexIO2 */
+    kDmaRequestMuxFlexIO1Request0Request1 = 0|0x100U, /**< FlexIO1 Request0 and Request1 */
+    kDmaRequestMuxFlexIO2Request0Request1 = 1|0x100U, /**< FlexIO2 Request0 and Request1 */
     kDmaRequestMuxLPUART1Tx         = 2|0x100U,    /**< LPUART1 Transmit */
     kDmaRequestMuxLPUART1Rx         = 3|0x100U,    /**< LPUART1 Receive */
     kDmaRequestMuxLPUART3Tx         = 4|0x100U,    /**< LPUART3 Transmit */
@@ -343,14 +320,14 @@ typedef enum _dma_request_source
     kDmaRequestMuxLPSPI3Tx          = 16|0x100U,   /**< LPSPI3 Transmit */
     kDmaRequestMuxLPI2C1            = 17|0x100U,   /**< LPI2C1 */
     kDmaRequestMuxLPI2C3            = 18|0x100U,   /**< LPI2C3 */
-    kDmaRequestMuxSai1Rx            = 19|0x100U,   /**< Sai1 Receive */
-    kDmaRequestMuxSai1Tx            = 20|0x100U,   /**< Sai1 Transmit */
-    kDmaRequestMuxSai2Rx            = 21|0x100U,   /**< Sai2 Receive */
-    kDmaRequestMuxSai2Tx            = 22|0x100U,   /**< Sai2 Transmit */
+    kDmaRequestMuxSai1Rx            = 19|0x100U,   /**< SAI1 Receive */
+    kDmaRequestMuxSai1Tx            = 20|0x100U,   /**< SAI1 Transmit */
+    kDmaRequestMuxSai2Rx            = 21|0x100U,   /**< SAI2 Receive */
+    kDmaRequestMuxSai2Tx            = 22|0x100U,   /**< SAI2 Transmit */
     kDmaRequestMuxADC_ETC           = 23|0x100U,   /**< ADC_ETC */
     kDmaRequestMuxADC1              = 24|0x100U,   /**< ADC1 */
     kDmaRequestMuxACMP1             = 25|0x100U,   /**< ACMP1 */
-    kDmaRequestMuxACMP2             = 26|0x100U,   /**< ACMP2 */
+    kDmaRequestMuxACMP3             = 26|0x100U,   /**< ACMP3 */
     kDmaRequestMuxFlexSPIRx         = 28|0x100U,   /**< FlexSPI Receive */
     kDmaRequestMuxFlexSPITx         = 29|0x100U,   /**< FlexSPI Transmit */
     kDmaRequestMuxXBAR1Request0     = 30|0x100U,   /**< XBAR1 Request 0 */
@@ -371,20 +348,20 @@ typedef enum _dma_request_source
     kDmaRequestMuxFlexPWM3ValueSub1 = 45|0x100U,   /**< FlexPWM3 Value sub-module1 */
     kDmaRequestMuxFlexPWM3ValueSub2 = 46|0x100U,   /**< FlexPWM3 Value sub-module2 */
     kDmaRequestMuxFlexPWM3ValueSub3 = 47|0x100U,   /**< FlexPWM3 Value sub-module3 */
-    kDmaRequestMuxQTIMER1CaptTimer0 = 48|0x100U,   /**< QTIMER1 Capture timer 0 */
-    kDmaRequestMuxQTIMER1CaptTimer1 = 49|0x100U,   /**< QTIMER1 Capture timer 1 */
-    kDmaRequestMuxQTIMER1CaptTimer2 = 50|0x100U,   /**< QTIMER1 Capture timer 2 */
-    kDmaRequestMuxQTIMER1CaptTimer3 = 51|0x100U,   /**< QTIMER1 Capture timer 3 */
-    kDmaRequestMuxQTIMER1Cmpld1Timer0Cmpld2Timer1 = 52|0x100U, /**< QTIMER1 cmpld1 in timer 0 or cmpld2 in timer 1 */
-    kDmaRequestMuxQTIMER1Cmpld1Timer1Cmpld2Timer0 = 53|0x100U, /**< QTIMER1 cmpld1 in timer 1 or cmpld2 in timer 0 */
-    kDmaRequestMuxQTIMER1Cmpld1Timer2Cmpld2Timer3 = 54|0x100U, /**< QTIMER1 cmpld1 in timer 2 or cmpld2 in timer 3 */
-    kDmaRequestMuxQTIMER1Cmpld1Timer3Cmpld2Timer2 = 55|0x100U, /**< QTIMER1 cmpld1 in timer 3 or cmpld2 in timer 2 */
-    kDmaRequestMuxQTIMER3CaptTimer0Cmpld1Timer0Cmpld2Timer1 = 56|0x100U, /**< QTIMER3 capture timer 0, cmpld1 in timer 0 or cmpld2 in timer 1 */
-    kDmaRequestMuxQTIMER3CaptTimer1Cmpld1Timer0Cmpld2Timer1 = 57|0x100U, /**< QTIMER3 capture timer 1, cmpld1 in timer 0 or cmpld2 in timer 1 */
-    kDmaRequestMuxQTIMER3CaptTimer2Cmpld1Timer0Cmpld2Timer1 = 58|0x100U, /**< QTIMER3 capture timer 2, cmpld1 in timer 0 or cmpld2 in timer 1 */
-    kDmaRequestMuxQTIMER3CaptTimer3Cmpld1Timer0Cmpld2Timer1 = 59|0x100U, /**< QTIMER3 capture timer 3, cmpld1 in timer 0 or cmpld2 in timer 1 */
-    kDmaRequestMuxFlexIO1Request2Request3 = 64|0x100U, /**< FlexIO1 */
-    kDmaRequestMuxFlexIO2Request2Request3 = 65|0x100U, /**< FlexIO2 */
+    kDmaRequestMuxQTIMER1CaptTimer0 = 48|0x100U,   /**< TMR1 Capture timer 0 */
+    kDmaRequestMuxQTIMER1CaptTimer1 = 49|0x100U,   /**< TMR1 Capture timer 1 */
+    kDmaRequestMuxQTIMER1CaptTimer2 = 50|0x100U,   /**< TMR1 Capture timer 2 */
+    kDmaRequestMuxQTIMER1CaptTimer3 = 51|0x100U,   /**< TMR1 Capture timer 3 */
+    kDmaRequestMuxQTIMER1Cmpld1Timer0Cmpld2Timer1 = 52|0x100U, /**< TMR1 cmpld1 in timer 0 or cmpld2 in timer 1 */
+    kDmaRequestMuxQTIMER1Cmpld1Timer1Cmpld2Timer0 = 53|0x100U, /**< TMR1 cmpld1 in timer 1 or cmpld2 in timer 0 */
+    kDmaRequestMuxQTIMER1Cmpld1Timer2Cmpld2Timer3 = 54|0x100U, /**< TMR1 cmpld1 in timer 2 or cmpld2 in timer 3 */
+    kDmaRequestMuxQTIMER1Cmpld1Timer3Cmpld2Timer2 = 55|0x100U, /**< TMR1 cmpld1 in timer 3 or cmpld2 in timer 2 */
+    kDmaRequestMuxQTIMER3CaptTimer0Cmpld1Timer0Cmpld2Timer1 = 56|0x100U, /**< TMR3 capture timer 0, cmpld1 in timer 0 or cmpld2 in timer 1 */
+    kDmaRequestMuxQTIMER3CaptTimer1Cmpld1Timer1Cmpld2Timer0 = 57|0x100U, /**< TMR3 capture timer 1, cmpld1 in timer 1 or cmpld2 in timer 0 */
+    kDmaRequestMuxQTIMER3CaptTimer2Cmpld1Timer2Cmpld2Timer3 = 58|0x100U, /**< TMR3 capture timer 2, cmpld1 in timer 2 or cmpld2 in timer 3 */
+    kDmaRequestMuxQTIMER3CaptTimer3Cmpld1Timer3Cmpld2Timer2 = 59|0x100U, /**< TMR3 capture timer 3, cmpld1 in timer 3 or cmpld2 in timer 2 */
+    kDmaRequestMuxFlexIO1Request2Request3 = 64|0x100U, /**< FlexIO1 Request2 and Request3 */
+    kDmaRequestMuxFlexIO2Request2Request3 = 65|0x100U, /**< FlexIO2 Request2 and Request3 */
     kDmaRequestMuxLPUART2Tx         = 66|0x100U,   /**< LPUART2 Transmit */
     kDmaRequestMuxLPUART2Rx         = 67|0x100U,   /**< LPUART2 Receive */
     kDmaRequestMuxLPUART4Tx         = 68|0x100U,   /**< LPUART4 Transmit */
@@ -401,15 +378,15 @@ typedef enum _dma_request_source
     kDmaRequestMuxLPSPI4Tx          = 80|0x100U,   /**< LPSPI4 Transmit */
     kDmaRequestMuxLPI2C2            = 81|0x100U,   /**< LPI2C2 */
     kDmaRequestMuxLPI2C4            = 82|0x100U,   /**< LPI2C4 */
-    kDmaRequestMuxSai3Rx            = 83|0x100U,   /**< Sai3 Receive */
-    kDmaRequestMuxSai3Tx            = 84|0x100U,   /**< Sai3 Transmit */
-    kDmaRequestMuxSpdifRx           = 85|0x100U,   /**< Spdif Receive */
-    kDmaRequestMuxSpdifTx           = 86|0x100U,   /**< Spdif Transmit */
+    kDmaRequestMuxSai3Rx            = 83|0x100U,   /**< SAI3 Receive */
+    kDmaRequestMuxSai3Tx            = 84|0x100U,   /**< SAI3 Transmit */
+    kDmaRequestMuxSpdifRx           = 85|0x100U,   /**< SPDIF Receive */
+    kDmaRequestMuxSpdifTx           = 86|0x100U,   /**< SPDIF Transmit */
     kDmaRequestMuxADC2              = 88|0x100U,   /**< ADC2 */
-    kDmaRequestMuxACMP3             = 89|0x100U,   /**< ACMP3 */
+    kDmaRequestMuxACMP2             = 89|0x100U,   /**< ACMP2 */
     kDmaRequestMuxACMP4             = 90|0x100U,   /**< ACMP4 */
-    kDmaRequestMuxEnetTimer0        = 92|0x100U,   /**< Enet Timer0 */
-    kDmaRequestMuxEnetTimer1        = 93|0x100U,   /**< Enet Timer1 */
+    kDmaRequestMuxEnetTimer0        = 92|0x100U,   /**< ENET Timer0 */
+    kDmaRequestMuxEnetTimer1        = 93|0x100U,   /**< ENET Timer1 */
     kDmaRequestMuxXBAR1Request2     = 94|0x100U,   /**< XBAR1 Request 2 */
     kDmaRequestMuxXBAR1Request3     = 95|0x100U,   /**< XBAR1 Request 3 */
     kDmaRequestMuxFlexPWM2CaptureSub0 = 96|0x100U, /**< FlexPWM2 Capture sub-module0 */
@@ -428,18 +405,18 @@ typedef enum _dma_request_source
     kDmaRequestMuxFlexPWM4ValueSub1 = 109|0x100U,  /**< FlexPWM4 Value sub-module1 */
     kDmaRequestMuxFlexPWM4ValueSub2 = 110|0x100U,  /**< FlexPWM4 Value sub-module2 */
     kDmaRequestMuxFlexPWM4ValueSub3 = 111|0x100U,  /**< FlexPWM4 Value sub-module3 */
-    kDmaRequestMuxQTIMER2CaptTimer0 = 112|0x100U,  /**< QTIMER2 Capture timer 0 */
-    kDmaRequestMuxQTIMER2CaptTimer1 = 113|0x100U,  /**< QTIMER2 Capture timer 1 */
-    kDmaRequestMuxQTIMER2CaptTimer2 = 114|0x100U,  /**< QTIMER2 Capture timer 2 */
-    kDmaRequestMuxQTIMER2CaptTimer3 = 115|0x100U,  /**< QTIMER2 Capture timer 3 */
-    kDmaRequestMuxQTIMER2Cmpld1Timer0Cmpld2Timer1 = 116|0x100U, /**< QTIMER2 cmpld1 in timer 0 or cmpld2 in timer 1 */
-    kDmaRequestMuxQTIMER2Cmpld1Timer1Cmpld2Timer0 = 117|0x100U, /**< QTIMER2 cmpld1 in timer 1 or cmpld2 in timer 0 */
-    kDmaRequestMuxQTIMER2Cmpld1Timer2Cmpld2Timer3 = 118|0x100U, /**< QTIMER2 cmpld1 in timer 2 or cmpld2 in timer 3 */
-    kDmaRequestMuxQTIMER2Cmpld1Timer3Cmpld2Timer2 = 119|0x100U, /**< QTIMER2 cmpld1 in timer 3 or cmpld2 in timer 2 */
-    kDmaRequestMuxQTIMER4CaptTimer0Cmpld1Timer0Cmpld2Timer1 = 120|0x100U, /**< QTIMER4 capture timer 0, cmpld1 in timer 0 or cmpld2 in timer 1 */
-    kDmaRequestMuxQTIMER4CaptTimer1Cmpld1Timer0Cmpld2Timer1 = 121|0x100U, /**< QTIMER4 capture timer 1, cmpld1 in timer 0 or cmpld2 in timer 1 */
-    kDmaRequestMuxQTIMER4CaptTimer2Cmpld1Timer0Cmpld2Timer1 = 122|0x100U, /**< QTIMER4 capture timer 2, cmpld1 in timer 0 or cmpld2 in timer 1 */
-    kDmaRequestMuxQTIMER4CaptTimer3Cmpld1Timer0Cmpld2Timer1 = 123|0x100U, /**< QTIMER4 capture timer 3, cmpld1 in timer 0 or cmpld2 in timer 1 */
+    kDmaRequestMuxQTIMER2CaptTimer0 = 112|0x100U,  /**< TMR2 Capture timer 0 */
+    kDmaRequestMuxQTIMER2CaptTimer1 = 113|0x100U,  /**< TMR2 Capture timer 1 */
+    kDmaRequestMuxQTIMER2CaptTimer2 = 114|0x100U,  /**< TMR2 Capture timer 2 */
+    kDmaRequestMuxQTIMER2CaptTimer3 = 115|0x100U,  /**< TMR2 Capture timer 3 */
+    kDmaRequestMuxQTIMER2Cmpld1Timer0Cmpld2Timer1 = 116|0x100U, /**< TMR2 cmpld1 in timer 0 or cmpld2 in timer 1 */
+    kDmaRequestMuxQTIMER2Cmpld1Timer1Cmpld2Timer0 = 117|0x100U, /**< TMR2 cmpld1 in timer 1 or cmpld2 in timer 0 */
+    kDmaRequestMuxQTIMER2Cmpld1Timer2Cmpld2Timer3 = 118|0x100U, /**< TMR2 cmpld1 in timer 2 or cmpld2 in timer 3 */
+    kDmaRequestMuxQTIMER2Cmpld1Timer3Cmpld2Timer2 = 119|0x100U, /**< TMR2 cmpld1 in timer 3 or cmpld2 in timer 2 */
+    kDmaRequestMuxQTIMER4CaptTimer0Cmpld1Timer0Cmpld2Timer1 = 120|0x100U, /**< TMR4 capture timer 0, cmpld1 in timer 0 or cmpld2 in timer 1 */
+    kDmaRequestMuxQTIMER4CaptTimer1Cmpld1Timer1Cmpld2Timer0 = 121|0x100U, /**< TMR4 capture timer 1, cmpld1 in timer 1 or cmpld2 in timer 0 */
+    kDmaRequestMuxQTIMER4CaptTimer2Cmpld1Timer2Cmpld2Timer3 = 122|0x100U, /**< TMR4 capture timer 2, cmpld1 in timer 2 or cmpld2 in timer 3 */
+    kDmaRequestMuxQTIMER4CaptTimer3Cmpld1Timer3Cmpld2Timer2 = 123|0x100U, /**< TMR4 capture timer 3, cmpld1 in timer 3 or cmpld2 in timer 2 */
 } dma_request_source_t;
 
 /* @} */
@@ -1341,9 +1318,21 @@ typedef struct {
 /*! @{ */
 #define ADC_HC_ADCH_MASK                         (0x1FU)
 #define ADC_HC_ADCH_SHIFT                        (0U)
+/*! ADCH - Input Channel Select
+ *  0b10000..External channel selection from ADC_ETC
+ *  0b11000..Reserved.
+ *  0b11001..VREFSH = internal channel, for ADC self-test, hard connected to VRH internally
+ *  0b11010..Reserved.
+ *  0b11011..Reserved.
+ *  0b11111..Conversion Disabled. Hardware Triggers will not initiate any conversion.
+ */
 #define ADC_HC_ADCH(x)                           (((uint32_t)(((uint32_t)(x)) << ADC_HC_ADCH_SHIFT)) & ADC_HC_ADCH_MASK)
 #define ADC_HC_AIEN_MASK                         (0x80U)
 #define ADC_HC_AIEN_SHIFT                        (7U)
+/*! AIEN - Conversion Complete Interrupt Enable/Disable Control
+ *  0b1..Conversion complete interrupt enabled
+ *  0b0..Conversion complete interrupt disabled
+ */
 #define ADC_HC_AIEN(x)                           (((uint32_t)(((uint32_t)(x)) << ADC_HC_AIEN_SHIFT)) & ADC_HC_AIEN_MASK)
 /*! @} */
 
@@ -1371,36 +1360,92 @@ typedef struct {
 /*! @{ */
 #define ADC_CFG_ADICLK_MASK                      (0x3U)
 #define ADC_CFG_ADICLK_SHIFT                     (0U)
+/*! ADICLK - Input Clock Select
+ *  0b00..IPG clock
+ *  0b01..IPG clock divided by 2
+ *  0b10..Reserved
+ *  0b11..Asynchronous clock (ADACK)
+ */
 #define ADC_CFG_ADICLK(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADICLK_SHIFT)) & ADC_CFG_ADICLK_MASK)
 #define ADC_CFG_MODE_MASK                        (0xCU)
 #define ADC_CFG_MODE_SHIFT                       (2U)
+/*! MODE - Conversion Mode Selection
+ *  0b00..8-bit conversion
+ *  0b01..10-bit conversion
+ *  0b10..12-bit conversion
+ *  0b11..Reserved
+ */
 #define ADC_CFG_MODE(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_CFG_MODE_SHIFT)) & ADC_CFG_MODE_MASK)
 #define ADC_CFG_ADLSMP_MASK                      (0x10U)
 #define ADC_CFG_ADLSMP_SHIFT                     (4U)
+/*! ADLSMP - Long Sample Time Configuration
+ *  0b0..Short sample mode.
+ *  0b1..Long sample mode.
+ */
 #define ADC_CFG_ADLSMP(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADLSMP_SHIFT)) & ADC_CFG_ADLSMP_MASK)
 #define ADC_CFG_ADIV_MASK                        (0x60U)
 #define ADC_CFG_ADIV_SHIFT                       (5U)
+/*! ADIV - Clock Divide Select
+ *  0b00..Input clock
+ *  0b01..Input clock / 2
+ *  0b10..Input clock / 4
+ *  0b11..Input clock / 8
+ */
 #define ADC_CFG_ADIV(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADIV_SHIFT)) & ADC_CFG_ADIV_MASK)
 #define ADC_CFG_ADLPC_MASK                       (0x80U)
 #define ADC_CFG_ADLPC_SHIFT                      (7U)
+/*! ADLPC - Low-Power Configuration
+ *  0b0..ADC hard block not in low power mode.
+ *  0b1..ADC hard block in low power mode.
+ */
 #define ADC_CFG_ADLPC(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADLPC_SHIFT)) & ADC_CFG_ADLPC_MASK)
 #define ADC_CFG_ADSTS_MASK                       (0x300U)
 #define ADC_CFG_ADSTS_SHIFT                      (8U)
+/*! ADSTS
+ *  0b00..Sample period (ADC clocks) = 2 if ADLSMP=0b Sample period (ADC clocks) = 12 if ADLSMP=1b
+ *  0b01..Sample period (ADC clocks) = 4 if ADLSMP=0b Sample period (ADC clocks) = 16 if ADLSMP=1b
+ *  0b10..Sample period (ADC clocks) = 6 if ADLSMP=0b Sample period (ADC clocks) = 20 if ADLSMP=1b
+ *  0b11..Sample period (ADC clocks) = 8 if ADLSMP=0b Sample period (ADC clocks) = 24 if ADLSMP=1b
+ */
 #define ADC_CFG_ADSTS(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADSTS_SHIFT)) & ADC_CFG_ADSTS_MASK)
 #define ADC_CFG_ADHSC_MASK                       (0x400U)
 #define ADC_CFG_ADHSC_SHIFT                      (10U)
+/*! ADHSC - High Speed Configuration
+ *  0b0..Normal conversion selected.
+ *  0b1..High speed conversion selected.
+ */
 #define ADC_CFG_ADHSC(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADHSC_SHIFT)) & ADC_CFG_ADHSC_MASK)
 #define ADC_CFG_REFSEL_MASK                      (0x1800U)
 #define ADC_CFG_REFSEL_SHIFT                     (11U)
+/*! REFSEL - Voltage Reference Selection
+ *  0b00..Selects VREFH/VREFL as reference voltage.
+ *  0b01..Reserved
+ *  0b10..Reserved
+ *  0b11..Reserved
+ */
 #define ADC_CFG_REFSEL(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK)
 #define ADC_CFG_ADTRG_MASK                       (0x2000U)
 #define ADC_CFG_ADTRG_SHIFT                      (13U)
+/*! ADTRG - Conversion Trigger Select
+ *  0b0..Software trigger selected
+ *  0b1..Hardware trigger selected
+ */
 #define ADC_CFG_ADTRG(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADTRG_SHIFT)) & ADC_CFG_ADTRG_MASK)
 #define ADC_CFG_AVGS_MASK                        (0xC000U)
 #define ADC_CFG_AVGS_SHIFT                       (14U)
+/*! AVGS - Hardware Average select
+ *  0b00..4 samples averaged
+ *  0b01..8 samples averaged
+ *  0b10..16 samples averaged
+ *  0b11..32 samples averaged
+ */
 #define ADC_CFG_AVGS(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_CFG_AVGS_SHIFT)) & ADC_CFG_AVGS_MASK)
 #define ADC_CFG_OVWREN_MASK                      (0x10000U)
 #define ADC_CFG_OVWREN_SHIFT                     (16U)
+/*! OVWREN - Data Overwrite Enable
+ *  0b1..Enable the overwriting.
+ *  0b0..Disable the overwriting. Existing Data in Data result register will not be overwritten by subsequent converted data.
+ */
 #define ADC_CFG_OVWREN(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CFG_OVWREN_SHIFT)) & ADC_CFG_OVWREN_MASK)
 /*! @} */
 
@@ -1408,24 +1453,54 @@ typedef struct {
 /*! @{ */
 #define ADC_GC_ADACKEN_MASK                      (0x1U)
 #define ADC_GC_ADACKEN_SHIFT                     (0U)
+/*! ADACKEN - Asynchronous clock output enable
+ *  0b0..Asynchronous clock output disabled; Asynchronous clock only enabled if selected by ADICLK and a conversion is active.
+ *  0b1..Asynchronous clock and clock output enabled regardless of the state of the ADC
+ */
 #define ADC_GC_ADACKEN(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_GC_ADACKEN_SHIFT)) & ADC_GC_ADACKEN_MASK)
 #define ADC_GC_DMAEN_MASK                        (0x2U)
 #define ADC_GC_DMAEN_SHIFT                       (1U)
+/*! DMAEN - DMA Enable
+ *  0b0..DMA disabled (default)
+ *  0b1..DMA enabled
+ */
 #define ADC_GC_DMAEN(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_GC_DMAEN_SHIFT)) & ADC_GC_DMAEN_MASK)
 #define ADC_GC_ACREN_MASK                        (0x4U)
 #define ADC_GC_ACREN_SHIFT                       (2U)
+/*! ACREN - Compare Function Range Enable
+ *  0b0..Range function disabled. Only the compare value 1 of ADC_CV register (CV1) is compared.
+ *  0b1..Range function enabled. Both compare values of ADC_CV registers (CV1 and CV2) are compared.
+ */
 #define ADC_GC_ACREN(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACREN_SHIFT)) & ADC_GC_ACREN_MASK)
 #define ADC_GC_ACFGT_MASK                        (0x8U)
 #define ADC_GC_ACFGT_SHIFT                       (3U)
+/*! ACFGT - Compare Function Greater Than Enable
+ *  0b0..Configures "Less Than Threshold, Outside Range Not Inclusive and Inside Range Not Inclusive"
+ *       functionality based on the values placed in the ADC_CV register.
+ *  0b1..Configures "Greater Than Or Equal To Threshold, Outside Range Inclusive and Inside Range Inclusive"
+ *       functionality based on the values placed in the ADC_CV registers.
+ */
 #define ADC_GC_ACFGT(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACFGT_SHIFT)) & ADC_GC_ACFGT_MASK)
 #define ADC_GC_ACFE_MASK                         (0x10U)
 #define ADC_GC_ACFE_SHIFT                        (4U)
+/*! ACFE - Compare Function Enable
+ *  0b0..Compare function disabled
+ *  0b1..Compare function enabled
+ */
 #define ADC_GC_ACFE(x)                           (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACFE_SHIFT)) & ADC_GC_ACFE_MASK)
 #define ADC_GC_AVGE_MASK                         (0x20U)
 #define ADC_GC_AVGE_SHIFT                        (5U)
+/*! AVGE - Hardware average enable
+ *  0b0..Hardware average function disabled
+ *  0b1..Hardware average function enabled
+ */
 #define ADC_GC_AVGE(x)                           (((uint32_t)(((uint32_t)(x)) << ADC_GC_AVGE_SHIFT)) & ADC_GC_AVGE_MASK)
 #define ADC_GC_ADCO_MASK                         (0x40U)
 #define ADC_GC_ADCO_SHIFT                        (6U)
+/*! ADCO - Continuous Conversion Enable
+ *  0b0..One conversion or one set of conversions if the hardware average function is enabled (AVGE=1) after initiating a conversion.
+ *  0b1..Continuous conversions or sets of conversions if the hardware average function is enabled (AVGE=1) after initiating a conversion.
+ */
 #define ADC_GC_ADCO(x)                           (((uint32_t)(((uint32_t)(x)) << ADC_GC_ADCO_SHIFT)) & ADC_GC_ADCO_MASK)
 #define ADC_GC_CAL_MASK                          (0x80U)
 #define ADC_GC_CAL_SHIFT                         (7U)
@@ -1436,12 +1511,24 @@ typedef struct {
 /*! @{ */
 #define ADC_GS_ADACT_MASK                        (0x1U)
 #define ADC_GS_ADACT_SHIFT                       (0U)
+/*! ADACT - Conversion Active
+ *  0b0..Conversion not in progress.
+ *  0b1..Conversion in progress.
+ */
 #define ADC_GS_ADACT(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_GS_ADACT_SHIFT)) & ADC_GS_ADACT_MASK)
 #define ADC_GS_CALF_MASK                         (0x2U)
 #define ADC_GS_CALF_SHIFT                        (1U)
+/*! CALF - Calibration Failed Flag
+ *  0b0..Calibration completed normally.
+ *  0b1..Calibration failed. ADC accuracy specifications are not guaranteed.
+ */
 #define ADC_GS_CALF(x)                           (((uint32_t)(((uint32_t)(x)) << ADC_GS_CALF_SHIFT)) & ADC_GS_CALF_MASK)
 #define ADC_GS_AWKST_MASK                        (0x4U)
 #define ADC_GS_AWKST_SHIFT                       (2U)
+/*! AWKST - Asynchronous wakeup interrupt status
+ *  0b1..Asynchronous wake up interrupt occurred in stop mode.
+ *  0b0..No asynchronous interrupt.
+ */
 #define ADC_GS_AWKST(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_GS_AWKST_SHIFT)) & ADC_GS_AWKST_MASK)
 /*! @} */
 
@@ -1462,6 +1549,10 @@ typedef struct {
 #define ADC_OFS_OFS(x)                           (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK)
 #define ADC_OFS_SIGN_MASK                        (0x1000U)
 #define ADC_OFS_SIGN_SHIFT                       (12U)
+/*! SIGN - Sign bit
+ *  0b0..The offset value is added with the raw result
+ *  0b1..The offset value is subtracted from the raw converted value
+ */
 #define ADC_OFS_SIGN(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_OFS_SIGN_SHIFT)) & ADC_OFS_SIGN_MASK)
 /*! @} */
 
@@ -1992,18 +2083,63 @@ typedef struct {
 /*! @{ */
 #define AIPSTZ_MPR_MPROT5_MASK                   (0xF00U)
 #define AIPSTZ_MPR_MPROT5_SHIFT                  (8U)
+/*! MPROT5
+ *  0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute.
+ *  0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access.
+ *  0bxx0x..This master is not trusted for write accesses.
+ *  0bxx1x..This master is trusted for write accesses.
+ *  0bx0xx..This master is not trusted for read accesses.
+ *  0bx1xx..This master is trusted for read accesses.
+ *  0b1xxx..Write accesses from this master are allowed to be buffered
+ */
 #define AIPSTZ_MPR_MPROT5(x)                     (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT5_SHIFT)) & AIPSTZ_MPR_MPROT5_MASK)
 #define AIPSTZ_MPR_MPROT3_MASK                   (0xF0000U)
 #define AIPSTZ_MPR_MPROT3_SHIFT                  (16U)
+/*! MPROT3
+ *  0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute.
+ *  0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access.
+ *  0bxx0x..This master is not trusted for write accesses.
+ *  0bxx1x..This master is trusted for write accesses.
+ *  0bx0xx..This master is not trusted for read accesses.
+ *  0bx1xx..This master is trusted for read accesses.
+ *  0b1xxx..Write accesses from this master are allowed to be buffered
+ */
 #define AIPSTZ_MPR_MPROT3(x)                     (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT3_SHIFT)) & AIPSTZ_MPR_MPROT3_MASK)
 #define AIPSTZ_MPR_MPROT2_MASK                   (0xF00000U)
 #define AIPSTZ_MPR_MPROT2_SHIFT                  (20U)
+/*! MPROT2
+ *  0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute.
+ *  0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access.
+ *  0bxx0x..This master is not trusted for write accesses.
+ *  0bxx1x..This master is trusted for write accesses.
+ *  0bx0xx..This master is not trusted for read accesses.
+ *  0bx1xx..This master is trusted for read accesses.
+ *  0b1xxx..Write accesses from this master are allowed to be buffered
+ */
 #define AIPSTZ_MPR_MPROT2(x)                     (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT2_SHIFT)) & AIPSTZ_MPR_MPROT2_MASK)
 #define AIPSTZ_MPR_MPROT1_MASK                   (0xF000000U)
 #define AIPSTZ_MPR_MPROT1_SHIFT                  (24U)
+/*! MPROT1
+ *  0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute.
+ *  0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access.
+ *  0bxx0x..This master is not trusted for write accesses.
+ *  0bxx1x..This master is trusted for write accesses.
+ *  0bx0xx..This master is not trusted for read accesses.
+ *  0bx1xx..This master is trusted for read accesses.
+ *  0b1xxx..Write accesses from this master are allowed to be buffered
+ */
 #define AIPSTZ_MPR_MPROT1(x)                     (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT1_SHIFT)) & AIPSTZ_MPR_MPROT1_MASK)
 #define AIPSTZ_MPR_MPROT0_MASK                   (0xF0000000U)
 #define AIPSTZ_MPR_MPROT0_SHIFT                  (28U)
+/*! MPROT0
+ *  0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute.
+ *  0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access.
+ *  0bxx0x..This master is not trusted for write accesses.
+ *  0bxx1x..This master is trusted for write accesses.
+ *  0bx0xx..This master is not trusted for read accesses.
+ *  0bx1xx..This master is trusted for read accesses.
+ *  0b1xxx..Write accesses from this master are allowed to be buffered
+ */
 #define AIPSTZ_MPR_MPROT0(x)                     (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT0_SHIFT)) & AIPSTZ_MPR_MPROT0_MASK)
 /*! @} */
 
@@ -2011,27 +2147,139 @@ typedef struct {
 /*! @{ */
 #define AIPSTZ_OPACR_OPAC7_MASK                  (0xFU)
 #define AIPSTZ_OPACR_OPAC7_SHIFT                 (0U)
+/*! OPAC7
+ *  0bxxx0..Accesses from an untrusted master are allowed.
+ *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ *  0bxx0x..This peripheral allows write accesses.
+ *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ *          error response and no peripheral access is initiated on the IPS bus.
+ *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ *          on the IPS bus.
+ *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
 #define AIPSTZ_OPACR_OPAC7(x)                    (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC7_SHIFT)) & AIPSTZ_OPACR_OPAC7_MASK)
 #define AIPSTZ_OPACR_OPAC6_MASK                  (0xF0U)
 #define AIPSTZ_OPACR_OPAC6_SHIFT                 (4U)
+/*! OPAC6
+ *  0bxxx0..Accesses from an untrusted master are allowed.
+ *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ *  0bxx0x..This peripheral allows write accesses.
+ *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ *          error response and no peripheral access is initiated on the IPS bus.
+ *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ *          on the IPS bus.
+ *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
 #define AIPSTZ_OPACR_OPAC6(x)                    (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC6_SHIFT)) & AIPSTZ_OPACR_OPAC6_MASK)
 #define AIPSTZ_OPACR_OPAC5_MASK                  (0xF00U)
 #define AIPSTZ_OPACR_OPAC5_SHIFT                 (8U)
+/*! OPAC5
+ *  0bxxx0..Accesses from an untrusted master are allowed.
+ *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ *  0bxx0x..This peripheral allows write accesses.
+ *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ *          error response and no peripheral access is initiated on the IPS bus.
+ *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ *          on the IPS bus.
+ *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
 #define AIPSTZ_OPACR_OPAC5(x)                    (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC5_SHIFT)) & AIPSTZ_OPACR_OPAC5_MASK)
 #define AIPSTZ_OPACR_OPAC4_MASK                  (0xF000U)
 #define AIPSTZ_OPACR_OPAC4_SHIFT                 (12U)
+/*! OPAC4
+ *  0bxxx0..Accesses from an untrusted master are allowed.
+ *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ *  0bxx0x..This peripheral allows write accesses.
+ *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ *          error response and no peripheral access is initiated on the IPS bus.
+ *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ *          on the IPS bus.
+ *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
 #define AIPSTZ_OPACR_OPAC4(x)                    (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC4_SHIFT)) & AIPSTZ_OPACR_OPAC4_MASK)
 #define AIPSTZ_OPACR_OPAC3_MASK                  (0xF0000U)
 #define AIPSTZ_OPACR_OPAC3_SHIFT                 (16U)
+/*! OPAC3
+ *  0bxxx0..Accesses from an untrusted master are allowed.
+ *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ *  0bxx0x..This peripheral allows write accesses.
+ *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ *          error response and no peripheral access is initiated on the IPS bus.
+ *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ *          on the IPS bus.
+ *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
 #define AIPSTZ_OPACR_OPAC3(x)                    (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC3_SHIFT)) & AIPSTZ_OPACR_OPAC3_MASK)
 #define AIPSTZ_OPACR_OPAC2_MASK                  (0xF00000U)
 #define AIPSTZ_OPACR_OPAC2_SHIFT                 (20U)
+/*! OPAC2
+ *  0bxxx0..Accesses from an untrusted master are allowed.
+ *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ *  0bxx0x..This peripheral allows write accesses.
+ *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ *          error response and no peripheral access is initiated on the IPS bus.
+ *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ *          on the IPS bus.
+ *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
 #define AIPSTZ_OPACR_OPAC2(x)                    (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC2_SHIFT)) & AIPSTZ_OPACR_OPAC2_MASK)
 #define AIPSTZ_OPACR_OPAC1_MASK                  (0xF000000U)
 #define AIPSTZ_OPACR_OPAC1_SHIFT                 (24U)
+/*! OPAC1
+ *  0bxxx0..Accesses from an untrusted master are allowed.
+ *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ *  0bxx0x..This peripheral allows write accesses.
+ *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ *          error response and no peripheral access is initiated on the IPS bus.
+ *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ *          on the IPS bus.
+ *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
 #define AIPSTZ_OPACR_OPAC1(x)                    (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC1_SHIFT)) & AIPSTZ_OPACR_OPAC1_MASK)
 #define AIPSTZ_OPACR_OPAC0_MASK                  (0xF0000000U)
 #define AIPSTZ_OPACR_OPAC0_SHIFT                 (28U)
+/*! OPAC0
+ *  0bxxx0..Accesses from an untrusted master are allowed.
+ *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ *  0bxx0x..This peripheral allows write accesses.
+ *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ *          error response and no peripheral access is initiated on the IPS bus.
+ *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ *          on the IPS bus.
+ *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
 #define AIPSTZ_OPACR_OPAC0(x)                    (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC0_SHIFT)) & AIPSTZ_OPACR_OPAC0_MASK)
 /*! @} */
 
@@ -2039,27 +2287,139 @@ typedef struct {
 /*! @{ */
 #define AIPSTZ_OPACR1_OPAC15_MASK                (0xFU)
 #define AIPSTZ_OPACR1_OPAC15_SHIFT               (0U)
+/*! OPAC15
+ *  0bxxx0..Accesses from an untrusted master are allowed.
+ *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ *  0bxx0x..This peripheral allows write accesses.
+ *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ *          error response and no peripheral access is initiated on the IPS bus.
+ *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ *          on the IPS bus.
+ *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
 #define AIPSTZ_OPACR1_OPAC15(x)                  (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC15_SHIFT)) & AIPSTZ_OPACR1_OPAC15_MASK)
 #define AIPSTZ_OPACR1_OPAC14_MASK                (0xF0U)
 #define AIPSTZ_OPACR1_OPAC14_SHIFT               (4U)
+/*! OPAC14
+ *  0bxxx0..Accesses from an untrusted master are allowed.
+ *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ *  0bxx0x..This peripheral allows write accesses.
+ *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ *          error response and no peripheral access is initiated on the IPS bus.
+ *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ *          on the IPS bus.
+ *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
 #define AIPSTZ_OPACR1_OPAC14(x)                  (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC14_SHIFT)) & AIPSTZ_OPACR1_OPAC14_MASK)
 #define AIPSTZ_OPACR1_OPAC13_MASK                (0xF00U)
 #define AIPSTZ_OPACR1_OPAC13_SHIFT               (8U)
+/*! OPAC13
+ *  0bxxx0..Accesses from an untrusted master are allowed.
+ *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ *  0bxx0x..This peripheral allows write accesses.
+ *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ *          error response and no peripheral access is initiated on the IPS bus.
+ *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ *          on the IPS bus.
+ *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
 #define AIPSTZ_OPACR1_OPAC13(x)                  (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC13_SHIFT)) & AIPSTZ_OPACR1_OPAC13_MASK)
 #define AIPSTZ_OPACR1_OPAC12_MASK                (0xF000U)
 #define AIPSTZ_OPACR1_OPAC12_SHIFT               (12U)
+/*! OPAC12
+ *  0bxxx0..Accesses from an untrusted master are allowed.
+ *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ *  0bxx0x..This peripheral allows write accesses.
+ *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ *          error response and no peripheral access is initiated on the IPS bus.
+ *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ *          on the IPS bus.
+ *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
 #define AIPSTZ_OPACR1_OPAC12(x)                  (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC12_SHIFT)) & AIPSTZ_OPACR1_OPAC12_MASK)
 #define AIPSTZ_OPACR1_OPAC11_MASK                (0xF0000U)
 #define AIPSTZ_OPACR1_OPAC11_SHIFT               (16U)
+/*! OPAC11
+ *  0bxxx0..Accesses from an untrusted master are allowed.
+ *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ *  0bxx0x..This peripheral allows write accesses.
+ *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ *          error response and no peripheral access is initiated on the IPS bus.
+ *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ *          on the IPS bus.
+ *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
 #define AIPSTZ_OPACR1_OPAC11(x)                  (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC11_SHIFT)) & AIPSTZ_OPACR1_OPAC11_MASK)
 #define AIPSTZ_OPACR1_OPAC10_MASK                (0xF00000U)
 #define AIPSTZ_OPACR1_OPAC10_SHIFT               (20U)
+/*! OPAC10
+ *  0bxxx0..Accesses from an untrusted master are allowed.
+ *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ *  0bxx0x..This peripheral allows write accesses.
+ *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ *          error response and no peripheral access is initiated on the IPS bus.
+ *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ *          on the IPS bus.
+ *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
 #define AIPSTZ_OPACR1_OPAC10(x)                  (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC10_SHIFT)) & AIPSTZ_OPACR1_OPAC10_MASK)
 #define AIPSTZ_OPACR1_OPAC9_MASK                 (0xF000000U)
 #define AIPSTZ_OPACR1_OPAC9_SHIFT                (24U)
+/*! OPAC9
+ *  0bxxx0..Accesses from an untrusted master are allowed.
+ *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ *  0bxx0x..This peripheral allows write accesses.
+ *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ *          error response and no peripheral access is initiated on the IPS bus.
+ *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ *          on the IPS bus.
+ *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
 #define AIPSTZ_OPACR1_OPAC9(x)                   (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC9_SHIFT)) & AIPSTZ_OPACR1_OPAC9_MASK)
 #define AIPSTZ_OPACR1_OPAC8_MASK                 (0xF0000000U)
 #define AIPSTZ_OPACR1_OPAC8_SHIFT                (28U)
+/*! OPAC8
+ *  0bxxx0..Accesses from an untrusted master are allowed.
+ *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ *  0bxx0x..This peripheral allows write accesses.
+ *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ *          error response and no peripheral access is initiated on the IPS bus.
+ *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ *          on the IPS bus.
+ *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
 #define AIPSTZ_OPACR1_OPAC8(x)                   (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC8_SHIFT)) & AIPSTZ_OPACR1_OPAC8_MASK)
 /*! @} */
 
@@ -2067,27 +2427,139 @@ typedef struct {
 /*! @{ */
 #define AIPSTZ_OPACR2_OPAC23_MASK                (0xFU)
 #define AIPSTZ_OPACR2_OPAC23_SHIFT               (0U)
+/*! OPAC23
+ *  0bxxx0..Accesses from an untrusted master are allowed.
+ *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ *  0bxx0x..This peripheral allows write accesses.
+ *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ *          error response and no peripheral access is initiated on the IPS bus.
+ *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ *          on the IPS bus.
+ *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
 #define AIPSTZ_OPACR2_OPAC23(x)                  (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC23_SHIFT)) & AIPSTZ_OPACR2_OPAC23_MASK)
 #define AIPSTZ_OPACR2_OPAC22_MASK                (0xF0U)
 #define AIPSTZ_OPACR2_OPAC22_SHIFT               (4U)
+/*! OPAC22
+ *  0bxxx0..Accesses from an untrusted master are allowed.
+ *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ *  0bxx0x..This peripheral allows write accesses.
+ *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ *          error response and no peripheral access is initiated on the IPS bus.
+ *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ *          on the IPS bus.
+ *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
 #define AIPSTZ_OPACR2_OPAC22(x)                  (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC22_SHIFT)) & AIPSTZ_OPACR2_OPAC22_MASK)
 #define AIPSTZ_OPACR2_OPAC21_MASK                (0xF00U)
 #define AIPSTZ_OPACR2_OPAC21_SHIFT               (8U)
+/*! OPAC21
+ *  0bxxx0..Accesses from an untrusted master are allowed.
+ *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ *  0bxx0x..This peripheral allows write accesses.
+ *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ *          error response and no peripheral access is initiated on the IPS bus.
+ *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ *          on the IPS bus.
+ *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
 #define AIPSTZ_OPACR2_OPAC21(x)                  (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC21_SHIFT)) & AIPSTZ_OPACR2_OPAC21_MASK)
 #define AIPSTZ_OPACR2_OPAC20_MASK                (0xF000U)
 #define AIPSTZ_OPACR2_OPAC20_SHIFT               (12U)
+/*! OPAC20
+ *  0bxxx0..Accesses from an untrusted master are allowed.
+ *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ *  0bxx0x..This peripheral allows write accesses.
+ *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ *          error response and no peripheral access is initiated on the IPS bus.
+ *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ *          on the IPS bus.
+ *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
 #define AIPSTZ_OPACR2_OPAC20(x)                  (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC20_SHIFT)) & AIPSTZ_OPACR2_OPAC20_MASK)
 #define AIPSTZ_OPACR2_OPAC19_MASK                (0xF0000U)
 #define AIPSTZ_OPACR2_OPAC19_SHIFT               (16U)
+/*! OPAC19
+ *  0bxxx0..Accesses from an untrusted master are allowed.
+ *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ *  0bxx0x..This peripheral allows write accesses.
+ *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ *          error response and no peripheral access is initiated on the IPS bus.
+ *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ *          on the IPS bus.
+ *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
 #define AIPSTZ_OPACR2_OPAC19(x)                  (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC19_SHIFT)) & AIPSTZ_OPACR2_OPAC19_MASK)
 #define AIPSTZ_OPACR2_OPAC18_MASK                (0xF00000U)
 #define AIPSTZ_OPACR2_OPAC18_SHIFT               (20U)
+/*! OPAC18
+ *  0bxxx0..Accesses from an untrusted master are allowed.
+ *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ *  0bxx0x..This peripheral allows write accesses.
+ *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ *          error response and no peripheral access is initiated on the IPS bus.
+ *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ *          on the IPS bus.
+ *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
 #define AIPSTZ_OPACR2_OPAC18(x)                  (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC18_SHIFT)) & AIPSTZ_OPACR2_OPAC18_MASK)
 #define AIPSTZ_OPACR2_OPAC17_MASK                (0xF000000U)
 #define AIPSTZ_OPACR2_OPAC17_SHIFT               (24U)
+/*! OPAC17
+ *  0bxxx0..Accesses from an untrusted master are allowed.
+ *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ *  0bxx0x..This peripheral allows write accesses.
+ *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ *          error response and no peripheral access is initiated on the IPS bus.
+ *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ *          on the IPS bus.
+ *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
 #define AIPSTZ_OPACR2_OPAC17(x)                  (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC17_SHIFT)) & AIPSTZ_OPACR2_OPAC17_MASK)
 #define AIPSTZ_OPACR2_OPAC16_MASK                (0xF0000000U)
 #define AIPSTZ_OPACR2_OPAC16_SHIFT               (28U)
+/*! OPAC16
+ *  0bxxx0..Accesses from an untrusted master are allowed.
+ *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ *  0bxx0x..This peripheral allows write accesses.
+ *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ *          error response and no peripheral access is initiated on the IPS bus.
+ *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ *          on the IPS bus.
+ *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
 #define AIPSTZ_OPACR2_OPAC16(x)                  (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC16_SHIFT)) & AIPSTZ_OPACR2_OPAC16_MASK)
 /*! @} */
 
@@ -2095,27 +2567,139 @@ typedef struct {
 /*! @{ */
 #define AIPSTZ_OPACR3_OPAC31_MASK                (0xFU)
 #define AIPSTZ_OPACR3_OPAC31_SHIFT               (0U)
+/*! OPAC31
+ *  0bxxx0..Accesses from an untrusted master are allowed.
+ *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ *  0bxx0x..This peripheral allows write accesses.
+ *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ *          error response and no peripheral access is initiated on the IPS bus.
+ *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ *          on the IPS bus.
+ *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
 #define AIPSTZ_OPACR3_OPAC31(x)                  (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC31_SHIFT)) & AIPSTZ_OPACR3_OPAC31_MASK)
 #define AIPSTZ_OPACR3_OPAC30_MASK                (0xF0U)
 #define AIPSTZ_OPACR3_OPAC30_SHIFT               (4U)
+/*! OPAC30
+ *  0bxxx0..Accesses from an untrusted master are allowed.
+ *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ *  0bxx0x..This peripheral allows write accesses.
+ *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ *          error response and no peripheral access is initiated on the IPS bus.
+ *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ *          on the IPS bus.
+ *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
 #define AIPSTZ_OPACR3_OPAC30(x)                  (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC30_SHIFT)) & AIPSTZ_OPACR3_OPAC30_MASK)
 #define AIPSTZ_OPACR3_OPAC29_MASK                (0xF00U)
 #define AIPSTZ_OPACR3_OPAC29_SHIFT               (8U)
+/*! OPAC29
+ *  0bxxx0..Accesses from an untrusted master are allowed.
+ *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ *  0bxx0x..This peripheral allows write accesses.
+ *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ *          error response and no peripheral access is initiated on the IPS bus.
+ *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ *          on the IPS bus.
+ *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
 #define AIPSTZ_OPACR3_OPAC29(x)                  (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC29_SHIFT)) & AIPSTZ_OPACR3_OPAC29_MASK)
 #define AIPSTZ_OPACR3_OPAC28_MASK                (0xF000U)
 #define AIPSTZ_OPACR3_OPAC28_SHIFT               (12U)
+/*! OPAC28
+ *  0bxxx0..Accesses from an untrusted master are allowed.
+ *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ *  0bxx0x..This peripheral allows write accesses.
+ *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ *          error response and no peripheral access is initiated on the IPS bus.
+ *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ *          on the IPS bus.
+ *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
 #define AIPSTZ_OPACR3_OPAC28(x)                  (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC28_SHIFT)) & AIPSTZ_OPACR3_OPAC28_MASK)
 #define AIPSTZ_OPACR3_OPAC27_MASK                (0xF0000U)
 #define AIPSTZ_OPACR3_OPAC27_SHIFT               (16U)
+/*! OPAC27
+ *  0bxxx0..Accesses from an untrusted master are allowed.
+ *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ *  0bxx0x..This peripheral allows write accesses.
+ *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ *          error response and no peripheral access is initiated on the IPS bus.
+ *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ *          on the IPS bus.
+ *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
 #define AIPSTZ_OPACR3_OPAC27(x)                  (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC27_SHIFT)) & AIPSTZ_OPACR3_OPAC27_MASK)
 #define AIPSTZ_OPACR3_OPAC26_MASK                (0xF00000U)
 #define AIPSTZ_OPACR3_OPAC26_SHIFT               (20U)
+/*! OPAC26
+ *  0bxxx0..Accesses from an untrusted master are allowed.
+ *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ *  0bxx0x..This peripheral allows write accesses.
+ *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ *          error response and no peripheral access is initiated on the IPS bus.
+ *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ *          on the IPS bus.
+ *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
 #define AIPSTZ_OPACR3_OPAC26(x)                  (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC26_SHIFT)) & AIPSTZ_OPACR3_OPAC26_MASK)
 #define AIPSTZ_OPACR3_OPAC25_MASK                (0xF000000U)
 #define AIPSTZ_OPACR3_OPAC25_SHIFT               (24U)
+/*! OPAC25
+ *  0bxxx0..Accesses from an untrusted master are allowed.
+ *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ *  0bxx0x..This peripheral allows write accesses.
+ *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ *          error response and no peripheral access is initiated on the IPS bus.
+ *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ *          on the IPS bus.
+ *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
 #define AIPSTZ_OPACR3_OPAC25(x)                  (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC25_SHIFT)) & AIPSTZ_OPACR3_OPAC25_MASK)
 #define AIPSTZ_OPACR3_OPAC24_MASK                (0xF0000000U)
 #define AIPSTZ_OPACR3_OPAC24_SHIFT               (28U)
+/*! OPAC24
+ *  0bxxx0..Accesses from an untrusted master are allowed.
+ *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ *  0bxx0x..This peripheral allows write accesses.
+ *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ *          error response and no peripheral access is initiated on the IPS bus.
+ *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ *          on the IPS bus.
+ *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
 #define AIPSTZ_OPACR3_OPAC24(x)                  (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC24_SHIFT)) & AIPSTZ_OPACR3_OPAC24_MASK)
 /*! @} */
 
@@ -2123,9 +2707,37 @@ typedef struct {
 /*! @{ */
 #define AIPSTZ_OPACR4_OPAC33_MASK                (0xF000000U)
 #define AIPSTZ_OPACR4_OPAC33_SHIFT               (24U)
+/*! OPAC33
+ *  0bxxx0..Accesses from an untrusted master are allowed.
+ *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ *  0bxx0x..This peripheral allows write accesses.
+ *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ *          error response and no peripheral access is initiated on the IPS bus.
+ *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ *          on the IPS bus.
+ *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
 #define AIPSTZ_OPACR4_OPAC33(x)                  (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR4_OPAC33_SHIFT)) & AIPSTZ_OPACR4_OPAC33_MASK)
 #define AIPSTZ_OPACR4_OPAC32_MASK                (0xF0000000U)
 #define AIPSTZ_OPACR4_OPAC32_SHIFT               (28U)
+/*! OPAC32
+ *  0bxxx0..Accesses from an untrusted master are allowed.
+ *  0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ *          the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ *  0bxx0x..This peripheral allows write accesses.
+ *  0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ *          error response and no peripheral access is initiated on the IPS bus.
+ *  0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ *  0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ *          indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ *          be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ *          on the IPS bus.
+ *  0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
 #define AIPSTZ_OPACR4_OPAC32(x)                  (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR4_OPAC32_SHIFT)) & AIPSTZ_OPACR4_OPAC32_MASK)
 /*! @} */
 
@@ -2192,27 +2804,75 @@ typedef struct {
 /*! @{ */
 #define AOI_BFCRT01_PT1_DC_MASK                  (0x3U)
 #define AOI_BFCRT01_PT1_DC_SHIFT                 (0U)
+/*! PT1_DC - Product term 1, D input configuration
+ *  0b00..Force the D input in this product term to a logical zero
+ *  0b01..Pass the D input in this product term
+ *  0b10..Complement the D input in this product term
+ *  0b11..Force the D input in this product term to a logical one
+ */
 #define AOI_BFCRT01_PT1_DC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_DC_SHIFT)) & AOI_BFCRT01_PT1_DC_MASK)
 #define AOI_BFCRT01_PT1_CC_MASK                  (0xCU)
 #define AOI_BFCRT01_PT1_CC_SHIFT                 (2U)
+/*! PT1_CC - Product term 1, C input configuration
+ *  0b00..Force the C input in this product term to a logical zero
+ *  0b01..Pass the C input in this product term
+ *  0b10..Complement the C input in this product term
+ *  0b11..Force the C input in this product term to a logical one
+ */
 #define AOI_BFCRT01_PT1_CC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_CC_SHIFT)) & AOI_BFCRT01_PT1_CC_MASK)
 #define AOI_BFCRT01_PT1_BC_MASK                  (0x30U)
 #define AOI_BFCRT01_PT1_BC_SHIFT                 (4U)
+/*! PT1_BC - Product term 1, B input configuration
+ *  0b00..Force the B input in this product term to a logical zero
+ *  0b01..Pass the B input in this product term
+ *  0b10..Complement the B input in this product term
+ *  0b11..Force the B input in this product term to a logical one
+ */
 #define AOI_BFCRT01_PT1_BC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_BC_SHIFT)) & AOI_BFCRT01_PT1_BC_MASK)
 #define AOI_BFCRT01_PT1_AC_MASK                  (0xC0U)
 #define AOI_BFCRT01_PT1_AC_SHIFT                 (6U)
+/*! PT1_AC - Product term 1, A input configuration
+ *  0b00..Force the A input in this product term to a logical zero
+ *  0b01..Pass the A input in this product term
+ *  0b10..Complement the A input in this product term
+ *  0b11..Force the A input in this product term to a logical one
+ */
 #define AOI_BFCRT01_PT1_AC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_AC_SHIFT)) & AOI_BFCRT01_PT1_AC_MASK)
 #define AOI_BFCRT01_PT0_DC_MASK                  (0x300U)
 #define AOI_BFCRT01_PT0_DC_SHIFT                 (8U)
+/*! PT0_DC - Product term 0, D input configuration
+ *  0b00..Force the D input in this product term to a logical zero
+ *  0b01..Pass the D input in this product term
+ *  0b10..Complement the D input in this product term
+ *  0b11..Force the D input in this product term to a logical one
+ */
 #define AOI_BFCRT01_PT0_DC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_DC_SHIFT)) & AOI_BFCRT01_PT0_DC_MASK)
 #define AOI_BFCRT01_PT0_CC_MASK                  (0xC00U)
 #define AOI_BFCRT01_PT0_CC_SHIFT                 (10U)
+/*! PT0_CC - Product term 0, C input configuration
+ *  0b00..Force the C input in this product term to a logical zero
+ *  0b01..Pass the C input in this product term
+ *  0b10..Complement the C input in this product term
+ *  0b11..Force the C input in this product term to a logical one
+ */
 #define AOI_BFCRT01_PT0_CC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_CC_SHIFT)) & AOI_BFCRT01_PT0_CC_MASK)
 #define AOI_BFCRT01_PT0_BC_MASK                  (0x3000U)
 #define AOI_BFCRT01_PT0_BC_SHIFT                 (12U)
+/*! PT0_BC - Product term 0, B input configuration
+ *  0b00..Force the B input in this product term to a logical zero
+ *  0b01..Pass the B input in this product term
+ *  0b10..Complement the B input in this product term
+ *  0b11..Force the B input in this product term to a logical one
+ */
 #define AOI_BFCRT01_PT0_BC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_BC_SHIFT)) & AOI_BFCRT01_PT0_BC_MASK)
 #define AOI_BFCRT01_PT0_AC_MASK                  (0xC000U)
 #define AOI_BFCRT01_PT0_AC_SHIFT                 (14U)
+/*! PT0_AC - Product term 0, A input configuration
+ *  0b00..Force the A input in this product term to a logical zero
+ *  0b01..Pass the A input in this product term
+ *  0b10..Complement the A input in this product term
+ *  0b11..Force the A input in this product term to a logical one
+ */
 #define AOI_BFCRT01_PT0_AC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_AC_SHIFT)) & AOI_BFCRT01_PT0_AC_MASK)
 /*! @} */
 
@@ -2223,27 +2883,75 @@ typedef struct {
 /*! @{ */
 #define AOI_BFCRT23_PT3_DC_MASK                  (0x3U)
 #define AOI_BFCRT23_PT3_DC_SHIFT                 (0U)
+/*! PT3_DC - Product term 3, D input configuration
+ *  0b00..Force the D input in this product term to a logical zero
+ *  0b01..Pass the D input in this product term
+ *  0b10..Complement the D input in this product term
+ *  0b11..Force the D input in this product term to a logical one
+ */
 #define AOI_BFCRT23_PT3_DC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_DC_SHIFT)) & AOI_BFCRT23_PT3_DC_MASK)
 #define AOI_BFCRT23_PT3_CC_MASK                  (0xCU)
 #define AOI_BFCRT23_PT3_CC_SHIFT                 (2U)
+/*! PT3_CC - Product term 3, C input configuration
+ *  0b00..Force the C input in this product term to a logical zero
+ *  0b01..Pass the C input in this product term
+ *  0b10..Complement the C input in this product term
+ *  0b11..Force the C input in this product term to a logical one
+ */
 #define AOI_BFCRT23_PT3_CC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_CC_SHIFT)) & AOI_BFCRT23_PT3_CC_MASK)
 #define AOI_BFCRT23_PT3_BC_MASK                  (0x30U)
 #define AOI_BFCRT23_PT3_BC_SHIFT                 (4U)
+/*! PT3_BC - Product term 3, B input configuration
+ *  0b00..Force the B input in this product term to a logical zero
+ *  0b01..Pass the B input in this product term
+ *  0b10..Complement the B input in this product term
+ *  0b11..Force the B input in this product term to a logical one
+ */
 #define AOI_BFCRT23_PT3_BC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_BC_SHIFT)) & AOI_BFCRT23_PT3_BC_MASK)
 #define AOI_BFCRT23_PT3_AC_MASK                  (0xC0U)
 #define AOI_BFCRT23_PT3_AC_SHIFT                 (6U)
+/*! PT3_AC - Product term 3, A input configuration
+ *  0b00..Force the A input in this product term to a logical zero
+ *  0b01..Pass the A input in this product term
+ *  0b10..Complement the A input in this product term
+ *  0b11..Force the A input in this product term to a logical one
+ */
 #define AOI_BFCRT23_PT3_AC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_AC_SHIFT)) & AOI_BFCRT23_PT3_AC_MASK)
 #define AOI_BFCRT23_PT2_DC_MASK                  (0x300U)
 #define AOI_BFCRT23_PT2_DC_SHIFT                 (8U)
+/*! PT2_DC - Product term 2, D input configuration
+ *  0b00..Force the D input in this product term to a logical zero
+ *  0b01..Pass the D input in this product term
+ *  0b10..Complement the D input in this product term
+ *  0b11..Force the D input in this product term to a logical one
+ */
 #define AOI_BFCRT23_PT2_DC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_DC_SHIFT)) & AOI_BFCRT23_PT2_DC_MASK)
 #define AOI_BFCRT23_PT2_CC_MASK                  (0xC00U)
 #define AOI_BFCRT23_PT2_CC_SHIFT                 (10U)
+/*! PT2_CC - Product term 2, C input configuration
+ *  0b00..Force the C input in this product term to a logical zero
+ *  0b01..Pass the C input in this product term
+ *  0b10..Complement the C input in this product term
+ *  0b11..Force the C input in this product term to a logical one
+ */
 #define AOI_BFCRT23_PT2_CC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_CC_SHIFT)) & AOI_BFCRT23_PT2_CC_MASK)
 #define AOI_BFCRT23_PT2_BC_MASK                  (0x3000U)
 #define AOI_BFCRT23_PT2_BC_SHIFT                 (12U)
+/*! PT2_BC - Product term 2, B input configuration
+ *  0b00..Force the B input in this product term to a logical zero
+ *  0b01..Pass the B input in this product term
+ *  0b10..Complement the B input in this product term
+ *  0b11..Force the B input in this product term to a logical one
+ */
 #define AOI_BFCRT23_PT2_BC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_BC_SHIFT)) & AOI_BFCRT23_PT2_BC_MASK)
 #define AOI_BFCRT23_PT2_AC_MASK                  (0xC000U)
 #define AOI_BFCRT23_PT2_AC_SHIFT                 (14U)
+/*! PT2_AC - Product term 2, A input configuration
+ *  0b00..Force the A input in this product term to a logical zero
+ *  0b01..Pass the A input in this product term
+ *  0b10..Complement the A input in this product term
+ *  0b11..Force the A input in this product term to a logical one
+ */
 #define AOI_BFCRT23_PT2_AC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_AC_SHIFT)) & AOI_BFCRT23_PT2_AC_MASK)
 /*! @} */
 
@@ -2319,6 +3027,10 @@ typedef struct {
 /*! @{ */
 #define BEE_CTRL_BEE_ENABLE_MASK                 (0x1U)
 #define BEE_CTRL_BEE_ENABLE_SHIFT                (0U)
+/*! BEE_ENABLE
+ *  0b0..Disable BEE
+ *  0b1..Enable BEE
+ */
 #define BEE_CTRL_BEE_ENABLE(x)                   (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_BEE_ENABLE_SHIFT)) & BEE_CTRL_BEE_ENABLE_MASK)
 #define BEE_CTRL_CTRL_CLK_EN_MASK                (0x2U)
 #define BEE_CTRL_CTRL_CLK_EN_SHIFT               (1U)
@@ -2331,24 +3043,42 @@ typedef struct {
 #define BEE_CTRL_KEY_VALID(x)                    (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_VALID_SHIFT)) & BEE_CTRL_KEY_VALID_MASK)
 #define BEE_CTRL_KEY_REGION_SEL_MASK             (0x20U)
 #define BEE_CTRL_KEY_REGION_SEL_SHIFT            (5U)
+/*! KEY_REGION_SEL
+ *  0b0..Load AES key for region0
+ *  0b1..Load AES key for region1
+ */
 #define BEE_CTRL_KEY_REGION_SEL(x)               (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_REGION_SEL_SHIFT)) & BEE_CTRL_KEY_REGION_SEL_MASK)
 #define BEE_CTRL_AC_PROT_EN_MASK                 (0x40U)
 #define BEE_CTRL_AC_PROT_EN_SHIFT                (6U)
 #define BEE_CTRL_AC_PROT_EN(x)                   (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_AC_PROT_EN_SHIFT)) & BEE_CTRL_AC_PROT_EN_MASK)
 #define BEE_CTRL_LITTLE_ENDIAN_MASK              (0x80U)
 #define BEE_CTRL_LITTLE_ENDIAN_SHIFT             (7U)
+/*! LITTLE_ENDIAN
+ *  0b0..The input and output data of the AES core is swapped as below: {B15,B14,B13,B12,B11,B10,B9,B8,
+ *       B7,B6,B5,B4,B3,B2,B1,B0} swap to {B0,B1,B2,B3,B4,B5,B6,B7, B8,B9,B10,B11,B12,B13,B14,B15}, where B0~B15 refers to
+ *       Byte0 to Byte15.
+ *  0b1..The input and output data of AES core is not swapped.
+ */
 #define BEE_CTRL_LITTLE_ENDIAN(x)                (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_LITTLE_ENDIAN_SHIFT)) & BEE_CTRL_LITTLE_ENDIAN_MASK)
 #define BEE_CTRL_SECURITY_LEVEL_R0_MASK          (0x300U)
 #define BEE_CTRL_SECURITY_LEVEL_R0_SHIFT         (8U)
 #define BEE_CTRL_SECURITY_LEVEL_R0(x)            (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R0_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R0_MASK)
 #define BEE_CTRL_CTRL_AES_MODE_R0_MASK           (0x400U)
 #define BEE_CTRL_CTRL_AES_MODE_R0_SHIFT          (10U)
+/*! CTRL_AES_MODE_R0
+ *  0b0..ECB
+ *  0b1..CTR
+ */
 #define BEE_CTRL_CTRL_AES_MODE_R0(x)             (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R0_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R0_MASK)
 #define BEE_CTRL_SECURITY_LEVEL_R1_MASK          (0x3000U)
 #define BEE_CTRL_SECURITY_LEVEL_R1_SHIFT         (12U)
 #define BEE_CTRL_SECURITY_LEVEL_R1(x)            (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R1_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R1_MASK)
 #define BEE_CTRL_CTRL_AES_MODE_R1_MASK           (0x4000U)
 #define BEE_CTRL_CTRL_AES_MODE_R1_SHIFT          (14U)
+/*! CTRL_AES_MODE_R1
+ *  0b0..ECB
+ *  0b1..CTR
+ */
 #define BEE_CTRL_CTRL_AES_MODE_R1(x)             (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R1_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R1_MASK)
 #define BEE_CTRL_BEE_ENABLE_LOCK_MASK            (0x10000U)
 #define BEE_CTRL_BEE_ENABLE_LOCK_SHIFT           (16U)
@@ -2406,12 +3136,12 @@ typedef struct {
 
 /*! @name ADDR_OFFSET1 -  */
 /*! @{ */
-#define BEE_ADDR_OFFSET1_ADDR_OFFSET0_MASK       (0xFFFFU)
-#define BEE_ADDR_OFFSET1_ADDR_OFFSET0_SHIFT      (0U)
-#define BEE_ADDR_OFFSET1_ADDR_OFFSET0(x)         (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET1_ADDR_OFFSET0_SHIFT)) & BEE_ADDR_OFFSET1_ADDR_OFFSET0_MASK)
-#define BEE_ADDR_OFFSET1_ADDR_OFFSET0_LOCK_MASK  (0xFFFF0000U)
-#define BEE_ADDR_OFFSET1_ADDR_OFFSET0_LOCK_SHIFT (16U)
-#define BEE_ADDR_OFFSET1_ADDR_OFFSET0_LOCK(x)    (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET1_ADDR_OFFSET0_LOCK_SHIFT)) & BEE_ADDR_OFFSET1_ADDR_OFFSET0_LOCK_MASK)
+#define BEE_ADDR_OFFSET1_ADDR_OFFSET1_MASK       (0xFFFFU)
+#define BEE_ADDR_OFFSET1_ADDR_OFFSET1_SHIFT      (0U)
+#define BEE_ADDR_OFFSET1_ADDR_OFFSET1(x)         (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET1_ADDR_OFFSET1_SHIFT)) & BEE_ADDR_OFFSET1_ADDR_OFFSET1_MASK)
+#define BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK_MASK  (0xFFFF0000U)
+#define BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK_SHIFT (16U)
+#define BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK(x)    (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK_SHIFT)) & BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK_MASK)
 /*! @} */
 
 /*! @name AES_KEY0_W0 -  */
@@ -2573,16 +3303,19 @@ typedef struct {
   __I  uint32_t CRCR;                              /**< CRC Register, offset: 0x44 */
   __IO uint32_t RXFGMASK;                          /**< Rx FIFO Global Mask Register, offset: 0x48 */
   __I  uint32_t RXFIR;                             /**< Rx FIFO Information Register, offset: 0x4C */
-       uint8_t RESERVED_2[48];
+       uint8_t RESERVED_2[8];
+  __I  uint32_t DBG1;                              /**< Debug 1 register, offset: 0x58 */
+  __I  uint32_t DBG2;                              /**< Debug 2 register, offset: 0x5C */
+       uint8_t RESERVED_3[32];
   struct {                                         /* offset: 0x80, array step: 0x10 */
     __IO uint32_t CS;                                /**< Message Buffer 0 CS Register..Message Buffer 63 CS Register, array offset: 0x80, array step: 0x10 */
     __IO uint32_t ID;                                /**< Message Buffer 0 ID Register..Message Buffer 63 ID Register, array offset: 0x84, array step: 0x10 */
     __IO uint32_t WORD0;                             /**< Message Buffer 0 WORD0 Register..Message Buffer 63 WORD0 Register, array offset: 0x88, array step: 0x10 */
     __IO uint32_t WORD1;                             /**< Message Buffer 0 WORD1 Register..Message Buffer 63 WORD1 Register, array offset: 0x8C, array step: 0x10 */
   } MB[64];
-       uint8_t RESERVED_3[1024];
+       uint8_t RESERVED_4[1024];
   __IO uint32_t RXIMR[64];                         /**< Rx Individual Mask Registers, array offset: 0x880, array step: 0x4 */
-       uint8_t RESERVED_4[96];
+       uint8_t RESERVED_5[96];
   __IO uint32_t GFWR;                              /**< Glitch Filter Width Registers, offset: 0x9E0 */
 } CAN_Type;
 
@@ -2602,57 +3335,132 @@ typedef struct {
 #define CAN_MCR_MAXMB(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MAXMB_SHIFT)) & CAN_MCR_MAXMB_MASK)
 #define CAN_MCR_IDAM_MASK                        (0x300U)
 #define CAN_MCR_IDAM_SHIFT                       (8U)
+/*! IDAM
+ *  0b00..Format A One full ID (standard or extended) per ID filter Table element.
+ *  0b01..Format B Two full standard IDs or two partial 14-bit extended IDs per ID filter Table element.
+ *  0b10..Format C Four partial 8-bit IDs (standard or extended) per ID filter Table element.
+ *  0b11..Format D All frames rejected.
+ */
 #define CAN_MCR_IDAM(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK)
 #define CAN_MCR_AEN_MASK                         (0x1000U)
 #define CAN_MCR_AEN_SHIFT                        (12U)
+/*! AEN
+ *  0b1..Abort enabled
+ *  0b0..Abort disabled
+ */
 #define CAN_MCR_AEN(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK)
 #define CAN_MCR_LPRIOEN_MASK                     (0x2000U)
 #define CAN_MCR_LPRIOEN_SHIFT                    (13U)
+/*! LPRIOEN
+ *  0b1..Local Priority enabled
+ *  0b0..Local Priority disabled
+ */
 #define CAN_MCR_LPRIOEN(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK)
 #define CAN_MCR_IRMQ_MASK                        (0x10000U)
 #define CAN_MCR_IRMQ_SHIFT                       (16U)
+/*! IRMQ
+ *  0b1..Individual Rx masking and queue feature are enabled.
+ *  0b0..Individual Rx masking and queue feature are disabled.For backward compatibility, the reading of C/S word locks the MB even if it is EMPTY.
+ */
 #define CAN_MCR_IRMQ(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK)
 #define CAN_MCR_SRXDIS_MASK                      (0x20000U)
 #define CAN_MCR_SRXDIS_SHIFT                     (17U)
+/*! SRXDIS
+ *  0b1..Self reception disabled
+ *  0b0..Self reception enabled
+ */
 #define CAN_MCR_SRXDIS(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK)
 #define CAN_MCR_WAKSRC_MASK                      (0x80000U)
 #define CAN_MCR_WAKSRC_SHIFT                     (19U)
+/*! WAKSRC
+ *  0b1..FLEXCAN uses the filtered FLEXCAN_RX input to detect recessive to dominant edges on the CAN bus
+ *  0b0..FLEXCAN uses the unfiltered FLEXCAN_RX input to detect recessive to dominant edges on the CAN bus.
+ */
 #define CAN_MCR_WAKSRC(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK)
 #define CAN_MCR_LPMACK_MASK                      (0x100000U)
 #define CAN_MCR_LPMACK_SHIFT                     (20U)
+/*! LPMACK
+ *  0b1..FLEXCAN is either in Disable Mode, or Stop mode
+ *  0b0..FLEXCAN not in any of the low power modes
+ */
 #define CAN_MCR_LPMACK(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK)
 #define CAN_MCR_WRNEN_MASK                       (0x200000U)
 #define CAN_MCR_WRNEN_SHIFT                      (21U)
+/*! WRNEN
+ *  0b1..TWRN_INT and RWRN_INT bits are set when the respective error counter transition from <96 to >= 96.
+ *  0b0..TWRN_INT and RWRN_INT bits are zero, independent of the values in the error counters.
+ */
 #define CAN_MCR_WRNEN(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK)
 #define CAN_MCR_SLFWAK_MASK                      (0x400000U)
 #define CAN_MCR_SLFWAK_SHIFT                     (22U)
+/*! SLFWAK
+ *  0b1..FLEXCAN Self Wake Up feature is enabled
+ *  0b0..FLEXCAN Self Wake Up feature is disabled
+ */
 #define CAN_MCR_SLFWAK(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK)
 #define CAN_MCR_SUPV_MASK                        (0x800000U)
 #define CAN_MCR_SUPV_SHIFT                       (23U)
+/*! SUPV
+ *  0b1..FlexCAN is in Supervisor Mode. Affected registers allow only Supervisor access. Unrestricted access
+ *       behaves as though the access was done to an unimplemented register location
+ *  0b0..FlexCAN is in User Mode. Affected registers allow both Supervisor and Unrestricted accesses
+ */
 #define CAN_MCR_SUPV(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SUPV_SHIFT)) & CAN_MCR_SUPV_MASK)
 #define CAN_MCR_FRZACK_MASK                      (0x1000000U)
 #define CAN_MCR_FRZACK_SHIFT                     (24U)
+/*! FRZACK
+ *  0b1..FLEXCAN in Freeze Mode, prescaler stopped
+ *  0b0..FLEXCAN not in Freeze Mode, prescaler running
+ */
 #define CAN_MCR_FRZACK(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK)
 #define CAN_MCR_SOFTRST_MASK                     (0x2000000U)
 #define CAN_MCR_SOFTRST_SHIFT                    (25U)
+/*! SOFTRST
+ *  0b1..Reset the registers
+ *  0b0..No reset request
+ */
 #define CAN_MCR_SOFTRST(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK)
 #define CAN_MCR_WAKMSK_MASK                      (0x4000000U)
 #define CAN_MCR_WAKMSK_SHIFT                     (26U)
+/*! WAKMSK
+ *  0b1..Wake Up Interrupt is enabled
+ *  0b0..Wake Up Interrupt is disabled
+ */
 #define CAN_MCR_WAKMSK(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK)
 #define CAN_MCR_NOTRDY_MASK                      (0x8000000U)
 #define CAN_MCR_NOTRDY_SHIFT                     (27U)
+/*! NOTRDY
+ *  0b1..FLEXCAN module is either in Disable Mode, Stop Mode or Freeze Mode
+ *  0b0..FLEXCAN module is either in Normal Mode, Listen-Only Mode or Loop-Back Mode
+ */
 #define CAN_MCR_NOTRDY(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK)
 #define CAN_MCR_HALT_MASK                        (0x10000000U)
 #define CAN_MCR_HALT_SHIFT                       (28U)
+/*! HALT
+ *  0b1..Enters Freeze Mode if the FRZ bit is asserted.
+ *  0b0..No Freeze Mode request.
+ */
 #define CAN_MCR_HALT(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK)
 #define CAN_MCR_RFEN_MASK                        (0x20000000U)
 #define CAN_MCR_RFEN_SHIFT                       (29U)
+/*! RFEN
+ *  0b1..FIFO enabled
+ *  0b0..FIFO not enabled
+ */
 #define CAN_MCR_RFEN(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK)
 #define CAN_MCR_FRZ_MASK                         (0x40000000U)
 #define CAN_MCR_FRZ_SHIFT                        (30U)
+/*! FRZ
+ *  0b1..Enabled to enter Freeze Mode
+ *  0b0..Not enabled to enter Freeze Mode
+ */
 #define CAN_MCR_FRZ(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK)
 #define CAN_MCR_MDIS_MASK                        (0x80000000U)
 #define CAN_MCR_MDIS_SHIFT                       (31U)
+/*! MDIS
+ *  0b1..Disable the FLEXCAN module
+ *  0b0..Enable the FLEXCAN module
+ */
 #define CAN_MCR_MDIS(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK)
 /*! @} */
 
@@ -2663,33 +3471,74 @@ typedef struct {
 #define CAN_CTRL1_PROPSEG(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PROPSEG_SHIFT)) & CAN_CTRL1_PROPSEG_MASK)
 #define CAN_CTRL1_LOM_MASK                       (0x8U)
 #define CAN_CTRL1_LOM_SHIFT                      (3U)
+/*! LOM
+ *  0b1..FLEXCAN module operates in Listen Only Mode
+ *  0b0..Listen Only Mode is deactivated
+ */
 #define CAN_CTRL1_LOM(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LOM_SHIFT)) & CAN_CTRL1_LOM_MASK)
 #define CAN_CTRL1_LBUF_MASK                      (0x10U)
 #define CAN_CTRL1_LBUF_SHIFT                     (4U)
+/*! LBUF
+ *  0b1..Lowest number buffer is transmitted first
+ *  0b0..Buffer with highest priority is transmitted first
+ */
 #define CAN_CTRL1_LBUF(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LBUF_SHIFT)) & CAN_CTRL1_LBUF_MASK)
 #define CAN_CTRL1_TSYN_MASK                      (0x20U)
 #define CAN_CTRL1_TSYN_SHIFT                     (5U)
+/*! TSYN
+ *  0b1..Timer Sync feature enabled
+ *  0b0..Timer Sync feature disabled
+ */
 #define CAN_CTRL1_TSYN(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK)
 #define CAN_CTRL1_BOFFREC_MASK                   (0x40U)
 #define CAN_CTRL1_BOFFREC_SHIFT                  (6U)
+/*! BOFFREC
+ *  0b1..Automatic recovering from Bus Off state disabled
+ *  0b0..Automatic recovering from Bus Off state enabled, according to CAN Spec 2.0 part B
+ */
 #define CAN_CTRL1_BOFFREC(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK)
 #define CAN_CTRL1_SMP_MASK                       (0x80U)
 #define CAN_CTRL1_SMP_SHIFT                      (7U)
+/*! SMP
+ *  0b1..Three samples are used to determine the value of the received bit: the regular one (sample point) and 2
+ *       preceding samples, a majority rule is used
+ *  0b0..Just one sample is used to determine the bit value
+ */
 #define CAN_CTRL1_SMP(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK)
 #define CAN_CTRL1_RWRNMSK_MASK                   (0x400U)
 #define CAN_CTRL1_RWRNMSK_SHIFT                  (10U)
+/*! RWRNMSK
+ *  0b1..Rx Warning Interrupt enabled
+ *  0b0..Rx Warning Interrupt disabled
+ */
 #define CAN_CTRL1_RWRNMSK(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK)
 #define CAN_CTRL1_TWRNMSK_MASK                   (0x800U)
 #define CAN_CTRL1_TWRNMSK_SHIFT                  (11U)
+/*! TWRNMSK
+ *  0b1..Tx Warning Interrupt enabled
+ *  0b0..Tx Warning Interrupt disabled
+ */
 #define CAN_CTRL1_TWRNMSK(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK)
 #define CAN_CTRL1_LPB_MASK                       (0x1000U)
 #define CAN_CTRL1_LPB_SHIFT                      (12U)
+/*! LPB
+ *  0b1..Loop Back enabled
+ *  0b0..Loop Back disabled
+ */
 #define CAN_CTRL1_LPB(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK)
 #define CAN_CTRL1_ERRMSK_MASK                    (0x4000U)
 #define CAN_CTRL1_ERRMSK_SHIFT                   (14U)
+/*! ERRMSK
+ *  0b1..Error interrupt enabled
+ *  0b0..Error interrupt disabled
+ */
 #define CAN_CTRL1_ERRMSK(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK)
 #define CAN_CTRL1_BOFFMSK_MASK                   (0x8000U)
 #define CAN_CTRL1_BOFFMSK_SHIFT                  (15U)
+/*! BOFFMSK
+ *  0b1..Bus Off interrupt enabled
+ *  0b0..Bus Off interrupt disabled
+ */
 #define CAN_CTRL1_BOFFMSK(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK)
 #define CAN_CTRL1_PSEG2_MASK                     (0x70000U)
 #define CAN_CTRL1_PSEG2_SHIFT                    (16U)
@@ -2716,6 +3565,10 @@ typedef struct {
 /*! @{ */
 #define CAN_RXMGMASK_MG_MASK                     (0xFFFFFFFFU)
 #define CAN_RXMGMASK_MG_SHIFT                    (0U)
+/*! MG
+ *  0b00000000000000000000000000000001..The corresponding bit in the filter is checked against the one received
+ *  0b00000000000000000000000000000000..the corresponding bit in the filter is "don't care"
+ */
 #define CAN_RXMGMASK_MG(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK)
 /*! @} */
 
@@ -2723,6 +3576,10 @@ typedef struct {
 /*! @{ */
 #define CAN_RX14MASK_RX14M_MASK                  (0xFFFFFFFFU)
 #define CAN_RX14MASK_RX14M_SHIFT                 (0U)
+/*! RX14M
+ *  0b00000000000000000000000000000001..The corresponding bit in the filter is checked
+ *  0b00000000000000000000000000000000..the corresponding bit in the filter is "don't care"
+ */
 #define CAN_RX14MASK_RX14M(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK)
 /*! @} */
 
@@ -2730,6 +3587,10 @@ typedef struct {
 /*! @{ */
 #define CAN_RX15MASK_RX15M_MASK                  (0xFFFFFFFFU)
 #define CAN_RX15MASK_RX15M_SHIFT                 (0U)
+/*! RX15M
+ *  0b00000000000000000000000000000001..The corresponding bit in the filter is checked
+ *  0b00000000000000000000000000000000..the corresponding bit in the filter is "don't care"
+ */
 #define CAN_RX15MASK_RX15M(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK)
 /*! @} */
 
@@ -2747,57 +3608,130 @@ typedef struct {
 /*! @{ */
 #define CAN_ESR1_WAKINT_MASK                     (0x1U)
 #define CAN_ESR1_WAKINT_SHIFT                    (0U)
+/*! WAKINT
+ *  0b1..Indicates a recessive to dominant transition received on the CAN bus when the FLEXCAN module is in Stop Mode
+ *  0b0..No such occurrence
+ */
 #define CAN_ESR1_WAKINT(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK)
 #define CAN_ESR1_ERRINT_MASK                     (0x2U)
 #define CAN_ESR1_ERRINT_SHIFT                    (1U)
+/*! ERRINT
+ *  0b1..Indicates setting of any Error Bit in the Error and Status Register
+ *  0b0..No such occurrence
+ */
 #define CAN_ESR1_ERRINT(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_SHIFT)) & CAN_ESR1_ERRINT_MASK)
 #define CAN_ESR1_BOFFINT_MASK                    (0x4U)
 #define CAN_ESR1_BOFFINT_SHIFT                   (2U)
+/*! BOFFINT
+ *  0b1..FLEXCAN module entered 'Bus Off' state
+ *  0b0..No such occurrence
+ */
 #define CAN_ESR1_BOFFINT(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFINT_SHIFT)) & CAN_ESR1_BOFFINT_MASK)
 #define CAN_ESR1_RX_MASK                         (0x8U)
 #define CAN_ESR1_RX_SHIFT                        (3U)
+/*! RX
+ *  0b1..FLEXCAN is transmitting a message
+ *  0b0..FLEXCAN is receiving a message
+ */
 #define CAN_ESR1_RX(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RX_SHIFT)) & CAN_ESR1_RX_MASK)
 #define CAN_ESR1_FLTCONF_MASK                    (0x30U)
 #define CAN_ESR1_FLTCONF_SHIFT                   (4U)
+/*! FLTCONF
+ *  0b00..Error Active
+ *  0b01..Error Passive
+ *  0b1x..Bus off
+ */
 #define CAN_ESR1_FLTCONF(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK)
 #define CAN_ESR1_TX_MASK                         (0x40U)
 #define CAN_ESR1_TX_SHIFT                        (6U)
+/*! TX
+ *  0b1..FLEXCAN is transmitting a message
+ *  0b0..FLEXCAN is receiving a message
+ */
 #define CAN_ESR1_TX(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TX_SHIFT)) & CAN_ESR1_TX_MASK)
 #define CAN_ESR1_IDLE_MASK                       (0x80U)
 #define CAN_ESR1_IDLE_SHIFT                      (7U)
+/*! IDLE
+ *  0b1..CAN bus is now IDLE
+ *  0b0..No such occurrence
+ */
 #define CAN_ESR1_IDLE(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_IDLE_SHIFT)) & CAN_ESR1_IDLE_MASK)
 #define CAN_ESR1_RXWRN_MASK                      (0x100U)
 #define CAN_ESR1_RXWRN_SHIFT                     (8U)
+/*! RXWRN
+ *  0b1..Rx_Err_Counter >= 96
+ *  0b0..No such occurrence
+ */
 #define CAN_ESR1_RXWRN(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RXWRN_SHIFT)) & CAN_ESR1_RXWRN_MASK)
 #define CAN_ESR1_TXWRN_MASK                      (0x200U)
 #define CAN_ESR1_TXWRN_SHIFT                     (9U)
+/*! TXWRN
+ *  0b1..TX_Err_Counter >= 96
+ *  0b0..No such occurrence
+ */
 #define CAN_ESR1_TXWRN(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TXWRN_SHIFT)) & CAN_ESR1_TXWRN_MASK)
 #define CAN_ESR1_STFERR_MASK                     (0x400U)
 #define CAN_ESR1_STFERR_SHIFT                    (10U)
+/*! STFERR
+ *  0b1..A Stuffing Error occurred since last read of this register.
+ *  0b0..No such occurrence.
+ */
 #define CAN_ESR1_STFERR(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_SHIFT)) & CAN_ESR1_STFERR_MASK)
 #define CAN_ESR1_FRMERR_MASK                     (0x800U)
 #define CAN_ESR1_FRMERR_SHIFT                    (11U)
+/*! FRMERR
+ *  0b1..A Form Error occurred since last read of this register
+ *  0b0..No such occurrence
+ */
 #define CAN_ESR1_FRMERR(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_SHIFT)) & CAN_ESR1_FRMERR_MASK)
 #define CAN_ESR1_CRCERR_MASK                     (0x1000U)
 #define CAN_ESR1_CRCERR_SHIFT                    (12U)
+/*! CRCERR
+ *  0b1..A CRC error occurred since last read of this register.
+ *  0b0..No such occurrence
+ */
 #define CAN_ESR1_CRCERR(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_SHIFT)) & CAN_ESR1_CRCERR_MASK)
 #define CAN_ESR1_ACKERR_MASK                     (0x2000U)
 #define CAN_ESR1_ACKERR_SHIFT                    (13U)
+/*! ACKERR
+ *  0b1..An ACK error occurred since last read of this register
+ *  0b0..No such occurrence
+ */
 #define CAN_ESR1_ACKERR(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ACKERR_SHIFT)) & CAN_ESR1_ACKERR_MASK)
 #define CAN_ESR1_BIT0ERR_MASK                    (0x4000U)
 #define CAN_ESR1_BIT0ERR_SHIFT                   (14U)
+/*! BIT0ERR
+ *  0b1..At least one bit sent as dominant is received as recessive
+ *  0b0..No such occurrence
+ */
 #define CAN_ESR1_BIT0ERR(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_SHIFT)) & CAN_ESR1_BIT0ERR_MASK)
 #define CAN_ESR1_BIT1ERR_MASK                    (0x8000U)
 #define CAN_ESR1_BIT1ERR_SHIFT                   (15U)
+/*! BIT1ERR
+ *  0b1..At least one bit sent as recessive is received as dominant
+ *  0b0..No such occurrence
+ */
 #define CAN_ESR1_BIT1ERR(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_SHIFT)) & CAN_ESR1_BIT1ERR_MASK)
 #define CAN_ESR1_RWRNINT_MASK                    (0x10000U)
 #define CAN_ESR1_RWRNINT_SHIFT                   (16U)
+/*! RWRNINT
+ *  0b1..The Rx error counter transition from < 96 to >= 96
+ *  0b0..No such occurrence
+ */
 #define CAN_ESR1_RWRNINT(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RWRNINT_SHIFT)) & CAN_ESR1_RWRNINT_MASK)
 #define CAN_ESR1_TWRNINT_MASK                    (0x20000U)
 #define CAN_ESR1_TWRNINT_SHIFT                   (17U)
+/*! TWRNINT
+ *  0b1..The Tx error counter transition from < 96 to >= 96
+ *  0b0..No such occurrence
+ */
 #define CAN_ESR1_TWRNINT(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TWRNINT_SHIFT)) & CAN_ESR1_TWRNINT_MASK)
 #define CAN_ESR1_SYNCH_MASK                      (0x40000U)
 #define CAN_ESR1_SYNCH_SHIFT                     (18U)
+/*! SYNCH
+ *  0b1..FlexCAN is synchronized to the CAN bus
+ *  0b0..FlexCAN is not synchronized to the CAN bus
+ */
 #define CAN_ESR1_SYNCH(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK)
 /*! @} */
 
@@ -2805,6 +3739,10 @@ typedef struct {
 /*! @{ */
 #define CAN_IMASK2_BUFHM_MASK                    (0xFFFFFFFFU)
 #define CAN_IMASK2_BUFHM_SHIFT                   (0U)
+/*! BUFHM
+ *  0b00000000000000000000000000000001..The corresponding buffer Interrupt is enabled
+ *  0b00000000000000000000000000000000..The corresponding buffer Interrupt is disabled
+ */
 #define CAN_IMASK2_BUFHM(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_IMASK2_BUFHM_SHIFT)) & CAN_IMASK2_BUFHM_MASK)
 /*! @} */
 
@@ -2812,6 +3750,10 @@ typedef struct {
 /*! @{ */
 #define CAN_IMASK1_BUFLM_MASK                    (0xFFFFFFFFU)
 #define CAN_IMASK1_BUFLM_SHIFT                   (0U)
+/*! BUFLM
+ *  0b00000000000000000000000000000001..The corresponding buffer Interrupt is enabled
+ *  0b00000000000000000000000000000000..The corresponding buffer Interrupt is disabled
+ */
 #define CAN_IMASK1_BUFLM(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUFLM_SHIFT)) & CAN_IMASK1_BUFLM_MASK)
 /*! @} */
 
@@ -2819,6 +3761,10 @@ typedef struct {
 /*! @{ */
 #define CAN_IFLAG2_BUFHI_MASK                    (0xFFFFFFFFU)
 #define CAN_IFLAG2_BUFHI_SHIFT                   (0U)
+/*! BUFHI
+ *  0b00000000000000000000000000000001..The corresponding buffer has successfully completed transmission or reception
+ *  0b00000000000000000000000000000000..No such occurrence
+ */
 #define CAN_IFLAG2_BUFHI(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG2_BUFHI_SHIFT)) & CAN_IFLAG2_BUFHI_MASK)
 /*! @} */
 
@@ -2826,18 +3772,38 @@ typedef struct {
 /*! @{ */
 #define CAN_IFLAG1_BUF4TO0I_MASK                 (0x1FU)
 #define CAN_IFLAG1_BUF4TO0I_SHIFT                (0U)
+/*! BUF4TO0I
+ *  0b00001..Corresponding MB completed transmission/reception
+ *  0b00000..No such occurrence
+ */
 #define CAN_IFLAG1_BUF4TO0I(x)                   (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO0I_SHIFT)) & CAN_IFLAG1_BUF4TO0I_MASK)
 #define CAN_IFLAG1_BUF5I_MASK                    (0x20U)
 #define CAN_IFLAG1_BUF5I_SHIFT                   (5U)
+/*! BUF5I
+ *  0b1..MB5 completed transmission/reception or frames available in the FIFO
+ *  0b0..No such occurrence
+ */
 #define CAN_IFLAG1_BUF5I(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK)
 #define CAN_IFLAG1_BUF6I_MASK                    (0x40U)
 #define CAN_IFLAG1_BUF6I_SHIFT                   (6U)
+/*! BUF6I
+ *  0b1..MB6 completed transmission/reception or FIFO almost full
+ *  0b0..No such occurrence
+ */
 #define CAN_IFLAG1_BUF6I(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK)
 #define CAN_IFLAG1_BUF7I_MASK                    (0x80U)
 #define CAN_IFLAG1_BUF7I_SHIFT                   (7U)
+/*! BUF7I
+ *  0b1..MB7 completed transmission/reception or FIFO overflow
+ *  0b0..No such occurrence
+ */
 #define CAN_IFLAG1_BUF7I(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK)
 #define CAN_IFLAG1_BUF31TO8I_MASK                (0xFFFFFF00U)
 #define CAN_IFLAG1_BUF31TO8I_SHIFT               (8U)
+/*! BUF31TO8I
+ *  0b000000000000000000000001..The corresponding MB has successfully completed transmission or reception
+ *  0b000000000000000000000000..No such occurrence
+ */
 #define CAN_IFLAG1_BUF31TO8I(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK)
 /*! @} */
 
@@ -2845,12 +3811,25 @@ typedef struct {
 /*! @{ */
 #define CAN_CTRL2_EACEN_MASK                     (0x10000U)
 #define CAN_CTRL2_EACEN_SHIFT                    (16U)
+/*! EACEN
+ *  0b1..Enables the comparison of both Rx Mailbox filter's IDE and RTR bit with their corresponding bits within
+ *       the incoming frame. Mask bits do apply.
+ *  0b0..Rx Mailbox filter's IDE bit is always compared and RTR is never compared despite mask bits.
+ */
 #define CAN_CTRL2_EACEN(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK)
 #define CAN_CTRL2_RRS_MASK                       (0x20000U)
 #define CAN_CTRL2_RRS_SHIFT                      (17U)
+/*! RRS
+ *  0b1..Remote Request Frame is stored
+ *  0b0..Remote Response Frame is generated
+ */
 #define CAN_CTRL2_RRS(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RRS_SHIFT)) & CAN_CTRL2_RRS_MASK)
 #define CAN_CTRL2_MRP_MASK                       (0x40000U)
 #define CAN_CTRL2_MRP_SHIFT                      (18U)
+/*! MRP
+ *  0b1..Matching starts from Mailboxes and continues on Rx FIFO
+ *  0b0..Matching starts from Rx FIFO and continues on Mailboxes
+ */
 #define CAN_CTRL2_MRP(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MRP_SHIFT)) & CAN_CTRL2_MRP_MASK)
 #define CAN_CTRL2_TASD_MASK                      (0xF80000U)
 #define CAN_CTRL2_TASD_SHIFT                     (19U)
@@ -2860,6 +3839,10 @@ typedef struct {
 #define CAN_CTRL2_RFFN(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RFFN_SHIFT)) & CAN_CTRL2_RFFN_MASK)
 #define CAN_CTRL2_WRMFRZ_MASK                    (0x10000000U)
 #define CAN_CTRL2_WRMFRZ_SHIFT                   (28U)
+/*! WRMFRZ
+ *  0b1..Enable unrestricted write access to FlexCAN memory
+ *  0b0..Keep the write access restricted in some regions of FlexCAN memory
+ */
 #define CAN_CTRL2_WRMFRZ(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_WRMFRZ_SHIFT)) & CAN_CTRL2_WRMFRZ_MASK)
 /*! @} */
 
@@ -2867,9 +3850,17 @@ typedef struct {
 /*! @{ */
 #define CAN_ESR2_IMB_MASK                        (0x2000U)
 #define CAN_ESR2_IMB_SHIFT                       (13U)
+/*! IMB
+ *  0b1..If ESR2[VPS] is asserted, there is at least one inactive Mailbox. LPTM content is the number of the first one.
+ *  0b0..If ESR2[VPS] is asserted, the ESR2[LPTM] is not an inactive Mailbox.
+ */
 #define CAN_ESR2_IMB(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK)
 #define CAN_ESR2_VPS_MASK                        (0x4000U)
 #define CAN_ESR2_VPS_SHIFT                       (14U)
+/*! VPS
+ *  0b1..Contents of IMB and LPTM are valid
+ *  0b0..Contents of IMB and LPTM are invalid
+ */
 #define CAN_ESR2_VPS(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_VPS_SHIFT)) & CAN_ESR2_VPS_MASK)
 #define CAN_ESR2_LPTM_MASK                       (0x7F0000U)
 #define CAN_ESR2_LPTM_SHIFT                      (16U)
@@ -2890,6 +3881,10 @@ typedef struct {
 /*! @{ */
 #define CAN_RXFGMASK_FGM_MASK                    (0xFFFFFFFFU)
 #define CAN_RXFGMASK_FGM_SHIFT                   (0U)
+/*! FGM
+ *  0b00000000000000000000000000000001..The corresponding bit in the filter is checked
+ *  0b00000000000000000000000000000000..The corresponding bit in the filter is "don't care"
+ */
 #define CAN_RXFGMASK_FGM(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_RXFGMASK_FGM_SHIFT)) & CAN_RXFGMASK_FGM_MASK)
 /*! @} */
 
@@ -2900,6 +3895,40 @@ typedef struct {
 #define CAN_RXFIR_IDHIT(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_RXFIR_IDHIT_SHIFT)) & CAN_RXFIR_IDHIT_MASK)
 /*! @} */
 
+/*! @name DBG1 - Debug 1 register */
+/*! @{ */
+#define CAN_DBG1_CFSM_MASK                       (0x3FU)
+#define CAN_DBG1_CFSM_SHIFT                      (0U)
+#define CAN_DBG1_CFSM(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_DBG1_CFSM_SHIFT)) & CAN_DBG1_CFSM_MASK)
+#define CAN_DBG1_CBN_MASK                        (0x1F000000U)
+#define CAN_DBG1_CBN_SHIFT                       (24U)
+#define CAN_DBG1_CBN(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_DBG1_CBN_SHIFT)) & CAN_DBG1_CBN_MASK)
+/*! @} */
+
+/*! @name DBG2 - Debug 2 register */
+/*! @{ */
+#define CAN_DBG2_RMP_MASK                        (0x7FU)
+#define CAN_DBG2_RMP_SHIFT                       (0U)
+#define CAN_DBG2_RMP(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_RMP_SHIFT)) & CAN_DBG2_RMP_MASK)
+#define CAN_DBG2_MPP_MASK                        (0x80U)
+#define CAN_DBG2_MPP_SHIFT                       (7U)
+/*! MPP - Matching Process in Progress
+ *  0b0..No matching process ongoing.
+ *  0b1..Matching process is in progress.
+ */
+#define CAN_DBG2_MPP(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_MPP_SHIFT)) & CAN_DBG2_MPP_MASK)
+#define CAN_DBG2_TAP_MASK                        (0x7F00U)
+#define CAN_DBG2_TAP_SHIFT                       (8U)
+#define CAN_DBG2_TAP(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_TAP_SHIFT)) & CAN_DBG2_TAP_MASK)
+#define CAN_DBG2_APP_MASK                        (0x8000U)
+#define CAN_DBG2_APP_SHIFT                       (15U)
+/*! APP - Arbitration Process in Progress
+ *  0b0..No matching process ongoing.
+ *  0b1..Matching process is in progress.
+ */
+#define CAN_DBG2_APP(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_APP_SHIFT)) & CAN_DBG2_APP_MASK)
+/*! @} */
+
 /*! @name CS - Message Buffer 0 CS Register..Message Buffer 63 CS Register */
 /*! @{ */
 #define CAN_CS_TIME_STAMP_MASK                   (0xFFFFU)
@@ -2983,6 +4012,10 @@ typedef struct {
 /*! @{ */
 #define CAN_RXIMR_MI_MASK                        (0xFFFFFFFFU)
 #define CAN_RXIMR_MI_SHIFT                       (0U)
+/*! MI
+ *  0b00000000000000000000000000000001..The corresponding bit in the filter is checked
+ *  0b00000000000000000000000000000000..the corresponding bit in the filter is "don't care"
+ */
 #define CAN_RXIMR_MI(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_RXIMR_MI_SHIFT)) & CAN_RXIMR_MI_MASK)
 /*! @} */
 
@@ -3098,12 +4131,25 @@ typedef struct {
 #define CCM_CCR_OSCNT(x)                         (((uint32_t)(((uint32_t)(x)) << CCM_CCR_OSCNT_SHIFT)) & CCM_CCR_OSCNT_MASK)
 #define CCM_CCR_COSC_EN_MASK                     (0x1000U)
 #define CCM_CCR_COSC_EN_SHIFT                    (12U)
+/*! COSC_EN
+ *  0b0..disable on chip oscillator
+ *  0b1..enable on chip oscillator
+ */
 #define CCM_CCR_COSC_EN(x)                       (((uint32_t)(((uint32_t)(x)) << CCM_CCR_COSC_EN_SHIFT)) & CCM_CCR_COSC_EN_MASK)
 #define CCM_CCR_REG_BYPASS_COUNT_MASK            (0x7E00000U)
 #define CCM_CCR_REG_BYPASS_COUNT_SHIFT           (21U)
+/*! REG_BYPASS_COUNT
+ *  0b000000..no delay
+ *  0b000001..1 CKIL clock period delay
+ *  0b111111..63 CKIL clock periods delay
+ */
 #define CCM_CCR_REG_BYPASS_COUNT(x)              (((uint32_t)(((uint32_t)(x)) << CCM_CCR_REG_BYPASS_COUNT_SHIFT)) & CCM_CCR_REG_BYPASS_COUNT_MASK)
 #define CCM_CCR_RBC_EN_MASK                      (0x8000000U)
 #define CCM_CCR_RBC_EN_SHIFT                     (27U)
+/*! RBC_EN
+ *  0b1..REG_BYPASS_COUNTER enabled.
+ *  0b0..REG_BYPASS_COUNTER disabled
+ */
 #define CCM_CCR_RBC_EN(x)                        (((uint32_t)(((uint32_t)(x)) << CCM_CCR_RBC_EN_SHIFT)) & CCM_CCR_RBC_EN_MASK)
 /*! @} */
 
@@ -3111,12 +4157,24 @@ typedef struct {
 /*! @{ */
 #define CCM_CSR_REF_EN_B_MASK                    (0x1U)
 #define CCM_CSR_REF_EN_B_SHIFT                   (0U)
+/*! REF_EN_B
+ *  0b0..value of CCM_REF_EN_B is '0'
+ *  0b1..value of CCM_REF_EN_B is '1'
+ */
 #define CCM_CSR_REF_EN_B(x)                      (((uint32_t)(((uint32_t)(x)) << CCM_CSR_REF_EN_B_SHIFT)) & CCM_CSR_REF_EN_B_MASK)
 #define CCM_CSR_CAMP2_READY_MASK                 (0x8U)
 #define CCM_CSR_CAMP2_READY_SHIFT                (3U)
+/*! CAMP2_READY
+ *  0b0..CAMP2 is not ready.
+ *  0b1..CAMP2 is ready.
+ */
 #define CCM_CSR_CAMP2_READY(x)                   (((uint32_t)(((uint32_t)(x)) << CCM_CSR_CAMP2_READY_SHIFT)) & CCM_CSR_CAMP2_READY_MASK)
 #define CCM_CSR_COSC_READY_MASK                  (0x20U)
 #define CCM_CSR_COSC_READY_SHIFT                 (5U)
+/*! COSC_READY
+ *  0b0..on board oscillator is not ready.
+ *  0b1..on board oscillator is ready.
+ */
 #define CCM_CSR_COSC_READY(x)                    (((uint32_t)(((uint32_t)(x)) << CCM_CSR_COSC_READY_SHIFT)) & CCM_CSR_COSC_READY_MASK)
 /*! @} */
 
@@ -3124,6 +4182,10 @@ typedef struct {
 /*! @{ */
 #define CCM_CCSR_PLL3_SW_CLK_SEL_MASK            (0x1U)
 #define CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT           (0U)
+/*! PLL3_SW_CLK_SEL
+ *  0b0..pll3_main_clk
+ *  0b1..pll3 bypass clock
+ */
 #define CCM_CCSR_PLL3_SW_CLK_SEL(x)              (((uint32_t)(((uint32_t)(x)) << CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT)) & CCM_CCSR_PLL3_SW_CLK_SEL_MASK)
 /*! @} */
 
@@ -3131,6 +4193,16 @@ typedef struct {
 /*! @{ */
 #define CCM_CACRR_ARM_PODF_MASK                  (0x7U)
 #define CCM_CACRR_ARM_PODF_SHIFT                 (0U)
+/*! ARM_PODF
+ *  0b000..divide by 1
+ *  0b001..divide by 2
+ *  0b010..divide by 3
+ *  0b011..divide by 4
+ *  0b100..divide by 5
+ *  0b101..divide by 6
+ *  0b110..divide by 7
+ *  0b111..divide by 8
+ */
 #define CCM_CACRR_ARM_PODF(x)                    (((uint32_t)(((uint32_t)(x)) << CCM_CACRR_ARM_PODF_SHIFT)) & CCM_CACRR_ARM_PODF_MASK)
 /*! @} */
 
@@ -3138,24 +4210,72 @@ typedef struct {
 /*! @{ */
 #define CCM_CBCDR_SEMC_CLK_SEL_MASK              (0x40U)
 #define CCM_CBCDR_SEMC_CLK_SEL_SHIFT             (6U)
+/*! SEMC_CLK_SEL
+ *  0b0..Periph_clk output will be used as SEMC clock root
+ *  0b1..SEMC alternative clock will be used as SEMC clock root
+ */
 #define CCM_CBCDR_SEMC_CLK_SEL(x)                (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_SEMC_CLK_SEL_SHIFT)) & CCM_CBCDR_SEMC_CLK_SEL_MASK)
 #define CCM_CBCDR_SEMC_ALT_CLK_SEL_MASK          (0x80U)
 #define CCM_CBCDR_SEMC_ALT_CLK_SEL_SHIFT         (7U)
+/*! SEMC_ALT_CLK_SEL
+ *  0b0..PLL2 PFD2 will be selected as alternative clock for SEMC root clock
+ *  0b1..PLL3 PFD1 will be selected as alternative clock for SEMC root clock
+ */
 #define CCM_CBCDR_SEMC_ALT_CLK_SEL(x)            (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_SEMC_ALT_CLK_SEL_SHIFT)) & CCM_CBCDR_SEMC_ALT_CLK_SEL_MASK)
 #define CCM_CBCDR_IPG_PODF_MASK                  (0x300U)
 #define CCM_CBCDR_IPG_PODF_SHIFT                 (8U)
+/*! IPG_PODF
+ *  0b00..divide by 1
+ *  0b01..divide by 2
+ *  0b10..divide by 3
+ *  0b11..divide by 4
+ */
 #define CCM_CBCDR_IPG_PODF(x)                    (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_IPG_PODF_SHIFT)) & CCM_CBCDR_IPG_PODF_MASK)
 #define CCM_CBCDR_AHB_PODF_MASK                  (0x1C00U)
 #define CCM_CBCDR_AHB_PODF_SHIFT                 (10U)
+/*! AHB_PODF
+ *  0b000..divide by 1
+ *  0b001..divide by 2
+ *  0b010..divide by 3
+ *  0b011..divide by 4
+ *  0b100..divide by 5
+ *  0b101..divide by 6
+ *  0b110..divide by 7
+ *  0b111..divide by 8
+ */
 #define CCM_CBCDR_AHB_PODF(x)                    (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_AHB_PODF_SHIFT)) & CCM_CBCDR_AHB_PODF_MASK)
 #define CCM_CBCDR_SEMC_PODF_MASK                 (0x70000U)
 #define CCM_CBCDR_SEMC_PODF_SHIFT                (16U)
+/*! SEMC_PODF
+ *  0b000..divide by 1
+ *  0b001..divide by 2
+ *  0b010..divide by 3
+ *  0b011..divide by 4
+ *  0b100..divide by 5
+ *  0b101..divide by 6
+ *  0b110..divide by 7
+ *  0b111..divide by 8
+ */
 #define CCM_CBCDR_SEMC_PODF(x)                   (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_SEMC_PODF_SHIFT)) & CCM_CBCDR_SEMC_PODF_MASK)
 #define CCM_CBCDR_PERIPH_CLK_SEL_MASK            (0x2000000U)
 #define CCM_CBCDR_PERIPH_CLK_SEL_SHIFT           (25U)
+/*! PERIPH_CLK_SEL
+ *  0b0..derive clock from pre_periph_clk_sel
+ *  0b1..derive clock from periph_clk2_clk_divided
+ */
 #define CCM_CBCDR_PERIPH_CLK_SEL(x)              (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_PERIPH_CLK_SEL_SHIFT)) & CCM_CBCDR_PERIPH_CLK_SEL_MASK)
 #define CCM_CBCDR_PERIPH_CLK2_PODF_MASK          (0x38000000U)
 #define CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT         (27U)
+/*! PERIPH_CLK2_PODF
+ *  0b000..divide by 1
+ *  0b001..divide by 2
+ *  0b010..divide by 3
+ *  0b011..divide by 4
+ *  0b100..divide by 5
+ *  0b101..divide by 6
+ *  0b110..divide by 7
+ *  0b111..divide by 8
+ */
 #define CCM_CBCDR_PERIPH_CLK2_PODF(x)            (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT)) & CCM_CBCDR_PERIPH_CLK2_PODF_MASK)
 /*! @} */
 
@@ -3163,21 +4283,65 @@ typedef struct {
 /*! @{ */
 #define CCM_CBCMR_LPSPI_CLK_SEL_MASK             (0x30U)
 #define CCM_CBCMR_LPSPI_CLK_SEL_SHIFT            (4U)
+/*! LPSPI_CLK_SEL
+ *  0b00..derive clock from PLL3 PFD1 clk
+ *  0b01..derive clock from PLL3 PFD0
+ *  0b10..derive clock from PLL2
+ *  0b11..derive clock from PLL2 PFD2
+ */
 #define CCM_CBCMR_LPSPI_CLK_SEL(x)               (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_LPSPI_CLK_SEL_SHIFT)) & CCM_CBCMR_LPSPI_CLK_SEL_MASK)
 #define CCM_CBCMR_PERIPH_CLK2_SEL_MASK           (0x3000U)
 #define CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT          (12U)
+/*! PERIPH_CLK2_SEL
+ *  0b00..derive clock from pll3_sw_clk
+ *  0b01..derive clock from osc_clk (pll1_ref_clk)
+ *  0b10..derive clock from pll2_bypass_clk
+ *  0b11..reserved
+ */
 #define CCM_CBCMR_PERIPH_CLK2_SEL(x)             (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT)) & CCM_CBCMR_PERIPH_CLK2_SEL_MASK)
 #define CCM_CBCMR_TRACE_CLK_SEL_MASK             (0xC000U)
 #define CCM_CBCMR_TRACE_CLK_SEL_SHIFT            (14U)
+/*! TRACE_CLK_SEL
+ *  0b00..derive clock from PLL2
+ *  0b01..derive clock from PLL2 PFD2
+ *  0b10..derive clock from PLL2 PFD0
+ *  0b11..derive clock from PLL2 PFD1
+ */
 #define CCM_CBCMR_TRACE_CLK_SEL(x)               (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_TRACE_CLK_SEL_SHIFT)) & CCM_CBCMR_TRACE_CLK_SEL_MASK)
 #define CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK        (0xC0000U)
 #define CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT       (18U)
+/*! PRE_PERIPH_CLK_SEL
+ *  0b00..derive clock from PLL2
+ *  0b01..derive clock from PLL2 PFD2
+ *  0b10..derive clock from PLL2 PFD0
+ *  0b11..derive clock from divided PLL1
+ */
 #define CCM_CBCMR_PRE_PERIPH_CLK_SEL(x)          (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT)) & CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK)
 #define CCM_CBCMR_LCDIF_PODF_MASK                (0x3800000U)
 #define CCM_CBCMR_LCDIF_PODF_SHIFT               (23U)
+/*! LCDIF_PODF
+ *  0b000..divide by 1
+ *  0b001..divide by 2
+ *  0b010..divide by 3
+ *  0b011..divide by 4
+ *  0b100..divide by 5
+ *  0b101..divide by 6
+ *  0b110..divide by 7
+ *  0b111..divide by 8
+ */
 #define CCM_CBCMR_LCDIF_PODF(x)                  (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_LCDIF_PODF_SHIFT)) & CCM_CBCMR_LCDIF_PODF_MASK)
 #define CCM_CBCMR_LPSPI_PODF_MASK                (0x1C000000U)
 #define CCM_CBCMR_LPSPI_PODF_SHIFT               (26U)
+/*! LPSPI_PODF
+ *  0b000..divide by 1
+ *  0b001..divide by 2
+ *  0b010..divide by 3
+ *  0b011..divide by 4
+ *  0b100..divide by 5
+ *  0b101..divide by 6
+ *  0b110..divide by 7
+ *  0b111..divide by 8
+ */
 #define CCM_CBCMR_LPSPI_PODF(x)                  (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_LPSPI_PODF_SHIFT)) & CCM_CBCMR_LPSPI_PODF_MASK)
 /*! @} */
 
@@ -3185,30 +4349,142 @@ typedef struct {
 /*! @{ */
 #define CCM_CSCMR1_PERCLK_PODF_MASK              (0x3FU)
 #define CCM_CSCMR1_PERCLK_PODF_SHIFT             (0U)
+/*! PERCLK_PODF - Divider for perclk podf.
+ *  0b000000..Divide by 1
+ *  0b000001..Divide by 2
+ *  0b000010..Divide by 3
+ *  0b000011..Divide by 4
+ *  0b000100..Divide by 5
+ *  0b000101..Divide by 6
+ *  0b000110..Divide by 7
+ *  0b000111..Divide by 8
+ *  0b001000..Divide by 9
+ *  0b001001..Divide by 10
+ *  0b001010..Divide by 11
+ *  0b001011..Divide by 12
+ *  0b001100..Divide by 13
+ *  0b001101..Divide by 14
+ *  0b001110..Divide by 15
+ *  0b001111..Divide by 16
+ *  0b010000..Divide by 17
+ *  0b010001..Divide by 18
+ *  0b010010..Divide by 19
+ *  0b010011..Divide by 20
+ *  0b010100..Divide by 21
+ *  0b010101..Divide by 22
+ *  0b010110..Divide by 23
+ *  0b010111..Divide by 24
+ *  0b011000..Divide by 25
+ *  0b011001..Divide by 26
+ *  0b011010..Divide by 27
+ *  0b011011..Divide by 28
+ *  0b011100..Divide by 29
+ *  0b011101..Divide by 30
+ *  0b011110..Divide by 31
+ *  0b011111..Divide by 32
+ *  0b100000..Divide by 33
+ *  0b100001..Divide by 34
+ *  0b100010..Divide by 35
+ *  0b100011..Divide by 36
+ *  0b100100..Divide by 37
+ *  0b100101..Divide by 38
+ *  0b100110..Divide by 39
+ *  0b100111..Divide by 40
+ *  0b101000..Divide by 41
+ *  0b101001..Divide by 42
+ *  0b101010..Divide by 43
+ *  0b101011..Divide by 44
+ *  0b101100..Divide by 45
+ *  0b101101..Divide by 46
+ *  0b101110..Divide by 47
+ *  0b101111..Divide by 48
+ *  0b110000..Divide by 49
+ *  0b110001..Divide by 50
+ *  0b110010..Divide by 51
+ *  0b110011..Divide by 52
+ *  0b110100..Divide by 53
+ *  0b110101..Divide by 54
+ *  0b110110..Divide by 55
+ *  0b110111..Divide by 56
+ *  0b111000..Divide by 57
+ *  0b111001..Divide by 58
+ *  0b111010..Divide by 59
+ *  0b111011..Divide by 60
+ *  0b111100..Divide by 61
+ *  0b111101..Divide by 62
+ *  0b111110..Divide by 63
+ *  0b111111..Divide by 64
+ */
 #define CCM_CSCMR1_PERCLK_PODF(x)                (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_PERCLK_PODF_SHIFT)) & CCM_CSCMR1_PERCLK_PODF_MASK)
 #define CCM_CSCMR1_PERCLK_CLK_SEL_MASK           (0x40U)
 #define CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT          (6U)
+/*! PERCLK_CLK_SEL
+ *  0b0..derive clock from ipg clk root
+ *  0b1..derive clock from osc_clk
+ */
 #define CCM_CSCMR1_PERCLK_CLK_SEL(x)             (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT)) & CCM_CSCMR1_PERCLK_CLK_SEL_MASK)
 #define CCM_CSCMR1_SAI1_CLK_SEL_MASK             (0xC00U)
 #define CCM_CSCMR1_SAI1_CLK_SEL_SHIFT            (10U)
+/*! SAI1_CLK_SEL
+ *  0b00..derive clock from PLL3 PFD2
+ *  0b01..derive clock from PLL5
+ *  0b10..derive clock from PLL4
+ *  0b11..Reserved
+ */
 #define CCM_CSCMR1_SAI1_CLK_SEL(x)               (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI1_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI1_CLK_SEL_MASK)
 #define CCM_CSCMR1_SAI2_CLK_SEL_MASK             (0x3000U)
 #define CCM_CSCMR1_SAI2_CLK_SEL_SHIFT            (12U)
+/*! SAI2_CLK_SEL
+ *  0b00..derive clock from PLL3 PFD2
+ *  0b01..derive clock from PLL5
+ *  0b10..derive clock from PLL4
+ *  0b11..Reserved
+ */
 #define CCM_CSCMR1_SAI2_CLK_SEL(x)               (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI2_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI2_CLK_SEL_MASK)
 #define CCM_CSCMR1_SAI3_CLK_SEL_MASK             (0xC000U)
 #define CCM_CSCMR1_SAI3_CLK_SEL_SHIFT            (14U)
+/*! SAI3_CLK_SEL
+ *  0b00..derive clock from PLL3 PFD2
+ *  0b01..derive clock from PLL5
+ *  0b10..derive clock from PLL4
+ *  0b11..Reserved
+ */
 #define CCM_CSCMR1_SAI3_CLK_SEL(x)               (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI3_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI3_CLK_SEL_MASK)
 #define CCM_CSCMR1_USDHC1_CLK_SEL_MASK           (0x10000U)
 #define CCM_CSCMR1_USDHC1_CLK_SEL_SHIFT          (16U)
+/*! USDHC1_CLK_SEL
+ *  0b0..derive clock from PLL2 PFD2
+ *  0b1..derive clock from PLL2 PFD0
+ */
 #define CCM_CSCMR1_USDHC1_CLK_SEL(x)             (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_USDHC1_CLK_SEL_SHIFT)) & CCM_CSCMR1_USDHC1_CLK_SEL_MASK)
 #define CCM_CSCMR1_USDHC2_CLK_SEL_MASK           (0x20000U)
 #define CCM_CSCMR1_USDHC2_CLK_SEL_SHIFT          (17U)
+/*! USDHC2_CLK_SEL
+ *  0b0..derive clock from PLL2 PFD2
+ *  0b1..derive clock from PLL2 PFD0
+ */
 #define CCM_CSCMR1_USDHC2_CLK_SEL(x)             (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_USDHC2_CLK_SEL_SHIFT)) & CCM_CSCMR1_USDHC2_CLK_SEL_MASK)
 #define CCM_CSCMR1_FLEXSPI_PODF_MASK             (0x3800000U)
 #define CCM_CSCMR1_FLEXSPI_PODF_SHIFT            (23U)
+/*! FLEXSPI_PODF
+ *  0b000..divide by 1
+ *  0b001..divide by 2
+ *  0b010..divide by 3
+ *  0b011..divide by 4
+ *  0b100..divide by 5
+ *  0b101..divide by 6
+ *  0b110..divide by 7
+ *  0b111..divide by 8
+ */
 #define CCM_CSCMR1_FLEXSPI_PODF(x)               (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_FLEXSPI_PODF_SHIFT)) & CCM_CSCMR1_FLEXSPI_PODF_MASK)
 #define CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK          (0x60000000U)
 #define CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT         (29U)
+/*! FLEXSPI_CLK_SEL
+ *  0b00..derive clock from semc_clk_root_pre
+ *  0b01..derive clock from pll3_sw_clk
+ *  0b10..derive clock from PLL2 PFD2
+ *  0b11..derive clock from PLL3 PFD0
+ */
 #define CCM_CSCMR1_FLEXSPI_CLK_SEL(x)            (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT)) & CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK)
 /*! @} */
 
@@ -3216,12 +4492,90 @@ typedef struct {
 /*! @{ */
 #define CCM_CSCMR2_CAN_CLK_PODF_MASK             (0xFCU)
 #define CCM_CSCMR2_CAN_CLK_PODF_SHIFT            (2U)
+/*! CAN_CLK_PODF - Divider for CAN clock podf.
+ *  0b000000..Divide by 1
+ *  0b000001..Divide by 2
+ *  0b000010..Divide by 3
+ *  0b000011..Divide by 4
+ *  0b000100..Divide by 5
+ *  0b000101..Divide by 6
+ *  0b000110..Divide by 7
+ *  0b000111..Divide by 8
+ *  0b001000..Divide by 9
+ *  0b001001..Divide by 10
+ *  0b001010..Divide by 11
+ *  0b001011..Divide by 12
+ *  0b001100..Divide by 13
+ *  0b001101..Divide by 14
+ *  0b001110..Divide by 15
+ *  0b001111..Divide by 16
+ *  0b010000..Divide by 17
+ *  0b010001..Divide by 18
+ *  0b010010..Divide by 19
+ *  0b010011..Divide by 20
+ *  0b010100..Divide by 21
+ *  0b010101..Divide by 22
+ *  0b010110..Divide by 23
+ *  0b010111..Divide by 24
+ *  0b011000..Divide by 25
+ *  0b011001..Divide by 26
+ *  0b011010..Divide by 27
+ *  0b011011..Divide by 28
+ *  0b011100..Divide by 29
+ *  0b011101..Divide by 30
+ *  0b011110..Divide by 31
+ *  0b011111..Divide by 32
+ *  0b100000..Divide by 33
+ *  0b100001..Divide by 34
+ *  0b100010..Divide by 35
+ *  0b100011..Divide by 36
+ *  0b100100..Divide by 37
+ *  0b100101..Divide by 38
+ *  0b100110..Divide by 39
+ *  0b100111..Divide by 40
+ *  0b101000..Divide by 41
+ *  0b101001..Divide by 42
+ *  0b101010..Divide by 43
+ *  0b101011..Divide by 44
+ *  0b101100..Divide by 45
+ *  0b101101..Divide by 46
+ *  0b101110..Divide by 47
+ *  0b101111..Divide by 48
+ *  0b110000..Divide by 49
+ *  0b110001..Divide by 50
+ *  0b110010..Divide by 51
+ *  0b110011..Divide by 52
+ *  0b110100..Divide by 53
+ *  0b110101..Divide by 54
+ *  0b110110..Divide by 55
+ *  0b110111..Divide by 56
+ *  0b111000..Divide by 57
+ *  0b111001..Divide by 58
+ *  0b111010..Divide by 59
+ *  0b111011..Divide by 60
+ *  0b111100..Divide by 61
+ *  0b111101..Divide by 62
+ *  0b111110..Divide by 63
+ *  0b111111..Divide by 64
+ */
 #define CCM_CSCMR2_CAN_CLK_PODF(x)               (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_CAN_CLK_PODF_SHIFT)) & CCM_CSCMR2_CAN_CLK_PODF_MASK)
 #define CCM_CSCMR2_CAN_CLK_SEL_MASK              (0x300U)
 #define CCM_CSCMR2_CAN_CLK_SEL_SHIFT             (8U)
+/*! CAN_CLK_SEL
+ *  0b00..derive clock from pll3_sw_clk divided clock (60M)
+ *  0b01..derive clock from osc_clk (24M)
+ *  0b10..derive clock from pll3_sw_clk divided clock (80M)
+ *  0b11..Disable FlexCAN clock
+ */
 #define CCM_CSCMR2_CAN_CLK_SEL(x)                (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_CAN_CLK_SEL_SHIFT)) & CCM_CSCMR2_CAN_CLK_SEL_MASK)
 #define CCM_CSCMR2_FLEXIO2_CLK_SEL_MASK          (0x180000U)
 #define CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT         (19U)
+/*! FLEXIO2_CLK_SEL
+ *  0b00..derive clock from PLL4 divided clock
+ *  0b01..derive clock from PLL3 PFD2 clock
+ *  0b10..derive clock from PLL5 clock
+ *  0b11..derive clock from pll3_sw_clk
+ */
 #define CCM_CSCMR2_FLEXIO2_CLK_SEL(x)            (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT)) & CCM_CSCMR2_FLEXIO2_CLK_SEL_MASK)
 /*! @} */
 
@@ -3229,18 +4583,114 @@ typedef struct {
 /*! @{ */
 #define CCM_CSCDR1_UART_CLK_PODF_MASK            (0x3FU)
 #define CCM_CSCDR1_UART_CLK_PODF_SHIFT           (0U)
+/*! UART_CLK_PODF - Divider for uart clock podf.
+ *  0b000000..Divide by 1
+ *  0b000001..Divide by 2
+ *  0b000010..Divide by 3
+ *  0b000011..Divide by 4
+ *  0b000100..Divide by 5
+ *  0b000101..Divide by 6
+ *  0b000110..Divide by 7
+ *  0b000111..Divide by 8
+ *  0b001000..Divide by 9
+ *  0b001001..Divide by 10
+ *  0b001010..Divide by 11
+ *  0b001011..Divide by 12
+ *  0b001100..Divide by 13
+ *  0b001101..Divide by 14
+ *  0b001110..Divide by 15
+ *  0b001111..Divide by 16
+ *  0b010000..Divide by 17
+ *  0b010001..Divide by 18
+ *  0b010010..Divide by 19
+ *  0b010011..Divide by 20
+ *  0b010100..Divide by 21
+ *  0b010101..Divide by 22
+ *  0b010110..Divide by 23
+ *  0b010111..Divide by 24
+ *  0b011000..Divide by 25
+ *  0b011001..Divide by 26
+ *  0b011010..Divide by 27
+ *  0b011011..Divide by 28
+ *  0b011100..Divide by 29
+ *  0b011101..Divide by 30
+ *  0b011110..Divide by 31
+ *  0b011111..Divide by 32
+ *  0b100000..Divide by 33
+ *  0b100001..Divide by 34
+ *  0b100010..Divide by 35
+ *  0b100011..Divide by 36
+ *  0b100100..Divide by 37
+ *  0b100101..Divide by 38
+ *  0b100110..Divide by 39
+ *  0b100111..Divide by 40
+ *  0b101000..Divide by 41
+ *  0b101001..Divide by 42
+ *  0b101010..Divide by 43
+ *  0b101011..Divide by 44
+ *  0b101100..Divide by 45
+ *  0b101101..Divide by 46
+ *  0b101110..Divide by 47
+ *  0b101111..Divide by 48
+ *  0b110000..Divide by 49
+ *  0b110001..Divide by 50
+ *  0b110010..Divide by 51
+ *  0b110011..Divide by 52
+ *  0b110100..Divide by 53
+ *  0b110101..Divide by 54
+ *  0b110110..Divide by 55
+ *  0b110111..Divide by 56
+ *  0b111000..Divide by 57
+ *  0b111001..Divide by 58
+ *  0b111010..Divide by 59
+ *  0b111011..Divide by 60
+ *  0b111100..Divide by 61
+ *  0b111101..Divide by 62
+ *  0b111110..Divide by 63
+ *  0b111111..Divide by 64
+ */
 #define CCM_CSCDR1_UART_CLK_PODF(x)              (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_UART_CLK_PODF_SHIFT)) & CCM_CSCDR1_UART_CLK_PODF_MASK)
 #define CCM_CSCDR1_UART_CLK_SEL_MASK             (0x40U)
 #define CCM_CSCDR1_UART_CLK_SEL_SHIFT            (6U)
+/*! UART_CLK_SEL
+ *  0b0..derive clock from pll3_80m
+ *  0b1..derive clock from osc_clk
+ */
 #define CCM_CSCDR1_UART_CLK_SEL(x)               (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_UART_CLK_SEL_SHIFT)) & CCM_CSCDR1_UART_CLK_SEL_MASK)
 #define CCM_CSCDR1_USDHC1_PODF_MASK              (0x3800U)
 #define CCM_CSCDR1_USDHC1_PODF_SHIFT             (11U)
+/*! USDHC1_PODF
+ *  0b000..divide by 1
+ *  0b001..divide by 2
+ *  0b010..divide by 3
+ *  0b011..divide by 4
+ *  0b100..divide by 5
+ *  0b101..divide by 6
+ *  0b110..divide by 7
+ *  0b111..divide by 8
+ */
 #define CCM_CSCDR1_USDHC1_PODF(x)                (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_USDHC1_PODF_SHIFT)) & CCM_CSCDR1_USDHC1_PODF_MASK)
 #define CCM_CSCDR1_USDHC2_PODF_MASK              (0x70000U)
 #define CCM_CSCDR1_USDHC2_PODF_SHIFT             (16U)
+/*! USDHC2_PODF
+ *  0b000..divide by 1
+ *  0b001..divide by 2
+ *  0b010..divide by 3
+ *  0b011..divide by 4
+ *  0b100..divide by 5
+ *  0b101..divide by 6
+ *  0b110..divide by 7
+ *  0b111..divide by 8
+ */
 #define CCM_CSCDR1_USDHC2_PODF(x)                (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_USDHC2_PODF_SHIFT)) & CCM_CSCDR1_USDHC2_PODF_MASK)
 #define CCM_CSCDR1_TRACE_PODF_MASK               (0x6000000U)
 #define CCM_CSCDR1_TRACE_PODF_SHIFT              (25U)
+/*! TRACE_PODF
+ *  0b00..divide by 1
+ *  0b01..divide by 2
+ *  0b10..divide by 3
+ *  0b11..divide by 4
+ */
 #define CCM_CSCDR1_TRACE_PODF(x)                 (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_TRACE_PODF_SHIFT)) & CCM_CSCDR1_TRACE_PODF_MASK)
 /*! @} */
 
@@ -3248,21 +4698,195 @@ typedef struct {
 /*! @{ */
 #define CCM_CS1CDR_SAI1_CLK_PODF_MASK            (0x3FU)
 #define CCM_CS1CDR_SAI1_CLK_PODF_SHIFT           (0U)
+/*! SAI1_CLK_PODF - Divider for sai1 clock podf. The input clock to this divider should be lower
+ *    than 300Mhz, the predivider can be used to achieve this.
+ *  0b000000..Divide by 1
+ *  0b000001..Divide by 2
+ *  0b000010..Divide by 3
+ *  0b000011..Divide by 4
+ *  0b000100..Divide by 5
+ *  0b000101..Divide by 6
+ *  0b000110..Divide by 7
+ *  0b000111..Divide by 8
+ *  0b001000..Divide by 9
+ *  0b001001..Divide by 10
+ *  0b001010..Divide by 11
+ *  0b001011..Divide by 12
+ *  0b001100..Divide by 13
+ *  0b001101..Divide by 14
+ *  0b001110..Divide by 15
+ *  0b001111..Divide by 16
+ *  0b010000..Divide by 17
+ *  0b010001..Divide by 18
+ *  0b010010..Divide by 19
+ *  0b010011..Divide by 20
+ *  0b010100..Divide by 21
+ *  0b010101..Divide by 22
+ *  0b010110..Divide by 23
+ *  0b010111..Divide by 24
+ *  0b011000..Divide by 25
+ *  0b011001..Divide by 26
+ *  0b011010..Divide by 27
+ *  0b011011..Divide by 28
+ *  0b011100..Divide by 29
+ *  0b011101..Divide by 30
+ *  0b011110..Divide by 31
+ *  0b011111..Divide by 32
+ *  0b100000..Divide by 33
+ *  0b100001..Divide by 34
+ *  0b100010..Divide by 35
+ *  0b100011..Divide by 36
+ *  0b100100..Divide by 37
+ *  0b100101..Divide by 38
+ *  0b100110..Divide by 39
+ *  0b100111..Divide by 40
+ *  0b101000..Divide by 41
+ *  0b101001..Divide by 42
+ *  0b101010..Divide by 43
+ *  0b101011..Divide by 44
+ *  0b101100..Divide by 45
+ *  0b101101..Divide by 46
+ *  0b101110..Divide by 47
+ *  0b101111..Divide by 48
+ *  0b110000..Divide by 49
+ *  0b110001..Divide by 50
+ *  0b110010..Divide by 51
+ *  0b110011..Divide by 52
+ *  0b110100..Divide by 53
+ *  0b110101..Divide by 54
+ *  0b110110..Divide by 55
+ *  0b110111..Divide by 56
+ *  0b111000..Divide by 57
+ *  0b111001..Divide by 58
+ *  0b111010..Divide by 59
+ *  0b111011..Divide by 60
+ *  0b111100..Divide by 61
+ *  0b111101..Divide by 62
+ *  0b111110..Divide by 63
+ *  0b111111..Divide by 64
+ */
 #define CCM_CS1CDR_SAI1_CLK_PODF(x)              (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI1_CLK_PODF_SHIFT)) & CCM_CS1CDR_SAI1_CLK_PODF_MASK)
 #define CCM_CS1CDR_SAI1_CLK_PRED_MASK            (0x1C0U)
 #define CCM_CS1CDR_SAI1_CLK_PRED_SHIFT           (6U)
+/*! SAI1_CLK_PRED
+ *  0b000..divide by 1
+ *  0b001..divide by 2
+ *  0b010..divide by 3
+ *  0b011..divide by 4
+ *  0b100..divide by 5
+ *  0b101..divide by 6
+ *  0b110..divide by 7
+ *  0b111..divide by 8
+ */
 #define CCM_CS1CDR_SAI1_CLK_PRED(x)              (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI1_CLK_PRED_SHIFT)) & CCM_CS1CDR_SAI1_CLK_PRED_MASK)
 #define CCM_CS1CDR_FLEXIO2_CLK_PRED_MASK         (0xE00U)
 #define CCM_CS1CDR_FLEXIO2_CLK_PRED_SHIFT        (9U)
+/*! FLEXIO2_CLK_PRED
+ *  0b000..divide by 1
+ *  0b001..divide by 2
+ *  0b010..divide by 3
+ *  0b011..divide by 4
+ *  0b100..divide by 5
+ *  0b101..divide by 6
+ *  0b110..divide by 7
+ *  0b111..divide by 8
+ */
 #define CCM_CS1CDR_FLEXIO2_CLK_PRED(x)           (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_FLEXIO2_CLK_PRED_SHIFT)) & CCM_CS1CDR_FLEXIO2_CLK_PRED_MASK)
 #define CCM_CS1CDR_SAI3_CLK_PODF_MASK            (0x3F0000U)
 #define CCM_CS1CDR_SAI3_CLK_PODF_SHIFT           (16U)
+/*! SAI3_CLK_PODF - Divider for sai3 clock podf. The input clock to this divider should be lower
+ *    than 300Mhz, the predivider can be used to achieve this.
+ *  0b000000..Divide by 1
+ *  0b000001..Divide by 2
+ *  0b000010..Divide by 3
+ *  0b000011..Divide by 4
+ *  0b000100..Divide by 5
+ *  0b000101..Divide by 6
+ *  0b000110..Divide by 7
+ *  0b000111..Divide by 8
+ *  0b001000..Divide by 9
+ *  0b001001..Divide by 10
+ *  0b001010..Divide by 11
+ *  0b001011..Divide by 12
+ *  0b001100..Divide by 13
+ *  0b001101..Divide by 14
+ *  0b001110..Divide by 15
+ *  0b001111..Divide by 16
+ *  0b010000..Divide by 17
+ *  0b010001..Divide by 18
+ *  0b010010..Divide by 19
+ *  0b010011..Divide by 20
+ *  0b010100..Divide by 21
+ *  0b010101..Divide by 22
+ *  0b010110..Divide by 23
+ *  0b010111..Divide by 24
+ *  0b011000..Divide by 25
+ *  0b011001..Divide by 26
+ *  0b011010..Divide by 27
+ *  0b011011..Divide by 28
+ *  0b011100..Divide by 29
+ *  0b011101..Divide by 30
+ *  0b011110..Divide by 31
+ *  0b011111..Divide by 32
+ *  0b100000..Divide by 33
+ *  0b100001..Divide by 34
+ *  0b100010..Divide by 35
+ *  0b100011..Divide by 36
+ *  0b100100..Divide by 37
+ *  0b100101..Divide by 38
+ *  0b100110..Divide by 39
+ *  0b100111..Divide by 40
+ *  0b101000..Divide by 41
+ *  0b101001..Divide by 42
+ *  0b101010..Divide by 43
+ *  0b101011..Divide by 44
+ *  0b101100..Divide by 45
+ *  0b101101..Divide by 46
+ *  0b101110..Divide by 47
+ *  0b101111..Divide by 48
+ *  0b110000..Divide by 49
+ *  0b110001..Divide by 50
+ *  0b110010..Divide by 51
+ *  0b110011..Divide by 52
+ *  0b110100..Divide by 53
+ *  0b110101..Divide by 54
+ *  0b110110..Divide by 55
+ *  0b110111..Divide by 56
+ *  0b111000..Divide by 57
+ *  0b111001..Divide by 58
+ *  0b111010..Divide by 59
+ *  0b111011..Divide by 60
+ *  0b111100..Divide by 61
+ *  0b111101..Divide by 62
+ *  0b111110..Divide by 63
+ *  0b111111..Divide by 64
+ */
 #define CCM_CS1CDR_SAI3_CLK_PODF(x)              (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI3_CLK_PODF_SHIFT)) & CCM_CS1CDR_SAI3_CLK_PODF_MASK)
 #define CCM_CS1CDR_SAI3_CLK_PRED_MASK            (0x1C00000U)
 #define CCM_CS1CDR_SAI3_CLK_PRED_SHIFT           (22U)
+/*! SAI3_CLK_PRED
+ *  0b000..divide by 1
+ *  0b001..divide by 2
+ *  0b010..divide by 3
+ *  0b011..divide by 4
+ *  0b100..divide by 5
+ *  0b101..divide by 6
+ *  0b110..divide by 7
+ *  0b111..divide by 8
+ */
 #define CCM_CS1CDR_SAI3_CLK_PRED(x)              (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI3_CLK_PRED_SHIFT)) & CCM_CS1CDR_SAI3_CLK_PRED_MASK)
 #define CCM_CS1CDR_FLEXIO2_CLK_PODF_MASK         (0xE000000U)
 #define CCM_CS1CDR_FLEXIO2_CLK_PODF_SHIFT        (25U)
+/*! FLEXIO2_CLK_PODF - Divider for flexio2 clock. Divider should be updated when output clock is gated.
+ *  0b000..Divide by 1
+ *  0b001..Divide by 2
+ *  0b010..Divide by 3
+ *  0b011..Divide by 4
+ *  0b100..Divide by 5
+ *  0b101..Divide by 6
+ *  0b110..Divide by 7
+ *  0b111..Divide by 8
+ */
 #define CCM_CS1CDR_FLEXIO2_CLK_PODF(x)           (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_FLEXIO2_CLK_PODF_SHIFT)) & CCM_CS1CDR_FLEXIO2_CLK_PODF_MASK)
 /*! @} */
 
@@ -3270,9 +4894,86 @@ typedef struct {
 /*! @{ */
 #define CCM_CS2CDR_SAI2_CLK_PODF_MASK            (0x3FU)
 #define CCM_CS2CDR_SAI2_CLK_PODF_SHIFT           (0U)
+/*! SAI2_CLK_PODF - Divider for sai2 clock podf. The input clock to this divider should be lower
+ *    than 300Mhz, the predivider can be used to achieve this.
+ *  0b000000..Divide by 1
+ *  0b000001..Divide by 2
+ *  0b000010..Divide by 3
+ *  0b000011..Divide by 4
+ *  0b000100..Divide by 5
+ *  0b000101..Divide by 6
+ *  0b000110..Divide by 7
+ *  0b000111..Divide by 8
+ *  0b001000..Divide by 9
+ *  0b001001..Divide by 10
+ *  0b001010..Divide by 11
+ *  0b001011..Divide by 12
+ *  0b001100..Divide by 13
+ *  0b001101..Divide by 14
+ *  0b001110..Divide by 15
+ *  0b001111..Divide by 16
+ *  0b010000..Divide by 17
+ *  0b010001..Divide by 18
+ *  0b010010..Divide by 19
+ *  0b010011..Divide by 20
+ *  0b010100..Divide by 21
+ *  0b010101..Divide by 22
+ *  0b010110..Divide by 23
+ *  0b010111..Divide by 24
+ *  0b011000..Divide by 25
+ *  0b011001..Divide by 26
+ *  0b011010..Divide by 27
+ *  0b011011..Divide by 28
+ *  0b011100..Divide by 29
+ *  0b011101..Divide by 30
+ *  0b011110..Divide by 31
+ *  0b011111..Divide by 32
+ *  0b100000..Divide by 33
+ *  0b100001..Divide by 34
+ *  0b100010..Divide by 35
+ *  0b100011..Divide by 36
+ *  0b100100..Divide by 37
+ *  0b100101..Divide by 38
+ *  0b100110..Divide by 39
+ *  0b100111..Divide by 40
+ *  0b101000..Divide by 41
+ *  0b101001..Divide by 42
+ *  0b101010..Divide by 43
+ *  0b101011..Divide by 44
+ *  0b101100..Divide by 45
+ *  0b101101..Divide by 46
+ *  0b101110..Divide by 47
+ *  0b101111..Divide by 48
+ *  0b110000..Divide by 49
+ *  0b110001..Divide by 50
+ *  0b110010..Divide by 51
+ *  0b110011..Divide by 52
+ *  0b110100..Divide by 53
+ *  0b110101..Divide by 54
+ *  0b110110..Divide by 55
+ *  0b110111..Divide by 56
+ *  0b111000..Divide by 57
+ *  0b111001..Divide by 58
+ *  0b111010..Divide by 59
+ *  0b111011..Divide by 60
+ *  0b111100..Divide by 61
+ *  0b111101..Divide by 62
+ *  0b111110..Divide by 63
+ *  0b111111..Divide by 64
+ */
 #define CCM_CS2CDR_SAI2_CLK_PODF(x)              (((uint32_t)(((uint32_t)(x)) << CCM_CS2CDR_SAI2_CLK_PODF_SHIFT)) & CCM_CS2CDR_SAI2_CLK_PODF_MASK)
 #define CCM_CS2CDR_SAI2_CLK_PRED_MASK            (0x1C0U)
 #define CCM_CS2CDR_SAI2_CLK_PRED_SHIFT           (6U)
+/*! SAI2_CLK_PRED
+ *  0b000..divide by 1
+ *  0b001..divide by 2
+ *  0b010..divide by 3
+ *  0b011..divide by 4
+ *  0b100..divide by 5
+ *  0b101..divide by 6
+ *  0b110..divide by 7
+ *  0b111..divide by 8
+ */
 #define CCM_CS2CDR_SAI2_CLK_PRED(x)              (((uint32_t)(((uint32_t)(x)) << CCM_CS2CDR_SAI2_CLK_PRED_SHIFT)) & CCM_CS2CDR_SAI2_CLK_PRED_MASK)
 /*! @} */
 
@@ -3280,21 +4981,73 @@ typedef struct {
 /*! @{ */
 #define CCM_CDCDR_FLEXIO1_CLK_SEL_MASK           (0x180U)
 #define CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT          (7U)
+/*! FLEXIO1_CLK_SEL
+ *  0b00..derive clock from PLL4
+ *  0b01..derive clock from PLL3 PFD2
+ *  0b10..derive clock from PLL5
+ *  0b11..derive clock from pll3_sw_clk
+ */
 #define CCM_CDCDR_FLEXIO1_CLK_SEL(x)             (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT)) & CCM_CDCDR_FLEXIO1_CLK_SEL_MASK)
 #define CCM_CDCDR_FLEXIO1_CLK_PODF_MASK          (0xE00U)
 #define CCM_CDCDR_FLEXIO1_CLK_PODF_SHIFT         (9U)
+/*! FLEXIO1_CLK_PODF - Divider for flexio1 clock podf. Divider should be updated when output clock is gated.
+ *  0b000..Divide by 1
+ *  0b001..Divide by 2
+ *  0b010..Divide by 3
+ *  0b011..Divide by 4
+ *  0b100..Divide by 5
+ *  0b101..Divide by 6
+ *  0b110..Divide by 7
+ *  0b111..Divide by 8
+ */
 #define CCM_CDCDR_FLEXIO1_CLK_PODF(x)            (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_FLEXIO1_CLK_PODF_SHIFT)) & CCM_CDCDR_FLEXIO1_CLK_PODF_MASK)
 #define CCM_CDCDR_FLEXIO1_CLK_PRED_MASK          (0x7000U)
 #define CCM_CDCDR_FLEXIO1_CLK_PRED_SHIFT         (12U)
+/*! FLEXIO1_CLK_PRED - Divider for flexio1 clock pred. Divider should be updated when output clock is gated.
+ *  0b000..Divide by 1
+ *  0b001..Divide by 2
+ *  0b010..Divide by 3
+ *  0b011..Divide by 4
+ *  0b100..Divide by 5
+ *  0b101..Divide by 6
+ *  0b110..Divide by 7
+ *  0b111..Divide by 8
+ */
 #define CCM_CDCDR_FLEXIO1_CLK_PRED(x)            (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_FLEXIO1_CLK_PRED_SHIFT)) & CCM_CDCDR_FLEXIO1_CLK_PRED_MASK)
 #define CCM_CDCDR_SPDIF0_CLK_SEL_MASK            (0x300000U)
 #define CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT           (20U)
+/*! SPDIF0_CLK_SEL
+ *  0b00..derive clock from PLL4
+ *  0b01..derive clock from PLL3 PFD2
+ *  0b10..derive clock from PLL5
+ *  0b11..derive clock from pll3_sw_clk
+ */
 #define CCM_CDCDR_SPDIF0_CLK_SEL(x)              (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_SEL_MASK)
 #define CCM_CDCDR_SPDIF0_CLK_PODF_MASK           (0x1C00000U)
 #define CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT          (22U)
+/*! SPDIF0_CLK_PODF - Divider for spdif0 clock podf. Divider should be updated when output clock is gated.
+ *  0b000..Divide by 1
+ *  0b001..Divide by 2
+ *  0b010..Divide by 3
+ *  0b011..Divide by 4
+ *  0b100..Divide by 5
+ *  0b101..Divide by 6
+ *  0b110..Divide by 7
+ *  0b111..Divide by 8
+ */
 #define CCM_CDCDR_SPDIF0_CLK_PODF(x)             (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_PODF_MASK)
 #define CCM_CDCDR_SPDIF0_CLK_PRED_MASK           (0xE000000U)
 #define CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT          (25U)
+/*! SPDIF0_CLK_PRED - Divider for spdif0 clock pred. Divider should be updated when output clock is gated.
+ *  0b000..Divide by 1
+ *  0b001..Divide by 2
+ *  0b010..Divide by 3
+ *  0b011..Divide by 4
+ *  0b100..Divide by 5
+ *  0b101..Divide by 6
+ *  0b110..Divide by 7
+ *  0b111..Divide by 8
+ */
 #define CCM_CDCDR_SPDIF0_CLK_PRED(x)             (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_PRED_MASK)
 /*! @} */
 
@@ -3302,15 +5055,105 @@ typedef struct {
 /*! @{ */
 #define CCM_CSCDR2_LCDIF_PRED_MASK               (0x7000U)
 #define CCM_CSCDR2_LCDIF_PRED_SHIFT              (12U)
+/*! LCDIF_PRED
+ *  0b000..divide by 1
+ *  0b001..divide by 2
+ *  0b010..divide by 3
+ *  0b011..divide by 4
+ *  0b100..divide by 5
+ *  0b101..divide by 6
+ *  0b110..divide by 7
+ *  0b111..divide by 8
+ */
 #define CCM_CSCDR2_LCDIF_PRED(x)                 (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LCDIF_PRED_SHIFT)) & CCM_CSCDR2_LCDIF_PRED_MASK)
 #define CCM_CSCDR2_LCDIF_PRE_CLK_SEL_MASK        (0x38000U)
 #define CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT       (15U)
+/*! LCDIF_PRE_CLK_SEL
+ *  0b000..derive clock from PLL2
+ *  0b001..derive clock from PLL3 PFD3
+ *  0b010..derive clock from PLL5
+ *  0b011..derive clock from PLL2 PFD0
+ *  0b100..derive clock from PLL2 PFD1
+ *  0b101..derive clock from PLL3 PFD1
+ */
 #define CCM_CSCDR2_LCDIF_PRE_CLK_SEL(x)          (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT)) & CCM_CSCDR2_LCDIF_PRE_CLK_SEL_MASK)
 #define CCM_CSCDR2_LPI2C_CLK_SEL_MASK            (0x40000U)
 #define CCM_CSCDR2_LPI2C_CLK_SEL_SHIFT           (18U)
+/*! LPI2C_CLK_SEL
+ *  0b0..derive clock from pll3_60m
+ *  0b1..derive clock from osc_clk
+ */
 #define CCM_CSCDR2_LPI2C_CLK_SEL(x)              (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LPI2C_CLK_SEL_SHIFT)) & CCM_CSCDR2_LPI2C_CLK_SEL_MASK)
 #define CCM_CSCDR2_LPI2C_CLK_PODF_MASK           (0x1F80000U)
 #define CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT          (19U)
+/*! LPI2C_CLK_PODF - Divider for lpi2c clock podf. Divider should be updated when output clock is
+ *    gated. The input clock to this divider should be lower than 300Mhz, the predivider can be used
+ *    to achieve this.
+ *  0b000000..Divide by 1
+ *  0b000001..Divide by 2
+ *  0b000010..Divide by 3
+ *  0b000011..Divide by 4
+ *  0b000100..Divide by 5
+ *  0b000101..Divide by 6
+ *  0b000110..Divide by 7
+ *  0b000111..Divide by 8
+ *  0b001000..Divide by 9
+ *  0b001001..Divide by 10
+ *  0b001010..Divide by 11
+ *  0b001011..Divide by 12
+ *  0b001100..Divide by 13
+ *  0b001101..Divide by 14
+ *  0b001110..Divide by 15
+ *  0b001111..Divide by 16
+ *  0b010000..Divide by 17
+ *  0b010001..Divide by 18
+ *  0b010010..Divide by 19
+ *  0b010011..Divide by 20
+ *  0b010100..Divide by 21
+ *  0b010101..Divide by 22
+ *  0b010110..Divide by 23
+ *  0b010111..Divide by 24
+ *  0b011000..Divide by 25
+ *  0b011001..Divide by 26
+ *  0b011010..Divide by 27
+ *  0b011011..Divide by 28
+ *  0b011100..Divide by 29
+ *  0b011101..Divide by 30
+ *  0b011110..Divide by 31
+ *  0b011111..Divide by 32
+ *  0b100000..Divide by 33
+ *  0b100001..Divide by 34
+ *  0b100010..Divide by 35
+ *  0b100011..Divide by 36
+ *  0b100100..Divide by 37
+ *  0b100101..Divide by 38
+ *  0b100110..Divide by 39
+ *  0b100111..Divide by 40
+ *  0b101000..Divide by 41
+ *  0b101001..Divide by 42
+ *  0b101010..Divide by 43
+ *  0b101011..Divide by 44
+ *  0b101100..Divide by 45
+ *  0b101101..Divide by 46
+ *  0b101110..Divide by 47
+ *  0b101111..Divide by 48
+ *  0b110000..Divide by 49
+ *  0b110001..Divide by 50
+ *  0b110010..Divide by 51
+ *  0b110011..Divide by 52
+ *  0b110100..Divide by 53
+ *  0b110101..Divide by 54
+ *  0b110110..Divide by 55
+ *  0b110111..Divide by 56
+ *  0b111000..Divide by 57
+ *  0b111001..Divide by 58
+ *  0b111010..Divide by 59
+ *  0b111011..Divide by 60
+ *  0b111100..Divide by 61
+ *  0b111101..Divide by 62
+ *  0b111110..Divide by 63
+ *  0b111111..Divide by 64
+ */
 #define CCM_CSCDR2_LPI2C_CLK_PODF(x)             (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT)) & CCM_CSCDR2_LPI2C_CLK_PODF_MASK)
 /*! @} */
 
@@ -3318,9 +5161,25 @@ typedef struct {
 /*! @{ */
 #define CCM_CSCDR3_CSI_CLK_SEL_MASK              (0x600U)
 #define CCM_CSCDR3_CSI_CLK_SEL_SHIFT             (9U)
+/*! CSI_CLK_SEL
+ *  0b00..derive clock from osc_clk (24M)
+ *  0b01..derive clock from PLL2 PFD2
+ *  0b10..derive clock from pll3_120M
+ *  0b11..derive clock from PLL3 PFD1
+ */
 #define CCM_CSCDR3_CSI_CLK_SEL(x)                (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR3_CSI_CLK_SEL_SHIFT)) & CCM_CSCDR3_CSI_CLK_SEL_MASK)
 #define CCM_CSCDR3_CSI_PODF_MASK                 (0x3800U)
 #define CCM_CSCDR3_CSI_PODF_SHIFT                (11U)
+/*! CSI_PODF
+ *  0b000..divide by 1
+ *  0b001..divide by 2
+ *  0b010..divide by 3
+ *  0b011..divide by 4
+ *  0b100..divide by 5
+ *  0b101..divide by 6
+ *  0b110..divide by 7
+ *  0b111..divide by 8
+ */
 #define CCM_CSCDR3_CSI_PODF(x)                   (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR3_CSI_PODF_SHIFT)) & CCM_CSCDR3_CSI_PODF_MASK)
 /*! @} */
 
@@ -3328,18 +5187,43 @@ typedef struct {
 /*! @{ */
 #define CCM_CDHIPR_SEMC_PODF_BUSY_MASK           (0x1U)
 #define CCM_CDHIPR_SEMC_PODF_BUSY_SHIFT          (0U)
+/*! SEMC_PODF_BUSY
+ *  0b0..divider is not busy and its value represents the actual division.
+ *  0b1..divider is busy with handshake process with module. The value read in the divider represents the previous
+ *       value of the division factor, and after the handshake the written value of the semc_podf will be applied.
+ */
 #define CCM_CDHIPR_SEMC_PODF_BUSY(x)             (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_SEMC_PODF_BUSY_SHIFT)) & CCM_CDHIPR_SEMC_PODF_BUSY_MASK)
 #define CCM_CDHIPR_AHB_PODF_BUSY_MASK            (0x2U)
 #define CCM_CDHIPR_AHB_PODF_BUSY_SHIFT           (1U)
+/*! AHB_PODF_BUSY
+ *  0b0..divider is not busy and its value represents the actual division.
+ *  0b1..divider is busy with handshake process with module. The value read in the divider represents the previous
+ *       value of the division factor, and after the handshake the written value of the ahb_podf will be applied.
+ */
 #define CCM_CDHIPR_AHB_PODF_BUSY(x)              (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_AHB_PODF_BUSY_SHIFT)) & CCM_CDHIPR_AHB_PODF_BUSY_MASK)
 #define CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_MASK     (0x8U)
 #define CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_SHIFT    (3U)
+/*! PERIPH2_CLK_SEL_BUSY
+ *  0b0..mux is not busy and its value represents the actual division.
+ *  0b1..mux is busy with handshake process with module. The value read in the periph2_clk_sel represents the
+ *       previous value of select, and after the handshake periph2_clk_sel value will be applied.
+ */
 #define CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY(x)       (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_SHIFT)) & CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_MASK)
 #define CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_MASK      (0x20U)
 #define CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_SHIFT     (5U)
+/*! PERIPH_CLK_SEL_BUSY
+ *  0b0..mux is not busy and its value represents the actual division.
+ *  0b1..mux is busy with handshake process with module. The value read in the periph_clk_sel represents the
+ *       previous value of select, and after the handshake periph_clk_sel value will be applied.
+ */
 #define CCM_CDHIPR_PERIPH_CLK_SEL_BUSY(x)        (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_SHIFT)) & CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_MASK)
 #define CCM_CDHIPR_ARM_PODF_BUSY_MASK            (0x10000U)
 #define CCM_CDHIPR_ARM_PODF_BUSY_SHIFT           (16U)
+/*! ARM_PODF_BUSY
+ *  0b0..divider is not busy and its value represents the actual division.
+ *  0b1..divider is busy with handshake process with module. The value read in the divider represents the previous
+ *       value of the division factor, and after the handshake the written value of the arm_podf will be applied.
+ */
 #define CCM_CDHIPR_ARM_PODF_BUSY(x)              (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_ARM_PODF_BUSY_SHIFT)) & CCM_CDHIPR_ARM_PODF_BUSY_MASK)
 /*! @} */
 
@@ -3347,24 +5231,60 @@ typedef struct {
 /*! @{ */
 #define CCM_CLPCR_LPM_MASK                       (0x3U)
 #define CCM_CLPCR_LPM_SHIFT                      (0U)
+/*! LPM
+ *  0b00..Remain in run mode
+ *  0b01..Transfer to wait mode
+ *  0b10..Transfer to stop mode
+ *  0b11..Reserved
+ */
 #define CCM_CLPCR_LPM(x)                         (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_LPM_SHIFT)) & CCM_CLPCR_LPM_MASK)
 #define CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK        (0x20U)
 #define CCM_CLPCR_ARM_CLK_DIS_ON_LPM_SHIFT       (5U)
+/*! ARM_CLK_DIS_ON_LPM
+ *  0b0..ARM clock enabled on wait mode.
+ *  0b1..ARM clock disabled on wait mode. .
+ */
 #define CCM_CLPCR_ARM_CLK_DIS_ON_LPM(x)          (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_ARM_CLK_DIS_ON_LPM_SHIFT)) & CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK)
 #define CCM_CLPCR_SBYOS_MASK                     (0x40U)
 #define CCM_CLPCR_SBYOS_SHIFT                    (6U)
+/*! SBYOS
+ *  0b0..On-chip oscillator will not be powered down, after next entrance to STOP mode. (CCM_REF_EN_B will remain
+ *       asserted - '0' and cosc_pwrdown will remain de asserted - '0')
+ *  0b1..On-chip oscillator will be powered down, after next entrance to STOP mode. (CCM_REF_EN_B will be
+ *       deasserted - '1' and cosc_pwrdown will be asserted - '1'). When returning from STOP mode, external oscillator will
+ *       be enabled again, on-chip oscillator will return to oscillator mode, and after oscnt count, CCM will
+ *       continue with the exit from the STOP mode process.
+ */
 #define CCM_CLPCR_SBYOS(x)                       (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_SBYOS_SHIFT)) & CCM_CLPCR_SBYOS_MASK)
 #define CCM_CLPCR_DIS_REF_OSC_MASK               (0x80U)
 #define CCM_CLPCR_DIS_REF_OSC_SHIFT              (7U)
+/*! DIS_REF_OSC
+ *  0b0..external high frequency oscillator will be enabled, i.e. CCM_REF_EN_B = '0'.
+ *  0b1..external high frequency oscillator will be disabled, i.e. CCM_REF_EN_B = '1'
+ */
 #define CCM_CLPCR_DIS_REF_OSC(x)                 (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_DIS_REF_OSC_SHIFT)) & CCM_CLPCR_DIS_REF_OSC_MASK)
 #define CCM_CLPCR_VSTBY_MASK                     (0x100U)
 #define CCM_CLPCR_VSTBY_SHIFT                    (8U)
+/*! VSTBY
+ *  0b0..Voltage will not be changed to standby voltage after next entrance to STOP mode. ( PMIC_STBY_REQ will remain negated - '0')
+ *  0b1..Voltage will be requested to change to standby voltage after next entrance to stop mode. ( PMIC_STBY_REQ will be asserted - '1').
+ */
 #define CCM_CLPCR_VSTBY(x)                       (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_VSTBY_SHIFT)) & CCM_CLPCR_VSTBY_MASK)
 #define CCM_CLPCR_STBY_COUNT_MASK                (0x600U)
 #define CCM_CLPCR_STBY_COUNT_SHIFT               (9U)
+/*! STBY_COUNT
+ *  0b00..CCM will wait (1*pmic_delay_scaler)+1 ckil clock cycles
+ *  0b01..CCM will wait (3*pmic_delay_scaler)+1 ckil clock cycles
+ *  0b10..CCM will wait (7*pmic_delay_scaler)+1 ckil clock cycles
+ *  0b11..CCM will wait (15*pmic_delay_scaler)+1 ckil clock cycles
+ */
 #define CCM_CLPCR_STBY_COUNT(x)                  (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_STBY_COUNT_SHIFT)) & CCM_CLPCR_STBY_COUNT_MASK)
 #define CCM_CLPCR_COSC_PWRDOWN_MASK              (0x800U)
 #define CCM_CLPCR_COSC_PWRDOWN_SHIFT             (11U)
+/*! COSC_PWRDOWN
+ *  0b0..On chip oscillator will not be powered down, i.e. cosc_pwrdown = '0'.
+ *  0b1..On chip oscillator will be powered down, i.e. cosc_pwrdown = '1'.
+ */
 #define CCM_CLPCR_COSC_PWRDOWN(x)                (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_COSC_PWRDOWN_SHIFT)) & CCM_CLPCR_COSC_PWRDOWN_MASK)
 #define CCM_CLPCR_BYPASS_LPM_HS1_MASK            (0x80000U)
 #define CCM_CLPCR_BYPASS_LPM_HS1_SHIFT           (19U)
@@ -3374,12 +5294,24 @@ typedef struct {
 #define CCM_CLPCR_BYPASS_LPM_HS0(x)              (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_BYPASS_LPM_HS0_SHIFT)) & CCM_CLPCR_BYPASS_LPM_HS0_MASK)
 #define CCM_CLPCR_MASK_CORE0_WFI_MASK            (0x400000U)
 #define CCM_CLPCR_MASK_CORE0_WFI_SHIFT           (22U)
+/*! MASK_CORE0_WFI
+ *  0b0..WFI of core0 is not masked
+ *  0b1..WFI of core0 is masked
+ */
 #define CCM_CLPCR_MASK_CORE0_WFI(x)              (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_CORE0_WFI_SHIFT)) & CCM_CLPCR_MASK_CORE0_WFI_MASK)
 #define CCM_CLPCR_MASK_SCU_IDLE_MASK             (0x4000000U)
 #define CCM_CLPCR_MASK_SCU_IDLE_SHIFT            (26U)
+/*! MASK_SCU_IDLE
+ *  0b1..SCU IDLE is masked
+ *  0b0..SCU IDLE is not masked
+ */
 #define CCM_CLPCR_MASK_SCU_IDLE(x)               (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_SCU_IDLE_SHIFT)) & CCM_CLPCR_MASK_SCU_IDLE_MASK)
 #define CCM_CLPCR_MASK_L2CC_IDLE_MASK            (0x8000000U)
 #define CCM_CLPCR_MASK_L2CC_IDLE_SHIFT           (27U)
+/*! MASK_L2CC_IDLE
+ *  0b1..L2CC IDLE is masked
+ *  0b0..L2CC IDLE is not masked
+ */
 #define CCM_CLPCR_MASK_L2CC_IDLE(x)              (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_L2CC_IDLE_SHIFT)) & CCM_CLPCR_MASK_L2CC_IDLE_MASK)
 /*! @} */
 
@@ -3387,24 +5319,52 @@ typedef struct {
 /*! @{ */
 #define CCM_CISR_LRF_PLL_MASK                    (0x1U)
 #define CCM_CISR_LRF_PLL_SHIFT                   (0U)
+/*! LRF_PLL
+ *  0b0..interrupt is not generated due to lock ready of all enabled and not bypaseed PLLs
+ *  0b1..interrupt generated due to lock ready of all enabled and not bypaseed PLLs
+ */
 #define CCM_CISR_LRF_PLL(x)                      (((uint32_t)(((uint32_t)(x)) << CCM_CISR_LRF_PLL_SHIFT)) & CCM_CISR_LRF_PLL_MASK)
 #define CCM_CISR_COSC_READY_MASK                 (0x40U)
 #define CCM_CISR_COSC_READY_SHIFT                (6U)
+/*! COSC_READY
+ *  0b0..interrupt is not generated due to on board oscillator ready
+ *  0b1..interrupt generated due to on board oscillator ready
+ */
 #define CCM_CISR_COSC_READY(x)                   (((uint32_t)(((uint32_t)(x)) << CCM_CISR_COSC_READY_SHIFT)) & CCM_CISR_COSC_READY_MASK)
 #define CCM_CISR_SEMC_PODF_LOADED_MASK           (0x20000U)
 #define CCM_CISR_SEMC_PODF_LOADED_SHIFT          (17U)
+/*! SEMC_PODF_LOADED
+ *  0b0..interrupt is not generated due to frequency change of semc_podf
+ *  0b1..interrupt generated due to frequency change of semc_podf
+ */
 #define CCM_CISR_SEMC_PODF_LOADED(x)             (((uint32_t)(((uint32_t)(x)) << CCM_CISR_SEMC_PODF_LOADED_SHIFT)) & CCM_CISR_SEMC_PODF_LOADED_MASK)
 #define CCM_CISR_PERIPH2_CLK_SEL_LOADED_MASK     (0x80000U)
 #define CCM_CISR_PERIPH2_CLK_SEL_LOADED_SHIFT    (19U)
+/*! PERIPH2_CLK_SEL_LOADED
+ *  0b0..interrupt is not generated due to frequency change of periph2_clk_sel
+ *  0b1..interrupt generated due to frequency change of periph2_clk_sel
+ */
 #define CCM_CISR_PERIPH2_CLK_SEL_LOADED(x)       (((uint32_t)(((uint32_t)(x)) << CCM_CISR_PERIPH2_CLK_SEL_LOADED_SHIFT)) & CCM_CISR_PERIPH2_CLK_SEL_LOADED_MASK)
 #define CCM_CISR_AHB_PODF_LOADED_MASK            (0x100000U)
 #define CCM_CISR_AHB_PODF_LOADED_SHIFT           (20U)
+/*! AHB_PODF_LOADED
+ *  0b0..interrupt is not generated due to frequency change of ahb_podf
+ *  0b1..interrupt generated due to frequency change of ahb_podf
+ */
 #define CCM_CISR_AHB_PODF_LOADED(x)              (((uint32_t)(((uint32_t)(x)) << CCM_CISR_AHB_PODF_LOADED_SHIFT)) & CCM_CISR_AHB_PODF_LOADED_MASK)
 #define CCM_CISR_PERIPH_CLK_SEL_LOADED_MASK      (0x400000U)
 #define CCM_CISR_PERIPH_CLK_SEL_LOADED_SHIFT     (22U)
+/*! PERIPH_CLK_SEL_LOADED
+ *  0b0..interrupt is not generated due to update of periph_clk_sel.
+ *  0b1..interrupt generated due to update of periph_clk_sel.
+ */
 #define CCM_CISR_PERIPH_CLK_SEL_LOADED(x)        (((uint32_t)(((uint32_t)(x)) << CCM_CISR_PERIPH_CLK_SEL_LOADED_SHIFT)) & CCM_CISR_PERIPH_CLK_SEL_LOADED_MASK)
 #define CCM_CISR_ARM_PODF_LOADED_MASK            (0x4000000U)
 #define CCM_CISR_ARM_PODF_LOADED_SHIFT           (26U)
+/*! ARM_PODF_LOADED
+ *  0b0..interrupt is not generated due to frequency change of arm_podf
+ *  0b1..interrupt generated due to frequency change of arm_podf
+ */
 #define CCM_CISR_ARM_PODF_LOADED(x)              (((uint32_t)(((uint32_t)(x)) << CCM_CISR_ARM_PODF_LOADED_SHIFT)) & CCM_CISR_ARM_PODF_LOADED_MASK)
 /*! @} */
 
@@ -3412,24 +5372,52 @@ typedef struct {
 /*! @{ */
 #define CCM_CIMR_MASK_LRF_PLL_MASK               (0x1U)
 #define CCM_CIMR_MASK_LRF_PLL_SHIFT              (0U)
+/*! MASK_LRF_PLL
+ *  0b0..don't mask interrupt due to lrf of PLLs - interrupt will be created
+ *  0b1..mask interrupt due to lrf of PLLs
+ */
 #define CCM_CIMR_MASK_LRF_PLL(x)                 (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_LRF_PLL_SHIFT)) & CCM_CIMR_MASK_LRF_PLL_MASK)
 #define CCM_CIMR_MASK_COSC_READY_MASK            (0x40U)
 #define CCM_CIMR_MASK_COSC_READY_SHIFT           (6U)
+/*! MASK_COSC_READY
+ *  0b0..don't mask interrupt due to on board oscillator ready - interrupt will be created
+ *  0b1..mask interrupt due to on board oscillator ready
+ */
 #define CCM_CIMR_MASK_COSC_READY(x)              (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_COSC_READY_SHIFT)) & CCM_CIMR_MASK_COSC_READY_MASK)
 #define CCM_CIMR_MASK_SEMC_PODF_LOADED_MASK      (0x20000U)
 #define CCM_CIMR_MASK_SEMC_PODF_LOADED_SHIFT     (17U)
+/*! MASK_SEMC_PODF_LOADED
+ *  0b0..don't mask interrupt due to frequency change of semc_podf - interrupt will be created
+ *  0b1..mask interrupt due to frequency change of semc_podf
+ */
 #define CCM_CIMR_MASK_SEMC_PODF_LOADED(x)        (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_SEMC_PODF_LOADED_SHIFT)) & CCM_CIMR_MASK_SEMC_PODF_LOADED_MASK)
 #define CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_MASK (0x80000U)
 #define CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_SHIFT (19U)
+/*! MASK_PERIPH2_CLK_SEL_LOADED
+ *  0b0..don't mask interrupt due to update of periph2_clk_sel - interrupt will be created
+ *  0b1..mask interrupt due to update of periph2_clk_sel
+ */
 #define CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED(x)  (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_SHIFT)) & CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_MASK)
 #define CCM_CIMR_MASK_AHB_PODF_LOADED_MASK       (0x100000U)
 #define CCM_CIMR_MASK_AHB_PODF_LOADED_SHIFT      (20U)
+/*! MASK_AHB_PODF_LOADED
+ *  0b0..don't mask interrupt due to frequency change of ahb_podf - interrupt will be created
+ *  0b1..mask interrupt due to frequency change of ahb_podf
+ */
 #define CCM_CIMR_MASK_AHB_PODF_LOADED(x)         (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_AHB_PODF_LOADED_SHIFT)) & CCM_CIMR_MASK_AHB_PODF_LOADED_MASK)
 #define CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_MASK (0x400000U)
 #define CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_SHIFT (22U)
+/*! MASK_PERIPH_CLK_SEL_LOADED
+ *  0b0..don't mask interrupt due to update of periph_clk_sel - interrupt will be created
+ *  0b1..mask interrupt due to update of periph_clk_sel
+ */
 #define CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_SHIFT)) & CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_MASK)
 #define CCM_CIMR_ARM_PODF_LOADED_MASK            (0x4000000U)
 #define CCM_CIMR_ARM_PODF_LOADED_SHIFT           (26U)
+/*! ARM_PODF_LOADED
+ *  0b0..don't mask interrupt due to frequency change of arm_podf - interrupt will be created
+ *  0b1..mask interrupt due to frequency change of arm_podf
+ */
 #define CCM_CIMR_ARM_PODF_LOADED(x)              (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_ARM_PODF_LOADED_SHIFT)) & CCM_CIMR_ARM_PODF_LOADED_MASK)
 /*! @} */
 
@@ -3437,24 +5425,85 @@ typedef struct {
 /*! @{ */
 #define CCM_CCOSR_CLKO1_SEL_MASK                 (0xFU)
 #define CCM_CCOSR_CLKO1_SEL_SHIFT                (0U)
+/*! CLKO1_SEL
+ *  0b0000..USB1 PLL clock (divided by 2)
+ *  0b0001..SYS PLL clock (divided by 2)
+ *  0b0011..VIDEO PLL clock (divided by 2)
+ *  0b0101..semc_clk_root
+ *  0b0110..Reserved
+ *  0b1010..lcdif_pix_clk_root
+ *  0b1011..ahb_clk_root
+ *  0b1100..ipg_clk_root
+ *  0b1101..perclk_root
+ *  0b1110..ckil_sync_clk_root
+ *  0b1111..pll4_main_clk
+ */
 #define CCM_CCOSR_CLKO1_SEL(x)                   (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO1_SEL_SHIFT)) & CCM_CCOSR_CLKO1_SEL_MASK)
 #define CCM_CCOSR_CLKO1_DIV_MASK                 (0x70U)
 #define CCM_CCOSR_CLKO1_DIV_SHIFT                (4U)
+/*! CLKO1_DIV
+ *  0b000..divide by 1
+ *  0b001..divide by 2
+ *  0b010..divide by 3
+ *  0b011..divide by 4
+ *  0b100..divide by 5
+ *  0b101..divide by 6
+ *  0b110..divide by 7
+ *  0b111..divide by 8
+ */
 #define CCM_CCOSR_CLKO1_DIV(x)                   (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO1_DIV_SHIFT)) & CCM_CCOSR_CLKO1_DIV_MASK)
 #define CCM_CCOSR_CLKO1_EN_MASK                  (0x80U)
 #define CCM_CCOSR_CLKO1_EN_SHIFT                 (7U)
+/*! CLKO1_EN
+ *  0b0..CCM_CLKO1 disabled.
+ *  0b1..CCM_CLKO1 enabled.
+ */
 #define CCM_CCOSR_CLKO1_EN(x)                    (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO1_EN_SHIFT)) & CCM_CCOSR_CLKO1_EN_MASK)
 #define CCM_CCOSR_CLK_OUT_SEL_MASK               (0x100U)
 #define CCM_CCOSR_CLK_OUT_SEL_SHIFT              (8U)
+/*! CLK_OUT_SEL
+ *  0b0..CCM_CLKO1 output drives CCM_CLKO1 clock
+ *  0b1..CCM_CLKO1 output drives CCM_CLKO2 clock
+ */
 #define CCM_CCOSR_CLK_OUT_SEL(x)                 (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLK_OUT_SEL_SHIFT)) & CCM_CCOSR_CLK_OUT_SEL_MASK)
 #define CCM_CCOSR_CLKO2_SEL_MASK                 (0x1F0000U)
 #define CCM_CCOSR_CLKO2_SEL_SHIFT                (16U)
+/*! CLKO2_SEL
+ *  0b00011..usdhc1_clk_root
+ *  0b00101..wrck_clk_root
+ *  0b00110..lpi2c_clk_root
+ *  0b01011..csi_clk_root
+ *  0b01110..osc_clk
+ *  0b10001..usdhc2_clk_root
+ *  0b10010..sai1_clk_root
+ *  0b10011..sai2_clk_root
+ *  0b10100..sai3_clk_root
+ *  0b10111..can_clk_root
+ *  0b11011..flexspi_clk_root
+ *  0b11100..uart_clk_root
+ *  0b11101..spdif0_clk_root
+ *  0b11111..Reserved
+ */
 #define CCM_CCOSR_CLKO2_SEL(x)                   (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_SEL_SHIFT)) & CCM_CCOSR_CLKO2_SEL_MASK)
 #define CCM_CCOSR_CLKO2_DIV_MASK                 (0xE00000U)
 #define CCM_CCOSR_CLKO2_DIV_SHIFT                (21U)
+/*! CLKO2_DIV
+ *  0b000..divide by 1
+ *  0b001..divide by 2
+ *  0b010..divide by 3
+ *  0b011..divide by 4
+ *  0b100..divide by 5
+ *  0b101..divide by 6
+ *  0b110..divide by 7
+ *  0b111..divide by 8
+ */
 #define CCM_CCOSR_CLKO2_DIV(x)                   (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_DIV_SHIFT)) & CCM_CCOSR_CLKO2_DIV_MASK)
 #define CCM_CCOSR_CLKO2_EN_MASK                  (0x1000000U)
 #define CCM_CCOSR_CLKO2_EN_SHIFT                 (24U)
+/*! CLKO2_EN
+ *  0b0..CCM_CLKO2 disabled.
+ *  0b1..CCM_CLKO2 enabled.
+ */
 #define CCM_CCOSR_CLKO2_EN(x)                    (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_EN_SHIFT)) & CCM_CCOSR_CLKO2_EN_MASK)
 /*! @} */
 
@@ -3462,18 +5511,40 @@ typedef struct {
 /*! @{ */
 #define CCM_CGPR_PMIC_DELAY_SCALER_MASK          (0x1U)
 #define CCM_CGPR_PMIC_DELAY_SCALER_SHIFT         (0U)
+/*! PMIC_DELAY_SCALER
+ *  0b0..clock is not divided
+ *  0b1..clock is divided /8
+ */
 #define CCM_CGPR_PMIC_DELAY_SCALER(x)            (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_PMIC_DELAY_SCALER_SHIFT)) & CCM_CGPR_PMIC_DELAY_SCALER_MASK)
 #define CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_MASK     (0x10U)
 #define CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_SHIFT    (4U)
+/*! EFUSE_PROG_SUPPLY_GATE
+ *  0b0..fuse programing supply voltage is gated off to the efuse module
+ *  0b1..allow fuse programing.
+ */
 #define CCM_CGPR_EFUSE_PROG_SUPPLY_GATE(x)       (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_SHIFT)) & CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_MASK)
 #define CCM_CGPR_SYS_MEM_DS_CTRL_MASK            (0xC000U)
 #define CCM_CGPR_SYS_MEM_DS_CTRL_SHIFT           (14U)
+/*! SYS_MEM_DS_CTRL
+ *  0b00..Disable memory DS mode always
+ *  0b01..Enable memory (outside ARM platform) DS mode when system STOP and PLL are disabled
+ *  0b1x..enable memory (outside ARM platform) DS mode when system is in STOP mode
+ */
 #define CCM_CGPR_SYS_MEM_DS_CTRL(x)              (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_SYS_MEM_DS_CTRL_SHIFT)) & CCM_CGPR_SYS_MEM_DS_CTRL_MASK)
 #define CCM_CGPR_FPL_MASK                        (0x10000U)
 #define CCM_CGPR_FPL_SHIFT                       (16U)
+/*! FPL - Fast PLL enable.
+ *  0b0..Engage PLL enable default way.
+ *  0b1..Engage PLL enable 3 CKIL clocks earlier at exiting low power mode (STOP). Should be used only if 24MHz OSC was active in low power mode.
+ */
 #define CCM_CGPR_FPL(x)                          (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_FPL_SHIFT)) & CCM_CGPR_FPL_MASK)
 #define CCM_CGPR_INT_MEM_CLK_LPM_MASK            (0x20000U)
 #define CCM_CGPR_INT_MEM_CLK_LPM_SHIFT           (17U)
+/*! INT_MEM_CLK_LPM
+ *  0b0..Disable the clock to the ARM platform memories when entering Low Power Mode
+ *  0b1..Keep the clocks to the ARM platform memories enabled only if an interrupt is pending when entering Low
+ *       Power Modes (WAIT and STOP without power gating)
+ */
 #define CCM_CGPR_INT_MEM_CLK_LPM(x)              (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_INT_MEM_CLK_LPM_SHIFT)) & CCM_CGPR_INT_MEM_CLK_LPM_MASK)
 /*! @} */
 
@@ -3845,21 +5916,45 @@ typedef struct {
 /*! @{ */
 #define CCM_CMEOR_MOD_EN_OV_GPT_MASK             (0x20U)
 #define CCM_CMEOR_MOD_EN_OV_GPT_SHIFT            (5U)
+/*! MOD_EN_OV_GPT
+ *  0b0..don't override module enable signal
+ *  0b1..override module enable signal
+ */
 #define CCM_CMEOR_MOD_EN_OV_GPT(x)               (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_GPT_SHIFT)) & CCM_CMEOR_MOD_EN_OV_GPT_MASK)
 #define CCM_CMEOR_MOD_EN_OV_PIT_MASK             (0x40U)
 #define CCM_CMEOR_MOD_EN_OV_PIT_SHIFT            (6U)
+/*! MOD_EN_OV_PIT
+ *  0b0..don't override module enable signal
+ *  0b1..override module enable signal
+ */
 #define CCM_CMEOR_MOD_EN_OV_PIT(x)               (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_PIT_SHIFT)) & CCM_CMEOR_MOD_EN_OV_PIT_MASK)
 #define CCM_CMEOR_MOD_EN_USDHC_MASK              (0x80U)
 #define CCM_CMEOR_MOD_EN_USDHC_SHIFT             (7U)
+/*! MOD_EN_USDHC
+ *  0b0..don't override module enable signal
+ *  0b1..override module enable signal
+ */
 #define CCM_CMEOR_MOD_EN_USDHC(x)                (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_USDHC_SHIFT)) & CCM_CMEOR_MOD_EN_USDHC_MASK)
 #define CCM_CMEOR_MOD_EN_OV_TRNG_MASK            (0x200U)
 #define CCM_CMEOR_MOD_EN_OV_TRNG_SHIFT           (9U)
+/*! MOD_EN_OV_TRNG
+ *  0b0..don't override module enable signal
+ *  0b1..override module enable signal
+ */
 #define CCM_CMEOR_MOD_EN_OV_TRNG(x)              (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_TRNG_SHIFT)) & CCM_CMEOR_MOD_EN_OV_TRNG_MASK)
 #define CCM_CMEOR_MOD_EN_OV_CAN2_CPI_MASK        (0x10000000U)
 #define CCM_CMEOR_MOD_EN_OV_CAN2_CPI_SHIFT       (28U)
+/*! MOD_EN_OV_CAN2_CPI
+ *  0b0..don't override module enable signal
+ *  0b1..override module enable signal
+ */
 #define CCM_CMEOR_MOD_EN_OV_CAN2_CPI(x)          (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_CAN2_CPI_SHIFT)) & CCM_CMEOR_MOD_EN_OV_CAN2_CPI_MASK)
 #define CCM_CMEOR_MOD_EN_OV_CAN1_CPI_MASK        (0x40000000U)
 #define CCM_CMEOR_MOD_EN_OV_CAN1_CPI_SHIFT       (30U)
+/*! MOD_EN_OV_CAN1_CPI
+ *  0b0..don't overide module enable signal
+ *  0b1..overide module enable signal
+ */
 #define CCM_CMEOR_MOD_EN_OV_CAN1_CPI(x)          (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_CAN1_CPI_SHIFT)) & CCM_CMEOR_MOD_EN_OV_CAN1_CPI_MASK)
 /*! @} */
 
@@ -3984,6 +6079,12 @@ typedef struct {
 #define CCM_ANALOG_PLL_ARM_ENABLE(x)             (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ARM_ENABLE_MASK)
 #define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK   (0xC000U)
 #define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT  (14U)
+/*! BYPASS_CLK_SRC
+ *  0b00..Select the 24MHz oscillator as source.
+ *  0b01..Select the CLK1_N / CLK1_P as source.
+ *  0b10..Reserved1
+ *  0b11..Reserved2
+ */
 #define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC(x)     (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK)
 #define CCM_ANALOG_PLL_ARM_BYPASS_MASK           (0x10000U)
 #define CCM_ANALOG_PLL_ARM_BYPASS_SHIFT          (16U)
@@ -4009,6 +6110,12 @@ typedef struct {
 #define CCM_ANALOG_PLL_ARM_SET_ENABLE(x)         (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_ENABLE_MASK)
 #define CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_MASK (0xC000U)
 #define CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_SHIFT (14U)
+/*! BYPASS_CLK_SRC
+ *  0b00..Select the 24MHz oscillator as source.
+ *  0b01..Select the CLK1_N / CLK1_P as source.
+ *  0b10..Reserved1
+ *  0b11..Reserved2
+ */
 #define CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_MASK)
 #define CCM_ANALOG_PLL_ARM_SET_BYPASS_MASK       (0x10000U)
 #define CCM_ANALOG_PLL_ARM_SET_BYPASS_SHIFT      (16U)
@@ -4034,6 +6141,12 @@ typedef struct {
 #define CCM_ANALOG_PLL_ARM_CLR_ENABLE(x)         (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_ENABLE_MASK)
 #define CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_MASK (0xC000U)
 #define CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_SHIFT (14U)
+/*! BYPASS_CLK_SRC
+ *  0b00..Select the 24MHz oscillator as source.
+ *  0b01..Select the CLK1_N / CLK1_P as source.
+ *  0b10..Reserved1
+ *  0b11..Reserved2
+ */
 #define CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_MASK)
 #define CCM_ANALOG_PLL_ARM_CLR_BYPASS_MASK       (0x10000U)
 #define CCM_ANALOG_PLL_ARM_CLR_BYPASS_SHIFT      (16U)
@@ -4059,6 +6172,12 @@ typedef struct {
 #define CCM_ANALOG_PLL_ARM_TOG_ENABLE(x)         (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_ENABLE_MASK)
 #define CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_MASK (0xC000U)
 #define CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_SHIFT (14U)
+/*! BYPASS_CLK_SRC
+ *  0b00..Select the 24MHz oscillator as source.
+ *  0b01..Select the CLK1_N / CLK1_P as source.
+ *  0b10..Reserved1
+ *  0b11..Reserved2
+ */
 #define CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_MASK)
 #define CCM_ANALOG_PLL_ARM_TOG_BYPASS_MASK       (0x10000U)
 #define CCM_ANALOG_PLL_ARM_TOG_BYPASS_SHIFT      (16U)
@@ -4078,6 +6197,10 @@ typedef struct {
 #define CCM_ANALOG_PLL_USB1_DIV_SELECT(x)        (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK)
 #define CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK     (0x40U)
 #define CCM_ANALOG_PLL_USB1_EN_USB_CLKS_SHIFT    (6U)
+/*! EN_USB_CLKS
+ *  0b0..PLL outputs for USBPHYn off.
+ *  0b1..PLL outputs for USBPHYn on.
+ */
 #define CCM_ANALOG_PLL_USB1_EN_USB_CLKS(x)       (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK)
 #define CCM_ANALOG_PLL_USB1_POWER_MASK           (0x1000U)
 #define CCM_ANALOG_PLL_USB1_POWER_SHIFT          (12U)
@@ -4087,6 +6210,10 @@ typedef struct {
 #define CCM_ANALOG_PLL_USB1_ENABLE(x)            (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_ENABLE_MASK)
 #define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK  (0xC000U)
 #define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT (14U)
+/*! BYPASS_CLK_SRC
+ *  0b00..Select the 24MHz oscillator as source.
+ *  0b01..Select the CLK1_N / CLK1_P as source.
+ */
 #define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC(x)    (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK)
 #define CCM_ANALOG_PLL_USB1_BYPASS_MASK          (0x10000U)
 #define CCM_ANALOG_PLL_USB1_BYPASS_SHIFT         (16U)
@@ -4103,6 +6230,10 @@ typedef struct {
 #define CCM_ANALOG_PLL_USB1_SET_DIV_SELECT(x)    (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_MASK)
 #define CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_MASK (0x40U)
 #define CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_SHIFT (6U)
+/*! EN_USB_CLKS
+ *  0b0..PLL outputs for USBPHYn off.
+ *  0b1..PLL outputs for USBPHYn on.
+ */
 #define CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_MASK)
 #define CCM_ANALOG_PLL_USB1_SET_POWER_MASK       (0x1000U)
 #define CCM_ANALOG_PLL_USB1_SET_POWER_SHIFT      (12U)
@@ -4112,6 +6243,10 @@ typedef struct {
 #define CCM_ANALOG_PLL_USB1_SET_ENABLE(x)        (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_ENABLE_MASK)
 #define CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_MASK (0xC000U)
 #define CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_SHIFT (14U)
+/*! BYPASS_CLK_SRC
+ *  0b00..Select the 24MHz oscillator as source.
+ *  0b01..Select the CLK1_N / CLK1_P as source.
+ */
 #define CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_MASK)
 #define CCM_ANALOG_PLL_USB1_SET_BYPASS_MASK      (0x10000U)
 #define CCM_ANALOG_PLL_USB1_SET_BYPASS_SHIFT     (16U)
@@ -4128,6 +6263,10 @@ typedef struct {
 #define CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT(x)    (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_MASK)
 #define CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_MASK (0x40U)
 #define CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_SHIFT (6U)
+/*! EN_USB_CLKS
+ *  0b0..PLL outputs for USBPHYn off.
+ *  0b1..PLL outputs for USBPHYn on.
+ */
 #define CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_MASK)
 #define CCM_ANALOG_PLL_USB1_CLR_POWER_MASK       (0x1000U)
 #define CCM_ANALOG_PLL_USB1_CLR_POWER_SHIFT      (12U)
@@ -4137,6 +6276,10 @@ typedef struct {
 #define CCM_ANALOG_PLL_USB1_CLR_ENABLE(x)        (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_ENABLE_MASK)
 #define CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_MASK (0xC000U)
 #define CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_SHIFT (14U)
+/*! BYPASS_CLK_SRC
+ *  0b00..Select the 24MHz oscillator as source.
+ *  0b01..Select the CLK1_N / CLK1_P as source.
+ */
 #define CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_MASK)
 #define CCM_ANALOG_PLL_USB1_CLR_BYPASS_MASK      (0x10000U)
 #define CCM_ANALOG_PLL_USB1_CLR_BYPASS_SHIFT     (16U)
@@ -4153,6 +6296,10 @@ typedef struct {
 #define CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT(x)    (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_MASK)
 #define CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_MASK (0x40U)
 #define CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_SHIFT (6U)
+/*! EN_USB_CLKS
+ *  0b0..PLL outputs for USBPHYn off.
+ *  0b1..PLL outputs for USBPHYn on.
+ */
 #define CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_MASK)
 #define CCM_ANALOG_PLL_USB1_TOG_POWER_MASK       (0x1000U)
 #define CCM_ANALOG_PLL_USB1_TOG_POWER_SHIFT      (12U)
@@ -4162,6 +6309,10 @@ typedef struct {
 #define CCM_ANALOG_PLL_USB1_TOG_ENABLE(x)        (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_ENABLE_MASK)
 #define CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_MASK (0xC000U)
 #define CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_SHIFT (14U)
+/*! BYPASS_CLK_SRC
+ *  0b00..Select the 24MHz oscillator as source.
+ *  0b01..Select the CLK1_N / CLK1_P as source.
+ */
 #define CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_MASK)
 #define CCM_ANALOG_PLL_USB1_TOG_BYPASS_MASK      (0x10000U)
 #define CCM_ANALOG_PLL_USB1_TOG_BYPASS_SHIFT     (16U)
@@ -4187,6 +6338,12 @@ typedef struct {
 #define CCM_ANALOG_PLL_USB2_ENABLE(x)            (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB2_ENABLE_MASK)
 #define CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_MASK  (0xC000U)
 #define CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_SHIFT (14U)
+/*! BYPASS_CLK_SRC
+ *  0b00..Select the 24MHz oscillator as source.
+ *  0b01..Select the CLK1_N / CLK1_P as source.
+ *  0b10..Reserved1
+ *  0b11..Reserved2
+ */
 #define CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC(x)    (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_MASK)
 #define CCM_ANALOG_PLL_USB2_BYPASS_MASK          (0x10000U)
 #define CCM_ANALOG_PLL_USB2_BYPASS_SHIFT         (16U)
@@ -4212,6 +6369,12 @@ typedef struct {
 #define CCM_ANALOG_PLL_USB2_SET_ENABLE(x)        (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_ENABLE_MASK)
 #define CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC_MASK (0xC000U)
 #define CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC_SHIFT (14U)
+/*! BYPASS_CLK_SRC
+ *  0b00..Select the 24MHz oscillator as source.
+ *  0b01..Select the CLK1_N / CLK1_P as source.
+ *  0b10..Reserved1
+ *  0b11..Reserved2
+ */
 #define CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC_MASK)
 #define CCM_ANALOG_PLL_USB2_SET_BYPASS_MASK      (0x10000U)
 #define CCM_ANALOG_PLL_USB2_SET_BYPASS_SHIFT     (16U)
@@ -4237,6 +6400,12 @@ typedef struct {
 #define CCM_ANALOG_PLL_USB2_CLR_ENABLE(x)        (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_ENABLE_MASK)
 #define CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC_MASK (0xC000U)
 #define CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC_SHIFT (14U)
+/*! BYPASS_CLK_SRC
+ *  0b00..Select the 24MHz oscillator as source.
+ *  0b01..Select the CLK1_N / CLK1_P as source.
+ *  0b10..Reserved1
+ *  0b11..Reserved2
+ */
 #define CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC_MASK)
 #define CCM_ANALOG_PLL_USB2_CLR_BYPASS_MASK      (0x10000U)
 #define CCM_ANALOG_PLL_USB2_CLR_BYPASS_SHIFT     (16U)
@@ -4262,6 +6431,12 @@ typedef struct {
 #define CCM_ANALOG_PLL_USB2_TOG_ENABLE(x)        (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_ENABLE_MASK)
 #define CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC_MASK (0xC000U)
 #define CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC_SHIFT (14U)
+/*! BYPASS_CLK_SRC
+ *  0b00..Select the 24MHz oscillator as source.
+ *  0b01..Select the CLK1_N / CLK1_P as source.
+ *  0b10..Reserved1
+ *  0b11..Reserved2
+ */
 #define CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC_MASK)
 #define CCM_ANALOG_PLL_USB2_TOG_BYPASS_MASK      (0x10000U)
 #define CCM_ANALOG_PLL_USB2_TOG_BYPASS_SHIFT     (16U)
@@ -4284,6 +6459,10 @@ typedef struct {
 #define CCM_ANALOG_PLL_SYS_ENABLE(x)             (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_ENABLE_MASK)
 #define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK   (0xC000U)
 #define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT  (14U)
+/*! BYPASS_CLK_SRC
+ *  0b00..Select the 24MHz oscillator as source.
+ *  0b01..Select the CLK1_N / CLK1_P as source.
+ */
 #define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC(x)     (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK)
 #define CCM_ANALOG_PLL_SYS_BYPASS_MASK           (0x10000U)
 #define CCM_ANALOG_PLL_SYS_BYPASS_SHIFT          (16U)
@@ -4309,6 +6488,10 @@ typedef struct {
 #define CCM_ANALOG_PLL_SYS_SET_ENABLE(x)         (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_ENABLE_MASK)
 #define CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_MASK (0xC000U)
 #define CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_SHIFT (14U)
+/*! BYPASS_CLK_SRC
+ *  0b00..Select the 24MHz oscillator as source.
+ *  0b01..Select the CLK1_N / CLK1_P as source.
+ */
 #define CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_MASK)
 #define CCM_ANALOG_PLL_SYS_SET_BYPASS_MASK       (0x10000U)
 #define CCM_ANALOG_PLL_SYS_SET_BYPASS_SHIFT      (16U)
@@ -4334,6 +6517,10 @@ typedef struct {
 #define CCM_ANALOG_PLL_SYS_CLR_ENABLE(x)         (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_ENABLE_MASK)
 #define CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_MASK (0xC000U)
 #define CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_SHIFT (14U)
+/*! BYPASS_CLK_SRC
+ *  0b00..Select the 24MHz oscillator as source.
+ *  0b01..Select the CLK1_N / CLK1_P as source.
+ */
 #define CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_MASK)
 #define CCM_ANALOG_PLL_SYS_CLR_BYPASS_MASK       (0x10000U)
 #define CCM_ANALOG_PLL_SYS_CLR_BYPASS_SHIFT      (16U)
@@ -4359,6 +6546,10 @@ typedef struct {
 #define CCM_ANALOG_PLL_SYS_TOG_ENABLE(x)         (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_ENABLE_MASK)
 #define CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_MASK (0xC000U)
 #define CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_SHIFT (14U)
+/*! BYPASS_CLK_SRC
+ *  0b00..Select the 24MHz oscillator as source.
+ *  0b01..Select the CLK1_N / CLK1_P as source.
+ */
 #define CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_MASK)
 #define CCM_ANALOG_PLL_SYS_TOG_BYPASS_MASK       (0x10000U)
 #define CCM_ANALOG_PLL_SYS_TOG_BYPASS_SHIFT      (16U)
@@ -4378,6 +6569,10 @@ typedef struct {
 #define CCM_ANALOG_PLL_SYS_SS_STEP(x)            (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SS_STEP_SHIFT)) & CCM_ANALOG_PLL_SYS_SS_STEP_MASK)
 #define CCM_ANALOG_PLL_SYS_SS_ENABLE_MASK        (0x8000U)
 #define CCM_ANALOG_PLL_SYS_SS_ENABLE_SHIFT       (15U)
+/*! ENABLE - Enable bit
+ *  0b0..Spread spectrum modulation disabled
+ *  0b1..Soread spectrum modulation enabled
+ */
 #define CCM_ANALOG_PLL_SYS_SS_ENABLE(x)          (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SS_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_SS_ENABLE_MASK)
 #define CCM_ANALOG_PLL_SYS_SS_STOP_MASK          (0xFFFF0000U)
 #define CCM_ANALOG_PLL_SYS_SS_STOP_SHIFT         (16U)
@@ -4411,6 +6606,12 @@ typedef struct {
 #define CCM_ANALOG_PLL_AUDIO_ENABLE(x)           (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_ENABLE_MASK)
 #define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK (0xC000U)
 #define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT (14U)
+/*! BYPASS_CLK_SRC
+ *  0b00..Select the 24MHz oscillator as source.
+ *  0b01..Select the CLK1_N / CLK1_P as source.
+ *  0b10..Reserved1
+ *  0b11..Reserved2
+ */
 #define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK)
 #define CCM_ANALOG_PLL_AUDIO_BYPASS_MASK         (0x10000U)
 #define CCM_ANALOG_PLL_AUDIO_BYPASS_SHIFT        (16U)
@@ -4420,6 +6621,12 @@ typedef struct {
 #define CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN(x)    (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN_MASK)
 #define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_MASK (0x180000U)
 #define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT (19U)
+/*! POST_DIV_SELECT
+ *  0b00..Divide by 4.
+ *  0b01..Divide by 2.
+ *  0b10..Divide by 1.
+ *  0b11..Reserved
+ */
 #define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(x)  (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_MASK)
 #define CCM_ANALOG_PLL_AUDIO_LOCK_MASK           (0x80000000U)
 #define CCM_ANALOG_PLL_AUDIO_LOCK_SHIFT          (31U)
@@ -4439,6 +6646,12 @@ typedef struct {
 #define CCM_ANALOG_PLL_AUDIO_SET_ENABLE(x)       (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_ENABLE_MASK)
 #define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_MASK (0xC000U)
 #define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_SHIFT (14U)
+/*! BYPASS_CLK_SRC
+ *  0b00..Select the 24MHz oscillator as source.
+ *  0b01..Select the CLK1_N / CLK1_P as source.
+ *  0b10..Reserved1
+ *  0b11..Reserved2
+ */
 #define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_MASK)
 #define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_MASK     (0x10000U)
 #define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_SHIFT    (16U)
@@ -4448,6 +6661,12 @@ typedef struct {
 #define CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN_MASK)
 #define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_MASK (0x180000U)
 #define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_SHIFT (19U)
+/*! POST_DIV_SELECT
+ *  0b00..Divide by 4.
+ *  0b01..Divide by 2.
+ *  0b10..Divide by 1.
+ *  0b11..Reserved
+ */
 #define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_MASK)
 #define CCM_ANALOG_PLL_AUDIO_SET_LOCK_MASK       (0x80000000U)
 #define CCM_ANALOG_PLL_AUDIO_SET_LOCK_SHIFT      (31U)
@@ -4467,6 +6686,12 @@ typedef struct {
 #define CCM_ANALOG_PLL_AUDIO_CLR_ENABLE(x)       (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_MASK)
 #define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_MASK (0xC000U)
 #define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_SHIFT (14U)
+/*! BYPASS_CLK_SRC
+ *  0b00..Select the 24MHz oscillator as source.
+ *  0b01..Select the CLK1_N / CLK1_P as source.
+ *  0b10..Reserved1
+ *  0b11..Reserved2
+ */
 #define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_MASK)
 #define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_MASK     (0x10000U)
 #define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_SHIFT    (16U)
@@ -4476,6 +6701,12 @@ typedef struct {
 #define CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN_MASK)
 #define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_MASK (0x180000U)
 #define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_SHIFT (19U)
+/*! POST_DIV_SELECT
+ *  0b00..Divide by 4.
+ *  0b01..Divide by 2.
+ *  0b10..Divide by 1.
+ *  0b11..Reserved
+ */
 #define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_MASK)
 #define CCM_ANALOG_PLL_AUDIO_CLR_LOCK_MASK       (0x80000000U)
 #define CCM_ANALOG_PLL_AUDIO_CLR_LOCK_SHIFT      (31U)
@@ -4495,6 +6726,12 @@ typedef struct {
 #define CCM_ANALOG_PLL_AUDIO_TOG_ENABLE(x)       (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_MASK)
 #define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_MASK (0xC000U)
 #define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_SHIFT (14U)
+/*! BYPASS_CLK_SRC
+ *  0b00..Select the 24MHz oscillator as source.
+ *  0b01..Select the CLK1_N / CLK1_P as source.
+ *  0b10..Reserved1
+ *  0b11..Reserved2
+ */
 #define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_MASK)
 #define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_MASK     (0x10000U)
 #define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_SHIFT    (16U)
@@ -4504,6 +6741,12 @@ typedef struct {
 #define CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN_MASK)
 #define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_MASK (0x180000U)
 #define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_SHIFT (19U)
+/*! POST_DIV_SELECT
+ *  0b00..Divide by 4.
+ *  0b01..Divide by 2.
+ *  0b10..Divide by 1.
+ *  0b11..Reserved
+ */
 #define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_MASK)
 #define CCM_ANALOG_PLL_AUDIO_TOG_LOCK_MASK       (0x80000000U)
 #define CCM_ANALOG_PLL_AUDIO_TOG_LOCK_SHIFT      (31U)
@@ -4537,6 +6780,12 @@ typedef struct {
 #define CCM_ANALOG_PLL_VIDEO_ENABLE(x)           (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_ENABLE_SHIFT)) & CCM_ANALOG_PLL_VIDEO_ENABLE_MASK)
 #define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK (0xC000U)
 #define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT (14U)
+/*! BYPASS_CLK_SRC
+ *  0b00..Select the 24MHz oscillator as source.
+ *  0b01..Select the CLK1_N / CLK1_P as source.
+ *  0b10..Reserved1
+ *  0b11..Reserved2
+ */
 #define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK)
 #define CCM_ANALOG_PLL_VIDEO_BYPASS_MASK         (0x10000U)
 #define CCM_ANALOG_PLL_VIDEO_BYPASS_SHIFT        (16U)
@@ -4546,6 +6795,12 @@ typedef struct {
 #define CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN(x)    (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN_MASK)
 #define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_MASK (0x180000U)
 #define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_SHIFT (19U)
+/*! POST_DIV_SELECT
+ *  0b00..Divide by 4.
+ *  0b01..Divide by 2.
+ *  0b10..Divide by 1.
+ *  0b11..Reserved
+ */
 #define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(x)  (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_MASK)
 #define CCM_ANALOG_PLL_VIDEO_LOCK_MASK           (0x80000000U)
 #define CCM_ANALOG_PLL_VIDEO_LOCK_SHIFT          (31U)
@@ -4565,6 +6820,12 @@ typedef struct {
 #define CCM_ANALOG_PLL_VIDEO_SET_ENABLE(x)       (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_ENABLE_MASK)
 #define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_MASK (0xC000U)
 #define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_SHIFT (14U)
+/*! BYPASS_CLK_SRC
+ *  0b00..Select the 24MHz oscillator as source.
+ *  0b01..Select the CLK1_N / CLK1_P as source.
+ *  0b10..Reserved1
+ *  0b11..Reserved2
+ */
 #define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_MASK)
 #define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_MASK     (0x10000U)
 #define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_SHIFT    (16U)
@@ -4574,6 +6835,12 @@ typedef struct {
 #define CCM_ANALOG_PLL_VIDEO_SET_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_PFD_OFFSET_EN_MASK)
 #define CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT_MASK (0x180000U)
 #define CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT_SHIFT (19U)
+/*! POST_DIV_SELECT
+ *  0b00..Divide by 4.
+ *  0b01..Divide by 2.
+ *  0b10..Divide by 1.
+ *  0b11..Reserved
+ */
 #define CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT_MASK)
 #define CCM_ANALOG_PLL_VIDEO_SET_LOCK_MASK       (0x80000000U)
 #define CCM_ANALOG_PLL_VIDEO_SET_LOCK_SHIFT      (31U)
@@ -4593,6 +6860,12 @@ typedef struct {
 #define CCM_ANALOG_PLL_VIDEO_CLR_ENABLE(x)       (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_MASK)
 #define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_MASK (0xC000U)
 #define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_SHIFT (14U)
+/*! BYPASS_CLK_SRC
+ *  0b00..Select the 24MHz oscillator as source.
+ *  0b01..Select the CLK1_N / CLK1_P as source.
+ *  0b10..Reserved1
+ *  0b11..Reserved2
+ */
 #define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_MASK)
 #define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_MASK     (0x10000U)
 #define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_SHIFT    (16U)
@@ -4602,6 +6875,12 @@ typedef struct {
 #define CCM_ANALOG_PLL_VIDEO_CLR_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_PFD_OFFSET_EN_MASK)
 #define CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT_MASK (0x180000U)
 #define CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT_SHIFT (19U)
+/*! POST_DIV_SELECT
+ *  0b00..Divide by 4.
+ *  0b01..Divide by 2.
+ *  0b10..Divide by 1.
+ *  0b11..Reserved
+ */
 #define CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT_MASK)
 #define CCM_ANALOG_PLL_VIDEO_CLR_LOCK_MASK       (0x80000000U)
 #define CCM_ANALOG_PLL_VIDEO_CLR_LOCK_SHIFT      (31U)
@@ -4621,6 +6900,12 @@ typedef struct {
 #define CCM_ANALOG_PLL_VIDEO_TOG_ENABLE(x)       (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_MASK)
 #define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_MASK (0xC000U)
 #define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_SHIFT (14U)
+/*! BYPASS_CLK_SRC
+ *  0b00..Select the 24MHz oscillator as source.
+ *  0b01..Select the CLK1_N / CLK1_P as source.
+ *  0b10..Reserved1
+ *  0b11..Reserved2
+ */
 #define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_MASK)
 #define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_MASK     (0x10000U)
 #define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_SHIFT    (16U)
@@ -4630,6 +6915,12 @@ typedef struct {
 #define CCM_ANALOG_PLL_VIDEO_TOG_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_PFD_OFFSET_EN_MASK)
 #define CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT_MASK (0x180000U)
 #define CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT_SHIFT (19U)
+/*! POST_DIV_SELECT
+ *  0b00..Divide by 4.
+ *  0b01..Divide by 2.
+ *  0b10..Divide by 1.
+ *  0b11..Reserved
+ */
 #define CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT_MASK)
 #define CCM_ANALOG_PLL_VIDEO_TOG_LOCK_MASK       (0x80000000U)
 #define CCM_ANALOG_PLL_VIDEO_TOG_LOCK_SHIFT      (31U)
@@ -4663,6 +6954,12 @@ typedef struct {
 #define CCM_ANALOG_PLL_ENET_ENABLE(x)            (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ENET_ENABLE_MASK)
 #define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK  (0xC000U)
 #define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT (14U)
+/*! BYPASS_CLK_SRC
+ *  0b00..Select the 24MHz oscillator as source.
+ *  0b01..Select the CLK1_N / CLK1_P as source.
+ *  0b10..Reserved1
+ *  0b11..Reserved2
+ */
 #define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC(x)    (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK)
 #define CCM_ANALOG_PLL_ENET_BYPASS_MASK          (0x10000U)
 #define CCM_ANALOG_PLL_ENET_BYPASS_SHIFT         (16U)
@@ -4691,6 +6988,12 @@ typedef struct {
 #define CCM_ANALOG_PLL_ENET_SET_ENABLE(x)        (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENABLE_MASK)
 #define CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_MASK (0xC000U)
 #define CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_SHIFT (14U)
+/*! BYPASS_CLK_SRC
+ *  0b00..Select the 24MHz oscillator as source.
+ *  0b01..Select the CLK1_N / CLK1_P as source.
+ *  0b10..Reserved1
+ *  0b11..Reserved2
+ */
 #define CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_MASK)
 #define CCM_ANALOG_PLL_ENET_SET_BYPASS_MASK      (0x10000U)
 #define CCM_ANALOG_PLL_ENET_SET_BYPASS_SHIFT     (16U)
@@ -4719,6 +7022,12 @@ typedef struct {
 #define CCM_ANALOG_PLL_ENET_CLR_ENABLE(x)        (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENABLE_MASK)
 #define CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_MASK (0xC000U)
 #define CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_SHIFT (14U)
+/*! BYPASS_CLK_SRC
+ *  0b00..Select the 24MHz oscillator as source.
+ *  0b01..Select the CLK1_N / CLK1_P as source.
+ *  0b10..Reserved1
+ *  0b11..Reserved2
+ */
 #define CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_MASK)
 #define CCM_ANALOG_PLL_ENET_CLR_BYPASS_MASK      (0x10000U)
 #define CCM_ANALOG_PLL_ENET_CLR_BYPASS_SHIFT     (16U)
@@ -4747,6 +7056,12 @@ typedef struct {
 #define CCM_ANALOG_PLL_ENET_TOG_ENABLE(x)        (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENABLE_MASK)
 #define CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_MASK (0xC000U)
 #define CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_SHIFT (14U)
+/*! BYPASS_CLK_SRC
+ *  0b00..Select the 24MHz oscillator as source.
+ *  0b01..Select the CLK1_N / CLK1_P as source.
+ *  0b10..Reserved1
+ *  0b11..Reserved2
+ */
 #define CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_MASK)
 #define CCM_ANALOG_PLL_ENET_TOG_BYPASS_MASK      (0x10000U)
 #define CCM_ANALOG_PLL_ENET_TOG_BYPASS_SHIFT     (16U)
@@ -5089,21 +7404,51 @@ typedef struct {
 #define CCM_ANALOG_MISC0_REFTOP_PWD(x)           (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_PWD_MASK)
 #define CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_MASK (0x8U)
 #define CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_SHIFT (3U)
+/*! REFTOP_SELFBIASOFF
+ *  0b0..Uses coarse bias currents for startup
+ *  0b1..Uses bandgap-based bias currents for best performance.
+ */
 #define CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_MASK)
 #define CCM_ANALOG_MISC0_REFTOP_VBGADJ_MASK      (0x70U)
 #define CCM_ANALOG_MISC0_REFTOP_VBGADJ_SHIFT     (4U)
+/*! REFTOP_VBGADJ
+ *  0b000..Nominal VBG
+ *  0b001..VBG+0.78%
+ *  0b010..VBG+1.56%
+ *  0b011..VBG+2.34%
+ *  0b100..VBG-0.78%
+ *  0b101..VBG-1.56%
+ *  0b110..VBG-2.34%
+ *  0b111..VBG-3.12%
+ */
 #define CCM_ANALOG_MISC0_REFTOP_VBGADJ(x)        (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_VBGADJ_MASK)
 #define CCM_ANALOG_MISC0_REFTOP_VBGUP_MASK       (0x80U)
 #define CCM_ANALOG_MISC0_REFTOP_VBGUP_SHIFT      (7U)
 #define CCM_ANALOG_MISC0_REFTOP_VBGUP(x)         (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_VBGUP_MASK)
 #define CCM_ANALOG_MISC0_STOP_MODE_CONFIG_MASK   (0xC00U)
 #define CCM_ANALOG_MISC0_STOP_MODE_CONFIG_SHIFT  (10U)
+/*! STOP_MODE_CONFIG
+ *  0b00..All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off;
+ *  0b01..Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off;
+ *  0b10..XtalOsc=off, RCOsc=on, Old BG=on, New BG=off.
+ *  0b11..XtalOsc=off, RCOsc=on, Old BG=off, New BG=on.
+ */
 #define CCM_ANALOG_MISC0_STOP_MODE_CONFIG(x)     (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_STOP_MODE_CONFIG_MASK)
 #define CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_MASK   (0x1000U)
 #define CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_SHIFT  (12U)
+/*! DISCON_HIGH_SNVS
+ *  0b0..Turn on the switch
+ *  0b1..Turn off the switch
+ */
 #define CCM_ANALOG_MISC0_DISCON_HIGH_SNVS(x)     (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_MASK)
 #define CCM_ANALOG_MISC0_OSC_I_MASK              (0x6000U)
 #define CCM_ANALOG_MISC0_OSC_I_SHIFT             (13U)
+/*! OSC_I
+ *  0b00..Nominal
+ *  0b01..Decrease current by 12.5%
+ *  0b10..Decrease current by 25.0%
+ *  0b11..Decrease current by 37.5%
+ */
 #define CCM_ANALOG_MISC0_OSC_I(x)                (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_OSC_I_MASK)
 #define CCM_ANALOG_MISC0_OSC_XTALOK_MASK         (0x8000U)
 #define CCM_ANALOG_MISC0_OSC_XTALOK_SHIFT        (15U)
@@ -5113,12 +7458,30 @@ typedef struct {
 #define CCM_ANALOG_MISC0_OSC_XTALOK_EN(x)        (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_OSC_XTALOK_EN_MASK)
 #define CCM_ANALOG_MISC0_CLKGATE_CTRL_MASK       (0x2000000U)
 #define CCM_ANALOG_MISC0_CLKGATE_CTRL_SHIFT      (25U)
+/*! CLKGATE_CTRL
+ *  0b0..Allow the logic to automatically gate the clock when the XTAL is powered down.
+ *  0b1..Prevent the logic from ever gating off the clock.
+ */
 #define CCM_ANALOG_MISC0_CLKGATE_CTRL(x)         (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_CLKGATE_CTRL_MASK)
 #define CCM_ANALOG_MISC0_CLKGATE_DELAY_MASK      (0x1C000000U)
 #define CCM_ANALOG_MISC0_CLKGATE_DELAY_SHIFT     (26U)
+/*! CLKGATE_DELAY
+ *  0b000..0.5ms
+ *  0b001..1.0ms
+ *  0b010..2.0ms
+ *  0b011..3.0ms
+ *  0b100..4.0ms
+ *  0b101..5.0ms
+ *  0b110..6.0ms
+ *  0b111..7.0ms
+ */
 #define CCM_ANALOG_MISC0_CLKGATE_DELAY(x)        (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_CLKGATE_DELAY_MASK)
 #define CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_MASK    (0x20000000U)
 #define CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_SHIFT   (29U)
+/*! RTC_XTAL_SOURCE
+ *  0b0..Internal ring oscillator
+ *  0b1..RTC_XTAL
+ */
 #define CCM_ANALOG_MISC0_RTC_XTAL_SOURCE(x)      (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_MASK)
 #define CCM_ANALOG_MISC0_XTAL_24M_PWD_MASK       (0x40000000U)
 #define CCM_ANALOG_MISC0_XTAL_24M_PWD_SHIFT      (30U)
@@ -5132,21 +7495,51 @@ typedef struct {
 #define CCM_ANALOG_MISC0_SET_REFTOP_PWD(x)       (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_PWD_MASK)
 #define CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_MASK (0x8U)
 #define CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT (3U)
+/*! REFTOP_SELFBIASOFF
+ *  0b0..Uses coarse bias currents for startup
+ *  0b1..Uses bandgap-based bias currents for best performance.
+ */
 #define CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_MASK)
 #define CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_MASK  (0x70U)
 #define CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_SHIFT (4U)
+/*! REFTOP_VBGADJ
+ *  0b000..Nominal VBG
+ *  0b001..VBG+0.78%
+ *  0b010..VBG+1.56%
+ *  0b011..VBG+2.34%
+ *  0b100..VBG-0.78%
+ *  0b101..VBG-1.56%
+ *  0b110..VBG-2.34%
+ *  0b111..VBG-3.12%
+ */
 #define CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ(x)    (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_MASK)
 #define CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_MASK   (0x80U)
 #define CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_SHIFT  (7U)
 #define CCM_ANALOG_MISC0_SET_REFTOP_VBGUP(x)     (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_MASK)
 #define CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_MASK (0xC00U)
 #define CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_SHIFT (10U)
+/*! STOP_MODE_CONFIG
+ *  0b00..All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off;
+ *  0b01..Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off;
+ *  0b10..XtalOsc=off, RCOsc=on, Old BG=on, New BG=off.
+ *  0b11..XtalOsc=off, RCOsc=on, Old BG=off, New BG=on.
+ */
 #define CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_MASK)
 #define CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_MASK (0x1000U)
 #define CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_SHIFT (12U)
+/*! DISCON_HIGH_SNVS
+ *  0b0..Turn on the switch
+ *  0b1..Turn off the switch
+ */
 #define CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_MASK)
 #define CCM_ANALOG_MISC0_SET_OSC_I_MASK          (0x6000U)
 #define CCM_ANALOG_MISC0_SET_OSC_I_SHIFT         (13U)
+/*! OSC_I
+ *  0b00..Nominal
+ *  0b01..Decrease current by 12.5%
+ *  0b10..Decrease current by 25.0%
+ *  0b11..Decrease current by 37.5%
+ */
 #define CCM_ANALOG_MISC0_SET_OSC_I(x)            (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_SET_OSC_I_MASK)
 #define CCM_ANALOG_MISC0_SET_OSC_XTALOK_MASK     (0x8000U)
 #define CCM_ANALOG_MISC0_SET_OSC_XTALOK_SHIFT    (15U)
@@ -5156,12 +7549,30 @@ typedef struct {
 #define CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN(x)    (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_MASK)
 #define CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_MASK   (0x2000000U)
 #define CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_SHIFT  (25U)
+/*! CLKGATE_CTRL
+ *  0b0..Allow the logic to automatically gate the clock when the XTAL is powered down.
+ *  0b1..Prevent the logic from ever gating off the clock.
+ */
 #define CCM_ANALOG_MISC0_SET_CLKGATE_CTRL(x)     (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_MASK)
 #define CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_MASK  (0x1C000000U)
 #define CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_SHIFT (26U)
+/*! CLKGATE_DELAY
+ *  0b000..0.5ms
+ *  0b001..1.0ms
+ *  0b010..2.0ms
+ *  0b011..3.0ms
+ *  0b100..4.0ms
+ *  0b101..5.0ms
+ *  0b110..6.0ms
+ *  0b111..7.0ms
+ */
 #define CCM_ANALOG_MISC0_SET_CLKGATE_DELAY(x)    (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_MASK)
 #define CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_MASK (0x20000000U)
 #define CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_SHIFT (29U)
+/*! RTC_XTAL_SOURCE
+ *  0b0..Internal ring oscillator
+ *  0b1..RTC_XTAL
+ */
 #define CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE(x)  (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_MASK)
 #define CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_MASK   (0x40000000U)
 #define CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_SHIFT  (30U)
@@ -5175,21 +7586,51 @@ typedef struct {
 #define CCM_ANALOG_MISC0_CLR_REFTOP_PWD(x)       (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_PWD_MASK)
 #define CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_MASK (0x8U)
 #define CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT (3U)
+/*! REFTOP_SELFBIASOFF
+ *  0b0..Uses coarse bias currents for startup
+ *  0b1..Uses bandgap-based bias currents for best performance.
+ */
 #define CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_MASK)
 #define CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_MASK  (0x70U)
 #define CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_SHIFT (4U)
+/*! REFTOP_VBGADJ
+ *  0b000..Nominal VBG
+ *  0b001..VBG+0.78%
+ *  0b010..VBG+1.56%
+ *  0b011..VBG+2.34%
+ *  0b100..VBG-0.78%
+ *  0b101..VBG-1.56%
+ *  0b110..VBG-2.34%
+ *  0b111..VBG-3.12%
+ */
 #define CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ(x)    (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_MASK)
 #define CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_MASK   (0x80U)
 #define CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_SHIFT  (7U)
 #define CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP(x)     (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_MASK)
 #define CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_MASK (0xC00U)
 #define CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_SHIFT (10U)
+/*! STOP_MODE_CONFIG
+ *  0b00..All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off;
+ *  0b01..Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off;
+ *  0b10..XtalOsc=off, RCOsc=on, Old BG=on, New BG=off.
+ *  0b11..XtalOsc=off, RCOsc=on, Old BG=off, New BG=on.
+ */
 #define CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_MASK)
 #define CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_MASK (0x1000U)
 #define CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT (12U)
+/*! DISCON_HIGH_SNVS
+ *  0b0..Turn on the switch
+ *  0b1..Turn off the switch
+ */
 #define CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_MASK)
 #define CCM_ANALOG_MISC0_CLR_OSC_I_MASK          (0x6000U)
 #define CCM_ANALOG_MISC0_CLR_OSC_I_SHIFT         (13U)
+/*! OSC_I
+ *  0b00..Nominal
+ *  0b01..Decrease current by 12.5%
+ *  0b10..Decrease current by 25.0%
+ *  0b11..Decrease current by 37.5%
+ */
 #define CCM_ANALOG_MISC0_CLR_OSC_I(x)            (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_CLR_OSC_I_MASK)
 #define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_MASK     (0x8000U)
 #define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_SHIFT    (15U)
@@ -5199,12 +7640,30 @@ typedef struct {
 #define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN(x)    (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_MASK)
 #define CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_MASK   (0x2000000U)
 #define CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_SHIFT  (25U)
+/*! CLKGATE_CTRL
+ *  0b0..Allow the logic to automatically gate the clock when the XTAL is powered down.
+ *  0b1..Prevent the logic from ever gating off the clock.
+ */
 #define CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL(x)     (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_MASK)
 #define CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_MASK  (0x1C000000U)
 #define CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_SHIFT (26U)
+/*! CLKGATE_DELAY
+ *  0b000..0.5ms
+ *  0b001..1.0ms
+ *  0b010..2.0ms
+ *  0b011..3.0ms
+ *  0b100..4.0ms
+ *  0b101..5.0ms
+ *  0b110..6.0ms
+ *  0b111..7.0ms
+ */
 #define CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY(x)    (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_MASK)
 #define CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_MASK (0x20000000U)
 #define CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT (29U)
+/*! RTC_XTAL_SOURCE
+ *  0b0..Internal ring oscillator
+ *  0b1..RTC_XTAL
+ */
 #define CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE(x)  (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_MASK)
 #define CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_MASK   (0x40000000U)
 #define CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_SHIFT  (30U)
@@ -5218,21 +7677,51 @@ typedef struct {
 #define CCM_ANALOG_MISC0_TOG_REFTOP_PWD(x)       (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_PWD_MASK)
 #define CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_MASK (0x8U)
 #define CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT (3U)
+/*! REFTOP_SELFBIASOFF
+ *  0b0..Uses coarse bias currents for startup
+ *  0b1..Uses bandgap-based bias currents for best performance.
+ */
 #define CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_MASK)
 #define CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_MASK  (0x70U)
 #define CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_SHIFT (4U)
+/*! REFTOP_VBGADJ
+ *  0b000..Nominal VBG
+ *  0b001..VBG+0.78%
+ *  0b010..VBG+1.56%
+ *  0b011..VBG+2.34%
+ *  0b100..VBG-0.78%
+ *  0b101..VBG-1.56%
+ *  0b110..VBG-2.34%
+ *  0b111..VBG-3.12%
+ */
 #define CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ(x)    (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_MASK)
 #define CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_MASK   (0x80U)
 #define CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_SHIFT  (7U)
 #define CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP(x)     (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_MASK)
 #define CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_MASK (0xC00U)
 #define CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_SHIFT (10U)
+/*! STOP_MODE_CONFIG
+ *  0b00..All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off;
+ *  0b01..Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off;
+ *  0b10..XtalOsc=off, RCOsc=on, Old BG=on, New BG=off.
+ *  0b11..XtalOsc=off, RCOsc=on, Old BG=off, New BG=on.
+ */
 #define CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_MASK)
 #define CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_MASK (0x1000U)
 #define CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT (12U)
+/*! DISCON_HIGH_SNVS
+ *  0b0..Turn on the switch
+ *  0b1..Turn off the switch
+ */
 #define CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_MASK)
 #define CCM_ANALOG_MISC0_TOG_OSC_I_MASK          (0x6000U)
 #define CCM_ANALOG_MISC0_TOG_OSC_I_SHIFT         (13U)
+/*! OSC_I
+ *  0b00..Nominal
+ *  0b01..Decrease current by 12.5%
+ *  0b10..Decrease current by 25.0%
+ *  0b11..Decrease current by 37.5%
+ */
 #define CCM_ANALOG_MISC0_TOG_OSC_I(x)            (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_TOG_OSC_I_MASK)
 #define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_MASK     (0x8000U)
 #define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_SHIFT    (15U)
@@ -5242,12 +7731,30 @@ typedef struct {
 #define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN(x)    (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_MASK)
 #define CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_MASK   (0x2000000U)
 #define CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_SHIFT  (25U)
+/*! CLKGATE_CTRL
+ *  0b0..Allow the logic to automatically gate the clock when the XTAL is powered down.
+ *  0b1..Prevent the logic from ever gating off the clock.
+ */
 #define CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL(x)     (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_MASK)
 #define CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_MASK  (0x1C000000U)
 #define CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_SHIFT (26U)
+/*! CLKGATE_DELAY
+ *  0b000..0.5ms
+ *  0b001..1.0ms
+ *  0b010..2.0ms
+ *  0b011..3.0ms
+ *  0b100..4.0ms
+ *  0b101..5.0ms
+ *  0b110..6.0ms
+ *  0b111..7.0ms
+ */
 #define CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY(x)    (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_MASK)
 #define CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_MASK (0x20000000U)
 #define CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT (29U)
+/*! RTC_XTAL_SOURCE
+ *  0b0..Internal ring oscillator
+ *  0b1..RTC_XTAL
+ */
 #define CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE(x)  (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_MASK)
 #define CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_MASK   (0x40000000U)
 #define CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_SHIFT  (30U)
@@ -5258,6 +7765,24 @@ typedef struct {
 /*! @{ */
 #define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK      (0x1FU)
 #define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT     (0U)
+/*! LVDS1_CLK_SEL
+ *  0b00000..Arm PLL
+ *  0b00001..System PLL
+ *  0b00010..ref_pfd4_clk == pll2_pfd0_clk
+ *  0b00011..ref_pfd5_clk == pll2_pfd1_clk
+ *  0b00100..ref_pfd6_clk == pll2_pfd2_clk
+ *  0b00101..ref_pfd7_clk == pll2_pfd3_clk
+ *  0b00110..Audio PLL
+ *  0b00111..Video PLL
+ *  0b01001..ethernet ref clock (ENET_PLL)
+ *  0b01100..USB1 PLL clock
+ *  0b01101..USB2 PLL clock
+ *  0b01110..ref_pfd0_clk == pll3_pfd0_clk
+ *  0b01111..ref_pfd1_clk == pll3_pfd1_clk
+ *  0b10000..ref_pfd2_clk == pll3_pfd2_clk
+ *  0b10001..ref_pfd3_clk == pll3_pfd3_clk
+ *  0b10010..xtal (24M)
+ */
 #define CCM_ANALOG_MISC1_LVDS1_CLK_SEL(x)        (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)
 #define CCM_ANALOG_MISC1_LVDSCLK1_OBEN_MASK      (0x400U)
 #define CCM_ANALOG_MISC1_LVDSCLK1_OBEN_SHIFT     (10U)
@@ -5292,6 +7817,24 @@ typedef struct {
 /*! @{ */
 #define CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_MASK  (0x1FU)
 #define CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_SHIFT (0U)
+/*! LVDS1_CLK_SEL
+ *  0b00000..Arm PLL
+ *  0b00001..System PLL
+ *  0b00010..ref_pfd4_clk == pll2_pfd0_clk
+ *  0b00011..ref_pfd5_clk == pll2_pfd1_clk
+ *  0b00100..ref_pfd6_clk == pll2_pfd2_clk
+ *  0b00101..ref_pfd7_clk == pll2_pfd3_clk
+ *  0b00110..Audio PLL
+ *  0b00111..Video PLL
+ *  0b01001..ethernet ref clock (ENET_PLL)
+ *  0b01100..USB1 PLL clock
+ *  0b01101..USB2 PLL clock
+ *  0b01110..ref_pfd0_clk == pll3_pfd0_clk
+ *  0b01111..ref_pfd1_clk == pll3_pfd1_clk
+ *  0b10000..ref_pfd2_clk == pll3_pfd2_clk
+ *  0b10001..ref_pfd3_clk == pll3_pfd3_clk
+ *  0b10010..xtal (24M)
+ */
 #define CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL(x)    (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_MASK)
 #define CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN_MASK  (0x400U)
 #define CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN_SHIFT (10U)
@@ -5326,6 +7869,24 @@ typedef struct {
 /*! @{ */
 #define CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_MASK  (0x1FU)
 #define CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_SHIFT (0U)
+/*! LVDS1_CLK_SEL
+ *  0b00000..Arm PLL
+ *  0b00001..System PLL
+ *  0b00010..ref_pfd4_clk == pll2_pfd0_clk
+ *  0b00011..ref_pfd5_clk == pll2_pfd1_clk
+ *  0b00100..ref_pfd6_clk == pll2_pfd2_clk
+ *  0b00101..ref_pfd7_clk == pll2_pfd3_clk
+ *  0b00110..Audio PLL
+ *  0b00111..Video PLL
+ *  0b01001..ethernet ref clock (ENET_PLL)
+ *  0b01100..USB1 PLL clock
+ *  0b01101..USB2 PLL clock
+ *  0b01110..ref_pfd0_clk == pll3_pfd0_clk
+ *  0b01111..ref_pfd1_clk == pll3_pfd1_clk
+ *  0b10000..ref_pfd2_clk == pll3_pfd2_clk
+ *  0b10001..ref_pfd3_clk == pll3_pfd3_clk
+ *  0b10010..xtal (24M)
+ */
 #define CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL(x)    (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_MASK)
 #define CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN_MASK  (0x400U)
 #define CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN_SHIFT (10U)
@@ -5360,6 +7921,24 @@ typedef struct {
 /*! @{ */
 #define CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_MASK  (0x1FU)
 #define CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_SHIFT (0U)
+/*! LVDS1_CLK_SEL
+ *  0b00000..Arm PLL
+ *  0b00001..System PLL
+ *  0b00010..ref_pfd4_clk == pll2_pfd0_clk
+ *  0b00011..ref_pfd5_clk == pll2_pfd1_clk
+ *  0b00100..ref_pfd6_clk == pll2_pfd2_clk
+ *  0b00101..ref_pfd7_clk == pll2_pfd3_clk
+ *  0b00110..Audio PLL
+ *  0b00111..Video PLL
+ *  0b01001..ethernet ref clock (ENET_PLL)
+ *  0b01100..USB1 PLL clock
+ *  0b01101..USB2 PLL clock
+ *  0b01110..ref_pfd0_clk == pll3_pfd0_clk
+ *  0b01111..ref_pfd1_clk == pll3_pfd1_clk
+ *  0b10000..ref_pfd2_clk == pll3_pfd2_clk
+ *  0b10001..ref_pfd3_clk == pll3_pfd3_clk
+ *  0b10010..xtal (24M)
+ */
 #define CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL(x)    (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_MASK)
 #define CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN_MASK  (0x400U)
 #define CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN_SHIFT (10U)
@@ -5394,9 +7973,16 @@ typedef struct {
 /*! @{ */
 #define CCM_ANALOG_MISC2_REG0_BO_OFFSET_MASK     (0x7U)
 #define CCM_ANALOG_MISC2_REG0_BO_OFFSET_SHIFT    (0U)
+/*! REG0_BO_OFFSET
+ *  0b100..Brownout offset = 0.100V
+ *  0b111..Brownout offset = 0.175V
+ */
 #define CCM_ANALOG_MISC2_REG0_BO_OFFSET(x)       (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_REG0_BO_OFFSET_MASK)
 #define CCM_ANALOG_MISC2_REG0_BO_STATUS_MASK     (0x8U)
 #define CCM_ANALOG_MISC2_REG0_BO_STATUS_SHIFT    (3U)
+/*! REG0_BO_STATUS
+ *  0b1..Brownout, supply is below target minus brownout offset.
+ */
 #define CCM_ANALOG_MISC2_REG0_BO_STATUS(x)       (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_REG0_BO_STATUS_MASK)
 #define CCM_ANALOG_MISC2_REG0_ENABLE_BO_MASK     (0x20U)
 #define CCM_ANALOG_MISC2_REG0_ENABLE_BO_SHIFT    (5U)
@@ -5406,12 +7992,23 @@ typedef struct {
 #define CCM_ANALOG_MISC2_REG0_OK(x)              (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_REG0_OK_MASK)
 #define CCM_ANALOG_MISC2_PLL3_disable_MASK       (0x80U)
 #define CCM_ANALOG_MISC2_PLL3_disable_SHIFT      (7U)
+/*! PLL3_disable
+ *  0b0..PLL3 is being used by peripherals and is enabled when SoC is not in any low power mode
+ *  0b1..PLL3 can be disabled when the SoC is not in any low power mode
+ */
 #define CCM_ANALOG_MISC2_PLL3_disable(x)         (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_PLL3_disable_SHIFT)) & CCM_ANALOG_MISC2_PLL3_disable_MASK)
 #define CCM_ANALOG_MISC2_REG1_BO_OFFSET_MASK     (0x700U)
 #define CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT    (8U)
+/*! REG1_BO_OFFSET
+ *  0b100..Brownout offset = 0.100V
+ *  0b111..Brownout offset = 0.175V
+ */
 #define CCM_ANALOG_MISC2_REG1_BO_OFFSET(x)       (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_REG1_BO_OFFSET_MASK)
 #define CCM_ANALOG_MISC2_REG1_BO_STATUS_MASK     (0x800U)
 #define CCM_ANALOG_MISC2_REG1_BO_STATUS_SHIFT    (11U)
+/*! REG1_BO_STATUS
+ *  0b1..Brownout, supply is below target minus brownout offset.
+ */
 #define CCM_ANALOG_MISC2_REG1_BO_STATUS(x)       (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_REG1_BO_STATUS_MASK)
 #define CCM_ANALOG_MISC2_REG1_ENABLE_BO_MASK     (0x2000U)
 #define CCM_ANALOG_MISC2_REG1_ENABLE_BO_SHIFT    (13U)
@@ -5421,9 +8018,17 @@ typedef struct {
 #define CCM_ANALOG_MISC2_REG1_OK(x)              (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_REG1_OK_MASK)
 #define CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK      (0x8000U)
 #define CCM_ANALOG_MISC2_AUDIO_DIV_LSB_SHIFT     (15U)
+/*! AUDIO_DIV_LSB
+ *  0b0..divide by 1 (Default)
+ *  0b1..divide by 2
+ */
 #define CCM_ANALOG_MISC2_AUDIO_DIV_LSB(x)        (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK)
 #define CCM_ANALOG_MISC2_REG2_BO_OFFSET_MASK     (0x70000U)
 #define CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT    (16U)
+/*! REG2_BO_OFFSET
+ *  0b100..Brownout offset = 0.100V
+ *  0b111..Brownout offset = 0.175V
+ */
 #define CCM_ANALOG_MISC2_REG2_BO_OFFSET(x)       (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_REG2_BO_OFFSET_MASK)
 #define CCM_ANALOG_MISC2_REG2_BO_STATUS_MASK     (0x80000U)
 #define CCM_ANALOG_MISC2_REG2_BO_STATUS_SHIFT    (19U)
@@ -5436,18 +8041,46 @@ typedef struct {
 #define CCM_ANALOG_MISC2_REG2_OK(x)              (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_REG2_OK_MASK)
 #define CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK      (0x800000U)
 #define CCM_ANALOG_MISC2_AUDIO_DIV_MSB_SHIFT     (23U)
+/*! AUDIO_DIV_MSB
+ *  0b0..divide by 1 (Default)
+ *  0b1..divide by 2
+ */
 #define CCM_ANALOG_MISC2_AUDIO_DIV_MSB(x)        (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK)
 #define CCM_ANALOG_MISC2_REG0_STEP_TIME_MASK     (0x3000000U)
 #define CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT    (24U)
+/*! REG0_STEP_TIME
+ *  0b00..64
+ *  0b01..128
+ *  0b10..256
+ *  0b11..512
+ */
 #define CCM_ANALOG_MISC2_REG0_STEP_TIME(x)       (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_REG0_STEP_TIME_MASK)
 #define CCM_ANALOG_MISC2_REG1_STEP_TIME_MASK     (0xC000000U)
 #define CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT    (26U)
+/*! REG1_STEP_TIME
+ *  0b00..64
+ *  0b01..128
+ *  0b10..256
+ *  0b11..512
+ */
 #define CCM_ANALOG_MISC2_REG1_STEP_TIME(x)       (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_REG1_STEP_TIME_MASK)
 #define CCM_ANALOG_MISC2_REG2_STEP_TIME_MASK     (0x30000000U)
 #define CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT    (28U)
+/*! REG2_STEP_TIME
+ *  0b00..64
+ *  0b01..128
+ *  0b10..256
+ *  0b11..512
+ */
 #define CCM_ANALOG_MISC2_REG2_STEP_TIME(x)       (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_REG2_STEP_TIME_MASK)
 #define CCM_ANALOG_MISC2_VIDEO_DIV_MASK          (0xC0000000U)
 #define CCM_ANALOG_MISC2_VIDEO_DIV_SHIFT         (30U)
+/*! VIDEO_DIV
+ *  0b00..divide by 1 (Default)
+ *  0b01..divide by 2
+ *  0b10..divide by 1
+ *  0b11..divide by 4
+ */
 #define CCM_ANALOG_MISC2_VIDEO_DIV(x)            (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_VIDEO_DIV_MASK)
 /*! @} */
 
@@ -5455,9 +8088,16 @@ typedef struct {
 /*! @{ */
 #define CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_MASK (0x7U)
 #define CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_SHIFT (0U)
+/*! REG0_BO_OFFSET
+ *  0b100..Brownout offset = 0.100V
+ *  0b111..Brownout offset = 0.175V
+ */
 #define CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_MASK)
 #define CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_MASK (0x8U)
 #define CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_SHIFT (3U)
+/*! REG0_BO_STATUS
+ *  0b1..Brownout, supply is below target minus brownout offset.
+ */
 #define CCM_ANALOG_MISC2_SET_REG0_BO_STATUS(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_MASK)
 #define CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_MASK (0x20U)
 #define CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_SHIFT (5U)
@@ -5467,12 +8107,23 @@ typedef struct {
 #define CCM_ANALOG_MISC2_SET_REG0_OK(x)          (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_OK_MASK)
 #define CCM_ANALOG_MISC2_SET_PLL3_disable_MASK   (0x80U)
 #define CCM_ANALOG_MISC2_SET_PLL3_disable_SHIFT  (7U)
+/*! PLL3_disable
+ *  0b0..PLL3 is being used by peripherals and is enabled when SoC is not in any low power mode
+ *  0b1..PLL3 can be disabled when the SoC is not in any low power mode
+ */
 #define CCM_ANALOG_MISC2_SET_PLL3_disable(x)     (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_PLL3_disable_SHIFT)) & CCM_ANALOG_MISC2_SET_PLL3_disable_MASK)
 #define CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_MASK (0x700U)
 #define CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_SHIFT (8U)
+/*! REG1_BO_OFFSET
+ *  0b100..Brownout offset = 0.100V
+ *  0b111..Brownout offset = 0.175V
+ */
 #define CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_MASK)
 #define CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_MASK (0x800U)
 #define CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_SHIFT (11U)
+/*! REG1_BO_STATUS
+ *  0b1..Brownout, supply is below target minus brownout offset.
+ */
 #define CCM_ANALOG_MISC2_SET_REG1_BO_STATUS(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_MASK)
 #define CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_MASK (0x2000U)
 #define CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_SHIFT (13U)
@@ -5482,9 +8133,17 @@ typedef struct {
 #define CCM_ANALOG_MISC2_SET_REG1_OK(x)          (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_OK_MASK)
 #define CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_MASK  (0x8000U)
 #define CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_SHIFT (15U)
+/*! AUDIO_DIV_LSB
+ *  0b0..divide by 1 (Default)
+ *  0b1..divide by 2
+ */
 #define CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB(x)    (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_MASK)
 #define CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_MASK (0x70000U)
 #define CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_SHIFT (16U)
+/*! REG2_BO_OFFSET
+ *  0b100..Brownout offset = 0.100V
+ *  0b111..Brownout offset = 0.175V
+ */
 #define CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_MASK)
 #define CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_MASK (0x80000U)
 #define CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_SHIFT (19U)
@@ -5497,18 +8156,46 @@ typedef struct {
 #define CCM_ANALOG_MISC2_SET_REG2_OK(x)          (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_OK_MASK)
 #define CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_MASK  (0x800000U)
 #define CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_SHIFT (23U)
+/*! AUDIO_DIV_MSB
+ *  0b0..divide by 1 (Default)
+ *  0b1..divide by 2
+ */
 #define CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB(x)    (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_MASK)
 #define CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_MASK (0x3000000U)
 #define CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_SHIFT (24U)
+/*! REG0_STEP_TIME
+ *  0b00..64
+ *  0b01..128
+ *  0b10..256
+ *  0b11..512
+ */
 #define CCM_ANALOG_MISC2_SET_REG0_STEP_TIME(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_MASK)
 #define CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_MASK (0xC000000U)
 #define CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_SHIFT (26U)
+/*! REG1_STEP_TIME
+ *  0b00..64
+ *  0b01..128
+ *  0b10..256
+ *  0b11..512
+ */
 #define CCM_ANALOG_MISC2_SET_REG1_STEP_TIME(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_MASK)
 #define CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_MASK (0x30000000U)
 #define CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_SHIFT (28U)
+/*! REG2_STEP_TIME
+ *  0b00..64
+ *  0b01..128
+ *  0b10..256
+ *  0b11..512
+ */
 #define CCM_ANALOG_MISC2_SET_REG2_STEP_TIME(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_MASK)
 #define CCM_ANALOG_MISC2_SET_VIDEO_DIV_MASK      (0xC0000000U)
 #define CCM_ANALOG_MISC2_SET_VIDEO_DIV_SHIFT     (30U)
+/*! VIDEO_DIV
+ *  0b00..divide by 1 (Default)
+ *  0b01..divide by 2
+ *  0b10..divide by 1
+ *  0b11..divide by 4
+ */
 #define CCM_ANALOG_MISC2_SET_VIDEO_DIV(x)        (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_SET_VIDEO_DIV_MASK)
 /*! @} */
 
@@ -5516,9 +8203,16 @@ typedef struct {
 /*! @{ */
 #define CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_MASK (0x7U)
 #define CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_SHIFT (0U)
+/*! REG0_BO_OFFSET
+ *  0b100..Brownout offset = 0.100V
+ *  0b111..Brownout offset = 0.175V
+ */
 #define CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_MASK)
 #define CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_MASK (0x8U)
 #define CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_SHIFT (3U)
+/*! REG0_BO_STATUS
+ *  0b1..Brownout, supply is below target minus brownout offset.
+ */
 #define CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_MASK)
 #define CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_MASK (0x20U)
 #define CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_SHIFT (5U)
@@ -5528,12 +8222,23 @@ typedef struct {
 #define CCM_ANALOG_MISC2_CLR_REG0_OK(x)          (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_OK_MASK)
 #define CCM_ANALOG_MISC2_CLR_PLL3_disable_MASK   (0x80U)
 #define CCM_ANALOG_MISC2_CLR_PLL3_disable_SHIFT  (7U)
+/*! PLL3_disable
+ *  0b0..PLL3 is being used by peripherals and is enabled when SoC is not in any low power mode
+ *  0b1..PLL3 can be disabled when the SoC is not in any low power mode
+ */
 #define CCM_ANALOG_MISC2_CLR_PLL3_disable(x)     (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_PLL3_disable_SHIFT)) & CCM_ANALOG_MISC2_CLR_PLL3_disable_MASK)
 #define CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_MASK (0x700U)
 #define CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_SHIFT (8U)
+/*! REG1_BO_OFFSET
+ *  0b100..Brownout offset = 0.100V
+ *  0b111..Brownout offset = 0.175V
+ */
 #define CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_MASK)
 #define CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_MASK (0x800U)
 #define CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_SHIFT (11U)
+/*! REG1_BO_STATUS
+ *  0b1..Brownout, supply is below target minus brownout offset.
+ */
 #define CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_MASK)
 #define CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_MASK (0x2000U)
 #define CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_SHIFT (13U)
@@ -5543,9 +8248,17 @@ typedef struct {
 #define CCM_ANALOG_MISC2_CLR_REG1_OK(x)          (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_OK_MASK)
 #define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_MASK  (0x8000U)
 #define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_SHIFT (15U)
+/*! AUDIO_DIV_LSB
+ *  0b0..divide by 1 (Default)
+ *  0b1..divide by 2
+ */
 #define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB(x)    (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_MASK)
 #define CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_MASK (0x70000U)
 #define CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_SHIFT (16U)
+/*! REG2_BO_OFFSET
+ *  0b100..Brownout offset = 0.100V
+ *  0b111..Brownout offset = 0.175V
+ */
 #define CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_MASK)
 #define CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_MASK (0x80000U)
 #define CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_SHIFT (19U)
@@ -5558,18 +8271,46 @@ typedef struct {
 #define CCM_ANALOG_MISC2_CLR_REG2_OK(x)          (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_OK_MASK)
 #define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_MASK  (0x800000U)
 #define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_SHIFT (23U)
+/*! AUDIO_DIV_MSB
+ *  0b0..divide by 1 (Default)
+ *  0b1..divide by 2
+ */
 #define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB(x)    (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_MASK)
 #define CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_MASK (0x3000000U)
 #define CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_SHIFT (24U)
+/*! REG0_STEP_TIME
+ *  0b00..64
+ *  0b01..128
+ *  0b10..256
+ *  0b11..512
+ */
 #define CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_MASK)
 #define CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_MASK (0xC000000U)
 #define CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_SHIFT (26U)
+/*! REG1_STEP_TIME
+ *  0b00..64
+ *  0b01..128
+ *  0b10..256
+ *  0b11..512
+ */
 #define CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_MASK)
 #define CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_MASK (0x30000000U)
 #define CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_SHIFT (28U)
+/*! REG2_STEP_TIME
+ *  0b00..64
+ *  0b01..128
+ *  0b10..256
+ *  0b11..512
+ */
 #define CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_MASK)
 #define CCM_ANALOG_MISC2_CLR_VIDEO_DIV_MASK      (0xC0000000U)
 #define CCM_ANALOG_MISC2_CLR_VIDEO_DIV_SHIFT     (30U)
+/*! VIDEO_DIV
+ *  0b00..divide by 1 (Default)
+ *  0b01..divide by 2
+ *  0b10..divide by 1
+ *  0b11..divide by 4
+ */
 #define CCM_ANALOG_MISC2_CLR_VIDEO_DIV(x)        (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_CLR_VIDEO_DIV_MASK)
 /*! @} */
 
@@ -5577,9 +8318,16 @@ typedef struct {
 /*! @{ */
 #define CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_MASK (0x7U)
 #define CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_SHIFT (0U)
+/*! REG0_BO_OFFSET
+ *  0b100..Brownout offset = 0.100V
+ *  0b111..Brownout offset = 0.175V
+ */
 #define CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_MASK)
 #define CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_MASK (0x8U)
 #define CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_SHIFT (3U)
+/*! REG0_BO_STATUS
+ *  0b1..Brownout, supply is below target minus brownout offset.
+ */
 #define CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_MASK)
 #define CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_MASK (0x20U)
 #define CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_SHIFT (5U)
@@ -5589,12 +8337,23 @@ typedef struct {
 #define CCM_ANALOG_MISC2_TOG_REG0_OK(x)          (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_OK_MASK)
 #define CCM_ANALOG_MISC2_TOG_PLL3_disable_MASK   (0x80U)
 #define CCM_ANALOG_MISC2_TOG_PLL3_disable_SHIFT  (7U)
+/*! PLL3_disable
+ *  0b0..PLL3 is being used by peripherals and is enabled when SoC is not in any low power mode
+ *  0b1..PLL3 can be disabled when the SoC is not in any low power mode
+ */
 #define CCM_ANALOG_MISC2_TOG_PLL3_disable(x)     (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_PLL3_disable_SHIFT)) & CCM_ANALOG_MISC2_TOG_PLL3_disable_MASK)
 #define CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_MASK (0x700U)
 #define CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_SHIFT (8U)
+/*! REG1_BO_OFFSET
+ *  0b100..Brownout offset = 0.100V
+ *  0b111..Brownout offset = 0.175V
+ */
 #define CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_MASK)
 #define CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_MASK (0x800U)
 #define CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_SHIFT (11U)
+/*! REG1_BO_STATUS
+ *  0b1..Brownout, supply is below target minus brownout offset.
+ */
 #define CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_MASK)
 #define CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_MASK (0x2000U)
 #define CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_SHIFT (13U)
@@ -5604,9 +8363,17 @@ typedef struct {
 #define CCM_ANALOG_MISC2_TOG_REG1_OK(x)          (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_OK_MASK)
 #define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_MASK  (0x8000U)
 #define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_SHIFT (15U)
+/*! AUDIO_DIV_LSB
+ *  0b0..divide by 1 (Default)
+ *  0b1..divide by 2
+ */
 #define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB(x)    (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_MASK)
 #define CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_MASK (0x70000U)
 #define CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_SHIFT (16U)
+/*! REG2_BO_OFFSET
+ *  0b100..Brownout offset = 0.100V
+ *  0b111..Brownout offset = 0.175V
+ */
 #define CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_MASK)
 #define CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_MASK (0x80000U)
 #define CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_SHIFT (19U)
@@ -5619,18 +8386,46 @@ typedef struct {
 #define CCM_ANALOG_MISC2_TOG_REG2_OK(x)          (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_OK_MASK)
 #define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_MASK  (0x800000U)
 #define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_SHIFT (23U)
+/*! AUDIO_DIV_MSB
+ *  0b0..divide by 1 (Default)
+ *  0b1..divide by 2
+ */
 #define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB(x)    (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_MASK)
 #define CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_MASK (0x3000000U)
 #define CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_SHIFT (24U)
+/*! REG0_STEP_TIME
+ *  0b00..64
+ *  0b01..128
+ *  0b10..256
+ *  0b11..512
+ */
 #define CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_MASK)
 #define CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_MASK (0xC000000U)
 #define CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_SHIFT (26U)
+/*! REG1_STEP_TIME
+ *  0b00..64
+ *  0b01..128
+ *  0b10..256
+ *  0b11..512
+ */
 #define CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_MASK)
 #define CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_MASK (0x30000000U)
 #define CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_SHIFT (28U)
+/*! REG2_STEP_TIME
+ *  0b00..64
+ *  0b01..128
+ *  0b10..256
+ *  0b11..512
+ */
 #define CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME(x)   (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_MASK)
 #define CCM_ANALOG_MISC2_TOG_VIDEO_DIV_MASK      (0xC0000000U)
 #define CCM_ANALOG_MISC2_TOG_VIDEO_DIV_SHIFT     (30U)
+/*! VIDEO_DIV
+ *  0b00..divide by 1 (Default)
+ *  0b01..divide by 2
+ *  0b10..divide by 1
+ *  0b11..divide by 4
+ */
 #define CCM_ANALOG_MISC2_TOG_VIDEO_DIV(x)        (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_TOG_VIDEO_DIV_MASK)
 /*! @} */
 
@@ -5687,9 +8482,25 @@ typedef struct {
 /*! @{ */
 #define CMP_CR0_HYSTCTR_MASK                     (0x3U)
 #define CMP_CR0_HYSTCTR_SHIFT                    (0U)
+/*! HYSTCTR - Comparator hard block hysteresis control
+ *  0b00..Level 0
+ *  0b01..Level 1
+ *  0b10..Level 2
+ *  0b11..Level 3
+ */
 #define CMP_CR0_HYSTCTR(x)                       (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK)
 #define CMP_CR0_FILTER_CNT_MASK                  (0x70U)
 #define CMP_CR0_FILTER_CNT_SHIFT                 (4U)
+/*! FILTER_CNT - Filter Sample Count
+ *  0b000..Filter is disabled. If SE = 1, then COUT is a logic 0. This is not a legal state, and is not recommended. If SE = 0, COUT = COUTA.
+ *  0b001..One sample must agree. The comparator output is simply sampled.
+ *  0b010..2 consecutive samples must agree.
+ *  0b011..3 consecutive samples must agree.
+ *  0b100..4 consecutive samples must agree.
+ *  0b101..5 consecutive samples must agree.
+ *  0b110..6 consecutive samples must agree.
+ *  0b111..7 consecutive samples must agree.
+ */
 #define CMP_CR0_FILTER_CNT(x)                    (((uint8_t)(((uint8_t)(x)) << CMP_CR0_FILTER_CNT_SHIFT)) & CMP_CR0_FILTER_CNT_MASK)
 /*! @} */
 
@@ -5697,24 +8508,54 @@ typedef struct {
 /*! @{ */
 #define CMP_CR1_EN_MASK                          (0x1U)
 #define CMP_CR1_EN_SHIFT                         (0U)
+/*! EN - Comparator Module Enable
+ *  0b0..Analog Comparator is disabled.
+ *  0b1..Analog Comparator is enabled.
+ */
 #define CMP_CR1_EN(x)                            (((uint8_t)(((uint8_t)(x)) << CMP_CR1_EN_SHIFT)) & CMP_CR1_EN_MASK)
 #define CMP_CR1_OPE_MASK                         (0x2U)
 #define CMP_CR1_OPE_SHIFT                        (1U)
+/*! OPE - Comparator Output Pin Enable
+ *  0b0..CMPO is not available on the associated CMPO output pin. If the comparator does not own the pin, this field has no effect.
+ *  0b1..CMPO is available on the associated CMPO output pin. The comparator output (CMPO) is driven out on the
+ *       associated CMPO output pin if the comparator owns the pin. If the comparator does not own the field, this
+ *       bit has no effect.
+ */
 #define CMP_CR1_OPE(x)                           (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK)
 #define CMP_CR1_COS_MASK                         (0x4U)
 #define CMP_CR1_COS_SHIFT                        (2U)
+/*! COS - Comparator Output Select
+ *  0b0..Set the filtered comparator output (CMPO) to equal COUT.
+ *  0b1..Set the unfiltered comparator output (CMPO) to equal COUTA.
+ */
 #define CMP_CR1_COS(x)                           (((uint8_t)(((uint8_t)(x)) << CMP_CR1_COS_SHIFT)) & CMP_CR1_COS_MASK)
 #define CMP_CR1_INV_MASK                         (0x8U)
 #define CMP_CR1_INV_SHIFT                        (3U)
+/*! INV - Comparator INVERT
+ *  0b0..Does not invert the comparator output.
+ *  0b1..Inverts the comparator output.
+ */
 #define CMP_CR1_INV(x)                           (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK)
 #define CMP_CR1_PMODE_MASK                       (0x10U)
 #define CMP_CR1_PMODE_SHIFT                      (4U)
+/*! PMODE - Power Mode Select
+ *  0b0..Low-Speed (LS) Comparison mode selected. In this mode, CMP has slower output propagation delay and lower current consumption.
+ *  0b1..High-Speed (HS) Comparison mode selected. In this mode, CMP has faster output propagation delay and higher current consumption.
+ */
 #define CMP_CR1_PMODE(x)                         (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK)
 #define CMP_CR1_WE_MASK                          (0x40U)
 #define CMP_CR1_WE_SHIFT                         (6U)
+/*! WE - Windowing Enable
+ *  0b0..Windowing mode is not selected.
+ *  0b1..Windowing mode is selected.
+ */
 #define CMP_CR1_WE(x)                            (((uint8_t)(((uint8_t)(x)) << CMP_CR1_WE_SHIFT)) & CMP_CR1_WE_MASK)
 #define CMP_CR1_SE_MASK                          (0x80U)
 #define CMP_CR1_SE_SHIFT                         (7U)
+/*! SE - Sample Enable
+ *  0b0..Sampling mode is not selected.
+ *  0b1..Sampling mode is selected.
+ */
 #define CMP_CR1_SE(x)                            (((uint8_t)(((uint8_t)(x)) << CMP_CR1_SE_SHIFT)) & CMP_CR1_SE_MASK)
 /*! @} */
 
@@ -5732,18 +8573,38 @@ typedef struct {
 #define CMP_SCR_COUT(x)                          (((uint8_t)(((uint8_t)(x)) << CMP_SCR_COUT_SHIFT)) & CMP_SCR_COUT_MASK)
 #define CMP_SCR_CFF_MASK                         (0x2U)
 #define CMP_SCR_CFF_SHIFT                        (1U)
+/*! CFF - Analog Comparator Flag Falling
+ *  0b0..Falling-edge on COUT has not been detected.
+ *  0b1..Falling-edge on COUT has occurred.
+ */
 #define CMP_SCR_CFF(x)                           (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) & CMP_SCR_CFF_MASK)
 #define CMP_SCR_CFR_MASK                         (0x4U)
 #define CMP_SCR_CFR_SHIFT                        (2U)
+/*! CFR - Analog Comparator Flag Rising
+ *  0b0..Rising-edge on COUT has not been detected.
+ *  0b1..Rising-edge on COUT has occurred.
+ */
 #define CMP_SCR_CFR(x)                           (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK)
 #define CMP_SCR_IEF_MASK                         (0x8U)
 #define CMP_SCR_IEF_SHIFT                        (3U)
+/*! IEF - Comparator Interrupt Enable Falling
+ *  0b0..Interrupt is disabled.
+ *  0b1..Interrupt is enabled.
+ */
 #define CMP_SCR_IEF(x)                           (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IEF_SHIFT)) & CMP_SCR_IEF_MASK)
 #define CMP_SCR_IER_MASK                         (0x10U)
 #define CMP_SCR_IER_SHIFT                        (4U)
+/*! IER - Comparator Interrupt Enable Rising
+ *  0b0..Interrupt is disabled.
+ *  0b1..Interrupt is enabled.
+ */
 #define CMP_SCR_IER(x)                           (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IER_SHIFT)) & CMP_SCR_IER_MASK)
 #define CMP_SCR_DMAEN_MASK                       (0x40U)
 #define CMP_SCR_DMAEN_SHIFT                      (6U)
+/*! DMAEN - DMA Enable Control
+ *  0b0..DMA is disabled.
+ *  0b1..DMA is enabled.
+ */
 #define CMP_SCR_DMAEN(x)                         (((uint8_t)(((uint8_t)(x)) << CMP_SCR_DMAEN_SHIFT)) & CMP_SCR_DMAEN_MASK)
 /*! @} */
 
@@ -5754,9 +8615,17 @@ typedef struct {
 #define CMP_DACCR_VOSEL(x)                       (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VOSEL_SHIFT)) & CMP_DACCR_VOSEL_MASK)
 #define CMP_DACCR_VRSEL_MASK                     (0x40U)
 #define CMP_DACCR_VRSEL_SHIFT                    (6U)
+/*! VRSEL - Supply Voltage Reference Source Select
+ *  0b0..Vin1 is selected as resistor ladder network supply reference.
+ *  0b1..Vin2 is selected as resistor ladder network supply reference.
+ */
 #define CMP_DACCR_VRSEL(x)                       (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK)
 #define CMP_DACCR_DACEN_MASK                     (0x80U)
 #define CMP_DACCR_DACEN_SHIFT                    (7U)
+/*! DACEN - DAC Enable
+ *  0b0..DAC is disabled.
+ *  0b1..DAC is enabled.
+ */
 #define CMP_DACCR_DACEN(x)                       (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK)
 /*! @} */
 
@@ -5764,9 +8633,29 @@ typedef struct {
 /*! @{ */
 #define CMP_MUXCR_MSEL_MASK                      (0x7U)
 #define CMP_MUXCR_MSEL_SHIFT                     (0U)
+/*! MSEL - Minus Input Mux Control
+ *  0b000..IN0
+ *  0b001..IN1
+ *  0b010..IN2
+ *  0b011..IN3
+ *  0b100..IN4
+ *  0b101..IN5
+ *  0b110..IN6
+ *  0b111..IN7
+ */
 #define CMP_MUXCR_MSEL(x)                        (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK)
 #define CMP_MUXCR_PSEL_MASK                      (0x38U)
 #define CMP_MUXCR_PSEL_SHIFT                     (3U)
+/*! PSEL - Plus Input Mux Control
+ *  0b000..IN0
+ *  0b001..IN1
+ *  0b010..IN2
+ *  0b011..IN3
+ *  0b100..IN4
+ *  0b101..IN5
+ *  0b110..IN6
+ *  0b111..IN7
+ */
 #define CMP_MUXCR_PSEL(x)                        (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSEL_SHIFT)) & CMP_MUXCR_PSEL_MASK)
 /*! @} */
 
@@ -5848,18 +8737,38 @@ typedef struct {
 /*! @{ */
 #define CSI_CSICR1_PIXEL_BIT_MASK                (0x1U)
 #define CSI_CSICR1_PIXEL_BIT_SHIFT               (0U)
+/*! PIXEL_BIT
+ *  0b0..8-bit data for each pixel
+ *  0b1..10-bit data for each pixel
+ */
 #define CSI_CSICR1_PIXEL_BIT(x)                  (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_PIXEL_BIT_SHIFT)) & CSI_CSICR1_PIXEL_BIT_MASK)
 #define CSI_CSICR1_REDGE_MASK                    (0x2U)
 #define CSI_CSICR1_REDGE_SHIFT                   (1U)
+/*! REDGE
+ *  0b0..Pixel data is latched at the falling edge of CSI_PIXCLK
+ *  0b1..Pixel data is latched at the rising edge of CSI_PIXCLK
+ */
 #define CSI_CSICR1_REDGE(x)                      (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_REDGE_SHIFT)) & CSI_CSICR1_REDGE_MASK)
 #define CSI_CSICR1_INV_PCLK_MASK                 (0x4U)
 #define CSI_CSICR1_INV_PCLK_SHIFT                (2U)
+/*! INV_PCLK
+ *  0b0..CSI_PIXCLK is directly applied to internal circuitry
+ *  0b1..CSI_PIXCLK is inverted before applied to internal circuitry
+ */
 #define CSI_CSICR1_INV_PCLK(x)                   (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_INV_PCLK_SHIFT)) & CSI_CSICR1_INV_PCLK_MASK)
 #define CSI_CSICR1_INV_DATA_MASK                 (0x8U)
 #define CSI_CSICR1_INV_DATA_SHIFT                (3U)
+/*! INV_DATA
+ *  0b0..CSI_D[7:0] data lines are directly applied to internal circuitry
+ *  0b1..CSI_D[7:0] data lines are inverted before applied to internal circuitry
+ */
 #define CSI_CSICR1_INV_DATA(x)                   (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_INV_DATA_SHIFT)) & CSI_CSICR1_INV_DATA_MASK)
 #define CSI_CSICR1_GCLK_MODE_MASK                (0x10U)
 #define CSI_CSICR1_GCLK_MODE_SHIFT               (4U)
+/*! GCLK_MODE
+ *  0b0..Non-gated clock mode. All incoming pixel clocks are valid. HSYNC is ignored.
+ *  0b1..Gated clock mode. Pixel clock signal is valid only when HSYNC is active.
+ */
 #define CSI_CSICR1_GCLK_MODE(x)                  (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_GCLK_MODE_SHIFT)) & CSI_CSICR1_GCLK_MODE_MASK)
 #define CSI_CSICR1_CLR_RXFIFO_MASK               (0x20U)
 #define CSI_CSICR1_CLR_RXFIFO_SHIFT              (5U)
@@ -5869,60 +8778,138 @@ typedef struct {
 #define CSI_CSICR1_CLR_STATFIFO(x)               (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_CLR_STATFIFO_SHIFT)) & CSI_CSICR1_CLR_STATFIFO_MASK)
 #define CSI_CSICR1_PACK_DIR_MASK                 (0x80U)
 #define CSI_CSICR1_PACK_DIR_SHIFT                (7U)
+/*! PACK_DIR
+ *  0b0..Pack from LSB first. For image data, 0x11, 0x22, 0x33, 0x44, it will appear as 0x44332211 in RX FIFO. For
+ *       stat data, 0xAAAA, 0xBBBB, it will appear as 0xBBBBAAAA in STAT FIFO.
+ *  0b1..Pack from MSB first. For image data, 0x11, 0x22, 0x33, 0x44, it will appear as 0x11223344 in RX FIFO. For
+ *       stat data, 0xAAAA, 0xBBBB, it will appear as 0xAAAABBBB in STAT FIFO.
+ */
 #define CSI_CSICR1_PACK_DIR(x)                   (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_PACK_DIR_SHIFT)) & CSI_CSICR1_PACK_DIR_MASK)
 #define CSI_CSICR1_FCC_MASK                      (0x100U)
 #define CSI_CSICR1_FCC_SHIFT                     (8U)
+/*! FCC
+ *  0b0..Asynchronous FIFO clear is selected.
+ *  0b1..Synchronous FIFO clear is selected.
+ */
 #define CSI_CSICR1_FCC(x)                        (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_FCC_SHIFT)) & CSI_CSICR1_FCC_MASK)
 #define CSI_CSICR1_CCIR_EN_MASK                  (0x400U)
 #define CSI_CSICR1_CCIR_EN_SHIFT                 (10U)
+/*! CCIR_EN
+ *  0b0..Traditional interface is selected. Timing interface logic is used to latch data.
+ *  0b1..CCIR656 interface is selected.
+ */
 #define CSI_CSICR1_CCIR_EN(x)                    (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_CCIR_EN_SHIFT)) & CSI_CSICR1_CCIR_EN_MASK)
 #define CSI_CSICR1_HSYNC_POL_MASK                (0x800U)
 #define CSI_CSICR1_HSYNC_POL_SHIFT               (11U)
+/*! HSYNC_POL
+ *  0b0..HSYNC is active low
+ *  0b1..HSYNC is active high
+ */
 #define CSI_CSICR1_HSYNC_POL(x)                  (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_HSYNC_POL_SHIFT)) & CSI_CSICR1_HSYNC_POL_MASK)
 #define CSI_CSICR1_SOF_INTEN_MASK                (0x10000U)
 #define CSI_CSICR1_SOF_INTEN_SHIFT               (16U)
+/*! SOF_INTEN
+ *  0b0..SOF interrupt disable
+ *  0b1..SOF interrupt enable
+ */
 #define CSI_CSICR1_SOF_INTEN(x)                  (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SOF_INTEN_SHIFT)) & CSI_CSICR1_SOF_INTEN_MASK)
 #define CSI_CSICR1_SOF_POL_MASK                  (0x20000U)
 #define CSI_CSICR1_SOF_POL_SHIFT                 (17U)
+/*! SOF_POL
+ *  0b0..SOF interrupt is generated on SOF falling edge
+ *  0b1..SOF interrupt is generated on SOF rising edge
+ */
 #define CSI_CSICR1_SOF_POL(x)                    (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SOF_POL_SHIFT)) & CSI_CSICR1_SOF_POL_MASK)
 #define CSI_CSICR1_RXFF_INTEN_MASK               (0x40000U)
 #define CSI_CSICR1_RXFF_INTEN_SHIFT              (18U)
+/*! RXFF_INTEN
+ *  0b0..RxFIFO full interrupt disable
+ *  0b1..RxFIFO full interrupt enable
+ */
 #define CSI_CSICR1_RXFF_INTEN(x)                 (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_RXFF_INTEN_SHIFT)) & CSI_CSICR1_RXFF_INTEN_MASK)
 #define CSI_CSICR1_FB1_DMA_DONE_INTEN_MASK       (0x80000U)
 #define CSI_CSICR1_FB1_DMA_DONE_INTEN_SHIFT      (19U)
+/*! FB1_DMA_DONE_INTEN
+ *  0b0..Frame Buffer1 DMA Transfer Done interrupt disable
+ *  0b1..Frame Buffer1 DMA Transfer Done interrupt enable
+ */
 #define CSI_CSICR1_FB1_DMA_DONE_INTEN(x)         (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_FB1_DMA_DONE_INTEN_SHIFT)) & CSI_CSICR1_FB1_DMA_DONE_INTEN_MASK)
 #define CSI_CSICR1_FB2_DMA_DONE_INTEN_MASK       (0x100000U)
 #define CSI_CSICR1_FB2_DMA_DONE_INTEN_SHIFT      (20U)
+/*! FB2_DMA_DONE_INTEN
+ *  0b0..Frame Buffer2 DMA Transfer Done interrupt disable
+ *  0b1..Frame Buffer2 DMA Transfer Done interrupt enable
+ */
 #define CSI_CSICR1_FB2_DMA_DONE_INTEN(x)         (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_FB2_DMA_DONE_INTEN_SHIFT)) & CSI_CSICR1_FB2_DMA_DONE_INTEN_MASK)
 #define CSI_CSICR1_STATFF_INTEN_MASK             (0x200000U)
 #define CSI_CSICR1_STATFF_INTEN_SHIFT            (21U)
+/*! STATFF_INTEN
+ *  0b0..STATFIFO full interrupt disable
+ *  0b1..STATFIFO full interrupt enable
+ */
 #define CSI_CSICR1_STATFF_INTEN(x)               (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_STATFF_INTEN_SHIFT)) & CSI_CSICR1_STATFF_INTEN_MASK)
 #define CSI_CSICR1_SFF_DMA_DONE_INTEN_MASK       (0x400000U)
 #define CSI_CSICR1_SFF_DMA_DONE_INTEN_SHIFT      (22U)
+/*! SFF_DMA_DONE_INTEN
+ *  0b0..STATFIFO DMA Transfer Done interrupt disable
+ *  0b1..STATFIFO DMA Transfer Done interrupt enable
+ */
 #define CSI_CSICR1_SFF_DMA_DONE_INTEN(x)         (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SFF_DMA_DONE_INTEN_SHIFT)) & CSI_CSICR1_SFF_DMA_DONE_INTEN_MASK)
 #define CSI_CSICR1_RF_OR_INTEN_MASK              (0x1000000U)
 #define CSI_CSICR1_RF_OR_INTEN_SHIFT             (24U)
+/*! RF_OR_INTEN
+ *  0b0..RxFIFO overrun interrupt is disabled
+ *  0b1..RxFIFO overrun interrupt is enabled
+ */
 #define CSI_CSICR1_RF_OR_INTEN(x)                (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_RF_OR_INTEN_SHIFT)) & CSI_CSICR1_RF_OR_INTEN_MASK)
 #define CSI_CSICR1_SF_OR_INTEN_MASK              (0x2000000U)
 #define CSI_CSICR1_SF_OR_INTEN_SHIFT             (25U)
+/*! SF_OR_INTEN
+ *  0b0..STATFIFO overrun interrupt is disabled
+ *  0b1..STATFIFO overrun interrupt is enabled
+ */
 #define CSI_CSICR1_SF_OR_INTEN(x)                (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SF_OR_INTEN_SHIFT)) & CSI_CSICR1_SF_OR_INTEN_MASK)
 #define CSI_CSICR1_COF_INT_EN_MASK               (0x4000000U)
 #define CSI_CSICR1_COF_INT_EN_SHIFT              (26U)
+/*! COF_INT_EN
+ *  0b0..COF interrupt is disabled
+ *  0b1..COF interrupt is enabled
+ */
 #define CSI_CSICR1_COF_INT_EN(x)                 (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_COF_INT_EN_SHIFT)) & CSI_CSICR1_COF_INT_EN_MASK)
 #define CSI_CSICR1_CCIR_MODE_MASK                (0x8000000U)
 #define CSI_CSICR1_CCIR_MODE_SHIFT               (27U)
+/*! CCIR_MODE
+ *  0b0..Progressive mode is selected
+ *  0b1..Interlace mode is selected
+ */
 #define CSI_CSICR1_CCIR_MODE(x)                  (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_CCIR_MODE_SHIFT)) & CSI_CSICR1_CCIR_MODE_MASK)
 #define CSI_CSICR1_PrP_IF_EN_MASK                (0x10000000U)
 #define CSI_CSICR1_PrP_IF_EN_SHIFT               (28U)
+/*! PrP_IF_EN
+ *  0b0..CSI to PrP bus is disabled
+ *  0b1..CSI to PrP bus is enabled
+ */
 #define CSI_CSICR1_PrP_IF_EN(x)                  (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_PrP_IF_EN_SHIFT)) & CSI_CSICR1_PrP_IF_EN_MASK)
 #define CSI_CSICR1_EOF_INT_EN_MASK               (0x20000000U)
 #define CSI_CSICR1_EOF_INT_EN_SHIFT              (29U)
+/*! EOF_INT_EN
+ *  0b0..EOF interrupt is disabled.
+ *  0b1..EOF interrupt is generated when RX count value is reached.
+ */
 #define CSI_CSICR1_EOF_INT_EN(x)                 (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_EOF_INT_EN_SHIFT)) & CSI_CSICR1_EOF_INT_EN_MASK)
 #define CSI_CSICR1_EXT_VSYNC_MASK                (0x40000000U)
 #define CSI_CSICR1_EXT_VSYNC_SHIFT               (30U)
+/*! EXT_VSYNC
+ *  0b0..Internal VSYNC mode
+ *  0b1..External VSYNC mode
+ */
 #define CSI_CSICR1_EXT_VSYNC(x)                  (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_EXT_VSYNC_SHIFT)) & CSI_CSICR1_EXT_VSYNC_MASK)
 #define CSI_CSICR1_SWAP16_EN_MASK                (0x80000000U)
 #define CSI_CSICR1_SWAP16_EN_SHIFT               (31U)
+/*! SWAP16_EN
+ *  0b0..Disable swapping
+ *  0b1..Enable swapping
+ */
 #define CSI_CSICR1_SWAP16_EN(x)                  (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SWAP16_EN_SHIFT)) & CSI_CSICR1_SWAP16_EN_MASK)
 /*! @} */
 
@@ -5936,24 +8923,62 @@ typedef struct {
 #define CSI_CSICR2_VSC(x)                        (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_VSC_SHIFT)) & CSI_CSICR2_VSC_MASK)
 #define CSI_CSICR2_LVRM_MASK                     (0x70000U)
 #define CSI_CSICR2_LVRM_SHIFT                    (16U)
+/*! LVRM
+ *  0b000..512 x 384
+ *  0b001..448 x 336
+ *  0b010..384 x 288
+ *  0b011..384 x 256
+ *  0b100..320 x 240
+ *  0b101..288 x 216
+ *  0b110..400 x 300
+ */
 #define CSI_CSICR2_LVRM(x)                       (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_LVRM_SHIFT)) & CSI_CSICR2_LVRM_MASK)
 #define CSI_CSICR2_BTS_MASK                      (0x180000U)
 #define CSI_CSICR2_BTS_SHIFT                     (19U)
+/*! BTS
+ *  0b00..GR
+ *  0b01..RG
+ *  0b10..BG
+ *  0b11..GB
+ */
 #define CSI_CSICR2_BTS(x)                        (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_BTS_SHIFT)) & CSI_CSICR2_BTS_MASK)
 #define CSI_CSICR2_SCE_MASK                      (0x800000U)
 #define CSI_CSICR2_SCE_SHIFT                     (23U)
+/*! SCE
+ *  0b0..Skip count disable
+ *  0b1..Skip count enable
+ */
 #define CSI_CSICR2_SCE(x)                        (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_SCE_SHIFT)) & CSI_CSICR2_SCE_MASK)
 #define CSI_CSICR2_AFS_MASK                      (0x3000000U)
 #define CSI_CSICR2_AFS_SHIFT                     (24U)
+/*! AFS
+ *  0b00..Abs Diff on consecutive green pixels
+ *  0b01..Abs Diff on every third green pixels
+ *  0b1x..Abs Diff on every four green pixels
+ */
 #define CSI_CSICR2_AFS(x)                        (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_AFS_SHIFT)) & CSI_CSICR2_AFS_MASK)
 #define CSI_CSICR2_DRM_MASK                      (0x4000000U)
 #define CSI_CSICR2_DRM_SHIFT                     (26U)
+/*! DRM
+ *  0b0..Stats grid of 8 x 6
+ *  0b1..Stats grid of 8 x 12
+ */
 #define CSI_CSICR2_DRM(x)                        (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_DRM_SHIFT)) & CSI_CSICR2_DRM_MASK)
 #define CSI_CSICR2_DMA_BURST_TYPE_SFF_MASK       (0x30000000U)
 #define CSI_CSICR2_DMA_BURST_TYPE_SFF_SHIFT      (28U)
+/*! DMA_BURST_TYPE_SFF
+ *  0bx0..INCR8
+ *  0b01..INCR4
+ *  0b11..INCR16
+ */
 #define CSI_CSICR2_DMA_BURST_TYPE_SFF(x)         (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_DMA_BURST_TYPE_SFF_SHIFT)) & CSI_CSICR2_DMA_BURST_TYPE_SFF_MASK)
 #define CSI_CSICR2_DMA_BURST_TYPE_RFF_MASK       (0xC0000000U)
 #define CSI_CSICR2_DMA_BURST_TYPE_RFF_SHIFT      (30U)
+/*! DMA_BURST_TYPE_RFF
+ *  0bx0..INCR8
+ *  0b01..INCR4
+ *  0b11..INCR16
+ */
 #define CSI_CSICR2_DMA_BURST_TYPE_RFF(x)         (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_DMA_BURST_TYPE_RFF_SHIFT)) & CSI_CSICR2_DMA_BURST_TYPE_RFF_MASK)
 /*! @} */
 
@@ -5961,39 +8986,99 @@ typedef struct {
 /*! @{ */
 #define CSI_CSICR3_ECC_AUTO_EN_MASK              (0x1U)
 #define CSI_CSICR3_ECC_AUTO_EN_SHIFT             (0U)
+/*! ECC_AUTO_EN
+ *  0b0..Auto Error correction is disabled.
+ *  0b1..Auto Error correction is enabled.
+ */
 #define CSI_CSICR3_ECC_AUTO_EN(x)                (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_ECC_AUTO_EN_SHIFT)) & CSI_CSICR3_ECC_AUTO_EN_MASK)
 #define CSI_CSICR3_ECC_INT_EN_MASK               (0x2U)
 #define CSI_CSICR3_ECC_INT_EN_SHIFT              (1U)
+/*! ECC_INT_EN
+ *  0b0..No interrupt is generated when error is detected. Only the status bit ECC_INT is set.
+ *  0b1..Interrupt is generated when error is detected.
+ */
 #define CSI_CSICR3_ECC_INT_EN(x)                 (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_ECC_INT_EN_SHIFT)) & CSI_CSICR3_ECC_INT_EN_MASK)
 #define CSI_CSICR3_ZERO_PACK_EN_MASK             (0x4U)
 #define CSI_CSICR3_ZERO_PACK_EN_SHIFT            (2U)
+/*! ZERO_PACK_EN
+ *  0b0..Zero packing disabled
+ *  0b1..Zero packing enabled
+ */
 #define CSI_CSICR3_ZERO_PACK_EN(x)               (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_ZERO_PACK_EN_SHIFT)) & CSI_CSICR3_ZERO_PACK_EN_MASK)
 #define CSI_CSICR3_TWO_8BIT_SENSOR_MASK          (0x8U)
 #define CSI_CSICR3_TWO_8BIT_SENSOR_SHIFT         (3U)
+/*! TWO_8BIT_SENSOR
+ *  0b0..Only one sensor is connected.
+ *  0b1..Two 8-bit sensors are connected or one 16-bit sensor is connected.
+ */
 #define CSI_CSICR3_TWO_8BIT_SENSOR(x)            (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_TWO_8BIT_SENSOR_SHIFT)) & CSI_CSICR3_TWO_8BIT_SENSOR_MASK)
 #define CSI_CSICR3_RxFF_LEVEL_MASK               (0x70U)
 #define CSI_CSICR3_RxFF_LEVEL_SHIFT              (4U)
+/*! RxFF_LEVEL
+ *  0b000..4 Double words
+ *  0b001..8 Double words
+ *  0b010..16 Double words
+ *  0b011..24 Double words
+ *  0b100..32 Double words
+ *  0b101..48 Double words
+ *  0b110..64 Double words
+ *  0b111..96 Double words
+ */
 #define CSI_CSICR3_RxFF_LEVEL(x)                 (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_RxFF_LEVEL_SHIFT)) & CSI_CSICR3_RxFF_LEVEL_MASK)
 #define CSI_CSICR3_HRESP_ERR_EN_MASK             (0x80U)
 #define CSI_CSICR3_HRESP_ERR_EN_SHIFT            (7U)
+/*! HRESP_ERR_EN
+ *  0b0..Disable hresponse error interrupt
+ *  0b1..Enable hresponse error interrupt
+ */
 #define CSI_CSICR3_HRESP_ERR_EN(x)               (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_HRESP_ERR_EN_SHIFT)) & CSI_CSICR3_HRESP_ERR_EN_MASK)
 #define CSI_CSICR3_STATFF_LEVEL_MASK             (0x700U)
 #define CSI_CSICR3_STATFF_LEVEL_SHIFT            (8U)
+/*! STATFF_LEVEL
+ *  0b000..4 Double words
+ *  0b001..8 Double words
+ *  0b010..12 Double words
+ *  0b011..16 Double words
+ *  0b100..24 Double words
+ *  0b101..32 Double words
+ *  0b110..48 Double words
+ *  0b111..64 Double words
+ */
 #define CSI_CSICR3_STATFF_LEVEL(x)               (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_STATFF_LEVEL_SHIFT)) & CSI_CSICR3_STATFF_LEVEL_MASK)
 #define CSI_CSICR3_DMA_REQ_EN_SFF_MASK           (0x800U)
 #define CSI_CSICR3_DMA_REQ_EN_SFF_SHIFT          (11U)
+/*! DMA_REQ_EN_SFF
+ *  0b0..Disable the dma request
+ *  0b1..Enable the dma request
+ */
 #define CSI_CSICR3_DMA_REQ_EN_SFF(x)             (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_DMA_REQ_EN_SFF_SHIFT)) & CSI_CSICR3_DMA_REQ_EN_SFF_MASK)
 #define CSI_CSICR3_DMA_REQ_EN_RFF_MASK           (0x1000U)
 #define CSI_CSICR3_DMA_REQ_EN_RFF_SHIFT          (12U)
+/*! DMA_REQ_EN_RFF
+ *  0b0..Disable the dma request
+ *  0b1..Enable the dma request
+ */
 #define CSI_CSICR3_DMA_REQ_EN_RFF(x)             (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_DMA_REQ_EN_RFF_SHIFT)) & CSI_CSICR3_DMA_REQ_EN_RFF_MASK)
 #define CSI_CSICR3_DMA_REFLASH_SFF_MASK          (0x2000U)
 #define CSI_CSICR3_DMA_REFLASH_SFF_SHIFT         (13U)
+/*! DMA_REFLASH_SFF
+ *  0b0..No reflashing
+ *  0b1..Reflash the embedded DMA controller
+ */
 #define CSI_CSICR3_DMA_REFLASH_SFF(x)            (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_DMA_REFLASH_SFF_SHIFT)) & CSI_CSICR3_DMA_REFLASH_SFF_MASK)
 #define CSI_CSICR3_DMA_REFLASH_RFF_MASK          (0x4000U)
 #define CSI_CSICR3_DMA_REFLASH_RFF_SHIFT         (14U)
+/*! DMA_REFLASH_RFF
+ *  0b0..No reflashing
+ *  0b1..Reflash the embedded DMA controller
+ */
 #define CSI_CSICR3_DMA_REFLASH_RFF(x)            (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_DMA_REFLASH_RFF_SHIFT)) & CSI_CSICR3_DMA_REFLASH_RFF_MASK)
 #define CSI_CSICR3_FRMCNT_RST_MASK               (0x8000U)
 #define CSI_CSICR3_FRMCNT_RST_SHIFT              (15U)
+/*! FRMCNT_RST
+ *  0b0..Do not reset
+ *  0b1..Reset frame counter immediately
+ */
 #define CSI_CSICR3_FRMCNT_RST(x)                 (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_FRMCNT_RST_SHIFT)) & CSI_CSICR3_FRMCNT_RST_MASK)
 #define CSI_CSICR3_FRMCNT_MASK                   (0xFFFF0000U)
 #define CSI_CSICR3_FRMCNT_SHIFT                  (16U)
@@ -6025,48 +9110,108 @@ typedef struct {
 /*! @{ */
 #define CSI_CSISR_DRDY_MASK                      (0x1U)
 #define CSI_CSISR_DRDY_SHIFT                     (0U)
+/*! DRDY
+ *  0b0..No data (word) is ready
+ *  0b1..At least 1 datum (word) is ready in RXFIFO.
+ */
 #define CSI_CSISR_DRDY(x)                        (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DRDY_SHIFT)) & CSI_CSISR_DRDY_MASK)
 #define CSI_CSISR_ECC_INT_MASK                   (0x2U)
 #define CSI_CSISR_ECC_INT_SHIFT                  (1U)
+/*! ECC_INT
+ *  0b0..No error detected
+ *  0b1..Error is detected in CCIR coding
+ */
 #define CSI_CSISR_ECC_INT(x)                     (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_ECC_INT_SHIFT)) & CSI_CSISR_ECC_INT_MASK)
 #define CSI_CSISR_HRESP_ERR_INT_MASK             (0x80U)
 #define CSI_CSISR_HRESP_ERR_INT_SHIFT            (7U)
+/*! HRESP_ERR_INT
+ *  0b0..No hresponse error.
+ *  0b1..Hresponse error is detected.
+ */
 #define CSI_CSISR_HRESP_ERR_INT(x)               (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_HRESP_ERR_INT_SHIFT)) & CSI_CSISR_HRESP_ERR_INT_MASK)
 #define CSI_CSISR_COF_INT_MASK                   (0x2000U)
 #define CSI_CSISR_COF_INT_SHIFT                  (13U)
+/*! COF_INT
+ *  0b0..Video field has no change.
+ *  0b1..Change of video field is detected.
+ */
 #define CSI_CSISR_COF_INT(x)                     (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_COF_INT_SHIFT)) & CSI_CSISR_COF_INT_MASK)
 #define CSI_CSISR_F1_INT_MASK                    (0x4000U)
 #define CSI_CSISR_F1_INT_SHIFT                   (14U)
+/*! F1_INT
+ *  0b0..Field 1 of video is not detected.
+ *  0b1..Field 1 of video is about to start.
+ */
 #define CSI_CSISR_F1_INT(x)                      (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_F1_INT_SHIFT)) & CSI_CSISR_F1_INT_MASK)
 #define CSI_CSISR_F2_INT_MASK                    (0x8000U)
 #define CSI_CSISR_F2_INT_SHIFT                   (15U)
+/*! F2_INT
+ *  0b0..Field 2 of video is not detected
+ *  0b1..Field 2 of video is about to start
+ */
 #define CSI_CSISR_F2_INT(x)                      (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_F2_INT_SHIFT)) & CSI_CSISR_F2_INT_MASK)
 #define CSI_CSISR_SOF_INT_MASK                   (0x10000U)
 #define CSI_CSISR_SOF_INT_SHIFT                  (16U)
+/*! SOF_INT
+ *  0b0..SOF is not detected.
+ *  0b1..SOF is detected.
+ */
 #define CSI_CSISR_SOF_INT(x)                     (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_SOF_INT_SHIFT)) & CSI_CSISR_SOF_INT_MASK)
 #define CSI_CSISR_EOF_INT_MASK                   (0x20000U)
 #define CSI_CSISR_EOF_INT_SHIFT                  (17U)
+/*! EOF_INT
+ *  0b0..EOF is not detected.
+ *  0b1..EOF is detected.
+ */
 #define CSI_CSISR_EOF_INT(x)                     (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_EOF_INT_SHIFT)) & CSI_CSISR_EOF_INT_MASK)
 #define CSI_CSISR_RxFF_INT_MASK                  (0x40000U)
 #define CSI_CSISR_RxFF_INT_SHIFT                 (18U)
+/*! RxFF_INT
+ *  0b0..RxFIFO is not full.
+ *  0b1..RxFIFO is full.
+ */
 #define CSI_CSISR_RxFF_INT(x)                    (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_RxFF_INT_SHIFT)) & CSI_CSISR_RxFF_INT_MASK)
 #define CSI_CSISR_DMA_TSF_DONE_FB1_MASK          (0x80000U)
 #define CSI_CSISR_DMA_TSF_DONE_FB1_SHIFT         (19U)
+/*! DMA_TSF_DONE_FB1
+ *  0b0..DMA transfer is not completed.
+ *  0b1..DMA transfer is completed.
+ */
 #define CSI_CSISR_DMA_TSF_DONE_FB1(x)            (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_TSF_DONE_FB1_SHIFT)) & CSI_CSISR_DMA_TSF_DONE_FB1_MASK)
 #define CSI_CSISR_DMA_TSF_DONE_FB2_MASK          (0x100000U)
 #define CSI_CSISR_DMA_TSF_DONE_FB2_SHIFT         (20U)
+/*! DMA_TSF_DONE_FB2
+ *  0b0..DMA transfer is not completed.
+ *  0b1..DMA transfer is completed.
+ */
 #define CSI_CSISR_DMA_TSF_DONE_FB2(x)            (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_TSF_DONE_FB2_SHIFT)) & CSI_CSISR_DMA_TSF_DONE_FB2_MASK)
 #define CSI_CSISR_STATFF_INT_MASK                (0x200000U)
 #define CSI_CSISR_STATFF_INT_SHIFT               (21U)
+/*! STATFF_INT
+ *  0b0..STATFIFO is not full.
+ *  0b1..STATFIFO is full.
+ */
 #define CSI_CSISR_STATFF_INT(x)                  (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_STATFF_INT_SHIFT)) & CSI_CSISR_STATFF_INT_MASK)
 #define CSI_CSISR_DMA_TSF_DONE_SFF_MASK          (0x400000U)
 #define CSI_CSISR_DMA_TSF_DONE_SFF_SHIFT         (22U)
+/*! DMA_TSF_DONE_SFF
+ *  0b0..DMA transfer is not completed.
+ *  0b1..DMA transfer is completed.
+ */
 #define CSI_CSISR_DMA_TSF_DONE_SFF(x)            (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_TSF_DONE_SFF_SHIFT)) & CSI_CSISR_DMA_TSF_DONE_SFF_MASK)
 #define CSI_CSISR_RF_OR_INT_MASK                 (0x1000000U)
 #define CSI_CSISR_RF_OR_INT_SHIFT                (24U)
+/*! RF_OR_INT
+ *  0b0..RXFIFO has not overflowed.
+ *  0b1..RXFIFO has overflowed.
+ */
 #define CSI_CSISR_RF_OR_INT(x)                   (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_RF_OR_INT_SHIFT)) & CSI_CSISR_RF_OR_INT_MASK)
 #define CSI_CSISR_SF_OR_INT_MASK                 (0x2000000U)
 #define CSI_CSISR_SF_OR_INT_SHIFT                (25U)
+/*! SF_OR_INT
+ *  0b0..STATFIFO has not overflowed.
+ *  0b1..STATFIFO has overflowed.
+ */
 #define CSI_CSISR_SF_OR_INT(x)                   (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_SF_OR_INT_SHIFT)) & CSI_CSISR_SF_OR_INT_MASK)
 #define CSI_CSISR_DMA_FIELD1_DONE_MASK           (0x4000000U)
 #define CSI_CSISR_DMA_FIELD1_DONE_SHIFT          (26U)
@@ -6131,6 +9276,10 @@ typedef struct {
 /*! @{ */
 #define CSI_CSICR18_DEINTERLACE_EN_MASK          (0x4U)
 #define CSI_CSICR18_DEINTERLACE_EN_SHIFT         (2U)
+/*! DEINTERLACE_EN
+ *  0b0..Deinterlace disabled
+ *  0b1..Deinterlace enabled
+ */
 #define CSI_CSICR18_DEINTERLACE_EN(x)            (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_DEINTERLACE_EN_SHIFT)) & CSI_CSICR18_DEINTERLACE_EN_MASK)
 #define CSI_CSICR18_PARALLEL24_EN_MASK           (0x8U)
 #define CSI_CSICR18_PARALLEL24_EN_SHIFT          (3U)
@@ -6140,27 +9289,53 @@ typedef struct {
 #define CSI_CSICR18_BASEADDR_SWITCH_EN(x)        (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_BASEADDR_SWITCH_EN_SHIFT)) & CSI_CSICR18_BASEADDR_SWITCH_EN_MASK)
 #define CSI_CSICR18_BASEADDR_SWITCH_SEL_MASK     (0x20U)
 #define CSI_CSICR18_BASEADDR_SWITCH_SEL_SHIFT    (5U)
+/*! BASEADDR_SWITCH_SEL
+ *  0b0..Switching base address at the edge of the vsync
+ *  0b1..Switching base address at the edge of the first data of each frame
+ */
 #define CSI_CSICR18_BASEADDR_SWITCH_SEL(x)       (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_BASEADDR_SWITCH_SEL_SHIFT)) & CSI_CSICR18_BASEADDR_SWITCH_SEL_MASK)
 #define CSI_CSICR18_FIELD0_DONE_IE_MASK          (0x40U)
 #define CSI_CSICR18_FIELD0_DONE_IE_SHIFT         (6U)
+/*! FIELD0_DONE_IE
+ *  0b0..Interrupt disabled
+ *  0b1..Interrupt enabled
+ */
 #define CSI_CSICR18_FIELD0_DONE_IE(x)            (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_FIELD0_DONE_IE_SHIFT)) & CSI_CSICR18_FIELD0_DONE_IE_MASK)
 #define CSI_CSICR18_DMA_FIELD1_DONE_IE_MASK      (0x80U)
 #define CSI_CSICR18_DMA_FIELD1_DONE_IE_SHIFT     (7U)
+/*! DMA_FIELD1_DONE_IE
+ *  0b0..Interrupt disabled
+ *  0b1..Interrupt enabled
+ */
 #define CSI_CSICR18_DMA_FIELD1_DONE_IE(x)        (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_DMA_FIELD1_DONE_IE_SHIFT)) & CSI_CSICR18_DMA_FIELD1_DONE_IE_MASK)
 #define CSI_CSICR18_LAST_DMA_REQ_SEL_MASK        (0x100U)
 #define CSI_CSICR18_LAST_DMA_REQ_SEL_SHIFT       (8U)
+/*! LAST_DMA_REQ_SEL
+ *  0b0..fifo_full_level
+ *  0b1..hburst_length
+ */
 #define CSI_CSICR18_LAST_DMA_REQ_SEL(x)          (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_LAST_DMA_REQ_SEL_SHIFT)) & CSI_CSICR18_LAST_DMA_REQ_SEL_MASK)
 #define CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_MASK (0x200U)
 #define CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_SHIFT (9U)
 #define CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE(x)  (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_SHIFT)) & CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_MASK)
 #define CSI_CSICR18_RGB888A_FORMAT_SEL_MASK      (0x400U)
 #define CSI_CSICR18_RGB888A_FORMAT_SEL_SHIFT     (10U)
+/*! RGB888A_FORMAT_SEL
+ *  0b0..{8'h0, data[23:0]}
+ *  0b1..{data[23:0], 8'h0}
+ */
 #define CSI_CSICR18_RGB888A_FORMAT_SEL(x)        (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_RGB888A_FORMAT_SEL_SHIFT)) & CSI_CSICR18_RGB888A_FORMAT_SEL_MASK)
 #define CSI_CSICR18_AHB_HPROT_MASK               (0xF000U)
 #define CSI_CSICR18_AHB_HPROT_SHIFT              (12U)
 #define CSI_CSICR18_AHB_HPROT(x)                 (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_AHB_HPROT_SHIFT)) & CSI_CSICR18_AHB_HPROT_MASK)
 #define CSI_CSICR18_MASK_OPTION_MASK             (0xC0000U)
 #define CSI_CSICR18_MASK_OPTION_SHIFT            (18U)
+/*! MASK_OPTION
+ *  0b00..Writing to memory from first completely frame, when using this option, the CSI_ENABLE should be 1.
+ *  0b01..Writing to memory when CSI_ENABLE is 1.
+ *  0b10..Writing to memory from second completely frame, when using this option, the CSI_ENABLE should be 1.
+ *  0b11..Writing to memory when data comes in, not matter the CSI_ENABLE is 1 or 0.
+ */
 #define CSI_CSICR18_MASK_OPTION(x)               (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_MASK_OPTION_SHIFT)) & CSI_CSICR18_MASK_OPTION_MASK)
 #define CSI_CSICR18_CSI_ENABLE_MASK              (0x80000000U)
 #define CSI_CSICR18_CSI_ENABLE_SHIFT             (31U)
@@ -6230,57 +9405,129 @@ typedef struct {
 /*! @{ */
 #define CSU_CSL_SUR_S2_MASK                      (0x1U)
 #define CSU_CSL_SUR_S2_SHIFT                     (0U)
+/*! SUR_S2
+ *  0b0..The secure user read access is disabled for the second slave.
+ *  0b1..The secure user read access is enabled for the second slave.
+ */
 #define CSU_CSL_SUR_S2(x)                        (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUR_S2_SHIFT)) & CSU_CSL_SUR_S2_MASK)
 #define CSU_CSL_SSR_S2_MASK                      (0x2U)
 #define CSU_CSL_SSR_S2_SHIFT                     (1U)
+/*! SSR_S2
+ *  0b0..The secure supervisor read access is disabled for the second slave.
+ *  0b1..The secure supervisor read access is enabled for the second slave.
+ */
 #define CSU_CSL_SSR_S2(x)                        (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSR_S2_SHIFT)) & CSU_CSL_SSR_S2_MASK)
 #define CSU_CSL_NUR_S2_MASK                      (0x4U)
 #define CSU_CSL_NUR_S2_SHIFT                     (2U)
+/*! NUR_S2
+ *  0b0..The non-secure user read access is disabled for the second slave.
+ *  0b1..The non-secure user read access is enabled for the second slave.
+ */
 #define CSU_CSL_NUR_S2(x)                        (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUR_S2_SHIFT)) & CSU_CSL_NUR_S2_MASK)
 #define CSU_CSL_NSR_S2_MASK                      (0x8U)
 #define CSU_CSL_NSR_S2_SHIFT                     (3U)
+/*! NSR_S2
+ *  0b0..The non-secure supervisor read access is disabled for the second slave.
+ *  0b1..The non-secure supervisor read access is enabled for the second slave.
+ */
 #define CSU_CSL_NSR_S2(x)                        (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSR_S2_SHIFT)) & CSU_CSL_NSR_S2_MASK)
 #define CSU_CSL_SUW_S2_MASK                      (0x10U)
 #define CSU_CSL_SUW_S2_SHIFT                     (4U)
+/*! SUW_S2
+ *  0b0..The secure user write access is disabled for the second slave.
+ *  0b1..The secure user write access is enabled for the second slave.
+ */
 #define CSU_CSL_SUW_S2(x)                        (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUW_S2_SHIFT)) & CSU_CSL_SUW_S2_MASK)
 #define CSU_CSL_SSW_S2_MASK                      (0x20U)
 #define CSU_CSL_SSW_S2_SHIFT                     (5U)
+/*! SSW_S2
+ *  0b0..The secure supervisor write access is disabled for the second slave.
+ *  0b1..The secure supervisor write access is enabled for the second slave.
+ */
 #define CSU_CSL_SSW_S2(x)                        (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSW_S2_SHIFT)) & CSU_CSL_SSW_S2_MASK)
 #define CSU_CSL_NUW_S2_MASK                      (0x40U)
 #define CSU_CSL_NUW_S2_SHIFT                     (6U)
+/*! NUW_S2
+ *  0b0..The non-secure user write access is disabled for the second slave.
+ *  0b1..The non-secure user write access is enabled for the second slave.
+ */
 #define CSU_CSL_NUW_S2(x)                        (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUW_S2_SHIFT)) & CSU_CSL_NUW_S2_MASK)
 #define CSU_CSL_NSW_S2_MASK                      (0x80U)
 #define CSU_CSL_NSW_S2_SHIFT                     (7U)
+/*! NSW_S2
+ *  0b0..The non-secure supervisor write access is disabled for the second slave.
+ *  0b1..The non-secure supervisor write access is enabled for the second slave.
+ */
 #define CSU_CSL_NSW_S2(x)                        (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSW_S2_SHIFT)) & CSU_CSL_NSW_S2_MASK)
 #define CSU_CSL_LOCK_S2_MASK                     (0x100U)
 #define CSU_CSL_LOCK_S2_SHIFT                    (8U)
+/*! LOCK_S2
+ *  0b0..Not locked. Bits 7-0 can be written by the software.
+ *  0b1..Bits 7-0 are locked and cannot be written by the software
+ */
 #define CSU_CSL_LOCK_S2(x)                       (((uint32_t)(((uint32_t)(x)) << CSU_CSL_LOCK_S2_SHIFT)) & CSU_CSL_LOCK_S2_MASK)
 #define CSU_CSL_SUR_S1_MASK                      (0x10000U)
 #define CSU_CSL_SUR_S1_SHIFT                     (16U)
+/*! SUR_S1
+ *  0b0..The secure user read access is disabled for the first slave.
+ *  0b1..The secure user read access is enabled for the first slave.
+ */
 #define CSU_CSL_SUR_S1(x)                        (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUR_S1_SHIFT)) & CSU_CSL_SUR_S1_MASK)
 #define CSU_CSL_SSR_S1_MASK                      (0x20000U)
 #define CSU_CSL_SSR_S1_SHIFT                     (17U)
+/*! SSR_S1
+ *  0b0..The secure supervisor read access is disabled for the first slave.
+ *  0b1..The secure supervisor read access is enabled for the first slave.
+ */
 #define CSU_CSL_SSR_S1(x)                        (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSR_S1_SHIFT)) & CSU_CSL_SSR_S1_MASK)
 #define CSU_CSL_NUR_S1_MASK                      (0x40000U)
 #define CSU_CSL_NUR_S1_SHIFT                     (18U)
+/*! NUR_S1
+ *  0b0..The non-secure user read access is disabled for the first slave.
+ *  0b1..The non-secure user read access is enabled for the first slave.
+ */
 #define CSU_CSL_NUR_S1(x)                        (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUR_S1_SHIFT)) & CSU_CSL_NUR_S1_MASK)
 #define CSU_CSL_NSR_S1_MASK                      (0x80000U)
 #define CSU_CSL_NSR_S1_SHIFT                     (19U)
+/*! NSR_S1
+ *  0b0..The non-secure supervisor read access is disabled for the first slave.
+ *  0b1..The non-secure supervisor read access is enabled for the first slave.
+ */
 #define CSU_CSL_NSR_S1(x)                        (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSR_S1_SHIFT)) & CSU_CSL_NSR_S1_MASK)
 #define CSU_CSL_SUW_S1_MASK                      (0x100000U)
 #define CSU_CSL_SUW_S1_SHIFT                     (20U)
+/*! SUW_S1
+ *  0b0..The secure user write access is disabled for the first slave.
+ *  0b1..The secure user write access is enabled for the first slave.
+ */
 #define CSU_CSL_SUW_S1(x)                        (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUW_S1_SHIFT)) & CSU_CSL_SUW_S1_MASK)
 #define CSU_CSL_SSW_S1_MASK                      (0x200000U)
 #define CSU_CSL_SSW_S1_SHIFT                     (21U)
+/*! SSW_S1
+ *  0b0..The secure supervisor write access is disabled for the first slave.
+ *  0b1..The secure supervisor write access is enabled for the first slave.
+ */
 #define CSU_CSL_SSW_S1(x)                        (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSW_S1_SHIFT)) & CSU_CSL_SSW_S1_MASK)
 #define CSU_CSL_NUW_S1_MASK                      (0x400000U)
 #define CSU_CSL_NUW_S1_SHIFT                     (22U)
+/*! NUW_S1
+ *  0b0..The non-secure user write access is disabled for the first slave.
+ *  0b1..The non-secure user write access is enabled for the first slave.
+ */
 #define CSU_CSL_NUW_S1(x)                        (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUW_S1_SHIFT)) & CSU_CSL_NUW_S1_MASK)
 #define CSU_CSL_NSW_S1_MASK                      (0x800000U)
 #define CSU_CSL_NSW_S1_SHIFT                     (23U)
+/*! NSW_S1
+ *  0b0..The non-secure supervisor write access is disabled for the first slave.
+ *  0b1..The non-secure supervisor write access is enabled for the first slave
+ */
 #define CSU_CSL_NSW_S1(x)                        (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSW_S1_SHIFT)) & CSU_CSL_NSW_S1_MASK)
 #define CSU_CSL_LOCK_S1_MASK                     (0x1000000U)
 #define CSU_CSL_LOCK_S1_SHIFT                    (24U)
+/*! LOCK_S1
+ *  0b0..Not locked. The bits 16-23 can be written by the software.
+ *  0b1..The bits 16-23 are locked and can't be written by the software.
+ */
 #define CSU_CSL_LOCK_S1(x)                       (((uint32_t)(((uint32_t)(x)) << CSU_CSL_LOCK_S1_SHIFT)) & CSU_CSL_LOCK_S1_MASK)
 /*! @} */
 
@@ -6291,63 +9538,143 @@ typedef struct {
 /*! @{ */
 #define CSU_HP0_HP_DMA_MASK                      (0x4U)
 #define CSU_HP0_HP_DMA_SHIFT                     (2U)
+/*! HP_DMA
+ *  0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master.
+ *  0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master.
+ */
 #define CSU_HP0_HP_DMA(x)                        (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_DMA_SHIFT)) & CSU_HP0_HP_DMA_MASK)
 #define CSU_HP0_L_DMA_MASK                       (0x8U)
 #define CSU_HP0_L_DMA_SHIFT                      (3U)
+/*! L_DMA
+ *  0b0..No lock-the adjacent (next lower) bit can be written by the software.
+ *  0b1..Lock-the adjacent (next lower) bit can't be written by the software.
+ */
 #define CSU_HP0_L_DMA(x)                         (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_DMA_SHIFT)) & CSU_HP0_L_DMA_MASK)
 #define CSU_HP0_HP_LCDIF_MASK                    (0x10U)
 #define CSU_HP0_HP_LCDIF_SHIFT                   (4U)
+/*! HP_LCDIF
+ *  0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master.
+ *  0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master.
+ */
 #define CSU_HP0_HP_LCDIF(x)                      (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_LCDIF_SHIFT)) & CSU_HP0_HP_LCDIF_MASK)
 #define CSU_HP0_L_LCDIF_MASK                     (0x20U)
 #define CSU_HP0_L_LCDIF_SHIFT                    (5U)
+/*! L_LCDIF
+ *  0b0..No lock-the adjacent (next lower) bit can be written by the software.
+ *  0b1..Lock-the adjacent (next lower) bit can't be written by the software.
+ */
 #define CSU_HP0_L_LCDIF(x)                       (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_LCDIF_SHIFT)) & CSU_HP0_L_LCDIF_MASK)
 #define CSU_HP0_HP_CSI_MASK                      (0x40U)
 #define CSU_HP0_HP_CSI_SHIFT                     (6U)
+/*! HP_CSI
+ *  0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master.
+ *  0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master.
+ */
 #define CSU_HP0_HP_CSI(x)                        (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_CSI_SHIFT)) & CSU_HP0_HP_CSI_MASK)
 #define CSU_HP0_L_CSI_MASK                       (0x80U)
 #define CSU_HP0_L_CSI_SHIFT                      (7U)
+/*! L_CSI
+ *  0b0..No lock-the adjacent (next lower) bit can be written by the software.
+ *  0b1..Lock-the adjacent (next lower) bit can't be written by the software.
+ */
 #define CSU_HP0_L_CSI(x)                         (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_CSI_SHIFT)) & CSU_HP0_L_CSI_MASK)
 #define CSU_HP0_HP_PXP_MASK                      (0x100U)
 #define CSU_HP0_HP_PXP_SHIFT                     (8U)
+/*! HP_PXP
+ *  0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master.
+ *  0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master.
+ */
 #define CSU_HP0_HP_PXP(x)                        (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_PXP_SHIFT)) & CSU_HP0_HP_PXP_MASK)
 #define CSU_HP0_L_PXP_MASK                       (0x200U)
 #define CSU_HP0_L_PXP_SHIFT                      (9U)
+/*! L_PXP
+ *  0b0..No lock-the adjacent (next lower) bit can be written by the software.
+ *  0b1..Lock-the adjacent (next lower) bit can't be written by the software.
+ */
 #define CSU_HP0_L_PXP(x)                         (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_PXP_SHIFT)) & CSU_HP0_L_PXP_MASK)
 #define CSU_HP0_HP_DCP_MASK                      (0x400U)
 #define CSU_HP0_HP_DCP_SHIFT                     (10U)
+/*! HP_DCP
+ *  0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master.
+ *  0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master.
+ */
 #define CSU_HP0_HP_DCP(x)                        (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_DCP_SHIFT)) & CSU_HP0_HP_DCP_MASK)
 #define CSU_HP0_L_DCP_MASK                       (0x800U)
 #define CSU_HP0_L_DCP_SHIFT                      (11U)
+/*! L_DCP
+ *  0b0..No lock-the adjacent (next lower) bit can be written by the software.
+ *  0b1..Lock-the adjacent (next lower) bit cannot be written by the software.
+ */
 #define CSU_HP0_L_DCP(x)                         (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_DCP_SHIFT)) & CSU_HP0_L_DCP_MASK)
 #define CSU_HP0_HP_ENET_MASK                     (0x4000U)
 #define CSU_HP0_HP_ENET_SHIFT                    (14U)
+/*! HP_ENET
+ *  0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master.
+ *  0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master.
+ */
 #define CSU_HP0_HP_ENET(x)                       (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_ENET_SHIFT)) & CSU_HP0_HP_ENET_MASK)
 #define CSU_HP0_L_ENET_MASK                      (0x8000U)
 #define CSU_HP0_L_ENET_SHIFT                     (15U)
+/*! L_ENET
+ *  0b0..No lock-the adjacent (next lower) bit can be written by the software.
+ *  0b1..Lock-the adjacent (next lower) bit can't be written by the software.
+ */
 #define CSU_HP0_L_ENET(x)                        (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_ENET_SHIFT)) & CSU_HP0_L_ENET_MASK)
 #define CSU_HP0_HP_USDHC1_MASK                   (0x10000U)
 #define CSU_HP0_HP_USDHC1_SHIFT                  (16U)
+/*! HP_USDHC1
+ *  0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master.
+ *  0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master.
+ */
 #define CSU_HP0_HP_USDHC1(x)                     (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_USDHC1_SHIFT)) & CSU_HP0_HP_USDHC1_MASK)
 #define CSU_HP0_L_USDHC1_MASK                    (0x20000U)
 #define CSU_HP0_L_USDHC1_SHIFT                   (17U)
+/*! L_USDHC1
+ *  0b0..No lock-the adjacent (next lower) bit can be written by the software.
+ *  0b1..Lock-the adjacent (next lower) bit can't be written by the software.
+ */
 #define CSU_HP0_L_USDHC1(x)                      (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_USDHC1_SHIFT)) & CSU_HP0_L_USDHC1_MASK)
 #define CSU_HP0_HP_USDHC2_MASK                   (0x40000U)
 #define CSU_HP0_HP_USDHC2_SHIFT                  (18U)
+/*! HP_USDHC2
+ *  0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master.
+ *  0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master.
+ */
 #define CSU_HP0_HP_USDHC2(x)                     (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_USDHC2_SHIFT)) & CSU_HP0_HP_USDHC2_MASK)
 #define CSU_HP0_L_USDHC2_MASK                    (0x80000U)
 #define CSU_HP0_L_USDHC2_SHIFT                   (19U)
+/*! L_USDHC2
+ *  0b0..No lock-the adjacent (next lower) bit can be written by the software.
+ *  0b1..Lock-the adjacent (next lower) bit can't be written by the software.
+ */
 #define CSU_HP0_L_USDHC2(x)                      (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_USDHC2_SHIFT)) & CSU_HP0_L_USDHC2_MASK)
 #define CSU_HP0_HP_TPSMP_MASK                    (0x100000U)
 #define CSU_HP0_HP_TPSMP_SHIFT                   (20U)
+/*! HP_TPSMP
+ *  0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master.
+ *  0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master.
+ */
 #define CSU_HP0_HP_TPSMP(x)                      (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_TPSMP_SHIFT)) & CSU_HP0_HP_TPSMP_MASK)
 #define CSU_HP0_L_TPSMP_MASK                     (0x200000U)
 #define CSU_HP0_L_TPSMP_SHIFT                    (21U)
+/*! L_TPSMP
+ *  0b0..No lock-the adjacent (next lower) bit can be written by the software.
+ *  0b1..Lock-the adjacent (next lower) bit can't be written by the software.
+ */
 #define CSU_HP0_L_TPSMP(x)                       (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_TPSMP_SHIFT)) & CSU_HP0_L_TPSMP_MASK)
 #define CSU_HP0_HP_USB_MASK                      (0x400000U)
 #define CSU_HP0_HP_USB_SHIFT                     (22U)
+/*! HP_USB
+ *  0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master.
+ *  0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master.
+ */
 #define CSU_HP0_HP_USB(x)                        (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_USB_SHIFT)) & CSU_HP0_HP_USB_MASK)
 #define CSU_HP0_L_USB_MASK                       (0x800000U)
 #define CSU_HP0_L_USB_SHIFT                      (23U)
+/*! L_USB
+ *  0b0..No lock-the adjacent (next lower) bit can be written by the software.
+ *  0b1..Lock-the adjacent (next lower) bit can't be written by the software.
+ */
 #define CSU_HP0_L_USB(x)                         (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_USB_SHIFT)) & CSU_HP0_L_USB_MASK)
 /*! @} */
 
@@ -6355,63 +9682,143 @@ typedef struct {
 /*! @{ */
 #define CSU_SA_NSA_DMA_MASK                      (0x4U)
 #define CSU_SA_NSA_DMA_SHIFT                     (2U)
+/*! NSA_DMA - Non-secure access policy indicator bit
+ *  0b0..Secure access for the corresponding type-1 master
+ *  0b1..Non-secure access for the corresponding type-1 master
+ */
 #define CSU_SA_NSA_DMA(x)                        (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_DMA_SHIFT)) & CSU_SA_NSA_DMA_MASK)
 #define CSU_SA_L_DMA_MASK                        (0x8U)
 #define CSU_SA_L_DMA_SHIFT                       (3U)
+/*! L_DMA
+ *  0b0..No lock-the adjacent (next lower) bit can be written by the software.
+ *  0b1..Lock-the adjacent (next lower) bit can't be written by the software.
+ */
 #define CSU_SA_L_DMA(x)                          (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_DMA_SHIFT)) & CSU_SA_L_DMA_MASK)
 #define CSU_SA_NSA_LCDIF_MASK                    (0x10U)
 #define CSU_SA_NSA_LCDIF_SHIFT                   (4U)
+/*! NSA_LCDIF - Non-secure access policy indicator bit
+ *  0b0..Secure access for the corresponding type-1 master
+ *  0b1..Non-secure access for the corresponding type-1 master
+ */
 #define CSU_SA_NSA_LCDIF(x)                      (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_LCDIF_SHIFT)) & CSU_SA_NSA_LCDIF_MASK)
 #define CSU_SA_L_LCDIF_MASK                      (0x20U)
 #define CSU_SA_L_LCDIF_SHIFT                     (5U)
+/*! L_LCDIF
+ *  0b0..No lock-the adjacent (next lower) bit can be written by the software.
+ *  0b1..Lock-the adjacent (next lower) bit can't be written by the software.
+ */
 #define CSU_SA_L_LCDIF(x)                        (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_LCDIF_SHIFT)) & CSU_SA_L_LCDIF_MASK)
 #define CSU_SA_NSA_CSI_MASK                      (0x40U)
 #define CSU_SA_NSA_CSI_SHIFT                     (6U)
+/*! NSA_CSI - Non-secure access policy indicator bit
+ *  0b0..Secure access for the corresponding type-1 master
+ *  0b1..Non-secure access for the corresponding type-1 master
+ */
 #define CSU_SA_NSA_CSI(x)                        (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_CSI_SHIFT)) & CSU_SA_NSA_CSI_MASK)
 #define CSU_SA_L_CSI_MASK                        (0x80U)
 #define CSU_SA_L_CSI_SHIFT                       (7U)
+/*! L_CSI
+ *  0b0..No lock-the adjacent (next lower) bit can be written by the software.
+ *  0b1..Lock-the adjacent (next lower) bit can't be written by the software.
+ */
 #define CSU_SA_L_CSI(x)                          (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_CSI_SHIFT)) & CSU_SA_L_CSI_MASK)
 #define CSU_SA_NSA_PXP_MASK                      (0x100U)
 #define CSU_SA_NSA_PXP_SHIFT                     (8U)
+/*! NSA_PXP - Non-Secure Access Policy indicator bit
+ *  0b0..Secure access for the corresponding type-1 master
+ *  0b1..Non-secure access for the corresponding type-1 master
+ */
 #define CSU_SA_NSA_PXP(x)                        (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_PXP_SHIFT)) & CSU_SA_NSA_PXP_MASK)
 #define CSU_SA_L_PXP_MASK                        (0x200U)
 #define CSU_SA_L_PXP_SHIFT                       (9U)
+/*! L_PXP
+ *  0b0..No lock-the adjacent (next lower) bit can be written by the software.
+ *  0b1..Lock-the adjacent (next lower) bit can't be written by the software.
+ */
 #define CSU_SA_L_PXP(x)                          (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_PXP_SHIFT)) & CSU_SA_L_PXP_MASK)
 #define CSU_SA_NSA_DCP_MASK                      (0x400U)
 #define CSU_SA_NSA_DCP_SHIFT                     (10U)
+/*! NSA_DCP - Non-secure access policy indicator bit
+ *  0b0..Secure access for the corresponding type-1 master
+ *  0b1..Non-secure access for the corresponding type-1 master
+ */
 #define CSU_SA_NSA_DCP(x)                        (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_DCP_SHIFT)) & CSU_SA_NSA_DCP_MASK)
 #define CSU_SA_L_DCP_MASK                        (0x800U)
 #define CSU_SA_L_DCP_SHIFT                       (11U)
+/*! L_DCP
+ *  0b0..No lock-the adjacent (next lower) bit can be written by the software.
+ *  0b1..Lock-the adjacent (next lower) bit can't be written by the software.
+ */
 #define CSU_SA_L_DCP(x)                          (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_DCP_SHIFT)) & CSU_SA_L_DCP_MASK)
 #define CSU_SA_NSA_ENET_MASK                     (0x4000U)
 #define CSU_SA_NSA_ENET_SHIFT                    (14U)
+/*! NSA_ENET - Non-secure access policy indicator bit
+ *  0b0..Secure access for the corresponding type-1 master
+ *  0b1..Non-secure access for the corresponding type-1 master
+ */
 #define CSU_SA_NSA_ENET(x)                       (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_ENET_SHIFT)) & CSU_SA_NSA_ENET_MASK)
 #define CSU_SA_L_ENET_MASK                       (0x8000U)
 #define CSU_SA_L_ENET_SHIFT                      (15U)
+/*! L_ENET
+ *  0b0..No lock-the adjacent (next lower) bit can be written by the software.
+ *  0b1..Lock-the adjacent (next lower) bit can't be written by the software.
+ */
 #define CSU_SA_L_ENET(x)                         (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_ENET_SHIFT)) & CSU_SA_L_ENET_MASK)
 #define CSU_SA_NSA_USDHC1_MASK                   (0x10000U)
 #define CSU_SA_NSA_USDHC1_SHIFT                  (16U)
+/*! NSA_USDHC1 - Non-secure access policy indicator bit
+ *  0b0..Secure access for the corresponding type-1 master
+ *  0b1..Non-secure access for the corresponding type-1 master
+ */
 #define CSU_SA_NSA_USDHC1(x)                     (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_USDHC1_SHIFT)) & CSU_SA_NSA_USDHC1_MASK)
 #define CSU_SA_L_USDHC1_MASK                     (0x20000U)
 #define CSU_SA_L_USDHC1_SHIFT                    (17U)
+/*! L_USDHC1
+ *  0b0..No lock-the adjacent (next lower) bit can be written by the software.
+ *  0b1..Lock-the adjacent (next lower) bit can't be written by the software.
+ */
 #define CSU_SA_L_USDHC1(x)                       (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_USDHC1_SHIFT)) & CSU_SA_L_USDHC1_MASK)
 #define CSU_SA_NSA_USDHC2_MASK                   (0x40000U)
 #define CSU_SA_NSA_USDHC2_SHIFT                  (18U)
+/*! NSA_USDHC2 - Non-secure access policy indicator bit
+ *  0b0..Secure access for the corresponding type-1 master
+ *  0b1..Non-secure access for the corresponding type-1 master
+ */
 #define CSU_SA_NSA_USDHC2(x)                     (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_USDHC2_SHIFT)) & CSU_SA_NSA_USDHC2_MASK)
 #define CSU_SA_L_USDHC2_MASK                     (0x80000U)
 #define CSU_SA_L_USDHC2_SHIFT                    (19U)
+/*! L_USDHC2
+ *  0b0..No lock-the adjacent (next lower) bit can be written by the software.
+ *  0b1..Lock-the adjacent (next lower) bit can't be written by the software.
+ */
 #define CSU_SA_L_USDHC2(x)                       (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_USDHC2_SHIFT)) & CSU_SA_L_USDHC2_MASK)
 #define CSU_SA_NSA_TPSMP_MASK                    (0x100000U)
 #define CSU_SA_NSA_TPSMP_SHIFT                   (20U)
+/*! NSA_TPSMP - Non-secure access policy indicator bit
+ *  0b0..Secure access for the corresponding type-1 master
+ *  0b1..Non-secure access for the corresponding type-1 master
+ */
 #define CSU_SA_NSA_TPSMP(x)                      (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_TPSMP_SHIFT)) & CSU_SA_NSA_TPSMP_MASK)
 #define CSU_SA_L_TPSMP_MASK                      (0x200000U)
 #define CSU_SA_L_TPSMP_SHIFT                     (21U)
+/*! L_TPSMP
+ *  0b0..No lock-the adjacent (next lower) bit can be written by the software.
+ *  0b1..Lock-the adjacent (next lower) bit can't be written by the software.
+ */
 #define CSU_SA_L_TPSMP(x)                        (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_TPSMP_SHIFT)) & CSU_SA_L_TPSMP_MASK)
 #define CSU_SA_NSA_USB_MASK                      (0x400000U)
 #define CSU_SA_NSA_USB_SHIFT                     (22U)
+/*! NSA_USB - Non-secure access policy indicator bit
+ *  0b0..Secure access for the corresponding type-1 master
+ *  0b1..Non-secure access for the corresponding type-1 master
+ */
 #define CSU_SA_NSA_USB(x)                        (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_USB_SHIFT)) & CSU_SA_NSA_USB_MASK)
 #define CSU_SA_L_USB_MASK                        (0x800000U)
 #define CSU_SA_L_USB_SHIFT                       (23U)
+/*! L_USB
+ *  0b0..No lock-the adjacent (next lower) bit can be written by the software.
+ *  0b1..Lock-the adjacent (next lower) bit can't be written by the software.
+ */
 #define CSU_SA_L_USB(x)                          (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_USB_SHIFT)) & CSU_SA_L_USB_MASK)
 /*! @} */
 
@@ -6419,63 +9826,143 @@ typedef struct {
 /*! @{ */
 #define CSU_HPCONTROL0_HPC_DMA_MASK              (0x4U)
 #define CSU_HPCONTROL0_HPC_DMA_SHIFT             (2U)
+/*! HPC_DMA
+ *  0b0..User mode for the corresponding master
+ *  0b1..Supervisor mode for the corresponding master
+ */
 #define CSU_HPCONTROL0_HPC_DMA(x)                (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_DMA_SHIFT)) & CSU_HPCONTROL0_HPC_DMA_MASK)
 #define CSU_HPCONTROL0_L_DMA_MASK                (0x8U)
 #define CSU_HPCONTROL0_L_DMA_SHIFT               (3U)
+/*! L_DMA
+ *  0b0..No lock-the adjacent (next lower) bit can be written by the software.
+ *  0b1..Lock-the adjacent (next lower) bit can't be written by the software.
+ */
 #define CSU_HPCONTROL0_L_DMA(x)                  (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_DMA_SHIFT)) & CSU_HPCONTROL0_L_DMA_MASK)
 #define CSU_HPCONTROL0_HPC_LCDIF_MASK            (0x10U)
 #define CSU_HPCONTROL0_HPC_LCDIF_SHIFT           (4U)
+/*! HPC_LCDIF
+ *  0b0..User mode for the corresponding master
+ *  0b1..Supervisor mode for the corresponding master
+ */
 #define CSU_HPCONTROL0_HPC_LCDIF(x)              (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_LCDIF_SHIFT)) & CSU_HPCONTROL0_HPC_LCDIF_MASK)
 #define CSU_HPCONTROL0_L_LCDIF_MASK              (0x20U)
 #define CSU_HPCONTROL0_L_LCDIF_SHIFT             (5U)
+/*! L_LCDIF
+ *  0b0..No lock-the adjacent (next lower) bit can be written by the software.
+ *  0b1..Lock-the adjacent (next lower) bit can't be written by the software.
+ */
 #define CSU_HPCONTROL0_L_LCDIF(x)                (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_LCDIF_SHIFT)) & CSU_HPCONTROL0_L_LCDIF_MASK)
 #define CSU_HPCONTROL0_HPC_CSI_MASK              (0x40U)
 #define CSU_HPCONTROL0_HPC_CSI_SHIFT             (6U)
+/*! HPC_CSI
+ *  0b0..User mode for the corresponding master
+ *  0b1..Supervisor mode for the corresponding master
+ */
 #define CSU_HPCONTROL0_HPC_CSI(x)                (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_CSI_SHIFT)) & CSU_HPCONTROL0_HPC_CSI_MASK)
 #define CSU_HPCONTROL0_L_CSI_MASK                (0x80U)
 #define CSU_HPCONTROL0_L_CSI_SHIFT               (7U)
+/*! L_CSI
+ *  0b0..No lock-the adjacent (next lower) bit can be written by the software.
+ *  0b1..Lock-the adjacent (next lower) bit can't be written by the software.
+ */
 #define CSU_HPCONTROL0_L_CSI(x)                  (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_CSI_SHIFT)) & CSU_HPCONTROL0_L_CSI_MASK)
 #define CSU_HPCONTROL0_HPC_PXP_MASK              (0x100U)
 #define CSU_HPCONTROL0_HPC_PXP_SHIFT             (8U)
+/*! HPC_PXP
+ *  0b0..User mode for the corresponding master
+ *  0b1..Supervisor mode for the corresponding master
+ */
 #define CSU_HPCONTROL0_HPC_PXP(x)                (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_PXP_SHIFT)) & CSU_HPCONTROL0_HPC_PXP_MASK)
 #define CSU_HPCONTROL0_L_PXP_MASK                (0x200U)
 #define CSU_HPCONTROL0_L_PXP_SHIFT               (9U)
+/*! L_PXP
+ *  0b0..No lock-the adjacent (next lower) bit can be written by the software.
+ *  0b1..Lock-the adjacent (next lower) bit can't be written by the software.
+ */
 #define CSU_HPCONTROL0_L_PXP(x)                  (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_PXP_SHIFT)) & CSU_HPCONTROL0_L_PXP_MASK)
 #define CSU_HPCONTROL0_HPC_DCP_MASK              (0x400U)
 #define CSU_HPCONTROL0_HPC_DCP_SHIFT             (10U)
+/*! HPC_DCP
+ *  0b0..User mode for the corresponding master
+ *  0b1..Supervisor mode for the corresponding master
+ */
 #define CSU_HPCONTROL0_HPC_DCP(x)                (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_DCP_SHIFT)) & CSU_HPCONTROL0_HPC_DCP_MASK)
 #define CSU_HPCONTROL0_L_DCP_MASK                (0x800U)
 #define CSU_HPCONTROL0_L_DCP_SHIFT               (11U)
+/*! L_DCP
+ *  0b0..No lock-the adjacent (next lower) bit can be written by the software.
+ *  0b1..Lock-the adjacent (next lower) bit can't be written by the software.
+ */
 #define CSU_HPCONTROL0_L_DCP(x)                  (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_DCP_SHIFT)) & CSU_HPCONTROL0_L_DCP_MASK)
 #define CSU_HPCONTROL0_HPC_ENET_MASK             (0x4000U)
 #define CSU_HPCONTROL0_HPC_ENET_SHIFT            (14U)
+/*! HPC_ENET
+ *  0b0..User mode for the corresponding master
+ *  0b1..Supervisor mode for the corresponding master
+ */
 #define CSU_HPCONTROL0_HPC_ENET(x)               (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_ENET_SHIFT)) & CSU_HPCONTROL0_HPC_ENET_MASK)
 #define CSU_HPCONTROL0_L_ENET_MASK               (0x8000U)
 #define CSU_HPCONTROL0_L_ENET_SHIFT              (15U)
+/*! L_ENET
+ *  0b0..No lock-the adjacent (next lower) bit can be written by the software.
+ *  0b1..Lock-the adjacent (next lower) bit can't be written by the software.
+ */
 #define CSU_HPCONTROL0_L_ENET(x)                 (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_ENET_SHIFT)) & CSU_HPCONTROL0_L_ENET_MASK)
 #define CSU_HPCONTROL0_HPC_USDHC1_MASK           (0x10000U)
 #define CSU_HPCONTROL0_HPC_USDHC1_SHIFT          (16U)
+/*! HPC_USDHC1
+ *  0b0..User mode for the corresponding master
+ *  0b1..Supervisor mode for the corresponding master
+ */
 #define CSU_HPCONTROL0_HPC_USDHC1(x)             (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_USDHC1_SHIFT)) & CSU_HPCONTROL0_HPC_USDHC1_MASK)
 #define CSU_HPCONTROL0_L_USDHC1_MASK             (0x20000U)
 #define CSU_HPCONTROL0_L_USDHC1_SHIFT            (17U)
+/*! L_USDHC1
+ *  0b0..No lock-the adjacent (next lower) bit can be written by the software.
+ *  0b1..Lock-the adjacent (next lower) bit can't be written by the software.
+ */
 #define CSU_HPCONTROL0_L_USDHC1(x)               (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_USDHC1_SHIFT)) & CSU_HPCONTROL0_L_USDHC1_MASK)
 #define CSU_HPCONTROL0_HPC_USDHC2_MASK           (0x40000U)
 #define CSU_HPCONTROL0_HPC_USDHC2_SHIFT          (18U)
+/*! HPC_USDHC2
+ *  0b0..User mode for the corresponding master
+ *  0b1..Supervisor mode for the corresponding master
+ */
 #define CSU_HPCONTROL0_HPC_USDHC2(x)             (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_USDHC2_SHIFT)) & CSU_HPCONTROL0_HPC_USDHC2_MASK)
 #define CSU_HPCONTROL0_L_USDHC2_MASK             (0x80000U)
 #define CSU_HPCONTROL0_L_USDHC2_SHIFT            (19U)
+/*! L_USDHC2
+ *  0b0..No lock-the adjacent (next lower) bit can be written by the software.
+ *  0b1..Lock-the adjacent (next lower) bit can't be written by the software.
+ */
 #define CSU_HPCONTROL0_L_USDHC2(x)               (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_USDHC2_SHIFT)) & CSU_HPCONTROL0_L_USDHC2_MASK)
 #define CSU_HPCONTROL0_HPC_TPSMP_MASK            (0x100000U)
 #define CSU_HPCONTROL0_HPC_TPSMP_SHIFT           (20U)
+/*! HPC_TPSMP
+ *  0b0..User mode for the corresponding master
+ *  0b1..Supervisor mode for the corresponding master
+ */
 #define CSU_HPCONTROL0_HPC_TPSMP(x)              (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_TPSMP_SHIFT)) & CSU_HPCONTROL0_HPC_TPSMP_MASK)
 #define CSU_HPCONTROL0_L_TPSMP_MASK              (0x200000U)
 #define CSU_HPCONTROL0_L_TPSMP_SHIFT             (21U)
+/*! L_TPSMP
+ *  0b0..No lock-the adjacent (next lower) bit can be written by the software.
+ *  0b1..Lock-the adjacent (next lower) bit can't be written by the software.
+ */
 #define CSU_HPCONTROL0_L_TPSMP(x)                (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_TPSMP_SHIFT)) & CSU_HPCONTROL0_L_TPSMP_MASK)
 #define CSU_HPCONTROL0_HPC_USB_MASK              (0x400000U)
 #define CSU_HPCONTROL0_HPC_USB_SHIFT             (22U)
+/*! HPC_USB
+ *  0b0..User mode for the corresponding master
+ *  0b1..Supervisor mode for the corresponding master
+ */
 #define CSU_HPCONTROL0_HPC_USB(x)                (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_USB_SHIFT)) & CSU_HPCONTROL0_HPC_USB_MASK)
 #define CSU_HPCONTROL0_L_USB_MASK                (0x800000U)
 #define CSU_HPCONTROL0_L_USB_SHIFT               (23U)
+/*! L_USB
+ *  0b0..No lock-the adjacent (next lower) bit can be written by the software.
+ *  0b1..Lock-the adjacent (next lower) bit can't be written by the software.
+ */
 #define CSU_HPCONTROL0_L_USB(x)                  (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_USB_SHIFT)) & CSU_HPCONTROL0_L_USB_MASK)
 /*! @} */
 
@@ -6697,73 +10184,96 @@ typedef struct {
 /** DCP - Register Layout Typedef */
 typedef struct {
   __IO uint32_t CTRL;                              /**< DCP control register 0, offset: 0x0 */
-       uint8_t RESERVED_0[12];
+  __IO uint32_t CTRL_SET;                          /**< DCP control register 0, offset: 0x4 */
+  __IO uint32_t CTRL_CLR;                          /**< DCP control register 0, offset: 0x8 */
+  __IO uint32_t CTRL_TOG;                          /**< DCP control register 0, offset: 0xC */
   __IO uint32_t STAT;                              /**< DCP status register, offset: 0x10 */
-       uint8_t RESERVED_1[12];
+  __IO uint32_t STAT_SET;                          /**< DCP status register, offset: 0x14 */
+  __IO uint32_t STAT_CLR;                          /**< DCP status register, offset: 0x18 */
+  __IO uint32_t STAT_TOG;                          /**< DCP status register, offset: 0x1C */
   __IO uint32_t CHANNELCTRL;                       /**< DCP channel control register, offset: 0x20 */
-       uint8_t RESERVED_2[12];
+  __IO uint32_t CHANNELCTRL_SET;                   /**< DCP channel control register, offset: 0x24 */
+  __IO uint32_t CHANNELCTRL_CLR;                   /**< DCP channel control register, offset: 0x28 */
+  __IO uint32_t CHANNELCTRL_TOG;                   /**< DCP channel control register, offset: 0x2C */
   __IO uint32_t CAPABILITY0;                       /**< DCP capability 0 register, offset: 0x30 */
-       uint8_t RESERVED_3[12];
+       uint8_t RESERVED_0[12];
   __I  uint32_t CAPABILITY1;                       /**< DCP capability 1 register, offset: 0x40 */
-       uint8_t RESERVED_4[12];
+       uint8_t RESERVED_1[12];
   __IO uint32_t CONTEXT;                           /**< DCP context buffer pointer, offset: 0x50 */
-       uint8_t RESERVED_5[12];
+       uint8_t RESERVED_2[12];
   __IO uint32_t KEY;                               /**< DCP key index, offset: 0x60 */
-       uint8_t RESERVED_6[12];
+       uint8_t RESERVED_3[12];
   __IO uint32_t KEYDATA;                           /**< DCP key data, offset: 0x70 */
-       uint8_t RESERVED_7[12];
+       uint8_t RESERVED_4[12];
   __I  uint32_t PACKET0;                           /**< DCP work packet 0 status register, offset: 0x80 */
-       uint8_t RESERVED_8[12];
+       uint8_t RESERVED_5[12];
   __I  uint32_t PACKET1;                           /**< DCP work packet 1 status register, offset: 0x90 */
-       uint8_t RESERVED_9[12];
+       uint8_t RESERVED_6[12];
   __I  uint32_t PACKET2;                           /**< DCP work packet 2 status register, offset: 0xA0 */
-       uint8_t RESERVED_10[12];
+       uint8_t RESERVED_7[12];
   __I  uint32_t PACKET3;                           /**< DCP work packet 3 status register, offset: 0xB0 */
-       uint8_t RESERVED_11[12];
+       uint8_t RESERVED_8[12];
   __I  uint32_t PACKET4;                           /**< DCP work packet 4 status register, offset: 0xC0 */
-       uint8_t RESERVED_12[12];
+       uint8_t RESERVED_9[12];
   __I  uint32_t PACKET5;                           /**< DCP work packet 5 status register, offset: 0xD0 */
-       uint8_t RESERVED_13[12];
+       uint8_t RESERVED_10[12];
   __I  uint32_t PACKET6;                           /**< DCP work packet 6 status register, offset: 0xE0 */
-       uint8_t RESERVED_14[28];
+       uint8_t RESERVED_11[28];
   __IO uint32_t CH0CMDPTR;                         /**< DCP channel 0 command pointer address register, offset: 0x100 */
-       uint8_t RESERVED_15[12];
+       uint8_t RESERVED_12[12];
   __IO uint32_t CH0SEMA;                           /**< DCP channel 0 semaphore register, offset: 0x110 */
-       uint8_t RESERVED_16[12];
+       uint8_t RESERVED_13[12];
   __IO uint32_t CH0STAT;                           /**< DCP channel 0 status register, offset: 0x120 */
-       uint8_t RESERVED_17[12];
+  __IO uint32_t CH0STAT_SET;                       /**< DCP channel 0 status register, offset: 0x124 */
+  __IO uint32_t CH0STAT_CLR;                       /**< DCP channel 0 status register, offset: 0x128 */
+  __IO uint32_t CH0STAT_TOG;                       /**< DCP channel 0 status register, offset: 0x12C */
   __IO uint32_t CH0OPTS;                           /**< DCP channel 0 options register, offset: 0x130 */
-       uint8_t RESERVED_18[12];
+  __IO uint32_t CH0OPTS_SET;                       /**< DCP channel 0 options register, offset: 0x134 */
+  __IO uint32_t CH0OPTS_CLR;                       /**< DCP channel 0 options register, offset: 0x138 */
+  __IO uint32_t CH0OPTS_TOG;                       /**< DCP channel 0 options register, offset: 0x13C */
   __IO uint32_t CH1CMDPTR;                         /**< DCP channel 1 command pointer address register, offset: 0x140 */
-       uint8_t RESERVED_19[12];
+       uint8_t RESERVED_14[12];
   __IO uint32_t CH1SEMA;                           /**< DCP channel 1 semaphore register, offset: 0x150 */
-       uint8_t RESERVED_20[12];
+       uint8_t RESERVED_15[12];
   __IO uint32_t CH1STAT;                           /**< DCP channel 1 status register, offset: 0x160 */
-       uint8_t RESERVED_21[12];
+  __IO uint32_t CH1STAT_SET;                       /**< DCP channel 1 status register, offset: 0x164 */
+  __IO uint32_t CH1STAT_CLR;                       /**< DCP channel 1 status register, offset: 0x168 */
+  __IO uint32_t CH1STAT_TOG;                       /**< DCP channel 1 status register, offset: 0x16C */
   __IO uint32_t CH1OPTS;                           /**< DCP channel 1 options register, offset: 0x170 */
-       uint8_t RESERVED_22[12];
+  __IO uint32_t CH1OPTS_SET;                       /**< DCP channel 1 options register, offset: 0x174 */
+  __IO uint32_t CH1OPTS_CLR;                       /**< DCP channel 1 options register, offset: 0x178 */
+  __IO uint32_t CH1OPTS_TOG;                       /**< DCP channel 1 options register, offset: 0x17C */
   __IO uint32_t CH2CMDPTR;                         /**< DCP channel 2 command pointer address register, offset: 0x180 */
-       uint8_t RESERVED_23[12];
+       uint8_t RESERVED_16[12];
   __IO uint32_t CH2SEMA;                           /**< DCP channel 2 semaphore register, offset: 0x190 */
-       uint8_t RESERVED_24[12];
+       uint8_t RESERVED_17[12];
   __IO uint32_t CH2STAT;                           /**< DCP channel 2 status register, offset: 0x1A0 */
-       uint8_t RESERVED_25[12];
+  __IO uint32_t CH2STAT_SET;                       /**< DCP channel 2 status register, offset: 0x1A4 */
+  __IO uint32_t CH2STAT_CLR;                       /**< DCP channel 2 status register, offset: 0x1A8 */
+  __IO uint32_t CH2STAT_TOG;                       /**< DCP channel 2 status register, offset: 0x1AC */
   __IO uint32_t CH2OPTS;                           /**< DCP channel 2 options register, offset: 0x1B0 */
-       uint8_t RESERVED_26[12];
+  __IO uint32_t CH2OPTS_SET;                       /**< DCP channel 2 options register, offset: 0x1B4 */
+  __IO uint32_t CH2OPTS_CLR;                       /**< DCP channel 2 options register, offset: 0x1B8 */
+  __IO uint32_t CH2OPTS_TOG;                       /**< DCP channel 2 options register, offset: 0x1BC */
   __IO uint32_t CH3CMDPTR;                         /**< DCP channel 3 command pointer address register, offset: 0x1C0 */
-       uint8_t RESERVED_27[12];
+       uint8_t RESERVED_18[12];
   __IO uint32_t CH3SEMA;                           /**< DCP channel 3 semaphore register, offset: 0x1D0 */
-       uint8_t RESERVED_28[12];
+       uint8_t RESERVED_19[12];
   __IO uint32_t CH3STAT;                           /**< DCP channel 3 status register, offset: 0x1E0 */
-       uint8_t RESERVED_29[12];
+  __IO uint32_t CH3STAT_SET;                       /**< DCP channel 3 status register, offset: 0x1E4 */
+  __IO uint32_t CH3STAT_CLR;                       /**< DCP channel 3 status register, offset: 0x1E8 */
+  __IO uint32_t CH3STAT_TOG;                       /**< DCP channel 3 status register, offset: 0x1EC */
   __IO uint32_t CH3OPTS;                           /**< DCP channel 3 options register, offset: 0x1F0 */
-       uint8_t RESERVED_30[524];
+  __IO uint32_t CH3OPTS_SET;                       /**< DCP channel 3 options register, offset: 0x1F4 */
+  __IO uint32_t CH3OPTS_CLR;                       /**< DCP channel 3 options register, offset: 0x1F8 */
+  __IO uint32_t CH3OPTS_TOG;                       /**< DCP channel 3 options register, offset: 0x1FC */
+       uint8_t RESERVED_20[512];
   __IO uint32_t DBGSELECT;                         /**< DCP debug select register, offset: 0x400 */
-       uint8_t RESERVED_31[12];
+       uint8_t RESERVED_21[12];
   __I  uint32_t DBGDATA;                           /**< DCP debug data register, offset: 0x410 */
-       uint8_t RESERVED_32[12];
+       uint8_t RESERVED_22[12];
   __IO uint32_t PAGETABLE;                         /**< DCP page table register, offset: 0x420 */
-       uint8_t RESERVED_33[12];
+       uint8_t RESERVED_23[12];
   __I  uint32_t VERSION;                           /**< DCP version register, offset: 0x430 */
 } DCP_Type;
 
@@ -6780,6 +10290,12 @@ typedef struct {
 /*! @{ */
 #define DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_MASK   (0xFFU)
 #define DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_SHIFT  (0U)
+/*! CHANNEL_INTERRUPT_ENABLE
+ *  0b00000001..CH0
+ *  0b00000010..CH1
+ *  0b00000100..CH2
+ *  0b00001000..CH3
+ */
 #define DCP_CTRL_CHANNEL_INTERRUPT_ENABLE(x)     (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_MASK)
 #define DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE_MASK  (0x100U)
 #define DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE_SHIFT (8U)
@@ -6795,9 +10311,17 @@ typedef struct {
 #define DCP_CTRL_GATHER_RESIDUAL_WRITES(x)       (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_GATHER_RESIDUAL_WRITES_SHIFT)) & DCP_CTRL_GATHER_RESIDUAL_WRITES_MASK)
 #define DCP_CTRL_PRESENT_SHA_MASK                (0x10000000U)
 #define DCP_CTRL_PRESENT_SHA_SHIFT               (28U)
+/*! PRESENT_SHA
+ *  0b1..Present
+ *  0b0..Absent
+ */
 #define DCP_CTRL_PRESENT_SHA(x)                  (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_PRESENT_SHA_SHIFT)) & DCP_CTRL_PRESENT_SHA_MASK)
 #define DCP_CTRL_PRESENT_CRYPTO_MASK             (0x20000000U)
 #define DCP_CTRL_PRESENT_CRYPTO_SHIFT            (29U)
+/*! PRESENT_CRYPTO
+ *  0b1..Present
+ *  0b0..Absent
+ */
 #define DCP_CTRL_PRESENT_CRYPTO(x)               (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_PRESENT_CRYPTO_SHIFT)) & DCP_CTRL_PRESENT_CRYPTO_MASK)
 #define DCP_CTRL_CLKGATE_MASK                    (0x40000000U)
 #define DCP_CTRL_CLKGATE_SHIFT                   (30U)
@@ -6807,6 +10331,141 @@ typedef struct {
 #define DCP_CTRL_SFTRST(x)                       (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SFTRST_SHIFT)) & DCP_CTRL_SFTRST_MASK)
 /*! @} */
 
+/*! @name CTRL_SET - DCP control register 0 */
+/*! @{ */
+#define DCP_CTRL_SET_CHANNEL_INTERRUPT_ENABLE_MASK (0xFFU)
+#define DCP_CTRL_SET_CHANNEL_INTERRUPT_ENABLE_SHIFT (0U)
+/*! CHANNEL_INTERRUPT_ENABLE
+ *  0b00000001..CH0
+ *  0b00000010..CH1
+ *  0b00000100..CH2
+ *  0b00001000..CH3
+ */
+#define DCP_CTRL_SET_CHANNEL_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_CHANNEL_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_SET_CHANNEL_INTERRUPT_ENABLE_MASK)
+#define DCP_CTRL_SET_RSVD_CSC_INTERRUPT_ENABLE_MASK (0x100U)
+#define DCP_CTRL_SET_RSVD_CSC_INTERRUPT_ENABLE_SHIFT (8U)
+#define DCP_CTRL_SET_RSVD_CSC_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_RSVD_CSC_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_SET_RSVD_CSC_INTERRUPT_ENABLE_MASK)
+#define DCP_CTRL_SET_ENABLE_CONTEXT_SWITCHING_MASK (0x200000U)
+#define DCP_CTRL_SET_ENABLE_CONTEXT_SWITCHING_SHIFT (21U)
+#define DCP_CTRL_SET_ENABLE_CONTEXT_SWITCHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_ENABLE_CONTEXT_SWITCHING_SHIFT)) & DCP_CTRL_SET_ENABLE_CONTEXT_SWITCHING_MASK)
+#define DCP_CTRL_SET_ENABLE_CONTEXT_CACHING_MASK (0x400000U)
+#define DCP_CTRL_SET_ENABLE_CONTEXT_CACHING_SHIFT (22U)
+#define DCP_CTRL_SET_ENABLE_CONTEXT_CACHING(x)   (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_ENABLE_CONTEXT_CACHING_SHIFT)) & DCP_CTRL_SET_ENABLE_CONTEXT_CACHING_MASK)
+#define DCP_CTRL_SET_GATHER_RESIDUAL_WRITES_MASK (0x800000U)
+#define DCP_CTRL_SET_GATHER_RESIDUAL_WRITES_SHIFT (23U)
+#define DCP_CTRL_SET_GATHER_RESIDUAL_WRITES(x)   (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_GATHER_RESIDUAL_WRITES_SHIFT)) & DCP_CTRL_SET_GATHER_RESIDUAL_WRITES_MASK)
+#define DCP_CTRL_SET_PRESENT_SHA_MASK            (0x10000000U)
+#define DCP_CTRL_SET_PRESENT_SHA_SHIFT           (28U)
+/*! PRESENT_SHA
+ *  0b1..Present
+ *  0b0..Absent
+ */
+#define DCP_CTRL_SET_PRESENT_SHA(x)              (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_PRESENT_SHA_SHIFT)) & DCP_CTRL_SET_PRESENT_SHA_MASK)
+#define DCP_CTRL_SET_PRESENT_CRYPTO_MASK         (0x20000000U)
+#define DCP_CTRL_SET_PRESENT_CRYPTO_SHIFT        (29U)
+/*! PRESENT_CRYPTO
+ *  0b1..Present
+ *  0b0..Absent
+ */
+#define DCP_CTRL_SET_PRESENT_CRYPTO(x)           (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_PRESENT_CRYPTO_SHIFT)) & DCP_CTRL_SET_PRESENT_CRYPTO_MASK)
+#define DCP_CTRL_SET_CLKGATE_MASK                (0x40000000U)
+#define DCP_CTRL_SET_CLKGATE_SHIFT               (30U)
+#define DCP_CTRL_SET_CLKGATE(x)                  (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_CLKGATE_SHIFT)) & DCP_CTRL_SET_CLKGATE_MASK)
+#define DCP_CTRL_SET_SFTRST_MASK                 (0x80000000U)
+#define DCP_CTRL_SET_SFTRST_SHIFT                (31U)
+#define DCP_CTRL_SET_SFTRST(x)                   (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_SFTRST_SHIFT)) & DCP_CTRL_SET_SFTRST_MASK)
+/*! @} */
+
+/*! @name CTRL_CLR - DCP control register 0 */
+/*! @{ */
+#define DCP_CTRL_CLR_CHANNEL_INTERRUPT_ENABLE_MASK (0xFFU)
+#define DCP_CTRL_CLR_CHANNEL_INTERRUPT_ENABLE_SHIFT (0U)
+/*! CHANNEL_INTERRUPT_ENABLE
+ *  0b00000001..CH0
+ *  0b00000010..CH1
+ *  0b00000100..CH2
+ *  0b00001000..CH3
+ */
+#define DCP_CTRL_CLR_CHANNEL_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_CHANNEL_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_CLR_CHANNEL_INTERRUPT_ENABLE_MASK)
+#define DCP_CTRL_CLR_RSVD_CSC_INTERRUPT_ENABLE_MASK (0x100U)
+#define DCP_CTRL_CLR_RSVD_CSC_INTERRUPT_ENABLE_SHIFT (8U)
+#define DCP_CTRL_CLR_RSVD_CSC_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_RSVD_CSC_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_CLR_RSVD_CSC_INTERRUPT_ENABLE_MASK)
+#define DCP_CTRL_CLR_ENABLE_CONTEXT_SWITCHING_MASK (0x200000U)
+#define DCP_CTRL_CLR_ENABLE_CONTEXT_SWITCHING_SHIFT (21U)
+#define DCP_CTRL_CLR_ENABLE_CONTEXT_SWITCHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_ENABLE_CONTEXT_SWITCHING_SHIFT)) & DCP_CTRL_CLR_ENABLE_CONTEXT_SWITCHING_MASK)
+#define DCP_CTRL_CLR_ENABLE_CONTEXT_CACHING_MASK (0x400000U)
+#define DCP_CTRL_CLR_ENABLE_CONTEXT_CACHING_SHIFT (22U)
+#define DCP_CTRL_CLR_ENABLE_CONTEXT_CACHING(x)   (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_ENABLE_CONTEXT_CACHING_SHIFT)) & DCP_CTRL_CLR_ENABLE_CONTEXT_CACHING_MASK)
+#define DCP_CTRL_CLR_GATHER_RESIDUAL_WRITES_MASK (0x800000U)
+#define DCP_CTRL_CLR_GATHER_RESIDUAL_WRITES_SHIFT (23U)
+#define DCP_CTRL_CLR_GATHER_RESIDUAL_WRITES(x)   (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_GATHER_RESIDUAL_WRITES_SHIFT)) & DCP_CTRL_CLR_GATHER_RESIDUAL_WRITES_MASK)
+#define DCP_CTRL_CLR_PRESENT_SHA_MASK            (0x10000000U)
+#define DCP_CTRL_CLR_PRESENT_SHA_SHIFT           (28U)
+/*! PRESENT_SHA
+ *  0b1..Present
+ *  0b0..Absent
+ */
+#define DCP_CTRL_CLR_PRESENT_SHA(x)              (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_PRESENT_SHA_SHIFT)) & DCP_CTRL_CLR_PRESENT_SHA_MASK)
+#define DCP_CTRL_CLR_PRESENT_CRYPTO_MASK         (0x20000000U)
+#define DCP_CTRL_CLR_PRESENT_CRYPTO_SHIFT        (29U)
+/*! PRESENT_CRYPTO
+ *  0b1..Present
+ *  0b0..Absent
+ */
+#define DCP_CTRL_CLR_PRESENT_CRYPTO(x)           (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_PRESENT_CRYPTO_SHIFT)) & DCP_CTRL_CLR_PRESENT_CRYPTO_MASK)
+#define DCP_CTRL_CLR_CLKGATE_MASK                (0x40000000U)
+#define DCP_CTRL_CLR_CLKGATE_SHIFT               (30U)
+#define DCP_CTRL_CLR_CLKGATE(x)                  (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_CLKGATE_SHIFT)) & DCP_CTRL_CLR_CLKGATE_MASK)
+#define DCP_CTRL_CLR_SFTRST_MASK                 (0x80000000U)
+#define DCP_CTRL_CLR_SFTRST_SHIFT                (31U)
+#define DCP_CTRL_CLR_SFTRST(x)                   (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_SFTRST_SHIFT)) & DCP_CTRL_CLR_SFTRST_MASK)
+/*! @} */
+
+/*! @name CTRL_TOG - DCP control register 0 */
+/*! @{ */
+#define DCP_CTRL_TOG_CHANNEL_INTERRUPT_ENABLE_MASK (0xFFU)
+#define DCP_CTRL_TOG_CHANNEL_INTERRUPT_ENABLE_SHIFT (0U)
+/*! CHANNEL_INTERRUPT_ENABLE
+ *  0b00000001..CH0
+ *  0b00000010..CH1
+ *  0b00000100..CH2
+ *  0b00001000..CH3
+ */
+#define DCP_CTRL_TOG_CHANNEL_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_CHANNEL_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_TOG_CHANNEL_INTERRUPT_ENABLE_MASK)
+#define DCP_CTRL_TOG_RSVD_CSC_INTERRUPT_ENABLE_MASK (0x100U)
+#define DCP_CTRL_TOG_RSVD_CSC_INTERRUPT_ENABLE_SHIFT (8U)
+#define DCP_CTRL_TOG_RSVD_CSC_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_RSVD_CSC_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_TOG_RSVD_CSC_INTERRUPT_ENABLE_MASK)
+#define DCP_CTRL_TOG_ENABLE_CONTEXT_SWITCHING_MASK (0x200000U)
+#define DCP_CTRL_TOG_ENABLE_CONTEXT_SWITCHING_SHIFT (21U)
+#define DCP_CTRL_TOG_ENABLE_CONTEXT_SWITCHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_ENABLE_CONTEXT_SWITCHING_SHIFT)) & DCP_CTRL_TOG_ENABLE_CONTEXT_SWITCHING_MASK)
+#define DCP_CTRL_TOG_ENABLE_CONTEXT_CACHING_MASK (0x400000U)
+#define DCP_CTRL_TOG_ENABLE_CONTEXT_CACHING_SHIFT (22U)
+#define DCP_CTRL_TOG_ENABLE_CONTEXT_CACHING(x)   (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_ENABLE_CONTEXT_CACHING_SHIFT)) & DCP_CTRL_TOG_ENABLE_CONTEXT_CACHING_MASK)
+#define DCP_CTRL_TOG_GATHER_RESIDUAL_WRITES_MASK (0x800000U)
+#define DCP_CTRL_TOG_GATHER_RESIDUAL_WRITES_SHIFT (23U)
+#define DCP_CTRL_TOG_GATHER_RESIDUAL_WRITES(x)   (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_GATHER_RESIDUAL_WRITES_SHIFT)) & DCP_CTRL_TOG_GATHER_RESIDUAL_WRITES_MASK)
+#define DCP_CTRL_TOG_PRESENT_SHA_MASK            (0x10000000U)
+#define DCP_CTRL_TOG_PRESENT_SHA_SHIFT           (28U)
+/*! PRESENT_SHA
+ *  0b1..Present
+ *  0b0..Absent
+ */
+#define DCP_CTRL_TOG_PRESENT_SHA(x)              (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_PRESENT_SHA_SHIFT)) & DCP_CTRL_TOG_PRESENT_SHA_MASK)
+#define DCP_CTRL_TOG_PRESENT_CRYPTO_MASK         (0x20000000U)
+#define DCP_CTRL_TOG_PRESENT_CRYPTO_SHIFT        (29U)
+/*! PRESENT_CRYPTO
+ *  0b1..Present
+ *  0b0..Absent
+ */
+#define DCP_CTRL_TOG_PRESENT_CRYPTO(x)           (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_PRESENT_CRYPTO_SHIFT)) & DCP_CTRL_TOG_PRESENT_CRYPTO_MASK)
+#define DCP_CTRL_TOG_CLKGATE_MASK                (0x40000000U)
+#define DCP_CTRL_TOG_CLKGATE_SHIFT               (30U)
+#define DCP_CTRL_TOG_CLKGATE(x)                  (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_CLKGATE_SHIFT)) & DCP_CTRL_TOG_CLKGATE_MASK)
+#define DCP_CTRL_TOG_SFTRST_MASK                 (0x80000000U)
+#define DCP_CTRL_TOG_SFTRST_SHIFT                (31U)
+#define DCP_CTRL_TOG_SFTRST(x)                   (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_SFTRST_SHIFT)) & DCP_CTRL_TOG_SFTRST_MASK)
+/*! @} */
+
 /*! @name STAT - DCP status register */
 /*! @{ */
 #define DCP_STAT_IRQ_MASK                        (0xFU)
@@ -6817,22 +10476,143 @@ typedef struct {
 #define DCP_STAT_RSVD_IRQ(x)                     (((uint32_t)(((uint32_t)(x)) << DCP_STAT_RSVD_IRQ_SHIFT)) & DCP_STAT_RSVD_IRQ_MASK)
 #define DCP_STAT_READY_CHANNELS_MASK             (0xFF0000U)
 #define DCP_STAT_READY_CHANNELS_SHIFT            (16U)
+/*! READY_CHANNELS
+ *  0b00000001..CH0
+ *  0b00000010..CH1
+ *  0b00000100..CH2
+ *  0b00001000..CH3
+ */
 #define DCP_STAT_READY_CHANNELS(x)               (((uint32_t)(((uint32_t)(x)) << DCP_STAT_READY_CHANNELS_SHIFT)) & DCP_STAT_READY_CHANNELS_MASK)
 #define DCP_STAT_CUR_CHANNEL_MASK                (0xF000000U)
 #define DCP_STAT_CUR_CHANNEL_SHIFT               (24U)
+/*! CUR_CHANNEL
+ *  0b0000..None
+ *  0b0001..CH0
+ *  0b0010..CH1
+ *  0b0011..CH2
+ *  0b0100..CH3
+ */
 #define DCP_STAT_CUR_CHANNEL(x)                  (((uint32_t)(((uint32_t)(x)) << DCP_STAT_CUR_CHANNEL_SHIFT)) & DCP_STAT_CUR_CHANNEL_MASK)
 #define DCP_STAT_OTP_KEY_READY_MASK              (0x10000000U)
 #define DCP_STAT_OTP_KEY_READY_SHIFT             (28U)
 #define DCP_STAT_OTP_KEY_READY(x)                (((uint32_t)(((uint32_t)(x)) << DCP_STAT_OTP_KEY_READY_SHIFT)) & DCP_STAT_OTP_KEY_READY_MASK)
 /*! @} */
 
+/*! @name STAT_SET - DCP status register */
+/*! @{ */
+#define DCP_STAT_SET_IRQ_MASK                    (0xFU)
+#define DCP_STAT_SET_IRQ_SHIFT                   (0U)
+#define DCP_STAT_SET_IRQ(x)                      (((uint32_t)(((uint32_t)(x)) << DCP_STAT_SET_IRQ_SHIFT)) & DCP_STAT_SET_IRQ_MASK)
+#define DCP_STAT_SET_RSVD_IRQ_MASK               (0x100U)
+#define DCP_STAT_SET_RSVD_IRQ_SHIFT              (8U)
+#define DCP_STAT_SET_RSVD_IRQ(x)                 (((uint32_t)(((uint32_t)(x)) << DCP_STAT_SET_RSVD_IRQ_SHIFT)) & DCP_STAT_SET_RSVD_IRQ_MASK)
+#define DCP_STAT_SET_READY_CHANNELS_MASK         (0xFF0000U)
+#define DCP_STAT_SET_READY_CHANNELS_SHIFT        (16U)
+/*! READY_CHANNELS
+ *  0b00000001..CH0
+ *  0b00000010..CH1
+ *  0b00000100..CH2
+ *  0b00001000..CH3
+ */
+#define DCP_STAT_SET_READY_CHANNELS(x)           (((uint32_t)(((uint32_t)(x)) << DCP_STAT_SET_READY_CHANNELS_SHIFT)) & DCP_STAT_SET_READY_CHANNELS_MASK)
+#define DCP_STAT_SET_CUR_CHANNEL_MASK            (0xF000000U)
+#define DCP_STAT_SET_CUR_CHANNEL_SHIFT           (24U)
+/*! CUR_CHANNEL
+ *  0b0000..None
+ *  0b0001..CH0
+ *  0b0010..CH1
+ *  0b0011..CH2
+ *  0b0100..CH3
+ */
+#define DCP_STAT_SET_CUR_CHANNEL(x)              (((uint32_t)(((uint32_t)(x)) << DCP_STAT_SET_CUR_CHANNEL_SHIFT)) & DCP_STAT_SET_CUR_CHANNEL_MASK)
+#define DCP_STAT_SET_OTP_KEY_READY_MASK          (0x10000000U)
+#define DCP_STAT_SET_OTP_KEY_READY_SHIFT         (28U)
+#define DCP_STAT_SET_OTP_KEY_READY(x)            (((uint32_t)(((uint32_t)(x)) << DCP_STAT_SET_OTP_KEY_READY_SHIFT)) & DCP_STAT_SET_OTP_KEY_READY_MASK)
+/*! @} */
+
+/*! @name STAT_CLR - DCP status register */
+/*! @{ */
+#define DCP_STAT_CLR_IRQ_MASK                    (0xFU)
+#define DCP_STAT_CLR_IRQ_SHIFT                   (0U)
+#define DCP_STAT_CLR_IRQ(x)                      (((uint32_t)(((uint32_t)(x)) << DCP_STAT_CLR_IRQ_SHIFT)) & DCP_STAT_CLR_IRQ_MASK)
+#define DCP_STAT_CLR_RSVD_IRQ_MASK               (0x100U)
+#define DCP_STAT_CLR_RSVD_IRQ_SHIFT              (8U)
+#define DCP_STAT_CLR_RSVD_IRQ(x)                 (((uint32_t)(((uint32_t)(x)) << DCP_STAT_CLR_RSVD_IRQ_SHIFT)) & DCP_STAT_CLR_RSVD_IRQ_MASK)
+#define DCP_STAT_CLR_READY_CHANNELS_MASK         (0xFF0000U)
+#define DCP_STAT_CLR_READY_CHANNELS_SHIFT        (16U)
+/*! READY_CHANNELS
+ *  0b00000001..CH0
+ *  0b00000010..CH1
+ *  0b00000100..CH2
+ *  0b00001000..CH3
+ */
+#define DCP_STAT_CLR_READY_CHANNELS(x)           (((uint32_t)(((uint32_t)(x)) << DCP_STAT_CLR_READY_CHANNELS_SHIFT)) & DCP_STAT_CLR_READY_CHANNELS_MASK)
+#define DCP_STAT_CLR_CUR_CHANNEL_MASK            (0xF000000U)
+#define DCP_STAT_CLR_CUR_CHANNEL_SHIFT           (24U)
+/*! CUR_CHANNEL
+ *  0b0000..None
+ *  0b0001..CH0
+ *  0b0010..CH1
+ *  0b0011..CH2
+ *  0b0100..CH3
+ */
+#define DCP_STAT_CLR_CUR_CHANNEL(x)              (((uint32_t)(((uint32_t)(x)) << DCP_STAT_CLR_CUR_CHANNEL_SHIFT)) & DCP_STAT_CLR_CUR_CHANNEL_MASK)
+#define DCP_STAT_CLR_OTP_KEY_READY_MASK          (0x10000000U)
+#define DCP_STAT_CLR_OTP_KEY_READY_SHIFT         (28U)
+#define DCP_STAT_CLR_OTP_KEY_READY(x)            (((uint32_t)(((uint32_t)(x)) << DCP_STAT_CLR_OTP_KEY_READY_SHIFT)) & DCP_STAT_CLR_OTP_KEY_READY_MASK)
+/*! @} */
+
+/*! @name STAT_TOG - DCP status register */
+/*! @{ */
+#define DCP_STAT_TOG_IRQ_MASK                    (0xFU)
+#define DCP_STAT_TOG_IRQ_SHIFT                   (0U)
+#define DCP_STAT_TOG_IRQ(x)                      (((uint32_t)(((uint32_t)(x)) << DCP_STAT_TOG_IRQ_SHIFT)) & DCP_STAT_TOG_IRQ_MASK)
+#define DCP_STAT_TOG_RSVD_IRQ_MASK               (0x100U)
+#define DCP_STAT_TOG_RSVD_IRQ_SHIFT              (8U)
+#define DCP_STAT_TOG_RSVD_IRQ(x)                 (((uint32_t)(((uint32_t)(x)) << DCP_STAT_TOG_RSVD_IRQ_SHIFT)) & DCP_STAT_TOG_RSVD_IRQ_MASK)
+#define DCP_STAT_TOG_READY_CHANNELS_MASK         (0xFF0000U)
+#define DCP_STAT_TOG_READY_CHANNELS_SHIFT        (16U)
+/*! READY_CHANNELS
+ *  0b00000001..CH0
+ *  0b00000010..CH1
+ *  0b00000100..CH2
+ *  0b00001000..CH3
+ */
+#define DCP_STAT_TOG_READY_CHANNELS(x)           (((uint32_t)(((uint32_t)(x)) << DCP_STAT_TOG_READY_CHANNELS_SHIFT)) & DCP_STAT_TOG_READY_CHANNELS_MASK)
+#define DCP_STAT_TOG_CUR_CHANNEL_MASK            (0xF000000U)
+#define DCP_STAT_TOG_CUR_CHANNEL_SHIFT           (24U)
+/*! CUR_CHANNEL
+ *  0b0000..None
+ *  0b0001..CH0
+ *  0b0010..CH1
+ *  0b0011..CH2
+ *  0b0100..CH3
+ */
+#define DCP_STAT_TOG_CUR_CHANNEL(x)              (((uint32_t)(((uint32_t)(x)) << DCP_STAT_TOG_CUR_CHANNEL_SHIFT)) & DCP_STAT_TOG_CUR_CHANNEL_MASK)
+#define DCP_STAT_TOG_OTP_KEY_READY_MASK          (0x10000000U)
+#define DCP_STAT_TOG_OTP_KEY_READY_SHIFT         (28U)
+#define DCP_STAT_TOG_OTP_KEY_READY(x)            (((uint32_t)(((uint32_t)(x)) << DCP_STAT_TOG_OTP_KEY_READY_SHIFT)) & DCP_STAT_TOG_OTP_KEY_READY_MASK)
+/*! @} */
+
 /*! @name CHANNELCTRL - DCP channel control register */
 /*! @{ */
 #define DCP_CHANNELCTRL_ENABLE_CHANNEL_MASK      (0xFFU)
 #define DCP_CHANNELCTRL_ENABLE_CHANNEL_SHIFT     (0U)
+/*! ENABLE_CHANNEL
+ *  0b00000001..CH0
+ *  0b00000010..CH1
+ *  0b00000100..CH2
+ *  0b00001000..CH3
+ */
 #define DCP_CHANNELCTRL_ENABLE_CHANNEL(x)        (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_ENABLE_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_ENABLE_CHANNEL_MASK)
 #define DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_MASK (0xFF00U)
 #define DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_SHIFT (8U)
+/*! HIGH_PRIORITY_CHANNEL
+ *  0b00000001..CH0
+ *  0b00000010..CH1
+ *  0b00000100..CH2
+ *  0b00001000..CH3
+ */
 #define DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_MASK)
 #define DCP_CHANNELCTRL_CH0_IRQ_MERGED_MASK      (0x10000U)
 #define DCP_CHANNELCTRL_CH0_IRQ_MERGED_SHIFT     (16U)
@@ -6842,6 +10622,90 @@ typedef struct {
 #define DCP_CHANNELCTRL_RSVD(x)                  (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_RSVD_SHIFT)) & DCP_CHANNELCTRL_RSVD_MASK)
 /*! @} */
 
+/*! @name CHANNELCTRL_SET - DCP channel control register */
+/*! @{ */
+#define DCP_CHANNELCTRL_SET_ENABLE_CHANNEL_MASK  (0xFFU)
+#define DCP_CHANNELCTRL_SET_ENABLE_CHANNEL_SHIFT (0U)
+/*! ENABLE_CHANNEL
+ *  0b00000001..CH0
+ *  0b00000010..CH1
+ *  0b00000100..CH2
+ *  0b00001000..CH3
+ */
+#define DCP_CHANNELCTRL_SET_ENABLE_CHANNEL(x)    (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_SET_ENABLE_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_SET_ENABLE_CHANNEL_MASK)
+#define DCP_CHANNELCTRL_SET_HIGH_PRIORITY_CHANNEL_MASK (0xFF00U)
+#define DCP_CHANNELCTRL_SET_HIGH_PRIORITY_CHANNEL_SHIFT (8U)
+/*! HIGH_PRIORITY_CHANNEL
+ *  0b00000001..CH0
+ *  0b00000010..CH1
+ *  0b00000100..CH2
+ *  0b00001000..CH3
+ */
+#define DCP_CHANNELCTRL_SET_HIGH_PRIORITY_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_SET_HIGH_PRIORITY_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_SET_HIGH_PRIORITY_CHANNEL_MASK)
+#define DCP_CHANNELCTRL_SET_CH0_IRQ_MERGED_MASK  (0x10000U)
+#define DCP_CHANNELCTRL_SET_CH0_IRQ_MERGED_SHIFT (16U)
+#define DCP_CHANNELCTRL_SET_CH0_IRQ_MERGED(x)    (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_SET_CH0_IRQ_MERGED_SHIFT)) & DCP_CHANNELCTRL_SET_CH0_IRQ_MERGED_MASK)
+#define DCP_CHANNELCTRL_SET_RSVD_MASK            (0xFFFE0000U)
+#define DCP_CHANNELCTRL_SET_RSVD_SHIFT           (17U)
+#define DCP_CHANNELCTRL_SET_RSVD(x)              (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_SET_RSVD_SHIFT)) & DCP_CHANNELCTRL_SET_RSVD_MASK)
+/*! @} */
+
+/*! @name CHANNELCTRL_CLR - DCP channel control register */
+/*! @{ */
+#define DCP_CHANNELCTRL_CLR_ENABLE_CHANNEL_MASK  (0xFFU)
+#define DCP_CHANNELCTRL_CLR_ENABLE_CHANNEL_SHIFT (0U)
+/*! ENABLE_CHANNEL
+ *  0b00000001..CH0
+ *  0b00000010..CH1
+ *  0b00000100..CH2
+ *  0b00001000..CH3
+ */
+#define DCP_CHANNELCTRL_CLR_ENABLE_CHANNEL(x)    (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_CLR_ENABLE_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_CLR_ENABLE_CHANNEL_MASK)
+#define DCP_CHANNELCTRL_CLR_HIGH_PRIORITY_CHANNEL_MASK (0xFF00U)
+#define DCP_CHANNELCTRL_CLR_HIGH_PRIORITY_CHANNEL_SHIFT (8U)
+/*! HIGH_PRIORITY_CHANNEL
+ *  0b00000001..CH0
+ *  0b00000010..CH1
+ *  0b00000100..CH2
+ *  0b00001000..CH3
+ */
+#define DCP_CHANNELCTRL_CLR_HIGH_PRIORITY_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_CLR_HIGH_PRIORITY_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_CLR_HIGH_PRIORITY_CHANNEL_MASK)
+#define DCP_CHANNELCTRL_CLR_CH0_IRQ_MERGED_MASK  (0x10000U)
+#define DCP_CHANNELCTRL_CLR_CH0_IRQ_MERGED_SHIFT (16U)
+#define DCP_CHANNELCTRL_CLR_CH0_IRQ_MERGED(x)    (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_CLR_CH0_IRQ_MERGED_SHIFT)) & DCP_CHANNELCTRL_CLR_CH0_IRQ_MERGED_MASK)
+#define DCP_CHANNELCTRL_CLR_RSVD_MASK            (0xFFFE0000U)
+#define DCP_CHANNELCTRL_CLR_RSVD_SHIFT           (17U)
+#define DCP_CHANNELCTRL_CLR_RSVD(x)              (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_CLR_RSVD_SHIFT)) & DCP_CHANNELCTRL_CLR_RSVD_MASK)
+/*! @} */
+
+/*! @name CHANNELCTRL_TOG - DCP channel control register */
+/*! @{ */
+#define DCP_CHANNELCTRL_TOG_ENABLE_CHANNEL_MASK  (0xFFU)
+#define DCP_CHANNELCTRL_TOG_ENABLE_CHANNEL_SHIFT (0U)
+/*! ENABLE_CHANNEL
+ *  0b00000001..CH0
+ *  0b00000010..CH1
+ *  0b00000100..CH2
+ *  0b00001000..CH3
+ */
+#define DCP_CHANNELCTRL_TOG_ENABLE_CHANNEL(x)    (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_TOG_ENABLE_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_TOG_ENABLE_CHANNEL_MASK)
+#define DCP_CHANNELCTRL_TOG_HIGH_PRIORITY_CHANNEL_MASK (0xFF00U)
+#define DCP_CHANNELCTRL_TOG_HIGH_PRIORITY_CHANNEL_SHIFT (8U)
+/*! HIGH_PRIORITY_CHANNEL
+ *  0b00000001..CH0
+ *  0b00000010..CH1
+ *  0b00000100..CH2
+ *  0b00001000..CH3
+ */
+#define DCP_CHANNELCTRL_TOG_HIGH_PRIORITY_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_TOG_HIGH_PRIORITY_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_TOG_HIGH_PRIORITY_CHANNEL_MASK)
+#define DCP_CHANNELCTRL_TOG_CH0_IRQ_MERGED_MASK  (0x10000U)
+#define DCP_CHANNELCTRL_TOG_CH0_IRQ_MERGED_SHIFT (16U)
+#define DCP_CHANNELCTRL_TOG_CH0_IRQ_MERGED(x)    (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_TOG_CH0_IRQ_MERGED_SHIFT)) & DCP_CHANNELCTRL_TOG_CH0_IRQ_MERGED_MASK)
+#define DCP_CHANNELCTRL_TOG_RSVD_MASK            (0xFFFE0000U)
+#define DCP_CHANNELCTRL_TOG_RSVD_SHIFT           (17U)
+#define DCP_CHANNELCTRL_TOG_RSVD(x)              (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_TOG_RSVD_SHIFT)) & DCP_CHANNELCTRL_TOG_RSVD_MASK)
+/*! @} */
+
 /*! @name CAPABILITY0 - DCP capability 0 register */
 /*! @{ */
 #define DCP_CAPABILITY0_NUM_KEYS_MASK            (0xFFU)
@@ -6865,9 +10729,17 @@ typedef struct {
 /*! @{ */
 #define DCP_CAPABILITY1_CIPHER_ALGORITHMS_MASK   (0xFFFFU)
 #define DCP_CAPABILITY1_CIPHER_ALGORITHMS_SHIFT  (0U)
+/*! CIPHER_ALGORITHMS
+ *  0b0000000000000001..AES128
+ */
 #define DCP_CAPABILITY1_CIPHER_ALGORITHMS(x)     (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY1_CIPHER_ALGORITHMS_SHIFT)) & DCP_CAPABILITY1_CIPHER_ALGORITHMS_MASK)
 #define DCP_CAPABILITY1_HASH_ALGORITHMS_MASK     (0xFFFF0000U)
 #define DCP_CAPABILITY1_HASH_ALGORITHMS_SHIFT    (16U)
+/*! HASH_ALGORITHMS
+ *  0b0000000000000001..SHA1
+ *  0b0000000000000010..CRC32
+ *  0b0000000000000100..SHA256
+ */
 #define DCP_CAPABILITY1_HASH_ALGORITHMS(x)       (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY1_HASH_ALGORITHMS_SHIFT)) & DCP_CAPABILITY1_HASH_ALGORITHMS_MASK)
 /*! @} */
 
@@ -6939,6 +10811,10 @@ typedef struct {
 #define DCP_PACKET1_ENABLE_BLIT(x)               (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_ENABLE_BLIT_SHIFT)) & DCP_PACKET1_ENABLE_BLIT_MASK)
 #define DCP_PACKET1_CIPHER_ENCRYPT_MASK          (0x100U)
 #define DCP_PACKET1_CIPHER_ENCRYPT_SHIFT         (8U)
+/*! CIPHER_ENCRYPT
+ *  0b1..ENCRYPT
+ *  0b0..DECRYPT
+ */
 #define DCP_PACKET1_CIPHER_ENCRYPT(x)            (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CIPHER_ENCRYPT_SHIFT)) & DCP_PACKET1_CIPHER_ENCRYPT_MASK)
 #define DCP_PACKET1_CIPHER_INIT_MASK             (0x200U)
 #define DCP_PACKET1_CIPHER_INIT_SHIFT            (9U)
@@ -6960,6 +10836,10 @@ typedef struct {
 #define DCP_PACKET1_CHECK_HASH(x)                (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CHECK_HASH_SHIFT)) & DCP_PACKET1_CHECK_HASH_MASK)
 #define DCP_PACKET1_HASH_OUTPUT_MASK             (0x8000U)
 #define DCP_PACKET1_HASH_OUTPUT_SHIFT            (15U)
+/*! HASH_OUTPUT
+ *  0b0..INPUT
+ *  0b1..OUTPUT
+ */
 #define DCP_PACKET1_HASH_OUTPUT(x)               (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_HASH_OUTPUT_SHIFT)) & DCP_PACKET1_HASH_OUTPUT_MASK)
 #define DCP_PACKET1_CONSTANT_FILL_MASK           (0x10000U)
 #define DCP_PACKET1_CONSTANT_FILL_SHIFT          (16U)
@@ -6994,15 +10874,35 @@ typedef struct {
 /*! @{ */
 #define DCP_PACKET2_CIPHER_SELECT_MASK           (0xFU)
 #define DCP_PACKET2_CIPHER_SELECT_SHIFT          (0U)
+/*! CIPHER_SELECT
+ *  0b0000..AES128
+ */
 #define DCP_PACKET2_CIPHER_SELECT(x)             (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_CIPHER_SELECT_SHIFT)) & DCP_PACKET2_CIPHER_SELECT_MASK)
 #define DCP_PACKET2_CIPHER_MODE_MASK             (0xF0U)
 #define DCP_PACKET2_CIPHER_MODE_SHIFT            (4U)
+/*! CIPHER_MODE
+ *  0b0000..ECB
+ *  0b0001..CBC
+ */
 #define DCP_PACKET2_CIPHER_MODE(x)               (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_CIPHER_MODE_SHIFT)) & DCP_PACKET2_CIPHER_MODE_MASK)
 #define DCP_PACKET2_KEY_SELECT_MASK              (0xFF00U)
 #define DCP_PACKET2_KEY_SELECT_SHIFT             (8U)
+/*! KEY_SELECT
+ *  0b00000000..KEY0
+ *  0b00000001..KEY1
+ *  0b00000010..KEY2
+ *  0b00000011..KEY3
+ *  0b11111110..UNIQUE_KEY
+ *  0b11111111..OTP_KEY
+ */
 #define DCP_PACKET2_KEY_SELECT(x)                (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_KEY_SELECT_SHIFT)) & DCP_PACKET2_KEY_SELECT_MASK)
 #define DCP_PACKET2_HASH_SELECT_MASK             (0xF0000U)
 #define DCP_PACKET2_HASH_SELECT_SHIFT            (16U)
+/*! HASH_SELECT
+ *  0b0000..SHA1
+ *  0b0001..CRC32
+ *  0b0010..SHA256
+ */
 #define DCP_PACKET2_HASH_SELECT(x)               (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_HASH_SELECT_SHIFT)) & DCP_PACKET2_HASH_SELECT_MASK)
 #define DCP_PACKET2_RSVD_MASK                    (0xF00000U)
 #define DCP_PACKET2_RSVD_SHIFT                   (20U)
@@ -7082,12 +10982,133 @@ typedef struct {
 #define DCP_CH0STAT_ERROR_PAGEFAULT(x)           (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_PAGEFAULT_SHIFT)) & DCP_CH0STAT_ERROR_PAGEFAULT_MASK)
 #define DCP_CH0STAT_ERROR_CODE_MASK              (0xFF0000U)
 #define DCP_CH0STAT_ERROR_CODE_SHIFT             (16U)
+/*! ERROR_CODE
+ *  0b00000001..Error signalled because the next pointer is 0x00000000
+ *  0b00000010..Error signalled because the semaphore is non-zero and neither chain bit is set
+ *  0b00000011..Error signalled because an error is reported reading/writing the context buffer
+ *  0b00000100..Error signalled because an error is reported reading/writing the payload
+ *  0b00000101..Error signalled because the control packet specifies an invalid mode select (for instance, blit + hash)
+ */
 #define DCP_CH0STAT_ERROR_CODE(x)                (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_CODE_SHIFT)) & DCP_CH0STAT_ERROR_CODE_MASK)
 #define DCP_CH0STAT_TAG_MASK                     (0xFF000000U)
 #define DCP_CH0STAT_TAG_SHIFT                    (24U)
 #define DCP_CH0STAT_TAG(x)                       (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TAG_SHIFT)) & DCP_CH0STAT_TAG_MASK)
 /*! @} */
 
+/*! @name CH0STAT_SET - DCP channel 0 status register */
+/*! @{ */
+#define DCP_CH0STAT_SET_RSVD_COMPLETE_MASK       (0x1U)
+#define DCP_CH0STAT_SET_RSVD_COMPLETE_SHIFT      (0U)
+#define DCP_CH0STAT_SET_RSVD_COMPLETE(x)         (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_SET_RSVD_COMPLETE_SHIFT)) & DCP_CH0STAT_SET_RSVD_COMPLETE_MASK)
+#define DCP_CH0STAT_SET_HASH_MISMATCH_MASK       (0x2U)
+#define DCP_CH0STAT_SET_HASH_MISMATCH_SHIFT      (1U)
+#define DCP_CH0STAT_SET_HASH_MISMATCH(x)         (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_SET_HASH_MISMATCH_SHIFT)) & DCP_CH0STAT_SET_HASH_MISMATCH_MASK)
+#define DCP_CH0STAT_SET_ERROR_SETUP_MASK         (0x4U)
+#define DCP_CH0STAT_SET_ERROR_SETUP_SHIFT        (2U)
+#define DCP_CH0STAT_SET_ERROR_SETUP(x)           (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_SET_ERROR_SETUP_SHIFT)) & DCP_CH0STAT_SET_ERROR_SETUP_MASK)
+#define DCP_CH0STAT_SET_ERROR_PACKET_MASK        (0x8U)
+#define DCP_CH0STAT_SET_ERROR_PACKET_SHIFT       (3U)
+#define DCP_CH0STAT_SET_ERROR_PACKET(x)          (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_SET_ERROR_PACKET_SHIFT)) & DCP_CH0STAT_SET_ERROR_PACKET_MASK)
+#define DCP_CH0STAT_SET_ERROR_SRC_MASK           (0x10U)
+#define DCP_CH0STAT_SET_ERROR_SRC_SHIFT          (4U)
+#define DCP_CH0STAT_SET_ERROR_SRC(x)             (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_SET_ERROR_SRC_SHIFT)) & DCP_CH0STAT_SET_ERROR_SRC_MASK)
+#define DCP_CH0STAT_SET_ERROR_DST_MASK           (0x20U)
+#define DCP_CH0STAT_SET_ERROR_DST_SHIFT          (5U)
+#define DCP_CH0STAT_SET_ERROR_DST(x)             (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_SET_ERROR_DST_SHIFT)) & DCP_CH0STAT_SET_ERROR_DST_MASK)
+#define DCP_CH0STAT_SET_ERROR_PAGEFAULT_MASK     (0x40U)
+#define DCP_CH0STAT_SET_ERROR_PAGEFAULT_SHIFT    (6U)
+#define DCP_CH0STAT_SET_ERROR_PAGEFAULT(x)       (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_SET_ERROR_PAGEFAULT_SHIFT)) & DCP_CH0STAT_SET_ERROR_PAGEFAULT_MASK)
+#define DCP_CH0STAT_SET_ERROR_CODE_MASK          (0xFF0000U)
+#define DCP_CH0STAT_SET_ERROR_CODE_SHIFT         (16U)
+/*! ERROR_CODE
+ *  0b00000001..Error signalled because the next pointer is 0x00000000
+ *  0b00000010..Error signalled because the semaphore is non-zero and neither chain bit is set
+ *  0b00000011..Error signalled because an error is reported reading/writing the context buffer
+ *  0b00000100..Error signalled because an error is reported reading/writing the payload
+ *  0b00000101..Error signalled because the control packet specifies an invalid mode select (for instance, blit + hash)
+ */
+#define DCP_CH0STAT_SET_ERROR_CODE(x)            (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_SET_ERROR_CODE_SHIFT)) & DCP_CH0STAT_SET_ERROR_CODE_MASK)
+#define DCP_CH0STAT_SET_TAG_MASK                 (0xFF000000U)
+#define DCP_CH0STAT_SET_TAG_SHIFT                (24U)
+#define DCP_CH0STAT_SET_TAG(x)                   (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_SET_TAG_SHIFT)) & DCP_CH0STAT_SET_TAG_MASK)
+/*! @} */
+
+/*! @name CH0STAT_CLR - DCP channel 0 status register */
+/*! @{ */
+#define DCP_CH0STAT_CLR_RSVD_COMPLETE_MASK       (0x1U)
+#define DCP_CH0STAT_CLR_RSVD_COMPLETE_SHIFT      (0U)
+#define DCP_CH0STAT_CLR_RSVD_COMPLETE(x)         (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_CLR_RSVD_COMPLETE_SHIFT)) & DCP_CH0STAT_CLR_RSVD_COMPLETE_MASK)
+#define DCP_CH0STAT_CLR_HASH_MISMATCH_MASK       (0x2U)
+#define DCP_CH0STAT_CLR_HASH_MISMATCH_SHIFT      (1U)
+#define DCP_CH0STAT_CLR_HASH_MISMATCH(x)         (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_CLR_HASH_MISMATCH_SHIFT)) & DCP_CH0STAT_CLR_HASH_MISMATCH_MASK)
+#define DCP_CH0STAT_CLR_ERROR_SETUP_MASK         (0x4U)
+#define DCP_CH0STAT_CLR_ERROR_SETUP_SHIFT        (2U)
+#define DCP_CH0STAT_CLR_ERROR_SETUP(x)           (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_CLR_ERROR_SETUP_SHIFT)) & DCP_CH0STAT_CLR_ERROR_SETUP_MASK)
+#define DCP_CH0STAT_CLR_ERROR_PACKET_MASK        (0x8U)
+#define DCP_CH0STAT_CLR_ERROR_PACKET_SHIFT       (3U)
+#define DCP_CH0STAT_CLR_ERROR_PACKET(x)          (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_CLR_ERROR_PACKET_SHIFT)) & DCP_CH0STAT_CLR_ERROR_PACKET_MASK)
+#define DCP_CH0STAT_CLR_ERROR_SRC_MASK           (0x10U)
+#define DCP_CH0STAT_CLR_ERROR_SRC_SHIFT          (4U)
+#define DCP_CH0STAT_CLR_ERROR_SRC(x)             (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_CLR_ERROR_SRC_SHIFT)) & DCP_CH0STAT_CLR_ERROR_SRC_MASK)
+#define DCP_CH0STAT_CLR_ERROR_DST_MASK           (0x20U)
+#define DCP_CH0STAT_CLR_ERROR_DST_SHIFT          (5U)
+#define DCP_CH0STAT_CLR_ERROR_DST(x)             (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_CLR_ERROR_DST_SHIFT)) & DCP_CH0STAT_CLR_ERROR_DST_MASK)
+#define DCP_CH0STAT_CLR_ERROR_PAGEFAULT_MASK     (0x40U)
+#define DCP_CH0STAT_CLR_ERROR_PAGEFAULT_SHIFT    (6U)
+#define DCP_CH0STAT_CLR_ERROR_PAGEFAULT(x)       (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_CLR_ERROR_PAGEFAULT_SHIFT)) & DCP_CH0STAT_CLR_ERROR_PAGEFAULT_MASK)
+#define DCP_CH0STAT_CLR_ERROR_CODE_MASK          (0xFF0000U)
+#define DCP_CH0STAT_CLR_ERROR_CODE_SHIFT         (16U)
+/*! ERROR_CODE
+ *  0b00000001..Error signalled because the next pointer is 0x00000000
+ *  0b00000010..Error signalled because the semaphore is non-zero and neither chain bit is set
+ *  0b00000011..Error signalled because an error is reported reading/writing the context buffer
+ *  0b00000100..Error signalled because an error is reported reading/writing the payload
+ *  0b00000101..Error signalled because the control packet specifies an invalid mode select (for instance, blit + hash)
+ */
+#define DCP_CH0STAT_CLR_ERROR_CODE(x)            (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_CLR_ERROR_CODE_SHIFT)) & DCP_CH0STAT_CLR_ERROR_CODE_MASK)
+#define DCP_CH0STAT_CLR_TAG_MASK                 (0xFF000000U)
+#define DCP_CH0STAT_CLR_TAG_SHIFT                (24U)
+#define DCP_CH0STAT_CLR_TAG(x)                   (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_CLR_TAG_SHIFT)) & DCP_CH0STAT_CLR_TAG_MASK)
+/*! @} */
+
+/*! @name CH0STAT_TOG - DCP channel 0 status register */
+/*! @{ */
+#define DCP_CH0STAT_TOG_RSVD_COMPLETE_MASK       (0x1U)
+#define DCP_CH0STAT_TOG_RSVD_COMPLETE_SHIFT      (0U)
+#define DCP_CH0STAT_TOG_RSVD_COMPLETE(x)         (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TOG_RSVD_COMPLETE_SHIFT)) & DCP_CH0STAT_TOG_RSVD_COMPLETE_MASK)
+#define DCP_CH0STAT_TOG_HASH_MISMATCH_MASK       (0x2U)
+#define DCP_CH0STAT_TOG_HASH_MISMATCH_SHIFT      (1U)
+#define DCP_CH0STAT_TOG_HASH_MISMATCH(x)         (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TOG_HASH_MISMATCH_SHIFT)) & DCP_CH0STAT_TOG_HASH_MISMATCH_MASK)
+#define DCP_CH0STAT_TOG_ERROR_SETUP_MASK         (0x4U)
+#define DCP_CH0STAT_TOG_ERROR_SETUP_SHIFT        (2U)
+#define DCP_CH0STAT_TOG_ERROR_SETUP(x)           (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TOG_ERROR_SETUP_SHIFT)) & DCP_CH0STAT_TOG_ERROR_SETUP_MASK)
+#define DCP_CH0STAT_TOG_ERROR_PACKET_MASK        (0x8U)
+#define DCP_CH0STAT_TOG_ERROR_PACKET_SHIFT       (3U)
+#define DCP_CH0STAT_TOG_ERROR_PACKET(x)          (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TOG_ERROR_PACKET_SHIFT)) & DCP_CH0STAT_TOG_ERROR_PACKET_MASK)
+#define DCP_CH0STAT_TOG_ERROR_SRC_MASK           (0x10U)
+#define DCP_CH0STAT_TOG_ERROR_SRC_SHIFT          (4U)
+#define DCP_CH0STAT_TOG_ERROR_SRC(x)             (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TOG_ERROR_SRC_SHIFT)) & DCP_CH0STAT_TOG_ERROR_SRC_MASK)
+#define DCP_CH0STAT_TOG_ERROR_DST_MASK           (0x20U)
+#define DCP_CH0STAT_TOG_ERROR_DST_SHIFT          (5U)
+#define DCP_CH0STAT_TOG_ERROR_DST(x)             (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TOG_ERROR_DST_SHIFT)) & DCP_CH0STAT_TOG_ERROR_DST_MASK)
+#define DCP_CH0STAT_TOG_ERROR_PAGEFAULT_MASK     (0x40U)
+#define DCP_CH0STAT_TOG_ERROR_PAGEFAULT_SHIFT    (6U)
+#define DCP_CH0STAT_TOG_ERROR_PAGEFAULT(x)       (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TOG_ERROR_PAGEFAULT_SHIFT)) & DCP_CH0STAT_TOG_ERROR_PAGEFAULT_MASK)
+#define DCP_CH0STAT_TOG_ERROR_CODE_MASK          (0xFF0000U)
+#define DCP_CH0STAT_TOG_ERROR_CODE_SHIFT         (16U)
+/*! ERROR_CODE
+ *  0b00000001..Error signalled because the next pointer is 0x00000000
+ *  0b00000010..Error signalled because the semaphore is non-zero and neither chain bit is set
+ *  0b00000011..Error signalled because an error is reported reading/writing the context buffer
+ *  0b00000100..Error signalled because an error is reported reading/writing the payload
+ *  0b00000101..Error signalled because the control packet specifies an invalid mode select (for instance, blit + hash)
+ */
+#define DCP_CH0STAT_TOG_ERROR_CODE(x)            (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TOG_ERROR_CODE_SHIFT)) & DCP_CH0STAT_TOG_ERROR_CODE_MASK)
+#define DCP_CH0STAT_TOG_TAG_MASK                 (0xFF000000U)
+#define DCP_CH0STAT_TOG_TAG_SHIFT                (24U)
+#define DCP_CH0STAT_TOG_TAG(x)                   (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TOG_TAG_SHIFT)) & DCP_CH0STAT_TOG_TAG_MASK)
+/*! @} */
+
 /*! @name CH0OPTS - DCP channel 0 options register */
 /*! @{ */
 #define DCP_CH0OPTS_RECOVERY_TIMER_MASK          (0xFFFFU)
@@ -7098,6 +11119,36 @@ typedef struct {
 #define DCP_CH0OPTS_RSVD(x)                      (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_RSVD_SHIFT)) & DCP_CH0OPTS_RSVD_MASK)
 /*! @} */
 
+/*! @name CH0OPTS_SET - DCP channel 0 options register */
+/*! @{ */
+#define DCP_CH0OPTS_SET_RECOVERY_TIMER_MASK      (0xFFFFU)
+#define DCP_CH0OPTS_SET_RECOVERY_TIMER_SHIFT     (0U)
+#define DCP_CH0OPTS_SET_RECOVERY_TIMER(x)        (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_SET_RECOVERY_TIMER_SHIFT)) & DCP_CH0OPTS_SET_RECOVERY_TIMER_MASK)
+#define DCP_CH0OPTS_SET_RSVD_MASK                (0xFFFF0000U)
+#define DCP_CH0OPTS_SET_RSVD_SHIFT               (16U)
+#define DCP_CH0OPTS_SET_RSVD(x)                  (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_SET_RSVD_SHIFT)) & DCP_CH0OPTS_SET_RSVD_MASK)
+/*! @} */
+
+/*! @name CH0OPTS_CLR - DCP channel 0 options register */
+/*! @{ */
+#define DCP_CH0OPTS_CLR_RECOVERY_TIMER_MASK      (0xFFFFU)
+#define DCP_CH0OPTS_CLR_RECOVERY_TIMER_SHIFT     (0U)
+#define DCP_CH0OPTS_CLR_RECOVERY_TIMER(x)        (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_CLR_RECOVERY_TIMER_SHIFT)) & DCP_CH0OPTS_CLR_RECOVERY_TIMER_MASK)
+#define DCP_CH0OPTS_CLR_RSVD_MASK                (0xFFFF0000U)
+#define DCP_CH0OPTS_CLR_RSVD_SHIFT               (16U)
+#define DCP_CH0OPTS_CLR_RSVD(x)                  (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_CLR_RSVD_SHIFT)) & DCP_CH0OPTS_CLR_RSVD_MASK)
+/*! @} */
+
+/*! @name CH0OPTS_TOG - DCP channel 0 options register */
+/*! @{ */
+#define DCP_CH0OPTS_TOG_RECOVERY_TIMER_MASK      (0xFFFFU)
+#define DCP_CH0OPTS_TOG_RECOVERY_TIMER_SHIFT     (0U)
+#define DCP_CH0OPTS_TOG_RECOVERY_TIMER(x)        (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_TOG_RECOVERY_TIMER_SHIFT)) & DCP_CH0OPTS_TOG_RECOVERY_TIMER_MASK)
+#define DCP_CH0OPTS_TOG_RSVD_MASK                (0xFFFF0000U)
+#define DCP_CH0OPTS_TOG_RSVD_SHIFT               (16U)
+#define DCP_CH0OPTS_TOG_RSVD(x)                  (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_TOG_RSVD_SHIFT)) & DCP_CH0OPTS_TOG_RSVD_MASK)
+/*! @} */
+
 /*! @name CH1CMDPTR - DCP channel 1 command pointer address register */
 /*! @{ */
 #define DCP_CH1CMDPTR_ADDR_MASK                  (0xFFFFFFFFU)
@@ -7140,12 +11191,133 @@ typedef struct {
 #define DCP_CH1STAT_ERROR_PAGEFAULT(x)           (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_PAGEFAULT_SHIFT)) & DCP_CH1STAT_ERROR_PAGEFAULT_MASK)
 #define DCP_CH1STAT_ERROR_CODE_MASK              (0xFF0000U)
 #define DCP_CH1STAT_ERROR_CODE_SHIFT             (16U)
+/*! ERROR_CODE
+ *  0b00000001..Error is signalled because the next pointer is 0x00000000.
+ *  0b00000010..Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set.
+ *  0b00000011..Error is signalled because an error was reported when reading/writing the context buffer.
+ *  0b00000100..Error is signalled because an error was reported when reading/writing the payload.
+ *  0b00000101..Error is signalled because the control packet specifies an invalid mode select (for example, blit + hash).
+ */
 #define DCP_CH1STAT_ERROR_CODE(x)                (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_CODE_SHIFT)) & DCP_CH1STAT_ERROR_CODE_MASK)
 #define DCP_CH1STAT_TAG_MASK                     (0xFF000000U)
 #define DCP_CH1STAT_TAG_SHIFT                    (24U)
 #define DCP_CH1STAT_TAG(x)                       (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TAG_SHIFT)) & DCP_CH1STAT_TAG_MASK)
 /*! @} */
 
+/*! @name CH1STAT_SET - DCP channel 1 status register */
+/*! @{ */
+#define DCP_CH1STAT_SET_RSVD_COMPLETE_MASK       (0x1U)
+#define DCP_CH1STAT_SET_RSVD_COMPLETE_SHIFT      (0U)
+#define DCP_CH1STAT_SET_RSVD_COMPLETE(x)         (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_SET_RSVD_COMPLETE_SHIFT)) & DCP_CH1STAT_SET_RSVD_COMPLETE_MASK)
+#define DCP_CH1STAT_SET_HASH_MISMATCH_MASK       (0x2U)
+#define DCP_CH1STAT_SET_HASH_MISMATCH_SHIFT      (1U)
+#define DCP_CH1STAT_SET_HASH_MISMATCH(x)         (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_SET_HASH_MISMATCH_SHIFT)) & DCP_CH1STAT_SET_HASH_MISMATCH_MASK)
+#define DCP_CH1STAT_SET_ERROR_SETUP_MASK         (0x4U)
+#define DCP_CH1STAT_SET_ERROR_SETUP_SHIFT        (2U)
+#define DCP_CH1STAT_SET_ERROR_SETUP(x)           (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_SET_ERROR_SETUP_SHIFT)) & DCP_CH1STAT_SET_ERROR_SETUP_MASK)
+#define DCP_CH1STAT_SET_ERROR_PACKET_MASK        (0x8U)
+#define DCP_CH1STAT_SET_ERROR_PACKET_SHIFT       (3U)
+#define DCP_CH1STAT_SET_ERROR_PACKET(x)          (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_SET_ERROR_PACKET_SHIFT)) & DCP_CH1STAT_SET_ERROR_PACKET_MASK)
+#define DCP_CH1STAT_SET_ERROR_SRC_MASK           (0x10U)
+#define DCP_CH1STAT_SET_ERROR_SRC_SHIFT          (4U)
+#define DCP_CH1STAT_SET_ERROR_SRC(x)             (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_SET_ERROR_SRC_SHIFT)) & DCP_CH1STAT_SET_ERROR_SRC_MASK)
+#define DCP_CH1STAT_SET_ERROR_DST_MASK           (0x20U)
+#define DCP_CH1STAT_SET_ERROR_DST_SHIFT          (5U)
+#define DCP_CH1STAT_SET_ERROR_DST(x)             (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_SET_ERROR_DST_SHIFT)) & DCP_CH1STAT_SET_ERROR_DST_MASK)
+#define DCP_CH1STAT_SET_ERROR_PAGEFAULT_MASK     (0x40U)
+#define DCP_CH1STAT_SET_ERROR_PAGEFAULT_SHIFT    (6U)
+#define DCP_CH1STAT_SET_ERROR_PAGEFAULT(x)       (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_SET_ERROR_PAGEFAULT_SHIFT)) & DCP_CH1STAT_SET_ERROR_PAGEFAULT_MASK)
+#define DCP_CH1STAT_SET_ERROR_CODE_MASK          (0xFF0000U)
+#define DCP_CH1STAT_SET_ERROR_CODE_SHIFT         (16U)
+/*! ERROR_CODE
+ *  0b00000001..Error is signalled because the next pointer is 0x00000000.
+ *  0b00000010..Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set.
+ *  0b00000011..Error is signalled because an error was reported when reading/writing the context buffer.
+ *  0b00000100..Error is signalled because an error was reported when reading/writing the payload.
+ *  0b00000101..Error is signalled because the control packet specifies an invalid mode select (for example, blit + hash).
+ */
+#define DCP_CH1STAT_SET_ERROR_CODE(x)            (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_SET_ERROR_CODE_SHIFT)) & DCP_CH1STAT_SET_ERROR_CODE_MASK)
+#define DCP_CH1STAT_SET_TAG_MASK                 (0xFF000000U)
+#define DCP_CH1STAT_SET_TAG_SHIFT                (24U)
+#define DCP_CH1STAT_SET_TAG(x)                   (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_SET_TAG_SHIFT)) & DCP_CH1STAT_SET_TAG_MASK)
+/*! @} */
+
+/*! @name CH1STAT_CLR - DCP channel 1 status register */
+/*! @{ */
+#define DCP_CH1STAT_CLR_RSVD_COMPLETE_MASK       (0x1U)
+#define DCP_CH1STAT_CLR_RSVD_COMPLETE_SHIFT      (0U)
+#define DCP_CH1STAT_CLR_RSVD_COMPLETE(x)         (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_CLR_RSVD_COMPLETE_SHIFT)) & DCP_CH1STAT_CLR_RSVD_COMPLETE_MASK)
+#define DCP_CH1STAT_CLR_HASH_MISMATCH_MASK       (0x2U)
+#define DCP_CH1STAT_CLR_HASH_MISMATCH_SHIFT      (1U)
+#define DCP_CH1STAT_CLR_HASH_MISMATCH(x)         (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_CLR_HASH_MISMATCH_SHIFT)) & DCP_CH1STAT_CLR_HASH_MISMATCH_MASK)
+#define DCP_CH1STAT_CLR_ERROR_SETUP_MASK         (0x4U)
+#define DCP_CH1STAT_CLR_ERROR_SETUP_SHIFT        (2U)
+#define DCP_CH1STAT_CLR_ERROR_SETUP(x)           (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_CLR_ERROR_SETUP_SHIFT)) & DCP_CH1STAT_CLR_ERROR_SETUP_MASK)
+#define DCP_CH1STAT_CLR_ERROR_PACKET_MASK        (0x8U)
+#define DCP_CH1STAT_CLR_ERROR_PACKET_SHIFT       (3U)
+#define DCP_CH1STAT_CLR_ERROR_PACKET(x)          (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_CLR_ERROR_PACKET_SHIFT)) & DCP_CH1STAT_CLR_ERROR_PACKET_MASK)
+#define DCP_CH1STAT_CLR_ERROR_SRC_MASK           (0x10U)
+#define DCP_CH1STAT_CLR_ERROR_SRC_SHIFT          (4U)
+#define DCP_CH1STAT_CLR_ERROR_SRC(x)             (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_CLR_ERROR_SRC_SHIFT)) & DCP_CH1STAT_CLR_ERROR_SRC_MASK)
+#define DCP_CH1STAT_CLR_ERROR_DST_MASK           (0x20U)
+#define DCP_CH1STAT_CLR_ERROR_DST_SHIFT          (5U)
+#define DCP_CH1STAT_CLR_ERROR_DST(x)             (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_CLR_ERROR_DST_SHIFT)) & DCP_CH1STAT_CLR_ERROR_DST_MASK)
+#define DCP_CH1STAT_CLR_ERROR_PAGEFAULT_MASK     (0x40U)
+#define DCP_CH1STAT_CLR_ERROR_PAGEFAULT_SHIFT    (6U)
+#define DCP_CH1STAT_CLR_ERROR_PAGEFAULT(x)       (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_CLR_ERROR_PAGEFAULT_SHIFT)) & DCP_CH1STAT_CLR_ERROR_PAGEFAULT_MASK)
+#define DCP_CH1STAT_CLR_ERROR_CODE_MASK          (0xFF0000U)
+#define DCP_CH1STAT_CLR_ERROR_CODE_SHIFT         (16U)
+/*! ERROR_CODE
+ *  0b00000001..Error is signalled because the next pointer is 0x00000000.
+ *  0b00000010..Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set.
+ *  0b00000011..Error is signalled because an error was reported when reading/writing the context buffer.
+ *  0b00000100..Error is signalled because an error was reported when reading/writing the payload.
+ *  0b00000101..Error is signalled because the control packet specifies an invalid mode select (for example, blit + hash).
+ */
+#define DCP_CH1STAT_CLR_ERROR_CODE(x)            (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_CLR_ERROR_CODE_SHIFT)) & DCP_CH1STAT_CLR_ERROR_CODE_MASK)
+#define DCP_CH1STAT_CLR_TAG_MASK                 (0xFF000000U)
+#define DCP_CH1STAT_CLR_TAG_SHIFT                (24U)
+#define DCP_CH1STAT_CLR_TAG(x)                   (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_CLR_TAG_SHIFT)) & DCP_CH1STAT_CLR_TAG_MASK)
+/*! @} */
+
+/*! @name CH1STAT_TOG - DCP channel 1 status register */
+/*! @{ */
+#define DCP_CH1STAT_TOG_RSVD_COMPLETE_MASK       (0x1U)
+#define DCP_CH1STAT_TOG_RSVD_COMPLETE_SHIFT      (0U)
+#define DCP_CH1STAT_TOG_RSVD_COMPLETE(x)         (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TOG_RSVD_COMPLETE_SHIFT)) & DCP_CH1STAT_TOG_RSVD_COMPLETE_MASK)
+#define DCP_CH1STAT_TOG_HASH_MISMATCH_MASK       (0x2U)
+#define DCP_CH1STAT_TOG_HASH_MISMATCH_SHIFT      (1U)
+#define DCP_CH1STAT_TOG_HASH_MISMATCH(x)         (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TOG_HASH_MISMATCH_SHIFT)) & DCP_CH1STAT_TOG_HASH_MISMATCH_MASK)
+#define DCP_CH1STAT_TOG_ERROR_SETUP_MASK         (0x4U)
+#define DCP_CH1STAT_TOG_ERROR_SETUP_SHIFT        (2U)
+#define DCP_CH1STAT_TOG_ERROR_SETUP(x)           (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TOG_ERROR_SETUP_SHIFT)) & DCP_CH1STAT_TOG_ERROR_SETUP_MASK)
+#define DCP_CH1STAT_TOG_ERROR_PACKET_MASK        (0x8U)
+#define DCP_CH1STAT_TOG_ERROR_PACKET_SHIFT       (3U)
+#define DCP_CH1STAT_TOG_ERROR_PACKET(x)          (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TOG_ERROR_PACKET_SHIFT)) & DCP_CH1STAT_TOG_ERROR_PACKET_MASK)
+#define DCP_CH1STAT_TOG_ERROR_SRC_MASK           (0x10U)
+#define DCP_CH1STAT_TOG_ERROR_SRC_SHIFT          (4U)
+#define DCP_CH1STAT_TOG_ERROR_SRC(x)             (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TOG_ERROR_SRC_SHIFT)) & DCP_CH1STAT_TOG_ERROR_SRC_MASK)
+#define DCP_CH1STAT_TOG_ERROR_DST_MASK           (0x20U)
+#define DCP_CH1STAT_TOG_ERROR_DST_SHIFT          (5U)
+#define DCP_CH1STAT_TOG_ERROR_DST(x)             (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TOG_ERROR_DST_SHIFT)) & DCP_CH1STAT_TOG_ERROR_DST_MASK)
+#define DCP_CH1STAT_TOG_ERROR_PAGEFAULT_MASK     (0x40U)
+#define DCP_CH1STAT_TOG_ERROR_PAGEFAULT_SHIFT    (6U)
+#define DCP_CH1STAT_TOG_ERROR_PAGEFAULT(x)       (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TOG_ERROR_PAGEFAULT_SHIFT)) & DCP_CH1STAT_TOG_ERROR_PAGEFAULT_MASK)
+#define DCP_CH1STAT_TOG_ERROR_CODE_MASK          (0xFF0000U)
+#define DCP_CH1STAT_TOG_ERROR_CODE_SHIFT         (16U)
+/*! ERROR_CODE
+ *  0b00000001..Error is signalled because the next pointer is 0x00000000.
+ *  0b00000010..Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set.
+ *  0b00000011..Error is signalled because an error was reported when reading/writing the context buffer.
+ *  0b00000100..Error is signalled because an error was reported when reading/writing the payload.
+ *  0b00000101..Error is signalled because the control packet specifies an invalid mode select (for example, blit + hash).
+ */
+#define DCP_CH1STAT_TOG_ERROR_CODE(x)            (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TOG_ERROR_CODE_SHIFT)) & DCP_CH1STAT_TOG_ERROR_CODE_MASK)
+#define DCP_CH1STAT_TOG_TAG_MASK                 (0xFF000000U)
+#define DCP_CH1STAT_TOG_TAG_SHIFT                (24U)
+#define DCP_CH1STAT_TOG_TAG(x)                   (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TOG_TAG_SHIFT)) & DCP_CH1STAT_TOG_TAG_MASK)
+/*! @} */
+
 /*! @name CH1OPTS - DCP channel 1 options register */
 /*! @{ */
 #define DCP_CH1OPTS_RECOVERY_TIMER_MASK          (0xFFFFU)
@@ -7156,6 +11328,36 @@ typedef struct {
 #define DCP_CH1OPTS_RSVD(x)                      (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_RSVD_SHIFT)) & DCP_CH1OPTS_RSVD_MASK)
 /*! @} */
 
+/*! @name CH1OPTS_SET - DCP channel 1 options register */
+/*! @{ */
+#define DCP_CH1OPTS_SET_RECOVERY_TIMER_MASK      (0xFFFFU)
+#define DCP_CH1OPTS_SET_RECOVERY_TIMER_SHIFT     (0U)
+#define DCP_CH1OPTS_SET_RECOVERY_TIMER(x)        (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_SET_RECOVERY_TIMER_SHIFT)) & DCP_CH1OPTS_SET_RECOVERY_TIMER_MASK)
+#define DCP_CH1OPTS_SET_RSVD_MASK                (0xFFFF0000U)
+#define DCP_CH1OPTS_SET_RSVD_SHIFT               (16U)
+#define DCP_CH1OPTS_SET_RSVD(x)                  (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_SET_RSVD_SHIFT)) & DCP_CH1OPTS_SET_RSVD_MASK)
+/*! @} */
+
+/*! @name CH1OPTS_CLR - DCP channel 1 options register */
+/*! @{ */
+#define DCP_CH1OPTS_CLR_RECOVERY_TIMER_MASK      (0xFFFFU)
+#define DCP_CH1OPTS_CLR_RECOVERY_TIMER_SHIFT     (0U)
+#define DCP_CH1OPTS_CLR_RECOVERY_TIMER(x)        (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_CLR_RECOVERY_TIMER_SHIFT)) & DCP_CH1OPTS_CLR_RECOVERY_TIMER_MASK)
+#define DCP_CH1OPTS_CLR_RSVD_MASK                (0xFFFF0000U)
+#define DCP_CH1OPTS_CLR_RSVD_SHIFT               (16U)
+#define DCP_CH1OPTS_CLR_RSVD(x)                  (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_CLR_RSVD_SHIFT)) & DCP_CH1OPTS_CLR_RSVD_MASK)
+/*! @} */
+
+/*! @name CH1OPTS_TOG - DCP channel 1 options register */
+/*! @{ */
+#define DCP_CH1OPTS_TOG_RECOVERY_TIMER_MASK      (0xFFFFU)
+#define DCP_CH1OPTS_TOG_RECOVERY_TIMER_SHIFT     (0U)
+#define DCP_CH1OPTS_TOG_RECOVERY_TIMER(x)        (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_TOG_RECOVERY_TIMER_SHIFT)) & DCP_CH1OPTS_TOG_RECOVERY_TIMER_MASK)
+#define DCP_CH1OPTS_TOG_RSVD_MASK                (0xFFFF0000U)
+#define DCP_CH1OPTS_TOG_RSVD_SHIFT               (16U)
+#define DCP_CH1OPTS_TOG_RSVD(x)                  (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_TOG_RSVD_SHIFT)) & DCP_CH1OPTS_TOG_RSVD_MASK)
+/*! @} */
+
 /*! @name CH2CMDPTR - DCP channel 2 command pointer address register */
 /*! @{ */
 #define DCP_CH2CMDPTR_ADDR_MASK                  (0xFFFFFFFFU)
@@ -7198,12 +11400,133 @@ typedef struct {
 #define DCP_CH2STAT_ERROR_PAGEFAULT(x)           (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_PAGEFAULT_SHIFT)) & DCP_CH2STAT_ERROR_PAGEFAULT_MASK)
 #define DCP_CH2STAT_ERROR_CODE_MASK              (0xFF0000U)
 #define DCP_CH2STAT_ERROR_CODE_SHIFT             (16U)
+/*! ERROR_CODE
+ *  0b00000001..Error is signalled because the next pointer is 0x00000000.
+ *  0b00000010..Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set.
+ *  0b00000011..Error is signalled because an error was reported while reading/writing the context buffer.
+ *  0b00000100..Error is signalled because an error was reported while reading/writing the payload.
+ *  0b00000101..Error is signalled because the control packet specifies an invalid mode select (for instance, blit + hash).
+ */
 #define DCP_CH2STAT_ERROR_CODE(x)                (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_CODE_SHIFT)) & DCP_CH2STAT_ERROR_CODE_MASK)
 #define DCP_CH2STAT_TAG_MASK                     (0xFF000000U)
 #define DCP_CH2STAT_TAG_SHIFT                    (24U)
 #define DCP_CH2STAT_TAG(x)                       (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TAG_SHIFT)) & DCP_CH2STAT_TAG_MASK)
 /*! @} */
 
+/*! @name CH2STAT_SET - DCP channel 2 status register */
+/*! @{ */
+#define DCP_CH2STAT_SET_RSVD_COMPLETE_MASK       (0x1U)
+#define DCP_CH2STAT_SET_RSVD_COMPLETE_SHIFT      (0U)
+#define DCP_CH2STAT_SET_RSVD_COMPLETE(x)         (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_SET_RSVD_COMPLETE_SHIFT)) & DCP_CH2STAT_SET_RSVD_COMPLETE_MASK)
+#define DCP_CH2STAT_SET_HASH_MISMATCH_MASK       (0x2U)
+#define DCP_CH2STAT_SET_HASH_MISMATCH_SHIFT      (1U)
+#define DCP_CH2STAT_SET_HASH_MISMATCH(x)         (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_SET_HASH_MISMATCH_SHIFT)) & DCP_CH2STAT_SET_HASH_MISMATCH_MASK)
+#define DCP_CH2STAT_SET_ERROR_SETUP_MASK         (0x4U)
+#define DCP_CH2STAT_SET_ERROR_SETUP_SHIFT        (2U)
+#define DCP_CH2STAT_SET_ERROR_SETUP(x)           (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_SET_ERROR_SETUP_SHIFT)) & DCP_CH2STAT_SET_ERROR_SETUP_MASK)
+#define DCP_CH2STAT_SET_ERROR_PACKET_MASK        (0x8U)
+#define DCP_CH2STAT_SET_ERROR_PACKET_SHIFT       (3U)
+#define DCP_CH2STAT_SET_ERROR_PACKET(x)          (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_SET_ERROR_PACKET_SHIFT)) & DCP_CH2STAT_SET_ERROR_PACKET_MASK)
+#define DCP_CH2STAT_SET_ERROR_SRC_MASK           (0x10U)
+#define DCP_CH2STAT_SET_ERROR_SRC_SHIFT          (4U)
+#define DCP_CH2STAT_SET_ERROR_SRC(x)             (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_SET_ERROR_SRC_SHIFT)) & DCP_CH2STAT_SET_ERROR_SRC_MASK)
+#define DCP_CH2STAT_SET_ERROR_DST_MASK           (0x20U)
+#define DCP_CH2STAT_SET_ERROR_DST_SHIFT          (5U)
+#define DCP_CH2STAT_SET_ERROR_DST(x)             (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_SET_ERROR_DST_SHIFT)) & DCP_CH2STAT_SET_ERROR_DST_MASK)
+#define DCP_CH2STAT_SET_ERROR_PAGEFAULT_MASK     (0x40U)
+#define DCP_CH2STAT_SET_ERROR_PAGEFAULT_SHIFT    (6U)
+#define DCP_CH2STAT_SET_ERROR_PAGEFAULT(x)       (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_SET_ERROR_PAGEFAULT_SHIFT)) & DCP_CH2STAT_SET_ERROR_PAGEFAULT_MASK)
+#define DCP_CH2STAT_SET_ERROR_CODE_MASK          (0xFF0000U)
+#define DCP_CH2STAT_SET_ERROR_CODE_SHIFT         (16U)
+/*! ERROR_CODE
+ *  0b00000001..Error is signalled because the next pointer is 0x00000000.
+ *  0b00000010..Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set.
+ *  0b00000011..Error is signalled because an error was reported while reading/writing the context buffer.
+ *  0b00000100..Error is signalled because an error was reported while reading/writing the payload.
+ *  0b00000101..Error is signalled because the control packet specifies an invalid mode select (for instance, blit + hash).
+ */
+#define DCP_CH2STAT_SET_ERROR_CODE(x)            (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_SET_ERROR_CODE_SHIFT)) & DCP_CH2STAT_SET_ERROR_CODE_MASK)
+#define DCP_CH2STAT_SET_TAG_MASK                 (0xFF000000U)
+#define DCP_CH2STAT_SET_TAG_SHIFT                (24U)
+#define DCP_CH2STAT_SET_TAG(x)                   (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_SET_TAG_SHIFT)) & DCP_CH2STAT_SET_TAG_MASK)
+/*! @} */
+
+/*! @name CH2STAT_CLR - DCP channel 2 status register */
+/*! @{ */
+#define DCP_CH2STAT_CLR_RSVD_COMPLETE_MASK       (0x1U)
+#define DCP_CH2STAT_CLR_RSVD_COMPLETE_SHIFT      (0U)
+#define DCP_CH2STAT_CLR_RSVD_COMPLETE(x)         (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_CLR_RSVD_COMPLETE_SHIFT)) & DCP_CH2STAT_CLR_RSVD_COMPLETE_MASK)
+#define DCP_CH2STAT_CLR_HASH_MISMATCH_MASK       (0x2U)
+#define DCP_CH2STAT_CLR_HASH_MISMATCH_SHIFT      (1U)
+#define DCP_CH2STAT_CLR_HASH_MISMATCH(x)         (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_CLR_HASH_MISMATCH_SHIFT)) & DCP_CH2STAT_CLR_HASH_MISMATCH_MASK)
+#define DCP_CH2STAT_CLR_ERROR_SETUP_MASK         (0x4U)
+#define DCP_CH2STAT_CLR_ERROR_SETUP_SHIFT        (2U)
+#define DCP_CH2STAT_CLR_ERROR_SETUP(x)           (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_CLR_ERROR_SETUP_SHIFT)) & DCP_CH2STAT_CLR_ERROR_SETUP_MASK)
+#define DCP_CH2STAT_CLR_ERROR_PACKET_MASK        (0x8U)
+#define DCP_CH2STAT_CLR_ERROR_PACKET_SHIFT       (3U)
+#define DCP_CH2STAT_CLR_ERROR_PACKET(x)          (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_CLR_ERROR_PACKET_SHIFT)) & DCP_CH2STAT_CLR_ERROR_PACKET_MASK)
+#define DCP_CH2STAT_CLR_ERROR_SRC_MASK           (0x10U)
+#define DCP_CH2STAT_CLR_ERROR_SRC_SHIFT          (4U)
+#define DCP_CH2STAT_CLR_ERROR_SRC(x)             (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_CLR_ERROR_SRC_SHIFT)) & DCP_CH2STAT_CLR_ERROR_SRC_MASK)
+#define DCP_CH2STAT_CLR_ERROR_DST_MASK           (0x20U)
+#define DCP_CH2STAT_CLR_ERROR_DST_SHIFT          (5U)
+#define DCP_CH2STAT_CLR_ERROR_DST(x)             (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_CLR_ERROR_DST_SHIFT)) & DCP_CH2STAT_CLR_ERROR_DST_MASK)
+#define DCP_CH2STAT_CLR_ERROR_PAGEFAULT_MASK     (0x40U)
+#define DCP_CH2STAT_CLR_ERROR_PAGEFAULT_SHIFT    (6U)
+#define DCP_CH2STAT_CLR_ERROR_PAGEFAULT(x)       (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_CLR_ERROR_PAGEFAULT_SHIFT)) & DCP_CH2STAT_CLR_ERROR_PAGEFAULT_MASK)
+#define DCP_CH2STAT_CLR_ERROR_CODE_MASK          (0xFF0000U)
+#define DCP_CH2STAT_CLR_ERROR_CODE_SHIFT         (16U)
+/*! ERROR_CODE
+ *  0b00000001..Error is signalled because the next pointer is 0x00000000.
+ *  0b00000010..Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set.
+ *  0b00000011..Error is signalled because an error was reported while reading/writing the context buffer.
+ *  0b00000100..Error is signalled because an error was reported while reading/writing the payload.
+ *  0b00000101..Error is signalled because the control packet specifies an invalid mode select (for instance, blit + hash).
+ */
+#define DCP_CH2STAT_CLR_ERROR_CODE(x)            (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_CLR_ERROR_CODE_SHIFT)) & DCP_CH2STAT_CLR_ERROR_CODE_MASK)
+#define DCP_CH2STAT_CLR_TAG_MASK                 (0xFF000000U)
+#define DCP_CH2STAT_CLR_TAG_SHIFT                (24U)
+#define DCP_CH2STAT_CLR_TAG(x)                   (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_CLR_TAG_SHIFT)) & DCP_CH2STAT_CLR_TAG_MASK)
+/*! @} */
+
+/*! @name CH2STAT_TOG - DCP channel 2 status register */
+/*! @{ */
+#define DCP_CH2STAT_TOG_RSVD_COMPLETE_MASK       (0x1U)
+#define DCP_CH2STAT_TOG_RSVD_COMPLETE_SHIFT      (0U)
+#define DCP_CH2STAT_TOG_RSVD_COMPLETE(x)         (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TOG_RSVD_COMPLETE_SHIFT)) & DCP_CH2STAT_TOG_RSVD_COMPLETE_MASK)
+#define DCP_CH2STAT_TOG_HASH_MISMATCH_MASK       (0x2U)
+#define DCP_CH2STAT_TOG_HASH_MISMATCH_SHIFT      (1U)
+#define DCP_CH2STAT_TOG_HASH_MISMATCH(x)         (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TOG_HASH_MISMATCH_SHIFT)) & DCP_CH2STAT_TOG_HASH_MISMATCH_MASK)
+#define DCP_CH2STAT_TOG_ERROR_SETUP_MASK         (0x4U)
+#define DCP_CH2STAT_TOG_ERROR_SETUP_SHIFT        (2U)
+#define DCP_CH2STAT_TOG_ERROR_SETUP(x)           (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TOG_ERROR_SETUP_SHIFT)) & DCP_CH2STAT_TOG_ERROR_SETUP_MASK)
+#define DCP_CH2STAT_TOG_ERROR_PACKET_MASK        (0x8U)
+#define DCP_CH2STAT_TOG_ERROR_PACKET_SHIFT       (3U)
+#define DCP_CH2STAT_TOG_ERROR_PACKET(x)          (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TOG_ERROR_PACKET_SHIFT)) & DCP_CH2STAT_TOG_ERROR_PACKET_MASK)
+#define DCP_CH2STAT_TOG_ERROR_SRC_MASK           (0x10U)
+#define DCP_CH2STAT_TOG_ERROR_SRC_SHIFT          (4U)
+#define DCP_CH2STAT_TOG_ERROR_SRC(x)             (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TOG_ERROR_SRC_SHIFT)) & DCP_CH2STAT_TOG_ERROR_SRC_MASK)
+#define DCP_CH2STAT_TOG_ERROR_DST_MASK           (0x20U)
+#define DCP_CH2STAT_TOG_ERROR_DST_SHIFT          (5U)
+#define DCP_CH2STAT_TOG_ERROR_DST(x)             (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TOG_ERROR_DST_SHIFT)) & DCP_CH2STAT_TOG_ERROR_DST_MASK)
+#define DCP_CH2STAT_TOG_ERROR_PAGEFAULT_MASK     (0x40U)
+#define DCP_CH2STAT_TOG_ERROR_PAGEFAULT_SHIFT    (6U)
+#define DCP_CH2STAT_TOG_ERROR_PAGEFAULT(x)       (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TOG_ERROR_PAGEFAULT_SHIFT)) & DCP_CH2STAT_TOG_ERROR_PAGEFAULT_MASK)
+#define DCP_CH2STAT_TOG_ERROR_CODE_MASK          (0xFF0000U)
+#define DCP_CH2STAT_TOG_ERROR_CODE_SHIFT         (16U)
+/*! ERROR_CODE
+ *  0b00000001..Error is signalled because the next pointer is 0x00000000.
+ *  0b00000010..Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set.
+ *  0b00000011..Error is signalled because an error was reported while reading/writing the context buffer.
+ *  0b00000100..Error is signalled because an error was reported while reading/writing the payload.
+ *  0b00000101..Error is signalled because the control packet specifies an invalid mode select (for instance, blit + hash).
+ */
+#define DCP_CH2STAT_TOG_ERROR_CODE(x)            (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TOG_ERROR_CODE_SHIFT)) & DCP_CH2STAT_TOG_ERROR_CODE_MASK)
+#define DCP_CH2STAT_TOG_TAG_MASK                 (0xFF000000U)
+#define DCP_CH2STAT_TOG_TAG_SHIFT                (24U)
+#define DCP_CH2STAT_TOG_TAG(x)                   (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TOG_TAG_SHIFT)) & DCP_CH2STAT_TOG_TAG_MASK)
+/*! @} */
+
 /*! @name CH2OPTS - DCP channel 2 options register */
 /*! @{ */
 #define DCP_CH2OPTS_RECOVERY_TIMER_MASK          (0xFFFFU)
@@ -7214,6 +11537,36 @@ typedef struct {
 #define DCP_CH2OPTS_RSVD(x)                      (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_RSVD_SHIFT)) & DCP_CH2OPTS_RSVD_MASK)
 /*! @} */
 
+/*! @name CH2OPTS_SET - DCP channel 2 options register */
+/*! @{ */
+#define DCP_CH2OPTS_SET_RECOVERY_TIMER_MASK      (0xFFFFU)
+#define DCP_CH2OPTS_SET_RECOVERY_TIMER_SHIFT     (0U)
+#define DCP_CH2OPTS_SET_RECOVERY_TIMER(x)        (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_SET_RECOVERY_TIMER_SHIFT)) & DCP_CH2OPTS_SET_RECOVERY_TIMER_MASK)
+#define DCP_CH2OPTS_SET_RSVD_MASK                (0xFFFF0000U)
+#define DCP_CH2OPTS_SET_RSVD_SHIFT               (16U)
+#define DCP_CH2OPTS_SET_RSVD(x)                  (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_SET_RSVD_SHIFT)) & DCP_CH2OPTS_SET_RSVD_MASK)
+/*! @} */
+
+/*! @name CH2OPTS_CLR - DCP channel 2 options register */
+/*! @{ */
+#define DCP_CH2OPTS_CLR_RECOVERY_TIMER_MASK      (0xFFFFU)
+#define DCP_CH2OPTS_CLR_RECOVERY_TIMER_SHIFT     (0U)
+#define DCP_CH2OPTS_CLR_RECOVERY_TIMER(x)        (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_CLR_RECOVERY_TIMER_SHIFT)) & DCP_CH2OPTS_CLR_RECOVERY_TIMER_MASK)
+#define DCP_CH2OPTS_CLR_RSVD_MASK                (0xFFFF0000U)
+#define DCP_CH2OPTS_CLR_RSVD_SHIFT               (16U)
+#define DCP_CH2OPTS_CLR_RSVD(x)                  (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_CLR_RSVD_SHIFT)) & DCP_CH2OPTS_CLR_RSVD_MASK)
+/*! @} */
+
+/*! @name CH2OPTS_TOG - DCP channel 2 options register */
+/*! @{ */
+#define DCP_CH2OPTS_TOG_RECOVERY_TIMER_MASK      (0xFFFFU)
+#define DCP_CH2OPTS_TOG_RECOVERY_TIMER_SHIFT     (0U)
+#define DCP_CH2OPTS_TOG_RECOVERY_TIMER(x)        (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_TOG_RECOVERY_TIMER_SHIFT)) & DCP_CH2OPTS_TOG_RECOVERY_TIMER_MASK)
+#define DCP_CH2OPTS_TOG_RSVD_MASK                (0xFFFF0000U)
+#define DCP_CH2OPTS_TOG_RSVD_SHIFT               (16U)
+#define DCP_CH2OPTS_TOG_RSVD(x)                  (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_TOG_RSVD_SHIFT)) & DCP_CH2OPTS_TOG_RSVD_MASK)
+/*! @} */
+
 /*! @name CH3CMDPTR - DCP channel 3 command pointer address register */
 /*! @{ */
 #define DCP_CH3CMDPTR_ADDR_MASK                  (0xFFFFFFFFU)
@@ -7256,12 +11609,133 @@ typedef struct {
 #define DCP_CH3STAT_ERROR_PAGEFAULT(x)           (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_PAGEFAULT_SHIFT)) & DCP_CH3STAT_ERROR_PAGEFAULT_MASK)
 #define DCP_CH3STAT_ERROR_CODE_MASK              (0xFF0000U)
 #define DCP_CH3STAT_ERROR_CODE_SHIFT             (16U)
+/*! ERROR_CODE
+ *  0b00000001..Error is signalled because the next pointer is 0x00000000.
+ *  0b00000010..Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set.
+ *  0b00000011..Error is signalled because an error was reported while reading/writing the context buffer.
+ *  0b00000100..Error is signalled because an error was reported while reading/writing the payload.
+ *  0b00000101..Error is signalled because the control packet specifies an invalid mode select (for example, blit + hash).
+ */
 #define DCP_CH3STAT_ERROR_CODE(x)                (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_CODE_SHIFT)) & DCP_CH3STAT_ERROR_CODE_MASK)
 #define DCP_CH3STAT_TAG_MASK                     (0xFF000000U)
 #define DCP_CH3STAT_TAG_SHIFT                    (24U)
 #define DCP_CH3STAT_TAG(x)                       (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TAG_SHIFT)) & DCP_CH3STAT_TAG_MASK)
 /*! @} */
 
+/*! @name CH3STAT_SET - DCP channel 3 status register */
+/*! @{ */
+#define DCP_CH3STAT_SET_RSVD_COMPLETE_MASK       (0x1U)
+#define DCP_CH3STAT_SET_RSVD_COMPLETE_SHIFT      (0U)
+#define DCP_CH3STAT_SET_RSVD_COMPLETE(x)         (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_SET_RSVD_COMPLETE_SHIFT)) & DCP_CH3STAT_SET_RSVD_COMPLETE_MASK)
+#define DCP_CH3STAT_SET_HASH_MISMATCH_MASK       (0x2U)
+#define DCP_CH3STAT_SET_HASH_MISMATCH_SHIFT      (1U)
+#define DCP_CH3STAT_SET_HASH_MISMATCH(x)         (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_SET_HASH_MISMATCH_SHIFT)) & DCP_CH3STAT_SET_HASH_MISMATCH_MASK)
+#define DCP_CH3STAT_SET_ERROR_SETUP_MASK         (0x4U)
+#define DCP_CH3STAT_SET_ERROR_SETUP_SHIFT        (2U)
+#define DCP_CH3STAT_SET_ERROR_SETUP(x)           (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_SET_ERROR_SETUP_SHIFT)) & DCP_CH3STAT_SET_ERROR_SETUP_MASK)
+#define DCP_CH3STAT_SET_ERROR_PACKET_MASK        (0x8U)
+#define DCP_CH3STAT_SET_ERROR_PACKET_SHIFT       (3U)
+#define DCP_CH3STAT_SET_ERROR_PACKET(x)          (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_SET_ERROR_PACKET_SHIFT)) & DCP_CH3STAT_SET_ERROR_PACKET_MASK)
+#define DCP_CH3STAT_SET_ERROR_SRC_MASK           (0x10U)
+#define DCP_CH3STAT_SET_ERROR_SRC_SHIFT          (4U)
+#define DCP_CH3STAT_SET_ERROR_SRC(x)             (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_SET_ERROR_SRC_SHIFT)) & DCP_CH3STAT_SET_ERROR_SRC_MASK)
+#define DCP_CH3STAT_SET_ERROR_DST_MASK           (0x20U)
+#define DCP_CH3STAT_SET_ERROR_DST_SHIFT          (5U)
+#define DCP_CH3STAT_SET_ERROR_DST(x)             (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_SET_ERROR_DST_SHIFT)) & DCP_CH3STAT_SET_ERROR_DST_MASK)
+#define DCP_CH3STAT_SET_ERROR_PAGEFAULT_MASK     (0x40U)
+#define DCP_CH3STAT_SET_ERROR_PAGEFAULT_SHIFT    (6U)
+#define DCP_CH3STAT_SET_ERROR_PAGEFAULT(x)       (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_SET_ERROR_PAGEFAULT_SHIFT)) & DCP_CH3STAT_SET_ERROR_PAGEFAULT_MASK)
+#define DCP_CH3STAT_SET_ERROR_CODE_MASK          (0xFF0000U)
+#define DCP_CH3STAT_SET_ERROR_CODE_SHIFT         (16U)
+/*! ERROR_CODE
+ *  0b00000001..Error is signalled because the next pointer is 0x00000000.
+ *  0b00000010..Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set.
+ *  0b00000011..Error is signalled because an error was reported while reading/writing the context buffer.
+ *  0b00000100..Error is signalled because an error was reported while reading/writing the payload.
+ *  0b00000101..Error is signalled because the control packet specifies an invalid mode select (for example, blit + hash).
+ */
+#define DCP_CH3STAT_SET_ERROR_CODE(x)            (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_SET_ERROR_CODE_SHIFT)) & DCP_CH3STAT_SET_ERROR_CODE_MASK)
+#define DCP_CH3STAT_SET_TAG_MASK                 (0xFF000000U)
+#define DCP_CH3STAT_SET_TAG_SHIFT                (24U)
+#define DCP_CH3STAT_SET_TAG(x)                   (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_SET_TAG_SHIFT)) & DCP_CH3STAT_SET_TAG_MASK)
+/*! @} */
+
+/*! @name CH3STAT_CLR - DCP channel 3 status register */
+/*! @{ */
+#define DCP_CH3STAT_CLR_RSVD_COMPLETE_MASK       (0x1U)
+#define DCP_CH3STAT_CLR_RSVD_COMPLETE_SHIFT      (0U)
+#define DCP_CH3STAT_CLR_RSVD_COMPLETE(x)         (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_CLR_RSVD_COMPLETE_SHIFT)) & DCP_CH3STAT_CLR_RSVD_COMPLETE_MASK)
+#define DCP_CH3STAT_CLR_HASH_MISMATCH_MASK       (0x2U)
+#define DCP_CH3STAT_CLR_HASH_MISMATCH_SHIFT      (1U)
+#define DCP_CH3STAT_CLR_HASH_MISMATCH(x)         (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_CLR_HASH_MISMATCH_SHIFT)) & DCP_CH3STAT_CLR_HASH_MISMATCH_MASK)
+#define DCP_CH3STAT_CLR_ERROR_SETUP_MASK         (0x4U)
+#define DCP_CH3STAT_CLR_ERROR_SETUP_SHIFT        (2U)
+#define DCP_CH3STAT_CLR_ERROR_SETUP(x)           (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_CLR_ERROR_SETUP_SHIFT)) & DCP_CH3STAT_CLR_ERROR_SETUP_MASK)
+#define DCP_CH3STAT_CLR_ERROR_PACKET_MASK        (0x8U)
+#define DCP_CH3STAT_CLR_ERROR_PACKET_SHIFT       (3U)
+#define DCP_CH3STAT_CLR_ERROR_PACKET(x)          (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_CLR_ERROR_PACKET_SHIFT)) & DCP_CH3STAT_CLR_ERROR_PACKET_MASK)
+#define DCP_CH3STAT_CLR_ERROR_SRC_MASK           (0x10U)
+#define DCP_CH3STAT_CLR_ERROR_SRC_SHIFT          (4U)
+#define DCP_CH3STAT_CLR_ERROR_SRC(x)             (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_CLR_ERROR_SRC_SHIFT)) & DCP_CH3STAT_CLR_ERROR_SRC_MASK)
+#define DCP_CH3STAT_CLR_ERROR_DST_MASK           (0x20U)
+#define DCP_CH3STAT_CLR_ERROR_DST_SHIFT          (5U)
+#define DCP_CH3STAT_CLR_ERROR_DST(x)             (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_CLR_ERROR_DST_SHIFT)) & DCP_CH3STAT_CLR_ERROR_DST_MASK)
+#define DCP_CH3STAT_CLR_ERROR_PAGEFAULT_MASK     (0x40U)
+#define DCP_CH3STAT_CLR_ERROR_PAGEFAULT_SHIFT    (6U)
+#define DCP_CH3STAT_CLR_ERROR_PAGEFAULT(x)       (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_CLR_ERROR_PAGEFAULT_SHIFT)) & DCP_CH3STAT_CLR_ERROR_PAGEFAULT_MASK)
+#define DCP_CH3STAT_CLR_ERROR_CODE_MASK          (0xFF0000U)
+#define DCP_CH3STAT_CLR_ERROR_CODE_SHIFT         (16U)
+/*! ERROR_CODE
+ *  0b00000001..Error is signalled because the next pointer is 0x00000000.
+ *  0b00000010..Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set.
+ *  0b00000011..Error is signalled because an error was reported while reading/writing the context buffer.
+ *  0b00000100..Error is signalled because an error was reported while reading/writing the payload.
+ *  0b00000101..Error is signalled because the control packet specifies an invalid mode select (for example, blit + hash).
+ */
+#define DCP_CH3STAT_CLR_ERROR_CODE(x)            (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_CLR_ERROR_CODE_SHIFT)) & DCP_CH3STAT_CLR_ERROR_CODE_MASK)
+#define DCP_CH3STAT_CLR_TAG_MASK                 (0xFF000000U)
+#define DCP_CH3STAT_CLR_TAG_SHIFT                (24U)
+#define DCP_CH3STAT_CLR_TAG(x)                   (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_CLR_TAG_SHIFT)) & DCP_CH3STAT_CLR_TAG_MASK)
+/*! @} */
+
+/*! @name CH3STAT_TOG - DCP channel 3 status register */
+/*! @{ */
+#define DCP_CH3STAT_TOG_RSVD_COMPLETE_MASK       (0x1U)
+#define DCP_CH3STAT_TOG_RSVD_COMPLETE_SHIFT      (0U)
+#define DCP_CH3STAT_TOG_RSVD_COMPLETE(x)         (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TOG_RSVD_COMPLETE_SHIFT)) & DCP_CH3STAT_TOG_RSVD_COMPLETE_MASK)
+#define DCP_CH3STAT_TOG_HASH_MISMATCH_MASK       (0x2U)
+#define DCP_CH3STAT_TOG_HASH_MISMATCH_SHIFT      (1U)
+#define DCP_CH3STAT_TOG_HASH_MISMATCH(x)         (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TOG_HASH_MISMATCH_SHIFT)) & DCP_CH3STAT_TOG_HASH_MISMATCH_MASK)
+#define DCP_CH3STAT_TOG_ERROR_SETUP_MASK         (0x4U)
+#define DCP_CH3STAT_TOG_ERROR_SETUP_SHIFT        (2U)
+#define DCP_CH3STAT_TOG_ERROR_SETUP(x)           (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TOG_ERROR_SETUP_SHIFT)) & DCP_CH3STAT_TOG_ERROR_SETUP_MASK)
+#define DCP_CH3STAT_TOG_ERROR_PACKET_MASK        (0x8U)
+#define DCP_CH3STAT_TOG_ERROR_PACKET_SHIFT       (3U)
+#define DCP_CH3STAT_TOG_ERROR_PACKET(x)          (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TOG_ERROR_PACKET_SHIFT)) & DCP_CH3STAT_TOG_ERROR_PACKET_MASK)
+#define DCP_CH3STAT_TOG_ERROR_SRC_MASK           (0x10U)
+#define DCP_CH3STAT_TOG_ERROR_SRC_SHIFT          (4U)
+#define DCP_CH3STAT_TOG_ERROR_SRC(x)             (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TOG_ERROR_SRC_SHIFT)) & DCP_CH3STAT_TOG_ERROR_SRC_MASK)
+#define DCP_CH3STAT_TOG_ERROR_DST_MASK           (0x20U)
+#define DCP_CH3STAT_TOG_ERROR_DST_SHIFT          (5U)
+#define DCP_CH3STAT_TOG_ERROR_DST(x)             (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TOG_ERROR_DST_SHIFT)) & DCP_CH3STAT_TOG_ERROR_DST_MASK)
+#define DCP_CH3STAT_TOG_ERROR_PAGEFAULT_MASK     (0x40U)
+#define DCP_CH3STAT_TOG_ERROR_PAGEFAULT_SHIFT    (6U)
+#define DCP_CH3STAT_TOG_ERROR_PAGEFAULT(x)       (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TOG_ERROR_PAGEFAULT_SHIFT)) & DCP_CH3STAT_TOG_ERROR_PAGEFAULT_MASK)
+#define DCP_CH3STAT_TOG_ERROR_CODE_MASK          (0xFF0000U)
+#define DCP_CH3STAT_TOG_ERROR_CODE_SHIFT         (16U)
+/*! ERROR_CODE
+ *  0b00000001..Error is signalled because the next pointer is 0x00000000.
+ *  0b00000010..Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set.
+ *  0b00000011..Error is signalled because an error was reported while reading/writing the context buffer.
+ *  0b00000100..Error is signalled because an error was reported while reading/writing the payload.
+ *  0b00000101..Error is signalled because the control packet specifies an invalid mode select (for example, blit + hash).
+ */
+#define DCP_CH3STAT_TOG_ERROR_CODE(x)            (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TOG_ERROR_CODE_SHIFT)) & DCP_CH3STAT_TOG_ERROR_CODE_MASK)
+#define DCP_CH3STAT_TOG_TAG_MASK                 (0xFF000000U)
+#define DCP_CH3STAT_TOG_TAG_SHIFT                (24U)
+#define DCP_CH3STAT_TOG_TAG(x)                   (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TOG_TAG_SHIFT)) & DCP_CH3STAT_TOG_TAG_MASK)
+/*! @} */
+
 /*! @name CH3OPTS - DCP channel 3 options register */
 /*! @{ */
 #define DCP_CH3OPTS_RECOVERY_TIMER_MASK          (0xFFFFU)
@@ -7272,10 +11746,47 @@ typedef struct {
 #define DCP_CH3OPTS_RSVD(x)                      (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_RSVD_SHIFT)) & DCP_CH3OPTS_RSVD_MASK)
 /*! @} */
 
+/*! @name CH3OPTS_SET - DCP channel 3 options register */
+/*! @{ */
+#define DCP_CH3OPTS_SET_RECOVERY_TIMER_MASK      (0xFFFFU)
+#define DCP_CH3OPTS_SET_RECOVERY_TIMER_SHIFT     (0U)
+#define DCP_CH3OPTS_SET_RECOVERY_TIMER(x)        (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_SET_RECOVERY_TIMER_SHIFT)) & DCP_CH3OPTS_SET_RECOVERY_TIMER_MASK)
+#define DCP_CH3OPTS_SET_RSVD_MASK                (0xFFFF0000U)
+#define DCP_CH3OPTS_SET_RSVD_SHIFT               (16U)
+#define DCP_CH3OPTS_SET_RSVD(x)                  (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_SET_RSVD_SHIFT)) & DCP_CH3OPTS_SET_RSVD_MASK)
+/*! @} */
+
+/*! @name CH3OPTS_CLR - DCP channel 3 options register */
+/*! @{ */
+#define DCP_CH3OPTS_CLR_RECOVERY_TIMER_MASK      (0xFFFFU)
+#define DCP_CH3OPTS_CLR_RECOVERY_TIMER_SHIFT     (0U)
+#define DCP_CH3OPTS_CLR_RECOVERY_TIMER(x)        (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_CLR_RECOVERY_TIMER_SHIFT)) & DCP_CH3OPTS_CLR_RECOVERY_TIMER_MASK)
+#define DCP_CH3OPTS_CLR_RSVD_MASK                (0xFFFF0000U)
+#define DCP_CH3OPTS_CLR_RSVD_SHIFT               (16U)
+#define DCP_CH3OPTS_CLR_RSVD(x)                  (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_CLR_RSVD_SHIFT)) & DCP_CH3OPTS_CLR_RSVD_MASK)
+/*! @} */
+
+/*! @name CH3OPTS_TOG - DCP channel 3 options register */
+/*! @{ */
+#define DCP_CH3OPTS_TOG_RECOVERY_TIMER_MASK      (0xFFFFU)
+#define DCP_CH3OPTS_TOG_RECOVERY_TIMER_SHIFT     (0U)
+#define DCP_CH3OPTS_TOG_RECOVERY_TIMER(x)        (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_TOG_RECOVERY_TIMER_SHIFT)) & DCP_CH3OPTS_TOG_RECOVERY_TIMER_MASK)
+#define DCP_CH3OPTS_TOG_RSVD_MASK                (0xFFFF0000U)
+#define DCP_CH3OPTS_TOG_RSVD_SHIFT               (16U)
+#define DCP_CH3OPTS_TOG_RSVD(x)                  (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_TOG_RSVD_SHIFT)) & DCP_CH3OPTS_TOG_RSVD_MASK)
+/*! @} */
+
 /*! @name DBGSELECT - DCP debug select register */
 /*! @{ */
 #define DCP_DBGSELECT_INDEX_MASK                 (0xFFU)
 #define DCP_DBGSELECT_INDEX_SHIFT                (0U)
+/*! INDEX
+ *  0b00000001..CONTROL
+ *  0b00010000..OTPKEY0
+ *  0b00010001..OTPKEY1
+ *  0b00010010..OTPKEY2
+ *  0b00010011..OTPKEY3
+ */
 #define DCP_DBGSELECT_INDEX(x)                   (((uint32_t)(((uint32_t)(x)) << DCP_DBGSELECT_INDEX_SHIFT)) & DCP_DBGSELECT_INDEX_MASK)
 #define DCP_DBGSELECT_RSVD_MASK                  (0xFFFFFF00U)
 #define DCP_DBGSELECT_RSVD_SHIFT                 (8U)
@@ -7444,24 +11955,58 @@ typedef struct {
 /*! @{ */
 #define DMA_CR_EDBG_MASK                         (0x2U)
 #define DMA_CR_EDBG_SHIFT                        (1U)
+/*! EDBG - Enable Debug
+ *  0b0..When in debug mode, the DMA continues to operate.
+ *  0b1..When in debug mode, the DMA stalls the start of a new channel. Executing channels are allowed to
+ *       complete. Channel execution resumes when the system exits debug mode or the EDBG bit is cleared.
+ */
 #define DMA_CR_EDBG(x)                           (((uint32_t)(((uint32_t)(x)) << DMA_CR_EDBG_SHIFT)) & DMA_CR_EDBG_MASK)
 #define DMA_CR_ERCA_MASK                         (0x4U)
 #define DMA_CR_ERCA_SHIFT                        (2U)
+/*! ERCA - Enable Round Robin Channel Arbitration
+ *  0b0..Fixed priority arbitration is used for channel selection within each group.
+ *  0b1..Round robin arbitration is used for channel selection within each group.
+ */
 #define DMA_CR_ERCA(x)                           (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERCA_SHIFT)) & DMA_CR_ERCA_MASK)
 #define DMA_CR_ERGA_MASK                         (0x8U)
 #define DMA_CR_ERGA_SHIFT                        (3U)
+/*! ERGA - Enable Round Robin Group Arbitration
+ *  0b0..Fixed priority arbitration is used for selection among the groups.
+ *  0b1..Round robin arbitration is used for selection among the groups.
+ */
 #define DMA_CR_ERGA(x)                           (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERGA_SHIFT)) & DMA_CR_ERGA_MASK)
 #define DMA_CR_HOE_MASK                          (0x10U)
 #define DMA_CR_HOE_SHIFT                         (4U)
+/*! HOE - Halt On Error
+ *  0b0..Normal operation
+ *  0b1..Any error causes the HALT bit to set. Subsequently, all service requests are ignored until the HALT bit is cleared.
+ */
 #define DMA_CR_HOE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_CR_HOE_SHIFT)) & DMA_CR_HOE_MASK)
 #define DMA_CR_HALT_MASK                         (0x20U)
 #define DMA_CR_HALT_SHIFT                        (5U)
+/*! HALT - Halt DMA Operations
+ *  0b0..Normal operation
+ *  0b1..Stall the start of any new channels. Executing channels are allowed to complete. Channel execution resumes when this bit is cleared.
+ */
 #define DMA_CR_HALT(x)                           (((uint32_t)(((uint32_t)(x)) << DMA_CR_HALT_SHIFT)) & DMA_CR_HALT_MASK)
 #define DMA_CR_CLM_MASK                          (0x40U)
 #define DMA_CR_CLM_SHIFT                         (6U)
+/*! CLM - Continuous Link Mode
+ *  0b0..A minor loop channel link made to itself goes through channel arbitration before being activated again.
+ *  0b1..A minor loop channel link made to itself does not go through channel arbitration before being activated
+ *       again. Upon minor loop completion, the channel activates again if that channel has a minor loop channel
+ *       link enabled and the link channel is itself. This effectively applies the minor loop offsets and restarts the
+ *       next minor loop.
+ */
 #define DMA_CR_CLM(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_CR_CLM_SHIFT)) & DMA_CR_CLM_MASK)
 #define DMA_CR_EMLM_MASK                         (0x80U)
 #define DMA_CR_EMLM_SHIFT                        (7U)
+/*! EMLM - Enable Minor Loop Mapping
+ *  0b0..Disabled. TCDn.word2 is defined as a 32-bit NBYTES field.
+ *  0b1..Enabled. TCDn.word2 is redefined to include individual enable fields, an offset field, and the NBYTES
+ *       field. The individual enable fields allow the minor loop offset to be applied to the source address, the
+ *       destination address, or both. The NBYTES field is reduced when either offset is enabled.
+ */
 #define DMA_CR_EMLM(x)                           (((uint32_t)(((uint32_t)(x)) << DMA_CR_EMLM_SHIFT)) & DMA_CR_EMLM_MASK)
 #define DMA_CR_GRP0PRI_MASK                      (0x100U)
 #define DMA_CR_GRP0PRI_SHIFT                     (8U)
@@ -7471,12 +12016,30 @@ typedef struct {
 #define DMA_CR_GRP1PRI(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP1PRI_SHIFT)) & DMA_CR_GRP1PRI_MASK)
 #define DMA_CR_ECX_MASK                          (0x10000U)
 #define DMA_CR_ECX_SHIFT                         (16U)
+/*! ECX - Error Cancel Transfer
+ *  0b0..Normal operation
+ *  0b1..Cancel the remaining data transfer in the same fashion as the CX bit. Stop the executing channel and
+ *       force the minor loop to finish. The cancel takes effect after the last write of the current read/write
+ *       sequence. The ECX bit clears itself after the cancel is honored. In addition to cancelling the transfer, ECX
+ *       treats the cancel as an error condition, thus updating the Error Status register (DMAx_ES) and generating an
+ *       optional error interrupt.
+ */
 #define DMA_CR_ECX(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_CR_ECX_SHIFT)) & DMA_CR_ECX_MASK)
 #define DMA_CR_CX_MASK                           (0x20000U)
 #define DMA_CR_CX_SHIFT                          (17U)
+/*! CX - Cancel Transfer
+ *  0b0..Normal operation
+ *  0b1..Cancel the remaining data transfer. Stop the executing channel and force the minor loop to finish. The
+ *       cancel takes effect after the last write of the current read/write sequence. The CX bit clears itself after
+ *       the cancel has been honored. This cancel retires the channel normally as if the minor loop was completed.
+ */
 #define DMA_CR_CX(x)                             (((uint32_t)(((uint32_t)(x)) << DMA_CR_CX_SHIFT)) & DMA_CR_CX_MASK)
 #define DMA_CR_ACTIVE_MASK                       (0x80000000U)
 #define DMA_CR_ACTIVE_SHIFT                      (31U)
+/*! ACTIVE - DMA Active Status
+ *  0b0..eDMA is idle.
+ *  0b1..eDMA is executing a channel.
+ */
 #define DMA_CR_ACTIVE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_CR_ACTIVE_SHIFT)) & DMA_CR_ACTIVE_MASK)
 /*! @} */
 
@@ -7484,42 +12047,95 @@ typedef struct {
 /*! @{ */
 #define DMA_ES_DBE_MASK                          (0x1U)
 #define DMA_ES_DBE_SHIFT                         (0U)
+/*! DBE - Destination Bus Error
+ *  0b0..No destination bus error
+ *  0b1..The last recorded error was a bus error on a destination write
+ */
 #define DMA_ES_DBE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_DBE_SHIFT)) & DMA_ES_DBE_MASK)
 #define DMA_ES_SBE_MASK                          (0x2U)
 #define DMA_ES_SBE_SHIFT                         (1U)
+/*! SBE - Source Bus Error
+ *  0b0..No source bus error
+ *  0b1..The last recorded error was a bus error on a source read
+ */
 #define DMA_ES_SBE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_SBE_SHIFT)) & DMA_ES_SBE_MASK)
 #define DMA_ES_SGE_MASK                          (0x4U)
 #define DMA_ES_SGE_SHIFT                         (2U)
+/*! SGE - Scatter/Gather Configuration Error
+ *  0b0..No scatter/gather configuration error
+ *  0b1..The last recorded error was a configuration error detected in the TCDn_DLASTSGA field. This field is
+ *       checked at the beginning of a scatter/gather operation after major loop completion if TCDn_CSR[ESG] is
+ *       enabled. TCDn_DLASTSGA is not on a 32 byte boundary.
+ */
 #define DMA_ES_SGE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_SGE_SHIFT)) & DMA_ES_SGE_MASK)
 #define DMA_ES_NCE_MASK                          (0x8U)
 #define DMA_ES_NCE_SHIFT                         (3U)
+/*! NCE - NBYTES/CITER Configuration Error
+ *  0b0..No NBYTES/CITER configuration error
+ *  0b1..The last recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER fields.
+ *       TCDn_NBYTES is not a multiple of TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or TCDn_CITER[CITER] is equal to zero,
+ *       or TCDn_CITER[ELINK] is not equal to TCDn_BITER[ELINK]
+ */
 #define DMA_ES_NCE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_NCE_SHIFT)) & DMA_ES_NCE_MASK)
 #define DMA_ES_DOE_MASK                          (0x10U)
 #define DMA_ES_DOE_SHIFT                         (4U)
+/*! DOE - Destination Offset Error
+ *  0b0..No destination offset configuration error
+ *  0b1..The last recorded error was a configuration error detected in the TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE].
+ */
 #define DMA_ES_DOE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_DOE_SHIFT)) & DMA_ES_DOE_MASK)
 #define DMA_ES_DAE_MASK                          (0x20U)
 #define DMA_ES_DAE_SHIFT                         (5U)
+/*! DAE - Destination Address Error
+ *  0b0..No destination address configuration error
+ *  0b1..The last recorded error was a configuration error detected in the TCDn_DADDR field. TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE].
+ */
 #define DMA_ES_DAE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_DAE_SHIFT)) & DMA_ES_DAE_MASK)
 #define DMA_ES_SOE_MASK                          (0x40U)
 #define DMA_ES_SOE_SHIFT                         (6U)
+/*! SOE - Source Offset Error
+ *  0b0..No source offset configuration error
+ *  0b1..The last recorded error was a configuration error detected in the TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE].
+ */
 #define DMA_ES_SOE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_SOE_SHIFT)) & DMA_ES_SOE_MASK)
 #define DMA_ES_SAE_MASK                          (0x80U)
 #define DMA_ES_SAE_SHIFT                         (7U)
+/*! SAE - Source Address Error
+ *  0b0..No source address configuration error.
+ *  0b1..The last recorded error was a configuration error detected in the TCDn_SADDR field. TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE].
+ */
 #define DMA_ES_SAE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_SAE_SHIFT)) & DMA_ES_SAE_MASK)
 #define DMA_ES_ERRCHN_MASK                       (0x1F00U)
 #define DMA_ES_ERRCHN_SHIFT                      (8U)
 #define DMA_ES_ERRCHN(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ES_ERRCHN_SHIFT)) & DMA_ES_ERRCHN_MASK)
 #define DMA_ES_CPE_MASK                          (0x4000U)
 #define DMA_ES_CPE_SHIFT                         (14U)
+/*! CPE - Channel Priority Error
+ *  0b0..No channel priority error
+ *  0b1..The last recorded error was a configuration error in the channel priorities within a group. Channel
+ *       priorities within a group are not unique.
+ */
 #define DMA_ES_CPE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_CPE_SHIFT)) & DMA_ES_CPE_MASK)
 #define DMA_ES_GPE_MASK                          (0x8000U)
 #define DMA_ES_GPE_SHIFT                         (15U)
+/*! GPE - Group Priority Error
+ *  0b0..No group priority error
+ *  0b1..The last recorded error was a configuration error among the group priorities. All group priorities are not unique.
+ */
 #define DMA_ES_GPE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_GPE_SHIFT)) & DMA_ES_GPE_MASK)
 #define DMA_ES_ECX_MASK                          (0x10000U)
 #define DMA_ES_ECX_SHIFT                         (16U)
+/*! ECX - Transfer Canceled
+ *  0b0..No canceled transfers
+ *  0b1..The last recorded entry was a canceled transfer by the error cancel transfer input
+ */
 #define DMA_ES_ECX(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_ECX_SHIFT)) & DMA_ES_ECX_MASK)
 #define DMA_ES_VLD_MASK                          (0x80000000U)
 #define DMA_ES_VLD_SHIFT                         (31U)
+/*! VLD - VLD
+ *  0b0..No ERR bits are set.
+ *  0b1..At least one ERR bit is set indicating a valid error exists that has not been cleared.
+ */
 #define DMA_ES_VLD(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_VLD_SHIFT)) & DMA_ES_VLD_MASK)
 /*! @} */
 
@@ -7527,99 +12143,227 @@ typedef struct {
 /*! @{ */
 #define DMA_ERQ_ERQ0_MASK                        (0x1U)
 #define DMA_ERQ_ERQ0_SHIFT                       (0U)
+/*! ERQ0 - Enable DMA Request 0
+ *  0b0..The DMA request signal for the corresponding channel is disabled
+ *  0b1..The DMA request signal for the corresponding channel is enabled
+ */
 #define DMA_ERQ_ERQ0(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ0_SHIFT)) & DMA_ERQ_ERQ0_MASK)
 #define DMA_ERQ_ERQ1_MASK                        (0x2U)
 #define DMA_ERQ_ERQ1_SHIFT                       (1U)
+/*! ERQ1 - Enable DMA Request 1
+ *  0b0..The DMA request signal for the corresponding channel is disabled
+ *  0b1..The DMA request signal for the corresponding channel is enabled
+ */
 #define DMA_ERQ_ERQ1(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ1_SHIFT)) & DMA_ERQ_ERQ1_MASK)
 #define DMA_ERQ_ERQ2_MASK                        (0x4U)
 #define DMA_ERQ_ERQ2_SHIFT                       (2U)
+/*! ERQ2 - Enable DMA Request 2
+ *  0b0..The DMA request signal for the corresponding channel is disabled
+ *  0b1..The DMA request signal for the corresponding channel is enabled
+ */
 #define DMA_ERQ_ERQ2(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ2_SHIFT)) & DMA_ERQ_ERQ2_MASK)
 #define DMA_ERQ_ERQ3_MASK                        (0x8U)
 #define DMA_ERQ_ERQ3_SHIFT                       (3U)
+/*! ERQ3 - Enable DMA Request 3
+ *  0b0..The DMA request signal for the corresponding channel is disabled
+ *  0b1..The DMA request signal for the corresponding channel is enabled
+ */
 #define DMA_ERQ_ERQ3(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ3_SHIFT)) & DMA_ERQ_ERQ3_MASK)
 #define DMA_ERQ_ERQ4_MASK                        (0x10U)
 #define DMA_ERQ_ERQ4_SHIFT                       (4U)
+/*! ERQ4 - Enable DMA Request 4
+ *  0b0..The DMA request signal for the corresponding channel is disabled
+ *  0b1..The DMA request signal for the corresponding channel is enabled
+ */
 #define DMA_ERQ_ERQ4(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ4_SHIFT)) & DMA_ERQ_ERQ4_MASK)
 #define DMA_ERQ_ERQ5_MASK                        (0x20U)
 #define DMA_ERQ_ERQ5_SHIFT                       (5U)
+/*! ERQ5 - Enable DMA Request 5
+ *  0b0..The DMA request signal for the corresponding channel is disabled
+ *  0b1..The DMA request signal for the corresponding channel is enabled
+ */
 #define DMA_ERQ_ERQ5(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ5_SHIFT)) & DMA_ERQ_ERQ5_MASK)
 #define DMA_ERQ_ERQ6_MASK                        (0x40U)
 #define DMA_ERQ_ERQ6_SHIFT                       (6U)
+/*! ERQ6 - Enable DMA Request 6
+ *  0b0..The DMA request signal for the corresponding channel is disabled
+ *  0b1..The DMA request signal for the corresponding channel is enabled
+ */
 #define DMA_ERQ_ERQ6(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ6_SHIFT)) & DMA_ERQ_ERQ6_MASK)
 #define DMA_ERQ_ERQ7_MASK                        (0x80U)
 #define DMA_ERQ_ERQ7_SHIFT                       (7U)
+/*! ERQ7 - Enable DMA Request 7
+ *  0b0..The DMA request signal for the corresponding channel is disabled
+ *  0b1..The DMA request signal for the corresponding channel is enabled
+ */
 #define DMA_ERQ_ERQ7(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ7_SHIFT)) & DMA_ERQ_ERQ7_MASK)
 #define DMA_ERQ_ERQ8_MASK                        (0x100U)
 #define DMA_ERQ_ERQ8_SHIFT                       (8U)
+/*! ERQ8 - Enable DMA Request 8
+ *  0b0..The DMA request signal for the corresponding channel is disabled
+ *  0b1..The DMA request signal for the corresponding channel is enabled
+ */
 #define DMA_ERQ_ERQ8(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ8_SHIFT)) & DMA_ERQ_ERQ8_MASK)
 #define DMA_ERQ_ERQ9_MASK                        (0x200U)
 #define DMA_ERQ_ERQ9_SHIFT                       (9U)
+/*! ERQ9 - Enable DMA Request 9
+ *  0b0..The DMA request signal for the corresponding channel is disabled
+ *  0b1..The DMA request signal for the corresponding channel is enabled
+ */
 #define DMA_ERQ_ERQ9(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ9_SHIFT)) & DMA_ERQ_ERQ9_MASK)
 #define DMA_ERQ_ERQ10_MASK                       (0x400U)
 #define DMA_ERQ_ERQ10_SHIFT                      (10U)
+/*! ERQ10 - Enable DMA Request 10
+ *  0b0..The DMA request signal for the corresponding channel is disabled
+ *  0b1..The DMA request signal for the corresponding channel is enabled
+ */
 #define DMA_ERQ_ERQ10(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ10_SHIFT)) & DMA_ERQ_ERQ10_MASK)
 #define DMA_ERQ_ERQ11_MASK                       (0x800U)
 #define DMA_ERQ_ERQ11_SHIFT                      (11U)
+/*! ERQ11 - Enable DMA Request 11
+ *  0b0..The DMA request signal for the corresponding channel is disabled
+ *  0b1..The DMA request signal for the corresponding channel is enabled
+ */
 #define DMA_ERQ_ERQ11(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ11_SHIFT)) & DMA_ERQ_ERQ11_MASK)
 #define DMA_ERQ_ERQ12_MASK                       (0x1000U)
 #define DMA_ERQ_ERQ12_SHIFT                      (12U)
+/*! ERQ12 - Enable DMA Request 12
+ *  0b0..The DMA request signal for the corresponding channel is disabled
+ *  0b1..The DMA request signal for the corresponding channel is enabled
+ */
 #define DMA_ERQ_ERQ12(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ12_SHIFT)) & DMA_ERQ_ERQ12_MASK)
 #define DMA_ERQ_ERQ13_MASK                       (0x2000U)
 #define DMA_ERQ_ERQ13_SHIFT                      (13U)
+/*! ERQ13 - Enable DMA Request 13
+ *  0b0..The DMA request signal for the corresponding channel is disabled
+ *  0b1..The DMA request signal for the corresponding channel is enabled
+ */
 #define DMA_ERQ_ERQ13(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ13_SHIFT)) & DMA_ERQ_ERQ13_MASK)
 #define DMA_ERQ_ERQ14_MASK                       (0x4000U)
 #define DMA_ERQ_ERQ14_SHIFT                      (14U)
+/*! ERQ14 - Enable DMA Request 14
+ *  0b0..The DMA request signal for the corresponding channel is disabled
+ *  0b1..The DMA request signal for the corresponding channel is enabled
+ */
 #define DMA_ERQ_ERQ14(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ14_SHIFT)) & DMA_ERQ_ERQ14_MASK)
 #define DMA_ERQ_ERQ15_MASK                       (0x8000U)
 #define DMA_ERQ_ERQ15_SHIFT                      (15U)
+/*! ERQ15 - Enable DMA Request 15
+ *  0b0..The DMA request signal for the corresponding channel is disabled
+ *  0b1..The DMA request signal for the corresponding channel is enabled
+ */
 #define DMA_ERQ_ERQ15(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ15_SHIFT)) & DMA_ERQ_ERQ15_MASK)
 #define DMA_ERQ_ERQ16_MASK                       (0x10000U)
 #define DMA_ERQ_ERQ16_SHIFT                      (16U)
+/*! ERQ16 - Enable DMA Request 16
+ *  0b0..The DMA request signal for the corresponding channel is disabled
+ *  0b1..The DMA request signal for the corresponding channel is enabled
+ */
 #define DMA_ERQ_ERQ16(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ16_SHIFT)) & DMA_ERQ_ERQ16_MASK)
 #define DMA_ERQ_ERQ17_MASK                       (0x20000U)
 #define DMA_ERQ_ERQ17_SHIFT                      (17U)
+/*! ERQ17 - Enable DMA Request 17
+ *  0b0..The DMA request signal for the corresponding channel is disabled
+ *  0b1..The DMA request signal for the corresponding channel is enabled
+ */
 #define DMA_ERQ_ERQ17(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ17_SHIFT)) & DMA_ERQ_ERQ17_MASK)
 #define DMA_ERQ_ERQ18_MASK                       (0x40000U)
 #define DMA_ERQ_ERQ18_SHIFT                      (18U)
+/*! ERQ18 - Enable DMA Request 18
+ *  0b0..The DMA request signal for the corresponding channel is disabled
+ *  0b1..The DMA request signal for the corresponding channel is enabled
+ */
 #define DMA_ERQ_ERQ18(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ18_SHIFT)) & DMA_ERQ_ERQ18_MASK)
 #define DMA_ERQ_ERQ19_MASK                       (0x80000U)
 #define DMA_ERQ_ERQ19_SHIFT                      (19U)
+/*! ERQ19 - Enable DMA Request 19
+ *  0b0..The DMA request signal for the corresponding channel is disabled
+ *  0b1..The DMA request signal for the corresponding channel is enabled
+ */
 #define DMA_ERQ_ERQ19(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ19_SHIFT)) & DMA_ERQ_ERQ19_MASK)
 #define DMA_ERQ_ERQ20_MASK                       (0x100000U)
 #define DMA_ERQ_ERQ20_SHIFT                      (20U)
+/*! ERQ20 - Enable DMA Request 20
+ *  0b0..The DMA request signal for the corresponding channel is disabled
+ *  0b1..The DMA request signal for the corresponding channel is enabled
+ */
 #define DMA_ERQ_ERQ20(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ20_SHIFT)) & DMA_ERQ_ERQ20_MASK)
 #define DMA_ERQ_ERQ21_MASK                       (0x200000U)
 #define DMA_ERQ_ERQ21_SHIFT                      (21U)
+/*! ERQ21 - Enable DMA Request 21
+ *  0b0..The DMA request signal for the corresponding channel is disabled
+ *  0b1..The DMA request signal for the corresponding channel is enabled
+ */
 #define DMA_ERQ_ERQ21(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ21_SHIFT)) & DMA_ERQ_ERQ21_MASK)
 #define DMA_ERQ_ERQ22_MASK                       (0x400000U)
 #define DMA_ERQ_ERQ22_SHIFT                      (22U)
+/*! ERQ22 - Enable DMA Request 22
+ *  0b0..The DMA request signal for the corresponding channel is disabled
+ *  0b1..The DMA request signal for the corresponding channel is enabled
+ */
 #define DMA_ERQ_ERQ22(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ22_SHIFT)) & DMA_ERQ_ERQ22_MASK)
 #define DMA_ERQ_ERQ23_MASK                       (0x800000U)
 #define DMA_ERQ_ERQ23_SHIFT                      (23U)
+/*! ERQ23 - Enable DMA Request 23
+ *  0b0..The DMA request signal for the corresponding channel is disabled
+ *  0b1..The DMA request signal for the corresponding channel is enabled
+ */
 #define DMA_ERQ_ERQ23(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ23_SHIFT)) & DMA_ERQ_ERQ23_MASK)
 #define DMA_ERQ_ERQ24_MASK                       (0x1000000U)
 #define DMA_ERQ_ERQ24_SHIFT                      (24U)
+/*! ERQ24 - Enable DMA Request 24
+ *  0b0..The DMA request signal for the corresponding channel is disabled
+ *  0b1..The DMA request signal for the corresponding channel is enabled
+ */
 #define DMA_ERQ_ERQ24(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ24_SHIFT)) & DMA_ERQ_ERQ24_MASK)
 #define DMA_ERQ_ERQ25_MASK                       (0x2000000U)
 #define DMA_ERQ_ERQ25_SHIFT                      (25U)
+/*! ERQ25 - Enable DMA Request 25
+ *  0b0..The DMA request signal for the corresponding channel is disabled
+ *  0b1..The DMA request signal for the corresponding channel is enabled
+ */
 #define DMA_ERQ_ERQ25(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ25_SHIFT)) & DMA_ERQ_ERQ25_MASK)
 #define DMA_ERQ_ERQ26_MASK                       (0x4000000U)
 #define DMA_ERQ_ERQ26_SHIFT                      (26U)
+/*! ERQ26 - Enable DMA Request 26
+ *  0b0..The DMA request signal for the corresponding channel is disabled
+ *  0b1..The DMA request signal for the corresponding channel is enabled
+ */
 #define DMA_ERQ_ERQ26(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ26_SHIFT)) & DMA_ERQ_ERQ26_MASK)
 #define DMA_ERQ_ERQ27_MASK                       (0x8000000U)
 #define DMA_ERQ_ERQ27_SHIFT                      (27U)
+/*! ERQ27 - Enable DMA Request 27
+ *  0b0..The DMA request signal for the corresponding channel is disabled
+ *  0b1..The DMA request signal for the corresponding channel is enabled
+ */
 #define DMA_ERQ_ERQ27(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ27_SHIFT)) & DMA_ERQ_ERQ27_MASK)
 #define DMA_ERQ_ERQ28_MASK                       (0x10000000U)
 #define DMA_ERQ_ERQ28_SHIFT                      (28U)
+/*! ERQ28 - Enable DMA Request 28
+ *  0b0..The DMA request signal for the corresponding channel is disabled
+ *  0b1..The DMA request signal for the corresponding channel is enabled
+ */
 #define DMA_ERQ_ERQ28(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ28_SHIFT)) & DMA_ERQ_ERQ28_MASK)
 #define DMA_ERQ_ERQ29_MASK                       (0x20000000U)
 #define DMA_ERQ_ERQ29_SHIFT                      (29U)
+/*! ERQ29 - Enable DMA Request 29
+ *  0b0..The DMA request signal for the corresponding channel is disabled
+ *  0b1..The DMA request signal for the corresponding channel is enabled
+ */
 #define DMA_ERQ_ERQ29(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ29_SHIFT)) & DMA_ERQ_ERQ29_MASK)
 #define DMA_ERQ_ERQ30_MASK                       (0x40000000U)
 #define DMA_ERQ_ERQ30_SHIFT                      (30U)
+/*! ERQ30 - Enable DMA Request 30
+ *  0b0..The DMA request signal for the corresponding channel is disabled
+ *  0b1..The DMA request signal for the corresponding channel is enabled
+ */
 #define DMA_ERQ_ERQ30(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ30_SHIFT)) & DMA_ERQ_ERQ30_MASK)
 #define DMA_ERQ_ERQ31_MASK                       (0x80000000U)
 #define DMA_ERQ_ERQ31_SHIFT                      (31U)
+/*! ERQ31 - Enable DMA Request 31
+ *  0b0..The DMA request signal for the corresponding channel is disabled
+ *  0b1..The DMA request signal for the corresponding channel is enabled
+ */
 #define DMA_ERQ_ERQ31(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ31_SHIFT)) & DMA_ERQ_ERQ31_MASK)
 /*! @} */
 
@@ -7627,99 +12371,227 @@ typedef struct {
 /*! @{ */
 #define DMA_EEI_EEI0_MASK                        (0x1U)
 #define DMA_EEI_EEI0_SHIFT                       (0U)
+/*! EEI0 - Enable Error Interrupt 0
+ *  0b0..The error signal for corresponding channel does not generate an error interrupt
+ *  0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
+ */
 #define DMA_EEI_EEI0(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI0_SHIFT)) & DMA_EEI_EEI0_MASK)
 #define DMA_EEI_EEI1_MASK                        (0x2U)
 #define DMA_EEI_EEI1_SHIFT                       (1U)
+/*! EEI1 - Enable Error Interrupt 1
+ *  0b0..The error signal for corresponding channel does not generate an error interrupt
+ *  0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
+ */
 #define DMA_EEI_EEI1(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI1_SHIFT)) & DMA_EEI_EEI1_MASK)
 #define DMA_EEI_EEI2_MASK                        (0x4U)
 #define DMA_EEI_EEI2_SHIFT                       (2U)
+/*! EEI2 - Enable Error Interrupt 2
+ *  0b0..The error signal for corresponding channel does not generate an error interrupt
+ *  0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
+ */
 #define DMA_EEI_EEI2(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI2_SHIFT)) & DMA_EEI_EEI2_MASK)
 #define DMA_EEI_EEI3_MASK                        (0x8U)
 #define DMA_EEI_EEI3_SHIFT                       (3U)
+/*! EEI3 - Enable Error Interrupt 3
+ *  0b0..The error signal for corresponding channel does not generate an error interrupt
+ *  0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
+ */
 #define DMA_EEI_EEI3(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI3_SHIFT)) & DMA_EEI_EEI3_MASK)
 #define DMA_EEI_EEI4_MASK                        (0x10U)
 #define DMA_EEI_EEI4_SHIFT                       (4U)
+/*! EEI4 - Enable Error Interrupt 4
+ *  0b0..The error signal for corresponding channel does not generate an error interrupt
+ *  0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
+ */
 #define DMA_EEI_EEI4(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI4_SHIFT)) & DMA_EEI_EEI4_MASK)
 #define DMA_EEI_EEI5_MASK                        (0x20U)
 #define DMA_EEI_EEI5_SHIFT                       (5U)
+/*! EEI5 - Enable Error Interrupt 5
+ *  0b0..The error signal for corresponding channel does not generate an error interrupt
+ *  0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
+ */
 #define DMA_EEI_EEI5(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI5_SHIFT)) & DMA_EEI_EEI5_MASK)
 #define DMA_EEI_EEI6_MASK                        (0x40U)
 #define DMA_EEI_EEI6_SHIFT                       (6U)
+/*! EEI6 - Enable Error Interrupt 6
+ *  0b0..The error signal for corresponding channel does not generate an error interrupt
+ *  0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
+ */
 #define DMA_EEI_EEI6(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI6_SHIFT)) & DMA_EEI_EEI6_MASK)
 #define DMA_EEI_EEI7_MASK                        (0x80U)
 #define DMA_EEI_EEI7_SHIFT                       (7U)
+/*! EEI7 - Enable Error Interrupt 7
+ *  0b0..The error signal for corresponding channel does not generate an error interrupt
+ *  0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
+ */
 #define DMA_EEI_EEI7(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI7_SHIFT)) & DMA_EEI_EEI7_MASK)
 #define DMA_EEI_EEI8_MASK                        (0x100U)
 #define DMA_EEI_EEI8_SHIFT                       (8U)
+/*! EEI8 - Enable Error Interrupt 8
+ *  0b0..The error signal for corresponding channel does not generate an error interrupt
+ *  0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
+ */
 #define DMA_EEI_EEI8(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI8_SHIFT)) & DMA_EEI_EEI8_MASK)
 #define DMA_EEI_EEI9_MASK                        (0x200U)
 #define DMA_EEI_EEI9_SHIFT                       (9U)
+/*! EEI9 - Enable Error Interrupt 9
+ *  0b0..The error signal for corresponding channel does not generate an error interrupt
+ *  0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
+ */
 #define DMA_EEI_EEI9(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI9_SHIFT)) & DMA_EEI_EEI9_MASK)
 #define DMA_EEI_EEI10_MASK                       (0x400U)
 #define DMA_EEI_EEI10_SHIFT                      (10U)
+/*! EEI10 - Enable Error Interrupt 10
+ *  0b0..The error signal for corresponding channel does not generate an error interrupt
+ *  0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
+ */
 #define DMA_EEI_EEI10(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI10_SHIFT)) & DMA_EEI_EEI10_MASK)
 #define DMA_EEI_EEI11_MASK                       (0x800U)
 #define DMA_EEI_EEI11_SHIFT                      (11U)
+/*! EEI11 - Enable Error Interrupt 11
+ *  0b0..The error signal for corresponding channel does not generate an error interrupt
+ *  0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
+ */
 #define DMA_EEI_EEI11(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI11_SHIFT)) & DMA_EEI_EEI11_MASK)
 #define DMA_EEI_EEI12_MASK                       (0x1000U)
 #define DMA_EEI_EEI12_SHIFT                      (12U)
+/*! EEI12 - Enable Error Interrupt 12
+ *  0b0..The error signal for corresponding channel does not generate an error interrupt
+ *  0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
+ */
 #define DMA_EEI_EEI12(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI12_SHIFT)) & DMA_EEI_EEI12_MASK)
 #define DMA_EEI_EEI13_MASK                       (0x2000U)
 #define DMA_EEI_EEI13_SHIFT                      (13U)
+/*! EEI13 - Enable Error Interrupt 13
+ *  0b0..The error signal for corresponding channel does not generate an error interrupt
+ *  0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
+ */
 #define DMA_EEI_EEI13(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI13_SHIFT)) & DMA_EEI_EEI13_MASK)
 #define DMA_EEI_EEI14_MASK                       (0x4000U)
 #define DMA_EEI_EEI14_SHIFT                      (14U)
+/*! EEI14 - Enable Error Interrupt 14
+ *  0b0..The error signal for corresponding channel does not generate an error interrupt
+ *  0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
+ */
 #define DMA_EEI_EEI14(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI14_SHIFT)) & DMA_EEI_EEI14_MASK)
 #define DMA_EEI_EEI15_MASK                       (0x8000U)
 #define DMA_EEI_EEI15_SHIFT                      (15U)
+/*! EEI15 - Enable Error Interrupt 15
+ *  0b0..The error signal for corresponding channel does not generate an error interrupt
+ *  0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
+ */
 #define DMA_EEI_EEI15(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI15_SHIFT)) & DMA_EEI_EEI15_MASK)
 #define DMA_EEI_EEI16_MASK                       (0x10000U)
 #define DMA_EEI_EEI16_SHIFT                      (16U)
+/*! EEI16 - Enable Error Interrupt 16
+ *  0b0..The error signal for corresponding channel does not generate an error interrupt
+ *  0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
+ */
 #define DMA_EEI_EEI16(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI16_SHIFT)) & DMA_EEI_EEI16_MASK)
 #define DMA_EEI_EEI17_MASK                       (0x20000U)
 #define DMA_EEI_EEI17_SHIFT                      (17U)
+/*! EEI17 - Enable Error Interrupt 17
+ *  0b0..The error signal for corresponding channel does not generate an error interrupt
+ *  0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
+ */
 #define DMA_EEI_EEI17(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI17_SHIFT)) & DMA_EEI_EEI17_MASK)
 #define DMA_EEI_EEI18_MASK                       (0x40000U)
 #define DMA_EEI_EEI18_SHIFT                      (18U)
+/*! EEI18 - Enable Error Interrupt 18
+ *  0b0..The error signal for corresponding channel does not generate an error interrupt
+ *  0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
+ */
 #define DMA_EEI_EEI18(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI18_SHIFT)) & DMA_EEI_EEI18_MASK)
 #define DMA_EEI_EEI19_MASK                       (0x80000U)
 #define DMA_EEI_EEI19_SHIFT                      (19U)
+/*! EEI19 - Enable Error Interrupt 19
+ *  0b0..The error signal for corresponding channel does not generate an error interrupt
+ *  0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
+ */
 #define DMA_EEI_EEI19(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI19_SHIFT)) & DMA_EEI_EEI19_MASK)
 #define DMA_EEI_EEI20_MASK                       (0x100000U)
 #define DMA_EEI_EEI20_SHIFT                      (20U)
+/*! EEI20 - Enable Error Interrupt 20
+ *  0b0..The error signal for corresponding channel does not generate an error interrupt
+ *  0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
+ */
 #define DMA_EEI_EEI20(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI20_SHIFT)) & DMA_EEI_EEI20_MASK)
 #define DMA_EEI_EEI21_MASK                       (0x200000U)
 #define DMA_EEI_EEI21_SHIFT                      (21U)
+/*! EEI21 - Enable Error Interrupt 21
+ *  0b0..The error signal for corresponding channel does not generate an error interrupt
+ *  0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
+ */
 #define DMA_EEI_EEI21(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI21_SHIFT)) & DMA_EEI_EEI21_MASK)
 #define DMA_EEI_EEI22_MASK                       (0x400000U)
 #define DMA_EEI_EEI22_SHIFT                      (22U)
+/*! EEI22 - Enable Error Interrupt 22
+ *  0b0..The error signal for corresponding channel does not generate an error interrupt
+ *  0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
+ */
 #define DMA_EEI_EEI22(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI22_SHIFT)) & DMA_EEI_EEI22_MASK)
 #define DMA_EEI_EEI23_MASK                       (0x800000U)
 #define DMA_EEI_EEI23_SHIFT                      (23U)
+/*! EEI23 - Enable Error Interrupt 23
+ *  0b0..The error signal for corresponding channel does not generate an error interrupt
+ *  0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
+ */
 #define DMA_EEI_EEI23(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI23_SHIFT)) & DMA_EEI_EEI23_MASK)
 #define DMA_EEI_EEI24_MASK                       (0x1000000U)
 #define DMA_EEI_EEI24_SHIFT                      (24U)
+/*! EEI24 - Enable Error Interrupt 24
+ *  0b0..The error signal for corresponding channel does not generate an error interrupt
+ *  0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
+ */
 #define DMA_EEI_EEI24(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI24_SHIFT)) & DMA_EEI_EEI24_MASK)
 #define DMA_EEI_EEI25_MASK                       (0x2000000U)
 #define DMA_EEI_EEI25_SHIFT                      (25U)
+/*! EEI25 - Enable Error Interrupt 25
+ *  0b0..The error signal for corresponding channel does not generate an error interrupt
+ *  0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
+ */
 #define DMA_EEI_EEI25(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI25_SHIFT)) & DMA_EEI_EEI25_MASK)
 #define DMA_EEI_EEI26_MASK                       (0x4000000U)
 #define DMA_EEI_EEI26_SHIFT                      (26U)
+/*! EEI26 - Enable Error Interrupt 26
+ *  0b0..The error signal for corresponding channel does not generate an error interrupt
+ *  0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
+ */
 #define DMA_EEI_EEI26(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI26_SHIFT)) & DMA_EEI_EEI26_MASK)
 #define DMA_EEI_EEI27_MASK                       (0x8000000U)
 #define DMA_EEI_EEI27_SHIFT                      (27U)
+/*! EEI27 - Enable Error Interrupt 27
+ *  0b0..The error signal for corresponding channel does not generate an error interrupt
+ *  0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
+ */
 #define DMA_EEI_EEI27(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI27_SHIFT)) & DMA_EEI_EEI27_MASK)
 #define DMA_EEI_EEI28_MASK                       (0x10000000U)
 #define DMA_EEI_EEI28_SHIFT                      (28U)
+/*! EEI28 - Enable Error Interrupt 28
+ *  0b0..The error signal for corresponding channel does not generate an error interrupt
+ *  0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
+ */
 #define DMA_EEI_EEI28(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI28_SHIFT)) & DMA_EEI_EEI28_MASK)
 #define DMA_EEI_EEI29_MASK                       (0x20000000U)
 #define DMA_EEI_EEI29_SHIFT                      (29U)
+/*! EEI29 - Enable Error Interrupt 29
+ *  0b0..The error signal for corresponding channel does not generate an error interrupt
+ *  0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
+ */
 #define DMA_EEI_EEI29(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI29_SHIFT)) & DMA_EEI_EEI29_MASK)
 #define DMA_EEI_EEI30_MASK                       (0x40000000U)
 #define DMA_EEI_EEI30_SHIFT                      (30U)
+/*! EEI30 - Enable Error Interrupt 30
+ *  0b0..The error signal for corresponding channel does not generate an error interrupt
+ *  0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
+ */
 #define DMA_EEI_EEI30(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI30_SHIFT)) & DMA_EEI_EEI30_MASK)
 #define DMA_EEI_EEI31_MASK                       (0x80000000U)
 #define DMA_EEI_EEI31_SHIFT                      (31U)
+/*! EEI31 - Enable Error Interrupt 31
+ *  0b0..The error signal for corresponding channel does not generate an error interrupt
+ *  0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
+ */
 #define DMA_EEI_EEI31(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI31_SHIFT)) & DMA_EEI_EEI31_MASK)
 /*! @} */
 
@@ -7730,9 +12602,17 @@ typedef struct {
 #define DMA_CEEI_CEEI(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CEEI_SHIFT)) & DMA_CEEI_CEEI_MASK)
 #define DMA_CEEI_CAEE_MASK                       (0x40U)
 #define DMA_CEEI_CAEE_SHIFT                      (6U)
+/*! CAEE - Clear All Enable Error Interrupts
+ *  0b0..Clear only the EEI bit specified in the CEEI field
+ *  0b1..Clear all bits in EEI
+ */
 #define DMA_CEEI_CAEE(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CAEE_SHIFT)) & DMA_CEEI_CAEE_MASK)
 #define DMA_CEEI_NOP_MASK                        (0x80U)
 #define DMA_CEEI_NOP_SHIFT                       (7U)
+/*! NOP - No Op enable
+ *  0b0..Normal operation
+ *  0b1..No operation, ignore the other bits in this register
+ */
 #define DMA_CEEI_NOP(x)                          (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_NOP_SHIFT)) & DMA_CEEI_NOP_MASK)
 /*! @} */
 
@@ -7743,9 +12623,17 @@ typedef struct {
 #define DMA_SEEI_SEEI(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SEEI_SHIFT)) & DMA_SEEI_SEEI_MASK)
 #define DMA_SEEI_SAEE_MASK                       (0x40U)
 #define DMA_SEEI_SAEE_SHIFT                      (6U)
+/*! SAEE - Sets All Enable Error Interrupts
+ *  0b0..Set only the EEI bit specified in the SEEI field.
+ *  0b1..Sets all bits in EEI
+ */
 #define DMA_SEEI_SAEE(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SAEE_SHIFT)) & DMA_SEEI_SAEE_MASK)
 #define DMA_SEEI_NOP_MASK                        (0x80U)
 #define DMA_SEEI_NOP_SHIFT                       (7U)
+/*! NOP - No Op enable
+ *  0b0..Normal operation
+ *  0b1..No operation, ignore the other bits in this register
+ */
 #define DMA_SEEI_NOP(x)                          (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_NOP_SHIFT)) & DMA_SEEI_NOP_MASK)
 /*! @} */
 
@@ -7756,9 +12644,17 @@ typedef struct {
 #define DMA_CERQ_CERQ(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CERQ_SHIFT)) & DMA_CERQ_CERQ_MASK)
 #define DMA_CERQ_CAER_MASK                       (0x40U)
 #define DMA_CERQ_CAER_SHIFT                      (6U)
+/*! CAER - Clear All Enable Requests
+ *  0b0..Clear only the ERQ bit specified in the CERQ field
+ *  0b1..Clear all bits in ERQ
+ */
 #define DMA_CERQ_CAER(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CAER_SHIFT)) & DMA_CERQ_CAER_MASK)
 #define DMA_CERQ_NOP_MASK                        (0x80U)
 #define DMA_CERQ_NOP_SHIFT                       (7U)
+/*! NOP - No Op enable
+ *  0b0..Normal operation
+ *  0b1..No operation, ignore the other bits in this register
+ */
 #define DMA_CERQ_NOP(x)                          (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_NOP_SHIFT)) & DMA_CERQ_NOP_MASK)
 /*! @} */
 
@@ -7769,9 +12665,17 @@ typedef struct {
 #define DMA_SERQ_SERQ(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SERQ_SHIFT)) & DMA_SERQ_SERQ_MASK)
 #define DMA_SERQ_SAER_MASK                       (0x40U)
 #define DMA_SERQ_SAER_SHIFT                      (6U)
+/*! SAER - Set All Enable Requests
+ *  0b0..Set only the ERQ bit specified in the SERQ field
+ *  0b1..Set all bits in ERQ
+ */
 #define DMA_SERQ_SAER(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SAER_SHIFT)) & DMA_SERQ_SAER_MASK)
 #define DMA_SERQ_NOP_MASK                        (0x80U)
 #define DMA_SERQ_NOP_SHIFT                       (7U)
+/*! NOP - No Op enable
+ *  0b0..Normal operation
+ *  0b1..No operation, ignore the other bits in this register
+ */
 #define DMA_SERQ_NOP(x)                          (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_NOP_SHIFT)) & DMA_SERQ_NOP_MASK)
 /*! @} */
 
@@ -7782,9 +12686,17 @@ typedef struct {
 #define DMA_CDNE_CDNE(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CDNE_SHIFT)) & DMA_CDNE_CDNE_MASK)
 #define DMA_CDNE_CADN_MASK                       (0x40U)
 #define DMA_CDNE_CADN_SHIFT                      (6U)
+/*! CADN - Clears All DONE Bits
+ *  0b0..Clears only the TCDn_CSR[DONE] bit specified in the CDNE field
+ *  0b1..Clears all bits in TCDn_CSR[DONE]
+ */
 #define DMA_CDNE_CADN(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CADN_SHIFT)) & DMA_CDNE_CADN_MASK)
 #define DMA_CDNE_NOP_MASK                        (0x80U)
 #define DMA_CDNE_NOP_SHIFT                       (7U)
+/*! NOP - No Op enable
+ *  0b0..Normal operation
+ *  0b1..No operation, ignore the other bits in this register
+ */
 #define DMA_CDNE_NOP(x)                          (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_NOP_SHIFT)) & DMA_CDNE_NOP_MASK)
 /*! @} */
 
@@ -7795,9 +12707,17 @@ typedef struct {
 #define DMA_SSRT_SSRT(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SSRT_SHIFT)) & DMA_SSRT_SSRT_MASK)
 #define DMA_SSRT_SAST_MASK                       (0x40U)
 #define DMA_SSRT_SAST_SHIFT                      (6U)
+/*! SAST - Set All START Bits (activates all channels)
+ *  0b0..Set only the TCDn_CSR[START] bit specified in the SSRT field
+ *  0b1..Set all bits in TCDn_CSR[START]
+ */
 #define DMA_SSRT_SAST(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SAST_SHIFT)) & DMA_SSRT_SAST_MASK)
 #define DMA_SSRT_NOP_MASK                        (0x80U)
 #define DMA_SSRT_NOP_SHIFT                       (7U)
+/*! NOP - No Op enable
+ *  0b0..Normal operation
+ *  0b1..No operation, ignore the other bits in this register
+ */
 #define DMA_SSRT_NOP(x)                          (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_NOP_SHIFT)) & DMA_SSRT_NOP_MASK)
 /*! @} */
 
@@ -7808,9 +12728,17 @@ typedef struct {
 #define DMA_CERR_CERR(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CERR_SHIFT)) & DMA_CERR_CERR_MASK)
 #define DMA_CERR_CAEI_MASK                       (0x40U)
 #define DMA_CERR_CAEI_SHIFT                      (6U)
+/*! CAEI - Clear All Error Indicators
+ *  0b0..Clear only the ERR bit specified in the CERR field
+ *  0b1..Clear all bits in ERR
+ */
 #define DMA_CERR_CAEI(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CAEI_SHIFT)) & DMA_CERR_CAEI_MASK)
 #define DMA_CERR_NOP_MASK                        (0x80U)
 #define DMA_CERR_NOP_SHIFT                       (7U)
+/*! NOP - No Op enable
+ *  0b0..Normal operation
+ *  0b1..No operation, ignore the other bits in this register
+ */
 #define DMA_CERR_NOP(x)                          (((uint8_t)(((uint8_t)(x)) << DMA_CERR_NOP_SHIFT)) & DMA_CERR_NOP_MASK)
 /*! @} */
 
@@ -7821,9 +12749,17 @@ typedef struct {
 #define DMA_CINT_CINT(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CINT_SHIFT)) & DMA_CINT_CINT_MASK)
 #define DMA_CINT_CAIR_MASK                       (0x40U)
 #define DMA_CINT_CAIR_SHIFT                      (6U)
+/*! CAIR - Clear All Interrupt Requests
+ *  0b0..Clear only the INT bit specified in the CINT field
+ *  0b1..Clear all bits in INT
+ */
 #define DMA_CINT_CAIR(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CAIR_SHIFT)) & DMA_CINT_CAIR_MASK)
 #define DMA_CINT_NOP_MASK                        (0x80U)
 #define DMA_CINT_NOP_SHIFT                       (7U)
+/*! NOP - No Op enable
+ *  0b0..Normal operation
+ *  0b1..No operation, ignore the other bits in this register
+ */
 #define DMA_CINT_NOP(x)                          (((uint8_t)(((uint8_t)(x)) << DMA_CINT_NOP_SHIFT)) & DMA_CINT_NOP_MASK)
 /*! @} */
 
@@ -7831,99 +12767,227 @@ typedef struct {
 /*! @{ */
 #define DMA_INT_INT0_MASK                        (0x1U)
 #define DMA_INT_INT0_SHIFT                       (0U)
+/*! INT0 - Interrupt Request 0
+ *  0b0..The interrupt request for corresponding channel is cleared
+ *  0b1..The interrupt request for corresponding channel is active
+ */
 #define DMA_INT_INT0(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT0_SHIFT)) & DMA_INT_INT0_MASK)
 #define DMA_INT_INT1_MASK                        (0x2U)
 #define DMA_INT_INT1_SHIFT                       (1U)
+/*! INT1 - Interrupt Request 1
+ *  0b0..The interrupt request for corresponding channel is cleared
+ *  0b1..The interrupt request for corresponding channel is active
+ */
 #define DMA_INT_INT1(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT1_SHIFT)) & DMA_INT_INT1_MASK)
 #define DMA_INT_INT2_MASK                        (0x4U)
 #define DMA_INT_INT2_SHIFT                       (2U)
+/*! INT2 - Interrupt Request 2
+ *  0b0..The interrupt request for corresponding channel is cleared
+ *  0b1..The interrupt request for corresponding channel is active
+ */
 #define DMA_INT_INT2(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT2_SHIFT)) & DMA_INT_INT2_MASK)
 #define DMA_INT_INT3_MASK                        (0x8U)
 #define DMA_INT_INT3_SHIFT                       (3U)
+/*! INT3 - Interrupt Request 3
+ *  0b0..The interrupt request for corresponding channel is cleared
+ *  0b1..The interrupt request for corresponding channel is active
+ */
 #define DMA_INT_INT3(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT3_SHIFT)) & DMA_INT_INT3_MASK)
 #define DMA_INT_INT4_MASK                        (0x10U)
 #define DMA_INT_INT4_SHIFT                       (4U)
+/*! INT4 - Interrupt Request 4
+ *  0b0..The interrupt request for corresponding channel is cleared
+ *  0b1..The interrupt request for corresponding channel is active
+ */
 #define DMA_INT_INT4(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT4_SHIFT)) & DMA_INT_INT4_MASK)
 #define DMA_INT_INT5_MASK                        (0x20U)
 #define DMA_INT_INT5_SHIFT                       (5U)
+/*! INT5 - Interrupt Request 5
+ *  0b0..The interrupt request for corresponding channel is cleared
+ *  0b1..The interrupt request for corresponding channel is active
+ */
 #define DMA_INT_INT5(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT5_SHIFT)) & DMA_INT_INT5_MASK)
 #define DMA_INT_INT6_MASK                        (0x40U)
 #define DMA_INT_INT6_SHIFT                       (6U)
+/*! INT6 - Interrupt Request 6
+ *  0b0..The interrupt request for corresponding channel is cleared
+ *  0b1..The interrupt request for corresponding channel is active
+ */
 #define DMA_INT_INT6(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT6_SHIFT)) & DMA_INT_INT6_MASK)
 #define DMA_INT_INT7_MASK                        (0x80U)
 #define DMA_INT_INT7_SHIFT                       (7U)
+/*! INT7 - Interrupt Request 7
+ *  0b0..The interrupt request for corresponding channel is cleared
+ *  0b1..The interrupt request for corresponding channel is active
+ */
 #define DMA_INT_INT7(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT7_SHIFT)) & DMA_INT_INT7_MASK)
 #define DMA_INT_INT8_MASK                        (0x100U)
 #define DMA_INT_INT8_SHIFT                       (8U)
+/*! INT8 - Interrupt Request 8
+ *  0b0..The interrupt request for corresponding channel is cleared
+ *  0b1..The interrupt request for corresponding channel is active
+ */
 #define DMA_INT_INT8(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT8_SHIFT)) & DMA_INT_INT8_MASK)
 #define DMA_INT_INT9_MASK                        (0x200U)
 #define DMA_INT_INT9_SHIFT                       (9U)
+/*! INT9 - Interrupt Request 9
+ *  0b0..The interrupt request for corresponding channel is cleared
+ *  0b1..The interrupt request for corresponding channel is active
+ */
 #define DMA_INT_INT9(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT9_SHIFT)) & DMA_INT_INT9_MASK)
 #define DMA_INT_INT10_MASK                       (0x400U)
 #define DMA_INT_INT10_SHIFT                      (10U)
+/*! INT10 - Interrupt Request 10
+ *  0b0..The interrupt request for corresponding channel is cleared
+ *  0b1..The interrupt request for corresponding channel is active
+ */
 #define DMA_INT_INT10(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT10_SHIFT)) & DMA_INT_INT10_MASK)
 #define DMA_INT_INT11_MASK                       (0x800U)
 #define DMA_INT_INT11_SHIFT                      (11U)
+/*! INT11 - Interrupt Request 11
+ *  0b0..The interrupt request for corresponding channel is cleared
+ *  0b1..The interrupt request for corresponding channel is active
+ */
 #define DMA_INT_INT11(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT11_SHIFT)) & DMA_INT_INT11_MASK)
 #define DMA_INT_INT12_MASK                       (0x1000U)
 #define DMA_INT_INT12_SHIFT                      (12U)
+/*! INT12 - Interrupt Request 12
+ *  0b0..The interrupt request for corresponding channel is cleared
+ *  0b1..The interrupt request for corresponding channel is active
+ */
 #define DMA_INT_INT12(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT12_SHIFT)) & DMA_INT_INT12_MASK)
 #define DMA_INT_INT13_MASK                       (0x2000U)
 #define DMA_INT_INT13_SHIFT                      (13U)
+/*! INT13 - Interrupt Request 13
+ *  0b0..The interrupt request for corresponding channel is cleared
+ *  0b1..The interrupt request for corresponding channel is active
+ */
 #define DMA_INT_INT13(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT13_SHIFT)) & DMA_INT_INT13_MASK)
 #define DMA_INT_INT14_MASK                       (0x4000U)
 #define DMA_INT_INT14_SHIFT                      (14U)
+/*! INT14 - Interrupt Request 14
+ *  0b0..The interrupt request for corresponding channel is cleared
+ *  0b1..The interrupt request for corresponding channel is active
+ */
 #define DMA_INT_INT14(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT14_SHIFT)) & DMA_INT_INT14_MASK)
 #define DMA_INT_INT15_MASK                       (0x8000U)
 #define DMA_INT_INT15_SHIFT                      (15U)
+/*! INT15 - Interrupt Request 15
+ *  0b0..The interrupt request for corresponding channel is cleared
+ *  0b1..The interrupt request for corresponding channel is active
+ */
 #define DMA_INT_INT15(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT15_SHIFT)) & DMA_INT_INT15_MASK)
 #define DMA_INT_INT16_MASK                       (0x10000U)
 #define DMA_INT_INT16_SHIFT                      (16U)
+/*! INT16 - Interrupt Request 16
+ *  0b0..The interrupt request for corresponding channel is cleared
+ *  0b1..The interrupt request for corresponding channel is active
+ */
 #define DMA_INT_INT16(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT16_SHIFT)) & DMA_INT_INT16_MASK)
 #define DMA_INT_INT17_MASK                       (0x20000U)
 #define DMA_INT_INT17_SHIFT                      (17U)
+/*! INT17 - Interrupt Request 17
+ *  0b0..The interrupt request for corresponding channel is cleared
+ *  0b1..The interrupt request for corresponding channel is active
+ */
 #define DMA_INT_INT17(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT17_SHIFT)) & DMA_INT_INT17_MASK)
 #define DMA_INT_INT18_MASK                       (0x40000U)
 #define DMA_INT_INT18_SHIFT                      (18U)
+/*! INT18 - Interrupt Request 18
+ *  0b0..The interrupt request for corresponding channel is cleared
+ *  0b1..The interrupt request for corresponding channel is active
+ */
 #define DMA_INT_INT18(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT18_SHIFT)) & DMA_INT_INT18_MASK)
 #define DMA_INT_INT19_MASK                       (0x80000U)
 #define DMA_INT_INT19_SHIFT                      (19U)
+/*! INT19 - Interrupt Request 19
+ *  0b0..The interrupt request for corresponding channel is cleared
+ *  0b1..The interrupt request for corresponding channel is active
+ */
 #define DMA_INT_INT19(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT19_SHIFT)) & DMA_INT_INT19_MASK)
 #define DMA_INT_INT20_MASK                       (0x100000U)
 #define DMA_INT_INT20_SHIFT                      (20U)
+/*! INT20 - Interrupt Request 20
+ *  0b0..The interrupt request for corresponding channel is cleared
+ *  0b1..The interrupt request for corresponding channel is active
+ */
 #define DMA_INT_INT20(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT20_SHIFT)) & DMA_INT_INT20_MASK)
 #define DMA_INT_INT21_MASK                       (0x200000U)
 #define DMA_INT_INT21_SHIFT                      (21U)
+/*! INT21 - Interrupt Request 21
+ *  0b0..The interrupt request for corresponding channel is cleared
+ *  0b1..The interrupt request for corresponding channel is active
+ */
 #define DMA_INT_INT21(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT21_SHIFT)) & DMA_INT_INT21_MASK)
 #define DMA_INT_INT22_MASK                       (0x400000U)
 #define DMA_INT_INT22_SHIFT                      (22U)
+/*! INT22 - Interrupt Request 22
+ *  0b0..The interrupt request for corresponding channel is cleared
+ *  0b1..The interrupt request for corresponding channel is active
+ */
 #define DMA_INT_INT22(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT22_SHIFT)) & DMA_INT_INT22_MASK)
 #define DMA_INT_INT23_MASK                       (0x800000U)
 #define DMA_INT_INT23_SHIFT                      (23U)
+/*! INT23 - Interrupt Request 23
+ *  0b0..The interrupt request for corresponding channel is cleared
+ *  0b1..The interrupt request for corresponding channel is active
+ */
 #define DMA_INT_INT23(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT23_SHIFT)) & DMA_INT_INT23_MASK)
 #define DMA_INT_INT24_MASK                       (0x1000000U)
 #define DMA_INT_INT24_SHIFT                      (24U)
+/*! INT24 - Interrupt Request 24
+ *  0b0..The interrupt request for corresponding channel is cleared
+ *  0b1..The interrupt request for corresponding channel is active
+ */
 #define DMA_INT_INT24(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT24_SHIFT)) & DMA_INT_INT24_MASK)
 #define DMA_INT_INT25_MASK                       (0x2000000U)
 #define DMA_INT_INT25_SHIFT                      (25U)
+/*! INT25 - Interrupt Request 25
+ *  0b0..The interrupt request for corresponding channel is cleared
+ *  0b1..The interrupt request for corresponding channel is active
+ */
 #define DMA_INT_INT25(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT25_SHIFT)) & DMA_INT_INT25_MASK)
 #define DMA_INT_INT26_MASK                       (0x4000000U)
 #define DMA_INT_INT26_SHIFT                      (26U)
+/*! INT26 - Interrupt Request 26
+ *  0b0..The interrupt request for corresponding channel is cleared
+ *  0b1..The interrupt request for corresponding channel is active
+ */
 #define DMA_INT_INT26(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT26_SHIFT)) & DMA_INT_INT26_MASK)
 #define DMA_INT_INT27_MASK                       (0x8000000U)
 #define DMA_INT_INT27_SHIFT                      (27U)
+/*! INT27 - Interrupt Request 27
+ *  0b0..The interrupt request for corresponding channel is cleared
+ *  0b1..The interrupt request for corresponding channel is active
+ */
 #define DMA_INT_INT27(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT27_SHIFT)) & DMA_INT_INT27_MASK)
 #define DMA_INT_INT28_MASK                       (0x10000000U)
 #define DMA_INT_INT28_SHIFT                      (28U)
+/*! INT28 - Interrupt Request 28
+ *  0b0..The interrupt request for corresponding channel is cleared
+ *  0b1..The interrupt request for corresponding channel is active
+ */
 #define DMA_INT_INT28(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT28_SHIFT)) & DMA_INT_INT28_MASK)
 #define DMA_INT_INT29_MASK                       (0x20000000U)
 #define DMA_INT_INT29_SHIFT                      (29U)
+/*! INT29 - Interrupt Request 29
+ *  0b0..The interrupt request for corresponding channel is cleared
+ *  0b1..The interrupt request for corresponding channel is active
+ */
 #define DMA_INT_INT29(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT29_SHIFT)) & DMA_INT_INT29_MASK)
 #define DMA_INT_INT30_MASK                       (0x40000000U)
 #define DMA_INT_INT30_SHIFT                      (30U)
+/*! INT30 - Interrupt Request 30
+ *  0b0..The interrupt request for corresponding channel is cleared
+ *  0b1..The interrupt request for corresponding channel is active
+ */
 #define DMA_INT_INT30(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT30_SHIFT)) & DMA_INT_INT30_MASK)
 #define DMA_INT_INT31_MASK                       (0x80000000U)
 #define DMA_INT_INT31_SHIFT                      (31U)
+/*! INT31 - Interrupt Request 31
+ *  0b0..The interrupt request for corresponding channel is cleared
+ *  0b1..The interrupt request for corresponding channel is active
+ */
 #define DMA_INT_INT31(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT31_SHIFT)) & DMA_INT_INT31_MASK)
 /*! @} */
 
@@ -7931,99 +12995,227 @@ typedef struct {
 /*! @{ */
 #define DMA_ERR_ERR0_MASK                        (0x1U)
 #define DMA_ERR_ERR0_SHIFT                       (0U)
+/*! ERR0 - Error In Channel 0
+ *  0b0..An error in this channel has not occurred
+ *  0b1..An error in this channel has occurred
+ */
 #define DMA_ERR_ERR0(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR0_SHIFT)) & DMA_ERR_ERR0_MASK)
 #define DMA_ERR_ERR1_MASK                        (0x2U)
 #define DMA_ERR_ERR1_SHIFT                       (1U)
+/*! ERR1 - Error In Channel 1
+ *  0b0..An error in this channel has not occurred
+ *  0b1..An error in this channel has occurred
+ */
 #define DMA_ERR_ERR1(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR1_SHIFT)) & DMA_ERR_ERR1_MASK)
 #define DMA_ERR_ERR2_MASK                        (0x4U)
 #define DMA_ERR_ERR2_SHIFT                       (2U)
+/*! ERR2 - Error In Channel 2
+ *  0b0..An error in this channel has not occurred
+ *  0b1..An error in this channel has occurred
+ */
 #define DMA_ERR_ERR2(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR2_SHIFT)) & DMA_ERR_ERR2_MASK)
 #define DMA_ERR_ERR3_MASK                        (0x8U)
 #define DMA_ERR_ERR3_SHIFT                       (3U)
+/*! ERR3 - Error In Channel 3
+ *  0b0..An error in this channel has not occurred
+ *  0b1..An error in this channel has occurred
+ */
 #define DMA_ERR_ERR3(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR3_SHIFT)) & DMA_ERR_ERR3_MASK)
 #define DMA_ERR_ERR4_MASK                        (0x10U)
 #define DMA_ERR_ERR4_SHIFT                       (4U)
+/*! ERR4 - Error In Channel 4
+ *  0b0..An error in this channel has not occurred
+ *  0b1..An error in this channel has occurred
+ */
 #define DMA_ERR_ERR4(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR4_SHIFT)) & DMA_ERR_ERR4_MASK)
 #define DMA_ERR_ERR5_MASK                        (0x20U)
 #define DMA_ERR_ERR5_SHIFT                       (5U)
+/*! ERR5 - Error In Channel 5
+ *  0b0..An error in this channel has not occurred
+ *  0b1..An error in this channel has occurred
+ */
 #define DMA_ERR_ERR5(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR5_SHIFT)) & DMA_ERR_ERR5_MASK)
 #define DMA_ERR_ERR6_MASK                        (0x40U)
 #define DMA_ERR_ERR6_SHIFT                       (6U)
+/*! ERR6 - Error In Channel 6
+ *  0b0..An error in this channel has not occurred
+ *  0b1..An error in this channel has occurred
+ */
 #define DMA_ERR_ERR6(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR6_SHIFT)) & DMA_ERR_ERR6_MASK)
 #define DMA_ERR_ERR7_MASK                        (0x80U)
 #define DMA_ERR_ERR7_SHIFT                       (7U)
+/*! ERR7 - Error In Channel 7
+ *  0b0..An error in this channel has not occurred
+ *  0b1..An error in this channel has occurred
+ */
 #define DMA_ERR_ERR7(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR7_SHIFT)) & DMA_ERR_ERR7_MASK)
 #define DMA_ERR_ERR8_MASK                        (0x100U)
 #define DMA_ERR_ERR8_SHIFT                       (8U)
+/*! ERR8 - Error In Channel 8
+ *  0b0..An error in this channel has not occurred
+ *  0b1..An error in this channel has occurred
+ */
 #define DMA_ERR_ERR8(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR8_SHIFT)) & DMA_ERR_ERR8_MASK)
 #define DMA_ERR_ERR9_MASK                        (0x200U)
 #define DMA_ERR_ERR9_SHIFT                       (9U)
+/*! ERR9 - Error In Channel 9
+ *  0b0..An error in this channel has not occurred
+ *  0b1..An error in this channel has occurred
+ */
 #define DMA_ERR_ERR9(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR9_SHIFT)) & DMA_ERR_ERR9_MASK)
 #define DMA_ERR_ERR10_MASK                       (0x400U)
 #define DMA_ERR_ERR10_SHIFT                      (10U)
+/*! ERR10 - Error In Channel 10
+ *  0b0..An error in this channel has not occurred
+ *  0b1..An error in this channel has occurred
+ */
 #define DMA_ERR_ERR10(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR10_SHIFT)) & DMA_ERR_ERR10_MASK)
 #define DMA_ERR_ERR11_MASK                       (0x800U)
 #define DMA_ERR_ERR11_SHIFT                      (11U)
+/*! ERR11 - Error In Channel 11
+ *  0b0..An error in this channel has not occurred
+ *  0b1..An error in this channel has occurred
+ */
 #define DMA_ERR_ERR11(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR11_SHIFT)) & DMA_ERR_ERR11_MASK)
 #define DMA_ERR_ERR12_MASK                       (0x1000U)
 #define DMA_ERR_ERR12_SHIFT                      (12U)
+/*! ERR12 - Error In Channel 12
+ *  0b0..An error in this channel has not occurred
+ *  0b1..An error in this channel has occurred
+ */
 #define DMA_ERR_ERR12(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR12_SHIFT)) & DMA_ERR_ERR12_MASK)
 #define DMA_ERR_ERR13_MASK                       (0x2000U)
 #define DMA_ERR_ERR13_SHIFT                      (13U)
+/*! ERR13 - Error In Channel 13
+ *  0b0..An error in this channel has not occurred
+ *  0b1..An error in this channel has occurred
+ */
 #define DMA_ERR_ERR13(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR13_SHIFT)) & DMA_ERR_ERR13_MASK)
 #define DMA_ERR_ERR14_MASK                       (0x4000U)
 #define DMA_ERR_ERR14_SHIFT                      (14U)
+/*! ERR14 - Error In Channel 14
+ *  0b0..An error in this channel has not occurred
+ *  0b1..An error in this channel has occurred
+ */
 #define DMA_ERR_ERR14(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR14_SHIFT)) & DMA_ERR_ERR14_MASK)
 #define DMA_ERR_ERR15_MASK                       (0x8000U)
 #define DMA_ERR_ERR15_SHIFT                      (15U)
+/*! ERR15 - Error In Channel 15
+ *  0b0..An error in this channel has not occurred
+ *  0b1..An error in this channel has occurred
+ */
 #define DMA_ERR_ERR15(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR15_SHIFT)) & DMA_ERR_ERR15_MASK)
 #define DMA_ERR_ERR16_MASK                       (0x10000U)
 #define DMA_ERR_ERR16_SHIFT                      (16U)
+/*! ERR16 - Error In Channel 16
+ *  0b0..An error in this channel has not occurred
+ *  0b1..An error in this channel has occurred
+ */
 #define DMA_ERR_ERR16(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR16_SHIFT)) & DMA_ERR_ERR16_MASK)
 #define DMA_ERR_ERR17_MASK                       (0x20000U)
 #define DMA_ERR_ERR17_SHIFT                      (17U)
+/*! ERR17 - Error In Channel 17
+ *  0b0..An error in this channel has not occurred
+ *  0b1..An error in this channel has occurred
+ */
 #define DMA_ERR_ERR17(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR17_SHIFT)) & DMA_ERR_ERR17_MASK)
 #define DMA_ERR_ERR18_MASK                       (0x40000U)
 #define DMA_ERR_ERR18_SHIFT                      (18U)
+/*! ERR18 - Error In Channel 18
+ *  0b0..An error in this channel has not occurred
+ *  0b1..An error in this channel has occurred
+ */
 #define DMA_ERR_ERR18(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR18_SHIFT)) & DMA_ERR_ERR18_MASK)
 #define DMA_ERR_ERR19_MASK                       (0x80000U)
 #define DMA_ERR_ERR19_SHIFT                      (19U)
+/*! ERR19 - Error In Channel 19
+ *  0b0..An error in this channel has not occurred
+ *  0b1..An error in this channel has occurred
+ */
 #define DMA_ERR_ERR19(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR19_SHIFT)) & DMA_ERR_ERR19_MASK)
 #define DMA_ERR_ERR20_MASK                       (0x100000U)
 #define DMA_ERR_ERR20_SHIFT                      (20U)
+/*! ERR20 - Error In Channel 20
+ *  0b0..An error in this channel has not occurred
+ *  0b1..An error in this channel has occurred
+ */
 #define DMA_ERR_ERR20(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR20_SHIFT)) & DMA_ERR_ERR20_MASK)
 #define DMA_ERR_ERR21_MASK                       (0x200000U)
 #define DMA_ERR_ERR21_SHIFT                      (21U)
+/*! ERR21 - Error In Channel 21
+ *  0b0..An error in this channel has not occurred
+ *  0b1..An error in this channel has occurred
+ */
 #define DMA_ERR_ERR21(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR21_SHIFT)) & DMA_ERR_ERR21_MASK)
 #define DMA_ERR_ERR22_MASK                       (0x400000U)
 #define DMA_ERR_ERR22_SHIFT                      (22U)
+/*! ERR22 - Error In Channel 22
+ *  0b0..An error in this channel has not occurred
+ *  0b1..An error in this channel has occurred
+ */
 #define DMA_ERR_ERR22(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR22_SHIFT)) & DMA_ERR_ERR22_MASK)
 #define DMA_ERR_ERR23_MASK                       (0x800000U)
 #define DMA_ERR_ERR23_SHIFT                      (23U)
+/*! ERR23 - Error In Channel 23
+ *  0b0..An error in this channel has not occurred
+ *  0b1..An error in this channel has occurred
+ */
 #define DMA_ERR_ERR23(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR23_SHIFT)) & DMA_ERR_ERR23_MASK)
 #define DMA_ERR_ERR24_MASK                       (0x1000000U)
 #define DMA_ERR_ERR24_SHIFT                      (24U)
+/*! ERR24 - Error In Channel 24
+ *  0b0..An error in this channel has not occurred
+ *  0b1..An error in this channel has occurred
+ */
 #define DMA_ERR_ERR24(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR24_SHIFT)) & DMA_ERR_ERR24_MASK)
 #define DMA_ERR_ERR25_MASK                       (0x2000000U)
 #define DMA_ERR_ERR25_SHIFT                      (25U)
+/*! ERR25 - Error In Channel 25
+ *  0b0..An error in this channel has not occurred
+ *  0b1..An error in this channel has occurred
+ */
 #define DMA_ERR_ERR25(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR25_SHIFT)) & DMA_ERR_ERR25_MASK)
 #define DMA_ERR_ERR26_MASK                       (0x4000000U)
 #define DMA_ERR_ERR26_SHIFT                      (26U)
+/*! ERR26 - Error In Channel 26
+ *  0b0..An error in this channel has not occurred
+ *  0b1..An error in this channel has occurred
+ */
 #define DMA_ERR_ERR26(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR26_SHIFT)) & DMA_ERR_ERR26_MASK)
 #define DMA_ERR_ERR27_MASK                       (0x8000000U)
 #define DMA_ERR_ERR27_SHIFT                      (27U)
+/*! ERR27 - Error In Channel 27
+ *  0b0..An error in this channel has not occurred
+ *  0b1..An error in this channel has occurred
+ */
 #define DMA_ERR_ERR27(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR27_SHIFT)) & DMA_ERR_ERR27_MASK)
 #define DMA_ERR_ERR28_MASK                       (0x10000000U)
 #define DMA_ERR_ERR28_SHIFT                      (28U)
+/*! ERR28 - Error In Channel 28
+ *  0b0..An error in this channel has not occurred
+ *  0b1..An error in this channel has occurred
+ */
 #define DMA_ERR_ERR28(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR28_SHIFT)) & DMA_ERR_ERR28_MASK)
 #define DMA_ERR_ERR29_MASK                       (0x20000000U)
 #define DMA_ERR_ERR29_SHIFT                      (29U)
+/*! ERR29 - Error In Channel 29
+ *  0b0..An error in this channel has not occurred
+ *  0b1..An error in this channel has occurred
+ */
 #define DMA_ERR_ERR29(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR29_SHIFT)) & DMA_ERR_ERR29_MASK)
 #define DMA_ERR_ERR30_MASK                       (0x40000000U)
 #define DMA_ERR_ERR30_SHIFT                      (30U)
+/*! ERR30 - Error In Channel 30
+ *  0b0..An error in this channel has not occurred
+ *  0b1..An error in this channel has occurred
+ */
 #define DMA_ERR_ERR30(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR30_SHIFT)) & DMA_ERR_ERR30_MASK)
 #define DMA_ERR_ERR31_MASK                       (0x80000000U)
 #define DMA_ERR_ERR31_SHIFT                      (31U)
+/*! ERR31 - Error In Channel 31
+ *  0b0..An error in this channel has not occurred
+ *  0b1..An error in this channel has occurred
+ */
 #define DMA_ERR_ERR31(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR31_SHIFT)) & DMA_ERR_ERR31_MASK)
 /*! @} */
 
@@ -8031,99 +13223,227 @@ typedef struct {
 /*! @{ */
 #define DMA_HRS_HRS0_MASK                        (0x1U)
 #define DMA_HRS_HRS0_SHIFT                       (0U)
+/*! HRS0 - Hardware Request Status Channel 0
+ *  0b0..A hardware service request for channel 0 is not present
+ *  0b1..A hardware service request for channel 0 is present
+ */
 #define DMA_HRS_HRS0(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS0_SHIFT)) & DMA_HRS_HRS0_MASK)
 #define DMA_HRS_HRS1_MASK                        (0x2U)
 #define DMA_HRS_HRS1_SHIFT                       (1U)
+/*! HRS1 - Hardware Request Status Channel 1
+ *  0b0..A hardware service request for channel 1 is not present
+ *  0b1..A hardware service request for channel 1 is present
+ */
 #define DMA_HRS_HRS1(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS1_SHIFT)) & DMA_HRS_HRS1_MASK)
 #define DMA_HRS_HRS2_MASK                        (0x4U)
 #define DMA_HRS_HRS2_SHIFT                       (2U)
+/*! HRS2 - Hardware Request Status Channel 2
+ *  0b0..A hardware service request for channel 2 is not present
+ *  0b1..A hardware service request for channel 2 is present
+ */
 #define DMA_HRS_HRS2(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS2_SHIFT)) & DMA_HRS_HRS2_MASK)
 #define DMA_HRS_HRS3_MASK                        (0x8U)
 #define DMA_HRS_HRS3_SHIFT                       (3U)
+/*! HRS3 - Hardware Request Status Channel 3
+ *  0b0..A hardware service request for channel 3 is not present
+ *  0b1..A hardware service request for channel 3 is present
+ */
 #define DMA_HRS_HRS3(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS3_SHIFT)) & DMA_HRS_HRS3_MASK)
 #define DMA_HRS_HRS4_MASK                        (0x10U)
 #define DMA_HRS_HRS4_SHIFT                       (4U)
+/*! HRS4 - Hardware Request Status Channel 4
+ *  0b0..A hardware service request for channel 4 is not present
+ *  0b1..A hardware service request for channel 4 is present
+ */
 #define DMA_HRS_HRS4(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS4_SHIFT)) & DMA_HRS_HRS4_MASK)
 #define DMA_HRS_HRS5_MASK                        (0x20U)
 #define DMA_HRS_HRS5_SHIFT                       (5U)
+/*! HRS5 - Hardware Request Status Channel 5
+ *  0b0..A hardware service request for channel 5 is not present
+ *  0b1..A hardware service request for channel 5 is present
+ */
 #define DMA_HRS_HRS5(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS5_SHIFT)) & DMA_HRS_HRS5_MASK)
 #define DMA_HRS_HRS6_MASK                        (0x40U)
 #define DMA_HRS_HRS6_SHIFT                       (6U)
+/*! HRS6 - Hardware Request Status Channel 6
+ *  0b0..A hardware service request for channel 6 is not present
+ *  0b1..A hardware service request for channel 6 is present
+ */
 #define DMA_HRS_HRS6(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS6_SHIFT)) & DMA_HRS_HRS6_MASK)
 #define DMA_HRS_HRS7_MASK                        (0x80U)
 #define DMA_HRS_HRS7_SHIFT                       (7U)
+/*! HRS7 - Hardware Request Status Channel 7
+ *  0b0..A hardware service request for channel 7 is not present
+ *  0b1..A hardware service request for channel 7 is present
+ */
 #define DMA_HRS_HRS7(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS7_SHIFT)) & DMA_HRS_HRS7_MASK)
 #define DMA_HRS_HRS8_MASK                        (0x100U)
 #define DMA_HRS_HRS8_SHIFT                       (8U)
+/*! HRS8 - Hardware Request Status Channel 8
+ *  0b0..A hardware service request for channel 8 is not present
+ *  0b1..A hardware service request for channel 8 is present
+ */
 #define DMA_HRS_HRS8(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS8_SHIFT)) & DMA_HRS_HRS8_MASK)
 #define DMA_HRS_HRS9_MASK                        (0x200U)
 #define DMA_HRS_HRS9_SHIFT                       (9U)
+/*! HRS9 - Hardware Request Status Channel 9
+ *  0b0..A hardware service request for channel 9 is not present
+ *  0b1..A hardware service request for channel 9 is present
+ */
 #define DMA_HRS_HRS9(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS9_SHIFT)) & DMA_HRS_HRS9_MASK)
 #define DMA_HRS_HRS10_MASK                       (0x400U)
 #define DMA_HRS_HRS10_SHIFT                      (10U)
+/*! HRS10 - Hardware Request Status Channel 10
+ *  0b0..A hardware service request for channel 10 is not present
+ *  0b1..A hardware service request for channel 10 is present
+ */
 #define DMA_HRS_HRS10(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS10_SHIFT)) & DMA_HRS_HRS10_MASK)
 #define DMA_HRS_HRS11_MASK                       (0x800U)
 #define DMA_HRS_HRS11_SHIFT                      (11U)
+/*! HRS11 - Hardware Request Status Channel 11
+ *  0b0..A hardware service request for channel 11 is not present
+ *  0b1..A hardware service request for channel 11 is present
+ */
 #define DMA_HRS_HRS11(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS11_SHIFT)) & DMA_HRS_HRS11_MASK)
 #define DMA_HRS_HRS12_MASK                       (0x1000U)
 #define DMA_HRS_HRS12_SHIFT                      (12U)
+/*! HRS12 - Hardware Request Status Channel 12
+ *  0b0..A hardware service request for channel 12 is not present
+ *  0b1..A hardware service request for channel 12 is present
+ */
 #define DMA_HRS_HRS12(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS12_SHIFT)) & DMA_HRS_HRS12_MASK)
 #define DMA_HRS_HRS13_MASK                       (0x2000U)
 #define DMA_HRS_HRS13_SHIFT                      (13U)
+/*! HRS13 - Hardware Request Status Channel 13
+ *  0b0..A hardware service request for channel 13 is not present
+ *  0b1..A hardware service request for channel 13 is present
+ */
 #define DMA_HRS_HRS13(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS13_SHIFT)) & DMA_HRS_HRS13_MASK)
 #define DMA_HRS_HRS14_MASK                       (0x4000U)
 #define DMA_HRS_HRS14_SHIFT                      (14U)
+/*! HRS14 - Hardware Request Status Channel 14
+ *  0b0..A hardware service request for channel 14 is not present
+ *  0b1..A hardware service request for channel 14 is present
+ */
 #define DMA_HRS_HRS14(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS14_SHIFT)) & DMA_HRS_HRS14_MASK)
 #define DMA_HRS_HRS15_MASK                       (0x8000U)
 #define DMA_HRS_HRS15_SHIFT                      (15U)
+/*! HRS15 - Hardware Request Status Channel 15
+ *  0b0..A hardware service request for channel 15 is not present
+ *  0b1..A hardware service request for channel 15 is present
+ */
 #define DMA_HRS_HRS15(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS15_SHIFT)) & DMA_HRS_HRS15_MASK)
 #define DMA_HRS_HRS16_MASK                       (0x10000U)
 #define DMA_HRS_HRS16_SHIFT                      (16U)
+/*! HRS16 - Hardware Request Status Channel 16
+ *  0b0..A hardware service request for channel 16 is not present
+ *  0b1..A hardware service request for channel 16 is present
+ */
 #define DMA_HRS_HRS16(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS16_SHIFT)) & DMA_HRS_HRS16_MASK)
 #define DMA_HRS_HRS17_MASK                       (0x20000U)
 #define DMA_HRS_HRS17_SHIFT                      (17U)
+/*! HRS17 - Hardware Request Status Channel 17
+ *  0b0..A hardware service request for channel 17 is not present
+ *  0b1..A hardware service request for channel 17 is present
+ */
 #define DMA_HRS_HRS17(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS17_SHIFT)) & DMA_HRS_HRS17_MASK)
 #define DMA_HRS_HRS18_MASK                       (0x40000U)
 #define DMA_HRS_HRS18_SHIFT                      (18U)
+/*! HRS18 - Hardware Request Status Channel 18
+ *  0b0..A hardware service request for channel 18 is not present
+ *  0b1..A hardware service request for channel 18 is present
+ */
 #define DMA_HRS_HRS18(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS18_SHIFT)) & DMA_HRS_HRS18_MASK)
 #define DMA_HRS_HRS19_MASK                       (0x80000U)
 #define DMA_HRS_HRS19_SHIFT                      (19U)
+/*! HRS19 - Hardware Request Status Channel 19
+ *  0b0..A hardware service request for channel 19 is not present
+ *  0b1..A hardware service request for channel 19 is present
+ */
 #define DMA_HRS_HRS19(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS19_SHIFT)) & DMA_HRS_HRS19_MASK)
 #define DMA_HRS_HRS20_MASK                       (0x100000U)
 #define DMA_HRS_HRS20_SHIFT                      (20U)
+/*! HRS20 - Hardware Request Status Channel 20
+ *  0b0..A hardware service request for channel 20 is not present
+ *  0b1..A hardware service request for channel 20 is present
+ */
 #define DMA_HRS_HRS20(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS20_SHIFT)) & DMA_HRS_HRS20_MASK)
 #define DMA_HRS_HRS21_MASK                       (0x200000U)
 #define DMA_HRS_HRS21_SHIFT                      (21U)
+/*! HRS21 - Hardware Request Status Channel 21
+ *  0b0..A hardware service request for channel 21 is not present
+ *  0b1..A hardware service request for channel 21 is present
+ */
 #define DMA_HRS_HRS21(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS21_SHIFT)) & DMA_HRS_HRS21_MASK)
 #define DMA_HRS_HRS22_MASK                       (0x400000U)
 #define DMA_HRS_HRS22_SHIFT                      (22U)
+/*! HRS22 - Hardware Request Status Channel 22
+ *  0b0..A hardware service request for channel 22 is not present
+ *  0b1..A hardware service request for channel 22 is present
+ */
 #define DMA_HRS_HRS22(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS22_SHIFT)) & DMA_HRS_HRS22_MASK)
 #define DMA_HRS_HRS23_MASK                       (0x800000U)
 #define DMA_HRS_HRS23_SHIFT                      (23U)
+/*! HRS23 - Hardware Request Status Channel 23
+ *  0b0..A hardware service request for channel 23 is not present
+ *  0b1..A hardware service request for channel 23 is present
+ */
 #define DMA_HRS_HRS23(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS23_SHIFT)) & DMA_HRS_HRS23_MASK)
 #define DMA_HRS_HRS24_MASK                       (0x1000000U)
 #define DMA_HRS_HRS24_SHIFT                      (24U)
+/*! HRS24 - Hardware Request Status Channel 24
+ *  0b0..A hardware service request for channel 24 is not present
+ *  0b1..A hardware service request for channel 24 is present
+ */
 #define DMA_HRS_HRS24(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS24_SHIFT)) & DMA_HRS_HRS24_MASK)
 #define DMA_HRS_HRS25_MASK                       (0x2000000U)
 #define DMA_HRS_HRS25_SHIFT                      (25U)
+/*! HRS25 - Hardware Request Status Channel 25
+ *  0b0..A hardware service request for channel 25 is not present
+ *  0b1..A hardware service request for channel 25 is present
+ */
 #define DMA_HRS_HRS25(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS25_SHIFT)) & DMA_HRS_HRS25_MASK)
 #define DMA_HRS_HRS26_MASK                       (0x4000000U)
 #define DMA_HRS_HRS26_SHIFT                      (26U)
+/*! HRS26 - Hardware Request Status Channel 26
+ *  0b0..A hardware service request for channel 26 is not present
+ *  0b1..A hardware service request for channel 26 is present
+ */
 #define DMA_HRS_HRS26(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS26_SHIFT)) & DMA_HRS_HRS26_MASK)
 #define DMA_HRS_HRS27_MASK                       (0x8000000U)
 #define DMA_HRS_HRS27_SHIFT                      (27U)
+/*! HRS27 - Hardware Request Status Channel 27
+ *  0b0..A hardware service request for channel 27 is not present
+ *  0b1..A hardware service request for channel 27 is present
+ */
 #define DMA_HRS_HRS27(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS27_SHIFT)) & DMA_HRS_HRS27_MASK)
 #define DMA_HRS_HRS28_MASK                       (0x10000000U)
 #define DMA_HRS_HRS28_SHIFT                      (28U)
+/*! HRS28 - Hardware Request Status Channel 28
+ *  0b0..A hardware service request for channel 28 is not present
+ *  0b1..A hardware service request for channel 28 is present
+ */
 #define DMA_HRS_HRS28(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS28_SHIFT)) & DMA_HRS_HRS28_MASK)
 #define DMA_HRS_HRS29_MASK                       (0x20000000U)
 #define DMA_HRS_HRS29_SHIFT                      (29U)
+/*! HRS29 - Hardware Request Status Channel 29
+ *  0b0..A hardware service request for channel 29 is not preset
+ *  0b1..A hardware service request for channel 29 is present
+ */
 #define DMA_HRS_HRS29(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS29_SHIFT)) & DMA_HRS_HRS29_MASK)
 #define DMA_HRS_HRS30_MASK                       (0x40000000U)
 #define DMA_HRS_HRS30_SHIFT                      (30U)
+/*! HRS30 - Hardware Request Status Channel 30
+ *  0b0..A hardware service request for channel 30 is not present
+ *  0b1..A hardware service request for channel 30 is present
+ */
 #define DMA_HRS_HRS30(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS30_SHIFT)) & DMA_HRS_HRS30_MASK)
 #define DMA_HRS_HRS31_MASK                       (0x80000000U)
 #define DMA_HRS_HRS31_SHIFT                      (31U)
+/*! HRS31 - Hardware Request Status Channel 31
+ *  0b0..A hardware service request for channel 31 is not present
+ *  0b1..A hardware service request for channel 31 is present
+ */
 #define DMA_HRS_HRS31(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS31_SHIFT)) & DMA_HRS_HRS31_MASK)
 /*! @} */
 
@@ -8131,99 +13451,227 @@ typedef struct {
 /*! @{ */
 #define DMA_EARS_EDREQ_0_MASK                    (0x1U)
 #define DMA_EARS_EDREQ_0_SHIFT                   (0U)
+/*! EDREQ_0 - Enable asynchronous DMA request in stop mode for channel 0.
+ *  0b0..Disable asynchronous DMA request for channel 0.
+ *  0b1..Enable asynchronous DMA request for channel 0.
+ */
 #define DMA_EARS_EDREQ_0(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_0_SHIFT)) & DMA_EARS_EDREQ_0_MASK)
 #define DMA_EARS_EDREQ_1_MASK                    (0x2U)
 #define DMA_EARS_EDREQ_1_SHIFT                   (1U)
+/*! EDREQ_1 - Enable asynchronous DMA request in stop mode for channel 1.
+ *  0b0..Disable asynchronous DMA request for channel 1
+ *  0b1..Enable asynchronous DMA request for channel 1.
+ */
 #define DMA_EARS_EDREQ_1(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_1_SHIFT)) & DMA_EARS_EDREQ_1_MASK)
 #define DMA_EARS_EDREQ_2_MASK                    (0x4U)
 #define DMA_EARS_EDREQ_2_SHIFT                   (2U)
+/*! EDREQ_2 - Enable asynchronous DMA request in stop mode for channel 2.
+ *  0b0..Disable asynchronous DMA request for channel 2.
+ *  0b1..Enable asynchronous DMA request for channel 2.
+ */
 #define DMA_EARS_EDREQ_2(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_2_SHIFT)) & DMA_EARS_EDREQ_2_MASK)
 #define DMA_EARS_EDREQ_3_MASK                    (0x8U)
 #define DMA_EARS_EDREQ_3_SHIFT                   (3U)
+/*! EDREQ_3 - Enable asynchronous DMA request in stop mode for channel 3.
+ *  0b0..Disable asynchronous DMA request for channel 3.
+ *  0b1..Enable asynchronous DMA request for channel 3.
+ */
 #define DMA_EARS_EDREQ_3(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_3_SHIFT)) & DMA_EARS_EDREQ_3_MASK)
 #define DMA_EARS_EDREQ_4_MASK                    (0x10U)
 #define DMA_EARS_EDREQ_4_SHIFT                   (4U)
+/*! EDREQ_4 - Enable asynchronous DMA request in stop mode for channel 4
+ *  0b0..Disable asynchronous DMA request for channel 4.
+ *  0b1..Enable asynchronous DMA request for channel 4.
+ */
 #define DMA_EARS_EDREQ_4(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_4_SHIFT)) & DMA_EARS_EDREQ_4_MASK)
 #define DMA_EARS_EDREQ_5_MASK                    (0x20U)
 #define DMA_EARS_EDREQ_5_SHIFT                   (5U)
+/*! EDREQ_5 - Enable asynchronous DMA request in stop mode for channel 5
+ *  0b0..Disable asynchronous DMA request for channel 5.
+ *  0b1..Enable asynchronous DMA request for channel 5.
+ */
 #define DMA_EARS_EDREQ_5(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_5_SHIFT)) & DMA_EARS_EDREQ_5_MASK)
 #define DMA_EARS_EDREQ_6_MASK                    (0x40U)
 #define DMA_EARS_EDREQ_6_SHIFT                   (6U)
+/*! EDREQ_6 - Enable asynchronous DMA request in stop mode for channel 6
+ *  0b0..Disable asynchronous DMA request for channel 6.
+ *  0b1..Enable asynchronous DMA request for channel 6.
+ */
 #define DMA_EARS_EDREQ_6(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_6_SHIFT)) & DMA_EARS_EDREQ_6_MASK)
 #define DMA_EARS_EDREQ_7_MASK                    (0x80U)
 #define DMA_EARS_EDREQ_7_SHIFT                   (7U)
+/*! EDREQ_7 - Enable asynchronous DMA request in stop mode for channel 7
+ *  0b0..Disable asynchronous DMA request for channel 7.
+ *  0b1..Enable asynchronous DMA request for channel 7.
+ */
 #define DMA_EARS_EDREQ_7(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_7_SHIFT)) & DMA_EARS_EDREQ_7_MASK)
 #define DMA_EARS_EDREQ_8_MASK                    (0x100U)
 #define DMA_EARS_EDREQ_8_SHIFT                   (8U)
+/*! EDREQ_8 - Enable asynchronous DMA request in stop mode for channel 8
+ *  0b0..Disable asynchronous DMA request for channel 8.
+ *  0b1..Enable asynchronous DMA request for channel 8.
+ */
 #define DMA_EARS_EDREQ_8(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_8_SHIFT)) & DMA_EARS_EDREQ_8_MASK)
 #define DMA_EARS_EDREQ_9_MASK                    (0x200U)
 #define DMA_EARS_EDREQ_9_SHIFT                   (9U)
+/*! EDREQ_9 - Enable asynchronous DMA request in stop mode for channel 9
+ *  0b0..Disable asynchronous DMA request for channel 9.
+ *  0b1..Enable asynchronous DMA request for channel 9.
+ */
 #define DMA_EARS_EDREQ_9(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_9_SHIFT)) & DMA_EARS_EDREQ_9_MASK)
 #define DMA_EARS_EDREQ_10_MASK                   (0x400U)
 #define DMA_EARS_EDREQ_10_SHIFT                  (10U)
+/*! EDREQ_10 - Enable asynchronous DMA request in stop mode for channel 10
+ *  0b0..Disable asynchronous DMA request for channel 10.
+ *  0b1..Enable asynchronous DMA request for channel 10.
+ */
 #define DMA_EARS_EDREQ_10(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_10_SHIFT)) & DMA_EARS_EDREQ_10_MASK)
 #define DMA_EARS_EDREQ_11_MASK                   (0x800U)
 #define DMA_EARS_EDREQ_11_SHIFT                  (11U)
+/*! EDREQ_11 - Enable asynchronous DMA request in stop mode for channel 11
+ *  0b0..Disable asynchronous DMA request for channel 11.
+ *  0b1..Enable asynchronous DMA request for channel 11.
+ */
 #define DMA_EARS_EDREQ_11(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_11_SHIFT)) & DMA_EARS_EDREQ_11_MASK)
 #define DMA_EARS_EDREQ_12_MASK                   (0x1000U)
 #define DMA_EARS_EDREQ_12_SHIFT                  (12U)
+/*! EDREQ_12 - Enable asynchronous DMA request in stop mode for channel 12
+ *  0b0..Disable asynchronous DMA request for channel 12.
+ *  0b1..Enable asynchronous DMA request for channel 12.
+ */
 #define DMA_EARS_EDREQ_12(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_12_SHIFT)) & DMA_EARS_EDREQ_12_MASK)
 #define DMA_EARS_EDREQ_13_MASK                   (0x2000U)
 #define DMA_EARS_EDREQ_13_SHIFT                  (13U)
+/*! EDREQ_13 - Enable asynchronous DMA request in stop mode for channel 13
+ *  0b0..Disable asynchronous DMA request for channel 13.
+ *  0b1..Enable asynchronous DMA request for channel 13.
+ */
 #define DMA_EARS_EDREQ_13(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_13_SHIFT)) & DMA_EARS_EDREQ_13_MASK)
 #define DMA_EARS_EDREQ_14_MASK                   (0x4000U)
 #define DMA_EARS_EDREQ_14_SHIFT                  (14U)
+/*! EDREQ_14 - Enable asynchronous DMA request in stop mode for channel 14
+ *  0b0..Disable asynchronous DMA request for channel 14.
+ *  0b1..Enable asynchronous DMA request for channel 14.
+ */
 #define DMA_EARS_EDREQ_14(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_14_SHIFT)) & DMA_EARS_EDREQ_14_MASK)
 #define DMA_EARS_EDREQ_15_MASK                   (0x8000U)
 #define DMA_EARS_EDREQ_15_SHIFT                  (15U)
+/*! EDREQ_15 - Enable asynchronous DMA request in stop mode for channel 15
+ *  0b0..Disable asynchronous DMA request for channel 15.
+ *  0b1..Enable asynchronous DMA request for channel 15.
+ */
 #define DMA_EARS_EDREQ_15(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_15_SHIFT)) & DMA_EARS_EDREQ_15_MASK)
 #define DMA_EARS_EDREQ_16_MASK                   (0x10000U)
 #define DMA_EARS_EDREQ_16_SHIFT                  (16U)
+/*! EDREQ_16 - Enable asynchronous DMA request in stop mode for channel 16
+ *  0b0..Disable asynchronous DMA request for channel 16
+ *  0b1..Enable asynchronous DMA request for channel 16
+ */
 #define DMA_EARS_EDREQ_16(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_16_SHIFT)) & DMA_EARS_EDREQ_16_MASK)
 #define DMA_EARS_EDREQ_17_MASK                   (0x20000U)
 #define DMA_EARS_EDREQ_17_SHIFT                  (17U)
+/*! EDREQ_17 - Enable asynchronous DMA request in stop mode for channel 17
+ *  0b0..Disable asynchronous DMA request for channel 17
+ *  0b1..Enable asynchronous DMA request for channel 17
+ */
 #define DMA_EARS_EDREQ_17(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_17_SHIFT)) & DMA_EARS_EDREQ_17_MASK)
 #define DMA_EARS_EDREQ_18_MASK                   (0x40000U)
 #define DMA_EARS_EDREQ_18_SHIFT                  (18U)
+/*! EDREQ_18 - Enable asynchronous DMA request in stop mode for channel 18
+ *  0b0..Disable asynchronous DMA request for channel 18
+ *  0b1..Enable asynchronous DMA request for channel 18
+ */
 #define DMA_EARS_EDREQ_18(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_18_SHIFT)) & DMA_EARS_EDREQ_18_MASK)
 #define DMA_EARS_EDREQ_19_MASK                   (0x80000U)
 #define DMA_EARS_EDREQ_19_SHIFT                  (19U)
+/*! EDREQ_19 - Enable asynchronous DMA request in stop mode for channel 19
+ *  0b0..Disable asynchronous DMA request for channel 19
+ *  0b1..Enable asynchronous DMA request for channel 19
+ */
 #define DMA_EARS_EDREQ_19(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_19_SHIFT)) & DMA_EARS_EDREQ_19_MASK)
 #define DMA_EARS_EDREQ_20_MASK                   (0x100000U)
 #define DMA_EARS_EDREQ_20_SHIFT                  (20U)
+/*! EDREQ_20 - Enable asynchronous DMA request in stop mode for channel 20
+ *  0b0..Disable asynchronous DMA request for channel 20
+ *  0b1..Enable asynchronous DMA request for channel 20
+ */
 #define DMA_EARS_EDREQ_20(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_20_SHIFT)) & DMA_EARS_EDREQ_20_MASK)
 #define DMA_EARS_EDREQ_21_MASK                   (0x200000U)
 #define DMA_EARS_EDREQ_21_SHIFT                  (21U)
+/*! EDREQ_21 - Enable asynchronous DMA request in stop mode for channel 21
+ *  0b0..Disable asynchronous DMA request for channel 21
+ *  0b1..Enable asynchronous DMA request for channel 21
+ */
 #define DMA_EARS_EDREQ_21(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_21_SHIFT)) & DMA_EARS_EDREQ_21_MASK)
 #define DMA_EARS_EDREQ_22_MASK                   (0x400000U)
 #define DMA_EARS_EDREQ_22_SHIFT                  (22U)
+/*! EDREQ_22 - Enable asynchronous DMA request in stop mode for channel 22
+ *  0b0..Disable asynchronous DMA request for channel 22
+ *  0b1..Enable asynchronous DMA request for channel 22
+ */
 #define DMA_EARS_EDREQ_22(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_22_SHIFT)) & DMA_EARS_EDREQ_22_MASK)
 #define DMA_EARS_EDREQ_23_MASK                   (0x800000U)
 #define DMA_EARS_EDREQ_23_SHIFT                  (23U)
+/*! EDREQ_23 - Enable asynchronous DMA request in stop mode for channel 23
+ *  0b0..Disable asynchronous DMA request for channel 23
+ *  0b1..Enable asynchronous DMA request for channel 23
+ */
 #define DMA_EARS_EDREQ_23(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_23_SHIFT)) & DMA_EARS_EDREQ_23_MASK)
 #define DMA_EARS_EDREQ_24_MASK                   (0x1000000U)
 #define DMA_EARS_EDREQ_24_SHIFT                  (24U)
+/*! EDREQ_24 - Enable asynchronous DMA request in stop mode for channel 24
+ *  0b0..Disable asynchronous DMA request for channel 24
+ *  0b1..Enable asynchronous DMA request for channel 24
+ */
 #define DMA_EARS_EDREQ_24(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_24_SHIFT)) & DMA_EARS_EDREQ_24_MASK)
 #define DMA_EARS_EDREQ_25_MASK                   (0x2000000U)
 #define DMA_EARS_EDREQ_25_SHIFT                  (25U)
+/*! EDREQ_25 - Enable asynchronous DMA request in stop mode for channel 25
+ *  0b0..Disable asynchronous DMA request for channel 25
+ *  0b1..Enable asynchronous DMA request for channel 25
+ */
 #define DMA_EARS_EDREQ_25(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_25_SHIFT)) & DMA_EARS_EDREQ_25_MASK)
 #define DMA_EARS_EDREQ_26_MASK                   (0x4000000U)
 #define DMA_EARS_EDREQ_26_SHIFT                  (26U)
+/*! EDREQ_26 - Enable asynchronous DMA request in stop mode for channel 26
+ *  0b0..Disable asynchronous DMA request for channel 26
+ *  0b1..Enable asynchronous DMA request for channel 26
+ */
 #define DMA_EARS_EDREQ_26(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_26_SHIFT)) & DMA_EARS_EDREQ_26_MASK)
 #define DMA_EARS_EDREQ_27_MASK                   (0x8000000U)
 #define DMA_EARS_EDREQ_27_SHIFT                  (27U)
+/*! EDREQ_27 - Enable asynchronous DMA request in stop mode for channel 27
+ *  0b0..Disable asynchronous DMA request for channel 27
+ *  0b1..Enable asynchronous DMA request for channel 27
+ */
 #define DMA_EARS_EDREQ_27(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_27_SHIFT)) & DMA_EARS_EDREQ_27_MASK)
 #define DMA_EARS_EDREQ_28_MASK                   (0x10000000U)
 #define DMA_EARS_EDREQ_28_SHIFT                  (28U)
+/*! EDREQ_28 - Enable asynchronous DMA request in stop mode for channel 28
+ *  0b0..Disable asynchronous DMA request for channel 28
+ *  0b1..Enable asynchronous DMA request for channel 28
+ */
 #define DMA_EARS_EDREQ_28(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_28_SHIFT)) & DMA_EARS_EDREQ_28_MASK)
 #define DMA_EARS_EDREQ_29_MASK                   (0x20000000U)
 #define DMA_EARS_EDREQ_29_SHIFT                  (29U)
+/*! EDREQ_29 - Enable asynchronous DMA request in stop mode for channel 29
+ *  0b0..Disable asynchronous DMA request for channel 29
+ *  0b1..Enable asynchronous DMA request for channel 29
+ */
 #define DMA_EARS_EDREQ_29(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_29_SHIFT)) & DMA_EARS_EDREQ_29_MASK)
 #define DMA_EARS_EDREQ_30_MASK                   (0x40000000U)
 #define DMA_EARS_EDREQ_30_SHIFT                  (30U)
+/*! EDREQ_30 - Enable asynchronous DMA request in stop mode for channel 30
+ *  0b0..Disable asynchronous DMA request for channel 30
+ *  0b1..Enable asynchronous DMA request for channel 30
+ */
 #define DMA_EARS_EDREQ_30(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_30_SHIFT)) & DMA_EARS_EDREQ_30_MASK)
 #define DMA_EARS_EDREQ_31_MASK                   (0x80000000U)
 #define DMA_EARS_EDREQ_31_SHIFT                  (31U)
+/*! EDREQ_31 - Enable asynchronous DMA request in stop mode for channel 31
+ *  0b0..Disable asynchronous DMA request for channel 31
+ *  0b1..Enable asynchronous DMA request for channel 31
+ */
 #define DMA_EARS_EDREQ_31(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_31_SHIFT)) & DMA_EARS_EDREQ_31_MASK)
 /*! @} */
 
@@ -8237,9 +13685,17 @@ typedef struct {
 #define DMA_DCHPRI3_GRPPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_GRPPRI_SHIFT)) & DMA_DCHPRI3_GRPPRI_MASK)
 #define DMA_DCHPRI3_DPA_MASK                     (0x40U)
 #define DMA_DCHPRI3_DPA_SHIFT                    (6U)
+/*! DPA - Disable Preempt Ability. This field resets to 0.
+ *  0b0..Channel n can suspend a lower priority channel.
+ *  0b1..Channel n cannot suspend any channel, regardless of channel priority.
+ */
 #define DMA_DCHPRI3_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_DPA_SHIFT)) & DMA_DCHPRI3_DPA_MASK)
 #define DMA_DCHPRI3_ECP_MASK                     (0x80U)
 #define DMA_DCHPRI3_ECP_SHIFT                    (7U)
+/*! ECP - Enable Channel Preemption. This field resets to 0.
+ *  0b0..Channel n cannot be suspended by a higher priority channel's service request.
+ *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
+ */
 #define DMA_DCHPRI3_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_ECP_SHIFT)) & DMA_DCHPRI3_ECP_MASK)
 /*! @} */
 
@@ -8253,9 +13709,17 @@ typedef struct {
 #define DMA_DCHPRI2_GRPPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_GRPPRI_SHIFT)) & DMA_DCHPRI2_GRPPRI_MASK)
 #define DMA_DCHPRI2_DPA_MASK                     (0x40U)
 #define DMA_DCHPRI2_DPA_SHIFT                    (6U)
+/*! DPA - Disable Preempt Ability. This field resets to 0.
+ *  0b0..Channel n can suspend a lower priority channel.
+ *  0b1..Channel n cannot suspend any channel, regardless of channel priority.
+ */
 #define DMA_DCHPRI2_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_DPA_SHIFT)) & DMA_DCHPRI2_DPA_MASK)
 #define DMA_DCHPRI2_ECP_MASK                     (0x80U)
 #define DMA_DCHPRI2_ECP_SHIFT                    (7U)
+/*! ECP - Enable Channel Preemption. This field resets to 0.
+ *  0b0..Channel n cannot be suspended by a higher priority channel's service request.
+ *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
+ */
 #define DMA_DCHPRI2_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_ECP_SHIFT)) & DMA_DCHPRI2_ECP_MASK)
 /*! @} */
 
@@ -8269,9 +13733,17 @@ typedef struct {
 #define DMA_DCHPRI1_GRPPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_GRPPRI_SHIFT)) & DMA_DCHPRI1_GRPPRI_MASK)
 #define DMA_DCHPRI1_DPA_MASK                     (0x40U)
 #define DMA_DCHPRI1_DPA_SHIFT                    (6U)
+/*! DPA - Disable Preempt Ability. This field resets to 0.
+ *  0b0..Channel n can suspend a lower priority channel.
+ *  0b1..Channel n cannot suspend any channel, regardless of channel priority.
+ */
 #define DMA_DCHPRI1_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_DPA_SHIFT)) & DMA_DCHPRI1_DPA_MASK)
 #define DMA_DCHPRI1_ECP_MASK                     (0x80U)
 #define DMA_DCHPRI1_ECP_SHIFT                    (7U)
+/*! ECP - Enable Channel Preemption. This field resets to 0.
+ *  0b0..Channel n cannot be suspended by a higher priority channel's service request.
+ *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
+ */
 #define DMA_DCHPRI1_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_ECP_SHIFT)) & DMA_DCHPRI1_ECP_MASK)
 /*! @} */
 
@@ -8285,9 +13757,17 @@ typedef struct {
 #define DMA_DCHPRI0_GRPPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_GRPPRI_SHIFT)) & DMA_DCHPRI0_GRPPRI_MASK)
 #define DMA_DCHPRI0_DPA_MASK                     (0x40U)
 #define DMA_DCHPRI0_DPA_SHIFT                    (6U)
+/*! DPA - Disable Preempt Ability. This field resets to 0.
+ *  0b0..Channel n can suspend a lower priority channel.
+ *  0b1..Channel n cannot suspend any channel, regardless of channel priority.
+ */
 #define DMA_DCHPRI0_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_DPA_SHIFT)) & DMA_DCHPRI0_DPA_MASK)
 #define DMA_DCHPRI0_ECP_MASK                     (0x80U)
 #define DMA_DCHPRI0_ECP_SHIFT                    (7U)
+/*! ECP - Enable Channel Preemption. This field resets to 0.
+ *  0b0..Channel n cannot be suspended by a higher priority channel's service request.
+ *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
+ */
 #define DMA_DCHPRI0_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_ECP_SHIFT)) & DMA_DCHPRI0_ECP_MASK)
 /*! @} */
 
@@ -8301,9 +13781,17 @@ typedef struct {
 #define DMA_DCHPRI7_GRPPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_GRPPRI_SHIFT)) & DMA_DCHPRI7_GRPPRI_MASK)
 #define DMA_DCHPRI7_DPA_MASK                     (0x40U)
 #define DMA_DCHPRI7_DPA_SHIFT                    (6U)
+/*! DPA - Disable Preempt Ability. This field resets to 0.
+ *  0b0..Channel n can suspend a lower priority channel.
+ *  0b1..Channel n cannot suspend any channel, regardless of channel priority.
+ */
 #define DMA_DCHPRI7_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_DPA_SHIFT)) & DMA_DCHPRI7_DPA_MASK)
 #define DMA_DCHPRI7_ECP_MASK                     (0x80U)
 #define DMA_DCHPRI7_ECP_SHIFT                    (7U)
+/*! ECP - Enable Channel Preemption. This field resets to 0.
+ *  0b0..Channel n cannot be suspended by a higher priority channel's service request.
+ *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
+ */
 #define DMA_DCHPRI7_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_ECP_SHIFT)) & DMA_DCHPRI7_ECP_MASK)
 /*! @} */
 
@@ -8317,9 +13805,17 @@ typedef struct {
 #define DMA_DCHPRI6_GRPPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_GRPPRI_SHIFT)) & DMA_DCHPRI6_GRPPRI_MASK)
 #define DMA_DCHPRI6_DPA_MASK                     (0x40U)
 #define DMA_DCHPRI6_DPA_SHIFT                    (6U)
+/*! DPA - Disable Preempt Ability. This field resets to 0.
+ *  0b0..Channel n can suspend a lower priority channel.
+ *  0b1..Channel n cannot suspend any channel, regardless of channel priority.
+ */
 #define DMA_DCHPRI6_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_DPA_SHIFT)) & DMA_DCHPRI6_DPA_MASK)
 #define DMA_DCHPRI6_ECP_MASK                     (0x80U)
 #define DMA_DCHPRI6_ECP_SHIFT                    (7U)
+/*! ECP - Enable Channel Preemption. This field resets to 0.
+ *  0b0..Channel n cannot be suspended by a higher priority channel's service request.
+ *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
+ */
 #define DMA_DCHPRI6_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_ECP_SHIFT)) & DMA_DCHPRI6_ECP_MASK)
 /*! @} */
 
@@ -8333,9 +13829,17 @@ typedef struct {
 #define DMA_DCHPRI5_GRPPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_GRPPRI_SHIFT)) & DMA_DCHPRI5_GRPPRI_MASK)
 #define DMA_DCHPRI5_DPA_MASK                     (0x40U)
 #define DMA_DCHPRI5_DPA_SHIFT                    (6U)
+/*! DPA - Disable Preempt Ability. This field resets to 0.
+ *  0b0..Channel n can suspend a lower priority channel.
+ *  0b1..Channel n cannot suspend any channel, regardless of channel priority.
+ */
 #define DMA_DCHPRI5_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_DPA_SHIFT)) & DMA_DCHPRI5_DPA_MASK)
 #define DMA_DCHPRI5_ECP_MASK                     (0x80U)
 #define DMA_DCHPRI5_ECP_SHIFT                    (7U)
+/*! ECP - Enable Channel Preemption. This field resets to 0.
+ *  0b0..Channel n cannot be suspended by a higher priority channel's service request.
+ *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
+ */
 #define DMA_DCHPRI5_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_ECP_SHIFT)) & DMA_DCHPRI5_ECP_MASK)
 /*! @} */
 
@@ -8349,9 +13853,17 @@ typedef struct {
 #define DMA_DCHPRI4_GRPPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_GRPPRI_SHIFT)) & DMA_DCHPRI4_GRPPRI_MASK)
 #define DMA_DCHPRI4_DPA_MASK                     (0x40U)
 #define DMA_DCHPRI4_DPA_SHIFT                    (6U)
+/*! DPA - Disable Preempt Ability. This field resets to 0.
+ *  0b0..Channel n can suspend a lower priority channel.
+ *  0b1..Channel n cannot suspend any channel, regardless of channel priority.
+ */
 #define DMA_DCHPRI4_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_DPA_SHIFT)) & DMA_DCHPRI4_DPA_MASK)
 #define DMA_DCHPRI4_ECP_MASK                     (0x80U)
 #define DMA_DCHPRI4_ECP_SHIFT                    (7U)
+/*! ECP - Enable Channel Preemption. This field resets to 0.
+ *  0b0..Channel n cannot be suspended by a higher priority channel's service request.
+ *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
+ */
 #define DMA_DCHPRI4_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_ECP_SHIFT)) & DMA_DCHPRI4_ECP_MASK)
 /*! @} */
 
@@ -8365,9 +13877,17 @@ typedef struct {
 #define DMA_DCHPRI11_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_GRPPRI_SHIFT)) & DMA_DCHPRI11_GRPPRI_MASK)
 #define DMA_DCHPRI11_DPA_MASK                    (0x40U)
 #define DMA_DCHPRI11_DPA_SHIFT                   (6U)
+/*! DPA - Disable Preempt Ability. This field resets to 0.
+ *  0b0..Channel n can suspend a lower priority channel.
+ *  0b1..Channel n cannot suspend any channel, regardless of channel priority.
+ */
 #define DMA_DCHPRI11_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_DPA_SHIFT)) & DMA_DCHPRI11_DPA_MASK)
 #define DMA_DCHPRI11_ECP_MASK                    (0x80U)
 #define DMA_DCHPRI11_ECP_SHIFT                   (7U)
+/*! ECP - Enable Channel Preemption. This field resets to 0.
+ *  0b0..Channel n cannot be suspended by a higher priority channel's service request.
+ *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
+ */
 #define DMA_DCHPRI11_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_ECP_SHIFT)) & DMA_DCHPRI11_ECP_MASK)
 /*! @} */
 
@@ -8381,9 +13901,17 @@ typedef struct {
 #define DMA_DCHPRI10_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_GRPPRI_SHIFT)) & DMA_DCHPRI10_GRPPRI_MASK)
 #define DMA_DCHPRI10_DPA_MASK                    (0x40U)
 #define DMA_DCHPRI10_DPA_SHIFT                   (6U)
+/*! DPA - Disable Preempt Ability. This field resets to 0.
+ *  0b0..Channel n can suspend a lower priority channel.
+ *  0b1..Channel n cannot suspend any channel, regardless of channel priority.
+ */
 #define DMA_DCHPRI10_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_DPA_SHIFT)) & DMA_DCHPRI10_DPA_MASK)
 #define DMA_DCHPRI10_ECP_MASK                    (0x80U)
 #define DMA_DCHPRI10_ECP_SHIFT                   (7U)
+/*! ECP - Enable Channel Preemption. This field resets to 0.
+ *  0b0..Channel n cannot be suspended by a higher priority channel's service request.
+ *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
+ */
 #define DMA_DCHPRI10_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_ECP_SHIFT)) & DMA_DCHPRI10_ECP_MASK)
 /*! @} */
 
@@ -8397,9 +13925,17 @@ typedef struct {
 #define DMA_DCHPRI9_GRPPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_GRPPRI_SHIFT)) & DMA_DCHPRI9_GRPPRI_MASK)
 #define DMA_DCHPRI9_DPA_MASK                     (0x40U)
 #define DMA_DCHPRI9_DPA_SHIFT                    (6U)
+/*! DPA - Disable Preempt Ability. This field resets to 0.
+ *  0b0..Channel n can suspend a lower priority channel.
+ *  0b1..Channel n cannot suspend any channel, regardless of channel priority.
+ */
 #define DMA_DCHPRI9_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_DPA_SHIFT)) & DMA_DCHPRI9_DPA_MASK)
 #define DMA_DCHPRI9_ECP_MASK                     (0x80U)
 #define DMA_DCHPRI9_ECP_SHIFT                    (7U)
+/*! ECP - Enable Channel Preemption. This field resets to 0.
+ *  0b0..Channel n cannot be suspended by a higher priority channel's service request.
+ *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
+ */
 #define DMA_DCHPRI9_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_ECP_SHIFT)) & DMA_DCHPRI9_ECP_MASK)
 /*! @} */
 
@@ -8413,9 +13949,17 @@ typedef struct {
 #define DMA_DCHPRI8_GRPPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_GRPPRI_SHIFT)) & DMA_DCHPRI8_GRPPRI_MASK)
 #define DMA_DCHPRI8_DPA_MASK                     (0x40U)
 #define DMA_DCHPRI8_DPA_SHIFT                    (6U)
+/*! DPA - Disable Preempt Ability. This field resets to 0.
+ *  0b0..Channel n can suspend a lower priority channel.
+ *  0b1..Channel n cannot suspend any channel, regardless of channel priority.
+ */
 #define DMA_DCHPRI8_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_DPA_SHIFT)) & DMA_DCHPRI8_DPA_MASK)
 #define DMA_DCHPRI8_ECP_MASK                     (0x80U)
 #define DMA_DCHPRI8_ECP_SHIFT                    (7U)
+/*! ECP - Enable Channel Preemption. This field resets to 0.
+ *  0b0..Channel n cannot be suspended by a higher priority channel's service request.
+ *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
+ */
 #define DMA_DCHPRI8_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_ECP_SHIFT)) & DMA_DCHPRI8_ECP_MASK)
 /*! @} */
 
@@ -8429,9 +13973,17 @@ typedef struct {
 #define DMA_DCHPRI15_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_GRPPRI_SHIFT)) & DMA_DCHPRI15_GRPPRI_MASK)
 #define DMA_DCHPRI15_DPA_MASK                    (0x40U)
 #define DMA_DCHPRI15_DPA_SHIFT                   (6U)
+/*! DPA - Disable Preempt Ability. This field resets to 0.
+ *  0b0..Channel n can suspend a lower priority channel.
+ *  0b1..Channel n cannot suspend any channel, regardless of channel priority.
+ */
 #define DMA_DCHPRI15_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_DPA_SHIFT)) & DMA_DCHPRI15_DPA_MASK)
 #define DMA_DCHPRI15_ECP_MASK                    (0x80U)
 #define DMA_DCHPRI15_ECP_SHIFT                   (7U)
+/*! ECP - Enable Channel Preemption. This field resets to 0.
+ *  0b0..Channel n cannot be suspended by a higher priority channel's service request.
+ *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
+ */
 #define DMA_DCHPRI15_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_ECP_SHIFT)) & DMA_DCHPRI15_ECP_MASK)
 /*! @} */
 
@@ -8445,9 +13997,17 @@ typedef struct {
 #define DMA_DCHPRI14_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_GRPPRI_SHIFT)) & DMA_DCHPRI14_GRPPRI_MASK)
 #define DMA_DCHPRI14_DPA_MASK                    (0x40U)
 #define DMA_DCHPRI14_DPA_SHIFT                   (6U)
+/*! DPA - Disable Preempt Ability. This field resets to 0.
+ *  0b0..Channel n can suspend a lower priority channel.
+ *  0b1..Channel n cannot suspend any channel, regardless of channel priority.
+ */
 #define DMA_DCHPRI14_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_DPA_SHIFT)) & DMA_DCHPRI14_DPA_MASK)
 #define DMA_DCHPRI14_ECP_MASK                    (0x80U)
 #define DMA_DCHPRI14_ECP_SHIFT                   (7U)
+/*! ECP - Enable Channel Preemption. This field resets to 0.
+ *  0b0..Channel n cannot be suspended by a higher priority channel's service request.
+ *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
+ */
 #define DMA_DCHPRI14_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_ECP_SHIFT)) & DMA_DCHPRI14_ECP_MASK)
 /*! @} */
 
@@ -8461,9 +14021,17 @@ typedef struct {
 #define DMA_DCHPRI13_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_GRPPRI_SHIFT)) & DMA_DCHPRI13_GRPPRI_MASK)
 #define DMA_DCHPRI13_DPA_MASK                    (0x40U)
 #define DMA_DCHPRI13_DPA_SHIFT                   (6U)
+/*! DPA - Disable Preempt Ability. This field resets to 0.
+ *  0b0..Channel n can suspend a lower priority channel.
+ *  0b1..Channel n cannot suspend any channel, regardless of channel priority.
+ */
 #define DMA_DCHPRI13_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_DPA_SHIFT)) & DMA_DCHPRI13_DPA_MASK)
 #define DMA_DCHPRI13_ECP_MASK                    (0x80U)
 #define DMA_DCHPRI13_ECP_SHIFT                   (7U)
+/*! ECP - Enable Channel Preemption. This field resets to 0.
+ *  0b0..Channel n cannot be suspended by a higher priority channel's service request.
+ *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
+ */
 #define DMA_DCHPRI13_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_ECP_SHIFT)) & DMA_DCHPRI13_ECP_MASK)
 /*! @} */
 
@@ -8477,9 +14045,17 @@ typedef struct {
 #define DMA_DCHPRI12_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_GRPPRI_SHIFT)) & DMA_DCHPRI12_GRPPRI_MASK)
 #define DMA_DCHPRI12_DPA_MASK                    (0x40U)
 #define DMA_DCHPRI12_DPA_SHIFT                   (6U)
+/*! DPA - Disable Preempt Ability. This field resets to 0.
+ *  0b0..Channel n can suspend a lower priority channel.
+ *  0b1..Channel n cannot suspend any channel, regardless of channel priority.
+ */
 #define DMA_DCHPRI12_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_DPA_SHIFT)) & DMA_DCHPRI12_DPA_MASK)
 #define DMA_DCHPRI12_ECP_MASK                    (0x80U)
 #define DMA_DCHPRI12_ECP_SHIFT                   (7U)
+/*! ECP - Enable Channel Preemption. This field resets to 0.
+ *  0b0..Channel n cannot be suspended by a higher priority channel's service request.
+ *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
+ */
 #define DMA_DCHPRI12_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_ECP_SHIFT)) & DMA_DCHPRI12_ECP_MASK)
 /*! @} */
 
@@ -8493,9 +14069,17 @@ typedef struct {
 #define DMA_DCHPRI19_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_GRPPRI_SHIFT)) & DMA_DCHPRI19_GRPPRI_MASK)
 #define DMA_DCHPRI19_DPA_MASK                    (0x40U)
 #define DMA_DCHPRI19_DPA_SHIFT                   (6U)
+/*! DPA - Disable Preempt Ability. This field resets to 0.
+ *  0b0..Channel n can suspend a lower priority channel.
+ *  0b1..Channel n cannot suspend any channel, regardless of channel priority.
+ */
 #define DMA_DCHPRI19_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_DPA_SHIFT)) & DMA_DCHPRI19_DPA_MASK)
 #define DMA_DCHPRI19_ECP_MASK                    (0x80U)
 #define DMA_DCHPRI19_ECP_SHIFT                   (7U)
+/*! ECP - Enable Channel Preemption. This field resets to 0.
+ *  0b0..Channel n cannot be suspended by a higher priority channel's service request.
+ *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
+ */
 #define DMA_DCHPRI19_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_ECP_SHIFT)) & DMA_DCHPRI19_ECP_MASK)
 /*! @} */
 
@@ -8509,9 +14093,17 @@ typedef struct {
 #define DMA_DCHPRI18_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_GRPPRI_SHIFT)) & DMA_DCHPRI18_GRPPRI_MASK)
 #define DMA_DCHPRI18_DPA_MASK                    (0x40U)
 #define DMA_DCHPRI18_DPA_SHIFT                   (6U)
+/*! DPA - Disable Preempt Ability. This field resets to 0.
+ *  0b0..Channel n can suspend a lower priority channel.
+ *  0b1..Channel n cannot suspend any channel, regardless of channel priority.
+ */
 #define DMA_DCHPRI18_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_DPA_SHIFT)) & DMA_DCHPRI18_DPA_MASK)
 #define DMA_DCHPRI18_ECP_MASK                    (0x80U)
 #define DMA_DCHPRI18_ECP_SHIFT                   (7U)
+/*! ECP - Enable Channel Preemption. This field resets to 0.
+ *  0b0..Channel n cannot be suspended by a higher priority channel's service request.
+ *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
+ */
 #define DMA_DCHPRI18_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_ECP_SHIFT)) & DMA_DCHPRI18_ECP_MASK)
 /*! @} */
 
@@ -8525,9 +14117,17 @@ typedef struct {
 #define DMA_DCHPRI17_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_GRPPRI_SHIFT)) & DMA_DCHPRI17_GRPPRI_MASK)
 #define DMA_DCHPRI17_DPA_MASK                    (0x40U)
 #define DMA_DCHPRI17_DPA_SHIFT                   (6U)
+/*! DPA - Disable Preempt Ability. This field resets to 0.
+ *  0b0..Channel n can suspend a lower priority channel.
+ *  0b1..Channel n cannot suspend any channel, regardless of channel priority.
+ */
 #define DMA_DCHPRI17_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_DPA_SHIFT)) & DMA_DCHPRI17_DPA_MASK)
 #define DMA_DCHPRI17_ECP_MASK                    (0x80U)
 #define DMA_DCHPRI17_ECP_SHIFT                   (7U)
+/*! ECP - Enable Channel Preemption. This field resets to 0.
+ *  0b0..Channel n cannot be suspended by a higher priority channel's service request.
+ *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
+ */
 #define DMA_DCHPRI17_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_ECP_SHIFT)) & DMA_DCHPRI17_ECP_MASK)
 /*! @} */
 
@@ -8541,9 +14141,17 @@ typedef struct {
 #define DMA_DCHPRI16_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_GRPPRI_SHIFT)) & DMA_DCHPRI16_GRPPRI_MASK)
 #define DMA_DCHPRI16_DPA_MASK                    (0x40U)
 #define DMA_DCHPRI16_DPA_SHIFT                   (6U)
+/*! DPA - Disable Preempt Ability. This field resets to 0.
+ *  0b0..Channel n can suspend a lower priority channel.
+ *  0b1..Channel n cannot suspend any channel, regardless of channel priority.
+ */
 #define DMA_DCHPRI16_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_DPA_SHIFT)) & DMA_DCHPRI16_DPA_MASK)
 #define DMA_DCHPRI16_ECP_MASK                    (0x80U)
 #define DMA_DCHPRI16_ECP_SHIFT                   (7U)
+/*! ECP - Enable Channel Preemption. This field resets to 0.
+ *  0b0..Channel n cannot be suspended by a higher priority channel's service request.
+ *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
+ */
 #define DMA_DCHPRI16_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_ECP_SHIFT)) & DMA_DCHPRI16_ECP_MASK)
 /*! @} */
 
@@ -8557,9 +14165,17 @@ typedef struct {
 #define DMA_DCHPRI23_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_GRPPRI_SHIFT)) & DMA_DCHPRI23_GRPPRI_MASK)
 #define DMA_DCHPRI23_DPA_MASK                    (0x40U)
 #define DMA_DCHPRI23_DPA_SHIFT                   (6U)
+/*! DPA - Disable Preempt Ability. This field resets to 0.
+ *  0b0..Channel n can suspend a lower priority channel.
+ *  0b1..Channel n cannot suspend any channel, regardless of channel priority.
+ */
 #define DMA_DCHPRI23_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_DPA_SHIFT)) & DMA_DCHPRI23_DPA_MASK)
 #define DMA_DCHPRI23_ECP_MASK                    (0x80U)
 #define DMA_DCHPRI23_ECP_SHIFT                   (7U)
+/*! ECP - Enable Channel Preemption. This field resets to 0.
+ *  0b0..Channel n cannot be suspended by a higher priority channel's service request.
+ *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
+ */
 #define DMA_DCHPRI23_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_ECP_SHIFT)) & DMA_DCHPRI23_ECP_MASK)
 /*! @} */
 
@@ -8573,9 +14189,17 @@ typedef struct {
 #define DMA_DCHPRI22_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_GRPPRI_SHIFT)) & DMA_DCHPRI22_GRPPRI_MASK)
 #define DMA_DCHPRI22_DPA_MASK                    (0x40U)
 #define DMA_DCHPRI22_DPA_SHIFT                   (6U)
+/*! DPA - Disable Preempt Ability. This field resets to 0.
+ *  0b0..Channel n can suspend a lower priority channel.
+ *  0b1..Channel n cannot suspend any channel, regardless of channel priority.
+ */
 #define DMA_DCHPRI22_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_DPA_SHIFT)) & DMA_DCHPRI22_DPA_MASK)
 #define DMA_DCHPRI22_ECP_MASK                    (0x80U)
 #define DMA_DCHPRI22_ECP_SHIFT                   (7U)
+/*! ECP - Enable Channel Preemption. This field resets to 0.
+ *  0b0..Channel n cannot be suspended by a higher priority channel's service request.
+ *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
+ */
 #define DMA_DCHPRI22_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_ECP_SHIFT)) & DMA_DCHPRI22_ECP_MASK)
 /*! @} */
 
@@ -8589,9 +14213,17 @@ typedef struct {
 #define DMA_DCHPRI21_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_GRPPRI_SHIFT)) & DMA_DCHPRI21_GRPPRI_MASK)
 #define DMA_DCHPRI21_DPA_MASK                    (0x40U)
 #define DMA_DCHPRI21_DPA_SHIFT                   (6U)
+/*! DPA - Disable Preempt Ability. This field resets to 0.
+ *  0b0..Channel n can suspend a lower priority channel.
+ *  0b1..Channel n cannot suspend any channel, regardless of channel priority.
+ */
 #define DMA_DCHPRI21_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_DPA_SHIFT)) & DMA_DCHPRI21_DPA_MASK)
 #define DMA_DCHPRI21_ECP_MASK                    (0x80U)
 #define DMA_DCHPRI21_ECP_SHIFT                   (7U)
+/*! ECP - Enable Channel Preemption. This field resets to 0.
+ *  0b0..Channel n cannot be suspended by a higher priority channel's service request.
+ *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
+ */
 #define DMA_DCHPRI21_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_ECP_SHIFT)) & DMA_DCHPRI21_ECP_MASK)
 /*! @} */
 
@@ -8605,9 +14237,17 @@ typedef struct {
 #define DMA_DCHPRI20_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_GRPPRI_SHIFT)) & DMA_DCHPRI20_GRPPRI_MASK)
 #define DMA_DCHPRI20_DPA_MASK                    (0x40U)
 #define DMA_DCHPRI20_DPA_SHIFT                   (6U)
+/*! DPA - Disable Preempt Ability. This field resets to 0.
+ *  0b0..Channel n can suspend a lower priority channel.
+ *  0b1..Channel n cannot suspend any channel, regardless of channel priority.
+ */
 #define DMA_DCHPRI20_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_DPA_SHIFT)) & DMA_DCHPRI20_DPA_MASK)
 #define DMA_DCHPRI20_ECP_MASK                    (0x80U)
 #define DMA_DCHPRI20_ECP_SHIFT                   (7U)
+/*! ECP - Enable Channel Preemption. This field resets to 0.
+ *  0b0..Channel n cannot be suspended by a higher priority channel's service request.
+ *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
+ */
 #define DMA_DCHPRI20_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_ECP_SHIFT)) & DMA_DCHPRI20_ECP_MASK)
 /*! @} */
 
@@ -8621,9 +14261,17 @@ typedef struct {
 #define DMA_DCHPRI27_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_GRPPRI_SHIFT)) & DMA_DCHPRI27_GRPPRI_MASK)
 #define DMA_DCHPRI27_DPA_MASK                    (0x40U)
 #define DMA_DCHPRI27_DPA_SHIFT                   (6U)
+/*! DPA - Disable Preempt Ability. This field resets to 0.
+ *  0b0..Channel n can suspend a lower priority channel.
+ *  0b1..Channel n cannot suspend any channel, regardless of channel priority.
+ */
 #define DMA_DCHPRI27_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_DPA_SHIFT)) & DMA_DCHPRI27_DPA_MASK)
 #define DMA_DCHPRI27_ECP_MASK                    (0x80U)
 #define DMA_DCHPRI27_ECP_SHIFT                   (7U)
+/*! ECP - Enable Channel Preemption. This field resets to 0.
+ *  0b0..Channel n cannot be suspended by a higher priority channel's service request.
+ *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
+ */
 #define DMA_DCHPRI27_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_ECP_SHIFT)) & DMA_DCHPRI27_ECP_MASK)
 /*! @} */
 
@@ -8637,9 +14285,17 @@ typedef struct {
 #define DMA_DCHPRI26_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_GRPPRI_SHIFT)) & DMA_DCHPRI26_GRPPRI_MASK)
 #define DMA_DCHPRI26_DPA_MASK                    (0x40U)
 #define DMA_DCHPRI26_DPA_SHIFT                   (6U)
+/*! DPA - Disable Preempt Ability. This field resets to 0.
+ *  0b0..Channel n can suspend a lower priority channel.
+ *  0b1..Channel n cannot suspend any channel, regardless of channel priority.
+ */
 #define DMA_DCHPRI26_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_DPA_SHIFT)) & DMA_DCHPRI26_DPA_MASK)
 #define DMA_DCHPRI26_ECP_MASK                    (0x80U)
 #define DMA_DCHPRI26_ECP_SHIFT                   (7U)
+/*! ECP - Enable Channel Preemption. This field resets to 0.
+ *  0b0..Channel n cannot be suspended by a higher priority channel's service request.
+ *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
+ */
 #define DMA_DCHPRI26_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_ECP_SHIFT)) & DMA_DCHPRI26_ECP_MASK)
 /*! @} */
 
@@ -8653,9 +14309,17 @@ typedef struct {
 #define DMA_DCHPRI25_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_GRPPRI_SHIFT)) & DMA_DCHPRI25_GRPPRI_MASK)
 #define DMA_DCHPRI25_DPA_MASK                    (0x40U)
 #define DMA_DCHPRI25_DPA_SHIFT                   (6U)
+/*! DPA - Disable Preempt Ability. This field resets to 0.
+ *  0b0..Channel n can suspend a lower priority channel.
+ *  0b1..Channel n cannot suspend any channel, regardless of channel priority.
+ */
 #define DMA_DCHPRI25_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_DPA_SHIFT)) & DMA_DCHPRI25_DPA_MASK)
 #define DMA_DCHPRI25_ECP_MASK                    (0x80U)
 #define DMA_DCHPRI25_ECP_SHIFT                   (7U)
+/*! ECP - Enable Channel Preemption. This field resets to 0.
+ *  0b0..Channel n cannot be suspended by a higher priority channel's service request.
+ *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
+ */
 #define DMA_DCHPRI25_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_ECP_SHIFT)) & DMA_DCHPRI25_ECP_MASK)
 /*! @} */
 
@@ -8669,9 +14333,17 @@ typedef struct {
 #define DMA_DCHPRI24_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_GRPPRI_SHIFT)) & DMA_DCHPRI24_GRPPRI_MASK)
 #define DMA_DCHPRI24_DPA_MASK                    (0x40U)
 #define DMA_DCHPRI24_DPA_SHIFT                   (6U)
+/*! DPA - Disable Preempt Ability. This field resets to 0.
+ *  0b0..Channel n can suspend a lower priority channel.
+ *  0b1..Channel n cannot suspend any channel, regardless of channel priority.
+ */
 #define DMA_DCHPRI24_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_DPA_SHIFT)) & DMA_DCHPRI24_DPA_MASK)
 #define DMA_DCHPRI24_ECP_MASK                    (0x80U)
 #define DMA_DCHPRI24_ECP_SHIFT                   (7U)
+/*! ECP - Enable Channel Preemption. This field resets to 0.
+ *  0b0..Channel n cannot be suspended by a higher priority channel's service request.
+ *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
+ */
 #define DMA_DCHPRI24_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_ECP_SHIFT)) & DMA_DCHPRI24_ECP_MASK)
 /*! @} */
 
@@ -8685,9 +14357,17 @@ typedef struct {
 #define DMA_DCHPRI31_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_GRPPRI_SHIFT)) & DMA_DCHPRI31_GRPPRI_MASK)
 #define DMA_DCHPRI31_DPA_MASK                    (0x40U)
 #define DMA_DCHPRI31_DPA_SHIFT                   (6U)
+/*! DPA - Disable Preempt Ability. This field resets to 0.
+ *  0b0..Channel n can suspend a lower priority channel.
+ *  0b1..Channel n cannot suspend any channel, regardless of channel priority.
+ */
 #define DMA_DCHPRI31_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_DPA_SHIFT)) & DMA_DCHPRI31_DPA_MASK)
 #define DMA_DCHPRI31_ECP_MASK                    (0x80U)
 #define DMA_DCHPRI31_ECP_SHIFT                   (7U)
+/*! ECP - Enable Channel Preemption. This field resets to 0.
+ *  0b0..Channel n cannot be suspended by a higher priority channel's service request.
+ *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
+ */
 #define DMA_DCHPRI31_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_ECP_SHIFT)) & DMA_DCHPRI31_ECP_MASK)
 /*! @} */
 
@@ -8701,9 +14381,17 @@ typedef struct {
 #define DMA_DCHPRI30_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_GRPPRI_SHIFT)) & DMA_DCHPRI30_GRPPRI_MASK)
 #define DMA_DCHPRI30_DPA_MASK                    (0x40U)
 #define DMA_DCHPRI30_DPA_SHIFT                   (6U)
+/*! DPA - Disable Preempt Ability. This field resets to 0.
+ *  0b0..Channel n can suspend a lower priority channel.
+ *  0b1..Channel n cannot suspend any channel, regardless of channel priority.
+ */
 #define DMA_DCHPRI30_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_DPA_SHIFT)) & DMA_DCHPRI30_DPA_MASK)
 #define DMA_DCHPRI30_ECP_MASK                    (0x80U)
 #define DMA_DCHPRI30_ECP_SHIFT                   (7U)
+/*! ECP - Enable Channel Preemption. This field resets to 0.
+ *  0b0..Channel n cannot be suspended by a higher priority channel's service request.
+ *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
+ */
 #define DMA_DCHPRI30_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_ECP_SHIFT)) & DMA_DCHPRI30_ECP_MASK)
 /*! @} */
 
@@ -8717,9 +14405,17 @@ typedef struct {
 #define DMA_DCHPRI29_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_GRPPRI_SHIFT)) & DMA_DCHPRI29_GRPPRI_MASK)
 #define DMA_DCHPRI29_DPA_MASK                    (0x40U)
 #define DMA_DCHPRI29_DPA_SHIFT                   (6U)
+/*! DPA - Disable Preempt Ability. This field resets to 0.
+ *  0b0..Channel n can suspend a lower priority channel.
+ *  0b1..Channel n cannot suspend any channel, regardless of channel priority.
+ */
 #define DMA_DCHPRI29_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_DPA_SHIFT)) & DMA_DCHPRI29_DPA_MASK)
 #define DMA_DCHPRI29_ECP_MASK                    (0x80U)
 #define DMA_DCHPRI29_ECP_SHIFT                   (7U)
+/*! ECP - Enable Channel Preemption. This field resets to 0.
+ *  0b0..Channel n cannot be suspended by a higher priority channel's service request.
+ *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
+ */
 #define DMA_DCHPRI29_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_ECP_SHIFT)) & DMA_DCHPRI29_ECP_MASK)
 /*! @} */
 
@@ -8733,9 +14429,17 @@ typedef struct {
 #define DMA_DCHPRI28_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_GRPPRI_SHIFT)) & DMA_DCHPRI28_GRPPRI_MASK)
 #define DMA_DCHPRI28_DPA_MASK                    (0x40U)
 #define DMA_DCHPRI28_DPA_SHIFT                   (6U)
+/*! DPA - Disable Preempt Ability. This field resets to 0.
+ *  0b0..Channel n can suspend a lower priority channel.
+ *  0b1..Channel n cannot suspend any channel, regardless of channel priority.
+ */
 #define DMA_DCHPRI28_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_DPA_SHIFT)) & DMA_DCHPRI28_DPA_MASK)
 #define DMA_DCHPRI28_ECP_MASK                    (0x80U)
 #define DMA_DCHPRI28_ECP_SHIFT                   (7U)
+/*! ECP - Enable Channel Preemption. This field resets to 0.
+ *  0b0..Channel n cannot be suspended by a higher priority channel's service request.
+ *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
+ */
 #define DMA_DCHPRI28_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_ECP_SHIFT)) & DMA_DCHPRI28_ECP_MASK)
 /*! @} */
 
@@ -8769,9 +14473,30 @@ typedef struct {
 #define DMA_ATTR_DMOD(x)                         (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DMOD_SHIFT)) & DMA_ATTR_DMOD_MASK)
 #define DMA_ATTR_SSIZE_MASK                      (0x700U)
 #define DMA_ATTR_SSIZE_SHIFT                     (8U)
+/*! SSIZE - Source data transfer size
+ *  0b000..8-bit
+ *  0b001..16-bit
+ *  0b010..32-bit
+ *  0b011..64-bit
+ *  0b100..Reserved
+ *  0b101..32-byte burst (4 beats of 64 bits)
+ *  0b110..Reserved
+ *  0b111..Reserved
+ */
 #define DMA_ATTR_SSIZE(x)                        (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SSIZE_SHIFT)) & DMA_ATTR_SSIZE_MASK)
 #define DMA_ATTR_SMOD_MASK                       (0xF800U)
 #define DMA_ATTR_SMOD_SHIFT                      (11U)
+/*! SMOD - Source Address Modulo
+ *  0b00000..Source address modulo feature is disabled
+ *  0b00001-0b11111..This value defines a specific address range specified to be the value after SADDR + SOFF
+ *                   calculation is performed on the original register value. Setting this field provides the ability
+ *                   to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the
+ *                   queue should start at a 0-modulo-size address and the SMOD field should be set to the
+ *                   appropriate value for the queue, freezing the desired number of upper address bits. The value
+ *                   programmed into this field specifies the number of lower address bits allowed to change. For a
+ *                   circular queue application, the SOFF is typically set to the transfer size to implement
+ *                   post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
+ */
 #define DMA_ATTR_SMOD(x)                         (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SMOD_SHIFT)) & DMA_ATTR_SMOD_MASK)
 /*! @} */
 
@@ -8795,9 +14520,17 @@ typedef struct {
 #define DMA_NBYTES_MLOFFNO_NBYTES(x)             (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFNO_NBYTES_MASK)
 #define DMA_NBYTES_MLOFFNO_DMLOE_MASK            (0x40000000U)
 #define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT           (30U)
+/*! DMLOE - Destination Minor Loop Offset enable
+ *  0b0..The minor loop offset is not applied to the DADDR
+ *  0b1..The minor loop offset is applied to the DADDR
+ */
 #define DMA_NBYTES_MLOFFNO_DMLOE(x)              (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_DMLOE_MASK)
 #define DMA_NBYTES_MLOFFNO_SMLOE_MASK            (0x80000000U)
 #define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT           (31U)
+/*! SMLOE - Source Minor Loop Offset Enable
+ *  0b0..The minor loop offset is not applied to the SADDR
+ *  0b1..The minor loop offset is applied to the SADDR
+ */
 #define DMA_NBYTES_MLOFFNO_SMLOE(x)              (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_SMLOE_MASK)
 /*! @} */
 
@@ -8814,9 +14547,17 @@ typedef struct {
 #define DMA_NBYTES_MLOFFYES_MLOFF(x)             (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_NBYTES_MLOFFYES_MLOFF_MASK)
 #define DMA_NBYTES_MLOFFYES_DMLOE_MASK           (0x40000000U)
 #define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT          (30U)
+/*! DMLOE - Destination Minor Loop Offset enable
+ *  0b0..The minor loop offset is not applied to the DADDR
+ *  0b1..The minor loop offset is applied to the DADDR
+ */
 #define DMA_NBYTES_MLOFFYES_DMLOE(x)             (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_DMLOE_MASK)
 #define DMA_NBYTES_MLOFFYES_SMLOE_MASK           (0x80000000U)
 #define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT          (31U)
+/*! SMLOE - Source Minor Loop Offset Enable
+ *  0b0..The minor loop offset is not applied to the SADDR
+ *  0b1..The minor loop offset is applied to the SADDR
+ */
 #define DMA_NBYTES_MLOFFYES_SMLOE(x)             (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_SMLOE_MASK)
 /*! @} */
 
@@ -8860,6 +14601,10 @@ typedef struct {
 #define DMA_CITER_ELINKNO_CITER(x)               (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_CITER_SHIFT)) & DMA_CITER_ELINKNO_CITER_MASK)
 #define DMA_CITER_ELINKNO_ELINK_MASK             (0x8000U)
 #define DMA_CITER_ELINKNO_ELINK_SHIFT            (15U)
+/*! ELINK - Enable channel-to-channel linking on minor-loop complete
+ *  0b0..The channel-to-channel linking is disabled
+ *  0b1..The channel-to-channel linking is enabled
+ */
 #define DMA_CITER_ELINKNO_ELINK(x)               (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_ELINK_SHIFT)) & DMA_CITER_ELINKNO_ELINK_MASK)
 /*! @} */
 
@@ -8876,6 +14621,10 @@ typedef struct {
 #define DMA_CITER_ELINKYES_LINKCH(x)             (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_CITER_ELINKYES_LINKCH_MASK)
 #define DMA_CITER_ELINKYES_ELINK_MASK            (0x8000U)
 #define DMA_CITER_ELINKYES_ELINK_SHIFT           (15U)
+/*! ELINK - Enable channel-to-channel linking on minor-loop complete
+ *  0b0..The channel-to-channel linking is disabled
+ *  0b1..The channel-to-channel linking is enabled
+ */
 #define DMA_CITER_ELINKYES_ELINK(x)              (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_ELINK_SHIFT)) & DMA_CITER_ELINKYES_ELINK_MASK)
 /*! @} */
 
@@ -8896,21 +14645,46 @@ typedef struct {
 /*! @{ */
 #define DMA_CSR_START_MASK                       (0x1U)
 #define DMA_CSR_START_SHIFT                      (0U)
+/*! START - Channel Start
+ *  0b0..The channel is not explicitly started.
+ *  0b1..The channel is explicitly started via a software initiated service request.
+ */
 #define DMA_CSR_START(x)                         (((uint16_t)(((uint16_t)(x)) << DMA_CSR_START_SHIFT)) & DMA_CSR_START_MASK)
 #define DMA_CSR_INTMAJOR_MASK                    (0x2U)
 #define DMA_CSR_INTMAJOR_SHIFT                   (1U)
+/*! INTMAJOR - Enable an interrupt when major iteration count completes.
+ *  0b0..The end-of-major loop interrupt is disabled.
+ *  0b1..The end-of-major loop interrupt is enabled.
+ */
 #define DMA_CSR_INTMAJOR(x)                      (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTMAJOR_SHIFT)) & DMA_CSR_INTMAJOR_MASK)
 #define DMA_CSR_INTHALF_MASK                     (0x4U)
 #define DMA_CSR_INTHALF_SHIFT                    (2U)
+/*! INTHALF - Enable an interrupt when major counter is half complete.
+ *  0b0..The half-point interrupt is disabled.
+ *  0b1..The half-point interrupt is enabled.
+ */
 #define DMA_CSR_INTHALF(x)                       (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK)
 #define DMA_CSR_DREQ_MASK                        (0x8U)
 #define DMA_CSR_DREQ_SHIFT                       (3U)
+/*! DREQ - Disable Request
+ *  0b0..The channel's ERQ bit is not affected.
+ *  0b1..The channel's ERQ bit is cleared when the major loop is complete.
+ */
 #define DMA_CSR_DREQ(x)                          (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DREQ_SHIFT)) & DMA_CSR_DREQ_MASK)
 #define DMA_CSR_ESG_MASK                         (0x10U)
 #define DMA_CSR_ESG_SHIFT                        (4U)
+/*! ESG - Enable Scatter/Gather Processing
+ *  0b0..The current channel's TCD is normal format.
+ *  0b1..The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer
+ *       to the next TCD to be loaded into this channel after the major loop completes its execution.
+ */
 #define DMA_CSR_ESG(x)                           (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ESG_SHIFT)) & DMA_CSR_ESG_MASK)
 #define DMA_CSR_MAJORELINK_MASK                  (0x20U)
 #define DMA_CSR_MAJORELINK_SHIFT                 (5U)
+/*! MAJORELINK - Enable channel-to-channel linking on major loop complete
+ *  0b0..The channel-to-channel linking is disabled.
+ *  0b1..The channel-to-channel linking is enabled.
+ */
 #define DMA_CSR_MAJORELINK(x)                    (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORELINK_SHIFT)) & DMA_CSR_MAJORELINK_MASK)
 #define DMA_CSR_ACTIVE_MASK                      (0x40U)
 #define DMA_CSR_ACTIVE_SHIFT                     (6U)
@@ -8923,6 +14697,12 @@ typedef struct {
 #define DMA_CSR_MAJORLINKCH(x)                   (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORLINKCH_SHIFT)) & DMA_CSR_MAJORLINKCH_MASK)
 #define DMA_CSR_BWC_MASK                         (0xC000U)
 #define DMA_CSR_BWC_SHIFT                        (14U)
+/*! BWC - Bandwidth Control
+ *  0b00..No eDMA engine stalls.
+ *  0b01..Reserved
+ *  0b10..eDMA engine stalls for 4 cycles after each R/W.
+ *  0b11..eDMA engine stalls for 8 cycles after each R/W.
+ */
 #define DMA_CSR_BWC(x)                           (((uint16_t)(((uint16_t)(x)) << DMA_CSR_BWC_SHIFT)) & DMA_CSR_BWC_MASK)
 /*! @} */
 
@@ -8936,6 +14716,10 @@ typedef struct {
 #define DMA_BITER_ELINKNO_BITER(x)               (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_BITER_SHIFT)) & DMA_BITER_ELINKNO_BITER_MASK)
 #define DMA_BITER_ELINKNO_ELINK_MASK             (0x8000U)
 #define DMA_BITER_ELINKNO_ELINK_SHIFT            (15U)
+/*! ELINK - Enables channel-to-channel linking on minor loop complete
+ *  0b0..The channel-to-channel linking is disabled
+ *  0b1..The channel-to-channel linking is enabled
+ */
 #define DMA_BITER_ELINKNO_ELINK(x)               (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_ELINK_SHIFT)) & DMA_BITER_ELINKNO_ELINK_MASK)
 /*! @} */
 
@@ -8952,6 +14736,10 @@ typedef struct {
 #define DMA_BITER_ELINKYES_LINKCH(x)             (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_BITER_ELINKYES_LINKCH_MASK)
 #define DMA_BITER_ELINKYES_ELINK_MASK            (0x8000U)
 #define DMA_BITER_ELINKYES_ELINK_SHIFT           (15U)
+/*! ELINK - Enables channel-to-channel linking on minor loop complete
+ *  0b0..The channel-to-channel linking is disabled
+ *  0b1..The channel-to-channel linking is enabled
+ */
 #define DMA_BITER_ELINKYES_ELINK(x)              (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_ELINK_SHIFT)) & DMA_BITER_ELINKYES_ELINK_MASK)
 /*! @} */
 
@@ -9012,12 +14800,25 @@ typedef struct {
 #define DMAMUX_CHCFG_SOURCE(x)                   (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK)
 #define DMAMUX_CHCFG_A_ON_MASK                   (0x20000000U)
 #define DMAMUX_CHCFG_A_ON_SHIFT                  (29U)
+/*! A_ON - DMA Channel Always Enable
+ *  0b0..DMA Channel Always ON function is disabled
+ *  0b1..DMA Channel Always ON function is enabled
+ */
 #define DMAMUX_CHCFG_A_ON(x)                     (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_A_ON_SHIFT)) & DMAMUX_CHCFG_A_ON_MASK)
 #define DMAMUX_CHCFG_TRIG_MASK                   (0x40000000U)
 #define DMAMUX_CHCFG_TRIG_SHIFT                  (30U)
+/*! TRIG - DMA Channel Trigger Enable
+ *  0b0..Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the
+ *       specified source to the DMA channel. (Normal mode)
+ *  0b1..Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.
+ */
 #define DMAMUX_CHCFG_TRIG(x)                     (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK)
 #define DMAMUX_CHCFG_ENBL_MASK                   (0x80000000U)
 #define DMAMUX_CHCFG_ENBL_SHIFT                  (31U)
+/*! ENBL - DMA Mux Channel Enable
+ *  0b0..DMA Mux channel is disabled
+ *  0b1..DMA Mux channel is enabled
+ */
 #define DMAMUX_CHCFG_ENBL(x)                     (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK)
 /*! @} */
 
@@ -9091,51 +14892,118 @@ typedef struct {
 /*! @{ */
 #define ENC_CTRL_CMPIE_MASK                      (0x1U)
 #define ENC_CTRL_CMPIE_SHIFT                     (0U)
+/*! CMPIE - Compare Interrupt Enable
+ *  0b0..Compare interrupt is disabled
+ *  0b1..Compare interrupt is enabled
+ */
 #define ENC_CTRL_CMPIE(x)                        (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_CMPIE_SHIFT)) & ENC_CTRL_CMPIE_MASK)
 #define ENC_CTRL_CMPIRQ_MASK                     (0x2U)
 #define ENC_CTRL_CMPIRQ_SHIFT                    (1U)
+/*! CMPIRQ - Compare Interrupt Request
+ *  0b0..No match has occurred
+ *  0b1..COMP match has occurred
+ */
 #define ENC_CTRL_CMPIRQ(x)                       (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_CMPIRQ_SHIFT)) & ENC_CTRL_CMPIRQ_MASK)
 #define ENC_CTRL_WDE_MASK                        (0x4U)
 #define ENC_CTRL_WDE_SHIFT                       (2U)
+/*! WDE - Watchdog Enable
+ *  0b0..Watchdog timer is disabled
+ *  0b1..Watchdog timer is enabled
+ */
 #define ENC_CTRL_WDE(x)                          (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_WDE_SHIFT)) & ENC_CTRL_WDE_MASK)
 #define ENC_CTRL_DIE_MASK                        (0x8U)
 #define ENC_CTRL_DIE_SHIFT                       (3U)
+/*! DIE - Watchdog Timeout Interrupt Enable
+ *  0b0..Watchdog timer interrupt is disabled
+ *  0b1..Watchdog timer interrupt is enabled
+ */
 #define ENC_CTRL_DIE(x)                          (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_DIE_SHIFT)) & ENC_CTRL_DIE_MASK)
 #define ENC_CTRL_DIRQ_MASK                       (0x10U)
 #define ENC_CTRL_DIRQ_SHIFT                      (4U)
+/*! DIRQ - Watchdog Timeout Interrupt Request
+ *  0b0..No interrupt has occurred
+ *  0b1..Watchdog timeout interrupt has occurred
+ */
 #define ENC_CTRL_DIRQ(x)                         (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_DIRQ_SHIFT)) & ENC_CTRL_DIRQ_MASK)
 #define ENC_CTRL_XNE_MASK                        (0x20U)
 #define ENC_CTRL_XNE_SHIFT                       (5U)
+/*! XNE - Use Negative Edge of INDEX Pulse
+ *  0b0..Use positive transition edge of INDEX pulse
+ *  0b1..Use negative transition edge of INDEX pulse
+ */
 #define ENC_CTRL_XNE(x)                          (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XNE_SHIFT)) & ENC_CTRL_XNE_MASK)
 #define ENC_CTRL_XIP_MASK                        (0x40U)
 #define ENC_CTRL_XIP_SHIFT                       (6U)
+/*! XIP - INDEX Triggered Initialization of Position Counters UPOS and LPOS
+ *  0b0..No action
+ *  0b1..INDEX pulse initializes the position counter
+ */
 #define ENC_CTRL_XIP(x)                          (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIP_SHIFT)) & ENC_CTRL_XIP_MASK)
 #define ENC_CTRL_XIE_MASK                        (0x80U)
 #define ENC_CTRL_XIE_SHIFT                       (7U)
+/*! XIE - INDEX Pulse Interrupt Enable
+ *  0b0..INDEX pulse interrupt is disabled
+ *  0b1..INDEX pulse interrupt is enabled
+ */
 #define ENC_CTRL_XIE(x)                          (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIE_SHIFT)) & ENC_CTRL_XIE_MASK)
 #define ENC_CTRL_XIRQ_MASK                       (0x100U)
 #define ENC_CTRL_XIRQ_SHIFT                      (8U)
+/*! XIRQ - INDEX Pulse Interrupt Request
+ *  0b0..No interrupt has occurred
+ *  0b1..INDEX pulse interrupt has occurred
+ */
 #define ENC_CTRL_XIRQ(x)                         (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIRQ_SHIFT)) & ENC_CTRL_XIRQ_MASK)
 #define ENC_CTRL_PH1_MASK                        (0x200U)
 #define ENC_CTRL_PH1_SHIFT                       (9U)
+/*! PH1 - Enable Signal Phase Count Mode
+ *  0b0..Use standard quadrature decoder where PHASEA and PHASEB represent a two phase quadrature signal.
+ *  0b1..Bypass the quadrature decoder. A positive transition of the PHASEA input generates a count signal. The
+ *       PHASEB input and the REV bit control the counter direction. If CTRL[REV] = 0, PHASEB = 0, then count up If
+ *       CTRL[REV] = 0, PHASEB = 1, then count down If CTRL[REV] = 1, PHASEB = 0, then count down If CTRL[REV] = 1,
+ *       PHASEB = 1, then count up
+ */
 #define ENC_CTRL_PH1(x)                          (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_PH1_SHIFT)) & ENC_CTRL_PH1_MASK)
 #define ENC_CTRL_REV_MASK                        (0x400U)
 #define ENC_CTRL_REV_SHIFT                       (10U)
+/*! REV - Enable Reverse Direction Counting
+ *  0b0..Count normally
+ *  0b1..Count in the reverse direction
+ */
 #define ENC_CTRL_REV(x)                          (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_REV_SHIFT)) & ENC_CTRL_REV_MASK)
 #define ENC_CTRL_SWIP_MASK                       (0x800U)
 #define ENC_CTRL_SWIP_SHIFT                      (11U)
+/*! SWIP - Software Triggered Initialization of Position Counters UPOS and LPOS
+ *  0b0..No action
+ *  0b1..Initialize position counter
+ */
 #define ENC_CTRL_SWIP(x)                         (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_SWIP_SHIFT)) & ENC_CTRL_SWIP_MASK)
 #define ENC_CTRL_HNE_MASK                        (0x1000U)
 #define ENC_CTRL_HNE_SHIFT                       (12U)
+/*! HNE - Use Negative Edge of HOME Input
+ *  0b0..Use positive going edge-to-trigger initialization of position counters UPOS and LPOS
+ *  0b1..Use negative going edge-to-trigger initialization of position counters UPOS and LPOS
+ */
 #define ENC_CTRL_HNE(x)                          (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HNE_SHIFT)) & ENC_CTRL_HNE_MASK)
 #define ENC_CTRL_HIP_MASK                        (0x2000U)
 #define ENC_CTRL_HIP_SHIFT                       (13U)
+/*! HIP - Enable HOME to Initialize Position Counters UPOS and LPOS
+ *  0b0..No action
+ *  0b1..HOME signal initializes the position counter
+ */
 #define ENC_CTRL_HIP(x)                          (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIP_SHIFT)) & ENC_CTRL_HIP_MASK)
 #define ENC_CTRL_HIE_MASK                        (0x4000U)
 #define ENC_CTRL_HIE_SHIFT                       (14U)
+/*! HIE - HOME Interrupt Enable
+ *  0b0..Disable HOME interrupts
+ *  0b1..Enable HOME interrupts
+ */
 #define ENC_CTRL_HIE(x)                          (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIE_SHIFT)) & ENC_CTRL_HIE_MASK)
 #define ENC_CTRL_HIRQ_MASK                       (0x8000U)
 #define ENC_CTRL_HIRQ_SHIFT                      (15U)
+/*! HIRQ - HOME Signal Transition Interrupt Request
+ *  0b0..No interrupt
+ *  0b1..HOME signal transition interrupt request
+ */
 #define ENC_CTRL_HIRQ(x)                         (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIRQ_SHIFT)) & ENC_CTRL_HIRQ_MASK)
 /*! @} */
 
@@ -9264,12 +15132,24 @@ typedef struct {
 #define ENC_TST_TEST_PERIOD(x)                   (((uint16_t)(((uint16_t)(x)) << ENC_TST_TEST_PERIOD_SHIFT)) & ENC_TST_TEST_PERIOD_MASK)
 #define ENC_TST_QDN_MASK                         (0x2000U)
 #define ENC_TST_QDN_SHIFT                        (13U)
+/*! QDN - Quadrature Decoder Negative Signal
+ *  0b0..Leaves quadrature decoder signal in a positive direction
+ *  0b1..Generates a negative quadrature decoder signal
+ */
 #define ENC_TST_QDN(x)                           (((uint16_t)(((uint16_t)(x)) << ENC_TST_QDN_SHIFT)) & ENC_TST_QDN_MASK)
 #define ENC_TST_TCE_MASK                         (0x4000U)
 #define ENC_TST_TCE_SHIFT                        (14U)
+/*! TCE - Test Counter Enable
+ *  0b0..Test count is not enabled
+ *  0b1..Test count is enabled
+ */
 #define ENC_TST_TCE(x)                           (((uint16_t)(((uint16_t)(x)) << ENC_TST_TCE_SHIFT)) & ENC_TST_TCE_MASK)
 #define ENC_TST_TEN_MASK                         (0x8000U)
 #define ENC_TST_TEN_SHIFT                        (15U)
+/*! TEN - Test Mode Enable
+ *  0b0..Test module is not enabled
+ *  0b1..Test module is enabled
+ */
 #define ENC_TST_TEN(x)                           (((uint16_t)(((uint16_t)(x)) << ENC_TST_TEN_SHIFT)) & ENC_TST_TEN_MASK)
 /*! @} */
 
@@ -9277,39 +15157,87 @@ typedef struct {
 /*! @{ */
 #define ENC_CTRL2_UPDHLD_MASK                    (0x1U)
 #define ENC_CTRL2_UPDHLD_SHIFT                   (0U)
+/*! UPDHLD - Update Hold Registers
+ *  0b0..Disable updates of hold registers on rising edge of TRIGGER
+ *  0b1..Enable updates of hold registers on rising edge of TRIGGER
+ */
 #define ENC_CTRL2_UPDHLD(x)                      (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_UPDHLD_SHIFT)) & ENC_CTRL2_UPDHLD_MASK)
 #define ENC_CTRL2_UPDPOS_MASK                    (0x2U)
 #define ENC_CTRL2_UPDPOS_SHIFT                   (1U)
+/*! UPDPOS - Update Position Registers
+ *  0b0..No action for POSD, REV, UPOS and LPOS on rising edge of TRIGGER
+ *  0b1..Clear POSD, REV, UPOS and LPOS on rising edge of TRIGGER
+ */
 #define ENC_CTRL2_UPDPOS(x)                      (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_UPDPOS_SHIFT)) & ENC_CTRL2_UPDPOS_MASK)
 #define ENC_CTRL2_MOD_MASK                       (0x4U)
 #define ENC_CTRL2_MOD_SHIFT                      (2U)
+/*! MOD - Enable Modulo Counting
+ *  0b0..Disable modulo counting
+ *  0b1..Enable modulo counting
+ */
 #define ENC_CTRL2_MOD(x)                         (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_MOD_SHIFT)) & ENC_CTRL2_MOD_MASK)
 #define ENC_CTRL2_DIR_MASK                       (0x8U)
 #define ENC_CTRL2_DIR_SHIFT                      (3U)
+/*! DIR - Count Direction Flag
+ *  0b0..Last count was in the down direction
+ *  0b1..Last count was in the up direction
+ */
 #define ENC_CTRL2_DIR(x)                         (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_DIR_SHIFT)) & ENC_CTRL2_DIR_MASK)
 #define ENC_CTRL2_RUIE_MASK                      (0x10U)
 #define ENC_CTRL2_RUIE_SHIFT                     (4U)
+/*! RUIE - Roll-under Interrupt Enable
+ *  0b0..Roll-under interrupt is disabled
+ *  0b1..Roll-under interrupt is enabled
+ */
 #define ENC_CTRL2_RUIE(x)                        (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_RUIE_SHIFT)) & ENC_CTRL2_RUIE_MASK)
 #define ENC_CTRL2_RUIRQ_MASK                     (0x20U)
 #define ENC_CTRL2_RUIRQ_SHIFT                    (5U)
+/*! RUIRQ - Roll-under Interrupt Request
+ *  0b0..No roll-under has occurred
+ *  0b1..Roll-under has occurred
+ */
 #define ENC_CTRL2_RUIRQ(x)                       (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_RUIRQ_SHIFT)) & ENC_CTRL2_RUIRQ_MASK)
 #define ENC_CTRL2_ROIE_MASK                      (0x40U)
 #define ENC_CTRL2_ROIE_SHIFT                     (6U)
+/*! ROIE - Roll-over Interrupt Enable
+ *  0b0..Roll-over interrupt is disabled
+ *  0b1..Roll-over interrupt is enabled
+ */
 #define ENC_CTRL2_ROIE(x)                        (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_ROIE_SHIFT)) & ENC_CTRL2_ROIE_MASK)
 #define ENC_CTRL2_ROIRQ_MASK                     (0x80U)
 #define ENC_CTRL2_ROIRQ_SHIFT                    (7U)
+/*! ROIRQ - Roll-over Interrupt Request
+ *  0b0..No roll-over has occurred
+ *  0b1..Roll-over has occurred
+ */
 #define ENC_CTRL2_ROIRQ(x)                       (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_ROIRQ_SHIFT)) & ENC_CTRL2_ROIRQ_MASK)
 #define ENC_CTRL2_REVMOD_MASK                    (0x100U)
 #define ENC_CTRL2_REVMOD_SHIFT                   (8U)
+/*! REVMOD - Revolution Counter Modulus Enable
+ *  0b0..Use INDEX pulse to increment/decrement revolution counter (REV).
+ *  0b1..Use modulus counting roll-over/under to increment/decrement revolution counter (REV).
+ */
 #define ENC_CTRL2_REVMOD(x)                      (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_REVMOD_SHIFT)) & ENC_CTRL2_REVMOD_MASK)
 #define ENC_CTRL2_OUTCTL_MASK                    (0x200U)
 #define ENC_CTRL2_OUTCTL_SHIFT                   (9U)
+/*! OUTCTL - Output Control
+ *  0b0..POSMATCH pulses when a match occurs between the position counters (POS) and the compare value (COMP).
+ *  0b1..POSMATCH pulses when the UPOS, LPOS, REV, or POSD registers are read.
+ */
 #define ENC_CTRL2_OUTCTL(x)                      (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_OUTCTL_SHIFT)) & ENC_CTRL2_OUTCTL_MASK)
 #define ENC_CTRL2_SABIE_MASK                     (0x400U)
 #define ENC_CTRL2_SABIE_SHIFT                    (10U)
+/*! SABIE - Simultaneous PHASEA and PHASEB Change Interrupt Enable
+ *  0b0..Simultaneous PHASEA and PHASEB change interrupt disabled.
+ *  0b1..Simultaneous PHASEA and PHASEB change interrupt enabled.
+ */
 #define ENC_CTRL2_SABIE(x)                       (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_SABIE_SHIFT)) & ENC_CTRL2_SABIE_MASK)
 #define ENC_CTRL2_SABIRQ_MASK                    (0x800U)
 #define ENC_CTRL2_SABIRQ_SHIFT                   (11U)
+/*! SABIRQ - Simultaneous PHASEA and PHASEB Change Interrupt Request
+ *  0b0..No simultaneous change of PHASEA and PHASEB has occurred.
+ *  0b1..A simultaneous change of PHASEA and PHASEB has occurred.
+ */
 #define ENC_CTRL2_SABIRQ(x)                      (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_SABIRQ_SHIFT)) & ENC_CTRL2_SABIRQ_MASK)
 /*! @} */
 
@@ -9609,18 +15537,38 @@ typedef struct {
 #define ENET_EIMR_RXF(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF_SHIFT)) & ENET_EIMR_RXF_MASK)
 #define ENET_EIMR_TXB_MASK                       (0x4000000U)
 #define ENET_EIMR_TXB_SHIFT                      (26U)
+/*! TXB - TXB Interrupt Mask
+ *  0b0..The corresponding interrupt source is masked.
+ *  0b1..The corresponding interrupt source is not masked.
+ */
 #define ENET_EIMR_TXB(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB_SHIFT)) & ENET_EIMR_TXB_MASK)
 #define ENET_EIMR_TXF_MASK                       (0x8000000U)
 #define ENET_EIMR_TXF_SHIFT                      (27U)
+/*! TXF - TXF Interrupt Mask
+ *  0b0..The corresponding interrupt source is masked.
+ *  0b1..The corresponding interrupt source is not masked.
+ */
 #define ENET_EIMR_TXF(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF_SHIFT)) & ENET_EIMR_TXF_MASK)
 #define ENET_EIMR_GRA_MASK                       (0x10000000U)
 #define ENET_EIMR_GRA_SHIFT                      (28U)
+/*! GRA - GRA Interrupt Mask
+ *  0b0..The corresponding interrupt source is masked.
+ *  0b1..The corresponding interrupt source is not masked.
+ */
 #define ENET_EIMR_GRA(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_GRA_SHIFT)) & ENET_EIMR_GRA_MASK)
 #define ENET_EIMR_BABT_MASK                      (0x20000000U)
 #define ENET_EIMR_BABT_SHIFT                     (29U)
+/*! BABT - BABT Interrupt Mask
+ *  0b0..The corresponding interrupt source is masked.
+ *  0b1..The corresponding interrupt source is not masked.
+ */
 #define ENET_EIMR_BABT(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABT_SHIFT)) & ENET_EIMR_BABT_MASK)
 #define ENET_EIMR_BABR_MASK                      (0x40000000U)
 #define ENET_EIMR_BABR_SHIFT                     (30U)
+/*! BABR - BABR Interrupt Mask
+ *  0b0..The corresponding interrupt source is masked.
+ *  0b1..The corresponding interrupt source is not masked.
+ */
 #define ENET_EIMR_BABR(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABR_SHIFT)) & ENET_EIMR_BABR_MASK)
 /*! @} */
 
@@ -9645,21 +15593,45 @@ typedef struct {
 #define ENET_ECR_RESET(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_ECR_RESET_SHIFT)) & ENET_ECR_RESET_MASK)
 #define ENET_ECR_ETHEREN_MASK                    (0x2U)
 #define ENET_ECR_ETHEREN_SHIFT                   (1U)
+/*! ETHEREN - Ethernet Enable
+ *  0b0..Reception immediately stops and transmission stops after a bad CRC is appended to any currently transmitted frame.
+ *  0b1..MAC is enabled, and reception and transmission are possible.
+ */
 #define ENET_ECR_ETHEREN(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_ECR_ETHEREN_SHIFT)) & ENET_ECR_ETHEREN_MASK)
 #define ENET_ECR_MAGICEN_MASK                    (0x4U)
 #define ENET_ECR_MAGICEN_SHIFT                   (2U)
+/*! MAGICEN - Magic Packet Detection Enable
+ *  0b0..Magic detection logic disabled.
+ *  0b1..The MAC core detects magic packets and asserts EIR[WAKEUP] when a frame is detected.
+ */
 #define ENET_ECR_MAGICEN(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_ECR_MAGICEN_SHIFT)) & ENET_ECR_MAGICEN_MASK)
 #define ENET_ECR_SLEEP_MASK                      (0x8U)
 #define ENET_ECR_SLEEP_SHIFT                     (3U)
+/*! SLEEP - Sleep Mode Enable
+ *  0b0..Normal operating mode.
+ *  0b1..Sleep mode.
+ */
 #define ENET_ECR_SLEEP(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SLEEP_SHIFT)) & ENET_ECR_SLEEP_MASK)
 #define ENET_ECR_EN1588_MASK                     (0x10U)
 #define ENET_ECR_EN1588_SHIFT                    (4U)
+/*! EN1588 - EN1588 Enable
+ *  0b0..Legacy FEC buffer descriptors and functions enabled.
+ *  0b1..Enhanced frame time-stamping functions enabled.
+ */
 #define ENET_ECR_EN1588(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_ECR_EN1588_SHIFT)) & ENET_ECR_EN1588_MASK)
 #define ENET_ECR_DBGEN_MASK                      (0x40U)
 #define ENET_ECR_DBGEN_SHIFT                     (6U)
+/*! DBGEN - Debug Enable
+ *  0b0..MAC continues operation in debug mode.
+ *  0b1..MAC enters hardware freeze mode when the processor is in debug mode.
+ */
 #define ENET_ECR_DBGEN(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBGEN_SHIFT)) & ENET_ECR_DBGEN_MASK)
 #define ENET_ECR_DBSWP_MASK                      (0x100U)
 #define ENET_ECR_DBSWP_SHIFT                     (8U)
+/*! DBSWP - Descriptor Byte Swapping Enable
+ *  0b0..The buffer descriptor bytes are not swapped to support big-endian devices.
+ *  0b1..The buffer descriptor bytes are swapped to support little-endian devices.
+ */
 #define ENET_ECR_DBSWP(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBSWP_SHIFT)) & ENET_ECR_DBSWP_MASK)
 /*! @} */
 
@@ -9692,9 +15664,19 @@ typedef struct {
 #define ENET_MSCR_MII_SPEED(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_MII_SPEED_SHIFT)) & ENET_MSCR_MII_SPEED_MASK)
 #define ENET_MSCR_DIS_PRE_MASK                   (0x80U)
 #define ENET_MSCR_DIS_PRE_SHIFT                  (7U)
+/*! DIS_PRE - Disable Preamble
+ *  0b0..Preamble enabled.
+ *  0b1..Preamble (32 ones) is not prepended to the MII management frame.
+ */
 #define ENET_MSCR_DIS_PRE(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_DIS_PRE_SHIFT)) & ENET_MSCR_DIS_PRE_MASK)
 #define ENET_MSCR_HOLDTIME_MASK                  (0x700U)
 #define ENET_MSCR_HOLDTIME_SHIFT                 (8U)
+/*! HOLDTIME - Hold time On MDIO Output
+ *  0b000..1 internal module clock cycle
+ *  0b001..2 internal module clock cycles
+ *  0b010..3 internal module clock cycles
+ *  0b111..8 internal module clock cycles
+ */
 #define ENET_MSCR_HOLDTIME(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_HOLDTIME_SHIFT)) & ENET_MSCR_HOLDTIME_MASK)
 /*! @} */
 
@@ -9702,12 +15684,24 @@ typedef struct {
 /*! @{ */
 #define ENET_MIBC_MIB_CLEAR_MASK                 (0x20000000U)
 #define ENET_MIBC_MIB_CLEAR_SHIFT                (29U)
+/*! MIB_CLEAR - MIB Clear
+ *  0b0..See note above.
+ *  0b1..All statistics counters are reset to 0.
+ */
 #define ENET_MIBC_MIB_CLEAR(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_CLEAR_SHIFT)) & ENET_MIBC_MIB_CLEAR_MASK)
 #define ENET_MIBC_MIB_IDLE_MASK                  (0x40000000U)
 #define ENET_MIBC_MIB_IDLE_SHIFT                 (30U)
+/*! MIB_IDLE - MIB Idle
+ *  0b0..The MIB block is updating MIB counters.
+ *  0b1..The MIB block is not currently updating any MIB counters.
+ */
 #define ENET_MIBC_MIB_IDLE(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_IDLE_SHIFT)) & ENET_MIBC_MIB_IDLE_MASK)
 #define ENET_MIBC_MIB_DIS_MASK                   (0x80000000U)
 #define ENET_MIBC_MIB_DIS_SHIFT                  (31U)
+/*! MIB_DIS - Disable MIB Logic
+ *  0b0..MIB logic is enabled.
+ *  0b1..MIB logic is disabled. The MIB logic halts and does not update any MIB counters.
+ */
 #define ENET_MIBC_MIB_DIS(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_DIS_SHIFT)) & ENET_MIBC_MIB_DIS_MASK)
 /*! @} */
 
@@ -9715,15 +15709,31 @@ typedef struct {
 /*! @{ */
 #define ENET_RCR_LOOP_MASK                       (0x1U)
 #define ENET_RCR_LOOP_SHIFT                      (0U)
+/*! LOOP - Internal Loopback
+ *  0b0..Loopback disabled.
+ *  0b1..Transmitted frames are looped back internal to the device and transmit MII output signals are not asserted. DRT must be cleared.
+ */
 #define ENET_RCR_LOOP(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_RCR_LOOP_SHIFT)) & ENET_RCR_LOOP_MASK)
 #define ENET_RCR_DRT_MASK                        (0x2U)
 #define ENET_RCR_DRT_SHIFT                       (1U)
+/*! DRT - Disable Receive On Transmit
+ *  0b0..Receive path operates independently of transmit (i.e., full-duplex mode). Can also be used to monitor transmit activity in half-duplex mode.
+ *  0b1..Disable reception of frames while transmitting. (Normally used for half-duplex mode.)
+ */
 #define ENET_RCR_DRT(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_RCR_DRT_SHIFT)) & ENET_RCR_DRT_MASK)
 #define ENET_RCR_MII_MODE_MASK                   (0x4U)
 #define ENET_RCR_MII_MODE_SHIFT                  (2U)
+/*! MII_MODE - Media Independent Interface Mode
+ *  0b0..Reserved.
+ *  0b1..MII or RMII mode, as indicated by the RMII_MODE field.
+ */
 #define ENET_RCR_MII_MODE(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MII_MODE_SHIFT)) & ENET_RCR_MII_MODE_MASK)
 #define ENET_RCR_PROM_MASK                       (0x8U)
 #define ENET_RCR_PROM_SHIFT                      (3U)
+/*! PROM - Promiscuous Mode
+ *  0b0..Disabled.
+ *  0b1..Enabled.
+ */
 #define ENET_RCR_PROM(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PROM_SHIFT)) & ENET_RCR_PROM_MASK)
 #define ENET_RCR_BC_REJ_MASK                     (0x10U)
 #define ENET_RCR_BC_REJ_SHIFT                    (4U)
@@ -9733,27 +15743,55 @@ typedef struct {
 #define ENET_RCR_FCE(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_RCR_FCE_SHIFT)) & ENET_RCR_FCE_MASK)
 #define ENET_RCR_RMII_MODE_MASK                  (0x100U)
 #define ENET_RCR_RMII_MODE_SHIFT                 (8U)
+/*! RMII_MODE - RMII Mode Enable
+ *  0b0..MAC configured for MII mode.
+ *  0b1..MAC configured for RMII operation.
+ */
 #define ENET_RCR_RMII_MODE(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_MODE_SHIFT)) & ENET_RCR_RMII_MODE_MASK)
 #define ENET_RCR_RMII_10T_MASK                   (0x200U)
 #define ENET_RCR_RMII_10T_SHIFT                  (9U)
+/*! RMII_10T
+ *  0b0..100-Mbit/s operation.
+ *  0b1..10-Mbit/s operation.
+ */
 #define ENET_RCR_RMII_10T(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_10T_SHIFT)) & ENET_RCR_RMII_10T_MASK)
 #define ENET_RCR_PADEN_MASK                      (0x1000U)
 #define ENET_RCR_PADEN_SHIFT                     (12U)
+/*! PADEN - Enable Frame Padding Remove On Receive
+ *  0b0..No padding is removed on receive by the MAC.
+ *  0b1..Padding is removed from received frames.
+ */
 #define ENET_RCR_PADEN(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PADEN_SHIFT)) & ENET_RCR_PADEN_MASK)
 #define ENET_RCR_PAUFWD_MASK                     (0x2000U)
 #define ENET_RCR_PAUFWD_SHIFT                    (13U)
+/*! PAUFWD - Terminate/Forward Pause Frames
+ *  0b0..Pause frames are terminated and discarded in the MAC.
+ *  0b1..Pause frames are forwarded to the user application.
+ */
 #define ENET_RCR_PAUFWD(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PAUFWD_SHIFT)) & ENET_RCR_PAUFWD_MASK)
 #define ENET_RCR_CRCFWD_MASK                     (0x4000U)
 #define ENET_RCR_CRCFWD_SHIFT                    (14U)
+/*! CRCFWD - Terminate/Forward Received CRC
+ *  0b0..The CRC field of received frames is transmitted to the user application.
+ *  0b1..The CRC field is stripped from the frame.
+ */
 #define ENET_RCR_CRCFWD(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CRCFWD_SHIFT)) & ENET_RCR_CRCFWD_MASK)
 #define ENET_RCR_CFEN_MASK                       (0x8000U)
 #define ENET_RCR_CFEN_SHIFT                      (15U)
+/*! CFEN - MAC Control Frame Enable
+ *  0b0..MAC control frames with any opcode other than 0x0001 (pause frame) are accepted and forwarded to the client interface.
+ *  0b1..MAC control frames with any opcode other than 0x0001 (pause frame) are silently discarded.
+ */
 #define ENET_RCR_CFEN(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CFEN_SHIFT)) & ENET_RCR_CFEN_MASK)
 #define ENET_RCR_MAX_FL_MASK                     (0x3FFF0000U)
 #define ENET_RCR_MAX_FL_SHIFT                    (16U)
 #define ENET_RCR_MAX_FL(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MAX_FL_SHIFT)) & ENET_RCR_MAX_FL_MASK)
 #define ENET_RCR_NLC_MASK                        (0x40000000U)
 #define ENET_RCR_NLC_SHIFT                       (30U)
+/*! NLC - Payload Length Check Disable
+ *  0b0..The payload length check is disabled.
+ *  0b1..The core checks the frame's payload length with the frame length/type field. Errors are indicated in the EIR[PLR] field.
+ */
 #define ENET_RCR_NLC(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_RCR_NLC_SHIFT)) & ENET_RCR_NLC_MASK)
 #define ENET_RCR_GRS_MASK                        (0x80000000U)
 #define ENET_RCR_GRS_SHIFT                       (31U)
@@ -9770,18 +15808,36 @@ typedef struct {
 #define ENET_TCR_FDEN(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_TCR_FDEN_SHIFT)) & ENET_TCR_FDEN_MASK)
 #define ENET_TCR_TFC_PAUSE_MASK                  (0x8U)
 #define ENET_TCR_TFC_PAUSE_SHIFT                 (3U)
+/*! TFC_PAUSE - Transmit Frame Control Pause
+ *  0b0..No PAUSE frame transmitted.
+ *  0b1..The MAC stops transmission of data frames after the current transmission is complete.
+ */
 #define ENET_TCR_TFC_PAUSE(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_TCR_TFC_PAUSE_SHIFT)) & ENET_TCR_TFC_PAUSE_MASK)
 #define ENET_TCR_RFC_PAUSE_MASK                  (0x10U)
 #define ENET_TCR_RFC_PAUSE_SHIFT                 (4U)
 #define ENET_TCR_RFC_PAUSE(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_TCR_RFC_PAUSE_SHIFT)) & ENET_TCR_RFC_PAUSE_MASK)
 #define ENET_TCR_ADDSEL_MASK                     (0xE0U)
 #define ENET_TCR_ADDSEL_SHIFT                    (5U)
+/*! ADDSEL - Source MAC Address Select On Transmit
+ *  0b000..Node MAC address programmed on PADDR1/2 registers.
+ *  0b100..Reserved.
+ *  0b101..Reserved.
+ *  0b110..Reserved.
+ */
 #define ENET_TCR_ADDSEL(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDSEL_SHIFT)) & ENET_TCR_ADDSEL_MASK)
 #define ENET_TCR_ADDINS_MASK                     (0x100U)
 #define ENET_TCR_ADDINS_SHIFT                    (8U)
+/*! ADDINS - Set MAC Address On Transmit
+ *  0b0..The source MAC address is not modified by the MAC.
+ *  0b1..The MAC overwrites the source MAC address with the programmed MAC address according to ADDSEL.
+ */
 #define ENET_TCR_ADDINS(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDINS_SHIFT)) & ENET_TCR_ADDINS_MASK)
 #define ENET_TCR_CRCFWD_MASK                     (0x200U)
 #define ENET_TCR_CRCFWD_SHIFT                    (9U)
+/*! CRCFWD - Forward Frame From Application With CRC
+ *  0b0..TxBD[TC] controls whether the frame has a CRC from the application.
+ *  0b1..The transmitter does not append any CRC to transmitted frames, as it is expecting a frame with CRC from the application.
+ */
 #define ENET_TCR_CRCFWD(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_TCR_CRCFWD_SHIFT)) & ENET_TCR_CRCFWD_MASK)
 /*! @} */
 
@@ -9822,9 +15878,17 @@ typedef struct {
 #define ENET_TXIC_ICFT(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICFT_SHIFT)) & ENET_TXIC_ICFT_MASK)
 #define ENET_TXIC_ICCS_MASK                      (0x40000000U)
 #define ENET_TXIC_ICCS_SHIFT                     (30U)
+/*! ICCS - Interrupt Coalescing Timer Clock Source Select
+ *  0b0..Use MII/GMII TX clocks.
+ *  0b1..Use ENET system clock.
+ */
 #define ENET_TXIC_ICCS(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICCS_SHIFT)) & ENET_TXIC_ICCS_MASK)
 #define ENET_TXIC_ICEN_MASK                      (0x80000000U)
 #define ENET_TXIC_ICEN_SHIFT                     (31U)
+/*! ICEN - Interrupt Coalescing Enable
+ *  0b0..Disable Interrupt coalescing.
+ *  0b1..Enable Interrupt coalescing.
+ */
 #define ENET_TXIC_ICEN(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICEN_SHIFT)) & ENET_TXIC_ICEN_MASK)
 /*! @} */
 
@@ -9838,9 +15902,17 @@ typedef struct {
 #define ENET_RXIC_ICFT(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICFT_SHIFT)) & ENET_RXIC_ICFT_MASK)
 #define ENET_RXIC_ICCS_MASK                      (0x40000000U)
 #define ENET_RXIC_ICCS_SHIFT                     (30U)
+/*! ICCS - Interrupt Coalescing Timer Clock Source Select
+ *  0b0..Use MII/GMII TX clocks.
+ *  0b1..Use ENET system clock.
+ */
 #define ENET_RXIC_ICCS(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICCS_SHIFT)) & ENET_RXIC_ICCS_MASK)
 #define ENET_RXIC_ICEN_MASK                      (0x80000000U)
 #define ENET_RXIC_ICEN_SHIFT                     (31U)
+/*! ICEN - Interrupt Coalescing Enable
+ *  0b0..Disable Interrupt coalescing.
+ *  0b1..Enable Interrupt coalescing.
+ */
 #define ENET_RXIC_ICEN(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICEN_SHIFT)) & ENET_RXIC_ICEN_MASK)
 /*! @} */
 
@@ -9876,9 +15948,20 @@ typedef struct {
 /*! @{ */
 #define ENET_TFWR_TFWR_MASK                      (0x3FU)
 #define ENET_TFWR_TFWR_SHIFT                     (0U)
+/*! TFWR - Transmit FIFO Write
+ *  0b000000..64 bytes written.
+ *  0b000001..64 bytes written.
+ *  0b000010..128 bytes written.
+ *  0b000011..192 bytes written.
+ *  0b011111..1984 bytes written.
+ */
 #define ENET_TFWR_TFWR(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_TFWR_SHIFT)) & ENET_TFWR_TFWR_MASK)
 #define ENET_TFWR_STRFWD_MASK                    (0x100U)
 #define ENET_TFWR_STRFWD_SHIFT                   (8U)
+/*! STRFWD - Store And Forward Enable
+ *  0b0..Reset. The transmission start threshold is programmed in TFWR[TFWR].
+ *  0b1..Enabled.
+ */
 #define ENET_TFWR_STRFWD(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_STRFWD_SHIFT)) & ENET_TFWR_STRFWD_MASK)
 /*! @} */
 
@@ -9973,12 +16056,29 @@ typedef struct {
 /*! @{ */
 #define ENET_TACC_SHIFT16_MASK                   (0x1U)
 #define ENET_TACC_SHIFT16_SHIFT                  (0U)
+/*! SHIFT16 - TX FIFO Shift-16
+ *  0b0..Disabled.
+ *  0b1..Indicates to the transmit data FIFO that the written frames contain two additional octets before the
+ *       frame data. This means the actual frame begins at bit 16 of the first word written into the FIFO. This
+ *       function allows putting the frame payload on a 32-bit boundary in memory, as the 14-byte Ethernet header is
+ *       extended to a 16-byte header.
+ */
 #define ENET_TACC_SHIFT16(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_TACC_SHIFT16_SHIFT)) & ENET_TACC_SHIFT16_MASK)
 #define ENET_TACC_IPCHK_MASK                     (0x8U)
 #define ENET_TACC_IPCHK_SHIFT                    (3U)
+/*! IPCHK
+ *  0b0..Checksum is not inserted.
+ *  0b1..If an IP frame is transmitted, the checksum is inserted automatically. The IP header checksum field must
+ *       be cleared. If a non-IP frame is transmitted the frame is not modified.
+ */
 #define ENET_TACC_IPCHK(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_TACC_IPCHK_SHIFT)) & ENET_TACC_IPCHK_MASK)
 #define ENET_TACC_PROCHK_MASK                    (0x10U)
 #define ENET_TACC_PROCHK_SHIFT                   (4U)
+/*! PROCHK
+ *  0b0..Checksum not inserted.
+ *  0b1..If an IP frame with a known protocol is transmitted, the checksum is inserted automatically into the
+ *       frame. The checksum field must be cleared. The other frames are not modified.
+ */
 #define ENET_TACC_PROCHK(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_TACC_PROCHK_SHIFT)) & ENET_TACC_PROCHK_MASK)
 /*! @} */
 
@@ -9986,18 +16086,42 @@ typedef struct {
 /*! @{ */
 #define ENET_RACC_PADREM_MASK                    (0x1U)
 #define ENET_RACC_PADREM_SHIFT                   (0U)
+/*! PADREM - Enable Padding Removal For Short IP Frames
+ *  0b0..Padding not removed.
+ *  0b1..Any bytes following the IP payload section of the frame are removed from the frame.
+ */
 #define ENET_RACC_PADREM(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PADREM_SHIFT)) & ENET_RACC_PADREM_MASK)
 #define ENET_RACC_IPDIS_MASK                     (0x2U)
 #define ENET_RACC_IPDIS_SHIFT                    (1U)
+/*! IPDIS - Enable Discard Of Frames With Wrong IPv4 Header Checksum
+ *  0b0..Frames with wrong IPv4 header checksum are not discarded.
+ *  0b1..If an IPv4 frame is received with a mismatching header checksum, the frame is discarded. IPv6 has no
+ *       header checksum and is not affected by this setting. Discarding is only available when the RX FIFO operates in
+ *       store and forward mode (RSFL cleared).
+ */
 #define ENET_RACC_IPDIS(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_RACC_IPDIS_SHIFT)) & ENET_RACC_IPDIS_MASK)
 #define ENET_RACC_PRODIS_MASK                    (0x4U)
 #define ENET_RACC_PRODIS_SHIFT                   (2U)
+/*! PRODIS - Enable Discard Of Frames With Wrong Protocol Checksum
+ *  0b0..Frames with wrong checksum are not discarded.
+ *  0b1..If a TCP/IP, UDP/IP, or ICMP/IP frame is received that has a wrong TCP, UDP, or ICMP checksum, the frame
+ *       is discarded. Discarding is only available when the RX FIFO operates in store and forward mode (RSFL
+ *       cleared).
+ */
 #define ENET_RACC_PRODIS(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PRODIS_SHIFT)) & ENET_RACC_PRODIS_MASK)
 #define ENET_RACC_LINEDIS_MASK                   (0x40U)
 #define ENET_RACC_LINEDIS_SHIFT                  (6U)
+/*! LINEDIS - Enable Discard Of Frames With MAC Layer Errors
+ *  0b0..Frames with errors are not discarded.
+ *  0b1..Any frame received with a CRC, length, or PHY error is automatically discarded and not forwarded to the user application interface.
+ */
 #define ENET_RACC_LINEDIS(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_RACC_LINEDIS_SHIFT)) & ENET_RACC_LINEDIS_MASK)
 #define ENET_RACC_SHIFT16_MASK                   (0x80U)
 #define ENET_RACC_SHIFT16_SHIFT                  (7U)
+/*! SHIFT16 - RX FIFO Shift-16
+ *  0b0..Disabled.
+ *  0b1..Instructs the MAC to write two additional bytes in front of each frame received into the RX FIFO.
+ */
 #define ENET_RACC_SHIFT16(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_RACC_SHIFT16_SHIFT)) & ENET_RACC_SHIFT16_MASK)
 /*! @} */
 
@@ -10362,27 +16486,60 @@ typedef struct {
 /*! @{ */
 #define ENET_ATCR_EN_MASK                        (0x1U)
 #define ENET_ATCR_EN_SHIFT                       (0U)
+/*! EN - Enable Timer
+ *  0b0..The timer stops at the current value.
+ *  0b1..The timer starts incrementing.
+ */
 #define ENET_ATCR_EN(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_EN_SHIFT)) & ENET_ATCR_EN_MASK)
 #define ENET_ATCR_OFFEN_MASK                     (0x4U)
 #define ENET_ATCR_OFFEN_SHIFT                    (2U)
+/*! OFFEN - Enable One-Shot Offset Event
+ *  0b0..Disable.
+ *  0b1..The timer can be reset to zero when the given offset time is reached (offset event). The field is cleared
+ *       when the offset event is reached, so no further event occurs until the field is set again. The timer
+ *       offset value must be set before setting this field.
+ */
 #define ENET_ATCR_OFFEN(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFEN_SHIFT)) & ENET_ATCR_OFFEN_MASK)
 #define ENET_ATCR_OFFRST_MASK                    (0x8U)
 #define ENET_ATCR_OFFRST_SHIFT                   (3U)
+/*! OFFRST - Reset Timer On Offset Event
+ *  0b0..The timer is not affected and no action occurs, besides clearing OFFEN, when the offset is reached.
+ *  0b1..If OFFEN is set, the timer resets to zero when the offset setting is reached. The offset event does not cause a timer interrupt.
+ */
 #define ENET_ATCR_OFFRST(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFRST_SHIFT)) & ENET_ATCR_OFFRST_MASK)
 #define ENET_ATCR_PEREN_MASK                     (0x10U)
 #define ENET_ATCR_PEREN_SHIFT                    (4U)
+/*! PEREN - Enable Periodical Event
+ *  0b0..Disable.
+ *  0b1..A period event interrupt can be generated (EIR[TS_TIMER]) and the event signal output is asserted when
+ *       the timer wraps around according to the periodic setting ATPER. The timer period value must be set before
+ *       setting this bit. Not all devices contain the event signal output. See the chip configuration details.
+ */
 #define ENET_ATCR_PEREN(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PEREN_SHIFT)) & ENET_ATCR_PEREN_MASK)
 #define ENET_ATCR_PINPER_MASK                    (0x80U)
 #define ENET_ATCR_PINPER_SHIFT                   (7U)
+/*! PINPER
+ *  0b0..Disable.
+ *  0b1..Enable.
+ */
 #define ENET_ATCR_PINPER(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PINPER_SHIFT)) & ENET_ATCR_PINPER_MASK)
 #define ENET_ATCR_RESTART_MASK                   (0x200U)
 #define ENET_ATCR_RESTART_SHIFT                  (9U)
 #define ENET_ATCR_RESTART(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_RESTART_SHIFT)) & ENET_ATCR_RESTART_MASK)
 #define ENET_ATCR_CAPTURE_MASK                   (0x800U)
 #define ENET_ATCR_CAPTURE_SHIFT                  (11U)
+/*! CAPTURE - Capture Timer Value
+ *  0b0..No effect.
+ *  0b1..The current time is captured and can be read from the ATVR register.
+ */
 #define ENET_ATCR_CAPTURE(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_CAPTURE_SHIFT)) & ENET_ATCR_CAPTURE_MASK)
 #define ENET_ATCR_SLAVE_MASK                     (0x2000U)
 #define ENET_ATCR_SLAVE_SHIFT                    (13U)
+/*! SLAVE - Enable Timer Slave Mode
+ *  0b0..The timer is active and all configuration fields in this register are relevant.
+ *  0b1..The internal timer is disabled and the externally provided timer value is used. All other fields, except
+ *       CAPTURE, in this register have no effect. CAPTURE can still be used to capture the current timer value.
+ */
 #define ENET_ATCR_SLAVE(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_SLAVE_SHIFT)) & ENET_ATCR_SLAVE_MASK)
 /*! @} */
 
@@ -10435,15 +16592,31 @@ typedef struct {
 /*! @{ */
 #define ENET_TGSR_TF0_MASK                       (0x1U)
 #define ENET_TGSR_TF0_SHIFT                      (0U)
+/*! TF0 - Copy Of Timer Flag For Channel 0
+ *  0b0..Timer Flag for Channel 0 is clear
+ *  0b1..Timer Flag for Channel 0 is set
+ */
 #define ENET_TGSR_TF0(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF0_SHIFT)) & ENET_TGSR_TF0_MASK)
 #define ENET_TGSR_TF1_MASK                       (0x2U)
 #define ENET_TGSR_TF1_SHIFT                      (1U)
+/*! TF1 - Copy Of Timer Flag For Channel 1
+ *  0b0..Timer Flag for Channel 1 is clear
+ *  0b1..Timer Flag for Channel 1 is set
+ */
 #define ENET_TGSR_TF1(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF1_SHIFT)) & ENET_TGSR_TF1_MASK)
 #define ENET_TGSR_TF2_MASK                       (0x4U)
 #define ENET_TGSR_TF2_SHIFT                      (2U)
+/*! TF2 - Copy Of Timer Flag For Channel 2
+ *  0b0..Timer Flag for Channel 2 is clear
+ *  0b1..Timer Flag for Channel 2 is set
+ */
 #define ENET_TGSR_TF2(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF2_SHIFT)) & ENET_TGSR_TF2_MASK)
 #define ENET_TGSR_TF3_MASK                       (0x8U)
 #define ENET_TGSR_TF3_SHIFT                      (3U)
+/*! TF3 - Copy Of Timer Flag For Channel 3
+ *  0b0..Timer Flag for Channel 3 is clear
+ *  0b1..Timer Flag for Channel 3 is set
+ */
 #define ENET_TGSR_TF3(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF3_SHIFT)) & ENET_TGSR_TF3_MASK)
 /*! @} */
 
@@ -10451,18 +16624,53 @@ typedef struct {
 /*! @{ */
 #define ENET_TCSR_TDRE_MASK                      (0x1U)
 #define ENET_TCSR_TDRE_SHIFT                     (0U)
+/*! TDRE - Timer DMA Request Enable
+ *  0b0..DMA request is disabled
+ *  0b1..DMA request is enabled
+ */
 #define ENET_TCSR_TDRE(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TDRE_SHIFT)) & ENET_TCSR_TDRE_MASK)
 #define ENET_TCSR_TMODE_MASK                     (0x3CU)
 #define ENET_TCSR_TMODE_SHIFT                    (2U)
+/*! TMODE - Timer Mode
+ *  0b0000..Timer Channel is disabled.
+ *  0b0001..Timer Channel is configured for Input Capture on rising edge.
+ *  0b0010..Timer Channel is configured for Input Capture on falling edge.
+ *  0b0011..Timer Channel is configured for Input Capture on both edges.
+ *  0b0100..Timer Channel is configured for Output Compare - software only.
+ *  0b0101..Timer Channel is configured for Output Compare - toggle output on compare.
+ *  0b0110..Timer Channel is configured for Output Compare - clear output on compare.
+ *  0b0111..Timer Channel is configured for Output Compare - set output on compare.
+ *  0b1000..Reserved
+ *  0b1010..Timer Channel is configured for Output Compare - clear output on compare, set output on overflow.
+ *  0b10x1..Timer Channel is configured for Output Compare - set output on compare, clear output on overflow.
+ *  0b110x..Reserved
+ *  0b1110..Timer Channel is configured for Output Compare - pulse output low on compare for 1 to 32 1588-clock cycles as specified by TPWC.
+ *  0b1111..Timer Channel is configured for Output Compare - pulse output high on compare for 1 to 32 1588-clock cycles as specified by TPWC.
+ */
 #define ENET_TCSR_TMODE(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TMODE_SHIFT)) & ENET_TCSR_TMODE_MASK)
 #define ENET_TCSR_TIE_MASK                       (0x40U)
 #define ENET_TCSR_TIE_SHIFT                      (6U)
+/*! TIE - Timer Interrupt Enable
+ *  0b0..Interrupt is disabled
+ *  0b1..Interrupt is enabled
+ */
 #define ENET_TCSR_TIE(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TIE_SHIFT)) & ENET_TCSR_TIE_MASK)
 #define ENET_TCSR_TF_MASK                        (0x80U)
 #define ENET_TCSR_TF_SHIFT                       (7U)
+/*! TF - Timer Flag
+ *  0b0..Input Capture or Output Compare has not occurred.
+ *  0b1..Input Capture or Output Compare has occurred.
+ */
 #define ENET_TCSR_TF(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TF_SHIFT)) & ENET_TCSR_TF_MASK)
 #define ENET_TCSR_TPWC_MASK                      (0xF800U)
 #define ENET_TCSR_TPWC_SHIFT                     (11U)
+/*! TPWC - Timer PulseWidth Control
+ *  0b00000..Pulse width is one 1588-clock cycle.
+ *  0b00001..Pulse width is two 1588-clock cycles.
+ *  0b00010..Pulse width is three 1588-clock cycles.
+ *  0b00011..Pulse width is four 1588-clock cycles.
+ *  0b11111..Pulse width is 32 1588-clock cycles.
+ */
 #define ENET_TCSR_TPWC(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TPWC_SHIFT)) & ENET_TCSR_TPWC_MASK)
 /*! @} */
 
@@ -10675,6 +16883,10 @@ typedef struct {
 /*! @{ */
 #define FLEXIO_VERID_FEATURE_MASK                (0xFFFFU)
 #define FLEXIO_VERID_FEATURE_SHIFT               (0U)
+/*! FEATURE - Feature Specification Number
+ *  0b0000000000000000..Standard features implemented.
+ *  0b0000000000000001..Supports state, logic and parallel modes.
+ */
 #define FLEXIO_VERID_FEATURE(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_FEATURE_SHIFT)) & FLEXIO_VERID_FEATURE_MASK)
 #define FLEXIO_VERID_MINOR_MASK                  (0xFF0000U)
 #define FLEXIO_VERID_MINOR_SHIFT                 (16U)
@@ -10704,18 +16916,38 @@ typedef struct {
 /*! @{ */
 #define FLEXIO_CTRL_FLEXEN_MASK                  (0x1U)
 #define FLEXIO_CTRL_FLEXEN_SHIFT                 (0U)
+/*! FLEXEN - FlexIO Enable
+ *  0b0..FlexIO module is disabled.
+ *  0b1..FlexIO module is enabled.
+ */
 #define FLEXIO_CTRL_FLEXEN(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FLEXEN_SHIFT)) & FLEXIO_CTRL_FLEXEN_MASK)
 #define FLEXIO_CTRL_SWRST_MASK                   (0x2U)
 #define FLEXIO_CTRL_SWRST_SHIFT                  (1U)
+/*! SWRST - Software Reset
+ *  0b0..Software reset is disabled
+ *  0b1..Software reset is enabled, all FlexIO registers except the Control Register are reset.
+ */
 #define FLEXIO_CTRL_SWRST(x)                     (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_SWRST_SHIFT)) & FLEXIO_CTRL_SWRST_MASK)
 #define FLEXIO_CTRL_FASTACC_MASK                 (0x4U)
 #define FLEXIO_CTRL_FASTACC_SHIFT                (2U)
+/*! FASTACC - Fast Access
+ *  0b0..Configures for normal register accesses to FlexIO
+ *  0b1..Configures for fast register accesses to FlexIO
+ */
 #define FLEXIO_CTRL_FASTACC(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FASTACC_SHIFT)) & FLEXIO_CTRL_FASTACC_MASK)
 #define FLEXIO_CTRL_DBGE_MASK                    (0x40000000U)
 #define FLEXIO_CTRL_DBGE_SHIFT                   (30U)
+/*! DBGE - Debug Enable
+ *  0b0..FlexIO is disabled in debug modes.
+ *  0b1..FlexIO is enabled in debug modes
+ */
 #define FLEXIO_CTRL_DBGE(x)                      (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DBGE_SHIFT)) & FLEXIO_CTRL_DBGE_MASK)
 #define FLEXIO_CTRL_DOZEN_MASK                   (0x80000000U)
 #define FLEXIO_CTRL_DOZEN_SHIFT                  (31U)
+/*! DOZEN - Doze Enable
+ *  0b0..FlexIO enabled in Doze modes.
+ *  0b1..FlexIO disabled in Doze modes.
+ */
 #define FLEXIO_CTRL_DOZEN(x)                     (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DOZEN_SHIFT)) & FLEXIO_CTRL_DOZEN_MASK)
 /*! @} */
 
@@ -10786,18 +17018,42 @@ typedef struct {
 /*! @{ */
 #define FLEXIO_SHIFTCTL_SMOD_MASK                (0x7U)
 #define FLEXIO_SHIFTCTL_SMOD_SHIFT               (0U)
+/*! SMOD - Shifter Mode
+ *  0b000..Disabled.
+ *  0b001..Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer.
+ *  0b010..Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer.
+ *  0b011..Reserved.
+ *  0b100..Match Store mode. Shifter data is compared to SHIFTBUF content on expiration of the Timer.
+ *  0b101..Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents.
+ *  0b110..State mode. SHIFTBUF contents are used for storing programmable state attributes.
+ *  0b111..Logic mode. SHIFTBUF contents are used for implementing programmable logic look up table.
+ */
 #define FLEXIO_SHIFTCTL_SMOD(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_SMOD_SHIFT)) & FLEXIO_SHIFTCTL_SMOD_MASK)
 #define FLEXIO_SHIFTCTL_PINPOL_MASK              (0x80U)
 #define FLEXIO_SHIFTCTL_PINPOL_SHIFT             (7U)
+/*! PINPOL - Shifter Pin Polarity
+ *  0b0..Pin is active high
+ *  0b1..Pin is active low
+ */
 #define FLEXIO_SHIFTCTL_PINPOL(x)                (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINPOL_SHIFT)) & FLEXIO_SHIFTCTL_PINPOL_MASK)
 #define FLEXIO_SHIFTCTL_PINSEL_MASK              (0x1F00U)
 #define FLEXIO_SHIFTCTL_PINSEL_SHIFT             (8U)
 #define FLEXIO_SHIFTCTL_PINSEL(x)                (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINSEL_SHIFT)) & FLEXIO_SHIFTCTL_PINSEL_MASK)
 #define FLEXIO_SHIFTCTL_PINCFG_MASK              (0x30000U)
 #define FLEXIO_SHIFTCTL_PINCFG_SHIFT             (16U)
+/*! PINCFG - Shifter Pin Configuration
+ *  0b00..Shifter pin output disabled
+ *  0b01..Shifter pin open drain or bidirectional output enable
+ *  0b10..Shifter pin bidirectional output data
+ *  0b11..Shifter pin output
+ */
 #define FLEXIO_SHIFTCTL_PINCFG(x)                (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINCFG_SHIFT)) & FLEXIO_SHIFTCTL_PINCFG_MASK)
 #define FLEXIO_SHIFTCTL_TIMPOL_MASK              (0x800000U)
 #define FLEXIO_SHIFTCTL_TIMPOL_SHIFT             (23U)
+/*! TIMPOL - Timer Polarity
+ *  0b0..Shift on posedge of Shift clock
+ *  0b1..Shift on negedge of Shift clock
+ */
 #define FLEXIO_SHIFTCTL_TIMPOL(x)                (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMPOL_SHIFT)) & FLEXIO_SHIFTCTL_TIMPOL_MASK)
 #define FLEXIO_SHIFTCTL_TIMSEL_MASK              (0x3000000U)
 #define FLEXIO_SHIFTCTL_TIMSEL_SHIFT             (24U)
@@ -10811,12 +17067,28 @@ typedef struct {
 /*! @{ */
 #define FLEXIO_SHIFTCFG_SSTART_MASK              (0x3U)
 #define FLEXIO_SHIFTCFG_SSTART_SHIFT             (0U)
+/*! SSTART - Shifter Start bit
+ *  0b00..Start bit disabled for transmitter/receiver/match store, transmitter loads data on enable
+ *  0b01..Start bit disabled for transmitter/receiver/match store, transmitter loads data on first shift
+ *  0b10..Transmitter outputs start bit value 0 before loading data on first shift, receiver/match store sets error flag if start bit is not 0
+ *  0b11..Transmitter outputs start bit value 1 before loading data on first shift, receiver/match store sets error flag if start bit is not 1
+ */
 #define FLEXIO_SHIFTCFG_SSTART(x)                (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTART_SHIFT)) & FLEXIO_SHIFTCFG_SSTART_MASK)
 #define FLEXIO_SHIFTCFG_SSTOP_MASK               (0x30U)
 #define FLEXIO_SHIFTCFG_SSTOP_SHIFT              (4U)
+/*! SSTOP - Shifter Stop bit
+ *  0b00..Stop bit disabled for transmitter/receiver/match store
+ *  0b01..Reserved for transmitter/receiver/match store
+ *  0b10..Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0
+ *  0b11..Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1
+ */
 #define FLEXIO_SHIFTCFG_SSTOP(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTOP_SHIFT)) & FLEXIO_SHIFTCFG_SSTOP_MASK)
 #define FLEXIO_SHIFTCFG_INSRC_MASK               (0x100U)
 #define FLEXIO_SHIFTCFG_INSRC_SHIFT              (8U)
+/*! INSRC - Input Source
+ *  0b0..Pin
+ *  0b1..Shifter N+1 Output
+ */
 #define FLEXIO_SHIFTCFG_INSRC(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_INSRC_SHIFT)) & FLEXIO_SHIFTCFG_INSRC_MASK)
 #define FLEXIO_SHIFTCFG_PWIDTH_MASK              (0x1F0000U)
 #define FLEXIO_SHIFTCFG_PWIDTH_SHIFT             (16U)
@@ -10870,21 +17142,45 @@ typedef struct {
 /*! @{ */
 #define FLEXIO_TIMCTL_TIMOD_MASK                 (0x3U)
 #define FLEXIO_TIMCTL_TIMOD_SHIFT                (0U)
+/*! TIMOD - Timer Mode
+ *  0b00..Timer Disabled.
+ *  0b01..Dual 8-bit counters baud mode.
+ *  0b10..Dual 8-bit counters PWM high mode.
+ *  0b11..Single 16-bit counter mode.
+ */
 #define FLEXIO_TIMCTL_TIMOD(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TIMOD_SHIFT)) & FLEXIO_TIMCTL_TIMOD_MASK)
 #define FLEXIO_TIMCTL_PINPOL_MASK                (0x80U)
 #define FLEXIO_TIMCTL_PINPOL_SHIFT               (7U)
+/*! PINPOL - Timer Pin Polarity
+ *  0b0..Pin is active high
+ *  0b1..Pin is active low
+ */
 #define FLEXIO_TIMCTL_PINPOL(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINPOL_SHIFT)) & FLEXIO_TIMCTL_PINPOL_MASK)
 #define FLEXIO_TIMCTL_PINSEL_MASK                (0x1F00U)
 #define FLEXIO_TIMCTL_PINSEL_SHIFT               (8U)
 #define FLEXIO_TIMCTL_PINSEL(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINSEL_SHIFT)) & FLEXIO_TIMCTL_PINSEL_MASK)
 #define FLEXIO_TIMCTL_PINCFG_MASK                (0x30000U)
 #define FLEXIO_TIMCTL_PINCFG_SHIFT               (16U)
+/*! PINCFG - Timer Pin Configuration
+ *  0b00..Timer pin output disabled
+ *  0b01..Timer pin open drain or bidirectional output enable
+ *  0b10..Timer pin bidirectional output data
+ *  0b11..Timer pin output
+ */
 #define FLEXIO_TIMCTL_PINCFG(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINCFG_SHIFT)) & FLEXIO_TIMCTL_PINCFG_MASK)
 #define FLEXIO_TIMCTL_TRGSRC_MASK                (0x400000U)
 #define FLEXIO_TIMCTL_TRGSRC_SHIFT               (22U)
+/*! TRGSRC - Trigger Source
+ *  0b0..External trigger selected
+ *  0b1..Internal trigger selected
+ */
 #define FLEXIO_TIMCTL_TRGSRC(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSRC_SHIFT)) & FLEXIO_TIMCTL_TRGSRC_MASK)
 #define FLEXIO_TIMCTL_TRGPOL_MASK                (0x800000U)
 #define FLEXIO_TIMCTL_TRGPOL_SHIFT               (23U)
+/*! TRGPOL - Trigger Polarity
+ *  0b0..Trigger active high
+ *  0b1..Trigger active low
+ */
 #define FLEXIO_TIMCTL_TRGPOL(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGPOL_SHIFT)) & FLEXIO_TIMCTL_TRGPOL_MASK)
 #define FLEXIO_TIMCTL_TRGSEL_MASK                (0x3F000000U)
 #define FLEXIO_TIMCTL_TRGSEL_SHIFT               (24U)
@@ -10898,24 +17194,76 @@ typedef struct {
 /*! @{ */
 #define FLEXIO_TIMCFG_TSTART_MASK                (0x2U)
 #define FLEXIO_TIMCFG_TSTART_SHIFT               (1U)
+/*! TSTART - Timer Start Bit
+ *  0b0..Start bit disabled
+ *  0b1..Start bit enabled
+ */
 #define FLEXIO_TIMCFG_TSTART(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTART_SHIFT)) & FLEXIO_TIMCFG_TSTART_MASK)
 #define FLEXIO_TIMCFG_TSTOP_MASK                 (0x30U)
 #define FLEXIO_TIMCFG_TSTOP_SHIFT                (4U)
+/*! TSTOP - Timer Stop Bit
+ *  0b00..Stop bit disabled
+ *  0b01..Stop bit is enabled on timer compare
+ *  0b10..Stop bit is enabled on timer disable
+ *  0b11..Stop bit is enabled on timer compare and timer disable
+ */
 #define FLEXIO_TIMCFG_TSTOP(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTOP_SHIFT)) & FLEXIO_TIMCFG_TSTOP_MASK)
 #define FLEXIO_TIMCFG_TIMENA_MASK                (0x700U)
 #define FLEXIO_TIMCFG_TIMENA_SHIFT               (8U)
+/*! TIMENA - Timer Enable
+ *  0b000..Timer always enabled
+ *  0b001..Timer enabled on Timer N-1 enable
+ *  0b010..Timer enabled on Trigger high
+ *  0b011..Timer enabled on Trigger high and Pin high
+ *  0b100..Timer enabled on Pin rising edge
+ *  0b101..Timer enabled on Pin rising edge and Trigger high
+ *  0b110..Timer enabled on Trigger rising edge
+ *  0b111..Timer enabled on Trigger rising or falling edge
+ */
 #define FLEXIO_TIMCFG_TIMENA(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMENA_SHIFT)) & FLEXIO_TIMCFG_TIMENA_MASK)
 #define FLEXIO_TIMCFG_TIMDIS_MASK                (0x7000U)
 #define FLEXIO_TIMCFG_TIMDIS_SHIFT               (12U)
+/*! TIMDIS - Timer Disable
+ *  0b000..Timer never disabled
+ *  0b001..Timer disabled on Timer N-1 disable
+ *  0b010..Timer disabled on Timer compare (upper 8-bits match and decrement)
+ *  0b011..Timer disabled on Timer compare (upper 8-bits match and decrement) and Trigger Low
+ *  0b100..Timer disabled on Pin rising or falling edge
+ *  0b101..Timer disabled on Pin rising or falling edge provided Trigger is high
+ *  0b110..Timer disabled on Trigger falling edge
+ *  0b111..Reserved
+ */
 #define FLEXIO_TIMCFG_TIMDIS(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDIS_SHIFT)) & FLEXIO_TIMCFG_TIMDIS_MASK)
 #define FLEXIO_TIMCFG_TIMRST_MASK                (0x70000U)
 #define FLEXIO_TIMCFG_TIMRST_SHIFT               (16U)
+/*! TIMRST - Timer Reset
+ *  0b000..Timer never reset
+ *  0b001..Reserved
+ *  0b010..Timer reset on Timer Pin equal to Timer Output
+ *  0b011..Timer reset on Timer Trigger equal to Timer Output
+ *  0b100..Timer reset on Timer Pin rising edge
+ *  0b101..Reserved
+ *  0b110..Timer reset on Trigger rising edge
+ *  0b111..Timer reset on Trigger rising or falling edge
+ */
 #define FLEXIO_TIMCFG_TIMRST(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMRST_SHIFT)) & FLEXIO_TIMCFG_TIMRST_MASK)
 #define FLEXIO_TIMCFG_TIMDEC_MASK                (0x300000U)
 #define FLEXIO_TIMCFG_TIMDEC_SHIFT               (20U)
+/*! TIMDEC - Timer Decrement
+ *  0b00..Decrement counter on FlexIO clock, Shift clock equals Timer output.
+ *  0b01..Decrement counter on Trigger input (both edges), Shift clock equals Timer output.
+ *  0b10..Decrement counter on Pin input (both edges), Shift clock equals Pin input.
+ *  0b11..Decrement counter on Trigger input (both edges), Shift clock equals Trigger input.
+ */
 #define FLEXIO_TIMCFG_TIMDEC(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDEC_SHIFT)) & FLEXIO_TIMCFG_TIMDEC_MASK)
 #define FLEXIO_TIMCFG_TIMOUT_MASK                (0x3000000U)
 #define FLEXIO_TIMCFG_TIMOUT_SHIFT               (24U)
+/*! TIMOUT - Timer Output
+ *  0b00..Timer output is logic one when enabled and is not affected by timer reset
+ *  0b01..Timer output is logic zero when enabled and is not affected by timer reset
+ *  0b10..Timer output is logic one when enabled and on timer reset
+ *  0b11..Timer output is logic zero when enabled and on timer reset
+ */
 #define FLEXIO_TIMCFG_TIMOUT(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMOUT_SHIFT)) & FLEXIO_TIMCFG_TIMOUT_MASK)
 /*! @} */
 
@@ -11001,9 +17349,7 @@ typedef struct {
 /** FLEXRAM - Register Layout Typedef */
 typedef struct {
   __IO uint32_t TCM_CTRL;                          /**< TCM CRTL Register, offset: 0x0 */
-  __IO uint32_t OCRAM_MAGIC_ADDR;                  /**< OCRAM Magic Address Register, offset: 0x4 */
-  __IO uint32_t DTCM_MAGIC_ADDR;                   /**< DTCM Magic Address Register, offset: 0x8 */
-  __IO uint32_t ITCM_MAGIC_ADDR;                   /**< ITCM Magic Address Register, offset: 0xC */
+       uint8_t RESERVED_0[12];
   __IO uint32_t INT_STATUS;                        /**< Interrupt Status Register, offset: 0x10 */
   __IO uint32_t INT_STAT_EN;                       /**< Interrupt Status Enable Register, offset: 0x14 */
   __IO uint32_t INT_SIG_EN;                        /**< Interrupt Enable Register, offset: 0x18 */
@@ -11022,130 +17368,96 @@ typedef struct {
 /*! @{ */
 #define FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_MASK       (0x1U)
 #define FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_SHIFT      (0U)
+/*! TCM_WWAIT_EN - TCM Write Wait Mode Enable
+ *  0b0..TCM write fast mode: Write RAM accesses are expected to be finished in 1-cycle.
+ *  0b1..TCM write wait mode: Write RAM accesses are expected to be finished in 2-cycles.
+ */
 #define FLEXRAM_TCM_CTRL_TCM_WWAIT_EN(x)         (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_SHIFT)) & FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_MASK)
 #define FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_MASK       (0x2U)
 #define FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_SHIFT      (1U)
+/*! TCM_RWAIT_EN - TCM Read Wait Mode Enable
+ *  0b0..TCM read fast mode: Read RAM accesses are expected to be finished in 1-cycle.
+ *  0b1..TCM read wait mode: Read RAM accesses are expected to be finished in 2-cycles.
+ */
 #define FLEXRAM_TCM_CTRL_TCM_RWAIT_EN(x)         (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_SHIFT)) & FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_MASK)
 #define FLEXRAM_TCM_CTRL_FORCE_CLK_ON_MASK       (0x4U)
 #define FLEXRAM_TCM_CTRL_FORCE_CLK_ON_SHIFT      (2U)
 #define FLEXRAM_TCM_CTRL_FORCE_CLK_ON(x)         (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_FORCE_CLK_ON_SHIFT)) & FLEXRAM_TCM_CTRL_FORCE_CLK_ON_MASK)
-#define FLEXRAM_TCM_CTRL_Reserved_MASK           (0xFFFFFFF8U)
-#define FLEXRAM_TCM_CTRL_Reserved_SHIFT          (3U)
-#define FLEXRAM_TCM_CTRL_Reserved(x)             (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_Reserved_SHIFT)) & FLEXRAM_TCM_CTRL_Reserved_MASK)
-/*! @} */
-
-/*! @name OCRAM_MAGIC_ADDR - OCRAM Magic Address Register */
-/*! @{ */
-#define FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL_MASK (0x1U)
-#define FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL_SHIFT (0U)
-#define FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL_SHIFT)) & FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL_MASK)
-#define FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR_MASK (0x1FFFEU)
-#define FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR_SHIFT (1U)
-#define FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR_SHIFT)) & FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR_MASK)
-#define FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_MASK   (0xFFFE0000U)
-#define FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_SHIFT  (17U)
-#define FLEXRAM_OCRAM_MAGIC_ADDR_Reserved(x)     (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_SHIFT)) & FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_MASK)
-/*! @} */
-
-/*! @name DTCM_MAGIC_ADDR - DTCM Magic Address Register */
-/*! @{ */
-#define FLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL_MASK (0x1U)
-#define FLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL_SHIFT (0U)
-#define FLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL_SHIFT)) & FLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL_MASK)
-#define FLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR_MASK (0x1FFFEU)
-#define FLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR_SHIFT (1U)
-#define FLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR_SHIFT)) & FLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR_MASK)
-#define FLEXRAM_DTCM_MAGIC_ADDR_Reserved_MASK    (0xFFFE0000U)
-#define FLEXRAM_DTCM_MAGIC_ADDR_Reserved_SHIFT   (17U)
-#define FLEXRAM_DTCM_MAGIC_ADDR_Reserved(x)      (((uint32_t)(((uint32_t)(x)) << FLEXRAM_DTCM_MAGIC_ADDR_Reserved_SHIFT)) & FLEXRAM_DTCM_MAGIC_ADDR_Reserved_MASK)
-/*! @} */
-
-/*! @name ITCM_MAGIC_ADDR - ITCM Magic Address Register */
-/*! @{ */
-#define FLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL_MASK (0x1U)
-#define FLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL_SHIFT (0U)
-#define FLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL_SHIFT)) & FLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL_MASK)
-#define FLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR_MASK (0x1FFFEU)
-#define FLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR_SHIFT (1U)
-#define FLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR_SHIFT)) & FLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR_MASK)
-#define FLEXRAM_ITCM_MAGIC_ADDR_Reserved_MASK    (0xFFFE0000U)
-#define FLEXRAM_ITCM_MAGIC_ADDR_Reserved_SHIFT   (17U)
-#define FLEXRAM_ITCM_MAGIC_ADDR_Reserved(x)      (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_MAGIC_ADDR_Reserved_SHIFT)) & FLEXRAM_ITCM_MAGIC_ADDR_Reserved_MASK)
 /*! @} */
 
 /*! @name INT_STATUS - Interrupt Status Register */
 /*! @{ */
-#define FLEXRAM_INT_STATUS_ITCM_MAM_STATUS_MASK  (0x1U)
-#define FLEXRAM_INT_STATUS_ITCM_MAM_STATUS_SHIFT (0U)
-#define FLEXRAM_INT_STATUS_ITCM_MAM_STATUS(x)    (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_ITCM_MAM_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_ITCM_MAM_STATUS_MASK)
-#define FLEXRAM_INT_STATUS_DTCM_MAM_STATUS_MASK  (0x2U)
-#define FLEXRAM_INT_STATUS_DTCM_MAM_STATUS_SHIFT (1U)
-#define FLEXRAM_INT_STATUS_DTCM_MAM_STATUS(x)    (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_DTCM_MAM_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_DTCM_MAM_STATUS_MASK)
-#define FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS_MASK (0x4U)
-#define FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS_SHIFT (2U)
-#define FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS(x)   (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS_MASK)
 #define FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK  (0x8U)
 #define FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_SHIFT (3U)
+/*! ITCM_ERR_STATUS - ITCM Access Error Status
+ *  0b0..ITCM access error does not happen
+ *  0b1..ITCM access error happens.
+ */
 #define FLEXRAM_INT_STATUS_ITCM_ERR_STATUS(x)    (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK)
 #define FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK  (0x10U)
 #define FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_SHIFT (4U)
+/*! DTCM_ERR_STATUS - DTCM Access Error Status
+ *  0b0..DTCM access error does not happen
+ *  0b1..DTCM access error happens.
+ */
 #define FLEXRAM_INT_STATUS_DTCM_ERR_STATUS(x)    (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK)
 #define FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK (0x20U)
 #define FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_SHIFT (5U)
+/*! OCRAM_ERR_STATUS - OCRAM Access Error Status
+ *  0b0..OCRAM access error does not happen
+ *  0b1..OCRAM access error happens.
+ */
 #define FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS(x)   (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK)
-#define FLEXRAM_INT_STATUS_Reserved_MASK         (0xFFFFFFC0U)
-#define FLEXRAM_INT_STATUS_Reserved_SHIFT        (6U)
-#define FLEXRAM_INT_STATUS_Reserved(x)           (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_Reserved_SHIFT)) & FLEXRAM_INT_STATUS_Reserved_MASK)
 /*! @} */
 
 /*! @name INT_STAT_EN - Interrupt Status Enable Register */
 /*! @{ */
-#define FLEXRAM_INT_STAT_EN_ITCM_MAM_STAT_EN_MASK (0x1U)
-#define FLEXRAM_INT_STAT_EN_ITCM_MAM_STAT_EN_SHIFT (0U)
-#define FLEXRAM_INT_STAT_EN_ITCM_MAM_STAT_EN(x)  (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_ITCM_MAM_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_ITCM_MAM_STAT_EN_MASK)
-#define FLEXRAM_INT_STAT_EN_DTCM_MAM_STAT_EN_MASK (0x2U)
-#define FLEXRAM_INT_STAT_EN_DTCM_MAM_STAT_EN_SHIFT (1U)
-#define FLEXRAM_INT_STAT_EN_DTCM_MAM_STAT_EN(x)  (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_DTCM_MAM_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_DTCM_MAM_STAT_EN_MASK)
-#define FLEXRAM_INT_STAT_EN_OCRAM_MAM_STAT_EN_MASK (0x4U)
-#define FLEXRAM_INT_STAT_EN_OCRAM_MAM_STAT_EN_SHIFT (2U)
-#define FLEXRAM_INT_STAT_EN_OCRAM_MAM_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_OCRAM_MAM_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_OCRAM_MAM_STAT_EN_MASK)
 #define FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_MASK (0x8U)
 #define FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_SHIFT (3U)
+/*! ITCM_ERR_STAT_EN - ITCM Access Error Status Enable
+ *  0b0..Masked
+ *  0b1..Enabled
+ */
 #define FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN(x)  (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_MASK)
 #define FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_MASK (0x10U)
 #define FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_SHIFT (4U)
+/*! DTCM_ERR_STAT_EN - DTCM Access Error Status Enable
+ *  0b0..Masked
+ *  0b1..Enabled
+ */
 #define FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN(x)  (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_MASK)
 #define FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_MASK (0x20U)
 #define FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_SHIFT (5U)
+/*! OCRAM_ERR_STAT_EN - OCRAM Access Error Status Enable
+ *  0b0..Masked
+ *  0b1..Enabled
+ */
 #define FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_MASK)
-#define FLEXRAM_INT_STAT_EN_Reserved_MASK        (0xFFFFFFC0U)
-#define FLEXRAM_INT_STAT_EN_Reserved_SHIFT       (6U)
-#define FLEXRAM_INT_STAT_EN_Reserved(x)          (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_Reserved_SHIFT)) & FLEXRAM_INT_STAT_EN_Reserved_MASK)
 /*! @} */
 
 /*! @name INT_SIG_EN - Interrupt Enable Register */
 /*! @{ */
-#define FLEXRAM_INT_SIG_EN_ITCM_MAM_SIG_EN_MASK  (0x1U)
-#define FLEXRAM_INT_SIG_EN_ITCM_MAM_SIG_EN_SHIFT (0U)
-#define FLEXRAM_INT_SIG_EN_ITCM_MAM_SIG_EN(x)    (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_ITCM_MAM_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_ITCM_MAM_SIG_EN_MASK)
-#define FLEXRAM_INT_SIG_EN_DTCM_MAM_SIG_EN_MASK  (0x2U)
-#define FLEXRAM_INT_SIG_EN_DTCM_MAM_SIG_EN_SHIFT (1U)
-#define FLEXRAM_INT_SIG_EN_DTCM_MAM_SIG_EN(x)    (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_DTCM_MAM_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_DTCM_MAM_SIG_EN_MASK)
-#define FLEXRAM_INT_SIG_EN_OCRAM_MAM_SIG_EN_MASK (0x4U)
-#define FLEXRAM_INT_SIG_EN_OCRAM_MAM_SIG_EN_SHIFT (2U)
-#define FLEXRAM_INT_SIG_EN_OCRAM_MAM_SIG_EN(x)   (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_OCRAM_MAM_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_OCRAM_MAM_SIG_EN_MASK)
 #define FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_MASK  (0x8U)
 #define FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_SHIFT (3U)
+/*! ITCM_ERR_SIG_EN - ITCM Access Error Interrupt Enable
+ *  0b0..Masked
+ *  0b1..Enabled
+ */
 #define FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN(x)    (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_MASK)
 #define FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_MASK  (0x10U)
 #define FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_SHIFT (4U)
+/*! DTCM_ERR_SIG_EN - DTCM Access Error Interrupt Enable
+ *  0b0..Masked
+ *  0b1..Enabled
+ */
 #define FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN(x)    (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_MASK)
 #define FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_MASK (0x20U)
 #define FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_SHIFT (5U)
+/*! OCRAM_ERR_SIG_EN - OCRAM Access Error Interrupt Enable
+ *  0b0..Masked
+ *  0b1..Enabled
+ */
 #define FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN(x)   (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_MASK)
-#define FLEXRAM_INT_SIG_EN_Reserved_MASK         (0xFFFFFFC0U)
-#define FLEXRAM_INT_SIG_EN_Reserved_SHIFT        (6U)
-#define FLEXRAM_INT_SIG_EN_Reserved(x)           (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_Reserved_SHIFT)) & FLEXRAM_INT_SIG_EN_Reserved_MASK)
 /*! @} */
 
 
@@ -11238,24 +17550,56 @@ typedef struct {
 #define FLEXSPI_MCR0_MDIS(x)                     (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_MDIS_SHIFT)) & FLEXSPI_MCR0_MDIS_MASK)
 #define FLEXSPI_MCR0_RXCLKSRC_MASK               (0x30U)
 #define FLEXSPI_MCR0_RXCLKSRC_SHIFT              (4U)
+/*! RXCLKSRC - Sample Clock source selection for Flash Reading
+ *  0b00..Dummy Read strobe generated by FlexSPI Controller and loopback internally.
+ *  0b01..Dummy Read strobe generated by FlexSPI Controller and loopback from DQS pad.
+ *  0b10..Reserved
+ *  0b11..Flash provided Read strobe and input from DQS pad
+ */
 #define FLEXSPI_MCR0_RXCLKSRC(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_RXCLKSRC_SHIFT)) & FLEXSPI_MCR0_RXCLKSRC_MASK)
 #define FLEXSPI_MCR0_ARDFEN_MASK                 (0x40U)
 #define FLEXSPI_MCR0_ARDFEN_SHIFT                (6U)
+/*! ARDFEN - Enable AHB bus Read Access to IP RX FIFO.
+ *  0b0..IP RX FIFO should be read by IP Bus. AHB Bus read access to IP RX FIFO memory space will get bus error response.
+ *  0b1..IP RX FIFO should be read by AHB Bus. IP Bus read access to IP RX FIFO memory space will always return data zero but no bus error response.
+ */
 #define FLEXSPI_MCR0_ARDFEN(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ARDFEN_SHIFT)) & FLEXSPI_MCR0_ARDFEN_MASK)
 #define FLEXSPI_MCR0_ATDFEN_MASK                 (0x80U)
 #define FLEXSPI_MCR0_ATDFEN_SHIFT                (7U)
+/*! ATDFEN - Enable AHB bus Write Access to IP TX FIFO.
+ *  0b0..IP TX FIFO should be written by IP Bus. AHB Bus write access to IP TX FIFO memory space will get bus error response.
+ *  0b1..IP TX FIFO should be written by AHB Bus. IP Bus write access to IP TX FIFO memory space will be ignored but no bus error response.
+ */
 #define FLEXSPI_MCR0_ATDFEN(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ATDFEN_SHIFT)) & FLEXSPI_MCR0_ATDFEN_MASK)
 #define FLEXSPI_MCR0_HSEN_MASK                   (0x800U)
 #define FLEXSPI_MCR0_HSEN_SHIFT                  (11U)
+/*! HSEN - Half Speed Serial Flash access Enable.
+ *  0b0..Disable divide by 2 of serial flash clock for half speed commands.
+ *  0b1..Enable divide by 2 of serial flash clock for half speed commands.
+ */
 #define FLEXSPI_MCR0_HSEN(x)                     (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_HSEN_SHIFT)) & FLEXSPI_MCR0_HSEN_MASK)
 #define FLEXSPI_MCR0_DOZEEN_MASK                 (0x1000U)
 #define FLEXSPI_MCR0_DOZEEN_SHIFT                (12U)
+/*! DOZEEN - Doze mode enable bit
+ *  0b0..Doze mode support disabled. AHB clock and serial clock will not be gated off when there is doze mode request from system.
+ *  0b1..Doze mode support enabled. AHB clock and serial clock will be gated off when there is doze mode request from system.
+ */
 #define FLEXSPI_MCR0_DOZEEN(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_DOZEEN_SHIFT)) & FLEXSPI_MCR0_DOZEEN_MASK)
 #define FLEXSPI_MCR0_COMBINATIONEN_MASK          (0x2000U)
 #define FLEXSPI_MCR0_COMBINATIONEN_SHIFT         (13U)
+/*! COMBINATIONEN - This bit is to support Flash Octal mode access by combining Port A and B Data pins (SIOA[3:0] and SIOB[3:0]).
+ *  0b0..Disable.
+ *  0b1..Enable.
+ */
 #define FLEXSPI_MCR0_COMBINATIONEN(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_COMBINATIONEN_SHIFT)) & FLEXSPI_MCR0_COMBINATIONEN_MASK)
 #define FLEXSPI_MCR0_SCKFREERUNEN_MASK           (0x4000U)
 #define FLEXSPI_MCR0_SCKFREERUNEN_SHIFT          (14U)
+/*! SCKFREERUNEN - This bit is used to force SCK output free-running. For FPGA applications,
+ *    external device may use SCK clock as reference clock to its internal PLL. If SCK free-running is
+ *    enabled, data sampling with loopback clock from SCK pad is not supported (MCR0[RXCLKSRC]=2).
+ *  0b0..Disable.
+ *  0b1..Enable.
+ */
 #define FLEXSPI_MCR0_SCKFREERUNEN(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SCKFREERUNEN_SHIFT)) & FLEXSPI_MCR0_SCKFREERUNEN_MASK)
 #define FLEXSPI_MCR0_IPGRANTWAIT_MASK            (0xFF0000U)
 #define FLEXSPI_MCR0_IPGRANTWAIT_SHIFT           (16U)
@@ -11279,15 +17623,35 @@ typedef struct {
 /*! @{ */
 #define FLEXSPI_MCR2_CLRAHBBUFOPT_MASK           (0x800U)
 #define FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT          (11U)
+/*! CLRAHBBUFOPT - This bit determines whether AHB RX Buffer and AHB TX Buffer will be cleaned
+ *    automaticaly when FlexSPI returns STOP mode ACK. Software should set this bit if AHB RX Buffer or
+ *    AHB TX Buffer will be powered off in STOP mode. Otherwise AHB read access after exiting STOP
+ *    mode may hit AHB RX Buffer or AHB TX Buffer but their data entries are invalid.
+ *  0b0..AHB RX/TX Buffer will not be cleaned automatically when FlexSPI return Stop mode ACK.
+ *  0b1..AHB RX/TX Buffer will be cleaned automatically when FlexSPI return Stop mode ACK.
+ */
 #define FLEXSPI_MCR2_CLRAHBBUFOPT(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT)) & FLEXSPI_MCR2_CLRAHBBUFOPT_MASK)
 #define FLEXSPI_MCR2_CLRLEARNPHASE_MASK          (0x4000U)
 #define FLEXSPI_MCR2_CLRLEARNPHASE_SHIFT         (14U)
 #define FLEXSPI_MCR2_CLRLEARNPHASE(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLRLEARNPHASE_SHIFT)) & FLEXSPI_MCR2_CLRLEARNPHASE_MASK)
 #define FLEXSPI_MCR2_SAMEDEVICEEN_MASK           (0x8000U)
 #define FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT          (15U)
+/*! SAMEDEVICEEN - All external devices are same devices (both in types and size) for A1/A2/B1/B2.
+ *  0b0..In Individual mode, FLSHA1CRx/FLSHA2CRx/FLSHB1CRx/FLSHB2CRx register setting will be applied to Flash
+ *       A1/A2/B1/B2 seperately. In Parallel mode, FLSHA1CRx register setting will be applied to Flash A1 and B1,
+ *       FLSHA2CRx register setting will be applied to Flash A2 and B2. FLSHB1CRx/FLSHB2CRx register settings will be
+ *       ignored.
+ *  0b1..FLSHA1CR0/FLSHA1CR1/FLSHA1CR2 register settings will be applied to Flash A1/A2/B1/B2. FLSHA2CRx/FLSHB1CRx/FLSHB2CRx will be ignored.
+ */
 #define FLEXSPI_MCR2_SAMEDEVICEEN(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT)) & FLEXSPI_MCR2_SAMEDEVICEEN_MASK)
 #define FLEXSPI_MCR2_SCKBDIFFOPT_MASK            (0x80000U)
 #define FLEXSPI_MCR2_SCKBDIFFOPT_SHIFT           (19U)
+/*! SCKBDIFFOPT - SCKB pad can be used as SCKA differential clock output (inverted clock to SCKA).
+ *    In this case, port B flash access is not available. After change the value of this feild,
+ *    MCR0[SWRESET] should be set.
+ *  0b1..SCKB pad is used as port A SCK inverted clock output (Differential clock to SCKA). Port B flash access is not available.
+ *  0b0..SCKB pad is used as port B SCK clock output. Port B flash access is available.
+ */
 #define FLEXSPI_MCR2_SCKBDIFFOPT(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SCKBDIFFOPT_SHIFT)) & FLEXSPI_MCR2_SCKBDIFFOPT_MASK)
 #define FLEXSPI_MCR2_RESUMEWAIT_MASK             (0xFF000000U)
 #define FLEXSPI_MCR2_RESUMEWAIT_SHIFT            (24U)
@@ -11298,18 +17662,38 @@ typedef struct {
 /*! @{ */
 #define FLEXSPI_AHBCR_APAREN_MASK                (0x1U)
 #define FLEXSPI_AHBCR_APAREN_SHIFT               (0U)
+/*! APAREN - Parallel mode enabled for AHB triggered Command (both read and write) .
+ *  0b0..Flash will be accessed in Individual mode.
+ *  0b1..Flash will be accessed in Parallel mode.
+ */
 #define FLEXSPI_AHBCR_APAREN(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_APAREN_SHIFT)) & FLEXSPI_AHBCR_APAREN_MASK)
 #define FLEXSPI_AHBCR_CACHABLEEN_MASK            (0x8U)
 #define FLEXSPI_AHBCR_CACHABLEEN_SHIFT           (3U)
+/*! CACHABLEEN - Enable AHB bus cachable read access support.
+ *  0b0..Disabled. When there is AHB bus cachable read access, FlexSPI will not check whether it hit AHB TX Buffer.
+ *  0b1..Enabled. When there is AHB bus cachable read access, FlexSPI will check whether it hit AHB TX Buffer first.
+ */
 #define FLEXSPI_AHBCR_CACHABLEEN(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_CACHABLEEN_SHIFT)) & FLEXSPI_AHBCR_CACHABLEEN_MASK)
 #define FLEXSPI_AHBCR_BUFFERABLEEN_MASK          (0x10U)
 #define FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT         (4U)
+/*! BUFFERABLEEN - Enable AHB bus bufferable write access support. This field affects the last beat
+ *    of AHB write access, refer for more details about AHB bufferable write.
+ *  0b0..Disabled. For all AHB write access (no matter bufferable or non-bufferable ), FlexSPI will return AHB Bus
+ *       ready after all data is transmitted to External device and AHB command finished.
+ *  0b1..Enabled. For AHB bufferable write access, FlexSPI will return AHB Bus ready when the AHB command is
+ *       granted by arbitrator and will not wait for AHB command finished.
+ */
 #define FLEXSPI_AHBCR_BUFFERABLEEN(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT)) & FLEXSPI_AHBCR_BUFFERABLEEN_MASK)
 #define FLEXSPI_AHBCR_PREFETCHEN_MASK            (0x20U)
 #define FLEXSPI_AHBCR_PREFETCHEN_SHIFT           (5U)
 #define FLEXSPI_AHBCR_PREFETCHEN(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_PREFETCHEN_SHIFT)) & FLEXSPI_AHBCR_PREFETCHEN_MASK)
 #define FLEXSPI_AHBCR_READADDROPT_MASK           (0x40U)
 #define FLEXSPI_AHBCR_READADDROPT_SHIFT          (6U)
+/*! READADDROPT - AHB Read Address option bit. This option bit is intend to remove AHB burst start address alignment limitation.
+ *  0b0..There is AHB read burst start address alignment limitation when flash is accessed in parallel mode or flash is wordaddressable.
+ *  0b1..There is no AHB read burst start address alignment limitation. FlexSPI will fetch more datas than AHB
+ *       burst required to meet the alignment requirement.
+ */
 #define FLEXSPI_AHBCR_READADDROPT(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_READADDROPT_SHIFT)) & FLEXSPI_AHBCR_READADDROPT_MASK)
 /*! @} */
 
@@ -11449,6 +17833,10 @@ typedef struct {
 #define FLEXSPI_FLSHCR1_CAS(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CAS_SHIFT)) & FLEXSPI_FLSHCR1_CAS_MASK)
 #define FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK      (0x8000U)
 #define FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT     (15U)
+/*! CSINTERVALUNIT - CS interval unit
+ *  0b0..The CS interval unit is 1 serial clock cycle
+ *  0b1..The CS interval unit is 256 serial clock cycle
+ */
 #define FLEXSPI_FLSHCR1_CSINTERVALUNIT(x)        (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK)
 #define FLEXSPI_FLSHCR1_CSINTERVAL_MASK          (0xFFFF0000U)
 #define FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT         (16U)
@@ -11477,6 +17865,16 @@ typedef struct {
 #define FLEXSPI_FLSHCR2_AWRWAIT(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAIT_MASK)
 #define FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK         (0x70000000U)
 #define FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT        (28U)
+/*! AWRWAITUNIT - AWRWAIT unit
+ *  0b000..The AWRWAIT unit is 2 ahb clock cycle
+ *  0b001..The AWRWAIT unit is 8 ahb clock cycle
+ *  0b010..The AWRWAIT unit is 32 ahb clock cycle
+ *  0b011..The AWRWAIT unit is 128 ahb clock cycle
+ *  0b100..The AWRWAIT unit is 512 ahb clock cycle
+ *  0b101..The AWRWAIT unit is 2048 ahb clock cycle
+ *  0b110..The AWRWAIT unit is 8192 ahb clock cycle
+ *  0b111..The AWRWAIT unit is 32768 ahb clock cycle
+ */
 #define FLEXSPI_FLSHCR2_AWRWAITUNIT(x)           (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK)
 #define FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK         (0x80000000U)
 #define FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT        (31U)
@@ -11490,12 +17888,28 @@ typedef struct {
 /*! @{ */
 #define FLEXSPI_FLSHCR4_WMOPT1_MASK              (0x1U)
 #define FLEXSPI_FLSHCR4_WMOPT1_SHIFT             (0U)
+/*! WMOPT1 - Write mask option bit 1. This option bit could be used to remove AHB write burst start address alignment limitation.
+ *  0b0..DQS pin will be used as Write Mask when writing to external device. There is no limitation on AHB write
+ *       burst start address alignment when flash is accessed in individual mode.
+ *  0b1..DQS pin will not be used as Write Mask when writing to external device. There is limitation on AHB write
+ *       burst start address alignment when flash is accessed in individual mode.
+ */
 #define FLEXSPI_FLSHCR4_WMOPT1(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMOPT1_SHIFT)) & FLEXSPI_FLSHCR4_WMOPT1_MASK)
 #define FLEXSPI_FLSHCR4_WMENA_MASK               (0x4U)
 #define FLEXSPI_FLSHCR4_WMENA_SHIFT              (2U)
+/*! WMENA - Write mask enable bit for flash device on port A. When write mask function is needed for
+ *    memory device on port A, this bit must be set.
+ *  0b0..Write mask is disabled, DQS(RWDS) pin will be un-driven when writing to external device.
+ *  0b1..Write mask is enabled, DQS(RWDS) pin will be driven by FlexSPI as write mask output when writing to external device.
+ */
 #define FLEXSPI_FLSHCR4_WMENA(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENA_SHIFT)) & FLEXSPI_FLSHCR4_WMENA_MASK)
 #define FLEXSPI_FLSHCR4_WMENB_MASK               (0x8U)
 #define FLEXSPI_FLSHCR4_WMENB_SHIFT              (3U)
+/*! WMENB - Write mask enable bit for flash device on port B. When write mask function is needed for
+ *    memory device on port B, this bit must be set.
+ *  0b0..Write mask is disabled, DQS(RWDS) pin will be un-driven when writing to external device.
+ *  0b1..Write mask is enabled, DQS(RWDS) pin will be driven by FlexSPI as write mask output when writing to external device.
+ */
 #define FLEXSPI_FLSHCR4_WMENB(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENB_SHIFT)) & FLEXSPI_FLSHCR4_WMENB_MASK)
 /*! @} */
 
@@ -11519,6 +17933,10 @@ typedef struct {
 #define FLEXSPI_IPCR1_ISEQNUM(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQNUM_SHIFT)) & FLEXSPI_IPCR1_ISEQNUM_MASK)
 #define FLEXSPI_IPCR1_IPAREN_MASK                (0x80000000U)
 #define FLEXSPI_IPCR1_IPAREN_SHIFT               (31U)
+/*! IPAREN - Parallel mode Enabled for IP command.
+ *  0b0..Flash will be accessed in Individual mode.
+ *  0b1..Flash will be accessed in Parallel mode.
+ */
 #define FLEXSPI_IPCR1_IPAREN(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IPAREN_SHIFT)) & FLEXSPI_IPCR1_IPAREN_MASK)
 /*! @} */
 
@@ -11536,6 +17954,10 @@ typedef struct {
 #define FLEXSPI_IPRXFCR_CLRIPRXF(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT)) & FLEXSPI_IPRXFCR_CLRIPRXF_MASK)
 #define FLEXSPI_IPRXFCR_RXDMAEN_MASK             (0x2U)
 #define FLEXSPI_IPRXFCR_RXDMAEN_SHIFT            (1U)
+/*! RXDMAEN - IP RX FIFO reading by DMA enabled.
+ *  0b0..IP RX FIFO would be read by processor.
+ *  0b1..IP RX FIFO would be read by DMA.
+ */
 #define FLEXSPI_IPRXFCR_RXDMAEN(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXDMAEN_SHIFT)) & FLEXSPI_IPRXFCR_RXDMAEN_MASK)
 #define FLEXSPI_IPRXFCR_RXWMRK_MASK              (0x3CU)
 #define FLEXSPI_IPRXFCR_RXWMRK_SHIFT             (2U)
@@ -11549,6 +17971,10 @@ typedef struct {
 #define FLEXSPI_IPTXFCR_CLRIPTXF(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT)) & FLEXSPI_IPTXFCR_CLRIPTXF_MASK)
 #define FLEXSPI_IPTXFCR_TXDMAEN_MASK             (0x2U)
 #define FLEXSPI_IPTXFCR_TXDMAEN_SHIFT            (1U)
+/*! TXDMAEN - IP TX FIFO filling by DMA enabled.
+ *  0b0..IP TX FIFO would be filled by processor.
+ *  0b1..IP TX FIFO would be filled by DMA.
+ */
 #define FLEXSPI_IPTXFCR_TXDMAEN(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXDMAEN_SHIFT)) & FLEXSPI_IPTXFCR_TXDMAEN_MASK)
 #define FLEXSPI_IPTXFCR_TXWMRK_MASK              (0x3CU)
 #define FLEXSPI_IPTXFCR_TXWMRK_SHIFT             (2U)
@@ -11587,6 +18013,13 @@ typedef struct {
 #define FLEXSPI_STS0_ARBIDLE(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBIDLE_SHIFT)) & FLEXSPI_STS0_ARBIDLE_MASK)
 #define FLEXSPI_STS0_ARBCMDSRC_MASK              (0xCU)
 #define FLEXSPI_STS0_ARBCMDSRC_SHIFT             (2U)
+/*! ARBCMDSRC - This status field indicates the trigger source of current command sequence granted
+ *    by arbitrator. This field value is meaningless when ARB_CTL is not busy (STS0[ARBIDLE]=0x1).
+ *  0b00..Triggered by AHB read command (triggered by AHB read).
+ *  0b01..Triggered by AHB write command (triggered by AHB Write).
+ *  0b10..Triggered by IP command (triggered by setting register bit IPCMD.TRG).
+ *  0b11..Triggered by suspended command (resumed).
+ */
 #define FLEXSPI_STS0_ARBCMDSRC(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBCMDSRC_SHIFT)) & FLEXSPI_STS0_ARBCMDSRC_MASK)
 /*! @} */
 
@@ -11597,12 +18030,32 @@ typedef struct {
 #define FLEXSPI_STS1_AHBCMDERRID(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRID_SHIFT)) & FLEXSPI_STS1_AHBCMDERRID_MASK)
 #define FLEXSPI_STS1_AHBCMDERRCODE_MASK          (0xF00U)
 #define FLEXSPI_STS1_AHBCMDERRCODE_SHIFT         (8U)
+/*! AHBCMDERRCODE - Indicates the Error Code when AHB command Error detected. This field will be
+ *    cleared when INTR[AHBCMDERR] is write-1-clear(w1c).
+ *  0b0000..No error.
+ *  0b0010..AHB Write command with JMP_ON_CS instruction used in the sequence.
+ *  0b0011..There is unknown instruction opcode in the sequence.
+ *  0b0100..Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in DDR sequence.
+ *  0b0101..Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in SDR sequence.
+ *  0b1110..Sequence execution timeout.
+ */
 #define FLEXSPI_STS1_AHBCMDERRCODE(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRCODE_SHIFT)) & FLEXSPI_STS1_AHBCMDERRCODE_MASK)
 #define FLEXSPI_STS1_IPCMDERRID_MASK             (0xF0000U)
 #define FLEXSPI_STS1_IPCMDERRID_SHIFT            (16U)
 #define FLEXSPI_STS1_IPCMDERRID(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRID_SHIFT)) & FLEXSPI_STS1_IPCMDERRID_MASK)
 #define FLEXSPI_STS1_IPCMDERRCODE_MASK           (0xF000000U)
 #define FLEXSPI_STS1_IPCMDERRCODE_SHIFT          (24U)
+/*! IPCMDERRCODE - Indicates the Error Code when IP command Error detected. This field will be
+ *    cleared when INTR[IPCMDERR] is write-1-clear(w1c).
+ *  0b0000..No error.
+ *  0b0010..IP command with JMP_ON_CS instruction used in the sequence.
+ *  0b0011..There is unknown instruction opcode in the sequence.
+ *  0b0100..Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in DDR sequence.
+ *  0b0101..Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in SDR sequence.
+ *  0b0110..Flash access start address exceed the whole flash address range (A1/A2/B1/B2).
+ *  0b1110..Sequence execution timeout.
+ *  0b1111..Flash boundary crossed.
+ */
 #define FLEXSPI_STS1_IPCMDERRCODE(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRCODE_SHIFT)) & FLEXSPI_STS1_IPCMDERRCODE_MASK)
 /*! @} */
 
@@ -11777,12 +18230,24 @@ typedef struct {
 /*! @{ */
 #define GPC_CNTR_MEGA_PDN_REQ_MASK               (0x4U)
 #define GPC_CNTR_MEGA_PDN_REQ_SHIFT              (2U)
+/*! MEGA_PDN_REQ
+ *  0b0..No Request
+ *  0b1..Request power down sequence
+ */
 #define GPC_CNTR_MEGA_PDN_REQ(x)                 (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_MEGA_PDN_REQ_SHIFT)) & GPC_CNTR_MEGA_PDN_REQ_MASK)
 #define GPC_CNTR_MEGA_PUP_REQ_MASK               (0x8U)
 #define GPC_CNTR_MEGA_PUP_REQ_SHIFT              (3U)
+/*! MEGA_PUP_REQ
+ *  0b0..No Request
+ *  0b1..Request power up sequence
+ */
 #define GPC_CNTR_MEGA_PUP_REQ(x)                 (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_MEGA_PUP_REQ_SHIFT)) & GPC_CNTR_MEGA_PUP_REQ_MASK)
 #define GPC_CNTR_PDRAM0_PGE_MASK                 (0x400000U)
 #define GPC_CNTR_PDRAM0_PGE_SHIFT                (22U)
+/*! PDRAM0_PGE
+ *  0b1..FlexRAM PDRAM0 domain (bank1-7) will be power down once when CPU core is power down.
+ *  0b0..FlexRAM PDRAM0 domain (bank1-7) will keep power on even if CPU core is power down.
+ */
 #define GPC_CNTR_PDRAM0_PGE(x)                   (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_PDRAM0_PGE_SHIFT)) & GPC_CNTR_PDRAM0_PGE_MASK)
 /*! @} */
 
@@ -11920,51 +18385,147 @@ typedef struct {
 /*! @{ */
 #define GPIO_ICR1_ICR0_MASK                      (0x3U)
 #define GPIO_ICR1_ICR0_SHIFT                     (0U)
+/*! ICR0 - ICR0
+ *  0b00..Interrupt n is low-level sensitive.
+ *  0b01..Interrupt n is high-level sensitive.
+ *  0b10..Interrupt n is rising-edge sensitive.
+ *  0b11..Interrupt n is falling-edge sensitive.
+ */
 #define GPIO_ICR1_ICR0(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR0_SHIFT)) & GPIO_ICR1_ICR0_MASK)
 #define GPIO_ICR1_ICR1_MASK                      (0xCU)
 #define GPIO_ICR1_ICR1_SHIFT                     (2U)
+/*! ICR1 - ICR1
+ *  0b00..Interrupt n is low-level sensitive.
+ *  0b01..Interrupt n is high-level sensitive.
+ *  0b10..Interrupt n is rising-edge sensitive.
+ *  0b11..Interrupt n is falling-edge sensitive.
+ */
 #define GPIO_ICR1_ICR1(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR1_SHIFT)) & GPIO_ICR1_ICR1_MASK)
 #define GPIO_ICR1_ICR2_MASK                      (0x30U)
 #define GPIO_ICR1_ICR2_SHIFT                     (4U)
+/*! ICR2 - ICR2
+ *  0b00..Interrupt n is low-level sensitive.
+ *  0b01..Interrupt n is high-level sensitive.
+ *  0b10..Interrupt n is rising-edge sensitive.
+ *  0b11..Interrupt n is falling-edge sensitive.
+ */
 #define GPIO_ICR1_ICR2(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR2_SHIFT)) & GPIO_ICR1_ICR2_MASK)
 #define GPIO_ICR1_ICR3_MASK                      (0xC0U)
 #define GPIO_ICR1_ICR3_SHIFT                     (6U)
+/*! ICR3 - ICR3
+ *  0b00..Interrupt n is low-level sensitive.
+ *  0b01..Interrupt n is high-level sensitive.
+ *  0b10..Interrupt n is rising-edge sensitive.
+ *  0b11..Interrupt n is falling-edge sensitive.
+ */
 #define GPIO_ICR1_ICR3(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR3_SHIFT)) & GPIO_ICR1_ICR3_MASK)
 #define GPIO_ICR1_ICR4_MASK                      (0x300U)
 #define GPIO_ICR1_ICR4_SHIFT                     (8U)
+/*! ICR4 - ICR4
+ *  0b00..Interrupt n is low-level sensitive.
+ *  0b01..Interrupt n is high-level sensitive.
+ *  0b10..Interrupt n is rising-edge sensitive.
+ *  0b11..Interrupt n is falling-edge sensitive.
+ */
 #define GPIO_ICR1_ICR4(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR4_SHIFT)) & GPIO_ICR1_ICR4_MASK)
 #define GPIO_ICR1_ICR5_MASK                      (0xC00U)
 #define GPIO_ICR1_ICR5_SHIFT                     (10U)
+/*! ICR5 - ICR5
+ *  0b00..Interrupt n is low-level sensitive.
+ *  0b01..Interrupt n is high-level sensitive.
+ *  0b10..Interrupt n is rising-edge sensitive.
+ *  0b11..Interrupt n is falling-edge sensitive.
+ */
 #define GPIO_ICR1_ICR5(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR5_SHIFT)) & GPIO_ICR1_ICR5_MASK)
 #define GPIO_ICR1_ICR6_MASK                      (0x3000U)
 #define GPIO_ICR1_ICR6_SHIFT                     (12U)
+/*! ICR6 - ICR6
+ *  0b00..Interrupt n is low-level sensitive.
+ *  0b01..Interrupt n is high-level sensitive.
+ *  0b10..Interrupt n is rising-edge sensitive.
+ *  0b11..Interrupt n is falling-edge sensitive.
+ */
 #define GPIO_ICR1_ICR6(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR6_SHIFT)) & GPIO_ICR1_ICR6_MASK)
 #define GPIO_ICR1_ICR7_MASK                      (0xC000U)
 #define GPIO_ICR1_ICR7_SHIFT                     (14U)
+/*! ICR7 - ICR7
+ *  0b00..Interrupt n is low-level sensitive.
+ *  0b01..Interrupt n is high-level sensitive.
+ *  0b10..Interrupt n is rising-edge sensitive.
+ *  0b11..Interrupt n is falling-edge sensitive.
+ */
 #define GPIO_ICR1_ICR7(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR7_SHIFT)) & GPIO_ICR1_ICR7_MASK)
 #define GPIO_ICR1_ICR8_MASK                      (0x30000U)
 #define GPIO_ICR1_ICR8_SHIFT                     (16U)
+/*! ICR8 - ICR8
+ *  0b00..Interrupt n is low-level sensitive.
+ *  0b01..Interrupt n is high-level sensitive.
+ *  0b10..Interrupt n is rising-edge sensitive.
+ *  0b11..Interrupt n is falling-edge sensitive.
+ */
 #define GPIO_ICR1_ICR8(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR8_SHIFT)) & GPIO_ICR1_ICR8_MASK)
 #define GPIO_ICR1_ICR9_MASK                      (0xC0000U)
 #define GPIO_ICR1_ICR9_SHIFT                     (18U)
+/*! ICR9 - ICR9
+ *  0b00..Interrupt n is low-level sensitive.
+ *  0b01..Interrupt n is high-level sensitive.
+ *  0b10..Interrupt n is rising-edge sensitive.
+ *  0b11..Interrupt n is falling-edge sensitive.
+ */
 #define GPIO_ICR1_ICR9(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR9_SHIFT)) & GPIO_ICR1_ICR9_MASK)
 #define GPIO_ICR1_ICR10_MASK                     (0x300000U)
 #define GPIO_ICR1_ICR10_SHIFT                    (20U)
+/*! ICR10 - ICR10
+ *  0b00..Interrupt n is low-level sensitive.
+ *  0b01..Interrupt n is high-level sensitive.
+ *  0b10..Interrupt n is rising-edge sensitive.
+ *  0b11..Interrupt n is falling-edge sensitive.
+ */
 #define GPIO_ICR1_ICR10(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR10_SHIFT)) & GPIO_ICR1_ICR10_MASK)
 #define GPIO_ICR1_ICR11_MASK                     (0xC00000U)
 #define GPIO_ICR1_ICR11_SHIFT                    (22U)
+/*! ICR11 - ICR11
+ *  0b00..Interrupt n is low-level sensitive.
+ *  0b01..Interrupt n is high-level sensitive.
+ *  0b10..Interrupt n is rising-edge sensitive.
+ *  0b11..Interrupt n is falling-edge sensitive.
+ */
 #define GPIO_ICR1_ICR11(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR11_SHIFT)) & GPIO_ICR1_ICR11_MASK)
 #define GPIO_ICR1_ICR12_MASK                     (0x3000000U)
 #define GPIO_ICR1_ICR12_SHIFT                    (24U)
+/*! ICR12 - ICR12
+ *  0b00..Interrupt n is low-level sensitive.
+ *  0b01..Interrupt n is high-level sensitive.
+ *  0b10..Interrupt n is rising-edge sensitive.
+ *  0b11..Interrupt n is falling-edge sensitive.
+ */
 #define GPIO_ICR1_ICR12(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR12_SHIFT)) & GPIO_ICR1_ICR12_MASK)
 #define GPIO_ICR1_ICR13_MASK                     (0xC000000U)
 #define GPIO_ICR1_ICR13_SHIFT                    (26U)
+/*! ICR13 - ICR13
+ *  0b00..Interrupt n is low-level sensitive.
+ *  0b01..Interrupt n is high-level sensitive.
+ *  0b10..Interrupt n is rising-edge sensitive.
+ *  0b11..Interrupt n is falling-edge sensitive.
+ */
 #define GPIO_ICR1_ICR13(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR13_SHIFT)) & GPIO_ICR1_ICR13_MASK)
 #define GPIO_ICR1_ICR14_MASK                     (0x30000000U)
 #define GPIO_ICR1_ICR14_SHIFT                    (28U)
+/*! ICR14 - ICR14
+ *  0b00..Interrupt n is low-level sensitive.
+ *  0b01..Interrupt n is high-level sensitive.
+ *  0b10..Interrupt n is rising-edge sensitive.
+ *  0b11..Interrupt n is falling-edge sensitive.
+ */
 #define GPIO_ICR1_ICR14(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR14_SHIFT)) & GPIO_ICR1_ICR14_MASK)
 #define GPIO_ICR1_ICR15_MASK                     (0xC0000000U)
 #define GPIO_ICR1_ICR15_SHIFT                    (30U)
+/*! ICR15 - ICR15
+ *  0b00..Interrupt n is low-level sensitive.
+ *  0b01..Interrupt n is high-level sensitive.
+ *  0b10..Interrupt n is rising-edge sensitive.
+ *  0b11..Interrupt n is falling-edge sensitive.
+ */
 #define GPIO_ICR1_ICR15(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR15_SHIFT)) & GPIO_ICR1_ICR15_MASK)
 /*! @} */
 
@@ -11972,51 +18533,147 @@ typedef struct {
 /*! @{ */
 #define GPIO_ICR2_ICR16_MASK                     (0x3U)
 #define GPIO_ICR2_ICR16_SHIFT                    (0U)
+/*! ICR16 - ICR16
+ *  0b00..Interrupt n is low-level sensitive.
+ *  0b01..Interrupt n is high-level sensitive.
+ *  0b10..Interrupt n is rising-edge sensitive.
+ *  0b11..Interrupt n is falling-edge sensitive.
+ */
 #define GPIO_ICR2_ICR16(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR16_SHIFT)) & GPIO_ICR2_ICR16_MASK)
 #define GPIO_ICR2_ICR17_MASK                     (0xCU)
 #define GPIO_ICR2_ICR17_SHIFT                    (2U)
+/*! ICR17 - ICR17
+ *  0b00..Interrupt n is low-level sensitive.
+ *  0b01..Interrupt n is high-level sensitive.
+ *  0b10..Interrupt n is rising-edge sensitive.
+ *  0b11..Interrupt n is falling-edge sensitive.
+ */
 #define GPIO_ICR2_ICR17(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR17_SHIFT)) & GPIO_ICR2_ICR17_MASK)
 #define GPIO_ICR2_ICR18_MASK                     (0x30U)
 #define GPIO_ICR2_ICR18_SHIFT                    (4U)
+/*! ICR18 - ICR18
+ *  0b00..Interrupt n is low-level sensitive.
+ *  0b01..Interrupt n is high-level sensitive.
+ *  0b10..Interrupt n is rising-edge sensitive.
+ *  0b11..Interrupt n is falling-edge sensitive.
+ */
 #define GPIO_ICR2_ICR18(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR18_SHIFT)) & GPIO_ICR2_ICR18_MASK)
 #define GPIO_ICR2_ICR19_MASK                     (0xC0U)
 #define GPIO_ICR2_ICR19_SHIFT                    (6U)
+/*! ICR19 - ICR19
+ *  0b00..Interrupt n is low-level sensitive.
+ *  0b01..Interrupt n is high-level sensitive.
+ *  0b10..Interrupt n is rising-edge sensitive.
+ *  0b11..Interrupt n is falling-edge sensitive.
+ */
 #define GPIO_ICR2_ICR19(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR19_SHIFT)) & GPIO_ICR2_ICR19_MASK)
 #define GPIO_ICR2_ICR20_MASK                     (0x300U)
 #define GPIO_ICR2_ICR20_SHIFT                    (8U)
+/*! ICR20 - ICR20
+ *  0b00..Interrupt n is low-level sensitive.
+ *  0b01..Interrupt n is high-level sensitive.
+ *  0b10..Interrupt n is rising-edge sensitive.
+ *  0b11..Interrupt n is falling-edge sensitive.
+ */
 #define GPIO_ICR2_ICR20(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR20_SHIFT)) & GPIO_ICR2_ICR20_MASK)
 #define GPIO_ICR2_ICR21_MASK                     (0xC00U)
 #define GPIO_ICR2_ICR21_SHIFT                    (10U)
+/*! ICR21 - ICR21
+ *  0b00..Interrupt n is low-level sensitive.
+ *  0b01..Interrupt n is high-level sensitive.
+ *  0b10..Interrupt n is rising-edge sensitive.
+ *  0b11..Interrupt n is falling-edge sensitive.
+ */
 #define GPIO_ICR2_ICR21(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR21_SHIFT)) & GPIO_ICR2_ICR21_MASK)
 #define GPIO_ICR2_ICR22_MASK                     (0x3000U)
 #define GPIO_ICR2_ICR22_SHIFT                    (12U)
+/*! ICR22 - ICR22
+ *  0b00..Interrupt n is low-level sensitive.
+ *  0b01..Interrupt n is high-level sensitive.
+ *  0b10..Interrupt n is rising-edge sensitive.
+ *  0b11..Interrupt n is falling-edge sensitive.
+ */
 #define GPIO_ICR2_ICR22(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR22_SHIFT)) & GPIO_ICR2_ICR22_MASK)
 #define GPIO_ICR2_ICR23_MASK                     (0xC000U)
 #define GPIO_ICR2_ICR23_SHIFT                    (14U)
+/*! ICR23 - ICR23
+ *  0b00..Interrupt n is low-level sensitive.
+ *  0b01..Interrupt n is high-level sensitive.
+ *  0b10..Interrupt n is rising-edge sensitive.
+ *  0b11..Interrupt n is falling-edge sensitive.
+ */
 #define GPIO_ICR2_ICR23(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR23_SHIFT)) & GPIO_ICR2_ICR23_MASK)
 #define GPIO_ICR2_ICR24_MASK                     (0x30000U)
 #define GPIO_ICR2_ICR24_SHIFT                    (16U)
+/*! ICR24 - ICR24
+ *  0b00..Interrupt n is low-level sensitive.
+ *  0b01..Interrupt n is high-level sensitive.
+ *  0b10..Interrupt n is rising-edge sensitive.
+ *  0b11..Interrupt n is falling-edge sensitive.
+ */
 #define GPIO_ICR2_ICR24(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR24_SHIFT)) & GPIO_ICR2_ICR24_MASK)
 #define GPIO_ICR2_ICR25_MASK                     (0xC0000U)
 #define GPIO_ICR2_ICR25_SHIFT                    (18U)
+/*! ICR25 - ICR25
+ *  0b00..Interrupt n is low-level sensitive.
+ *  0b01..Interrupt n is high-level sensitive.
+ *  0b10..Interrupt n is rising-edge sensitive.
+ *  0b11..Interrupt n is falling-edge sensitive.
+ */
 #define GPIO_ICR2_ICR25(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR25_SHIFT)) & GPIO_ICR2_ICR25_MASK)
 #define GPIO_ICR2_ICR26_MASK                     (0x300000U)
 #define GPIO_ICR2_ICR26_SHIFT                    (20U)
+/*! ICR26 - ICR26
+ *  0b00..Interrupt n is low-level sensitive.
+ *  0b01..Interrupt n is high-level sensitive.
+ *  0b10..Interrupt n is rising-edge sensitive.
+ *  0b11..Interrupt n is falling-edge sensitive.
+ */
 #define GPIO_ICR2_ICR26(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR26_SHIFT)) & GPIO_ICR2_ICR26_MASK)
 #define GPIO_ICR2_ICR27_MASK                     (0xC00000U)
 #define GPIO_ICR2_ICR27_SHIFT                    (22U)
+/*! ICR27 - ICR27
+ *  0b00..Interrupt n is low-level sensitive.
+ *  0b01..Interrupt n is high-level sensitive.
+ *  0b10..Interrupt n is rising-edge sensitive.
+ *  0b11..Interrupt n is falling-edge sensitive.
+ */
 #define GPIO_ICR2_ICR27(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR27_SHIFT)) & GPIO_ICR2_ICR27_MASK)
 #define GPIO_ICR2_ICR28_MASK                     (0x3000000U)
 #define GPIO_ICR2_ICR28_SHIFT                    (24U)
+/*! ICR28 - ICR28
+ *  0b00..Interrupt n is low-level sensitive.
+ *  0b01..Interrupt n is high-level sensitive.
+ *  0b10..Interrupt n is rising-edge sensitive.
+ *  0b11..Interrupt n is falling-edge sensitive.
+ */
 #define GPIO_ICR2_ICR28(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR28_SHIFT)) & GPIO_ICR2_ICR28_MASK)
 #define GPIO_ICR2_ICR29_MASK                     (0xC000000U)
 #define GPIO_ICR2_ICR29_SHIFT                    (26U)
+/*! ICR29 - ICR29
+ *  0b00..Interrupt n is low-level sensitive.
+ *  0b01..Interrupt n is high-level sensitive.
+ *  0b10..Interrupt n is rising-edge sensitive.
+ *  0b11..Interrupt n is falling-edge sensitive.
+ */
 #define GPIO_ICR2_ICR29(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR29_SHIFT)) & GPIO_ICR2_ICR29_MASK)
 #define GPIO_ICR2_ICR30_MASK                     (0x30000000U)
 #define GPIO_ICR2_ICR30_SHIFT                    (28U)
+/*! ICR30 - ICR30
+ *  0b00..Interrupt n is low-level sensitive.
+ *  0b01..Interrupt n is high-level sensitive.
+ *  0b10..Interrupt n is rising-edge sensitive.
+ *  0b11..Interrupt n is falling-edge sensitive.
+ */
 #define GPIO_ICR2_ICR30(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR30_SHIFT)) & GPIO_ICR2_ICR30_MASK)
 #define GPIO_ICR2_ICR31_MASK                     (0xC0000000U)
 #define GPIO_ICR2_ICR31_SHIFT                    (30U)
+/*! ICR31 - ICR31
+ *  0b00..Interrupt n is low-level sensitive.
+ *  0b01..Interrupt n is high-level sensitive.
+ *  0b10..Interrupt n is rising-edge sensitive.
+ *  0b11..Interrupt n is falling-edge sensitive.
+ */
 #define GPIO_ICR2_ICR31(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR31_SHIFT)) & GPIO_ICR2_ICR31_MASK)
 /*! @} */
 
@@ -12095,7 +18752,8 @@ typedef struct {
 #define GPIO_BASE_PTRS                           { (GPIO_Type *)0u, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5 }
 /** Interrupt vectors for the GPIO peripheral type */
 #define GPIO_IRQS                                { NotAvail_IRQn, GPIO1_INT0_IRQn, GPIO1_INT1_IRQn, GPIO1_INT2_IRQn, GPIO1_INT3_IRQn, GPIO1_INT4_IRQn, GPIO1_INT5_IRQn, GPIO1_INT6_IRQn, GPIO1_INT7_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }
-#define GPIO_COMBINED_IRQS                       { NotAvail_IRQn, GPIO1_Combined_16_31_IRQn, GPIO1_Combined_0_15_IRQn, GPIO2_Combined_16_31_IRQn, GPIO2_Combined_0_15_IRQn, GPIO3_Combined_16_31_IRQn, GPIO3_Combined_0_15_IRQn, GPIO4_Combined_16_31_IRQn, GPIO4_Combined_0_15_IRQn, GPIO5_Combined_16_31_IRQn, GPIO5_Combined_0_15_IRQn }
+#define GPIO_COMBINED_LOW_IRQS                   { NotAvail_IRQn, GPIO1_Combined_0_15_IRQn, GPIO2_Combined_0_15_IRQn, GPIO3_Combined_0_15_IRQn, GPIO4_Combined_0_15_IRQn, GPIO5_Combined_0_15_IRQn }
+#define GPIO_COMBINED_HIGH_IRQS                  { NotAvail_IRQn, GPIO1_Combined_16_31_IRQn, GPIO2_Combined_16_31_IRQn, GPIO3_Combined_16_31_IRQn, GPIO4_Combined_16_31_IRQn, GPIO5_Combined_16_31_IRQn }
 
 /*!
  * @}
@@ -12135,39 +18793,89 @@ typedef struct {
 /*! @{ */
 #define GPT_CR_EN_MASK                           (0x1U)
 #define GPT_CR_EN_SHIFT                          (0U)
+/*! EN
+ *  0b0..GPT is disabled.
+ *  0b1..GPT is enabled.
+ */
 #define GPT_CR_EN(x)                             (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_SHIFT)) & GPT_CR_EN_MASK)
 #define GPT_CR_ENMOD_MASK                        (0x2U)
 #define GPT_CR_ENMOD_SHIFT                       (1U)
+/*! ENMOD
+ *  0b0..GPT counter will retain its value when it is disabled.
+ *  0b1..GPT counter value is reset to 0 when it is disabled.
+ */
 #define GPT_CR_ENMOD(x)                          (((uint32_t)(((uint32_t)(x)) << GPT_CR_ENMOD_SHIFT)) & GPT_CR_ENMOD_MASK)
 #define GPT_CR_DBGEN_MASK                        (0x4U)
 #define GPT_CR_DBGEN_SHIFT                       (2U)
+/*! DBGEN
+ *  0b0..GPT is disabled in debug mode.
+ *  0b1..GPT is enabled in debug mode.
+ */
 #define GPT_CR_DBGEN(x)                          (((uint32_t)(((uint32_t)(x)) << GPT_CR_DBGEN_SHIFT)) & GPT_CR_DBGEN_MASK)
 #define GPT_CR_WAITEN_MASK                       (0x8U)
 #define GPT_CR_WAITEN_SHIFT                      (3U)
+/*! WAITEN
+ *  0b0..GPT is disabled in wait mode.
+ *  0b1..GPT is enabled in wait mode.
+ */
 #define GPT_CR_WAITEN(x)                         (((uint32_t)(((uint32_t)(x)) << GPT_CR_WAITEN_SHIFT)) & GPT_CR_WAITEN_MASK)
 #define GPT_CR_DOZEEN_MASK                       (0x10U)
 #define GPT_CR_DOZEEN_SHIFT                      (4U)
+/*! DOZEEN
+ *  0b0..GPT is disabled in doze mode.
+ *  0b1..GPT is enabled in doze mode.
+ */
 #define GPT_CR_DOZEEN(x)                         (((uint32_t)(((uint32_t)(x)) << GPT_CR_DOZEEN_SHIFT)) & GPT_CR_DOZEEN_MASK)
 #define GPT_CR_STOPEN_MASK                       (0x20U)
 #define GPT_CR_STOPEN_SHIFT                      (5U)
+/*! STOPEN
+ *  0b0..GPT is disabled in Stop mode.
+ *  0b1..GPT is enabled in Stop mode.
+ */
 #define GPT_CR_STOPEN(x)                         (((uint32_t)(((uint32_t)(x)) << GPT_CR_STOPEN_SHIFT)) & GPT_CR_STOPEN_MASK)
 #define GPT_CR_CLKSRC_MASK                       (0x1C0U)
 #define GPT_CR_CLKSRC_SHIFT                      (6U)
+/*! CLKSRC
+ *  0b000..No clock
+ *  0b001..Peripheral Clock (ipg_clk)
+ *  0b010..High Frequency Reference Clock (ipg_clk_highfreq)
+ *  0b011..External Clock
+ *  0b100..Low Frequency Reference Clock (ipg_clk_32k)
+ *  0b101..Crystal oscillator as Reference Clock (ipg_clk_24M)
+ */
 #define GPT_CR_CLKSRC(x)                         (((uint32_t)(((uint32_t)(x)) << GPT_CR_CLKSRC_SHIFT)) & GPT_CR_CLKSRC_MASK)
 #define GPT_CR_FRR_MASK                          (0x200U)
 #define GPT_CR_FRR_SHIFT                         (9U)
+/*! FRR
+ *  0b0..Restart mode
+ *  0b1..Free-Run mode
+ */
 #define GPT_CR_FRR(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_CR_FRR_SHIFT)) & GPT_CR_FRR_MASK)
 #define GPT_CR_EN_24M_MASK                       (0x400U)
 #define GPT_CR_EN_24M_SHIFT                      (10U)
+/*! EN_24M
+ *  0b0..24M clock disabled
+ *  0b1..24M clock enabled
+ */
 #define GPT_CR_EN_24M(x)                         (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_24M_SHIFT)) & GPT_CR_EN_24M_MASK)
 #define GPT_CR_SWR_MASK                          (0x8000U)
 #define GPT_CR_SWR_SHIFT                         (15U)
+/*! SWR
+ *  0b0..GPT is not in reset state
+ *  0b1..GPT is in reset state
+ */
 #define GPT_CR_SWR(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_CR_SWR_SHIFT)) & GPT_CR_SWR_MASK)
 #define GPT_CR_IM1_MASK                          (0x30000U)
 #define GPT_CR_IM1_SHIFT                         (16U)
 #define GPT_CR_IM1(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM1_SHIFT)) & GPT_CR_IM1_MASK)
 #define GPT_CR_IM2_MASK                          (0xC0000U)
 #define GPT_CR_IM2_SHIFT                         (18U)
+/*! IM2
+ *  0b00..capture disabled
+ *  0b01..capture on rising edge only
+ *  0b10..capture on falling edge only
+ *  0b11..capture on both edges
+ */
 #define GPT_CR_IM2(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM2_SHIFT)) & GPT_CR_IM2_MASK)
 #define GPT_CR_OM1_MASK                          (0x700000U)
 #define GPT_CR_OM1_SHIFT                         (20U)
@@ -12177,6 +18885,13 @@ typedef struct {
 #define GPT_CR_OM2(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM2_SHIFT)) & GPT_CR_OM2_MASK)
 #define GPT_CR_OM3_MASK                          (0x1C000000U)
 #define GPT_CR_OM3_SHIFT                         (26U)
+/*! OM3
+ *  0b000..Output disconnected. No response on pin.
+ *  0b001..Toggle output pin
+ *  0b010..Clear output pin
+ *  0b011..Set output pin
+ *  0b1xx..Generate an active low pulse (that is one input clock wide) on the output pin.
+ */
 #define GPT_CR_OM3(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM3_SHIFT)) & GPT_CR_OM3_MASK)
 #define GPT_CR_FO1_MASK                          (0x20000000U)
 #define GPT_CR_FO1_SHIFT                         (29U)
@@ -12186,6 +18901,10 @@ typedef struct {
 #define GPT_CR_FO2(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO2_SHIFT)) & GPT_CR_FO2_MASK)
 #define GPT_CR_FO3_MASK                          (0x80000000U)
 #define GPT_CR_FO3_SHIFT                         (31U)
+/*! FO3
+ *  0b0..Writing a 0 has no effect.
+ *  0b1..Causes the programmed pin action on the timer Output Compare n pin; the OFn flag is not set.
+ */
 #define GPT_CR_FO3(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO3_SHIFT)) & GPT_CR_FO3_MASK)
 /*! @} */
 
@@ -12193,9 +18912,19 @@ typedef struct {
 /*! @{ */
 #define GPT_PR_PRESCALER_MASK                    (0xFFFU)
 #define GPT_PR_PRESCALER_SHIFT                   (0U)
+/*! PRESCALER
+ *  0b000000000000..Divide by 1
+ *  0b000000000001..Divide by 2
+ *  0b111111111111..Divide by 4096
+ */
 #define GPT_PR_PRESCALER(x)                      (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER_SHIFT)) & GPT_PR_PRESCALER_MASK)
 #define GPT_PR_PRESCALER24M_MASK                 (0xF000U)
 #define GPT_PR_PRESCALER24M_SHIFT                (12U)
+/*! PRESCALER24M
+ *  0b0000..Divide by 1
+ *  0b0001..Divide by 2
+ *  0b1111..Divide by 16
+ */
 #define GPT_PR_PRESCALER24M(x)                   (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER24M_SHIFT)) & GPT_PR_PRESCALER24M_MASK)
 /*! @} */
 
@@ -12209,15 +18938,27 @@ typedef struct {
 #define GPT_SR_OF2(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF2_SHIFT)) & GPT_SR_OF2_MASK)
 #define GPT_SR_OF3_MASK                          (0x4U)
 #define GPT_SR_OF3_SHIFT                         (2U)
+/*! OF3
+ *  0b0..Compare event has not occurred.
+ *  0b1..Compare event has occurred.
+ */
 #define GPT_SR_OF3(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF3_SHIFT)) & GPT_SR_OF3_MASK)
 #define GPT_SR_IF1_MASK                          (0x8U)
 #define GPT_SR_IF1_SHIFT                         (3U)
 #define GPT_SR_IF1(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF1_SHIFT)) & GPT_SR_IF1_MASK)
 #define GPT_SR_IF2_MASK                          (0x10U)
 #define GPT_SR_IF2_SHIFT                         (4U)
+/*! IF2
+ *  0b0..Capture event has not occurred.
+ *  0b1..Capture event has occurred.
+ */
 #define GPT_SR_IF2(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF2_SHIFT)) & GPT_SR_IF2_MASK)
 #define GPT_SR_ROV_MASK                          (0x20U)
 #define GPT_SR_ROV_SHIFT                         (5U)
+/*! ROV
+ *  0b0..Rollover has not occurred.
+ *  0b1..Rollover has occurred.
+ */
 #define GPT_SR_ROV(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_SR_ROV_SHIFT)) & GPT_SR_ROV_MASK)
 /*! @} */
 
@@ -12231,15 +18972,27 @@ typedef struct {
 #define GPT_IR_OF2IE(x)                          (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF2IE_SHIFT)) & GPT_IR_OF2IE_MASK)
 #define GPT_IR_OF3IE_MASK                        (0x4U)
 #define GPT_IR_OF3IE_SHIFT                       (2U)
+/*! OF3IE
+ *  0b0..Output Compare Channel n interrupt is disabled.
+ *  0b1..Output Compare Channel n interrupt is enabled.
+ */
 #define GPT_IR_OF3IE(x)                          (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF3IE_SHIFT)) & GPT_IR_OF3IE_MASK)
 #define GPT_IR_IF1IE_MASK                        (0x8U)
 #define GPT_IR_IF1IE_SHIFT                       (3U)
 #define GPT_IR_IF1IE(x)                          (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF1IE_SHIFT)) & GPT_IR_IF1IE_MASK)
 #define GPT_IR_IF2IE_MASK                        (0x10U)
 #define GPT_IR_IF2IE_SHIFT                       (4U)
+/*! IF2IE
+ *  0b0..IF2IE Input Capture n Interrupt Enable is disabled.
+ *  0b1..IF2IE Input Capture n Interrupt Enable is enabled.
+ */
 #define GPT_IR_IF2IE(x)                          (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF2IE_SHIFT)) & GPT_IR_IF2IE_MASK)
 #define GPT_IR_ROVIE_MASK                        (0x20U)
 #define GPT_IR_ROVIE_SHIFT                       (5U)
+/*! ROVIE
+ *  0b0..Rollover interrupt is disabled.
+ *  0b1..Rollover interrupt enabled.
+ */
 #define GPT_IR_ROVIE(x)                          (((uint32_t)(((uint32_t)(x)) << GPT_IR_ROVIE_SHIFT)) & GPT_IR_ROVIE_MASK)
 /*! @} */
 
@@ -12348,6 +19101,9 @@ typedef struct {
 /*! @{ */
 #define I2S_VERID_FEATURE_MASK                   (0xFFFFU)
 #define I2S_VERID_FEATURE_SHIFT                  (0U)
+/*! FEATURE - Feature Specification Number
+ *  0b0000000000000000..Standard feature set.
+ */
 #define I2S_VERID_FEATURE(x)                     (((uint32_t)(((uint32_t)(x)) << I2S_VERID_FEATURE_SHIFT)) & I2S_VERID_FEATURE_MASK)
 #define I2S_VERID_MINOR_MASK                     (0xFF0000U)
 #define I2S_VERID_MINOR_SHIFT                    (16U)
@@ -12374,57 +19130,129 @@ typedef struct {
 /*! @{ */
 #define I2S_TCSR_FRDE_MASK                       (0x1U)
 #define I2S_TCSR_FRDE_SHIFT                      (0U)
+/*! FRDE - FIFO Request DMA Enable
+ *  0b0..Disables the DMA request.
+ *  0b1..Enables the DMA request.
+ */
 #define I2S_TCSR_FRDE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK)
 #define I2S_TCSR_FWDE_MASK                       (0x2U)
 #define I2S_TCSR_FWDE_SHIFT                      (1U)
+/*! FWDE - FIFO Warning DMA Enable
+ *  0b0..Disables the DMA request.
+ *  0b1..Enables the DMA request.
+ */
 #define I2S_TCSR_FWDE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK)
 #define I2S_TCSR_FRIE_MASK                       (0x100U)
 #define I2S_TCSR_FRIE_SHIFT                      (8U)
+/*! FRIE - FIFO Request Interrupt Enable
+ *  0b0..Disables the interrupt.
+ *  0b1..Enables the interrupt.
+ */
 #define I2S_TCSR_FRIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK)
 #define I2S_TCSR_FWIE_MASK                       (0x200U)
 #define I2S_TCSR_FWIE_SHIFT                      (9U)
+/*! FWIE - FIFO Warning Interrupt Enable
+ *  0b0..Disables the interrupt.
+ *  0b1..Enables the interrupt.
+ */
 #define I2S_TCSR_FWIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK)
 #define I2S_TCSR_FEIE_MASK                       (0x400U)
 #define I2S_TCSR_FEIE_SHIFT                      (10U)
+/*! FEIE - FIFO Error Interrupt Enable
+ *  0b0..Disables the interrupt.
+ *  0b1..Enables the interrupt.
+ */
 #define I2S_TCSR_FEIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK)
 #define I2S_TCSR_SEIE_MASK                       (0x800U)
 #define I2S_TCSR_SEIE_SHIFT                      (11U)
+/*! SEIE - Sync Error Interrupt Enable
+ *  0b0..Disables interrupt.
+ *  0b1..Enables interrupt.
+ */
 #define I2S_TCSR_SEIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK)
 #define I2S_TCSR_WSIE_MASK                       (0x1000U)
 #define I2S_TCSR_WSIE_SHIFT                      (12U)
+/*! WSIE - Word Start Interrupt Enable
+ *  0b0..Disables interrupt.
+ *  0b1..Enables interrupt.
+ */
 #define I2S_TCSR_WSIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK)
 #define I2S_TCSR_FRF_MASK                        (0x10000U)
 #define I2S_TCSR_FRF_SHIFT                       (16U)
+/*! FRF - FIFO Request Flag
+ *  0b0..Transmit FIFO watermark has not been reached.
+ *  0b1..Transmit FIFO watermark has been reached.
+ */
 #define I2S_TCSR_FRF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK)
 #define I2S_TCSR_FWF_MASK                        (0x20000U)
 #define I2S_TCSR_FWF_SHIFT                       (17U)
+/*! FWF - FIFO Warning Flag
+ *  0b0..No enabled transmit FIFO is empty.
+ *  0b1..Enabled transmit FIFO is empty.
+ */
 #define I2S_TCSR_FWF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK)
 #define I2S_TCSR_FEF_MASK                        (0x40000U)
 #define I2S_TCSR_FEF_SHIFT                       (18U)
+/*! FEF - FIFO Error Flag
+ *  0b0..Transmit underrun not detected.
+ *  0b1..Transmit underrun detected.
+ */
 #define I2S_TCSR_FEF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK)
 #define I2S_TCSR_SEF_MASK                        (0x80000U)
 #define I2S_TCSR_SEF_SHIFT                       (19U)
+/*! SEF - Sync Error Flag
+ *  0b0..Sync error not detected.
+ *  0b1..Frame sync error detected.
+ */
 #define I2S_TCSR_SEF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK)
 #define I2S_TCSR_WSF_MASK                        (0x100000U)
 #define I2S_TCSR_WSF_SHIFT                       (20U)
+/*! WSF - Word Start Flag
+ *  0b0..Start of word not detected.
+ *  0b1..Start of word detected.
+ */
 #define I2S_TCSR_WSF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK)
 #define I2S_TCSR_SR_MASK                         (0x1000000U)
 #define I2S_TCSR_SR_SHIFT                        (24U)
+/*! SR - Software Reset
+ *  0b0..No effect.
+ *  0b1..Software reset.
+ */
 #define I2S_TCSR_SR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK)
 #define I2S_TCSR_FR_MASK                         (0x2000000U)
 #define I2S_TCSR_FR_SHIFT                        (25U)
+/*! FR - FIFO Reset
+ *  0b0..No effect.
+ *  0b1..FIFO reset.
+ */
 #define I2S_TCSR_FR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK)
 #define I2S_TCSR_BCE_MASK                        (0x10000000U)
 #define I2S_TCSR_BCE_SHIFT                       (28U)
+/*! BCE - Bit Clock Enable
+ *  0b0..Transmit bit clock is disabled.
+ *  0b1..Transmit bit clock is enabled.
+ */
 #define I2S_TCSR_BCE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK)
 #define I2S_TCSR_DBGE_MASK                       (0x20000000U)
 #define I2S_TCSR_DBGE_SHIFT                      (29U)
+/*! DBGE - Debug Enable
+ *  0b0..Transmitter is disabled in Debug mode, after completing the current frame.
+ *  0b1..Transmitter is enabled in Debug mode.
+ */
 #define I2S_TCSR_DBGE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK)
 #define I2S_TCSR_STOPE_MASK                      (0x40000000U)
 #define I2S_TCSR_STOPE_SHIFT                     (30U)
+/*! STOPE - Stop Enable
+ *  0b0..Transmitter disabled in Stop mode.
+ *  0b1..Transmitter enabled in Stop mode.
+ */
 #define I2S_TCSR_STOPE(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK)
 #define I2S_TCSR_TE_MASK                         (0x80000000U)
 #define I2S_TCSR_TE_SHIFT                        (31U)
+/*! TE - Transmitter Enable
+ *  0b0..Transmitter is disabled.
+ *  0b1..Transmitter is enabled, or transmitter has been disabled and has not yet reached end of frame.
+ */
 #define I2S_TCSR_TE(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK)
 /*! @} */
 
@@ -12442,21 +19270,49 @@ typedef struct {
 #define I2S_TCR2_DIV(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK)
 #define I2S_TCR2_BCD_MASK                        (0x1000000U)
 #define I2S_TCR2_BCD_SHIFT                       (24U)
+/*! BCD - Bit Clock Direction
+ *  0b0..Bit clock is generated externally in Slave mode.
+ *  0b1..Bit clock is generated internally in Master mode.
+ */
 #define I2S_TCR2_BCD(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK)
 #define I2S_TCR2_BCP_MASK                        (0x2000000U)
 #define I2S_TCR2_BCP_SHIFT                       (25U)
+/*! BCP - Bit Clock Polarity
+ *  0b0..Bit clock is active high with drive outputs on rising edge and sample inputs on falling edge.
+ *  0b1..Bit clock is active low with drive outputs on falling edge and sample inputs on rising edge.
+ */
 #define I2S_TCR2_BCP(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK)
 #define I2S_TCR2_MSEL_MASK                       (0xC000000U)
 #define I2S_TCR2_MSEL_SHIFT                      (26U)
+/*! MSEL - MCLK Select
+ *  0b00..Bus Clock selected.
+ *  0b01..Master Clock (MCLK) 1 option selected.
+ *  0b10..Master Clock (MCLK) 2 option selected.
+ *  0b11..Master Clock (MCLK) 3 option selected.
+ */
 #define I2S_TCR2_MSEL(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK)
 #define I2S_TCR2_BCI_MASK                        (0x10000000U)
 #define I2S_TCR2_BCI_SHIFT                       (28U)
+/*! BCI - Bit Clock Input
+ *  0b0..No effect.
+ *  0b1..Internal logic is clocked as if bit clock was externally generated.
+ */
 #define I2S_TCR2_BCI(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK)
 #define I2S_TCR2_BCS_MASK                        (0x20000000U)
 #define I2S_TCR2_BCS_SHIFT                       (29U)
+/*! BCS - Bit Clock Swap
+ *  0b0..Use the normal bit clock source.
+ *  0b1..Swap the bit clock source.
+ */
 #define I2S_TCR2_BCS(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK)
 #define I2S_TCR2_SYNC_MASK                       (0xC0000000U)
 #define I2S_TCR2_SYNC_SHIFT                      (30U)
+/*! SYNC - Synchronous Mode
+ *  0b00..Asynchronous mode.
+ *  0b01..Synchronous with receiver.
+ *  0b10..Reserved.
+ *  0b11..Reserved.
+ */
 #define I2S_TCR2_SYNC(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK)
 /*! @} */
 
@@ -12465,9 +19321,9 @@ typedef struct {
 #define I2S_TCR3_WDFL_MASK                       (0x1FU)
 #define I2S_TCR3_WDFL_SHIFT                      (0U)
 #define I2S_TCR3_WDFL(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK)
-#define I2S_TCR3_TCE_MASK                        (0xF0000U)
+#define I2S_TCR3_TCE_MASK                        (0xF0000U)  /* Merged from fields with different position or width, of widths (1, 4), largest definition used */
 #define I2S_TCR3_TCE_SHIFT                       (16U)
-#define I2S_TCR3_TCE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK)
+#define I2S_TCR3_TCE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK)  /* Merged from fields with different position or width, of widths (1, 4), largest definition used */
 #define I2S_TCR3_CFR_MASK                        (0xF000000U)
 #define I2S_TCR3_CFR_SHIFT                       (24U)
 #define I2S_TCR3_CFR(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_CFR_SHIFT)) & I2S_TCR3_CFR_MASK)
@@ -12477,21 +19333,45 @@ typedef struct {
 /*! @{ */
 #define I2S_TCR4_FSD_MASK                        (0x1U)
 #define I2S_TCR4_FSD_SHIFT                       (0U)
+/*! FSD - Frame Sync Direction
+ *  0b0..Frame sync is generated externally in Slave mode.
+ *  0b1..Frame sync is generated internally in Master mode.
+ */
 #define I2S_TCR4_FSD(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK)
 #define I2S_TCR4_FSP_MASK                        (0x2U)
 #define I2S_TCR4_FSP_SHIFT                       (1U)
+/*! FSP - Frame Sync Polarity
+ *  0b0..Frame sync is active high.
+ *  0b1..Frame sync is active low.
+ */
 #define I2S_TCR4_FSP(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK)
 #define I2S_TCR4_ONDEM_MASK                      (0x4U)
 #define I2S_TCR4_ONDEM_SHIFT                     (2U)
+/*! ONDEM - On Demand Mode
+ *  0b0..Internal frame sync is generated continuously.
+ *  0b1..Internal frame sync is generated when the FIFO warning flag is clear.
+ */
 #define I2S_TCR4_ONDEM(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_ONDEM_SHIFT)) & I2S_TCR4_ONDEM_MASK)
 #define I2S_TCR4_FSE_MASK                        (0x8U)
 #define I2S_TCR4_FSE_SHIFT                       (3U)
+/*! FSE - Frame Sync Early
+ *  0b0..Frame sync asserts with the first bit of the frame.
+ *  0b1..Frame sync asserts one bit before the first bit of the frame.
+ */
 #define I2S_TCR4_FSE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK)
 #define I2S_TCR4_MF_MASK                         (0x10U)
 #define I2S_TCR4_MF_SHIFT                        (4U)
+/*! MF - MSB First
+ *  0b0..LSB is transmitted first.
+ *  0b1..MSB is transmitted first.
+ */
 #define I2S_TCR4_MF(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK)
 #define I2S_TCR4_CHMOD_MASK                      (0x20U)
 #define I2S_TCR4_CHMOD_SHIFT                     (5U)
+/*! CHMOD - Channel Mode
+ *  0b0..TDM mode, transmit data pins are tri-stated when slots are masked or channels are disabled.
+ *  0b1..Output mode, transmit data pins are never tri-stated and will output zero when slots are masked or channels are disabled.
+ */
 #define I2S_TCR4_CHMOD(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_CHMOD_SHIFT)) & I2S_TCR4_CHMOD_MASK)
 #define I2S_TCR4_SYWD_MASK                       (0x1F00U)
 #define I2S_TCR4_SYWD_SHIFT                      (8U)
@@ -12501,12 +19381,28 @@ typedef struct {
 #define I2S_TCR4_FRSZ(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK)
 #define I2S_TCR4_FPACK_MASK                      (0x3000000U)
 #define I2S_TCR4_FPACK_SHIFT                     (24U)
+/*! FPACK - FIFO Packing Mode
+ *  0b00..FIFO packing is disabled
+ *  0b01..Reserved
+ *  0b10..8-bit FIFO packing is enabled
+ *  0b11..16-bit FIFO packing is enabled
+ */
 #define I2S_TCR4_FPACK(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FPACK_SHIFT)) & I2S_TCR4_FPACK_MASK)
 #define I2S_TCR4_FCOMB_MASK                      (0xC000000U)
 #define I2S_TCR4_FCOMB_SHIFT                     (26U)
+/*! FCOMB - FIFO Combine Mode
+ *  0b00..FIFO combine mode disabled.
+ *  0b01..FIFO combine mode enabled on FIFO reads (from transmit shift registers).
+ *  0b10..FIFO combine mode enabled on FIFO writes (by software).
+ *  0b11..FIFO combine mode enabled on FIFO reads (from transmit shift registers) and writes (by software).
+ */
 #define I2S_TCR4_FCOMB(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCOMB_SHIFT)) & I2S_TCR4_FCOMB_MASK)
 #define I2S_TCR4_FCONT_MASK                      (0x10000000U)
 #define I2S_TCR4_FCONT_SHIFT                     (28U)
+/*! FCONT - FIFO Continue on Error
+ *  0b0..On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared.
+ *  0b1..On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared.
+ */
 #define I2S_TCR4_FCONT(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCONT_SHIFT)) & I2S_TCR4_FCONT_MASK)
 /*! @} */
 
@@ -12543,6 +19439,10 @@ typedef struct {
 #define I2S_TFR_WFP(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WFP_SHIFT)) & I2S_TFR_WFP_MASK)
 #define I2S_TFR_WCP_MASK                         (0x80000000U)
 #define I2S_TFR_WCP_SHIFT                        (31U)
+/*! WCP - Write Channel Pointer
+ *  0b0..No effect.
+ *  0b1..FIFO combine is enabled for FIFO writes and this FIFO will be written on the next FIFO write.
+ */
 #define I2S_TFR_WCP(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WCP_SHIFT)) & I2S_TFR_WCP_MASK)
 /*! @} */
 
@@ -12553,6 +19453,10 @@ typedef struct {
 /*! @{ */
 #define I2S_TMR_TWM_MASK                         (0xFFFFFFFFU)
 #define I2S_TMR_TWM_SHIFT                        (0U)
+/*! TWM - Transmit Word Mask
+ *  0b00000000000000000000000000000000..Word N is enabled.
+ *  0b00000000000000000000000000000001..Word N is masked. The transmit data pins are tri-stated or drive zero when masked.
+ */
 #define I2S_TMR_TWM(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK)
 /*! @} */
 
@@ -12560,57 +19464,129 @@ typedef struct {
 /*! @{ */
 #define I2S_RCSR_FRDE_MASK                       (0x1U)
 #define I2S_RCSR_FRDE_SHIFT                      (0U)
+/*! FRDE - FIFO Request DMA Enable
+ *  0b0..Disables the DMA request.
+ *  0b1..Enables the DMA request.
+ */
 #define I2S_RCSR_FRDE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK)
 #define I2S_RCSR_FWDE_MASK                       (0x2U)
 #define I2S_RCSR_FWDE_SHIFT                      (1U)
+/*! FWDE - FIFO Warning DMA Enable
+ *  0b0..Disables the DMA request.
+ *  0b1..Enables the DMA request.
+ */
 #define I2S_RCSR_FWDE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK)
 #define I2S_RCSR_FRIE_MASK                       (0x100U)
 #define I2S_RCSR_FRIE_SHIFT                      (8U)
+/*! FRIE - FIFO Request Interrupt Enable
+ *  0b0..Disables the interrupt.
+ *  0b1..Enables the interrupt.
+ */
 #define I2S_RCSR_FRIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK)
 #define I2S_RCSR_FWIE_MASK                       (0x200U)
 #define I2S_RCSR_FWIE_SHIFT                      (9U)
+/*! FWIE - FIFO Warning Interrupt Enable
+ *  0b0..Disables the interrupt.
+ *  0b1..Enables the interrupt.
+ */
 #define I2S_RCSR_FWIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK)
 #define I2S_RCSR_FEIE_MASK                       (0x400U)
 #define I2S_RCSR_FEIE_SHIFT                      (10U)
+/*! FEIE - FIFO Error Interrupt Enable
+ *  0b0..Disables the interrupt.
+ *  0b1..Enables the interrupt.
+ */
 #define I2S_RCSR_FEIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK)
 #define I2S_RCSR_SEIE_MASK                       (0x800U)
 #define I2S_RCSR_SEIE_SHIFT                      (11U)
+/*! SEIE - Sync Error Interrupt Enable
+ *  0b0..Disables interrupt.
+ *  0b1..Enables interrupt.
+ */
 #define I2S_RCSR_SEIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK)
 #define I2S_RCSR_WSIE_MASK                       (0x1000U)
 #define I2S_RCSR_WSIE_SHIFT                      (12U)
+/*! WSIE - Word Start Interrupt Enable
+ *  0b0..Disables interrupt.
+ *  0b1..Enables interrupt.
+ */
 #define I2S_RCSR_WSIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK)
 #define I2S_RCSR_FRF_MASK                        (0x10000U)
 #define I2S_RCSR_FRF_SHIFT                       (16U)
+/*! FRF - FIFO Request Flag
+ *  0b0..Receive FIFO watermark not reached.
+ *  0b1..Receive FIFO watermark has been reached.
+ */
 #define I2S_RCSR_FRF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK)
 #define I2S_RCSR_FWF_MASK                        (0x20000U)
 #define I2S_RCSR_FWF_SHIFT                       (17U)
+/*! FWF - FIFO Warning Flag
+ *  0b0..No enabled receive FIFO is full.
+ *  0b1..Enabled receive FIFO is full.
+ */
 #define I2S_RCSR_FWF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK)
 #define I2S_RCSR_FEF_MASK                        (0x40000U)
 #define I2S_RCSR_FEF_SHIFT                       (18U)
+/*! FEF - FIFO Error Flag
+ *  0b0..Receive overflow not detected.
+ *  0b1..Receive overflow detected.
+ */
 #define I2S_RCSR_FEF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK)
 #define I2S_RCSR_SEF_MASK                        (0x80000U)
 #define I2S_RCSR_SEF_SHIFT                       (19U)
+/*! SEF - Sync Error Flag
+ *  0b0..Sync error not detected.
+ *  0b1..Frame sync error detected.
+ */
 #define I2S_RCSR_SEF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK)
 #define I2S_RCSR_WSF_MASK                        (0x100000U)
 #define I2S_RCSR_WSF_SHIFT                       (20U)
+/*! WSF - Word Start Flag
+ *  0b0..Start of word not detected.
+ *  0b1..Start of word detected.
+ */
 #define I2S_RCSR_WSF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK)
 #define I2S_RCSR_SR_MASK                         (0x1000000U)
 #define I2S_RCSR_SR_SHIFT                        (24U)
+/*! SR - Software Reset
+ *  0b0..No effect.
+ *  0b1..Software reset.
+ */
 #define I2S_RCSR_SR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK)
 #define I2S_RCSR_FR_MASK                         (0x2000000U)
 #define I2S_RCSR_FR_SHIFT                        (25U)
+/*! FR - FIFO Reset
+ *  0b0..No effect.
+ *  0b1..FIFO reset.
+ */
 #define I2S_RCSR_FR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK)
 #define I2S_RCSR_BCE_MASK                        (0x10000000U)
 #define I2S_RCSR_BCE_SHIFT                       (28U)
+/*! BCE - Bit Clock Enable
+ *  0b0..Receive bit clock is disabled.
+ *  0b1..Receive bit clock is enabled.
+ */
 #define I2S_RCSR_BCE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK)
 #define I2S_RCSR_DBGE_MASK                       (0x20000000U)
 #define I2S_RCSR_DBGE_SHIFT                      (29U)
+/*! DBGE - Debug Enable
+ *  0b0..Receiver is disabled in Debug mode, after completing the current frame.
+ *  0b1..Receiver is enabled in Debug mode.
+ */
 #define I2S_RCSR_DBGE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK)
 #define I2S_RCSR_STOPE_MASK                      (0x40000000U)
 #define I2S_RCSR_STOPE_SHIFT                     (30U)
+/*! STOPE - Stop Enable
+ *  0b0..Receiver disabled in Stop mode.
+ *  0b1..Receiver enabled in Stop mode.
+ */
 #define I2S_RCSR_STOPE(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK)
 #define I2S_RCSR_RE_MASK                         (0x80000000U)
 #define I2S_RCSR_RE_SHIFT                        (31U)
+/*! RE - Receiver Enable
+ *  0b0..Receiver is disabled.
+ *  0b1..Receiver is enabled, or receiver has been disabled and has not yet reached end of frame.
+ */
 #define I2S_RCSR_RE(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK)
 /*! @} */
 
@@ -12628,21 +19604,49 @@ typedef struct {
 #define I2S_RCR2_DIV(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK)
 #define I2S_RCR2_BCD_MASK                        (0x1000000U)
 #define I2S_RCR2_BCD_SHIFT                       (24U)
+/*! BCD - Bit Clock Direction
+ *  0b0..Bit clock is generated externally in Slave mode.
+ *  0b1..Bit clock is generated internally in Master mode.
+ */
 #define I2S_RCR2_BCD(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK)
 #define I2S_RCR2_BCP_MASK                        (0x2000000U)
 #define I2S_RCR2_BCP_SHIFT                       (25U)
+/*! BCP - Bit Clock Polarity
+ *  0b0..Bit Clock is active high with drive outputs on rising edge and sample inputs on falling edge.
+ *  0b1..Bit Clock is active low with drive outputs on falling edge and sample inputs on rising edge.
+ */
 #define I2S_RCR2_BCP(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK)
 #define I2S_RCR2_MSEL_MASK                       (0xC000000U)
 #define I2S_RCR2_MSEL_SHIFT                      (26U)
+/*! MSEL - MCLK Select
+ *  0b00..Bus Clock selected.
+ *  0b01..Master Clock (MCLK) 1 option selected.
+ *  0b10..Master Clock (MCLK) 2 option selected.
+ *  0b11..Master Clock (MCLK) 3 option selected.
+ */
 #define I2S_RCR2_MSEL(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK)
 #define I2S_RCR2_BCI_MASK                        (0x10000000U)
 #define I2S_RCR2_BCI_SHIFT                       (28U)
+/*! BCI - Bit Clock Input
+ *  0b0..No effect.
+ *  0b1..Internal logic is clocked as if bit clock was externally generated.
+ */
 #define I2S_RCR2_BCI(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK)
 #define I2S_RCR2_BCS_MASK                        (0x20000000U)
 #define I2S_RCR2_BCS_SHIFT                       (29U)
+/*! BCS - Bit Clock Swap
+ *  0b0..Use the normal bit clock source.
+ *  0b1..Swap the bit clock source.
+ */
 #define I2S_RCR2_BCS(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK)
 #define I2S_RCR2_SYNC_MASK                       (0xC0000000U)
 #define I2S_RCR2_SYNC_SHIFT                      (30U)
+/*! SYNC - Synchronous Mode
+ *  0b00..Asynchronous mode.
+ *  0b01..Synchronous with transmitter.
+ *  0b10..Reserved.
+ *  0b11..Reserved.
+ */
 #define I2S_RCR2_SYNC(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK)
 /*! @} */
 
@@ -12651,9 +19655,9 @@ typedef struct {
 #define I2S_RCR3_WDFL_MASK                       (0x1FU)
 #define I2S_RCR3_WDFL_SHIFT                      (0U)
 #define I2S_RCR3_WDFL(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK)
-#define I2S_RCR3_RCE_MASK                        (0xF0000U)
+#define I2S_RCR3_RCE_MASK                        (0xF0000U)  /* Merged from fields with different position or width, of widths (1, 4), largest definition used */
 #define I2S_RCR3_RCE_SHIFT                       (16U)
-#define I2S_RCR3_RCE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK)
+#define I2S_RCR3_RCE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK)  /* Merged from fields with different position or width, of widths (1, 4), largest definition used */
 #define I2S_RCR3_CFR_MASK                        (0xF000000U)
 #define I2S_RCR3_CFR_SHIFT                       (24U)
 #define I2S_RCR3_CFR(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_CFR_SHIFT)) & I2S_RCR3_CFR_MASK)
@@ -12663,18 +19667,38 @@ typedef struct {
 /*! @{ */
 #define I2S_RCR4_FSD_MASK                        (0x1U)
 #define I2S_RCR4_FSD_SHIFT                       (0U)
+/*! FSD - Frame Sync Direction
+ *  0b0..Frame Sync is generated externally in Slave mode.
+ *  0b1..Frame Sync is generated internally in Master mode.
+ */
 #define I2S_RCR4_FSD(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK)
 #define I2S_RCR4_FSP_MASK                        (0x2U)
 #define I2S_RCR4_FSP_SHIFT                       (1U)
+/*! FSP - Frame Sync Polarity
+ *  0b0..Frame sync is active high.
+ *  0b1..Frame sync is active low.
+ */
 #define I2S_RCR4_FSP(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK)
 #define I2S_RCR4_ONDEM_MASK                      (0x4U)
 #define I2S_RCR4_ONDEM_SHIFT                     (2U)
+/*! ONDEM - On Demand Mode
+ *  0b0..Internal frame sync is generated continuously.
+ *  0b1..Internal frame sync is generated when the FIFO warning flag is clear.
+ */
 #define I2S_RCR4_ONDEM(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_ONDEM_SHIFT)) & I2S_RCR4_ONDEM_MASK)
 #define I2S_RCR4_FSE_MASK                        (0x8U)
 #define I2S_RCR4_FSE_SHIFT                       (3U)
+/*! FSE - Frame Sync Early
+ *  0b0..Frame sync asserts with the first bit of the frame.
+ *  0b1..Frame sync asserts one bit before the first bit of the frame.
+ */
 #define I2S_RCR4_FSE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK)
 #define I2S_RCR4_MF_MASK                         (0x10U)
 #define I2S_RCR4_MF_SHIFT                        (4U)
+/*! MF - MSB First
+ *  0b0..LSB is received first.
+ *  0b1..MSB is received first.
+ */
 #define I2S_RCR4_MF(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK)
 #define I2S_RCR4_SYWD_MASK                       (0x1F00U)
 #define I2S_RCR4_SYWD_SHIFT                      (8U)
@@ -12684,12 +19708,28 @@ typedef struct {
 #define I2S_RCR4_FRSZ(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK)
 #define I2S_RCR4_FPACK_MASK                      (0x3000000U)
 #define I2S_RCR4_FPACK_SHIFT                     (24U)
+/*! FPACK - FIFO Packing Mode
+ *  0b00..FIFO packing is disabled
+ *  0b01..Reserved.
+ *  0b10..8-bit FIFO packing is enabled
+ *  0b11..16-bit FIFO packing is enabled
+ */
 #define I2S_RCR4_FPACK(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FPACK_SHIFT)) & I2S_RCR4_FPACK_MASK)
 #define I2S_RCR4_FCOMB_MASK                      (0xC000000U)
 #define I2S_RCR4_FCOMB_SHIFT                     (26U)
+/*! FCOMB - FIFO Combine Mode
+ *  0b00..FIFO combine mode disabled.
+ *  0b01..FIFO combine mode enabled on FIFO writes (from receive shift registers).
+ *  0b10..FIFO combine mode enabled on FIFO reads (by software).
+ *  0b11..FIFO combine mode enabled on FIFO writes (from receive shift registers) and reads (by software).
+ */
 #define I2S_RCR4_FCOMB(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCOMB_SHIFT)) & I2S_RCR4_FCOMB_MASK)
 #define I2S_RCR4_FCONT_MASK                      (0x10000000U)
 #define I2S_RCR4_FCONT_SHIFT                     (28U)
+/*! FCONT - FIFO Continue on Error
+ *  0b0..On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared.
+ *  0b1..On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared.
+ */
 #define I2S_RCR4_FCONT(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCONT_SHIFT)) & I2S_RCR4_FCONT_MASK)
 /*! @} */
 
@@ -12723,6 +19763,10 @@ typedef struct {
 #define I2S_RFR_RFP(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RFP_SHIFT)) & I2S_RFR_RFP_MASK)
 #define I2S_RFR_RCP_MASK                         (0x8000U)
 #define I2S_RFR_RCP_SHIFT                        (15U)
+/*! RCP - Receive Channel Pointer
+ *  0b0..No effect.
+ *  0b1..FIFO combine is enabled for FIFO reads and this FIFO will be read on the next FIFO read.
+ */
 #define I2S_RFR_RCP(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RCP_SHIFT)) & I2S_RFR_RCP_MASK)
 #define I2S_RFR_WFP_MASK                         (0x3F0000U)
 #define I2S_RFR_WFP_SHIFT                        (16U)
@@ -12736,6 +19780,10 @@ typedef struct {
 /*! @{ */
 #define I2S_RMR_RWM_MASK                         (0xFFFFFFFFU)
 #define I2S_RMR_RWM_SHIFT                        (0U)
+/*! RWM - Receive Word Mask
+ *  0b00000000000000000000000000000000..Word N is enabled.
+ *  0b00000000000000000000000000000001..Word N is masked.
+ */
 #define I2S_RMR_RWM(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK)
 /*! @} */
 
@@ -12801,9 +19849,21 @@ typedef struct {
 /*! @{ */
 #define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_MASK      (0x7U)
 #define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_SHIFT     (0U)
+/*! MUX_MODE - MUX Mode Select Field.
+ *  0b000..Select mux mode: ALT0 mux port: SEMC_DATA00 of instance: semc
+ *  0b001..Select mux mode: ALT1 mux port: FLEXPWM4_PWMA00 of instance: flexpwm4
+ *  0b010..Select mux mode: ALT2 mux port: LPSPI2_SCK of instance: lpspi2
+ *  0b011..Select mux mode: ALT3 mux port: XBAR1_XBAR_IN02 of instance: xbar1
+ *  0b100..Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO00 of instance: flexio1
+ *  0b101..Select mux mode: ALT5 mux port: GPIO4_IO00 of instance: gpio4
+ */
 #define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_MASK)
 #define IOMUXC_SW_MUX_CTL_PAD_SION_MASK          (0x10U)
 #define IOMUXC_SW_MUX_CTL_PAD_SION_SHIFT         (4U)
+/*! SION - Software Input On Field.
+ *  0b1..Force input path of pad GPIO_EMC_00
+ *  0b0..Input Path is determined by functionality
+ */
 #define IOMUXC_SW_MUX_CTL_PAD_SION(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_SION_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_SION_MASK)
 /*! @} */
 
@@ -12814,27 +19874,69 @@ typedef struct {
 /*! @{ */
 #define IOMUXC_SW_PAD_CTL_PAD_SRE_MASK           (0x1U)
 #define IOMUXC_SW_PAD_CTL_PAD_SRE_SHIFT          (0U)
+/*! SRE - Slew Rate Field
+ *  0b0..Slow Slew Rate
+ *  0b1..Fast Slew Rate
+ */
 #define IOMUXC_SW_PAD_CTL_PAD_SRE(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_SRE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_SRE_MASK)
 #define IOMUXC_SW_PAD_CTL_PAD_DSE_MASK           (0x38U)
 #define IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT          (3U)
+/*! DSE - Drive Strength Field
+ *  0b000..output driver disabled;
+ *  0b001..R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)
+ *  0b010..R0/2
+ *  0b011..R0/3
+ *  0b100..R0/4
+ *  0b101..R0/5
+ *  0b110..R0/6
+ *  0b111..R0/7
+ */
 #define IOMUXC_SW_PAD_CTL_PAD_DSE(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DSE_MASK)
 #define IOMUXC_SW_PAD_CTL_PAD_SPEED_MASK         (0xC0U)
 #define IOMUXC_SW_PAD_CTL_PAD_SPEED_SHIFT        (6U)
+/*! SPEED - Speed Field
+ *  0b00..low(50MHz)
+ *  0b01..medium(100MHz)
+ *  0b10..medium(100MHz)
+ *  0b11..max(200MHz)
+ */
 #define IOMUXC_SW_PAD_CTL_PAD_SPEED(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_SPEED_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_SPEED_MASK)
 #define IOMUXC_SW_PAD_CTL_PAD_ODE_MASK           (0x800U)
 #define IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT          (11U)
+/*! ODE - Open Drain Enable Field
+ *  0b0..Open Drain Disabled
+ *  0b1..Open Drain Enabled
+ */
 #define IOMUXC_SW_PAD_CTL_PAD_ODE(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_ODE_MASK)
 #define IOMUXC_SW_PAD_CTL_PAD_PKE_MASK           (0x1000U)
 #define IOMUXC_SW_PAD_CTL_PAD_PKE_SHIFT          (12U)
+/*! PKE - Pull / Keep Enable Field
+ *  0b0..Pull/Keeper Disabled
+ *  0b1..Pull/Keeper Enabled
+ */
 #define IOMUXC_SW_PAD_CTL_PAD_PKE(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PKE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PKE_MASK)
 #define IOMUXC_SW_PAD_CTL_PAD_PUE_MASK           (0x2000U)
 #define IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT          (13U)
+/*! PUE - Pull / Keep Select Field
+ *  0b0..Keeper
+ *  0b1..Pull
+ */
 #define IOMUXC_SW_PAD_CTL_PAD_PUE(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PUE_MASK)
 #define IOMUXC_SW_PAD_CTL_PAD_PUS_MASK           (0xC000U)
 #define IOMUXC_SW_PAD_CTL_PAD_PUS_SHIFT          (14U)
+/*! PUS - Pull Up / Down Config. Field
+ *  0b00..100K Ohm Pull Down
+ *  0b01..47K Ohm Pull Up
+ *  0b10..100K Ohm Pull Up
+ *  0b11..22K Ohm Pull Up
+ */
 #define IOMUXC_SW_PAD_CTL_PAD_PUS(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PUS_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PUS_MASK)
 #define IOMUXC_SW_PAD_CTL_PAD_HYS_MASK           (0x10000U)
 #define IOMUXC_SW_PAD_CTL_PAD_HYS_SHIFT          (16U)
+/*! HYS - Hyst. Enable Field
+ *  0b0..Hysteresis Disabled
+ *  0b1..Hysteresis Enabled
+ */
 #define IOMUXC_SW_PAD_CTL_PAD_HYS(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_HYS_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_HYS_MASK)
 /*! @} */
 
@@ -12845,6 +19947,10 @@ typedef struct {
 /*! @{ */
 #define IOMUXC_SELECT_INPUT_DAISY_MASK           (0x7U)  /* Merged from fields with different position or width, of widths (1, 2, 3), largest definition used */
 #define IOMUXC_SELECT_INPUT_DAISY_SHIFT          (0U)
+/*! DAISY - Selecting Pads Involved in Daisy Chain.
+ *  0b0..Selecting Pad: GPIO_AD_B0_01 for Mode: ALT3
+ *  0b1..Selecting Pad: GPIO_AD_B1_02 for Mode: ALT0
+ */
 #define IOMUXC_SELECT_INPUT_DAISY(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_SELECT_INPUT_DAISY_SHIFT)) & IOMUXC_SELECT_INPUT_DAISY_MASK)  /* Merged from fields with different position or width, of widths (1, 2, 3), largest definition used */
 /*! @} */
 
@@ -12924,48 +20030,127 @@ typedef struct {
 /*! @{ */
 #define IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_MASK      (0x7U)
 #define IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_SHIFT     (0U)
+/*! SAI1_MCLK1_SEL
+ *  0b000..ccm.ssi1_clk_root
+ *  0b001..ccm.ssi2_clk_root
+ *  0b010..ccm.ssi3_clk_root
+ *  0b011..iomux.sai1_ipg_clk_sai_mclk
+ *  0b100..iomux.sai2_ipg_clk_sai_mclk
+ *  0b101..iomux.sai3_ipg_clk_sai_mclk
+ *  0b110..Reserved
+ *  0b111..Reserved
+ */
 #define IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_MASK)
 #define IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_MASK      (0x38U)
 #define IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_SHIFT     (3U)
+/*! SAI1_MCLK2_SEL
+ *  0b000..ccm.ssi1_clk_root
+ *  0b001..ccm.ssi2_clk_root
+ *  0b010..ccm.ssi3_clk_root
+ *  0b011..iomux.sai1_ipg_clk_sai_mclk
+ *  0b100..iomux.sai2_ipg_clk_sai_mclk
+ *  0b101..iomux.sai3_ipg_clk_sai_mclk
+ *  0b110..Reserved
+ *  0b111..Reserved
+ */
 #define IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_MASK)
 #define IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_MASK      (0xC0U)
 #define IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_SHIFT     (6U)
+/*! SAI1_MCLK3_SEL
+ *  0b00..ccm.spdif0_clk_root
+ *  0b01..iomux.spdif_tx_clk2
+ *  0b10..spdif.spdif_srclk
+ *  0b11..spdif.spdif_outclock
+ */
 #define IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_MASK)
 #define IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK      (0x300U)
 #define IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_SHIFT     (8U)
+/*! SAI2_MCLK3_SEL
+ *  0b00..ccm.spdif0_clk_root
+ *  0b01..iomux.spdif_tx_clk2
+ *  0b10..spdif.spdif_srclk
+ *  0b11..spdif.spdif_outclock
+ */
 #define IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK)
 #define IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_MASK      (0xC00U)
 #define IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_SHIFT     (10U)
+/*! SAI3_MCLK3_SEL
+ *  0b00..ccm.spdif0_clk_root
+ *  0b01..iomux.spdif_tx_clk2
+ *  0b10..spdif.spdif_srclk
+ *  0b11..spdif.spdif_outclock
+ */
 #define IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_MASK)
 #define IOMUXC_GPR_GPR1_GINT_MASK                (0x1000U)
 #define IOMUXC_GPR_GPR1_GINT_SHIFT               (12U)
+/*! GINT
+ *  0b0..Global interrupt request is not asserted.
+ *  0b1..Global interrupt request is asserted.
+ */
 #define IOMUXC_GPR_GPR1_GINT(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_GINT_SHIFT)) & IOMUXC_GPR_GPR1_GINT_MASK)
 #define IOMUXC_GPR_GPR1_ENET1_CLK_SEL_MASK       (0x2000U)
 #define IOMUXC_GPR_GPR1_ENET1_CLK_SEL_SHIFT      (13U)
+/*! ENET1_CLK_SEL
+ *  0b0..ENET1 TX reference clock driven by ref_enetpll0. This clock is also output to pins via the IOMUX. ENET_REF_CLK1 function.
+ *  0b1..Gets ENET1 TX reference clock from the ENET1_TX_CLK pin. In this use case, an external OSC provides the
+ *       clock for both the external PHY and the internal controller.
+ */
 #define IOMUXC_GPR_GPR1_ENET1_CLK_SEL(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ENET1_CLK_SEL_SHIFT)) & IOMUXC_GPR_GPR1_ENET1_CLK_SEL_MASK)
 #define IOMUXC_GPR_GPR1_USB_EXP_MODE_MASK        (0x8000U)
 #define IOMUXC_GPR_GPR1_USB_EXP_MODE_SHIFT       (15U)
+/*! USB_EXP_MODE
+ *  0b0..Exposure mode is disabled.
+ *  0b1..Exposure mode is enabled.
+ */
 #define IOMUXC_GPR_GPR1_USB_EXP_MODE(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_USB_EXP_MODE_SHIFT)) & IOMUXC_GPR_GPR1_USB_EXP_MODE_MASK)
 #define IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK    (0x20000U)
 #define IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_SHIFT   (17U)
+/*! ENET1_TX_CLK_DIR
+ *  0b0..ENET1_TX_CLK output driver is disabled and ENET_REF_CLK1 is a clock input.
+ *  0b1..ENET1_TX_CLK output driver is enabled and ENET_REF_CLK1 is an output driven by ref_enetpll0.
+ */
 #define IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK)
 #define IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_MASK       (0x80000U)
 #define IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_SHIFT      (19U)
+/*! SAI1_MCLK_DIR
+ *  0b0..sai1.MCLK is input signal
+ *  0b1..sai1.MCLK is output signal
+ */
 #define IOMUXC_GPR_GPR1_SAI1_MCLK_DIR(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_MASK)
 #define IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_MASK       (0x100000U)
 #define IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_SHIFT      (20U)
+/*! SAI2_MCLK_DIR
+ *  0b0..sai2.MCLK is input signal
+ *  0b1..sai2.MCLK is output signal
+ */
 #define IOMUXC_GPR_GPR1_SAI2_MCLK_DIR(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_MASK)
 #define IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_MASK       (0x200000U)
 #define IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_SHIFT      (21U)
+/*! SAI3_MCLK_DIR
+ *  0b0..sai3.MCLK is input signal
+ *  0b1..sai3.MCLK is output signal
+ */
 #define IOMUXC_GPR_GPR1_SAI3_MCLK_DIR(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_MASK)
 #define IOMUXC_GPR_GPR1_EXC_MON_MASK             (0x400000U)
 #define IOMUXC_GPR_GPR1_EXC_MON_SHIFT            (22U)
+/*! EXC_MON
+ *  0b0..OKAY response
+ *  0b1..SLVError response
+ */
 #define IOMUXC_GPR_GPR1_EXC_MON(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_EXC_MON_SHIFT)) & IOMUXC_GPR_GPR1_EXC_MON_MASK)
 #define IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN_MASK   (0x800000U)
 #define IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN_SHIFT  (23U)
+/*! ENET_IPG_CLK_S_EN
+ *  0b0..ipg_clk_s is gated when there is no IPS access
+ *  0b1..ipg_clk_s is always on
+ */
 #define IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN_SHIFT)) & IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN_MASK)
 #define IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_MASK   (0x80000000U)
 #define IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_SHIFT  (31U)
+/*! CM7_FORCE_HCLK_EN
+ *  0b0..AHB clock is not running (gated)
+ *  0b1..AHB clock is running (enabled)
+ */
 #define IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_SHIFT)) & IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_MASK)
 /*! @} */
 
@@ -12973,33 +20158,327 @@ typedef struct {
 /*! @{ */
 #define IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_MASK (0x1000U)
 #define IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_SHIFT (12U)
+/*! L2_MEM_EN_POWERSAVING
+ *  0b0..none memory power saving features enabled, SHUTDOWN/DEEPSLEEP/LIGHTSLEEP will have no effect
+ *  0b1..memory power saving features enabled, set SHUTDOWN/DEEPSLEEP/LIGHTSLEEP(priority high to low) to enable power saving levels
+ */
 #define IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_SHIFT)) & IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_MASK)
 #define IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_MASK    (0x4000U)
 #define IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_SHIFT   (14U)
+/*! L2_MEM_DEEPSLEEP
+ *  0b0..no force sleep control supported, memory deep sleep mode only entered when whole system in stop mode
+ *  0b1..force memory into deep sleep mode
+ */
 #define IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_SHIFT)) & IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_MASK)
 #define IOMUXC_GPR_GPR2_MQS_CLK_DIV_MASK         (0xFF0000U)
 #define IOMUXC_GPR_GPR2_MQS_CLK_DIV_SHIFT        (16U)
+/*! MQS_CLK_DIV - Divider ratio control for mclk from hmclk. mclk frequency = 1/(n+1) * hmclk frequency.
+ *  0b00000000..mclk frequency = 1/1 * hmclk frequency
+ *  0b00000001..mclk frequency = 1/2 * hmclk frequency
+ *  0b00000010..mclk frequency = 1/3 * hmclk frequency
+ *  0b00000011..mclk frequency = 1/4 * hmclk frequency
+ *  0b00000100..mclk frequency = 1/5 * hmclk frequency
+ *  0b00000101..mclk frequency = 1/6 * hmclk frequency
+ *  0b00000110..mclk frequency = 1/7 * hmclk frequency
+ *  0b00000111..mclk frequency = 1/8 * hmclk frequency
+ *  0b00001000..mclk frequency = 1/9 * hmclk frequency
+ *  0b00001001..mclk frequency = 1/10 * hmclk frequency
+ *  0b00001010..mclk frequency = 1/11 * hmclk frequency
+ *  0b00001011..mclk frequency = 1/12 * hmclk frequency
+ *  0b00001100..mclk frequency = 1/13 * hmclk frequency
+ *  0b00001101..mclk frequency = 1/14 * hmclk frequency
+ *  0b00001110..mclk frequency = 1/15 * hmclk frequency
+ *  0b00001111..mclk frequency = 1/16 * hmclk frequency
+ *  0b00010000..mclk frequency = 1/17 * hmclk frequency
+ *  0b00010001..mclk frequency = 1/18 * hmclk frequency
+ *  0b00010010..mclk frequency = 1/19 * hmclk frequency
+ *  0b00010011..mclk frequency = 1/20 * hmclk frequency
+ *  0b00010100..mclk frequency = 1/21 * hmclk frequency
+ *  0b00010101..mclk frequency = 1/22 * hmclk frequency
+ *  0b00010110..mclk frequency = 1/23 * hmclk frequency
+ *  0b00010111..mclk frequency = 1/24 * hmclk frequency
+ *  0b00011000..mclk frequency = 1/25 * hmclk frequency
+ *  0b00011001..mclk frequency = 1/26 * hmclk frequency
+ *  0b00011010..mclk frequency = 1/27 * hmclk frequency
+ *  0b00011011..mclk frequency = 1/28 * hmclk frequency
+ *  0b00011100..mclk frequency = 1/29 * hmclk frequency
+ *  0b00011101..mclk frequency = 1/30 * hmclk frequency
+ *  0b00011110..mclk frequency = 1/31 * hmclk frequency
+ *  0b00011111..mclk frequency = 1/32 * hmclk frequency
+ *  0b00100000..mclk frequency = 1/33 * hmclk frequency
+ *  0b00100001..mclk frequency = 1/34 * hmclk frequency
+ *  0b00100010..mclk frequency = 1/35 * hmclk frequency
+ *  0b00100011..mclk frequency = 1/36 * hmclk frequency
+ *  0b00100100..mclk frequency = 1/37 * hmclk frequency
+ *  0b00100101..mclk frequency = 1/38 * hmclk frequency
+ *  0b00100110..mclk frequency = 1/39 * hmclk frequency
+ *  0b00100111..mclk frequency = 1/40 * hmclk frequency
+ *  0b00101000..mclk frequency = 1/41 * hmclk frequency
+ *  0b00101001..mclk frequency = 1/42 * hmclk frequency
+ *  0b00101010..mclk frequency = 1/43 * hmclk frequency
+ *  0b00101011..mclk frequency = 1/44 * hmclk frequency
+ *  0b00101100..mclk frequency = 1/45 * hmclk frequency
+ *  0b00101101..mclk frequency = 1/46 * hmclk frequency
+ *  0b00101110..mclk frequency = 1/47 * hmclk frequency
+ *  0b00101111..mclk frequency = 1/48 * hmclk frequency
+ *  0b00110000..mclk frequency = 1/49 * hmclk frequency
+ *  0b00110001..mclk frequency = 1/50 * hmclk frequency
+ *  0b00110010..mclk frequency = 1/51 * hmclk frequency
+ *  0b00110011..mclk frequency = 1/52 * hmclk frequency
+ *  0b00110100..mclk frequency = 1/53 * hmclk frequency
+ *  0b00110101..mclk frequency = 1/54 * hmclk frequency
+ *  0b00110110..mclk frequency = 1/55 * hmclk frequency
+ *  0b00110111..mclk frequency = 1/56 * hmclk frequency
+ *  0b00111000..mclk frequency = 1/57 * hmclk frequency
+ *  0b00111001..mclk frequency = 1/58 * hmclk frequency
+ *  0b00111010..mclk frequency = 1/59 * hmclk frequency
+ *  0b00111011..mclk frequency = 1/60 * hmclk frequency
+ *  0b00111100..mclk frequency = 1/61 * hmclk frequency
+ *  0b00111101..mclk frequency = 1/62 * hmclk frequency
+ *  0b00111110..mclk frequency = 1/63 * hmclk frequency
+ *  0b00111111..mclk frequency = 1/64 * hmclk frequency
+ *  0b01000000..mclk frequency = 1/65 * hmclk frequency
+ *  0b01000001..mclk frequency = 1/66 * hmclk frequency
+ *  0b01000010..mclk frequency = 1/67 * hmclk frequency
+ *  0b01000011..mclk frequency = 1/68 * hmclk frequency
+ *  0b01000100..mclk frequency = 1/69 * hmclk frequency
+ *  0b01000101..mclk frequency = 1/70 * hmclk frequency
+ *  0b01000110..mclk frequency = 1/71 * hmclk frequency
+ *  0b01000111..mclk frequency = 1/72 * hmclk frequency
+ *  0b01001000..mclk frequency = 1/73 * hmclk frequency
+ *  0b01001001..mclk frequency = 1/74 * hmclk frequency
+ *  0b01001010..mclk frequency = 1/75 * hmclk frequency
+ *  0b01001011..mclk frequency = 1/76 * hmclk frequency
+ *  0b01001100..mclk frequency = 1/77 * hmclk frequency
+ *  0b01001101..mclk frequency = 1/78 * hmclk frequency
+ *  0b01001110..mclk frequency = 1/79 * hmclk frequency
+ *  0b01001111..mclk frequency = 1/80 * hmclk frequency
+ *  0b01010000..mclk frequency = 1/81 * hmclk frequency
+ *  0b01010001..mclk frequency = 1/82 * hmclk frequency
+ *  0b01010010..mclk frequency = 1/83 * hmclk frequency
+ *  0b01010011..mclk frequency = 1/84 * hmclk frequency
+ *  0b01010100..mclk frequency = 1/85 * hmclk frequency
+ *  0b01010101..mclk frequency = 1/86 * hmclk frequency
+ *  0b01010110..mclk frequency = 1/87 * hmclk frequency
+ *  0b01010111..mclk frequency = 1/88 * hmclk frequency
+ *  0b01011000..mclk frequency = 1/89 * hmclk frequency
+ *  0b01011001..mclk frequency = 1/90 * hmclk frequency
+ *  0b01011010..mclk frequency = 1/91 * hmclk frequency
+ *  0b01011011..mclk frequency = 1/92 * hmclk frequency
+ *  0b01011100..mclk frequency = 1/93 * hmclk frequency
+ *  0b01011101..mclk frequency = 1/94 * hmclk frequency
+ *  0b01011110..mclk frequency = 1/95 * hmclk frequency
+ *  0b01011111..mclk frequency = 1/96 * hmclk frequency
+ *  0b01100000..mclk frequency = 1/97 * hmclk frequency
+ *  0b01100001..mclk frequency = 1/98 * hmclk frequency
+ *  0b01100010..mclk frequency = 1/99 * hmclk frequency
+ *  0b01100011..mclk frequency = 1/100 * hmclk frequency
+ *  0b01100100..mclk frequency = 1/101 * hmclk frequency
+ *  0b01100101..mclk frequency = 1/102 * hmclk frequency
+ *  0b01100110..mclk frequency = 1/103 * hmclk frequency
+ *  0b01100111..mclk frequency = 1/104 * hmclk frequency
+ *  0b01101000..mclk frequency = 1/105 * hmclk frequency
+ *  0b01101001..mclk frequency = 1/106 * hmclk frequency
+ *  0b01101010..mclk frequency = 1/107 * hmclk frequency
+ *  0b01101011..mclk frequency = 1/108 * hmclk frequency
+ *  0b01101100..mclk frequency = 1/109 * hmclk frequency
+ *  0b01101101..mclk frequency = 1/110 * hmclk frequency
+ *  0b01101110..mclk frequency = 1/111 * hmclk frequency
+ *  0b01101111..mclk frequency = 1/112 * hmclk frequency
+ *  0b01110000..mclk frequency = 1/113 * hmclk frequency
+ *  0b01110001..mclk frequency = 1/114 * hmclk frequency
+ *  0b01110010..mclk frequency = 1/115 * hmclk frequency
+ *  0b01110011..mclk frequency = 1/116 * hmclk frequency
+ *  0b01110100..mclk frequency = 1/117 * hmclk frequency
+ *  0b01110101..mclk frequency = 1/118 * hmclk frequency
+ *  0b01110110..mclk frequency = 1/119 * hmclk frequency
+ *  0b01110111..mclk frequency = 1/120 * hmclk frequency
+ *  0b01111000..mclk frequency = 1/121 * hmclk frequency
+ *  0b01111001..mclk frequency = 1/122 * hmclk frequency
+ *  0b01111010..mclk frequency = 1/123 * hmclk frequency
+ *  0b01111011..mclk frequency = 1/124 * hmclk frequency
+ *  0b01111100..mclk frequency = 1/125 * hmclk frequency
+ *  0b01111101..mclk frequency = 1/126 * hmclk frequency
+ *  0b01111110..mclk frequency = 1/127 * hmclk frequency
+ *  0b01111111..mclk frequency = 1/128 * hmclk frequency
+ *  0b10000000..mclk frequency = 1/129 * hmclk frequency
+ *  0b10000001..mclk frequency = 1/130 * hmclk frequency
+ *  0b10000010..mclk frequency = 1/131 * hmclk frequency
+ *  0b10000011..mclk frequency = 1/132 * hmclk frequency
+ *  0b10000100..mclk frequency = 1/133 * hmclk frequency
+ *  0b10000101..mclk frequency = 1/134 * hmclk frequency
+ *  0b10000110..mclk frequency = 1/135 * hmclk frequency
+ *  0b10000111..mclk frequency = 1/136 * hmclk frequency
+ *  0b10001000..mclk frequency = 1/137 * hmclk frequency
+ *  0b10001001..mclk frequency = 1/138 * hmclk frequency
+ *  0b10001010..mclk frequency = 1/139 * hmclk frequency
+ *  0b10001011..mclk frequency = 1/140 * hmclk frequency
+ *  0b10001100..mclk frequency = 1/141 * hmclk frequency
+ *  0b10001101..mclk frequency = 1/142 * hmclk frequency
+ *  0b10001110..mclk frequency = 1/143 * hmclk frequency
+ *  0b10001111..mclk frequency = 1/144 * hmclk frequency
+ *  0b10010000..mclk frequency = 1/145 * hmclk frequency
+ *  0b10010001..mclk frequency = 1/146 * hmclk frequency
+ *  0b10010010..mclk frequency = 1/147 * hmclk frequency
+ *  0b10010011..mclk frequency = 1/148 * hmclk frequency
+ *  0b10010100..mclk frequency = 1/149 * hmclk frequency
+ *  0b10010101..mclk frequency = 1/150 * hmclk frequency
+ *  0b10010110..mclk frequency = 1/151 * hmclk frequency
+ *  0b10010111..mclk frequency = 1/152 * hmclk frequency
+ *  0b10011000..mclk frequency = 1/153 * hmclk frequency
+ *  0b10011001..mclk frequency = 1/154 * hmclk frequency
+ *  0b10011010..mclk frequency = 1/155 * hmclk frequency
+ *  0b10011011..mclk frequency = 1/156 * hmclk frequency
+ *  0b10011100..mclk frequency = 1/157 * hmclk frequency
+ *  0b10011101..mclk frequency = 1/158 * hmclk frequency
+ *  0b10011110..mclk frequency = 1/159 * hmclk frequency
+ *  0b10011111..mclk frequency = 1/160 * hmclk frequency
+ *  0b10100000..mclk frequency = 1/161 * hmclk frequency
+ *  0b10100001..mclk frequency = 1/162 * hmclk frequency
+ *  0b10100010..mclk frequency = 1/163 * hmclk frequency
+ *  0b10100011..mclk frequency = 1/164 * hmclk frequency
+ *  0b10100100..mclk frequency = 1/165 * hmclk frequency
+ *  0b10100101..mclk frequency = 1/166 * hmclk frequency
+ *  0b10100110..mclk frequency = 1/167 * hmclk frequency
+ *  0b10100111..mclk frequency = 1/168 * hmclk frequency
+ *  0b10101000..mclk frequency = 1/169 * hmclk frequency
+ *  0b10101001..mclk frequency = 1/170 * hmclk frequency
+ *  0b10101010..mclk frequency = 1/171 * hmclk frequency
+ *  0b10101011..mclk frequency = 1/172 * hmclk frequency
+ *  0b10101100..mclk frequency = 1/173 * hmclk frequency
+ *  0b10101101..mclk frequency = 1/174 * hmclk frequency
+ *  0b10101110..mclk frequency = 1/175 * hmclk frequency
+ *  0b10101111..mclk frequency = 1/176 * hmclk frequency
+ *  0b10110000..mclk frequency = 1/177 * hmclk frequency
+ *  0b10110001..mclk frequency = 1/178 * hmclk frequency
+ *  0b10110010..mclk frequency = 1/179 * hmclk frequency
+ *  0b10110011..mclk frequency = 1/180 * hmclk frequency
+ *  0b10110100..mclk frequency = 1/181 * hmclk frequency
+ *  0b10110101..mclk frequency = 1/182 * hmclk frequency
+ *  0b10110110..mclk frequency = 1/183 * hmclk frequency
+ *  0b10110111..mclk frequency = 1/184 * hmclk frequency
+ *  0b10111000..mclk frequency = 1/185 * hmclk frequency
+ *  0b10111001..mclk frequency = 1/186 * hmclk frequency
+ *  0b10111010..mclk frequency = 1/187 * hmclk frequency
+ *  0b10111011..mclk frequency = 1/188 * hmclk frequency
+ *  0b10111100..mclk frequency = 1/189 * hmclk frequency
+ *  0b10111101..mclk frequency = 1/190 * hmclk frequency
+ *  0b10111110..mclk frequency = 1/191 * hmclk frequency
+ *  0b10111111..mclk frequency = 1/192 * hmclk frequency
+ *  0b11000000..mclk frequency = 1/193 * hmclk frequency
+ *  0b11000001..mclk frequency = 1/194 * hmclk frequency
+ *  0b11000010..mclk frequency = 1/195 * hmclk frequency
+ *  0b11000011..mclk frequency = 1/196 * hmclk frequency
+ *  0b11000100..mclk frequency = 1/197 * hmclk frequency
+ *  0b11000101..mclk frequency = 1/198 * hmclk frequency
+ *  0b11000110..mclk frequency = 1/199 * hmclk frequency
+ *  0b11000111..mclk frequency = 1/200 * hmclk frequency
+ *  0b11001000..mclk frequency = 1/201 * hmclk frequency
+ *  0b11001001..mclk frequency = 1/202 * hmclk frequency
+ *  0b11001010..mclk frequency = 1/203 * hmclk frequency
+ *  0b11001011..mclk frequency = 1/204 * hmclk frequency
+ *  0b11001100..mclk frequency = 1/205 * hmclk frequency
+ *  0b11001101..mclk frequency = 1/206 * hmclk frequency
+ *  0b11001110..mclk frequency = 1/207 * hmclk frequency
+ *  0b11001111..mclk frequency = 1/208 * hmclk frequency
+ *  0b11010000..mclk frequency = 1/209 * hmclk frequency
+ *  0b11010001..mclk frequency = 1/210 * hmclk frequency
+ *  0b11010010..mclk frequency = 1/211 * hmclk frequency
+ *  0b11010011..mclk frequency = 1/212 * hmclk frequency
+ *  0b11010100..mclk frequency = 1/213 * hmclk frequency
+ *  0b11010101..mclk frequency = 1/214 * hmclk frequency
+ *  0b11010110..mclk frequency = 1/215 * hmclk frequency
+ *  0b11010111..mclk frequency = 1/216 * hmclk frequency
+ *  0b11011000..mclk frequency = 1/217 * hmclk frequency
+ *  0b11011001..mclk frequency = 1/218 * hmclk frequency
+ *  0b11011010..mclk frequency = 1/219 * hmclk frequency
+ *  0b11011011..mclk frequency = 1/220 * hmclk frequency
+ *  0b11011100..mclk frequency = 1/221 * hmclk frequency
+ *  0b11011101..mclk frequency = 1/222 * hmclk frequency
+ *  0b11011110..mclk frequency = 1/223 * hmclk frequency
+ *  0b11011111..mclk frequency = 1/224 * hmclk frequency
+ *  0b11100000..mclk frequency = 1/225 * hmclk frequency
+ *  0b11100001..mclk frequency = 1/226 * hmclk frequency
+ *  0b11100010..mclk frequency = 1/227 * hmclk frequency
+ *  0b11100011..mclk frequency = 1/228 * hmclk frequency
+ *  0b11100100..mclk frequency = 1/229 * hmclk frequency
+ *  0b11100101..mclk frequency = 1/230 * hmclk frequency
+ *  0b11100110..mclk frequency = 1/231 * hmclk frequency
+ *  0b11100111..mclk frequency = 1/232 * hmclk frequency
+ *  0b11101000..mclk frequency = 1/233 * hmclk frequency
+ *  0b11101001..mclk frequency = 1/234 * hmclk frequency
+ *  0b11101010..mclk frequency = 1/235 * hmclk frequency
+ *  0b11101011..mclk frequency = 1/236 * hmclk frequency
+ *  0b11101100..mclk frequency = 1/237 * hmclk frequency
+ *  0b11101101..mclk frequency = 1/238 * hmclk frequency
+ *  0b11101110..mclk frequency = 1/239 * hmclk frequency
+ *  0b11101111..mclk frequency = 1/240 * hmclk frequency
+ *  0b11110000..mclk frequency = 1/241 * hmclk frequency
+ *  0b11110001..mclk frequency = 1/242 * hmclk frequency
+ *  0b11110010..mclk frequency = 1/243 * hmclk frequency
+ *  0b11110011..mclk frequency = 1/244 * hmclk frequency
+ *  0b11110100..mclk frequency = 1/245 * hmclk frequency
+ *  0b11110101..mclk frequency = 1/246 * hmclk frequency
+ *  0b11110110..mclk frequency = 1/247 * hmclk frequency
+ *  0b11110111..mclk frequency = 1/248 * hmclk frequency
+ *  0b11111000..mclk frequency = 1/249 * hmclk frequency
+ *  0b11111001..mclk frequency = 1/250 * hmclk frequency
+ *  0b11111010..mclk frequency = 1/251 * hmclk frequency
+ *  0b11111011..mclk frequency = 1/252 * hmclk frequency
+ *  0b11111100..mclk frequency = 1/253 * hmclk frequency
+ *  0b11111101..mclk frequency = 1/254 * hmclk frequency
+ *  0b11111110..mclk frequency = 1/255 * hmclk frequency
+ *  0b11111111..mclk frequency = 1/256 * hmclk frequency
+ */
 #define IOMUXC_GPR_GPR2_MQS_CLK_DIV(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_CLK_DIV_SHIFT)) & IOMUXC_GPR_GPR2_MQS_CLK_DIV_MASK)
 #define IOMUXC_GPR_GPR2_MQS_SW_RST_MASK          (0x1000000U)
 #define IOMUXC_GPR_GPR2_MQS_SW_RST_SHIFT         (24U)
+/*! MQS_SW_RST
+ *  0b0..Exit software reset for MQS
+ *  0b1..Enable software reset for MQS
+ */
 #define IOMUXC_GPR_GPR2_MQS_SW_RST(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_SW_RST_SHIFT)) & IOMUXC_GPR_GPR2_MQS_SW_RST_MASK)
 #define IOMUXC_GPR_GPR2_MQS_EN_MASK              (0x2000000U)
 #define IOMUXC_GPR_GPR2_MQS_EN_SHIFT             (25U)
+/*! MQS_EN
+ *  0b0..Disable MQS
+ *  0b1..Enable MQS
+ */
 #define IOMUXC_GPR_GPR2_MQS_EN(x)                (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_EN_SHIFT)) & IOMUXC_GPR_GPR2_MQS_EN_MASK)
 #define IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_MASK      (0x4000000U)
 #define IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_SHIFT     (26U)
+/*! MQS_OVERSAMPLE
+ *  0b0..32
+ *  0b1..64
+ */
 #define IOMUXC_GPR_GPR2_MQS_OVERSAMPLE(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_SHIFT)) & IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_MASK)
 #define IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_MASK (0x10000000U)
 #define IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_SHIFT (28U)
+/*! QTIMER1_TMR_CNTS_FREEZE
+ *  0b0..timer counter work normally
+ *  0b1..reset counter and ouput flags
+ */
 #define IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_MASK)
 #define IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_MASK (0x20000000U)
 #define IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_SHIFT (29U)
+/*! QTIMER2_TMR_CNTS_FREEZE
+ *  0b0..timer counter work normally
+ *  0b1..reset counter and ouput flags
+ */
 #define IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_MASK)
 #define IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE_MASK (0x40000000U)
 #define IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE_SHIFT (30U)
+/*! QTIMER3_TMR_CNTS_FREEZE
+ *  0b0..timer counter work normally
+ *  0b1..reset counter and ouput flags
+ */
 #define IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE_MASK)
 #define IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE_MASK (0x80000000U)
 #define IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE_SHIFT (31U)
+/*! QTIMER4_TMR_CNTS_FREEZE
+ *  0b0..timer counter work normally
+ *  0b1..reset counter and ouput flags
+ */
 #define IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE_MASK)
 /*! @} */
 
@@ -13010,9 +20489,17 @@ typedef struct {
 #define IOMUXC_GPR_GPR3_OCRAM_CTL(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_OCRAM_CTL_SHIFT)) & IOMUXC_GPR_GPR3_OCRAM_CTL_MASK)
 #define IOMUXC_GPR_GPR3_DCP_KEY_SEL_MASK         (0x10U)
 #define IOMUXC_GPR_GPR3_DCP_KEY_SEL_SHIFT        (4U)
+/*! DCP_KEY_SEL
+ *  0b0..Select [127:0] from snvs/ocotp key as dcp key
+ *  0b1..Select [255:128] from snvs/ocotp key as dcp key
+ */
 #define IOMUXC_GPR_GPR3_DCP_KEY_SEL(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_DCP_KEY_SEL_SHIFT)) & IOMUXC_GPR_GPR3_DCP_KEY_SEL_MASK)
 #define IOMUXC_GPR_GPR3_OCRAM_STATUS_MASK        (0xF0000U)
 #define IOMUXC_GPR_GPR3_OCRAM_STATUS_SHIFT       (16U)
+/*! OCRAM_STATUS
+ *  0b0000..read data pipeline configuration valid
+ *  0b0001..read data pipeline control bit changed
+ */
 #define IOMUXC_GPR_GPR3_OCRAM_STATUS(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_OCRAM_STATUS_SHIFT)) & IOMUXC_GPR_GPR3_OCRAM_STATUS_MASK)
 /*! @} */
 
@@ -13020,81 +20507,185 @@ typedef struct {
 /*! @{ */
 #define IOMUXC_GPR_GPR4_EDMA_STOP_REQ_MASK       (0x1U)
 #define IOMUXC_GPR_GPR4_EDMA_STOP_REQ_SHIFT      (0U)
+/*! EDMA_STOP_REQ
+ *  0b0..stop request off
+ *  0b1..stop request on
+ */
 #define IOMUXC_GPR_GPR4_EDMA_STOP_REQ(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_EDMA_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_EDMA_STOP_REQ_MASK)
 #define IOMUXC_GPR_GPR4_CAN1_STOP_REQ_MASK       (0x2U)
 #define IOMUXC_GPR_GPR4_CAN1_STOP_REQ_SHIFT      (1U)
+/*! CAN1_STOP_REQ
+ *  0b0..stop request off
+ *  0b1..stop request on
+ */
 #define IOMUXC_GPR_GPR4_CAN1_STOP_REQ(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_CAN1_STOP_REQ_MASK)
 #define IOMUXC_GPR_GPR4_CAN2_STOP_REQ_MASK       (0x4U)
 #define IOMUXC_GPR_GPR4_CAN2_STOP_REQ_SHIFT      (2U)
+/*! CAN2_STOP_REQ
+ *  0b0..stop request off
+ *  0b1..stop request on
+ */
 #define IOMUXC_GPR_GPR4_CAN2_STOP_REQ(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_CAN2_STOP_REQ_MASK)
 #define IOMUXC_GPR_GPR4_TRNG_STOP_REQ_MASK       (0x8U)
 #define IOMUXC_GPR_GPR4_TRNG_STOP_REQ_SHIFT      (3U)
+/*! TRNG_STOP_REQ
+ *  0b0..stop request off
+ *  0b1..stop request on
+ */
 #define IOMUXC_GPR_GPR4_TRNG_STOP_REQ(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_TRNG_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_TRNG_STOP_REQ_MASK)
 #define IOMUXC_GPR_GPR4_ENET_STOP_REQ_MASK       (0x10U)
 #define IOMUXC_GPR_GPR4_ENET_STOP_REQ_SHIFT      (4U)
+/*! ENET_STOP_REQ
+ *  0b0..stop request off
+ *  0b1..stop request on
+ */
 #define IOMUXC_GPR_GPR4_ENET_STOP_REQ(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_ENET_STOP_REQ_MASK)
 #define IOMUXC_GPR_GPR4_SAI1_STOP_REQ_MASK       (0x20U)
 #define IOMUXC_GPR_GPR4_SAI1_STOP_REQ_SHIFT      (5U)
+/*! SAI1_STOP_REQ
+ *  0b0..stop request off
+ *  0b1..stop request on
+ */
 #define IOMUXC_GPR_GPR4_SAI1_STOP_REQ(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SAI1_STOP_REQ_MASK)
 #define IOMUXC_GPR_GPR4_SAI2_STOP_REQ_MASK       (0x40U)
 #define IOMUXC_GPR_GPR4_SAI2_STOP_REQ_SHIFT      (6U)
+/*! SAI2_STOP_REQ
+ *  0b0..stop request off
+ *  0b1..stop request on
+ */
 #define IOMUXC_GPR_GPR4_SAI2_STOP_REQ(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SAI2_STOP_REQ_MASK)
 #define IOMUXC_GPR_GPR4_SAI3_STOP_REQ_MASK       (0x80U)
 #define IOMUXC_GPR_GPR4_SAI3_STOP_REQ_SHIFT      (7U)
+/*! SAI3_STOP_REQ
+ *  0b0..stop request off
+ *  0b1..stop request on
+ */
 #define IOMUXC_GPR_GPR4_SAI3_STOP_REQ(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SAI3_STOP_REQ_MASK)
 #define IOMUXC_GPR_GPR4_SEMC_STOP_REQ_MASK       (0x200U)
 #define IOMUXC_GPR_GPR4_SEMC_STOP_REQ_SHIFT      (9U)
+/*! SEMC_STOP_REQ
+ *  0b0..stop request off
+ *  0b1..stop request on
+ */
 #define IOMUXC_GPR_GPR4_SEMC_STOP_REQ(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SEMC_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SEMC_STOP_REQ_MASK)
 #define IOMUXC_GPR_GPR4_PIT_STOP_REQ_MASK        (0x400U)
 #define IOMUXC_GPR_GPR4_PIT_STOP_REQ_SHIFT       (10U)
+/*! PIT_STOP_REQ
+ *  0b0..stop request off
+ *  0b1..stop request on
+ */
 #define IOMUXC_GPR_GPR4_PIT_STOP_REQ(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_PIT_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_PIT_STOP_REQ_MASK)
 #define IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_MASK    (0x800U)
 #define IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_SHIFT   (11U)
+/*! FLEXSPI_STOP_REQ
+ *  0b0..stop request off
+ *  0b1..stop request on
+ */
 #define IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_MASK)
 #define IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_MASK    (0x1000U)
 #define IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_SHIFT   (12U)
+/*! FLEXIO1_STOP_REQ
+ *  0b0..stop request off
+ *  0b1..stop request on
+ */
 #define IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_MASK)
 #define IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ_MASK    (0x2000U)
 #define IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ_SHIFT   (13U)
+/*! FLEXIO2_STOP_REQ
+ *  0b0..stop request off
+ *  0b1..stop request on
+ */
 #define IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ_MASK)
 #define IOMUXC_GPR_GPR4_EDMA_STOP_ACK_MASK       (0x10000U)
 #define IOMUXC_GPR_GPR4_EDMA_STOP_ACK_SHIFT      (16U)
+/*! EDMA_STOP_ACK
+ *  0b0..EDMA stop acknowledge is not asserted
+ *  0b1..EDMA stop acknowledge is asserted (EDMA is in STOP mode).
+ */
 #define IOMUXC_GPR_GPR4_EDMA_STOP_ACK(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_EDMA_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_EDMA_STOP_ACK_MASK)
 #define IOMUXC_GPR_GPR4_CAN1_STOP_ACK_MASK       (0x20000U)
 #define IOMUXC_GPR_GPR4_CAN1_STOP_ACK_SHIFT      (17U)
+/*! CAN1_STOP_ACK
+ *  0b0..CAN1 stop acknowledge is not asserted
+ *  0b1..CAN1 stop acknowledge is asserted
+ */
 #define IOMUXC_GPR_GPR4_CAN1_STOP_ACK(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_CAN1_STOP_ACK_MASK)
 #define IOMUXC_GPR_GPR4_CAN2_STOP_ACK_MASK       (0x40000U)
 #define IOMUXC_GPR_GPR4_CAN2_STOP_ACK_SHIFT      (18U)
+/*! CAN2_STOP_ACK
+ *  0b0..CAN2 stop acknowledge is not asserted
+ *  0b1..CAN2 stop acknowledge is asserted
+ */
 #define IOMUXC_GPR_GPR4_CAN2_STOP_ACK(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_CAN2_STOP_ACK_MASK)
 #define IOMUXC_GPR_GPR4_TRNG_STOP_ACK_MASK       (0x80000U)
 #define IOMUXC_GPR_GPR4_TRNG_STOP_ACK_SHIFT      (19U)
+/*! TRNG_STOP_ACK
+ *  0b0..TRNG stop acknowledge is not asserted
+ *  0b1..TRNG stop acknowledge is asserted
+ */
 #define IOMUXC_GPR_GPR4_TRNG_STOP_ACK(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_TRNG_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_TRNG_STOP_ACK_MASK)
 #define IOMUXC_GPR_GPR4_ENET_STOP_ACK_MASK       (0x100000U)
 #define IOMUXC_GPR_GPR4_ENET_STOP_ACK_SHIFT      (20U)
+/*! ENET_STOP_ACK
+ *  0b0..ENET stop acknowledge is not asserted
+ *  0b1..ENET stop acknowledge is asserted
+ */
 #define IOMUXC_GPR_GPR4_ENET_STOP_ACK(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_ENET_STOP_ACK_MASK)
 #define IOMUXC_GPR_GPR4_SAI1_STOP_ACK_MASK       (0x200000U)
 #define IOMUXC_GPR_GPR4_SAI1_STOP_ACK_SHIFT      (21U)
+/*! SAI1_STOP_ACK
+ *  0b0..SAI1 stop acknowledge is not asserted
+ *  0b1..SAI1 stop acknowledge is asserted
+ */
 #define IOMUXC_GPR_GPR4_SAI1_STOP_ACK(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SAI1_STOP_ACK_MASK)
 #define IOMUXC_GPR_GPR4_SAI2_STOP_ACK_MASK       (0x400000U)
 #define IOMUXC_GPR_GPR4_SAI2_STOP_ACK_SHIFT      (22U)
+/*! SAI2_STOP_ACK
+ *  0b0..SAI2 stop acknowledge is not asserted
+ *  0b1..SAI2 stop acknowledge is asserted
+ */
 #define IOMUXC_GPR_GPR4_SAI2_STOP_ACK(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SAI2_STOP_ACK_MASK)
 #define IOMUXC_GPR_GPR4_SAI3_STOP_ACK_MASK       (0x800000U)
 #define IOMUXC_GPR_GPR4_SAI3_STOP_ACK_SHIFT      (23U)
+/*! SAI3_STOP_ACK
+ *  0b0..SAI3 stop acknowledge is not asserted
+ *  0b1..SAI3 stop acknowledge is asserted
+ */
 #define IOMUXC_GPR_GPR4_SAI3_STOP_ACK(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SAI3_STOP_ACK_MASK)
 #define IOMUXC_GPR_GPR4_SEMC_STOP_ACK_MASK       (0x2000000U)
 #define IOMUXC_GPR_GPR4_SEMC_STOP_ACK_SHIFT      (25U)
+/*! SEMC_STOP_ACK
+ *  0b0..SEMC stop acknowledge is not asserted
+ *  0b1..SEMC stop acknowledge is asserted
+ */
 #define IOMUXC_GPR_GPR4_SEMC_STOP_ACK(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SEMC_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SEMC_STOP_ACK_MASK)
 #define IOMUXC_GPR_GPR4_PIT_STOP_ACK_MASK        (0x4000000U)
 #define IOMUXC_GPR_GPR4_PIT_STOP_ACK_SHIFT       (26U)
+/*! PIT_STOP_ACK
+ *  0b0..PIT stop acknowledge is not asserted
+ *  0b1..PIT stop acknowledge is asserted
+ */
 #define IOMUXC_GPR_GPR4_PIT_STOP_ACK(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_PIT_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_PIT_STOP_ACK_MASK)
 #define IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_MASK    (0x8000000U)
 #define IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_SHIFT   (27U)
+/*! FLEXSPI_STOP_ACK
+ *  0b0..FLEXSPI stop acknowledge is not asserted
+ *  0b1..FLEXSPI stop acknowledge is asserted
+ */
 #define IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_MASK)
 #define IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_MASK    (0x10000000U)
 #define IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_SHIFT   (28U)
+/*! FLEXIO1_STOP_ACK
+ *  0b0..FLEXIO1 stop acknowledge is not asserted
+ *  0b1..FLEXIO1 stop acknowledge is asserted
+ */
 #define IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_MASK)
 #define IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK_MASK    (0x20000000U)
 #define IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK_SHIFT   (29U)
+/*! FLEXIO2_STOP_ACK
+ *  0b0..FLEXIO2 stop acknowledge is not asserted
+ *  0b1..FLEXIO2 stop acknowledge is asserted (FLEXIO2 is in STOP mode)
+ */
 #define IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK_MASK)
 /*! @} */
 
@@ -13102,21 +20693,45 @@ typedef struct {
 /*! @{ */
 #define IOMUXC_GPR_GPR5_WDOG1_MASK_MASK          (0x40U)
 #define IOMUXC_GPR_GPR5_WDOG1_MASK_SHIFT         (6U)
+/*! WDOG1_MASK
+ *  0b0..WDOG1 Timeout behaves normally
+ *  0b1..WDOG1 Timeout is masked
+ */
 #define IOMUXC_GPR_GPR5_WDOG1_MASK(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_WDOG1_MASK_SHIFT)) & IOMUXC_GPR_GPR5_WDOG1_MASK_MASK)
 #define IOMUXC_GPR_GPR5_WDOG2_MASK_MASK          (0x80U)
 #define IOMUXC_GPR_GPR5_WDOG2_MASK_SHIFT         (7U)
+/*! WDOG2_MASK
+ *  0b0..WDOG2 Timeout behaves normally
+ *  0b1..WDOG2 Timeout is masked
+ */
 #define IOMUXC_GPR_GPR5_WDOG2_MASK(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_WDOG2_MASK_SHIFT)) & IOMUXC_GPR_GPR5_WDOG2_MASK_MASK)
 #define IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_MASK     (0x800000U)
 #define IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_SHIFT    (23U)
+/*! GPT2_CAPIN1_SEL
+ *  0b0..source from pad
+ *  0b1..source from enet1.ipp_do_mac0_timer[3]
+ */
 #define IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_SHIFT)) & IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_MASK)
 #define IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_MASK   (0x2000000U)
 #define IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_SHIFT  (25U)
+/*! ENET_EVENT3IN_SEL
+ *  0b0..event3 source input from pad
+ *  0b1..event3 source input from gpt2.ipp_do_cmpout1
+ */
 #define IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_SHIFT)) & IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_MASK)
 #define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK    (0x10000000U)
 #define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_SHIFT   (28U)
+/*! VREF_1M_CLK_GPT1
+ *  0b0..GPT1 ipg_clk_highfreq driven by IPG_PERCLK
+ *  0b1..GPT1 ipg_clk_highfreq driven by anatop 1 MHz clock
+ */
 #define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_SHIFT)) & IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK)
 #define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK    (0x20000000U)
 #define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_SHIFT   (29U)
+/*! VREF_1M_CLK_GPT2
+ *  0b0..GPT2 ipg_clk_highfreq driven by IPG_PERCLK
+ *  0b1..GPT2 ipg_clk_highfreq driven by anatop 1 MHz clock
+ */
 #define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_SHIFT)) & IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK)
 /*! @} */
 
@@ -13124,99 +20739,227 @@ typedef struct {
 /*! @{ */
 #define IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_MASK (0x1U)
 #define IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_SHIFT (0U)
+/*! QTIMER1_TRM0_INPUT_SEL
+ *  0b0..input from IOMUX
+ *  0b1..input from XBAR
+ */
 #define IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_MASK)
 #define IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_MASK (0x2U)
 #define IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_SHIFT (1U)
+/*! QTIMER1_TRM1_INPUT_SEL
+ *  0b0..input from IOMUX
+ *  0b1..input from XBAR
+ */
 #define IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_MASK)
 #define IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_MASK (0x4U)
 #define IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_SHIFT (2U)
+/*! QTIMER1_TRM2_INPUT_SEL
+ *  0b0..input from IOMUX
+ *  0b1..input from XBAR
+ */
 #define IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_MASK)
 #define IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_MASK (0x8U)
 #define IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_SHIFT (3U)
+/*! QTIMER1_TRM3_INPUT_SEL
+ *  0b0..input from IOMUX
+ *  0b1..input from XBAR
+ */
 #define IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_MASK)
 #define IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_MASK (0x10U)
 #define IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_SHIFT (4U)
+/*! QTIMER2_TRM0_INPUT_SEL
+ *  0b0..input from IOMUX
+ *  0b1..input from XBAR
+ */
 #define IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_MASK)
 #define IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_MASK (0x20U)
 #define IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_SHIFT (5U)
+/*! QTIMER2_TRM1_INPUT_SEL
+ *  0b0..input from IOMUX
+ *  0b1..input from XBAR
+ */
 #define IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_MASK)
 #define IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_MASK (0x40U)
 #define IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_SHIFT (6U)
+/*! QTIMER2_TRM2_INPUT_SEL
+ *  0b0..input from IOMUX
+ *  0b1..input from XBAR
+ */
 #define IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_MASK)
 #define IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_MASK (0x80U)
 #define IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_SHIFT (7U)
+/*! QTIMER2_TRM3_INPUT_SEL
+ *  0b0..input from IOMUX
+ *  0b1..input from XBAR
+ */
 #define IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_MASK)
 #define IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_MASK (0x100U)
 #define IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_SHIFT (8U)
+/*! QTIMER3_TRM0_INPUT_SEL
+ *  0b0..input from IOMUX
+ *  0b1..input from XBAR
+ */
 #define IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_MASK)
 #define IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_MASK (0x200U)
 #define IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_SHIFT (9U)
+/*! QTIMER3_TRM1_INPUT_SEL
+ *  0b0..input from IOMUX
+ *  0b1..input from XBAR
+ */
 #define IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_MASK)
 #define IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_MASK (0x400U)
 #define IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_SHIFT (10U)
+/*! QTIMER3_TRM2_INPUT_SEL
+ *  0b0..input from IOMUX
+ *  0b1..input from XBAR
+ */
 #define IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_MASK)
 #define IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_MASK (0x800U)
 #define IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_SHIFT (11U)
+/*! QTIMER3_TRM3_INPUT_SEL
+ *  0b0..input from IOMUX
+ *  0b1..input from XBAR
+ */
 #define IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_MASK)
 #define IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_MASK (0x1000U)
 #define IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_SHIFT (12U)
+/*! QTIMER4_TRM0_INPUT_SEL
+ *  0b0..input from IOMUX
+ *  0b1..input from XBAR
+ */
 #define IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_MASK)
 #define IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_MASK (0x2000U)
 #define IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_SHIFT (13U)
+/*! QTIMER4_TRM1_INPUT_SEL
+ *  0b0..input from IOMUX
+ *  0b1..input from XBAR
+ */
 #define IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_MASK)
 #define IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_MASK (0x4000U)
 #define IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_SHIFT (14U)
+/*! QTIMER4_TRM2_INPUT_SEL
+ *  0b0..input from IOMUX
+ *  0b1..input from XBAR
+ */
 #define IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_MASK)
 #define IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_MASK (0x8000U)
 #define IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_SHIFT (15U)
+/*! QTIMER4_TRM3_INPUT_SEL
+ *  0b0..input from IOMUX
+ *  0b1..input from XBAR
+ */
 #define IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_MASK)
 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_MASK (0x10000U)
 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_SHIFT (16U)
+/*! IOMUXC_XBAR_DIR_SEL_4
+ *  0b0..XBAR_INOUT as input
+ *  0b1..XBAR_INOUT as output
+ */
 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_MASK)
 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_MASK (0x20000U)
 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_SHIFT (17U)
+/*! IOMUXC_XBAR_DIR_SEL_5
+ *  0b0..XBAR_INOUT as input
+ *  0b1..XBAR_INOUT as output
+ */
 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_MASK)
 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_MASK (0x40000U)
 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_SHIFT (18U)
+/*! IOMUXC_XBAR_DIR_SEL_6
+ *  0b0..XBAR_INOUT as input
+ *  0b1..XBAR_INOUT as output
+ */
 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_MASK)
 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_MASK (0x80000U)
 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_SHIFT (19U)
+/*! IOMUXC_XBAR_DIR_SEL_7
+ *  0b0..XBAR_INOUT as input
+ *  0b1..XBAR_INOUT as output
+ */
 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_MASK)
 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_MASK (0x100000U)
 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_SHIFT (20U)
+/*! IOMUXC_XBAR_DIR_SEL_8
+ *  0b0..XBAR_INOUT as input
+ *  0b1..XBAR_INOUT as output
+ */
 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_MASK)
 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_MASK (0x200000U)
 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_SHIFT (21U)
+/*! IOMUXC_XBAR_DIR_SEL_9
+ *  0b0..XBAR_INOUT as input
+ *  0b1..XBAR_INOUT as output
+ */
 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_MASK)
 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_MASK (0x400000U)
 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_SHIFT (22U)
+/*! IOMUXC_XBAR_DIR_SEL_10
+ *  0b0..XBAR_INOUT as input
+ *  0b1..XBAR_INOUT as output
+ */
 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_MASK)
 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_MASK (0x800000U)
 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_SHIFT (23U)
+/*! IOMUXC_XBAR_DIR_SEL_11
+ *  0b0..XBAR_INOUT as input
+ *  0b1..XBAR_INOUT as output
+ */
 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_MASK)
 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_MASK (0x1000000U)
 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_SHIFT (24U)
+/*! IOMUXC_XBAR_DIR_SEL_12
+ *  0b0..XBAR_INOUT as input
+ *  0b1..XBAR_INOUT as output
+ */
 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_MASK)
 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_MASK (0x2000000U)
 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_SHIFT (25U)
+/*! IOMUXC_XBAR_DIR_SEL_13
+ *  0b0..XBAR_INOUT as input
+ *  0b1..XBAR_INOUT as output
+ */
 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_MASK)
 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_MASK (0x4000000U)
 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_SHIFT (26U)
+/*! IOMUXC_XBAR_DIR_SEL_14
+ *  0b0..XBAR_INOUT as input
+ *  0b1..XBAR_INOUT as output
+ */
 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_MASK)
 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_MASK (0x8000000U)
 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_SHIFT (27U)
+/*! IOMUXC_XBAR_DIR_SEL_15
+ *  0b0..XBAR_INOUT as input
+ *  0b1..XBAR_INOUT as output
+ */
 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_MASK)
 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_MASK (0x10000000U)
 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_SHIFT (28U)
+/*! IOMUXC_XBAR_DIR_SEL_16
+ *  0b0..XBAR_INOUT as input
+ *  0b1..XBAR_INOUT as output
+ */
 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_MASK)
 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_MASK (0x20000000U)
 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_SHIFT (29U)
+/*! IOMUXC_XBAR_DIR_SEL_17
+ *  0b0..XBAR_INOUT as input
+ *  0b1..XBAR_INOUT as output
+ */
 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_MASK)
 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_MASK (0x40000000U)
 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_SHIFT (30U)
+/*! IOMUXC_XBAR_DIR_SEL_18
+ *  0b0..XBAR_INOUT as input
+ *  0b1..XBAR_INOUT as output
+ */
 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_MASK)
 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_MASK (0x80000000U)
 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_SHIFT (31U)
+/*! IOMUXC_XBAR_DIR_SEL_19
+ *  0b0..XBAR_INOUT as input
+ *  0b1..XBAR_INOUT as output
+ */
 #define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_MASK)
 /*! @} */
 
@@ -13224,99 +20967,227 @@ typedef struct {
 /*! @{ */
 #define IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_MASK     (0x1U)
 #define IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_SHIFT    (0U)
+/*! LPI2C1_STOP_REQ
+ *  0b0..stop request off
+ *  0b1..stop request on
+ */
 #define IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_MASK)
 #define IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_MASK     (0x2U)
 #define IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_SHIFT    (1U)
+/*! LPI2C2_STOP_REQ
+ *  0b0..stop request off
+ *  0b1..stop request on
+ */
 #define IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_MASK)
 #define IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_MASK     (0x4U)
 #define IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_SHIFT    (2U)
+/*! LPI2C3_STOP_REQ
+ *  0b0..stop request off
+ *  0b1..stop request on
+ */
 #define IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_MASK)
 #define IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_MASK     (0x8U)
 #define IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_SHIFT    (3U)
+/*! LPI2C4_STOP_REQ
+ *  0b0..stop request off
+ *  0b1..stop request on
+ */
 #define IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_MASK)
 #define IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_MASK     (0x10U)
 #define IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_SHIFT    (4U)
+/*! LPSPI1_STOP_REQ
+ *  0b0..stop request off
+ *  0b1..stop request on
+ */
 #define IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_MASK)
 #define IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_MASK     (0x20U)
 #define IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_SHIFT    (5U)
+/*! LPSPI2_STOP_REQ
+ *  0b0..stop request off
+ *  0b1..stop request on
+ */
 #define IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_MASK)
 #define IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_MASK     (0x40U)
 #define IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_SHIFT    (6U)
+/*! LPSPI3_STOP_REQ
+ *  0b0..stop request off
+ *  0b1..stop request on
+ */
 #define IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_MASK)
 #define IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_MASK     (0x80U)
 #define IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_SHIFT    (7U)
+/*! LPSPI4_STOP_REQ
+ *  0b0..stop request off
+ *  0b1..stop request on
+ */
 #define IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_MASK)
 #define IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_MASK    (0x100U)
 #define IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_SHIFT   (8U)
+/*! LPUART1_STOP_REQ
+ *  0b0..stop request off
+ *  0b1..stop request on
+ */
 #define IOMUXC_GPR_GPR7_LPUART1_STOP_REQ(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_MASK)
 #define IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_MASK    (0x200U)
 #define IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_SHIFT   (9U)
+/*! LPUART2_STOP_REQ
+ *  0b0..stop request off
+ *  0b1..stop request on
+ */
 #define IOMUXC_GPR_GPR7_LPUART2_STOP_REQ(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_MASK)
 #define IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_MASK    (0x400U)
 #define IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_SHIFT   (10U)
+/*! LPUART3_STOP_REQ
+ *  0b0..stop request off
+ *  0b1..stop request on
+ */
 #define IOMUXC_GPR_GPR7_LPUART3_STOP_REQ(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_MASK)
 #define IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_MASK    (0x800U)
 #define IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_SHIFT   (11U)
+/*! LPUART4_STOP_REQ
+ *  0b0..stop request off
+ *  0b1..stop request on
+ */
 #define IOMUXC_GPR_GPR7_LPUART4_STOP_REQ(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_MASK)
 #define IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_MASK    (0x1000U)
 #define IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_SHIFT   (12U)
+/*! LPUART5_STOP_REQ
+ *  0b0..stop request off
+ *  0b1..stop request on
+ */
 #define IOMUXC_GPR_GPR7_LPUART5_STOP_REQ(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_MASK)
 #define IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_MASK    (0x2000U)
 #define IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_SHIFT   (13U)
+/*! LPUART6_STOP_REQ
+ *  0b0..stop request off
+ *  0b1..stop request on
+ */
 #define IOMUXC_GPR_GPR7_LPUART6_STOP_REQ(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_MASK)
 #define IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_MASK    (0x4000U)
 #define IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_SHIFT   (14U)
+/*! LPUART7_STOP_REQ
+ *  0b0..stop request off
+ *  0b1..stop request on
+ */
 #define IOMUXC_GPR_GPR7_LPUART7_STOP_REQ(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_MASK)
 #define IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_MASK    (0x8000U)
 #define IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_SHIFT   (15U)
+/*! LPUART8_STOP_REQ
+ *  0b0..stop request off
+ *  0b1..stop request on
+ */
 #define IOMUXC_GPR_GPR7_LPUART8_STOP_REQ(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_MASK)
 #define IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_MASK     (0x10000U)
 #define IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_SHIFT    (16U)
+/*! LPI2C1_STOP_ACK
+ *  0b0..stop acknowledge is not asserted
+ *  0b1..stop acknowledge is asserted (the module is in Stop mode)
+ */
 #define IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_MASK)
 #define IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_MASK     (0x20000U)
 #define IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_SHIFT    (17U)
+/*! LPI2C2_STOP_ACK
+ *  0b0..stop acknowledge is not asserted
+ *  0b1..stop acknowledge is asserted
+ */
 #define IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_MASK)
 #define IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_MASK     (0x40000U)
 #define IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_SHIFT    (18U)
+/*! LPI2C3_STOP_ACK
+ *  0b0..stop acknowledge is not asserted
+ *  0b1..stop acknowledge is asserted
+ */
 #define IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_MASK)
 #define IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_MASK     (0x80000U)
 #define IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_SHIFT    (19U)
+/*! LPI2C4_STOP_ACK
+ *  0b0..stop acknowledge is not asserted
+ *  0b1..stop acknowledge is asserted
+ */
 #define IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_MASK)
 #define IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_MASK     (0x100000U)
 #define IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_SHIFT    (20U)
+/*! LPSPI1_STOP_ACK
+ *  0b0..stop acknowledge is not asserted
+ *  0b1..stop acknowledge is asserted
+ */
 #define IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_MASK)
 #define IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_MASK     (0x200000U)
 #define IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_SHIFT    (21U)
+/*! LPSPI2_STOP_ACK
+ *  0b0..stop acknowledge is not asserted
+ *  0b1..stop acknowledge is asserted
+ */
 #define IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_MASK)
 #define IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_MASK     (0x400000U)
 #define IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_SHIFT    (22U)
+/*! LPSPI3_STOP_ACK
+ *  0b0..stop acknowledge is not asserted
+ *  0b1..stop acknowledge is asserted
+ */
 #define IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_MASK)
 #define IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_MASK     (0x800000U)
 #define IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_SHIFT    (23U)
+/*! LPSPI4_STOP_ACK
+ *  0b0..stop acknowledge is not asserted
+ *  0b1..stop acknowledge is asserted
+ */
 #define IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_MASK)
 #define IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_MASK    (0x1000000U)
 #define IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_SHIFT   (24U)
+/*! LPUART1_STOP_ACK
+ *  0b0..stop acknowledge is not asserted
+ *  0b1..stop acknowledge is asserted
+ */
 #define IOMUXC_GPR_GPR7_LPUART1_STOP_ACK(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_MASK)
 #define IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_MASK    (0x2000000U)
 #define IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_SHIFT   (25U)
+/*! LPUART2_STOP_ACK
+ *  0b0..stop acknowledge is not asserted
+ *  0b1..stop acknowledge is asserted
+ */
 #define IOMUXC_GPR_GPR7_LPUART2_STOP_ACK(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_MASK)
 #define IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_MASK    (0x4000000U)
 #define IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_SHIFT   (26U)
+/*! LPUART3_STOP_ACK
+ *  0b0..stop acknowledge is not asserted
+ *  0b1..stop acknowledge is asserted
+ */
 #define IOMUXC_GPR_GPR7_LPUART3_STOP_ACK(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_MASK)
 #define IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_MASK    (0x8000000U)
 #define IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_SHIFT   (27U)
+/*! LPUART4_STOP_ACK
+ *  0b0..stop acknowledge is not asserted
+ *  0b1..stop acknowledge is asserted
+ */
 #define IOMUXC_GPR_GPR7_LPUART4_STOP_ACK(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_MASK)
 #define IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_MASK    (0x10000000U)
 #define IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_SHIFT   (28U)
+/*! LPUART5_STOP_ACK
+ *  0b0..stop acknowledge is not asserted
+ *  0b1..stop acknowledge is asserted
+ */
 #define IOMUXC_GPR_GPR7_LPUART5_STOP_ACK(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_MASK)
 #define IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_MASK    (0x20000000U)
 #define IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_SHIFT   (29U)
+/*! LPUART6_STOP_ACK
+ *  0b0..stop acknowledge is not asserted
+ *  0b1..stop acknowledge is asserted
+ */
 #define IOMUXC_GPR_GPR7_LPUART6_STOP_ACK(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_MASK)
 #define IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_MASK    (0x40000000U)
 #define IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_SHIFT   (30U)
+/*! LPUART7_STOP_ACK
+ *  0b0..stop acknowledge is not asserted
+ *  0b1..stop acknowledge is asserted
+ */
 #define IOMUXC_GPR_GPR7_LPUART7_STOP_ACK(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_MASK)
 #define IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_MASK    (0x80000000U)
 #define IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_SHIFT   (31U)
+/*! LPUART8_STOP_ACK
+ *  0b0..stop acknowledge is not asserted
+ *  0b1..stop acknowledge is asserted (the module is in Stop mode)
+ */
 #define IOMUXC_GPR_GPR7_LPUART8_STOP_ACK(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_MASK)
 /*! @} */
 
@@ -13324,99 +21195,227 @@ typedef struct {
 /*! @{ */
 #define IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_MASK (0x1U)
 #define IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_SHIFT (0U)
+/*! LPI2C1_IPG_STOP_MODE
+ *  0b0..the module is functional in Stop mode
+ *  0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted
+ */
 #define IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_MASK)
 #define IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_MASK     (0x2U)
 #define IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_SHIFT    (1U)
+/*! LPI2C1_IPG_DOZE
+ *  0b0..not in doze mode
+ *  0b1..in doze mode
+ */
 #define IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_MASK)
 #define IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_MASK (0x4U)
 #define IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_SHIFT (2U)
+/*! LPI2C2_IPG_STOP_MODE
+ *  0b0..the module is functional in Stop mode
+ *  0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted
+ */
 #define IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_MASK)
 #define IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_MASK     (0x8U)
 #define IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_SHIFT    (3U)
+/*! LPI2C2_IPG_DOZE
+ *  0b0..not in doze mode
+ *  0b1..in doze mode
+ */
 #define IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_MASK)
 #define IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_MASK (0x10U)
 #define IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_SHIFT (4U)
+/*! LPI2C3_IPG_STOP_MODE
+ *  0b0..the module is functional in Stop mode
+ *  0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted
+ */
 #define IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_MASK)
 #define IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_MASK     (0x20U)
 #define IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_SHIFT    (5U)
+/*! LPI2C3_IPG_DOZE
+ *  0b0..not in doze mode
+ *  0b1..in doze mode
+ */
 #define IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_MASK)
 #define IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_MASK (0x40U)
 #define IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_SHIFT (6U)
+/*! LPI2C4_IPG_STOP_MODE
+ *  0b0..the module is functional in Stop mode
+ *  0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted
+ */
 #define IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_MASK)
 #define IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_MASK     (0x80U)
 #define IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_SHIFT    (7U)
+/*! LPI2C4_IPG_DOZE
+ *  0b0..not in doze mode
+ *  0b1..in doze mode
+ */
 #define IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_MASK)
 #define IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_MASK (0x100U)
 #define IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_SHIFT (8U)
+/*! LPSPI1_IPG_STOP_MODE
+ *  0b0..the module is functional in Stop mode
+ *  0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted
+ */
 #define IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_MASK)
 #define IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_MASK     (0x200U)
 #define IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_SHIFT    (9U)
+/*! LPSPI1_IPG_DOZE
+ *  0b0..not in doze mode
+ *  0b1..in doze mode
+ */
 #define IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_MASK)
 #define IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_MASK (0x400U)
 #define IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_SHIFT (10U)
+/*! LPSPI2_IPG_STOP_MODE
+ *  0b0..the module is functional in Stop mode
+ *  0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted
+ */
 #define IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_MASK)
 #define IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_MASK     (0x800U)
 #define IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_SHIFT    (11U)
+/*! LPSPI2_IPG_DOZE
+ *  0b0..not in doze mode
+ *  0b1..in doze mode
+ */
 #define IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_MASK)
 #define IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_MASK (0x1000U)
 #define IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_SHIFT (12U)
+/*! LPSPI3_IPG_STOP_MODE
+ *  0b0..the module is functional in Stop mode
+ *  0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted
+ */
 #define IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_MASK)
 #define IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_MASK     (0x2000U)
 #define IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_SHIFT    (13U)
+/*! LPSPI3_IPG_DOZE
+ *  0b0..not in doze mode
+ *  0b1..in doze mode
+ */
 #define IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_MASK)
 #define IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_MASK (0x4000U)
 #define IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_SHIFT (14U)
+/*! LPSPI4_IPG_STOP_MODE
+ *  0b0..the module is functional in Stop mode
+ *  0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted
+ */
 #define IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_MASK)
 #define IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_MASK     (0x8000U)
 #define IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_SHIFT    (15U)
+/*! LPSPI4_IPG_DOZE
+ *  0b0..not in doze mode
+ *  0b1..in doze mode
+ */
 #define IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_MASK)
 #define IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_MASK (0x10000U)
 #define IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_SHIFT (16U)
+/*! LPUART1_IPG_STOP_MODE
+ *  0b0..the module is functional in Stop mode
+ *  0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted
+ */
 #define IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_MASK)
 #define IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_MASK    (0x20000U)
 #define IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_SHIFT   (17U)
+/*! LPUART1_IPG_DOZE
+ *  0b0..not in doze mode
+ *  0b1..in doze mode
+ */
 #define IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_MASK)
 #define IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_MASK (0x40000U)
 #define IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_SHIFT (18U)
+/*! LPUART2_IPG_STOP_MODE
+ *  0b0..the module is functional in Stop mode
+ *  0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted
+ */
 #define IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_MASK)
 #define IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_MASK    (0x80000U)
 #define IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_SHIFT   (19U)
+/*! LPUART2_IPG_DOZE
+ *  0b0..not in doze mode
+ *  0b1..in doze mode
+ */
 #define IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_MASK)
 #define IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_MASK (0x100000U)
 #define IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_SHIFT (20U)
+/*! LPUART3_IPG_STOP_MODE
+ *  0b0..the module is functional in Stop mode
+ *  0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted
+ */
 #define IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_MASK)
 #define IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_MASK    (0x200000U)
 #define IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_SHIFT   (21U)
+/*! LPUART3_IPG_DOZE
+ *  0b0..not in doze mode
+ *  0b1..in doze mode
+ */
 #define IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_MASK)
 #define IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_MASK (0x400000U)
 #define IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_SHIFT (22U)
+/*! LPUART4_IPG_STOP_MODE
+ *  0b0..the module is functional in Stop mode
+ *  0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted
+ */
 #define IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_MASK)
 #define IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_MASK    (0x800000U)
 #define IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_SHIFT   (23U)
+/*! LPUART4_IPG_DOZE
+ *  0b0..not in doze mode
+ *  0b1..in doze mode
+ */
 #define IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_MASK)
 #define IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_MASK (0x1000000U)
 #define IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_SHIFT (24U)
+/*! LPUART5_IPG_STOP_MODE
+ *  0b0..the module is functional in Stop mode
+ *  0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted
+ */
 #define IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_MASK)
 #define IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_MASK    (0x2000000U)
 #define IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_SHIFT   (25U)
+/*! LPUART5_IPG_DOZE
+ *  0b0..not in doze mode
+ *  0b1..in doze mode
+ */
 #define IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_MASK)
 #define IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_MASK (0x4000000U)
 #define IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_SHIFT (26U)
+/*! LPUART6_IPG_STOP_MODE
+ *  0b0..the module is functional in Stop mode
+ *  0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted
+ */
 #define IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_MASK)
 #define IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_MASK    (0x8000000U)
 #define IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_SHIFT   (27U)
+/*! LPUART6_IPG_DOZE
+ *  0b0..not in doze mode
+ *  0b1..in doze mode
+ */
 #define IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_MASK)
 #define IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_MASK (0x10000000U)
 #define IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_SHIFT (28U)
+/*! LPUART7_IPG_STOP_MODE
+ *  0b0..the module is functional in Stop mode
+ *  0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted
+ */
 #define IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_MASK)
 #define IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_MASK    (0x20000000U)
 #define IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_SHIFT   (29U)
+/*! LPUART7_IPG_DOZE
+ *  0b0..not in doze mode
+ *  0b1..in doze mode
+ */
 #define IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_MASK)
 #define IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_MASK (0x40000000U)
 #define IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_SHIFT (30U)
+/*! LPUART8_IPG_STOP_MODE
+ *  0b0..the module is functional in Stop mode
+ *  0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted
+ */
 #define IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_MASK)
 #define IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_MASK    (0x80000000U)
 #define IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_SHIFT   (31U)
+/*! LPUART8_IPG_DOZE
+ *  0b0..not in doze mode
+ *  0b1..in doze mode
+ */
 #define IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_MASK)
 /*! @} */
 
@@ -13424,39 +21423,84 @@ typedef struct {
 /*! @{ */
 #define IOMUXC_GPR_GPR10_NIDEN_MASK              (0x1U)
 #define IOMUXC_GPR_GPR10_NIDEN_SHIFT             (0U)
+/*! NIDEN
+ *  0b0..Debug turned off.
+ *  0b1..Debug enabled (default).
+ */
 #define IOMUXC_GPR_GPR10_NIDEN(x)                (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_NIDEN_SHIFT)) & IOMUXC_GPR_GPR10_NIDEN_MASK)
 #define IOMUXC_GPR_GPR10_DBG_EN_MASK             (0x2U)
 #define IOMUXC_GPR_GPR10_DBG_EN_SHIFT            (1U)
+/*! DBG_EN
+ *  0b0..Debug turned off.
+ *  0b1..Debug enabled (default).
+ */
 #define IOMUXC_GPR_GPR10_DBG_EN(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_DBG_EN_SHIFT)) & IOMUXC_GPR_GPR10_DBG_EN_MASK)
 #define IOMUXC_GPR_GPR10_SEC_ERR_RESP_MASK       (0x4U)
 #define IOMUXC_GPR_GPR10_SEC_ERR_RESP_SHIFT      (2U)
+/*! SEC_ERR_RESP
+ *  0b0..OKEY response
+ *  0b1..SLVError (default)
+ */
 #define IOMUXC_GPR_GPR10_SEC_ERR_RESP(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_SEC_ERR_RESP_SHIFT)) & IOMUXC_GPR_GPR10_SEC_ERR_RESP_MASK)
 #define IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_MASK (0x10U)
 #define IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_SHIFT (4U)
+/*! DCPKEY_OCOTP_OR_KEYMUX
+ *  0b0..Select key from Key MUX (SNVS/OTPMK).
+ *  0b1..Select key from OCOTP (SW_GP2).
+ */
 #define IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_SHIFT)) & IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_MASK)
 #define IOMUXC_GPR_GPR10_OCRAM_TZ_EN_MASK        (0x100U)
 #define IOMUXC_GPR_GPR10_OCRAM_TZ_EN_SHIFT       (8U)
+/*! OCRAM_TZ_EN
+ *  0b0..The TrustZone feature is disabled. Entire OCRAM space is available for all access types (secure/non-secure/user/supervisor).
+ *  0b1..The TrustZone feature is enabled. Access to address in the range specified by [ENDADDR:STARTADDR] follows
+ *       the execution mode access policy described in CSU chapter.
+ */
 #define IOMUXC_GPR_GPR10_OCRAM_TZ_EN(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_OCRAM_TZ_EN_SHIFT)) & IOMUXC_GPR_GPR10_OCRAM_TZ_EN_MASK)
 #define IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_MASK      (0xFE00U)
 #define IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_SHIFT     (9U)
 #define IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_SHIFT)) & IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_MASK)
 #define IOMUXC_GPR_GPR10_LOCK_NIDEN_MASK         (0x10000U)
 #define IOMUXC_GPR_GPR10_LOCK_NIDEN_SHIFT        (16U)
+/*! LOCK_NIDEN
+ *  0b0..Field is not locked
+ *  0b1..Field is locked (read access only)
+ */
 #define IOMUXC_GPR_GPR10_LOCK_NIDEN(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_NIDEN_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_NIDEN_MASK)
 #define IOMUXC_GPR_GPR10_LOCK_DBG_EN_MASK        (0x20000U)
 #define IOMUXC_GPR_GPR10_LOCK_DBG_EN_SHIFT       (17U)
+/*! LOCK_DBG_EN
+ *  0b0..Field is not locked
+ *  0b1..Field is locked (read access only)
+ */
 #define IOMUXC_GPR_GPR10_LOCK_DBG_EN(x)          (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_DBG_EN_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_DBG_EN_MASK)
 #define IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_MASK  (0x40000U)
 #define IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_SHIFT (18U)
+/*! LOCK_SEC_ERR_RESP
+ *  0b0..Field is not locked
+ *  0b1..Field is locked (read access only)
+ */
 #define IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_MASK)
 #define IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_MASK (0x100000U)
 #define IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_SHIFT (20U)
+/*! LOCK_DCPKEY_OCOTP_OR_KEYMUX
+ *  0b0..Field is not locked
+ *  0b1..Field is locked (read access only)
+ */
 #define IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_MASK)
 #define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_MASK   (0x1000000U)
 #define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_SHIFT  (24U)
+/*! LOCK_OCRAM_TZ_EN
+ *  0b0..Field is not locked
+ *  0b1..Field is locked (read access only)
+ */
 #define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_MASK)
 #define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_MASK (0xFE000000U)
 #define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_SHIFT (25U)
+/*! LOCK_OCRAM_TZ_ADDR
+ *  0b0000000..Field is not locked
+ *  0b0000001..Field is locked (read access only)
+ */
 #define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_MASK)
 /*! @} */
 
@@ -13464,15 +21508,39 @@ typedef struct {
 /*! @{ */
 #define IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_MASK  (0x3U)
 #define IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_SHIFT (0U)
+/*! M7_APC_AC_R0_CTRL
+ *  0b00..No access protection
+ *  0b01..M7 debug protection enabled
+ *  0b10..FlexSPI access protection
+ *  0b11..Both M7 debug and FlexSPI access are protected
+ */
 #define IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_MASK)
 #define IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_MASK  (0xCU)
 #define IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_SHIFT (2U)
+/*! M7_APC_AC_R1_CTRL
+ *  0b00..No access protection
+ *  0b01..M7 debug protection enabled
+ *  0b10..FlexSPI access protection
+ *  0b11..Both M7 debug and FlexSPI access are protected
+ */
 #define IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_MASK)
 #define IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_MASK  (0x30U)
 #define IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_SHIFT (4U)
+/*! M7_APC_AC_R2_CTRL
+ *  0b00..No access protection
+ *  0b01..M7 debug protection enabled
+ *  0b10..FlexSPI access protection
+ *  0b11..Both M7 debug and FlexSPI access are protected
+ */
 #define IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_MASK)
 #define IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_MASK  (0xC0U)
 #define IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_SHIFT (6U)
+/*! M7_APC_AC_R3_CTRL
+ *  0b00..No access protection
+ *  0b01..M7 debug protection enabled
+ *  0b10..FlexSPI access protection
+ *  0b11..Both M7 debug and FlexSPI access are protected
+ */
 #define IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_MASK)
 #define IOMUXC_GPR_GPR11_BEE_DE_RX_EN_MASK       (0xF00U)
 #define IOMUXC_GPR_GPR11_BEE_DE_RX_EN_SHIFT      (8U)
@@ -13498,18 +21566,38 @@ typedef struct {
 /*! @{ */
 #define IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_MASK (0x1U)
 #define IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_SHIFT (0U)
+/*! FLEXIO1_IPG_STOP_MODE
+ *  0b0..FlexIO1 is functional in Stop mode.
+ *  0b1..When this bit is equal to 1'b1 and ipg_stop is asserted, FlexIO1 is not functional in Stop mode.
+ */
 #define IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_MASK)
 #define IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_MASK   (0x2U)
 #define IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_SHIFT  (1U)
+/*! FLEXIO1_IPG_DOZE
+ *  0b0..FLEXIO1 is not in doze mode
+ *  0b1..FLEXIO1 is in doze mode
+ */
 #define IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_MASK)
 #define IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE_MASK (0x4U)
 #define IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE_SHIFT (2U)
+/*! FLEXIO2_IPG_STOP_MODE
+ *  0b0..FlexIO2 is functional in Stop mode.
+ *  0b1..When this bit is equal to 1'b1 and ipg_stop is asserted, FlexIO2 is not functional in Stop mode.
+ */
 #define IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE_MASK)
 #define IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE_MASK   (0x8U)
 #define IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE_SHIFT  (3U)
+/*! FLEXIO2_IPG_DOZE
+ *  0b0..FLEXIO2 is not in doze mode
+ *  0b1..FLEXIO2 is in doze mode
+ */
 #define IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE_MASK)
 #define IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_MASK (0x10U)
 #define IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_SHIFT (4U)
+/*! ACMP_IPG_STOP_MODE
+ *  0b0..ACMP is functional in Stop mode.
+ *  0b1..When this bit is equal to 1'b1 and ipg_stop is asserted, ACMP is not functional in Stop mode.
+ */
 #define IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_MASK)
 /*! @} */
 
@@ -13517,15 +21605,31 @@ typedef struct {
 /*! @{ */
 #define IOMUXC_GPR_GPR13_ARCACHE_USDHC_MASK      (0x1U)
 #define IOMUXC_GPR_GPR13_ARCACHE_USDHC_SHIFT     (0U)
+/*! ARCACHE_USDHC
+ *  0b0..Cacheable attribute is off for read transactions.
+ *  0b1..Cacheable attribute is on for read transactions.
+ */
 #define IOMUXC_GPR_GPR13_ARCACHE_USDHC(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_ARCACHE_USDHC_SHIFT)) & IOMUXC_GPR_GPR13_ARCACHE_USDHC_MASK)
 #define IOMUXC_GPR_GPR13_AWCACHE_USDHC_MASK      (0x2U)
 #define IOMUXC_GPR_GPR13_AWCACHE_USDHC_SHIFT     (1U)
+/*! AWCACHE_USDHC
+ *  0b0..Cacheable attribute is off for write transactions.
+ *  0b1..Cacheable attribute is on for write transactions.
+ */
 #define IOMUXC_GPR_GPR13_AWCACHE_USDHC(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_AWCACHE_USDHC_SHIFT)) & IOMUXC_GPR_GPR13_AWCACHE_USDHC_MASK)
 #define IOMUXC_GPR_GPR13_CACHE_ENET_MASK         (0x80U)
 #define IOMUXC_GPR_GPR13_CACHE_ENET_SHIFT        (7U)
+/*! CACHE_ENET
+ *  0b0..Cacheable attribute is off for read/write transactions.
+ *  0b1..Cacheable attribute is on for read/write transactions.
+ */
 #define IOMUXC_GPR_GPR13_CACHE_ENET(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_CACHE_ENET_SHIFT)) & IOMUXC_GPR_GPR13_CACHE_ENET_MASK)
 #define IOMUXC_GPR_GPR13_CACHE_USB_MASK          (0x2000U)
 #define IOMUXC_GPR_GPR13_CACHE_USB_SHIFT         (13U)
+/*! CACHE_USB
+ *  0b0..Cacheable attribute is off for read/write transactions.
+ *  0b1..Cacheable attribute is on for read/write transactions.
+ */
 #define IOMUXC_GPR_GPR13_CACHE_USB(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_CACHE_USB_SHIFT)) & IOMUXC_GPR_GPR13_CACHE_USB_MASK)
 /*! @} */
 
@@ -13533,45 +21637,115 @@ typedef struct {
 /*! @{ */
 #define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_MASK (0x1U)
 #define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_SHIFT (0U)
+/*! ACMP1_CMP_IGEN_TRIM_DN
+ *  0b0..no reduce
+ *  0b1..reduces
+ */
 #define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_MASK)
 #define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_MASK (0x2U)
 #define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_SHIFT (1U)
+/*! ACMP2_CMP_IGEN_TRIM_DN
+ *  0b0..no reduce
+ *  0b1..reduces
+ */
 #define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_MASK)
 #define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_MASK (0x4U)
 #define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_SHIFT (2U)
+/*! ACMP3_CMP_IGEN_TRIM_DN
+ *  0b0..no reduce
+ *  0b1..reduces
+ */
 #define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_MASK)
 #define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_MASK (0x8U)
 #define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_SHIFT (3U)
+/*! ACMP4_CMP_IGEN_TRIM_DN
+ *  0b0..no reduce
+ *  0b1..reduces
+ */
 #define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_MASK)
 #define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_MASK (0x10U)
 #define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_SHIFT (4U)
+/*! ACMP1_CMP_IGEN_TRIM_UP
+ *  0b0..no increase
+ *  0b1..increases
+ */
 #define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_SHIFT)) & IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_MASK)
 #define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_MASK (0x20U)
 #define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_SHIFT (5U)
+/*! ACMP2_CMP_IGEN_TRIM_UP
+ *  0b0..no increase
+ *  0b1..increases
+ */
 #define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_SHIFT)) & IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_MASK)
 #define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_MASK (0x40U)
 #define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_SHIFT (6U)
+/*! ACMP3_CMP_IGEN_TRIM_UP
+ *  0b0..no increase
+ *  0b1..increases
+ */
 #define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_SHIFT)) & IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_MASK)
 #define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_MASK (0x80U)
 #define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_SHIFT (7U)
+/*! ACMP4_CMP_IGEN_TRIM_UP
+ *  0b0..no increase
+ *  0b1..increases
+ */
 #define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_SHIFT)) & IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_MASK)
 #define IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_MASK (0x100U)
 #define IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_SHIFT (8U)
+/*! ACMP1_SAMPLE_SYNC_EN
+ *  0b0..select XBAR output
+ *  0b1..select synced sample_lv
+ */
 #define IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_MASK)
 #define IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_MASK (0x200U)
 #define IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_SHIFT (9U)
+/*! ACMP2_SAMPLE_SYNC_EN
+ *  0b0..select XBAR output
+ *  0b1..select synced sample_lv
+ */
 #define IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_MASK)
 #define IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_MASK (0x400U)
 #define IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_SHIFT (10U)
+/*! ACMP3_SAMPLE_SYNC_EN
+ *  0b0..select XBAR output
+ *  0b1..select synced sample_lv
+ */
 #define IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_MASK)
 #define IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_MASK (0x800U)
 #define IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_SHIFT (11U)
+/*! ACMP4_SAMPLE_SYNC_EN
+ *  0b0..select XBAR output
+ *  0b1..select synced sample_lv
+ */
 #define IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_MASK)
 #define IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_MASK      (0xF0000U)
 #define IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_SHIFT     (16U)
+/*! CM7_CFGITCMSZ
+ *  0b0000..0 KB (No ITCM)
+ *  0b0011..4 KB
+ *  0b0100..8 KB
+ *  0b0101..16 KB
+ *  0b0110..32 KB
+ *  0b0111..64 KB
+ *  0b1000..128 KB
+ *  0b1001..256 KB
+ *  0b1010..512 KB
+ */
 #define IOMUXC_GPR_GPR14_CM7_CFGITCMSZ(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_SHIFT)) & IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_MASK)
 #define IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_MASK      (0xF00000U)
 #define IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_SHIFT     (20U)
+/*! CM7_CFGDTCMSZ
+ *  0b0000..0 KB (No DTCM)
+ *  0b0011..4 KB
+ *  0b0100..8 KB
+ *  0b0101..16 KB
+ *  0b0110..32 KB
+ *  0b0111..64 KB
+ *  0b1000..128 KB
+ *  0b1001..256 KB
+ *  0b1010..512 KB
+ */
 #define IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_SHIFT)) & IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_MASK)
 /*! @} */
 
@@ -13579,16 +21753,25 @@ typedef struct {
 /*! @{ */
 #define IOMUXC_GPR_GPR16_INIT_ITCM_EN_MASK       (0x1U)
 #define IOMUXC_GPR_GPR16_INIT_ITCM_EN_SHIFT      (0U)
+/*! INIT_ITCM_EN
+ *  0b0..ITCM is disabled
+ *  0b1..ITCM is enabled
+ */
 #define IOMUXC_GPR_GPR16_INIT_ITCM_EN(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_INIT_ITCM_EN_SHIFT)) & IOMUXC_GPR_GPR16_INIT_ITCM_EN_MASK)
 #define IOMUXC_GPR_GPR16_INIT_DTCM_EN_MASK       (0x2U)
 #define IOMUXC_GPR_GPR16_INIT_DTCM_EN_SHIFT      (1U)
+/*! INIT_DTCM_EN
+ *  0b0..DTCM is disabled
+ *  0b1..DTCM is enabled
+ */
 #define IOMUXC_GPR_GPR16_INIT_DTCM_EN(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_INIT_DTCM_EN_SHIFT)) & IOMUXC_GPR_GPR16_INIT_DTCM_EN_MASK)
 #define IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_MASK (0x4U)
 #define IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_SHIFT (2U)
+/*! FLEXRAM_BANK_CFG_SEL
+ *  0b0..use fuse value to config
+ *  0b1..use FLEXRAM_BANK_CFG to config
+ */
 #define IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_SHIFT)) & IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_MASK)
-#define IOMUXC_GPR_GPR16_CM7_INIT_VTOR_MASK      (0xFFFFFF80U)
-#define IOMUXC_GPR_GPR16_CM7_INIT_VTOR_SHIFT     (7U)
-#define IOMUXC_GPR_GPR16_CM7_INIT_VTOR(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_CM7_INIT_VTOR_SHIFT)) & IOMUXC_GPR_GPR16_CM7_INIT_VTOR_MASK)
 /*! @} */
 
 /*! @name GPR17 - GPR17 General Purpose Register */
@@ -13602,6 +21785,10 @@ typedef struct {
 /*! @{ */
 #define IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_MASK (0x1U)
 #define IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_SHIFT (0U)
+/*! LOCK_M7_APC_AC_R0_BOT
+ *  0b0..Register field [31:1] is not locked
+ *  0b1..Register field [31:1] is locked (read access only)
+ */
 #define IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_SHIFT)) & IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_MASK)
 #define IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_MASK   (0xFFFFFFF8U)
 #define IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_SHIFT  (3U)
@@ -13612,6 +21799,10 @@ typedef struct {
 /*! @{ */
 #define IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_MASK (0x1U)
 #define IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_SHIFT (0U)
+/*! LOCK_M7_APC_AC_R0_TOP
+ *  0b0..Register field [31:1] is not locked
+ *  0b1..Register field [31:1] is locked (read access only)
+ */
 #define IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_SHIFT)) & IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_MASK)
 #define IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_MASK   (0xFFFFFFF8U)
 #define IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_SHIFT  (3U)
@@ -13622,6 +21813,10 @@ typedef struct {
 /*! @{ */
 #define IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_MASK (0x1U)
 #define IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_SHIFT (0U)
+/*! LOCK_M7_APC_AC_R1_BOT
+ *  0b0..Register field [31:1] is not locked
+ *  0b1..Register field [31:1] is locked (read access only)
+ */
 #define IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_SHIFT)) & IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_MASK)
 #define IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_MASK   (0xFFFFFFF8U)
 #define IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_SHIFT  (3U)
@@ -13632,6 +21827,10 @@ typedef struct {
 /*! @{ */
 #define IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_MASK (0x1U)
 #define IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_SHIFT (0U)
+/*! LOCK_M7_APC_AC_R1_TOP
+ *  0b0..Register field [31:1] is not locked
+ *  0b1..Register field [31:1] is locked (read access only)
+ */
 #define IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_SHIFT)) & IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_MASK)
 #define IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_MASK   (0xFFFFFFF8U)
 #define IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_SHIFT  (3U)
@@ -13642,6 +21841,10 @@ typedef struct {
 /*! @{ */
 #define IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_MASK (0x1U)
 #define IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_SHIFT (0U)
+/*! LOCK_M7_APC_AC_R2_BOT
+ *  0b0..Register field [31:1] is not locked
+ *  0b1..Register field [31:1] is locked (read access only)
+ */
 #define IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_SHIFT)) & IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_MASK)
 #define IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_MASK   (0xFFFFFFF8U)
 #define IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_SHIFT  (3U)
@@ -13650,9 +21853,13 @@ typedef struct {
 
 /*! @name GPR23 - GPR23 General Purpose Register */
 /*! @{ */
-#define IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R1_TOP_MASK (0x1U)
-#define IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R1_TOP_SHIFT (0U)
-#define IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R1_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R1_TOP_SHIFT)) & IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R1_TOP_MASK)
+#define IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP_MASK (0x1U)
+#define IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP_SHIFT (0U)
+/*! LOCK_M7_APC_AC_R2_TOP
+ *  0b0..Register field [31:1] is not locked
+ *  0b1..Register field [31:1] is locked (read access only)
+ */
+#define IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP_SHIFT)) & IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP_MASK)
 #define IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_MASK   (0xFFFFFFF8U)
 #define IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_SHIFT  (3U)
 #define IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_SHIFT)) & IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_MASK)
@@ -13662,16 +21869,24 @@ typedef struct {
 /*! @{ */
 #define IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_MASK (0x1U)
 #define IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_SHIFT (0U)
+/*! LOCK_M7_APC_AC_R3_BOT
+ *  0b0..Register field [31:1] is not locked
+ *  0b1..Register field [31:1] is locked (read access only)
+ */
 #define IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_SHIFT)) & IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_MASK)
-#define IOMUXC_GPR_GPR24_M7_APC_AC_R2_BOT_MASK   (0xFFFFFFF8U)
-#define IOMUXC_GPR_GPR24_M7_APC_AC_R2_BOT_SHIFT  (3U)
-#define IOMUXC_GPR_GPR24_M7_APC_AC_R2_BOT(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_M7_APC_AC_R2_BOT_SHIFT)) & IOMUXC_GPR_GPR24_M7_APC_AC_R2_BOT_MASK)
+#define IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT_MASK   (0xFFFFFFF8U)
+#define IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT_SHIFT  (3U)
+#define IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT_SHIFT)) & IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT_MASK)
 /*! @} */
 
 /*! @name GPR25 - GPR25 General Purpose Register */
 /*! @{ */
 #define IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_MASK (0x1U)
 #define IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_SHIFT (0U)
+/*! LOCK_M7_APC_AC_R3_TOP
+ *  0b0..Register field [31:1] is not locked
+ *  0b1..Register field [31:1] is locked (read access only)
+ */
 #define IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_SHIFT)) & IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_MASK)
 #define IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_MASK   (0xFFFFFFF8U)
 #define IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_SHIFT  (3U)
@@ -13734,9 +21949,17 @@ typedef struct {
 /*! @{ */
 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_MASK (0x7U)
 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_SHIFT (0U)
+/*! MUX_MODE - MUX Mode Select Field.
+ *  0b101..Select mux mode: ALT5 mux port: GPIO5_IO00 of instance: gpio5
+ *  0b111..Select mux mode: ALT7 mux port: NMI_GLUE_NMI of instance: nmi_glue
+ */
 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_MASK)
 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_MASK (0x10U)
 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_SHIFT (4U)
+/*! SION - Software Input On Field.
+ *  0b1..Force input path of pad WAKEUP
+ *  0b0..Input Path is determined by functionality
+ */
 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_MASK)
 /*! @} */
 
@@ -13744,9 +21967,17 @@ typedef struct {
 /*! @{ */
 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_MASK (0x7U)
 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_SHIFT (0U)
+/*! MUX_MODE - MUX Mode Select Field.
+ *  0b000..Select mux mode: ALT0 mux port: SNVS_LP_PMIC_ON_REQ of instance: snvs_lp
+ *  0b101..Select mux mode: ALT5 mux port: GPIO5_IO01 of instance: gpio5
+ */
 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_MASK)
 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_MASK (0x10U)
 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_SHIFT (4U)
+/*! SION - Software Input On Field.
+ *  0b1..Force input path of pad PMIC_ON_REQ
+ *  0b0..Input Path is determined by functionality
+ */
 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_MASK)
 /*! @} */
 
@@ -13754,9 +21985,17 @@ typedef struct {
 /*! @{ */
 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_MASK (0x7U)
 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_SHIFT (0U)
+/*! MUX_MODE - MUX Mode Select Field.
+ *  0b000..Select mux mode: ALT0 mux port: CCM_PMIC_VSTBY_REQ of instance: ccm
+ *  0b101..Select mux mode: ALT5 mux port: GPIO5_IO02 of instance: gpio5
+ */
 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_MASK)
 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_MASK (0x10U)
 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_SHIFT (4U)
+/*! SION - Software Input On Field.
+ *  0b1..Force input path of pad PMIC_STBY_REQ
+ *  0b0..Input Path is determined by functionality
+ */
 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_MASK)
 /*! @} */
 
@@ -13764,27 +22003,66 @@ typedef struct {
 /*! @{ */
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_MASK (0x1U)
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_SHIFT (0U)
+/*! SRE - Slew Rate Field
+ *  0b0..Slow Slew Rate
+ *  0b1..Fast Slew Rate
+ */
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_MASK)
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_MASK (0x38U)
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_SHIFT (3U)
+/*! DSE - Drive Strength Field
+ *  0b000..output driver disabled;
+ *  0b001..R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR)
+ *  0b010..R0/2
+ *  0b011..R0/3
+ *  0b100..R0/4
+ *  0b101..R0/5
+ *  0b110..R0/6
+ *  0b111..R0/7
+ */
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_MASK)
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_MASK (0xC0U)
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_SHIFT (6U)
+/*! SPEED - Speed Field
+ *  0b10..medium(100MHz)
+ */
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_MASK)
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_MASK (0x800U)
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_SHIFT (11U)
+/*! ODE - Open Drain Enable Field
+ *  0b0..Open Drain Disabled
+ *  0b1..Open Drain Enabled
+ */
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_MASK)
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_MASK (0x1000U)
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_SHIFT (12U)
+/*! PKE - Pull / Keep Enable Field
+ *  0b0..Pull/Keeper Disabled
+ *  0b1..Pull/Keeper Enabled
+ */
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_MASK)
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_MASK (0x2000U)
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_SHIFT (13U)
+/*! PUE - Pull / Keep Select Field
+ *  0b0..Keeper
+ *  0b1..Pull
+ */
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_MASK)
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_MASK (0xC000U)
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_SHIFT (14U)
+/*! PUS - Pull Up / Down Config. Field
+ *  0b00..100K Ohm Pull Down
+ *  0b01..47K Ohm Pull Up
+ *  0b10..100K Ohm Pull Up
+ *  0b11..22K Ohm Pull Up
+ */
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_MASK)
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_MASK (0x10000U)
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_SHIFT (16U)
+/*! HYS - Hyst. Enable Field
+ *  0b0..Hysteresis Disabled
+ *  0b1..Hysteresis Enabled
+ */
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_MASK)
 /*! @} */
 
@@ -13792,27 +22070,66 @@ typedef struct {
 /*! @{ */
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_MASK (0x1U)
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_SHIFT (0U)
+/*! SRE - Slew Rate Field
+ *  0b0..Slow Slew Rate
+ *  0b1..Fast Slew Rate
+ */
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_MASK)
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_MASK (0x38U)
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_SHIFT (3U)
+/*! DSE - Drive Strength Field
+ *  0b000..output driver disabled;
+ *  0b001..R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR)
+ *  0b010..R0/2
+ *  0b011..R0/3
+ *  0b100..R0/4
+ *  0b101..R0/5
+ *  0b110..R0/6
+ *  0b111..R0/7
+ */
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_MASK)
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_MASK (0xC0U)
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_SHIFT (6U)
+/*! SPEED - Speed Field
+ *  0b10..medium(100MHz)
+ */
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_MASK)
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_MASK (0x800U)
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_SHIFT (11U)
+/*! ODE - Open Drain Enable Field
+ *  0b0..Open Drain Disabled
+ *  0b1..Open Drain Enabled
+ */
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_MASK)
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_MASK (0x1000U)
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_SHIFT (12U)
+/*! PKE - Pull / Keep Enable Field
+ *  0b0..Pull/Keeper Disabled
+ *  0b1..Pull/Keeper Enabled
+ */
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_MASK)
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_MASK (0x2000U)
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_SHIFT (13U)
+/*! PUE - Pull / Keep Select Field
+ *  0b0..Keeper
+ *  0b1..Pull
+ */
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_MASK)
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_MASK (0xC000U)
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_SHIFT (14U)
+/*! PUS - Pull Up / Down Config. Field
+ *  0b00..100K Ohm Pull Down
+ *  0b01..47K Ohm Pull Up
+ *  0b10..100K Ohm Pull Up
+ *  0b11..22K Ohm Pull Up
+ */
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_MASK)
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_MASK (0x10000U)
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_SHIFT (16U)
+/*! HYS - Hyst. Enable Field
+ *  0b0..Hysteresis Disabled
+ *  0b1..Hysteresis Enabled
+ */
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_MASK)
 /*! @} */
 
@@ -13820,27 +22137,66 @@ typedef struct {
 /*! @{ */
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_MASK (0x1U)
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_SHIFT (0U)
+/*! SRE - Slew Rate Field
+ *  0b0..Slow Slew Rate
+ *  0b1..Fast Slew Rate
+ */
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_MASK)
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_MASK (0x38U)
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_SHIFT (3U)
+/*! DSE - Drive Strength Field
+ *  0b000..output driver disabled;
+ *  0b001..R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR)
+ *  0b010..R0/2
+ *  0b011..R0/3
+ *  0b100..R0/4
+ *  0b101..R0/5
+ *  0b110..R0/6
+ *  0b111..R0/7
+ */
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_MASK)
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_MASK (0xC0U)
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_SHIFT (6U)
+/*! SPEED - Speed Field
+ *  0b10..medium(100MHz)
+ */
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_MASK)
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_MASK (0x800U)
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_SHIFT (11U)
+/*! ODE - Open Drain Enable Field
+ *  0b0..Open Drain Disabled
+ *  0b1..Open Drain Enabled
+ */
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_MASK)
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_MASK (0x1000U)
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_SHIFT (12U)
+/*! PKE - Pull / Keep Enable Field
+ *  0b0..Pull/Keeper Disabled
+ *  0b1..Pull/Keeper Enabled
+ */
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_MASK)
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_MASK (0x2000U)
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_SHIFT (13U)
+/*! PUE - Pull / Keep Select Field
+ *  0b0..Keeper
+ *  0b1..Pull
+ */
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_MASK)
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_MASK (0xC000U)
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_SHIFT (14U)
+/*! PUS - Pull Up / Down Config. Field
+ *  0b00..100K Ohm Pull Down
+ *  0b01..47K Ohm Pull Up
+ *  0b10..100K Ohm Pull Up
+ *  0b11..22K Ohm Pull Up
+ */
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_MASK)
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_MASK (0x10000U)
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_SHIFT (16U)
+/*! HYS - Hyst. Enable Field
+ *  0b0..Hysteresis Disabled
+ *  0b1..Hysteresis Enabled
+ */
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_MASK)
 /*! @} */
 
@@ -13848,27 +22204,66 @@ typedef struct {
 /*! @{ */
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_MASK (0x1U)
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_SHIFT (0U)
+/*! SRE - Slew Rate Field
+ *  0b0..Slow Slew Rate
+ *  0b1..Fast Slew Rate
+ */
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_MASK)
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE_MASK (0x38U)
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE_SHIFT (3U)
+/*! DSE - Drive Strength Field
+ *  0b000..output driver disabled;
+ *  0b001..R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR)
+ *  0b010..R0/2
+ *  0b011..R0/3
+ *  0b100..R0/4
+ *  0b101..R0/5
+ *  0b110..R0/6
+ *  0b111..R0/7
+ */
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE_MASK)
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED_MASK (0xC0U)
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED_SHIFT (6U)
+/*! SPEED - Speed Field
+ *  0b10..medium(100MHz)
+ */
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED_MASK)
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE_MASK (0x800U)
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE_SHIFT (11U)
+/*! ODE - Open Drain Enable Field
+ *  0b0..Open Drain Disabled
+ *  0b1..Open Drain Enabled
+ */
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE_MASK)
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE_MASK (0x1000U)
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE_SHIFT (12U)
+/*! PKE - Pull / Keep Enable Field
+ *  0b0..Pull/Keeper Disabled
+ *  0b1..Pull/Keeper Enabled
+ */
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE_MASK)
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE_MASK (0x2000U)
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE_SHIFT (13U)
+/*! PUE - Pull / Keep Select Field
+ *  0b0..Keeper
+ *  0b1..Pull
+ */
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE_MASK)
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS_MASK (0xC000U)
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS_SHIFT (14U)
+/*! PUS - Pull Up / Down Config. Field
+ *  0b00..100K Ohm Pull Down
+ *  0b01..47K Ohm Pull Up
+ *  0b10..100K Ohm Pull Up
+ *  0b11..22K Ohm Pull Up
+ */
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS_MASK)
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_MASK (0x10000U)
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_SHIFT (16U)
+/*! HYS - Hyst. Enable Field
+ *  0b0..Hysteresis Disabled
+ *  0b1..Hysteresis Enabled
+ */
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_MASK)
 /*! @} */
 
@@ -13876,27 +22271,66 @@ typedef struct {
 /*! @{ */
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_MASK (0x1U)
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_SHIFT (0U)
+/*! SRE - Slew Rate Field
+ *  0b0..Slow Slew Rate
+ *  0b1..Fast Slew Rate
+ */
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_MASK)
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_MASK (0x38U)
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_SHIFT (3U)
+/*! DSE - Drive Strength Field
+ *  0b000..output driver disabled;
+ *  0b001..R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR)
+ *  0b010..R0/2
+ *  0b011..R0/3
+ *  0b100..R0/4
+ *  0b101..R0/5
+ *  0b110..R0/6
+ *  0b111..R0/7
+ */
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_MASK)
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_MASK (0xC0U)
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_SHIFT (6U)
+/*! SPEED - Speed Field
+ *  0b10..medium(100MHz)
+ */
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_MASK)
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_MASK (0x800U)
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_SHIFT (11U)
+/*! ODE - Open Drain Enable Field
+ *  0b0..Open Drain Disabled
+ *  0b1..Open Drain Enabled
+ */
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_MASK)
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_MASK (0x1000U)
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_SHIFT (12U)
+/*! PKE - Pull / Keep Enable Field
+ *  0b0..Pull/Keeper Disabled
+ *  0b1..Pull/Keeper Enabled
+ */
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_MASK)
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_MASK (0x2000U)
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_SHIFT (13U)
+/*! PUE - Pull / Keep Select Field
+ *  0b0..Keeper
+ *  0b1..Pull
+ */
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_MASK)
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_MASK (0xC000U)
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_SHIFT (14U)
+/*! PUS - Pull Up / Down Config. Field
+ *  0b00..100K Ohm Pull Down
+ *  0b01..47K Ohm Pull Up
+ *  0b10..100K Ohm Pull Up
+ *  0b11..22K Ohm Pull Up
+ */
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_MASK)
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_MASK (0x10000U)
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_SHIFT (16U)
+/*! HYS - Hyst. Enable Field
+ *  0b0..Hysteresis Disabled
+ *  0b1..Hysteresis Enabled
+ */
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_MASK)
 /*! @} */
 
@@ -13904,27 +22338,66 @@ typedef struct {
 /*! @{ */
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_MASK (0x1U)
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_SHIFT (0U)
+/*! SRE - Slew Rate Field
+ *  0b0..Slow Slew Rate
+ *  0b1..Fast Slew Rate
+ */
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_MASK)
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE_MASK (0x38U)
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE_SHIFT (3U)
+/*! DSE - Drive Strength Field
+ *  0b000..output driver disabled;
+ *  0b001..R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR)
+ *  0b010..R0/2
+ *  0b011..R0/3
+ *  0b100..R0/4
+ *  0b101..R0/5
+ *  0b110..R0/6
+ *  0b111..R0/7
+ */
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE_MASK)
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED_MASK (0xC0U)
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED_SHIFT (6U)
+/*! SPEED - Speed Field
+ *  0b10..medium(100MHz)
+ */
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED_MASK)
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE_MASK (0x800U)
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE_SHIFT (11U)
+/*! ODE - Open Drain Enable Field
+ *  0b0..Open Drain Disabled
+ *  0b1..Open Drain Enabled
+ */
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE_MASK)
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE_MASK (0x1000U)
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE_SHIFT (12U)
+/*! PKE - Pull / Keep Enable Field
+ *  0b0..Pull/Keeper Disabled
+ *  0b1..Pull/Keeper Enabled
+ */
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE_MASK)
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE_MASK (0x2000U)
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE_SHIFT (13U)
+/*! PUE - Pull / Keep Select Field
+ *  0b0..Keeper
+ *  0b1..Pull
+ */
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE_MASK)
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS_MASK (0xC000U)
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS_SHIFT (14U)
+/*! PUS - Pull Up / Down Config. Field
+ *  0b00..100K Ohm Pull Down
+ *  0b01..47K Ohm Pull Up
+ *  0b10..100K Ohm Pull Up
+ *  0b11..22K Ohm Pull Up
+ */
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS_MASK)
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_MASK (0x10000U)
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_SHIFT (16U)
+/*! HYS - Hyst. Enable Field
+ *  0b0..Hysteresis Disabled
+ *  0b1..Hysteresis Enabled
+ */
 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_MASK)
 /*! @} */
 
@@ -14051,9 +22524,17 @@ typedef struct {
 /*! @{ */
 #define KPP_KPCR_KRE_MASK                        (0xFFU)
 #define KPP_KPCR_KRE_SHIFT                       (0U)
+/*! KRE
+ *  0b00000000..Row is not included in the keypad key press detect.
+ *  0b00000001..Row is included in the keypad key press detect.
+ */
 #define KPP_KPCR_KRE(x)                          (((uint16_t)(((uint16_t)(x)) << KPP_KPCR_KRE_SHIFT)) & KPP_KPCR_KRE_MASK)
 #define KPP_KPCR_KCO_MASK                        (0xFF00U)
 #define KPP_KPCR_KCO_SHIFT                       (8U)
+/*! KCO
+ *  0b00000000..Column strobe output is totem pole drive.
+ *  0b00000001..Column strobe output is open drain.
+ */
 #define KPP_KPCR_KCO(x)                          (((uint16_t)(((uint16_t)(x)) << KPP_KPCR_KCO_SHIFT)) & KPP_KPCR_KCO_MASK)
 /*! @} */
 
@@ -14061,21 +22542,45 @@ typedef struct {
 /*! @{ */
 #define KPP_KPSR_KPKD_MASK                       (0x1U)
 #define KPP_KPSR_KPKD_SHIFT                      (0U)
+/*! KPKD
+ *  0b0..No key presses detected
+ *  0b1..A key has been depressed
+ */
 #define KPP_KPSR_KPKD(x)                         (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KPKD_SHIFT)) & KPP_KPSR_KPKD_MASK)
 #define KPP_KPSR_KPKR_MASK                       (0x2U)
 #define KPP_KPSR_KPKR_SHIFT                      (1U)
+/*! KPKR
+ *  0b0..No key release detected
+ *  0b1..All keys have been released
+ */
 #define KPP_KPSR_KPKR(x)                         (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KPKR_SHIFT)) & KPP_KPSR_KPKR_MASK)
 #define KPP_KPSR_KDSC_MASK                       (0x4U)
 #define KPP_KPSR_KDSC_SHIFT                      (2U)
+/*! KDSC
+ *  0b0..No effect
+ *  0b1..Set bits that clear the keypad depress synchronizer chain
+ */
 #define KPP_KPSR_KDSC(x)                         (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KDSC_SHIFT)) & KPP_KPSR_KDSC_MASK)
 #define KPP_KPSR_KRSS_MASK                       (0x8U)
 #define KPP_KPSR_KRSS_SHIFT                      (3U)
+/*! KRSS
+ *  0b0..No effect
+ *  0b1..Set bits which sets keypad release synchronizer chain
+ */
 #define KPP_KPSR_KRSS(x)                         (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KRSS_SHIFT)) & KPP_KPSR_KRSS_MASK)
 #define KPP_KPSR_KDIE_MASK                       (0x100U)
 #define KPP_KPSR_KDIE_SHIFT                      (8U)
+/*! KDIE
+ *  0b0..No interrupt request is generated when KPKD is set.
+ *  0b1..An interrupt request is generated when KPKD is set.
+ */
 #define KPP_KPSR_KDIE(x)                         (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KDIE_SHIFT)) & KPP_KPSR_KDIE_MASK)
 #define KPP_KPSR_KRIE_MASK                       (0x200U)
 #define KPP_KPSR_KRIE_SHIFT                      (9U)
+/*! KRIE
+ *  0b0..No interrupt request is generated when KPKR is set.
+ *  0b1..An interrupt request is generated when KPKR is set.
+ */
 #define KPP_KPSR_KRIE(x)                         (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KRIE_SHIFT)) & KPP_KPSR_KRIE_MASK)
 /*! @} */
 
@@ -14083,9 +22588,17 @@ typedef struct {
 /*! @{ */
 #define KPP_KDDR_KRDD_MASK                       (0xFFU)
 #define KPP_KDDR_KRDD_SHIFT                      (0U)
+/*! KRDD
+ *  0b00000000..ROWn pin configured as an input.
+ *  0b00000001..ROWn pin configured as an output.
+ */
 #define KPP_KDDR_KRDD(x)                         (((uint16_t)(((uint16_t)(x)) << KPP_KDDR_KRDD_SHIFT)) & KPP_KDDR_KRDD_MASK)
 #define KPP_KDDR_KCDD_MASK                       (0xFF00U)
 #define KPP_KDDR_KCDD_SHIFT                      (8U)
+/*! KCDD
+ *  0b00000000..COLn pin is configured as an input.
+ *  0b00000001..COLn pin is configured as an output.
+ */
 #define KPP_KDDR_KCDD(x)                         (((uint16_t)(((uint16_t)(x)) << KPP_KDDR_KCDD_SHIFT)) & KPP_KDDR_KCDD_MASK)
 /*! @} */
 
@@ -14219,9 +22732,18 @@ typedef struct {
 #define LCDIF_CTRL_RUN(x)                        (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_RUN_SHIFT)) & LCDIF_CTRL_RUN_MASK)
 #define LCDIF_CTRL_DATA_FORMAT_24_BIT_MASK       (0x2U)
 #define LCDIF_CTRL_DATA_FORMAT_24_BIT_SHIFT      (1U)
+/*! DATA_FORMAT_24_BIT
+ *  0b0..Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits.
+ *  0b1..Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in
+ *       each byte do not contain any useful data, and should be dropped.
+ */
 #define LCDIF_CTRL_DATA_FORMAT_24_BIT(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_24_BIT_MASK)
 #define LCDIF_CTRL_DATA_FORMAT_18_BIT_MASK       (0x4U)
 #define LCDIF_CTRL_DATA_FORMAT_18_BIT_SHIFT      (2U)
+/*! DATA_FORMAT_18_BIT
+ *  0b0..Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data.
+ *  0b1..Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data.
+ */
 #define LCDIF_CTRL_DATA_FORMAT_18_BIT(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_18_BIT_MASK)
 #define LCDIF_CTRL_DATA_FORMAT_16_BIT_MASK       (0x8U)
 #define LCDIF_CTRL_DATA_FORMAT_16_BIT_SHIFT      (3U)
@@ -14237,15 +22759,43 @@ typedef struct {
 #define LCDIF_CTRL_ENABLE_PXP_HANDSHAKE(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_MASK)
 #define LCDIF_CTRL_WORD_LENGTH_MASK              (0x300U)
 #define LCDIF_CTRL_WORD_LENGTH_SHIFT             (8U)
+/*! WORD_LENGTH
+ *  0b00..Input data is 16 bits per pixel.
+ *  0b01..Input data is 8 bits wide.
+ *  0b10..Input data is 18 bits per pixel.
+ *  0b11..Input data is 24 bits per pixel.
+ */
 #define LCDIF_CTRL_WORD_LENGTH(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_WORD_LENGTH_MASK)
 #define LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK        (0xC00U)
 #define LCDIF_CTRL_LCD_DATABUS_WIDTH_SHIFT       (10U)
+/*! LCD_DATABUS_WIDTH
+ *  0b00..16-bit data bus mode.
+ *  0b01..8-bit data bus mode.
+ *  0b10..18-bit data bus mode.
+ *  0b11..24-bit data bus mode.
+ */
 #define LCDIF_CTRL_LCD_DATABUS_WIDTH(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK)
 #define LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK         (0x3000U)
 #define LCDIF_CTRL_CSC_DATA_SWIZZLE_SHIFT        (12U)
+/*! CSC_DATA_SWIZZLE
+ *  0b00..No byte swapping.(Little endian)
+ *  0b00..Little Endian byte ordering (same as NO_SWAP).
+ *  0b01..Big Endian swap (swap bytes 0,3 and 1,2).
+ *  0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian).
+ *  0b10..Swap half-words.
+ *  0b11..Swap bytes within each half-word.
+ */
 #define LCDIF_CTRL_CSC_DATA_SWIZZLE(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK)
 #define LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK       (0xC000U)
 #define LCDIF_CTRL_INPUT_DATA_SWIZZLE_SHIFT      (14U)
+/*! INPUT_DATA_SWIZZLE
+ *  0b00..No byte swapping.(Little endian)
+ *  0b00..Little Endian byte ordering (same as NO_SWAP).
+ *  0b01..Big Endian swap (swap bytes 0,3 and 1,2).
+ *  0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian).
+ *  0b10..Swap half-words.
+ *  0b11..Swap bytes within each half-word.
+ */
 #define LCDIF_CTRL_INPUT_DATA_SWIZZLE(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK)
 #define LCDIF_CTRL_DOTCLK_MODE_MASK              (0x20000U)
 #define LCDIF_CTRL_DOTCLK_MODE_SHIFT             (17U)
@@ -14258,6 +22808,10 @@ typedef struct {
 #define LCDIF_CTRL_SHIFT_NUM_BITS(x)             (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_SHIFT_NUM_BITS_MASK)
 #define LCDIF_CTRL_DATA_SHIFT_DIR_MASK           (0x4000000U)
 #define LCDIF_CTRL_DATA_SHIFT_DIR_SHIFT          (26U)
+/*! DATA_SHIFT_DIR
+ *  0b0..Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits.
+ *  0b1..Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits.
+ */
 #define LCDIF_CTRL_DATA_SHIFT_DIR(x)             (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_DATA_SHIFT_DIR_MASK)
 #define LCDIF_CTRL_CLKGATE_MASK                  (0x40000000U)
 #define LCDIF_CTRL_CLKGATE_SHIFT                 (30U)
@@ -14274,9 +22828,18 @@ typedef struct {
 #define LCDIF_CTRL_SET_RUN(x)                    (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_RUN_SHIFT)) & LCDIF_CTRL_SET_RUN_MASK)
 #define LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_MASK   (0x2U)
 #define LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_SHIFT  (1U)
+/*! DATA_FORMAT_24_BIT
+ *  0b0..Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits.
+ *  0b1..Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in
+ *       each byte do not contain any useful data, and should be dropped.
+ */
 #define LCDIF_CTRL_SET_DATA_FORMAT_24_BIT(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_MASK)
 #define LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_MASK   (0x4U)
 #define LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_SHIFT  (2U)
+/*! DATA_FORMAT_18_BIT
+ *  0b0..Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data.
+ *  0b1..Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data.
+ */
 #define LCDIF_CTRL_SET_DATA_FORMAT_18_BIT(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_MASK)
 #define LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_MASK   (0x8U)
 #define LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_SHIFT  (3U)
@@ -14292,15 +22855,43 @@ typedef struct {
 #define LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE(x)   (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_MASK)
 #define LCDIF_CTRL_SET_WORD_LENGTH_MASK          (0x300U)
 #define LCDIF_CTRL_SET_WORD_LENGTH_SHIFT         (8U)
+/*! WORD_LENGTH
+ *  0b00..Input data is 16 bits per pixel.
+ *  0b01..Input data is 8 bits wide.
+ *  0b10..Input data is 18 bits per pixel.
+ *  0b11..Input data is 24 bits per pixel.
+ */
 #define LCDIF_CTRL_SET_WORD_LENGTH(x)            (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_SET_WORD_LENGTH_MASK)
 #define LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_MASK    (0xC00U)
 #define LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_SHIFT   (10U)
+/*! LCD_DATABUS_WIDTH
+ *  0b00..16-bit data bus mode.
+ *  0b01..8-bit data bus mode.
+ *  0b10..18-bit data bus mode.
+ *  0b11..24-bit data bus mode.
+ */
 #define LCDIF_CTRL_SET_LCD_DATABUS_WIDTH(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_MASK)
 #define LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_MASK     (0x3000U)
 #define LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_SHIFT    (12U)
+/*! CSC_DATA_SWIZZLE
+ *  0b00..No byte swapping.(Little endian)
+ *  0b00..Little Endian byte ordering (same as NO_SWAP).
+ *  0b01..Big Endian swap (swap bytes 0,3 and 1,2).
+ *  0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian).
+ *  0b10..Swap half-words.
+ *  0b11..Swap bytes within each half-word.
+ */
 #define LCDIF_CTRL_SET_CSC_DATA_SWIZZLE(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_MASK)
 #define LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_MASK   (0xC000U)
 #define LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_SHIFT  (14U)
+/*! INPUT_DATA_SWIZZLE
+ *  0b00..No byte swapping.(Little endian)
+ *  0b00..Little Endian byte ordering (same as NO_SWAP).
+ *  0b01..Big Endian swap (swap bytes 0,3 and 1,2).
+ *  0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian).
+ *  0b10..Swap half-words.
+ *  0b11..Swap bytes within each half-word.
+ */
 #define LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_MASK)
 #define LCDIF_CTRL_SET_DOTCLK_MODE_MASK          (0x20000U)
 #define LCDIF_CTRL_SET_DOTCLK_MODE_SHIFT         (17U)
@@ -14313,6 +22904,10 @@ typedef struct {
 #define LCDIF_CTRL_SET_SHIFT_NUM_BITS(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_SET_SHIFT_NUM_BITS_MASK)
 #define LCDIF_CTRL_SET_DATA_SHIFT_DIR_MASK       (0x4000000U)
 #define LCDIF_CTRL_SET_DATA_SHIFT_DIR_SHIFT      (26U)
+/*! DATA_SHIFT_DIR
+ *  0b0..Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits.
+ *  0b1..Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits.
+ */
 #define LCDIF_CTRL_SET_DATA_SHIFT_DIR(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_SET_DATA_SHIFT_DIR_MASK)
 #define LCDIF_CTRL_SET_CLKGATE_MASK              (0x40000000U)
 #define LCDIF_CTRL_SET_CLKGATE_SHIFT             (30U)
@@ -14329,9 +22924,18 @@ typedef struct {
 #define LCDIF_CTRL_CLR_RUN(x)                    (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_RUN_SHIFT)) & LCDIF_CTRL_CLR_RUN_MASK)
 #define LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_MASK   (0x2U)
 #define LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_SHIFT  (1U)
+/*! DATA_FORMAT_24_BIT
+ *  0b0..Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits.
+ *  0b1..Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in
+ *       each byte do not contain any useful data, and should be dropped.
+ */
 #define LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_MASK)
 #define LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_MASK   (0x4U)
 #define LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_SHIFT  (2U)
+/*! DATA_FORMAT_18_BIT
+ *  0b0..Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data.
+ *  0b1..Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data.
+ */
 #define LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_MASK)
 #define LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_MASK   (0x8U)
 #define LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_SHIFT  (3U)
@@ -14347,15 +22951,43 @@ typedef struct {
 #define LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE(x)   (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_MASK)
 #define LCDIF_CTRL_CLR_WORD_LENGTH_MASK          (0x300U)
 #define LCDIF_CTRL_CLR_WORD_LENGTH_SHIFT         (8U)
+/*! WORD_LENGTH
+ *  0b00..Input data is 16 bits per pixel.
+ *  0b01..Input data is 8 bits wide.
+ *  0b10..Input data is 18 bits per pixel.
+ *  0b11..Input data is 24 bits per pixel.
+ */
 #define LCDIF_CTRL_CLR_WORD_LENGTH(x)            (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_CLR_WORD_LENGTH_MASK)
 #define LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_MASK    (0xC00U)
 #define LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_SHIFT   (10U)
+/*! LCD_DATABUS_WIDTH
+ *  0b00..16-bit data bus mode.
+ *  0b01..8-bit data bus mode.
+ *  0b10..18-bit data bus mode.
+ *  0b11..24-bit data bus mode.
+ */
 #define LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_MASK)
 #define LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_MASK     (0x3000U)
 #define LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_SHIFT    (12U)
+/*! CSC_DATA_SWIZZLE
+ *  0b00..No byte swapping.(Little endian)
+ *  0b00..Little Endian byte ordering (same as NO_SWAP).
+ *  0b01..Big Endian swap (swap bytes 0,3 and 1,2).
+ *  0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian).
+ *  0b10..Swap half-words.
+ *  0b11..Swap bytes within each half-word.
+ */
 #define LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_MASK)
 #define LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_MASK   (0xC000U)
 #define LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_SHIFT  (14U)
+/*! INPUT_DATA_SWIZZLE
+ *  0b00..No byte swapping.(Little endian)
+ *  0b00..Little Endian byte ordering (same as NO_SWAP).
+ *  0b01..Big Endian swap (swap bytes 0,3 and 1,2).
+ *  0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian).
+ *  0b10..Swap half-words.
+ *  0b11..Swap bytes within each half-word.
+ */
 #define LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_MASK)
 #define LCDIF_CTRL_CLR_DOTCLK_MODE_MASK          (0x20000U)
 #define LCDIF_CTRL_CLR_DOTCLK_MODE_SHIFT         (17U)
@@ -14368,6 +23000,10 @@ typedef struct {
 #define LCDIF_CTRL_CLR_SHIFT_NUM_BITS(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_CLR_SHIFT_NUM_BITS_MASK)
 #define LCDIF_CTRL_CLR_DATA_SHIFT_DIR_MASK       (0x4000000U)
 #define LCDIF_CTRL_CLR_DATA_SHIFT_DIR_SHIFT      (26U)
+/*! DATA_SHIFT_DIR
+ *  0b0..Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits.
+ *  0b1..Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits.
+ */
 #define LCDIF_CTRL_CLR_DATA_SHIFT_DIR(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_CLR_DATA_SHIFT_DIR_MASK)
 #define LCDIF_CTRL_CLR_CLKGATE_MASK              (0x40000000U)
 #define LCDIF_CTRL_CLR_CLKGATE_SHIFT             (30U)
@@ -14384,9 +23020,18 @@ typedef struct {
 #define LCDIF_CTRL_TOG_RUN(x)                    (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_RUN_SHIFT)) & LCDIF_CTRL_TOG_RUN_MASK)
 #define LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_MASK   (0x2U)
 #define LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_SHIFT  (1U)
+/*! DATA_FORMAT_24_BIT
+ *  0b0..Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits.
+ *  0b1..Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in
+ *       each byte do not contain any useful data, and should be dropped.
+ */
 #define LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_MASK)
 #define LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_MASK   (0x4U)
 #define LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_SHIFT  (2U)
+/*! DATA_FORMAT_18_BIT
+ *  0b0..Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data.
+ *  0b1..Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data.
+ */
 #define LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_MASK)
 #define LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_MASK   (0x8U)
 #define LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_SHIFT  (3U)
@@ -14402,15 +23047,43 @@ typedef struct {
 #define LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE(x)   (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_MASK)
 #define LCDIF_CTRL_TOG_WORD_LENGTH_MASK          (0x300U)
 #define LCDIF_CTRL_TOG_WORD_LENGTH_SHIFT         (8U)
+/*! WORD_LENGTH
+ *  0b00..Input data is 16 bits per pixel.
+ *  0b01..Input data is 8 bits wide.
+ *  0b10..Input data is 18 bits per pixel.
+ *  0b11..Input data is 24 bits per pixel.
+ */
 #define LCDIF_CTRL_TOG_WORD_LENGTH(x)            (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_TOG_WORD_LENGTH_MASK)
 #define LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_MASK    (0xC00U)
 #define LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_SHIFT   (10U)
+/*! LCD_DATABUS_WIDTH
+ *  0b00..16-bit data bus mode.
+ *  0b01..8-bit data bus mode.
+ *  0b10..18-bit data bus mode.
+ *  0b11..24-bit data bus mode.
+ */
 #define LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_MASK)
 #define LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_MASK     (0x3000U)
 #define LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_SHIFT    (12U)
+/*! CSC_DATA_SWIZZLE
+ *  0b00..No byte swapping.(Little endian)
+ *  0b00..Little Endian byte ordering (same as NO_SWAP).
+ *  0b01..Big Endian swap (swap bytes 0,3 and 1,2).
+ *  0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian).
+ *  0b10..Swap half-words.
+ *  0b11..Swap bytes within each half-word.
+ */
 #define LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_MASK)
 #define LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_MASK   (0xC000U)
 #define LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_SHIFT  (14U)
+/*! INPUT_DATA_SWIZZLE
+ *  0b00..No byte swapping.(Little endian)
+ *  0b00..Little Endian byte ordering (same as NO_SWAP).
+ *  0b01..Big Endian swap (swap bytes 0,3 and 1,2).
+ *  0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian).
+ *  0b10..Swap half-words.
+ *  0b11..Swap bytes within each half-word.
+ */
 #define LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_MASK)
 #define LCDIF_CTRL_TOG_DOTCLK_MODE_MASK          (0x20000U)
 #define LCDIF_CTRL_TOG_DOTCLK_MODE_SHIFT         (17U)
@@ -14423,6 +23096,10 @@ typedef struct {
 #define LCDIF_CTRL_TOG_SHIFT_NUM_BITS(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_TOG_SHIFT_NUM_BITS_MASK)
 #define LCDIF_CTRL_TOG_DATA_SHIFT_DIR_MASK       (0x4000000U)
 #define LCDIF_CTRL_TOG_DATA_SHIFT_DIR_SHIFT      (26U)
+/*! DATA_SHIFT_DIR
+ *  0b0..Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits.
+ *  0b1..Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits.
+ */
 #define LCDIF_CTRL_TOG_DATA_SHIFT_DIR(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_TOG_DATA_SHIFT_DIR_MASK)
 #define LCDIF_CTRL_TOG_CLKGATE_MASK              (0x40000000U)
 #define LCDIF_CTRL_TOG_CLKGATE_SHIFT             (30U)
@@ -14439,15 +23116,31 @@ typedef struct {
 #define LCDIF_CTRL1_RSRVD0(x)                    (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_RSRVD0_SHIFT)) & LCDIF_CTRL1_RSRVD0_MASK)
 #define LCDIF_CTRL1_VSYNC_EDGE_IRQ_MASK          (0x100U)
 #define LCDIF_CTRL1_VSYNC_EDGE_IRQ_SHIFT         (8U)
+/*! VSYNC_EDGE_IRQ
+ *  0b0..No Interrupt Request Pending.
+ *  0b1..Interrupt Request Pending.
+ */
 #define LCDIF_CTRL1_VSYNC_EDGE_IRQ(x)            (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_VSYNC_EDGE_IRQ_MASK)
 #define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_MASK      (0x200U)
 #define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_SHIFT     (9U)
+/*! CUR_FRAME_DONE_IRQ
+ *  0b0..No Interrupt Request Pending.
+ *  0b1..Interrupt Request Pending.
+ */
 #define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ(x)        (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_MASK)
 #define LCDIF_CTRL1_UNDERFLOW_IRQ_MASK           (0x400U)
 #define LCDIF_CTRL1_UNDERFLOW_IRQ_SHIFT          (10U)
+/*! UNDERFLOW_IRQ
+ *  0b0..No Interrupt Request Pending.
+ *  0b1..Interrupt Request Pending.
+ */
 #define LCDIF_CTRL1_UNDERFLOW_IRQ(x)             (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_UNDERFLOW_IRQ_MASK)
 #define LCDIF_CTRL1_OVERFLOW_IRQ_MASK            (0x800U)
 #define LCDIF_CTRL1_OVERFLOW_IRQ_SHIFT           (11U)
+/*! OVERFLOW_IRQ
+ *  0b0..No Interrupt Request Pending.
+ *  0b1..Interrupt Request Pending.
+ */
 #define LCDIF_CTRL1_OVERFLOW_IRQ(x)              (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_OVERFLOW_IRQ_MASK)
 #define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_MASK       (0x1000U)
 #define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_SHIFT      (12U)
@@ -14481,6 +23174,10 @@ typedef struct {
 #define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_MASK)
 #define LCDIF_CTRL1_BM_ERROR_IRQ_MASK            (0x2000000U)
 #define LCDIF_CTRL1_BM_ERROR_IRQ_SHIFT           (25U)
+/*! BM_ERROR_IRQ
+ *  0b0..No Interrupt Request Pending.
+ *  0b1..Interrupt Request Pending.
+ */
 #define LCDIF_CTRL1_BM_ERROR_IRQ(x)              (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_BM_ERROR_IRQ_MASK)
 #define LCDIF_CTRL1_BM_ERROR_IRQ_EN_MASK         (0x4000000U)
 #define LCDIF_CTRL1_BM_ERROR_IRQ_EN_SHIFT        (26U)
@@ -14500,15 +23197,31 @@ typedef struct {
 #define LCDIF_CTRL1_SET_RSRVD0(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_RSRVD0_SHIFT)) & LCDIF_CTRL1_SET_RSRVD0_MASK)
 #define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_MASK      (0x100U)
 #define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_SHIFT     (8U)
+/*! VSYNC_EDGE_IRQ
+ *  0b0..No Interrupt Request Pending.
+ *  0b1..Interrupt Request Pending.
+ */
 #define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ(x)        (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_MASK)
 #define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_MASK  (0x200U)
 #define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_SHIFT (9U)
+/*! CUR_FRAME_DONE_IRQ
+ *  0b0..No Interrupt Request Pending.
+ *  0b1..Interrupt Request Pending.
+ */
 #define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ(x)    (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_MASK)
 #define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_MASK       (0x400U)
 #define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_SHIFT      (10U)
+/*! UNDERFLOW_IRQ
+ *  0b0..No Interrupt Request Pending.
+ *  0b1..Interrupt Request Pending.
+ */
 #define LCDIF_CTRL1_SET_UNDERFLOW_IRQ(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_SET_UNDERFLOW_IRQ_MASK)
 #define LCDIF_CTRL1_SET_OVERFLOW_IRQ_MASK        (0x800U)
 #define LCDIF_CTRL1_SET_OVERFLOW_IRQ_SHIFT       (11U)
+/*! OVERFLOW_IRQ
+ *  0b0..No Interrupt Request Pending.
+ *  0b1..Interrupt Request Pending.
+ */
 #define LCDIF_CTRL1_SET_OVERFLOW_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_SET_OVERFLOW_IRQ_MASK)
 #define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_MASK   (0x1000U)
 #define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_SHIFT  (12U)
@@ -14542,6 +23255,10 @@ typedef struct {
 #define LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW(x)  (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_MASK)
 #define LCDIF_CTRL1_SET_BM_ERROR_IRQ_MASK        (0x2000000U)
 #define LCDIF_CTRL1_SET_BM_ERROR_IRQ_SHIFT       (25U)
+/*! BM_ERROR_IRQ
+ *  0b0..No Interrupt Request Pending.
+ *  0b1..Interrupt Request Pending.
+ */
 #define LCDIF_CTRL1_SET_BM_ERROR_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_SET_BM_ERROR_IRQ_MASK)
 #define LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_MASK     (0x4000000U)
 #define LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_SHIFT    (26U)
@@ -14561,15 +23278,31 @@ typedef struct {
 #define LCDIF_CTRL1_CLR_RSRVD0(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL1_CLR_RSRVD0_MASK)
 #define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_MASK      (0x100U)
 #define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_SHIFT     (8U)
+/*! VSYNC_EDGE_IRQ
+ *  0b0..No Interrupt Request Pending.
+ *  0b1..Interrupt Request Pending.
+ */
 #define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ(x)        (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_MASK)
 #define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_MASK  (0x200U)
 #define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_SHIFT (9U)
+/*! CUR_FRAME_DONE_IRQ
+ *  0b0..No Interrupt Request Pending.
+ *  0b1..Interrupt Request Pending.
+ */
 #define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ(x)    (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_MASK)
 #define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_MASK       (0x400U)
 #define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_SHIFT      (10U)
+/*! UNDERFLOW_IRQ
+ *  0b0..No Interrupt Request Pending.
+ *  0b1..Interrupt Request Pending.
+ */
 #define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_MASK)
 #define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_MASK        (0x800U)
 #define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_SHIFT       (11U)
+/*! OVERFLOW_IRQ
+ *  0b0..No Interrupt Request Pending.
+ *  0b1..Interrupt Request Pending.
+ */
 #define LCDIF_CTRL1_CLR_OVERFLOW_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_OVERFLOW_IRQ_MASK)
 #define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_MASK   (0x1000U)
 #define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_SHIFT  (12U)
@@ -14603,6 +23336,10 @@ typedef struct {
 #define LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW(x)  (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_MASK)
 #define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_MASK        (0x2000000U)
 #define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_SHIFT       (25U)
+/*! BM_ERROR_IRQ
+ *  0b0..No Interrupt Request Pending.
+ *  0b1..Interrupt Request Pending.
+ */
 #define LCDIF_CTRL1_CLR_BM_ERROR_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_BM_ERROR_IRQ_MASK)
 #define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_MASK     (0x4000000U)
 #define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_SHIFT    (26U)
@@ -14622,15 +23359,31 @@ typedef struct {
 #define LCDIF_CTRL1_TOG_RSRVD0(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL1_TOG_RSRVD0_MASK)
 #define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_MASK      (0x100U)
 #define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_SHIFT     (8U)
+/*! VSYNC_EDGE_IRQ
+ *  0b0..No Interrupt Request Pending.
+ *  0b1..Interrupt Request Pending.
+ */
 #define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ(x)        (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_MASK)
 #define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_MASK  (0x200U)
 #define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_SHIFT (9U)
+/*! CUR_FRAME_DONE_IRQ
+ *  0b0..No Interrupt Request Pending.
+ *  0b1..Interrupt Request Pending.
+ */
 #define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ(x)    (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_MASK)
 #define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_MASK       (0x400U)
 #define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_SHIFT      (10U)
+/*! UNDERFLOW_IRQ
+ *  0b0..No Interrupt Request Pending.
+ *  0b1..Interrupt Request Pending.
+ */
 #define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_MASK)
 #define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_MASK        (0x800U)
 #define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_SHIFT       (11U)
+/*! OVERFLOW_IRQ
+ *  0b0..No Interrupt Request Pending.
+ *  0b1..Interrupt Request Pending.
+ */
 #define LCDIF_CTRL1_TOG_OVERFLOW_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_OVERFLOW_IRQ_MASK)
 #define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_MASK   (0x1000U)
 #define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_SHIFT  (12U)
@@ -14664,6 +23417,10 @@ typedef struct {
 #define LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW(x)  (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_MASK)
 #define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_MASK        (0x2000000U)
 #define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_SHIFT       (25U)
+/*! BM_ERROR_IRQ
+ *  0b0..No Interrupt Request Pending.
+ *  0b1..Interrupt Request Pending.
+ */
 #define LCDIF_CTRL1_TOG_BM_ERROR_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_BM_ERROR_IRQ_MASK)
 #define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_MASK     (0x4000000U)
 #define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_SHIFT    (26U)
@@ -14683,12 +23440,28 @@ typedef struct {
 #define LCDIF_CTRL2_RSRVD0(x)                    (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD0_SHIFT)) & LCDIF_CTRL2_RSRVD0_MASK)
 #define LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK       (0x7000U)
 #define LCDIF_CTRL2_EVEN_LINE_PATTERN_SHIFT      (12U)
+/*! EVEN_LINE_PATTERN
+ *  0b000..RGB
+ *  0b001..RBG
+ *  0b010..GBR
+ *  0b011..GRB
+ *  0b100..BRG
+ *  0b101..BGR
+ */
 #define LCDIF_CTRL2_EVEN_LINE_PATTERN(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK)
 #define LCDIF_CTRL2_RSRVD3_MASK                  (0x8000U)
 #define LCDIF_CTRL2_RSRVD3_SHIFT                 (15U)
 #define LCDIF_CTRL2_RSRVD3(x)                    (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD3_SHIFT)) & LCDIF_CTRL2_RSRVD3_MASK)
 #define LCDIF_CTRL2_ODD_LINE_PATTERN_MASK        (0x70000U)
 #define LCDIF_CTRL2_ODD_LINE_PATTERN_SHIFT       (16U)
+/*! ODD_LINE_PATTERN
+ *  0b000..RGB
+ *  0b001..RBG
+ *  0b010..GBR
+ *  0b011..GRB
+ *  0b100..BRG
+ *  0b101..BGR
+ */
 #define LCDIF_CTRL2_ODD_LINE_PATTERN(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_ODD_LINE_PATTERN_MASK)
 #define LCDIF_CTRL2_RSRVD4_MASK                  (0x80000U)
 #define LCDIF_CTRL2_RSRVD4_SHIFT                 (19U)
@@ -14698,6 +23471,13 @@ typedef struct {
 #define LCDIF_CTRL2_BURST_LEN_8(x)               (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_BURST_LEN_8_MASK)
 #define LCDIF_CTRL2_OUTSTANDING_REQS_MASK        (0xE00000U)
 #define LCDIF_CTRL2_OUTSTANDING_REQS_SHIFT       (21U)
+/*! OUTSTANDING_REQS
+ *  0b000..REQ_1
+ *  0b001..REQ_2
+ *  0b010..REQ_4
+ *  0b011..REQ_8
+ *  0b100..REQ_16
+ */
 #define LCDIF_CTRL2_OUTSTANDING_REQS(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_OUTSTANDING_REQS_MASK)
 #define LCDIF_CTRL2_RSRVD5_MASK                  (0xFF000000U)
 #define LCDIF_CTRL2_RSRVD5_SHIFT                 (24U)
@@ -14711,12 +23491,28 @@ typedef struct {
 #define LCDIF_CTRL2_SET_RSRVD0(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD0_SHIFT)) & LCDIF_CTRL2_SET_RSRVD0_MASK)
 #define LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_MASK   (0x7000U)
 #define LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_SHIFT  (12U)
+/*! EVEN_LINE_PATTERN
+ *  0b000..RGB
+ *  0b001..RBG
+ *  0b010..GBR
+ *  0b011..GRB
+ *  0b100..BRG
+ *  0b101..BGR
+ */
 #define LCDIF_CTRL2_SET_EVEN_LINE_PATTERN(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_MASK)
 #define LCDIF_CTRL2_SET_RSRVD3_MASK              (0x8000U)
 #define LCDIF_CTRL2_SET_RSRVD3_SHIFT             (15U)
 #define LCDIF_CTRL2_SET_RSRVD3(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD3_SHIFT)) & LCDIF_CTRL2_SET_RSRVD3_MASK)
 #define LCDIF_CTRL2_SET_ODD_LINE_PATTERN_MASK    (0x70000U)
 #define LCDIF_CTRL2_SET_ODD_LINE_PATTERN_SHIFT   (16U)
+/*! ODD_LINE_PATTERN
+ *  0b000..RGB
+ *  0b001..RBG
+ *  0b010..GBR
+ *  0b011..GRB
+ *  0b100..BRG
+ *  0b101..BGR
+ */
 #define LCDIF_CTRL2_SET_ODD_LINE_PATTERN(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_SET_ODD_LINE_PATTERN_MASK)
 #define LCDIF_CTRL2_SET_RSRVD4_MASK              (0x80000U)
 #define LCDIF_CTRL2_SET_RSRVD4_SHIFT             (19U)
@@ -14726,6 +23522,13 @@ typedef struct {
 #define LCDIF_CTRL2_SET_BURST_LEN_8(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_SET_BURST_LEN_8_MASK)
 #define LCDIF_CTRL2_SET_OUTSTANDING_REQS_MASK    (0xE00000U)
 #define LCDIF_CTRL2_SET_OUTSTANDING_REQS_SHIFT   (21U)
+/*! OUTSTANDING_REQS
+ *  0b000..REQ_1
+ *  0b001..REQ_2
+ *  0b010..REQ_4
+ *  0b011..REQ_8
+ *  0b100..REQ_16
+ */
 #define LCDIF_CTRL2_SET_OUTSTANDING_REQS(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_SET_OUTSTANDING_REQS_MASK)
 #define LCDIF_CTRL2_SET_RSRVD5_MASK              (0xFF000000U)
 #define LCDIF_CTRL2_SET_RSRVD5_SHIFT             (24U)
@@ -14739,12 +23542,28 @@ typedef struct {
 #define LCDIF_CTRL2_CLR_RSRVD0(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD0_MASK)
 #define LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_MASK   (0x7000U)
 #define LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_SHIFT  (12U)
+/*! EVEN_LINE_PATTERN
+ *  0b000..RGB
+ *  0b001..RBG
+ *  0b010..GBR
+ *  0b011..GRB
+ *  0b100..BRG
+ *  0b101..BGR
+ */
 #define LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_MASK)
 #define LCDIF_CTRL2_CLR_RSRVD3_MASK              (0x8000U)
 #define LCDIF_CTRL2_CLR_RSRVD3_SHIFT             (15U)
 #define LCDIF_CTRL2_CLR_RSRVD3(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD3_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD3_MASK)
 #define LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_MASK    (0x70000U)
 #define LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_SHIFT   (16U)
+/*! ODD_LINE_PATTERN
+ *  0b000..RGB
+ *  0b001..RBG
+ *  0b010..GBR
+ *  0b011..GRB
+ *  0b100..BRG
+ *  0b101..BGR
+ */
 #define LCDIF_CTRL2_CLR_ODD_LINE_PATTERN(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_MASK)
 #define LCDIF_CTRL2_CLR_RSRVD4_MASK              (0x80000U)
 #define LCDIF_CTRL2_CLR_RSRVD4_SHIFT             (19U)
@@ -14754,6 +23573,13 @@ typedef struct {
 #define LCDIF_CTRL2_CLR_BURST_LEN_8(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_CLR_BURST_LEN_8_MASK)
 #define LCDIF_CTRL2_CLR_OUTSTANDING_REQS_MASK    (0xE00000U)
 #define LCDIF_CTRL2_CLR_OUTSTANDING_REQS_SHIFT   (21U)
+/*! OUTSTANDING_REQS
+ *  0b000..REQ_1
+ *  0b001..REQ_2
+ *  0b010..REQ_4
+ *  0b011..REQ_8
+ *  0b100..REQ_16
+ */
 #define LCDIF_CTRL2_CLR_OUTSTANDING_REQS(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_CLR_OUTSTANDING_REQS_MASK)
 #define LCDIF_CTRL2_CLR_RSRVD5_MASK              (0xFF000000U)
 #define LCDIF_CTRL2_CLR_RSRVD5_SHIFT             (24U)
@@ -14767,12 +23593,28 @@ typedef struct {
 #define LCDIF_CTRL2_TOG_RSRVD0(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD0_MASK)
 #define LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_MASK   (0x7000U)
 #define LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_SHIFT  (12U)
+/*! EVEN_LINE_PATTERN
+ *  0b000..RGB
+ *  0b001..RBG
+ *  0b010..GBR
+ *  0b011..GRB
+ *  0b100..BRG
+ *  0b101..BGR
+ */
 #define LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_MASK)
 #define LCDIF_CTRL2_TOG_RSRVD3_MASK              (0x8000U)
 #define LCDIF_CTRL2_TOG_RSRVD3_SHIFT             (15U)
 #define LCDIF_CTRL2_TOG_RSRVD3(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD3_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD3_MASK)
 #define LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_MASK    (0x70000U)
 #define LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_SHIFT   (16U)
+/*! ODD_LINE_PATTERN
+ *  0b000..RGB
+ *  0b001..RBG
+ *  0b010..GBR
+ *  0b011..GRB
+ *  0b100..BRG
+ *  0b101..BGR
+ */
 #define LCDIF_CTRL2_TOG_ODD_LINE_PATTERN(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_MASK)
 #define LCDIF_CTRL2_TOG_RSRVD4_MASK              (0x80000U)
 #define LCDIF_CTRL2_TOG_RSRVD4_SHIFT             (19U)
@@ -14782,6 +23624,13 @@ typedef struct {
 #define LCDIF_CTRL2_TOG_BURST_LEN_8(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_TOG_BURST_LEN_8_MASK)
 #define LCDIF_CTRL2_TOG_OUTSTANDING_REQS_MASK    (0xE00000U)
 #define LCDIF_CTRL2_TOG_OUTSTANDING_REQS_SHIFT   (21U)
+/*! OUTSTANDING_REQS
+ *  0b000..REQ_1
+ *  0b001..REQ_2
+ *  0b010..REQ_4
+ *  0b011..REQ_8
+ *  0b100..REQ_16
+ */
 #define LCDIF_CTRL2_TOG_OUTSTANDING_REQS(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_TOG_OUTSTANDING_REQS_MASK)
 #define LCDIF_CTRL2_TOG_RSRVD5_MASK              (0xFF000000U)
 #define LCDIF_CTRL2_TOG_RSRVD5_SHIFT             (24U)
@@ -15209,21 +24058,51 @@ typedef struct {
 #define LCDIF_PIGEON_0_EN(x)                     (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_EN_SHIFT)) & LCDIF_PIGEON_0_EN_MASK)
 #define LCDIF_PIGEON_0_POL_MASK                  (0x2U)
 #define LCDIF_PIGEON_0_POL_SHIFT                 (1U)
+/*! POL
+ *  0b0..Normal Signal (Active high)
+ *  0b1..Inverted signal (Active low)
+ */
 #define LCDIF_PIGEON_0_POL(x)                    (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_POL_SHIFT)) & LCDIF_PIGEON_0_POL_MASK)
 #define LCDIF_PIGEON_0_INC_SEL_MASK              (0xCU)
 #define LCDIF_PIGEON_0_INC_SEL_SHIFT             (2U)
+/*! INC_SEL
+ *  0b00..pclk
+ *  0b01..Line start pulse
+ *  0b10..Frame start pulse
+ *  0b11..Use another signal as tick event
+ */
 #define LCDIF_PIGEON_0_INC_SEL(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_INC_SEL_SHIFT)) & LCDIF_PIGEON_0_INC_SEL_MASK)
 #define LCDIF_PIGEON_0_OFFSET_MASK               (0xF0U)
 #define LCDIF_PIGEON_0_OFFSET_SHIFT              (4U)
 #define LCDIF_PIGEON_0_OFFSET(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_OFFSET_SHIFT)) & LCDIF_PIGEON_0_OFFSET_MASK)
 #define LCDIF_PIGEON_0_MASK_CNT_SEL_MASK         (0xF00U)
 #define LCDIF_PIGEON_0_MASK_CNT_SEL_SHIFT        (8U)
+/*! MASK_CNT_SEL
+ *  0b0000..pclk counter within one hscan state
+ *  0b0001..pclk cycle within one hscan state
+ *  0b0010..line counter within one vscan state
+ *  0b0011..line cycle within one vscan state
+ *  0b0100..frame counter
+ *  0b0101..frame cycle
+ *  0b0110..horizontal counter (pclk counter within one line )
+ *  0b0111..vertical counter (line counter within one frame)
+ */
 #define LCDIF_PIGEON_0_MASK_CNT_SEL(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_MASK_CNT_SEL_SHIFT)) & LCDIF_PIGEON_0_MASK_CNT_SEL_MASK)
 #define LCDIF_PIGEON_0_MASK_CNT_MASK             (0xFFF000U)
 #define LCDIF_PIGEON_0_MASK_CNT_SHIFT            (12U)
 #define LCDIF_PIGEON_0_MASK_CNT(x)               (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_MASK_CNT_SHIFT)) & LCDIF_PIGEON_0_MASK_CNT_MASK)
 #define LCDIF_PIGEON_0_STATE_MASK_MASK           (0xFF000000U)
 #define LCDIF_PIGEON_0_STATE_MASK_SHIFT          (24U)
+/*! STATE_MASK
+ *  0b00000001..FRAME SYNC
+ *  0b00000010..FRAME BEGIN
+ *  0b00000100..FRAME DATA
+ *  0b00001000..FRAME END
+ *  0b00010000..LINE SYNC
+ *  0b00100000..LINE BEGIN
+ *  0b01000000..LINE DATA
+ *  0b10000000..LINE END
+ */
 #define LCDIF_PIGEON_0_STATE_MASK(x)             (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_STATE_MASK_SHIFT)) & LCDIF_PIGEON_0_STATE_MASK_MASK)
 /*! @} */
 
@@ -15234,9 +24113,15 @@ typedef struct {
 /*! @{ */
 #define LCDIF_PIGEON_1_SET_CNT_MASK              (0xFFFFU)
 #define LCDIF_PIGEON_1_SET_CNT_SHIFT             (0U)
+/*! SET_CNT
+ *  0b0000000000000000..Start as active
+ */
 #define LCDIF_PIGEON_1_SET_CNT(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_1_SET_CNT_SHIFT)) & LCDIF_PIGEON_1_SET_CNT_MASK)
 #define LCDIF_PIGEON_1_CLR_CNT_MASK              (0xFFFF0000U)
 #define LCDIF_PIGEON_1_CLR_CNT_SHIFT             (16U)
+/*! CLR_CNT
+ *  0b0000000000000000..Keep active until mask off
+ */
 #define LCDIF_PIGEON_1_CLR_CNT(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_1_CLR_CNT_SHIFT)) & LCDIF_PIGEON_1_CLR_CNT_MASK)
 /*! @} */
 
@@ -15247,9 +24132,18 @@ typedef struct {
 /*! @{ */
 #define LCDIF_PIGEON_2_SIG_LOGIC_MASK            (0xFU)
 #define LCDIF_PIGEON_2_SIG_LOGIC_SHIFT           (0U)
+/*! SIG_LOGIC
+ *  0b0000..No logic operation
+ *  0b0001..sigout = sig_another AND this_sig
+ *  0b0010..sigout = sig_another OR this_sig
+ *  0b0011..mask = sig_another AND other_masks
+ */
 #define LCDIF_PIGEON_2_SIG_LOGIC(x)              (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_2_SIG_LOGIC_SHIFT)) & LCDIF_PIGEON_2_SIG_LOGIC_MASK)
 #define LCDIF_PIGEON_2_SIG_ANOTHER_MASK          (0x1F0U)
 #define LCDIF_PIGEON_2_SIG_ANOTHER_SHIFT         (4U)
+/*! SIG_ANOTHER
+ *  0b00000..Keep active until mask off
+ */
 #define LCDIF_PIGEON_2_SIG_ANOTHER(x)            (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_2_SIG_ANOTHER_SHIFT)) & LCDIF_PIGEON_2_SIG_ANOTHER_MASK)
 #define LCDIF_PIGEON_2_RSVD_MASK                 (0xFFFFFE00U)
 #define LCDIF_PIGEON_2_RSVD_SHIFT                (9U)
@@ -15383,6 +24277,10 @@ typedef struct {
 /*! @{ */
 #define LPI2C_VERID_FEATURE_MASK                 (0xFFFFU)
 #define LPI2C_VERID_FEATURE_SHIFT                (0U)
+/*! FEATURE - Feature Specification Number
+ *  0b0000000000000010..Master only, with standard feature set
+ *  0b0000000000000011..Master and slave, with standard feature set
+ */
 #define LPI2C_VERID_FEATURE(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_FEATURE_SHIFT)) & LPI2C_VERID_FEATURE_MASK)
 #define LPI2C_VERID_MINOR_MASK                   (0xFF0000U)
 #define LPI2C_VERID_MINOR_SHIFT                  (16U)
@@ -15406,21 +24304,45 @@ typedef struct {
 /*! @{ */
 #define LPI2C_MCR_MEN_MASK                       (0x1U)
 #define LPI2C_MCR_MEN_SHIFT                      (0U)
+/*! MEN - Master Enable
+ *  0b0..Master logic is disabled
+ *  0b1..Master logic is enabled
+ */
 #define LPI2C_MCR_MEN(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_MEN_SHIFT)) & LPI2C_MCR_MEN_MASK)
 #define LPI2C_MCR_RST_MASK                       (0x2U)
 #define LPI2C_MCR_RST_SHIFT                      (1U)
+/*! RST - Software Reset
+ *  0b0..Master logic is not reset
+ *  0b1..Master logic is reset
+ */
 #define LPI2C_MCR_RST(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RST_SHIFT)) & LPI2C_MCR_RST_MASK)
 #define LPI2C_MCR_DOZEN_MASK                     (0x4U)
 #define LPI2C_MCR_DOZEN_SHIFT                    (2U)
+/*! DOZEN - Doze mode enable
+ *  0b0..Master is enabled in Doze mode
+ *  0b1..Master is disabled in Doze mode
+ */
 #define LPI2C_MCR_DOZEN(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DOZEN_SHIFT)) & LPI2C_MCR_DOZEN_MASK)
 #define LPI2C_MCR_DBGEN_MASK                     (0x8U)
 #define LPI2C_MCR_DBGEN_SHIFT                    (3U)
+/*! DBGEN - Debug Enable
+ *  0b0..Master is disabled in debug mode
+ *  0b1..Master is enabled in debug mode
+ */
 #define LPI2C_MCR_DBGEN(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DBGEN_SHIFT)) & LPI2C_MCR_DBGEN_MASK)
 #define LPI2C_MCR_RTF_MASK                       (0x100U)
 #define LPI2C_MCR_RTF_SHIFT                      (8U)
+/*! RTF - Reset Transmit FIFO
+ *  0b0..No effect
+ *  0b1..Transmit FIFO is reset
+ */
 #define LPI2C_MCR_RTF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RTF_SHIFT)) & LPI2C_MCR_RTF_MASK)
 #define LPI2C_MCR_RRF_MASK                       (0x200U)
 #define LPI2C_MCR_RRF_SHIFT                      (9U)
+/*! RRF - Reset Receive FIFO
+ *  0b0..No effect
+ *  0b1..Receive FIFO is reset
+ */
 #define LPI2C_MCR_RRF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RRF_SHIFT)) & LPI2C_MCR_RRF_MASK)
 /*! @} */
 
@@ -15428,36 +24350,80 @@ typedef struct {
 /*! @{ */
 #define LPI2C_MSR_TDF_MASK                       (0x1U)
 #define LPI2C_MSR_TDF_SHIFT                      (0U)
+/*! TDF - Transmit Data Flag
+ *  0b0..Transmit data is not requested
+ *  0b1..Transmit data is requested
+ */
 #define LPI2C_MSR_TDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_TDF_SHIFT)) & LPI2C_MSR_TDF_MASK)
 #define LPI2C_MSR_RDF_MASK                       (0x2U)
 #define LPI2C_MSR_RDF_SHIFT                      (1U)
+/*! RDF - Receive Data Flag
+ *  0b0..Receive Data is not ready
+ *  0b1..Receive data is ready
+ */
 #define LPI2C_MSR_RDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_RDF_SHIFT)) & LPI2C_MSR_RDF_MASK)
 #define LPI2C_MSR_EPF_MASK                       (0x100U)
 #define LPI2C_MSR_EPF_SHIFT                      (8U)
+/*! EPF - End Packet Flag
+ *  0b0..Master has not generated a STOP or Repeated START condition
+ *  0b1..Master has generated a STOP or Repeated START condition
+ */
 #define LPI2C_MSR_EPF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_EPF_SHIFT)) & LPI2C_MSR_EPF_MASK)
 #define LPI2C_MSR_SDF_MASK                       (0x200U)
 #define LPI2C_MSR_SDF_SHIFT                      (9U)
+/*! SDF - STOP Detect Flag
+ *  0b0..Master has not generated a STOP condition
+ *  0b1..Master has generated a STOP condition
+ */
 #define LPI2C_MSR_SDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_SDF_SHIFT)) & LPI2C_MSR_SDF_MASK)
 #define LPI2C_MSR_NDF_MASK                       (0x400U)
 #define LPI2C_MSR_NDF_SHIFT                      (10U)
+/*! NDF - NACK Detect Flag
+ *  0b0..Unexpected NACK was not detected
+ *  0b1..Unexpected NACK was detected
+ */
 #define LPI2C_MSR_NDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_NDF_SHIFT)) & LPI2C_MSR_NDF_MASK)
 #define LPI2C_MSR_ALF_MASK                       (0x800U)
 #define LPI2C_MSR_ALF_SHIFT                      (11U)
+/*! ALF - Arbitration Lost Flag
+ *  0b0..Master has not lost arbitration
+ *  0b1..Master has lost arbitration
+ */
 #define LPI2C_MSR_ALF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_ALF_SHIFT)) & LPI2C_MSR_ALF_MASK)
 #define LPI2C_MSR_FEF_MASK                       (0x1000U)
 #define LPI2C_MSR_FEF_SHIFT                      (12U)
+/*! FEF - FIFO Error Flag
+ *  0b0..No error
+ *  0b1..Master sending or receiving data without a START condition
+ */
 #define LPI2C_MSR_FEF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_FEF_SHIFT)) & LPI2C_MSR_FEF_MASK)
 #define LPI2C_MSR_PLTF_MASK                      (0x2000U)
 #define LPI2C_MSR_PLTF_SHIFT                     (13U)
+/*! PLTF - Pin Low Timeout Flag
+ *  0b0..Pin low timeout has not occurred or is disabled
+ *  0b1..Pin low timeout has occurred
+ */
 #define LPI2C_MSR_PLTF(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_PLTF_SHIFT)) & LPI2C_MSR_PLTF_MASK)
 #define LPI2C_MSR_DMF_MASK                       (0x4000U)
 #define LPI2C_MSR_DMF_SHIFT                      (14U)
+/*! DMF - Data Match Flag
+ *  0b0..Have not received matching data
+ *  0b1..Have received matching data
+ */
 #define LPI2C_MSR_DMF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_DMF_SHIFT)) & LPI2C_MSR_DMF_MASK)
 #define LPI2C_MSR_MBF_MASK                       (0x1000000U)
 #define LPI2C_MSR_MBF_SHIFT                      (24U)
+/*! MBF - Master Busy Flag
+ *  0b0..I2C Master is idle
+ *  0b1..I2C Master is busy
+ */
 #define LPI2C_MSR_MBF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_MBF_SHIFT)) & LPI2C_MSR_MBF_MASK)
 #define LPI2C_MSR_BBF_MASK                       (0x2000000U)
 #define LPI2C_MSR_BBF_SHIFT                      (25U)
+/*! BBF - Bus Busy Flag
+ *  0b0..I2C Bus is idle
+ *  0b1..I2C Bus is busy
+ */
 #define LPI2C_MSR_BBF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_BBF_SHIFT)) & LPI2C_MSR_BBF_MASK)
 /*! @} */
 
@@ -15465,30 +24431,66 @@ typedef struct {
 /*! @{ */
 #define LPI2C_MIER_TDIE_MASK                     (0x1U)
 #define LPI2C_MIER_TDIE_SHIFT                    (0U)
+/*! TDIE - Transmit Data Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
 #define LPI2C_MIER_TDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_TDIE_SHIFT)) & LPI2C_MIER_TDIE_MASK)
 #define LPI2C_MIER_RDIE_MASK                     (0x2U)
 #define LPI2C_MIER_RDIE_SHIFT                    (1U)
+/*! RDIE - Receive Data Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
 #define LPI2C_MIER_RDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_RDIE_SHIFT)) & LPI2C_MIER_RDIE_MASK)
 #define LPI2C_MIER_EPIE_MASK                     (0x100U)
 #define LPI2C_MIER_EPIE_SHIFT                    (8U)
+/*! EPIE - End Packet Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
 #define LPI2C_MIER_EPIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_EPIE_SHIFT)) & LPI2C_MIER_EPIE_MASK)
 #define LPI2C_MIER_SDIE_MASK                     (0x200U)
 #define LPI2C_MIER_SDIE_SHIFT                    (9U)
+/*! SDIE - STOP Detect Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
 #define LPI2C_MIER_SDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_SDIE_SHIFT)) & LPI2C_MIER_SDIE_MASK)
 #define LPI2C_MIER_NDIE_MASK                     (0x400U)
 #define LPI2C_MIER_NDIE_SHIFT                    (10U)
+/*! NDIE - NACK Detect Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
 #define LPI2C_MIER_NDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_NDIE_SHIFT)) & LPI2C_MIER_NDIE_MASK)
 #define LPI2C_MIER_ALIE_MASK                     (0x800U)
 #define LPI2C_MIER_ALIE_SHIFT                    (11U)
+/*! ALIE - Arbitration Lost Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
 #define LPI2C_MIER_ALIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_ALIE_SHIFT)) & LPI2C_MIER_ALIE_MASK)
 #define LPI2C_MIER_FEIE_MASK                     (0x1000U)
 #define LPI2C_MIER_FEIE_SHIFT                    (12U)
+/*! FEIE - FIFO Error Interrupt Enable
+ *  0b0..Enabled
+ *  0b1..Disabled
+ */
 #define LPI2C_MIER_FEIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_FEIE_SHIFT)) & LPI2C_MIER_FEIE_MASK)
 #define LPI2C_MIER_PLTIE_MASK                    (0x2000U)
 #define LPI2C_MIER_PLTIE_SHIFT                   (13U)
+/*! PLTIE - Pin Low Timeout Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
 #define LPI2C_MIER_PLTIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_PLTIE_SHIFT)) & LPI2C_MIER_PLTIE_MASK)
 #define LPI2C_MIER_DMIE_MASK                     (0x4000U)
 #define LPI2C_MIER_DMIE_SHIFT                    (14U)
+/*! DMIE - Data Match Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
 #define LPI2C_MIER_DMIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_DMIE_SHIFT)) & LPI2C_MIER_DMIE_MASK)
 /*! @} */
 
@@ -15496,9 +24498,17 @@ typedef struct {
 /*! @{ */
 #define LPI2C_MDER_TDDE_MASK                     (0x1U)
 #define LPI2C_MDER_TDDE_SHIFT                    (0U)
+/*! TDDE - Transmit Data DMA Enable
+ *  0b0..DMA request is disabled
+ *  0b1..DMA request is enabled
+ */
 #define LPI2C_MDER_TDDE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_TDDE_SHIFT)) & LPI2C_MDER_TDDE_MASK)
 #define LPI2C_MDER_RDDE_MASK                     (0x2U)
 #define LPI2C_MDER_RDDE_SHIFT                    (1U)
+/*! RDDE - Receive Data DMA Enable
+ *  0b0..DMA request is disabled
+ *  0b1..DMA request is enabled
+ */
 #define LPI2C_MDER_RDDE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_RDDE_SHIFT)) & LPI2C_MDER_RDDE_MASK)
 /*! @} */
 
@@ -15506,18 +24516,38 @@ typedef struct {
 /*! @{ */
 #define LPI2C_MCFGR0_HREN_MASK                   (0x1U)
 #define LPI2C_MCFGR0_HREN_SHIFT                  (0U)
+/*! HREN - Host Request Enable
+ *  0b0..Host request input is disabled
+ *  0b1..Host request input is enabled
+ */
 #define LPI2C_MCFGR0_HREN(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HREN_SHIFT)) & LPI2C_MCFGR0_HREN_MASK)
 #define LPI2C_MCFGR0_HRPOL_MASK                  (0x2U)
 #define LPI2C_MCFGR0_HRPOL_SHIFT                 (1U)
+/*! HRPOL - Host Request Polarity
+ *  0b0..Active low
+ *  0b1..Active high
+ */
 #define LPI2C_MCFGR0_HRPOL(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRPOL_SHIFT)) & LPI2C_MCFGR0_HRPOL_MASK)
 #define LPI2C_MCFGR0_HRSEL_MASK                  (0x4U)
 #define LPI2C_MCFGR0_HRSEL_SHIFT                 (2U)
+/*! HRSEL - Host Request Select
+ *  0b0..Host request input is pin HREQ
+ *  0b1..Host request input is input trigger
+ */
 #define LPI2C_MCFGR0_HRSEL(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRSEL_SHIFT)) & LPI2C_MCFGR0_HRSEL_MASK)
 #define LPI2C_MCFGR0_CIRFIFO_MASK                (0x100U)
 #define LPI2C_MCFGR0_CIRFIFO_SHIFT               (8U)
+/*! CIRFIFO - Circular FIFO Enable
+ *  0b0..Circular FIFO is disabled
+ *  0b1..Circular FIFO is enabled
+ */
 #define LPI2C_MCFGR0_CIRFIFO(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_CIRFIFO_SHIFT)) & LPI2C_MCFGR0_CIRFIFO_MASK)
 #define LPI2C_MCFGR0_RDMO_MASK                   (0x200U)
 #define LPI2C_MCFGR0_RDMO_SHIFT                  (9U)
+/*! RDMO - Receive Data Match Only
+ *  0b0..Received data is stored in the receive FIFO
+ *  0b1..Received data is discarded unless the the Data Match Flag (MSR[DMF]) is set
+ */
 #define LPI2C_MCFGR0_RDMO(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_RDMO_SHIFT)) & LPI2C_MCFGR0_RDMO_MASK)
 /*! @} */
 
@@ -15525,21 +24555,63 @@ typedef struct {
 /*! @{ */
 #define LPI2C_MCFGR1_PRESCALE_MASK               (0x7U)
 #define LPI2C_MCFGR1_PRESCALE_SHIFT              (0U)
+/*! PRESCALE - Prescaler
+ *  0b000..Divide by 1
+ *  0b001..Divide by 2
+ *  0b010..Divide by 4
+ *  0b011..Divide by 8
+ *  0b100..Divide by 16
+ *  0b101..Divide by 32
+ *  0b110..Divide by 64
+ *  0b111..Divide by 128
+ */
 #define LPI2C_MCFGR1_PRESCALE(x)                 (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PRESCALE_SHIFT)) & LPI2C_MCFGR1_PRESCALE_MASK)
 #define LPI2C_MCFGR1_AUTOSTOP_MASK               (0x100U)
 #define LPI2C_MCFGR1_AUTOSTOP_SHIFT              (8U)
+/*! AUTOSTOP - Automatic STOP Generation
+ *  0b0..No effect
+ *  0b1..STOP condition is automatically generated whenever the transmit FIFO is empty and the LPI2C master is busy
+ */
 #define LPI2C_MCFGR1_AUTOSTOP(x)                 (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_AUTOSTOP_SHIFT)) & LPI2C_MCFGR1_AUTOSTOP_MASK)
 #define LPI2C_MCFGR1_IGNACK_MASK                 (0x200U)
 #define LPI2C_MCFGR1_IGNACK_SHIFT                (9U)
+/*! IGNACK - IGNACK
+ *  0b0..LPI2C Master will receive ACK and NACK normally
+ *  0b1..LPI2C Master will treat a received NACK as if it (NACK) was an ACK
+ */
 #define LPI2C_MCFGR1_IGNACK(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_IGNACK_SHIFT)) & LPI2C_MCFGR1_IGNACK_MASK)
 #define LPI2C_MCFGR1_TIMECFG_MASK                (0x400U)
 #define LPI2C_MCFGR1_TIMECFG_SHIFT               (10U)
+/*! TIMECFG - Timeout Configuration
+ *  0b0..Pin Low Timeout Flag will set if SCL is low for longer than the configured timeout
+ *  0b1..Pin Low Timeout Flag will set if either SCL or SDA is low for longer than the configured timeout
+ */
 #define LPI2C_MCFGR1_TIMECFG(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_TIMECFG_SHIFT)) & LPI2C_MCFGR1_TIMECFG_MASK)
 #define LPI2C_MCFGR1_MATCFG_MASK                 (0x70000U)
 #define LPI2C_MCFGR1_MATCFG_SHIFT                (16U)
+/*! MATCFG - Match Configuration
+ *  0b000..Match is disabled
+ *  0b001..Reserved
+ *  0b010..Match is enabled (1st data word equals MATCH0 OR MATCH1)
+ *  0b011..Match is enabled (any data word equals MATCH0 OR MATCH1)
+ *  0b100..Match is enabled (1st data word equals MATCH0 AND 2nd data word equals MATCH1)
+ *  0b101..Match is enabled (any data word equals MATCH0 AND next data word equals MATCH1)
+ *  0b110..Match is enabled (1st data word AND MATCH1 equals MATCH0 AND MATCH1)
+ *  0b111..Match is enabled (any data word AND MATCH1 equals MATCH0 AND MATCH1)
+ */
 #define LPI2C_MCFGR1_MATCFG(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_MATCFG_SHIFT)) & LPI2C_MCFGR1_MATCFG_MASK)
 #define LPI2C_MCFGR1_PINCFG_MASK                 (0x7000000U)
 #define LPI2C_MCFGR1_PINCFG_SHIFT                (24U)
+/*! PINCFG - Pin Configuration
+ *  0b000..2-pin open drain mode
+ *  0b001..2-pin output only mode (ultra-fast mode)
+ *  0b010..2-pin push-pull mode
+ *  0b011..4-pin push-pull mode
+ *  0b100..2-pin open drain mode with separate LPI2C slave
+ *  0b101..2-pin output only mode (ultra-fast mode) with separate LPI2C slave
+ *  0b110..2-pin push-pull mode with separate LPI2C slave
+ *  0b111..4-pin push-pull mode (inverted outputs)
+ */
 #define LPI2C_MCFGR1_PINCFG(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PINCFG_SHIFT)) & LPI2C_MCFGR1_PINCFG_MASK)
 /*! @} */
 
@@ -15632,6 +24704,16 @@ typedef struct {
 #define LPI2C_MTDR_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_DATA_SHIFT)) & LPI2C_MTDR_DATA_MASK)
 #define LPI2C_MTDR_CMD_MASK                      (0x700U)
 #define LPI2C_MTDR_CMD_SHIFT                     (8U)
+/*! CMD - Command Data
+ *  0b000..Transmit DATA[7:0]
+ *  0b001..Receive (DATA[7:0] + 1) bytes
+ *  0b010..Generate STOP condition
+ *  0b011..Receive and discard (DATA[7:0] + 1) bytes
+ *  0b100..Generate (repeated) START and transmit address in DATA[7:0]
+ *  0b101..Generate (repeated) START and transmit address in DATA[7:0]. This transfer expects a NACK to be returned.
+ *  0b110..Generate (repeated) START and transmit address in DATA[7:0] using high speed mode
+ *  0b111..Generate (repeated) START and transmit address in DATA[7:0] using high speed mode. This transfer expects a NACK to be returned.
+ */
 #define LPI2C_MTDR_CMD(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_CMD_SHIFT)) & LPI2C_MTDR_CMD_MASK)
 /*! @} */
 
@@ -15642,6 +24724,10 @@ typedef struct {
 #define LPI2C_MRDR_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_DATA_SHIFT)) & LPI2C_MRDR_DATA_MASK)
 #define LPI2C_MRDR_RXEMPTY_MASK                  (0x4000U)
 #define LPI2C_MRDR_RXEMPTY_SHIFT                 (14U)
+/*! RXEMPTY - RX Empty
+ *  0b0..Receive FIFO is not empty
+ *  0b1..Receive FIFO is empty
+ */
 #define LPI2C_MRDR_RXEMPTY(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_RXEMPTY_SHIFT)) & LPI2C_MRDR_RXEMPTY_MASK)
 /*! @} */
 
@@ -15649,21 +24735,45 @@ typedef struct {
 /*! @{ */
 #define LPI2C_SCR_SEN_MASK                       (0x1U)
 #define LPI2C_SCR_SEN_SHIFT                      (0U)
+/*! SEN - Slave Enable
+ *  0b0..I2C Slave mode is disabled
+ *  0b1..I2C Slave mode is enabled
+ */
 #define LPI2C_SCR_SEN(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_SEN_SHIFT)) & LPI2C_SCR_SEN_MASK)
 #define LPI2C_SCR_RST_MASK                       (0x2U)
 #define LPI2C_SCR_RST_SHIFT                      (1U)
+/*! RST - Software Reset
+ *  0b0..Slave mode logic is not reset
+ *  0b1..Slave mode logic is reset
+ */
 #define LPI2C_SCR_RST(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RST_SHIFT)) & LPI2C_SCR_RST_MASK)
 #define LPI2C_SCR_FILTEN_MASK                    (0x10U)
 #define LPI2C_SCR_FILTEN_SHIFT                   (4U)
+/*! FILTEN - Filter Enable
+ *  0b0..Disable digital filter and output delay counter for slave mode
+ *  0b1..Enable digital filter and output delay counter for slave mode
+ */
 #define LPI2C_SCR_FILTEN(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTEN_SHIFT)) & LPI2C_SCR_FILTEN_MASK)
 #define LPI2C_SCR_FILTDZ_MASK                    (0x20U)
 #define LPI2C_SCR_FILTDZ_SHIFT                   (5U)
+/*! FILTDZ - Filter Doze Enable
+ *  0b0..Filter remains enabled in Doze mode
+ *  0b1..Filter is disabled in Doze mode
+ */
 #define LPI2C_SCR_FILTDZ(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTDZ_SHIFT)) & LPI2C_SCR_FILTDZ_MASK)
 #define LPI2C_SCR_RTF_MASK                       (0x100U)
 #define LPI2C_SCR_RTF_SHIFT                      (8U)
+/*! RTF - Reset Transmit FIFO
+ *  0b0..No effect
+ *  0b1..Transmit Data Register is now empty
+ */
 #define LPI2C_SCR_RTF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RTF_SHIFT)) & LPI2C_SCR_RTF_MASK)
 #define LPI2C_SCR_RRF_MASK                       (0x200U)
 #define LPI2C_SCR_RRF_SHIFT                      (9U)
+/*! RRF - Reset Receive FIFO
+ *  0b0..No effect
+ *  0b1..Receive Data Register is now empty
+ */
 #define LPI2C_SCR_RRF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RRF_SHIFT)) & LPI2C_SCR_RRF_MASK)
 /*! @} */
 
@@ -15671,45 +24781,101 @@ typedef struct {
 /*! @{ */
 #define LPI2C_SSR_TDF_MASK                       (0x1U)
 #define LPI2C_SSR_TDF_SHIFT                      (0U)
+/*! TDF - Transmit Data Flag
+ *  0b0..Transmit data not requested
+ *  0b1..Transmit data is requested
+ */
 #define LPI2C_SSR_TDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TDF_SHIFT)) & LPI2C_SSR_TDF_MASK)
 #define LPI2C_SSR_RDF_MASK                       (0x2U)
 #define LPI2C_SSR_RDF_SHIFT                      (1U)
+/*! RDF - Receive Data Flag
+ *  0b0..Receive data is not ready
+ *  0b1..Receive data is ready
+ */
 #define LPI2C_SSR_RDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RDF_SHIFT)) & LPI2C_SSR_RDF_MASK)
 #define LPI2C_SSR_AVF_MASK                       (0x4U)
 #define LPI2C_SSR_AVF_SHIFT                      (2U)
+/*! AVF - Address Valid Flag
+ *  0b0..Address Status Register is not valid
+ *  0b1..Address Status Register is valid
+ */
 #define LPI2C_SSR_AVF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AVF_SHIFT)) & LPI2C_SSR_AVF_MASK)
 #define LPI2C_SSR_TAF_MASK                       (0x8U)
 #define LPI2C_SSR_TAF_SHIFT                      (3U)
+/*! TAF - Transmit ACK Flag
+ *  0b0..Transmit ACK/NACK is not required
+ *  0b1..Transmit ACK/NACK is required
+ */
 #define LPI2C_SSR_TAF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TAF_SHIFT)) & LPI2C_SSR_TAF_MASK)
 #define LPI2C_SSR_RSF_MASK                       (0x100U)
 #define LPI2C_SSR_RSF_SHIFT                      (8U)
+/*! RSF - Repeated Start Flag
+ *  0b0..Slave has not detected a Repeated START condition
+ *  0b1..Slave has detected a Repeated START condition
+ */
 #define LPI2C_SSR_RSF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RSF_SHIFT)) & LPI2C_SSR_RSF_MASK)
 #define LPI2C_SSR_SDF_MASK                       (0x200U)
 #define LPI2C_SSR_SDF_SHIFT                      (9U)
+/*! SDF - STOP Detect Flag
+ *  0b0..Slave has not detected a STOP condition
+ *  0b1..Slave has detected a STOP condition
+ */
 #define LPI2C_SSR_SDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SDF_SHIFT)) & LPI2C_SSR_SDF_MASK)
 #define LPI2C_SSR_BEF_MASK                       (0x400U)
 #define LPI2C_SSR_BEF_SHIFT                      (10U)
+/*! BEF - Bit Error Flag
+ *  0b0..Slave has not detected a bit error
+ *  0b1..Slave has detected a bit error
+ */
 #define LPI2C_SSR_BEF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BEF_SHIFT)) & LPI2C_SSR_BEF_MASK)
 #define LPI2C_SSR_FEF_MASK                       (0x800U)
 #define LPI2C_SSR_FEF_SHIFT                      (11U)
+/*! FEF - FIFO Error Flag
+ *  0b0..FIFO underflow or overflow was not detected
+ *  0b1..FIFO underflow or overflow was detected
+ */
 #define LPI2C_SSR_FEF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_FEF_SHIFT)) & LPI2C_SSR_FEF_MASK)
 #define LPI2C_SSR_AM0F_MASK                      (0x1000U)
 #define LPI2C_SSR_AM0F_SHIFT                     (12U)
+/*! AM0F - Address Match 0 Flag
+ *  0b0..Have not received an ADDR0 matching address
+ *  0b1..Have received an ADDR0 matching address
+ */
 #define LPI2C_SSR_AM0F(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM0F_SHIFT)) & LPI2C_SSR_AM0F_MASK)
 #define LPI2C_SSR_AM1F_MASK                      (0x2000U)
 #define LPI2C_SSR_AM1F_SHIFT                     (13U)
+/*! AM1F - Address Match 1 Flag
+ *  0b0..Have not received an ADDR1 or ADDR0/ADDR1 range matching address
+ *  0b1..Have received an ADDR1 or ADDR0/ADDR1 range matching address
+ */
 #define LPI2C_SSR_AM1F(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM1F_SHIFT)) & LPI2C_SSR_AM1F_MASK)
 #define LPI2C_SSR_GCF_MASK                       (0x4000U)
 #define LPI2C_SSR_GCF_SHIFT                      (14U)
+/*! GCF - General Call Flag
+ *  0b0..Slave has not detected the General Call Address or the General Call Address is disabled
+ *  0b1..Slave has detected the General Call Address
+ */
 #define LPI2C_SSR_GCF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_GCF_SHIFT)) & LPI2C_SSR_GCF_MASK)
 #define LPI2C_SSR_SARF_MASK                      (0x8000U)
 #define LPI2C_SSR_SARF_SHIFT                     (15U)
+/*! SARF - SMBus Alert Response Flag
+ *  0b0..SMBus Alert Response is disabled or not detected
+ *  0b1..SMBus Alert Response is enabled and detected
+ */
 #define LPI2C_SSR_SARF(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SARF_SHIFT)) & LPI2C_SSR_SARF_MASK)
 #define LPI2C_SSR_SBF_MASK                       (0x1000000U)
 #define LPI2C_SSR_SBF_SHIFT                      (24U)
+/*! SBF - Slave Busy Flag
+ *  0b0..I2C Slave is idle
+ *  0b1..I2C Slave is busy
+ */
 #define LPI2C_SSR_SBF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SBF_SHIFT)) & LPI2C_SSR_SBF_MASK)
 #define LPI2C_SSR_BBF_MASK                       (0x2000000U)
 #define LPI2C_SSR_BBF_SHIFT                      (25U)
+/*! BBF - Bus Busy Flag
+ *  0b0..I2C Bus is idle
+ *  0b1..I2C Bus is busy
+ */
 #define LPI2C_SSR_BBF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BBF_SHIFT)) & LPI2C_SSR_BBF_MASK)
 /*! @} */
 
@@ -15717,39 +24883,87 @@ typedef struct {
 /*! @{ */
 #define LPI2C_SIER_TDIE_MASK                     (0x1U)
 #define LPI2C_SIER_TDIE_SHIFT                    (0U)
+/*! TDIE - Transmit Data Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
 #define LPI2C_SIER_TDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TDIE_SHIFT)) & LPI2C_SIER_TDIE_MASK)
 #define LPI2C_SIER_RDIE_MASK                     (0x2U)
 #define LPI2C_SIER_RDIE_SHIFT                    (1U)
+/*! RDIE - Receive Data Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
 #define LPI2C_SIER_RDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RDIE_SHIFT)) & LPI2C_SIER_RDIE_MASK)
 #define LPI2C_SIER_AVIE_MASK                     (0x4U)
 #define LPI2C_SIER_AVIE_SHIFT                    (2U)
+/*! AVIE - Address Valid Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
 #define LPI2C_SIER_AVIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AVIE_SHIFT)) & LPI2C_SIER_AVIE_MASK)
 #define LPI2C_SIER_TAIE_MASK                     (0x8U)
 #define LPI2C_SIER_TAIE_SHIFT                    (3U)
+/*! TAIE - Transmit ACK Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
 #define LPI2C_SIER_TAIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TAIE_SHIFT)) & LPI2C_SIER_TAIE_MASK)
 #define LPI2C_SIER_RSIE_MASK                     (0x100U)
 #define LPI2C_SIER_RSIE_SHIFT                    (8U)
+/*! RSIE - Repeated Start Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
 #define LPI2C_SIER_RSIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RSIE_SHIFT)) & LPI2C_SIER_RSIE_MASK)
 #define LPI2C_SIER_SDIE_MASK                     (0x200U)
 #define LPI2C_SIER_SDIE_SHIFT                    (9U)
+/*! SDIE - STOP Detect Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
 #define LPI2C_SIER_SDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SDIE_SHIFT)) & LPI2C_SIER_SDIE_MASK)
 #define LPI2C_SIER_BEIE_MASK                     (0x400U)
 #define LPI2C_SIER_BEIE_SHIFT                    (10U)
+/*! BEIE - Bit Error Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
 #define LPI2C_SIER_BEIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_BEIE_SHIFT)) & LPI2C_SIER_BEIE_MASK)
 #define LPI2C_SIER_FEIE_MASK                     (0x800U)
 #define LPI2C_SIER_FEIE_SHIFT                    (11U)
+/*! FEIE - FIFO Error Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
 #define LPI2C_SIER_FEIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_FEIE_SHIFT)) & LPI2C_SIER_FEIE_MASK)
 #define LPI2C_SIER_AM0IE_MASK                    (0x1000U)
 #define LPI2C_SIER_AM0IE_SHIFT                   (12U)
+/*! AM0IE - Address Match 0 Interrupt Enable
+ *  0b0..Enabled
+ *  0b1..Disabled
+ */
 #define LPI2C_SIER_AM0IE(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM0IE_SHIFT)) & LPI2C_SIER_AM0IE_MASK)
 #define LPI2C_SIER_AM1F_MASK                     (0x2000U)
 #define LPI2C_SIER_AM1F_SHIFT                    (13U)
+/*! AM1F - Address Match 1 Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
 #define LPI2C_SIER_AM1F(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM1F_SHIFT)) & LPI2C_SIER_AM1F_MASK)
 #define LPI2C_SIER_GCIE_MASK                     (0x4000U)
 #define LPI2C_SIER_GCIE_SHIFT                    (14U)
+/*! GCIE - General Call Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
 #define LPI2C_SIER_GCIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_GCIE_SHIFT)) & LPI2C_SIER_GCIE_MASK)
 #define LPI2C_SIER_SARIE_MASK                    (0x8000U)
 #define LPI2C_SIER_SARIE_SHIFT                   (15U)
+/*! SARIE - SMBus Alert Response Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
 #define LPI2C_SIER_SARIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SARIE_SHIFT)) & LPI2C_SIER_SARIE_MASK)
 /*! @} */
 
@@ -15757,12 +24971,24 @@ typedef struct {
 /*! @{ */
 #define LPI2C_SDER_TDDE_MASK                     (0x1U)
 #define LPI2C_SDER_TDDE_SHIFT                    (0U)
+/*! TDDE - Transmit Data DMA Enable
+ *  0b0..DMA request is disabled
+ *  0b1..DMA request is enabled
+ */
 #define LPI2C_SDER_TDDE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_TDDE_SHIFT)) & LPI2C_SDER_TDDE_MASK)
 #define LPI2C_SDER_RDDE_MASK                     (0x2U)
 #define LPI2C_SDER_RDDE_SHIFT                    (1U)
+/*! RDDE - Receive Data DMA Enable
+ *  0b0..DMA request is disabled
+ *  0b1..DMA request is enabled
+ */
 #define LPI2C_SDER_RDDE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_RDDE_SHIFT)) & LPI2C_SDER_RDDE_MASK)
 #define LPI2C_SDER_AVDE_MASK                     (0x4U)
 #define LPI2C_SDER_AVDE_SHIFT                    (2U)
+/*! AVDE - Address Valid DMA Enable
+ *  0b0..DMA request is disabled
+ *  0b1..DMA request is enabled
+ */
 #define LPI2C_SDER_AVDE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_AVDE_SHIFT)) & LPI2C_SDER_AVDE_MASK)
 /*! @} */
 
@@ -15770,36 +24996,88 @@ typedef struct {
 /*! @{ */
 #define LPI2C_SCFGR1_ADRSTALL_MASK               (0x1U)
 #define LPI2C_SCFGR1_ADRSTALL_SHIFT              (0U)
+/*! ADRSTALL - Address SCL Stall
+ *  0b0..Clock stretching is disabled
+ *  0b1..Clock stretching is enabled
+ */
 #define LPI2C_SCFGR1_ADRSTALL(x)                 (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADRSTALL_SHIFT)) & LPI2C_SCFGR1_ADRSTALL_MASK)
 #define LPI2C_SCFGR1_RXSTALL_MASK                (0x2U)
 #define LPI2C_SCFGR1_RXSTALL_SHIFT               (1U)
+/*! RXSTALL - RX SCL Stall
+ *  0b0..Clock stretching is disabled
+ *  0b1..Clock stretching is enabled
+ */
 #define LPI2C_SCFGR1_RXSTALL(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXSTALL_SHIFT)) & LPI2C_SCFGR1_RXSTALL_MASK)
 #define LPI2C_SCFGR1_TXDSTALL_MASK               (0x4U)
 #define LPI2C_SCFGR1_TXDSTALL_SHIFT              (2U)
+/*! TXDSTALL - TX Data SCL Stall
+ *  0b0..Clock stretching is disabled
+ *  0b1..Clock stretching is enabled
+ */
 #define LPI2C_SCFGR1_TXDSTALL(x)                 (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXDSTALL_SHIFT)) & LPI2C_SCFGR1_TXDSTALL_MASK)
 #define LPI2C_SCFGR1_ACKSTALL_MASK               (0x8U)
 #define LPI2C_SCFGR1_ACKSTALL_SHIFT              (3U)
+/*! ACKSTALL - ACK SCL Stall
+ *  0b0..Clock stretching is disabled
+ *  0b1..Clock stretching is enabled
+ */
 #define LPI2C_SCFGR1_ACKSTALL(x)                 (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ACKSTALL_SHIFT)) & LPI2C_SCFGR1_ACKSTALL_MASK)
 #define LPI2C_SCFGR1_GCEN_MASK                   (0x100U)
 #define LPI2C_SCFGR1_GCEN_SHIFT                  (8U)
+/*! GCEN - General Call Enable
+ *  0b0..General Call address is disabled
+ *  0b1..General Call address is enabled
+ */
 #define LPI2C_SCFGR1_GCEN(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_GCEN_SHIFT)) & LPI2C_SCFGR1_GCEN_MASK)
 #define LPI2C_SCFGR1_SAEN_MASK                   (0x200U)
 #define LPI2C_SCFGR1_SAEN_SHIFT                  (9U)
+/*! SAEN - SMBus Alert Enable
+ *  0b0..Disables match on SMBus Alert
+ *  0b1..Enables match on SMBus Alert
+ */
 #define LPI2C_SCFGR1_SAEN(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_SAEN_SHIFT)) & LPI2C_SCFGR1_SAEN_MASK)
 #define LPI2C_SCFGR1_TXCFG_MASK                  (0x400U)
 #define LPI2C_SCFGR1_TXCFG_SHIFT                 (10U)
+/*! TXCFG - Transmit Flag Configuration
+ *  0b0..Transmit Data Flag will only assert during a slave-transmit transfer when the Transmit Data register is empty
+ *  0b1..Transmit Data Flag will assert whenever the Transmit Data register is empty
+ */
 #define LPI2C_SCFGR1_TXCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXCFG_SHIFT)) & LPI2C_SCFGR1_TXCFG_MASK)
 #define LPI2C_SCFGR1_RXCFG_MASK                  (0x800U)
 #define LPI2C_SCFGR1_RXCFG_SHIFT                 (11U)
+/*! RXCFG - Receive Data Configuration
+ *  0b0..Reading the Receive Data register will return received data and clear the Receive Data flag (MSR[RDF]).
+ *  0b1..Reading the Receive Data register when the Address Valid flag (SSR[AVF])is set, will return the Address
+ *       Status register and clear the Address Valid flag. Reading the Receive Data register when the Address Valid
+ *       flag is clear, will return received data and clear the Receive Data flag (MSR[RDF]).
+ */
 #define LPI2C_SCFGR1_RXCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXCFG_SHIFT)) & LPI2C_SCFGR1_RXCFG_MASK)
 #define LPI2C_SCFGR1_IGNACK_MASK                 (0x1000U)
 #define LPI2C_SCFGR1_IGNACK_SHIFT                (12U)
+/*! IGNACK - Ignore NACK
+ *  0b0..Slave will end transfer when NACK is detected
+ *  0b1..Slave will not end transfer when NACK detected
+ */
 #define LPI2C_SCFGR1_IGNACK(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_IGNACK_SHIFT)) & LPI2C_SCFGR1_IGNACK_MASK)
 #define LPI2C_SCFGR1_HSMEN_MASK                  (0x2000U)
 #define LPI2C_SCFGR1_HSMEN_SHIFT                 (13U)
+/*! HSMEN - High Speed Mode Enable
+ *  0b0..Disables detection of HS-mode master code
+ *  0b1..Enables detection of HS-mode master code
+ */
 #define LPI2C_SCFGR1_HSMEN(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_HSMEN_SHIFT)) & LPI2C_SCFGR1_HSMEN_MASK)
 #define LPI2C_SCFGR1_ADDRCFG_MASK                (0x70000U)
 #define LPI2C_SCFGR1_ADDRCFG_SHIFT               (16U)
+/*! ADDRCFG - Address Configuration
+ *  0b000..Address match 0 (7-bit)
+ *  0b001..Address match 0 (10-bit)
+ *  0b010..Address match 0 (7-bit) or Address match 1 (7-bit)
+ *  0b011..Address match 0 (10-bit) or Address match 1 (10-bit)
+ *  0b100..Address match 0 (7-bit) or Address match 1 (10-bit)
+ *  0b101..Address match 0 (10-bit) or Address match 1 (7-bit)
+ *  0b110..From Address match 0 (7-bit) to Address match 1 (7-bit)
+ *  0b111..From Address match 0 (10-bit) to Address match 1 (10-bit)
+ */
 #define LPI2C_SCFGR1_ADDRCFG(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADDRCFG_SHIFT)) & LPI2C_SCFGR1_ADDRCFG_MASK)
 /*! @} */
 
@@ -15836,6 +25114,10 @@ typedef struct {
 #define LPI2C_SASR_RADDR(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_RADDR_SHIFT)) & LPI2C_SASR_RADDR_MASK)
 #define LPI2C_SASR_ANV_MASK                      (0x4000U)
 #define LPI2C_SASR_ANV_SHIFT                     (14U)
+/*! ANV - Address Not Valid
+ *  0b0..Received Address (RADDR) is valid
+ *  0b1..Received Address (RADDR) is not valid
+ */
 #define LPI2C_SASR_ANV(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_ANV_SHIFT)) & LPI2C_SASR_ANV_MASK)
 /*! @} */
 
@@ -15843,6 +25125,10 @@ typedef struct {
 /*! @{ */
 #define LPI2C_STAR_TXNACK_MASK                   (0x1U)
 #define LPI2C_STAR_TXNACK_SHIFT                  (0U)
+/*! TXNACK - Transmit NACK
+ *  0b0..Write a Transmit ACK for each received word
+ *  0b1..Write a Transmit NACK for each received word
+ */
 #define LPI2C_STAR_TXNACK(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_STAR_TXNACK_SHIFT)) & LPI2C_STAR_TXNACK_MASK)
 /*! @} */
 
@@ -15860,9 +25146,17 @@ typedef struct {
 #define LPI2C_SRDR_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_DATA_SHIFT)) & LPI2C_SRDR_DATA_MASK)
 #define LPI2C_SRDR_RXEMPTY_MASK                  (0x4000U)
 #define LPI2C_SRDR_RXEMPTY_SHIFT                 (14U)
+/*! RXEMPTY - RX Empty
+ *  0b0..The Receive Data Register is not empty
+ *  0b1..The Receive Data Register is empty
+ */
 #define LPI2C_SRDR_RXEMPTY(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_RXEMPTY_SHIFT)) & LPI2C_SRDR_RXEMPTY_MASK)
 #define LPI2C_SRDR_SOF_MASK                      (0x8000U)
 #define LPI2C_SRDR_SOF_SHIFT                     (15U)
+/*! SOF - Start Of Frame
+ *  0b0..Indicates this is not the first data word since a (repeated) START or STOP condition
+ *  0b1..Indicates this is the first data word since a (repeated) START or STOP condition
+ */
 #define LPI2C_SRDR_SOF(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_SOF_SHIFT)) & LPI2C_SRDR_SOF_MASK)
 /*! @} */
 
@@ -15949,6 +25243,9 @@ typedef struct {
 /*! @{ */
 #define LPSPI_VERID_FEATURE_MASK                 (0xFFFFU)
 #define LPSPI_VERID_FEATURE_SHIFT                (0U)
+/*! FEATURE - Module Identification Number
+ *  0b0000000000000100..Standard feature set supporting a 32-bit shift register.
+ */
 #define LPSPI_VERID_FEATURE(x)                   (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_FEATURE_SHIFT)) & LPSPI_VERID_FEATURE_MASK)
 #define LPSPI_VERID_MINOR_MASK                   (0xFF0000U)
 #define LPSPI_VERID_MINOR_SHIFT                  (16U)
@@ -15975,21 +25272,45 @@ typedef struct {
 /*! @{ */
 #define LPSPI_CR_MEN_MASK                        (0x1U)
 #define LPSPI_CR_MEN_SHIFT                       (0U)
+/*! MEN - Module Enable
+ *  0b0..Module is disabled
+ *  0b1..Module is enabled
+ */
 #define LPSPI_CR_MEN(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_MEN_SHIFT)) & LPSPI_CR_MEN_MASK)
 #define LPSPI_CR_RST_MASK                        (0x2U)
 #define LPSPI_CR_RST_SHIFT                       (1U)
+/*! RST - Software Reset
+ *  0b0..Module is not reset
+ *  0b1..Module is reset
+ */
 #define LPSPI_CR_RST(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RST_SHIFT)) & LPSPI_CR_RST_MASK)
 #define LPSPI_CR_DOZEN_MASK                      (0x4U)
 #define LPSPI_CR_DOZEN_SHIFT                     (2U)
+/*! DOZEN - Doze mode enable
+ *  0b0..Module is enabled in Doze mode
+ *  0b1..Module is disabled in Doze mode
+ */
 #define LPSPI_CR_DOZEN(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DOZEN_SHIFT)) & LPSPI_CR_DOZEN_MASK)
 #define LPSPI_CR_DBGEN_MASK                      (0x8U)
 #define LPSPI_CR_DBGEN_SHIFT                     (3U)
+/*! DBGEN - Debug Enable
+ *  0b0..Module is disabled in debug mode
+ *  0b1..Module is enabled in debug mode
+ */
 #define LPSPI_CR_DBGEN(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DBGEN_SHIFT)) & LPSPI_CR_DBGEN_MASK)
 #define LPSPI_CR_RTF_MASK                        (0x100U)
 #define LPSPI_CR_RTF_SHIFT                       (8U)
+/*! RTF - Reset Transmit FIFO
+ *  0b0..No effect
+ *  0b1..Transmit FIFO is reset
+ */
 #define LPSPI_CR_RTF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RTF_SHIFT)) & LPSPI_CR_RTF_MASK)
 #define LPSPI_CR_RRF_MASK                        (0x200U)
 #define LPSPI_CR_RRF_SHIFT                       (9U)
+/*! RRF - Reset Receive FIFO
+ *  0b0..No effect
+ *  0b1..Receive FIFO is reset
+ */
 #define LPSPI_CR_RRF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RRF_SHIFT)) & LPSPI_CR_RRF_MASK)
 /*! @} */
 
@@ -15997,30 +25318,66 @@ typedef struct {
 /*! @{ */
 #define LPSPI_SR_TDF_MASK                        (0x1U)
 #define LPSPI_SR_TDF_SHIFT                       (0U)
+/*! TDF - Transmit Data Flag
+ *  0b0..Transmit data not requested
+ *  0b1..Transmit data is requested
+ */
 #define LPSPI_SR_TDF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TDF_SHIFT)) & LPSPI_SR_TDF_MASK)
 #define LPSPI_SR_RDF_MASK                        (0x2U)
 #define LPSPI_SR_RDF_SHIFT                       (1U)
+/*! RDF - Receive Data Flag
+ *  0b0..Receive Data is not ready
+ *  0b1..Receive data is ready
+ */
 #define LPSPI_SR_RDF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_RDF_SHIFT)) & LPSPI_SR_RDF_MASK)
 #define LPSPI_SR_WCF_MASK                        (0x100U)
 #define LPSPI_SR_WCF_SHIFT                       (8U)
+/*! WCF - Word Complete Flag
+ *  0b0..Transfer of a received word has not yet completed
+ *  0b1..Transfer of a received word has completed
+ */
 #define LPSPI_SR_WCF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_WCF_SHIFT)) & LPSPI_SR_WCF_MASK)
 #define LPSPI_SR_FCF_MASK                        (0x200U)
 #define LPSPI_SR_FCF_SHIFT                       (9U)
+/*! FCF - Frame Complete Flag
+ *  0b0..Frame transfer has not completed
+ *  0b1..Frame transfer has completed
+ */
 #define LPSPI_SR_FCF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_FCF_SHIFT)) & LPSPI_SR_FCF_MASK)
 #define LPSPI_SR_TCF_MASK                        (0x400U)
 #define LPSPI_SR_TCF_SHIFT                       (10U)
+/*! TCF - Transfer Complete Flag
+ *  0b0..All transfers have not completed
+ *  0b1..All transfers have completed
+ */
 #define LPSPI_SR_TCF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TCF_SHIFT)) & LPSPI_SR_TCF_MASK)
 #define LPSPI_SR_TEF_MASK                        (0x800U)
 #define LPSPI_SR_TEF_SHIFT                       (11U)
+/*! TEF - Transmit Error Flag
+ *  0b0..Transmit FIFO underrun has not occurred
+ *  0b1..Transmit FIFO underrun has occurred
+ */
 #define LPSPI_SR_TEF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TEF_SHIFT)) & LPSPI_SR_TEF_MASK)
 #define LPSPI_SR_REF_MASK                        (0x1000U)
 #define LPSPI_SR_REF_SHIFT                       (12U)
+/*! REF - Receive Error Flag
+ *  0b0..Receive FIFO has not overflowed
+ *  0b1..Receive FIFO has overflowed
+ */
 #define LPSPI_SR_REF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_REF_SHIFT)) & LPSPI_SR_REF_MASK)
 #define LPSPI_SR_DMF_MASK                        (0x2000U)
 #define LPSPI_SR_DMF_SHIFT                       (13U)
+/*! DMF - Data Match Flag
+ *  0b0..Have not received matching data
+ *  0b1..Have received matching data
+ */
 #define LPSPI_SR_DMF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_DMF_SHIFT)) & LPSPI_SR_DMF_MASK)
 #define LPSPI_SR_MBF_MASK                        (0x1000000U)
 #define LPSPI_SR_MBF_SHIFT                       (24U)
+/*! MBF - Module Busy Flag
+ *  0b0..LPSPI is idle
+ *  0b1..LPSPI is busy
+ */
 #define LPSPI_SR_MBF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_MBF_SHIFT)) & LPSPI_SR_MBF_MASK)
 /*! @} */
 
@@ -16028,27 +25385,59 @@ typedef struct {
 /*! @{ */
 #define LPSPI_IER_TDIE_MASK                      (0x1U)
 #define LPSPI_IER_TDIE_SHIFT                     (0U)
+/*! TDIE - Transmit Data Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
 #define LPSPI_IER_TDIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TDIE_SHIFT)) & LPSPI_IER_TDIE_MASK)
 #define LPSPI_IER_RDIE_MASK                      (0x2U)
 #define LPSPI_IER_RDIE_SHIFT                     (1U)
+/*! RDIE - Receive Data Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
 #define LPSPI_IER_RDIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_RDIE_SHIFT)) & LPSPI_IER_RDIE_MASK)
 #define LPSPI_IER_WCIE_MASK                      (0x100U)
 #define LPSPI_IER_WCIE_SHIFT                     (8U)
+/*! WCIE - Word Complete Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
 #define LPSPI_IER_WCIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_WCIE_SHIFT)) & LPSPI_IER_WCIE_MASK)
 #define LPSPI_IER_FCIE_MASK                      (0x200U)
 #define LPSPI_IER_FCIE_SHIFT                     (9U)
+/*! FCIE - Frame Complete Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
 #define LPSPI_IER_FCIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_FCIE_SHIFT)) & LPSPI_IER_FCIE_MASK)
 #define LPSPI_IER_TCIE_MASK                      (0x400U)
 #define LPSPI_IER_TCIE_SHIFT                     (10U)
+/*! TCIE - Transfer Complete Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
 #define LPSPI_IER_TCIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TCIE_SHIFT)) & LPSPI_IER_TCIE_MASK)
 #define LPSPI_IER_TEIE_MASK                      (0x800U)
 #define LPSPI_IER_TEIE_SHIFT                     (11U)
+/*! TEIE - Transmit Error Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
 #define LPSPI_IER_TEIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TEIE_SHIFT)) & LPSPI_IER_TEIE_MASK)
 #define LPSPI_IER_REIE_MASK                      (0x1000U)
 #define LPSPI_IER_REIE_SHIFT                     (12U)
+/*! REIE - Receive Error Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
 #define LPSPI_IER_REIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_REIE_SHIFT)) & LPSPI_IER_REIE_MASK)
 #define LPSPI_IER_DMIE_MASK                      (0x2000U)
 #define LPSPI_IER_DMIE_SHIFT                     (13U)
+/*! DMIE - Data Match Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
 #define LPSPI_IER_DMIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_DMIE_SHIFT)) & LPSPI_IER_DMIE_MASK)
 /*! @} */
 
@@ -16056,9 +25445,17 @@ typedef struct {
 /*! @{ */
 #define LPSPI_DER_TDDE_MASK                      (0x1U)
 #define LPSPI_DER_TDDE_SHIFT                     (0U)
+/*! TDDE - Transmit Data DMA Enable
+ *  0b0..DMA request is disabled
+ *  0b1..DMA request is enabled
+ */
 #define LPSPI_DER_TDDE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_TDDE_SHIFT)) & LPSPI_DER_TDDE_MASK)
 #define LPSPI_DER_RDDE_MASK                      (0x2U)
 #define LPSPI_DER_RDDE_SHIFT                     (1U)
+/*! RDDE - Receive Data DMA Enable
+ *  0b0..DMA request is disabled
+ *  0b1..DMA request is enabled
+ */
 #define LPSPI_DER_RDDE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_RDDE_SHIFT)) & LPSPI_DER_RDDE_MASK)
 /*! @} */
 
@@ -16066,18 +25463,38 @@ typedef struct {
 /*! @{ */
 #define LPSPI_CFGR0_HREN_MASK                    (0x1U)
 #define LPSPI_CFGR0_HREN_SHIFT                   (0U)
+/*! HREN - Host Request Enable
+ *  0b0..Host request is disabled
+ *  0b1..Host request is enabled
+ */
 #define LPSPI_CFGR0_HREN(x)                      (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HREN_SHIFT)) & LPSPI_CFGR0_HREN_MASK)
 #define LPSPI_CFGR0_HRPOL_MASK                   (0x2U)
 #define LPSPI_CFGR0_HRPOL_SHIFT                  (1U)
+/*! HRPOL - Host Request Polarity
+ *  0b0..Active low
+ *  0b1..Active high
+ */
 #define LPSPI_CFGR0_HRPOL(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRPOL_SHIFT)) & LPSPI_CFGR0_HRPOL_MASK)
 #define LPSPI_CFGR0_HRSEL_MASK                   (0x4U)
 #define LPSPI_CFGR0_HRSEL_SHIFT                  (2U)
+/*! HRSEL - Host Request Select
+ *  0b0..Host request input is the LPSPI_HREQ pin
+ *  0b1..Host request input is the input trigger
+ */
 #define LPSPI_CFGR0_HRSEL(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRSEL_SHIFT)) & LPSPI_CFGR0_HRSEL_MASK)
 #define LPSPI_CFGR0_CIRFIFO_MASK                 (0x100U)
 #define LPSPI_CFGR0_CIRFIFO_SHIFT                (8U)
+/*! CIRFIFO - Circular FIFO Enable
+ *  0b0..Circular FIFO is disabled
+ *  0b1..Circular FIFO is enabled
+ */
 #define LPSPI_CFGR0_CIRFIFO(x)                   (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_CIRFIFO_SHIFT)) & LPSPI_CFGR0_CIRFIFO_MASK)
 #define LPSPI_CFGR0_RDMO_MASK                    (0x200U)
 #define LPSPI_CFGR0_RDMO_SHIFT                   (9U)
+/*! RDMO - Receive Data Match Only
+ *  0b0..Received data is stored in the receive FIFO as in normal operations
+ *  0b1..Received data is discarded unless the Data Match Flag (DMF) is set
+ */
 #define LPSPI_CFGR0_RDMO(x)                      (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_RDMO_SHIFT)) & LPSPI_CFGR0_RDMO_MASK)
 /*! @} */
 
@@ -16085,30 +25502,76 @@ typedef struct {
 /*! @{ */
 #define LPSPI_CFGR1_MASTER_MASK                  (0x1U)
 #define LPSPI_CFGR1_MASTER_SHIFT                 (0U)
+/*! MASTER - Master Mode
+ *  0b0..Slave mode
+ *  0b1..Master mode
+ */
 #define LPSPI_CFGR1_MASTER(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MASTER_SHIFT)) & LPSPI_CFGR1_MASTER_MASK)
 #define LPSPI_CFGR1_SAMPLE_MASK                  (0x2U)
 #define LPSPI_CFGR1_SAMPLE_SHIFT                 (1U)
+/*! SAMPLE - Sample Point
+ *  0b0..Input data is sampled on SCK edge
+ *  0b1..Input data is sampled on delayed SCK edge
+ */
 #define LPSPI_CFGR1_SAMPLE(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_SAMPLE_SHIFT)) & LPSPI_CFGR1_SAMPLE_MASK)
 #define LPSPI_CFGR1_AUTOPCS_MASK                 (0x4U)
 #define LPSPI_CFGR1_AUTOPCS_SHIFT                (2U)
+/*! AUTOPCS - Automatic PCS
+ *  0b0..Automatic PCS generation is disabled
+ *  0b1..Automatic PCS generation is enabled
+ */
 #define LPSPI_CFGR1_AUTOPCS(x)                   (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_AUTOPCS_SHIFT)) & LPSPI_CFGR1_AUTOPCS_MASK)
 #define LPSPI_CFGR1_NOSTALL_MASK                 (0x8U)
 #define LPSPI_CFGR1_NOSTALL_SHIFT                (3U)
+/*! NOSTALL - No Stall
+ *  0b0..Transfers will stall when the transmit FIFO is empty or the receive FIFO is full
+ *  0b1..Transfers will not stall, allowing transmit FIFO underruns or receive FIFO overruns to occur
+ */
 #define LPSPI_CFGR1_NOSTALL(x)                   (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_NOSTALL_SHIFT)) & LPSPI_CFGR1_NOSTALL_MASK)
 #define LPSPI_CFGR1_PCSPOL_MASK                  (0xF00U)
 #define LPSPI_CFGR1_PCSPOL_SHIFT                 (8U)
+/*! PCSPOL - Peripheral Chip Select Polarity
+ *  0b0000..The Peripheral Chip Select pin PCSx is active low
+ *  0b0001..The Peripheral Chip Select pin PCSx is active high
+ */
 #define LPSPI_CFGR1_PCSPOL(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSPOL_SHIFT)) & LPSPI_CFGR1_PCSPOL_MASK)
 #define LPSPI_CFGR1_MATCFG_MASK                  (0x70000U)
 #define LPSPI_CFGR1_MATCFG_SHIFT                 (16U)
+/*! MATCFG - Match Configuration
+ *  0b000..Match is disabled
+ *  0b001..Reserved
+ *  0b010..010b - Match is enabled, if 1st data word equals MATCH0 OR MATCH1, i.e., (1st data word = MATCH0 + MATCH1)
+ *  0b011..011b - Match is enabled, if any data word equals MATCH0 OR MATCH1, i.e., (any data word = MATCH0 + MATCH1)
+ *  0b100..100b - Match is enabled, if 1st data word equals MATCH0 AND 2nd data word equals MATCH1, i.e., [(1st
+ *         data word = MATCH0) * (2nd data word = MATCH1)]
+ *  0b101..101b - Match is enabled, if any data word equals MATCH0 AND the next data word equals MATCH1, i.e.,
+ *         [(any data word = MATCH0) * (next data word = MATCH1)]
+ *  0b110..110b - Match is enabled, if (1st data word AND MATCH1) equals (MATCH0 AND MATCH1), i.e., [(1st data word * MATCH1) = (MATCH0 * MATCH1)]
+ *  0b111..111b - Match is enabled, if (any data word AND MATCH1) equals (MATCH0 AND MATCH1), i.e., [(any data word * MATCH1) = (MATCH0 * MATCH1)]
+ */
 #define LPSPI_CFGR1_MATCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MATCFG_SHIFT)) & LPSPI_CFGR1_MATCFG_MASK)
 #define LPSPI_CFGR1_PINCFG_MASK                  (0x3000000U)
 #define LPSPI_CFGR1_PINCFG_SHIFT                 (24U)
+/*! PINCFG - Pin Configuration
+ *  0b00..SIN is used for input data and SOUT is used for output data
+ *  0b01..SIN is used for both input and output data
+ *  0b10..SOUT is used for both input and output data
+ *  0b11..SOUT is used for input data and SIN is used for output data
+ */
 #define LPSPI_CFGR1_PINCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PINCFG_SHIFT)) & LPSPI_CFGR1_PINCFG_MASK)
 #define LPSPI_CFGR1_OUTCFG_MASK                  (0x4000000U)
 #define LPSPI_CFGR1_OUTCFG_SHIFT                 (26U)
+/*! OUTCFG - Output Config
+ *  0b0..Output data retains last value when chip select is negated
+ *  0b1..Output data is tristated when chip select is negated
+ */
 #define LPSPI_CFGR1_OUTCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_OUTCFG_SHIFT)) & LPSPI_CFGR1_OUTCFG_MASK)
 #define LPSPI_CFGR1_PCSCFG_MASK                  (0x8000000U)
 #define LPSPI_CFGR1_PCSCFG_SHIFT                 (27U)
+/*! PCSCFG - Peripheral Chip Select Configuration
+ *  0b0..PCS[3:2] are enabled
+ *  0b1..PCS[3:2] are disabled
+ */
 #define LPSPI_CFGR1_PCSCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSCFG_SHIFT)) & LPSPI_CFGR1_PCSCFG_MASK)
 /*! @} */
 
@@ -16169,36 +25632,90 @@ typedef struct {
 #define LPSPI_TCR_FRAMESZ(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_FRAMESZ_SHIFT)) & LPSPI_TCR_FRAMESZ_MASK)
 #define LPSPI_TCR_WIDTH_MASK                     (0x30000U)
 #define LPSPI_TCR_WIDTH_SHIFT                    (16U)
+/*! WIDTH - Transfer Width
+ *  0b00..1 bit transfer
+ *  0b01..2 bit transfer
+ *  0b10..4 bit transfer
+ *  0b11..Reserved
+ */
 #define LPSPI_TCR_WIDTH(x)                       (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_WIDTH_SHIFT)) & LPSPI_TCR_WIDTH_MASK)
 #define LPSPI_TCR_TXMSK_MASK                     (0x40000U)
 #define LPSPI_TCR_TXMSK_SHIFT                    (18U)
+/*! TXMSK - Transmit Data Mask
+ *  0b0..Normal transfer
+ *  0b1..Mask transmit data
+ */
 #define LPSPI_TCR_TXMSK(x)                       (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_TXMSK_SHIFT)) & LPSPI_TCR_TXMSK_MASK)
 #define LPSPI_TCR_RXMSK_MASK                     (0x80000U)
 #define LPSPI_TCR_RXMSK_SHIFT                    (19U)
+/*! RXMSK - Receive Data Mask
+ *  0b0..Normal transfer
+ *  0b1..Receive data is masked
+ */
 #define LPSPI_TCR_RXMSK(x)                       (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_RXMSK_SHIFT)) & LPSPI_TCR_RXMSK_MASK)
 #define LPSPI_TCR_CONTC_MASK                     (0x100000U)
 #define LPSPI_TCR_CONTC_SHIFT                    (20U)
+/*! CONTC - Continuing Command
+ *  0b0..Command word for start of new transfer
+ *  0b1..Command word for continuing transfer
+ */
 #define LPSPI_TCR_CONTC(x)                       (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONTC_SHIFT)) & LPSPI_TCR_CONTC_MASK)
 #define LPSPI_TCR_CONT_MASK                      (0x200000U)
 #define LPSPI_TCR_CONT_SHIFT                     (21U)
+/*! CONT - Continuous Transfer
+ *  0b0..Continuous transfer is disabled
+ *  0b1..Continuous transfer is enabled
+ */
 #define LPSPI_TCR_CONT(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONT_SHIFT)) & LPSPI_TCR_CONT_MASK)
 #define LPSPI_TCR_BYSW_MASK                      (0x400000U)
 #define LPSPI_TCR_BYSW_SHIFT                     (22U)
+/*! BYSW - Byte Swap
+ *  0b0..Byte swap is disabled
+ *  0b1..Byte swap is enabled
+ */
 #define LPSPI_TCR_BYSW(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_BYSW_SHIFT)) & LPSPI_TCR_BYSW_MASK)
 #define LPSPI_TCR_LSBF_MASK                      (0x800000U)
 #define LPSPI_TCR_LSBF_SHIFT                     (23U)
+/*! LSBF - LSB First
+ *  0b0..Data is transferred MSB first
+ *  0b1..Data is transferred LSB first
+ */
 #define LPSPI_TCR_LSBF(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_LSBF_SHIFT)) & LPSPI_TCR_LSBF_MASK)
 #define LPSPI_TCR_PCS_MASK                       (0x3000000U)
 #define LPSPI_TCR_PCS_SHIFT                      (24U)
+/*! PCS - Peripheral Chip Select
+ *  0b00..Transfer using LPSPI_PCS[0]
+ *  0b01..Transfer using LPSPI_PCS[1]
+ *  0b10..Transfer using LPSPI_PCS[2]
+ *  0b11..Transfer using LPSPI_PCS[3]
+ */
 #define LPSPI_TCR_PCS(x)                         (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PCS_SHIFT)) & LPSPI_TCR_PCS_MASK)
 #define LPSPI_TCR_PRESCALE_MASK                  (0x38000000U)
 #define LPSPI_TCR_PRESCALE_SHIFT                 (27U)
+/*! PRESCALE - Prescaler Value
+ *  0b000..Divide by 1
+ *  0b001..Divide by 2
+ *  0b010..Divide by 4
+ *  0b011..Divide by 8
+ *  0b100..Divide by 16
+ *  0b101..Divide by 32
+ *  0b110..Divide by 64
+ *  0b111..Divide by 128
+ */
 #define LPSPI_TCR_PRESCALE(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PRESCALE_SHIFT)) & LPSPI_TCR_PRESCALE_MASK)
 #define LPSPI_TCR_CPHA_MASK                      (0x40000000U)
 #define LPSPI_TCR_CPHA_SHIFT                     (30U)
+/*! CPHA - Clock Phase
+ *  0b0..Data is captured on the leading edge of SCK and changed on the following edge of SCK
+ *  0b1..Data is changed on the leading edge of SCK and captured on the following edge of SCK
+ */
 #define LPSPI_TCR_CPHA(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPHA_SHIFT)) & LPSPI_TCR_CPHA_MASK)
 #define LPSPI_TCR_CPOL_MASK                      (0x80000000U)
 #define LPSPI_TCR_CPOL_SHIFT                     (31U)
+/*! CPOL - Clock Polarity
+ *  0b0..The inactive state value of SCK is low
+ *  0b1..The inactive state value of SCK is high
+ */
 #define LPSPI_TCR_CPOL(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPOL_SHIFT)) & LPSPI_TCR_CPOL_MASK)
 /*! @} */
 
@@ -16213,9 +25730,17 @@ typedef struct {
 /*! @{ */
 #define LPSPI_RSR_SOF_MASK                       (0x1U)
 #define LPSPI_RSR_SOF_SHIFT                      (0U)
+/*! SOF - Start Of Frame
+ *  0b0..Subsequent data word received after LPSPI_PCS assertion
+ *  0b1..First data word received after LPSPI_PCS assertion
+ */
 #define LPSPI_RSR_SOF(x)                         (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_SOF_SHIFT)) & LPSPI_RSR_SOF_MASK)
 #define LPSPI_RSR_RXEMPTY_MASK                   (0x2U)
 #define LPSPI_RSR_RXEMPTY_SHIFT                  (1U)
+/*! RXEMPTY - RX FIFO Empty
+ *  0b0..RX FIFO is not empty
+ *  0b1..RX FIFO is empty
+ */
 #define LPSPI_RSR_RXEMPTY(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_RXEMPTY_SHIFT)) & LPSPI_RSR_RXEMPTY_MASK)
 /*! @} */
 
@@ -16299,6 +25824,10 @@ typedef struct {
 /*! @{ */
 #define LPUART_VERID_FEATURE_MASK                (0xFFFFU)
 #define LPUART_VERID_FEATURE_SHIFT               (0U)
+/*! FEATURE - Feature Identification Number
+ *  0b0000000000000001..Standard feature set.
+ *  0b0000000000000011..Standard feature set with MODEM/IrDA support.
+ */
 #define LPUART_VERID_FEATURE(x)                  (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_FEATURE_SHIFT)) & LPUART_VERID_FEATURE_MASK)
 #define LPUART_VERID_MINOR_MASK                  (0xFF0000U)
 #define LPUART_VERID_MINOR_SHIFT                 (16U)
@@ -16322,6 +25851,10 @@ typedef struct {
 /*! @{ */
 #define LPUART_GLOBAL_RST_MASK                   (0x2U)
 #define LPUART_GLOBAL_RST_SHIFT                  (1U)
+/*! RST - Software Reset
+ *  0b0..Module is not reset.
+ *  0b1..Module is reset.
+ */
 #define LPUART_GLOBAL_RST(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_GLOBAL_RST_SHIFT)) & LPUART_GLOBAL_RST_MASK)
 /*! @} */
 
@@ -16329,6 +25862,12 @@ typedef struct {
 /*! @{ */
 #define LPUART_PINCFG_TRGSEL_MASK                (0x3U)
 #define LPUART_PINCFG_TRGSEL_SHIFT               (0U)
+/*! TRGSEL - Trigger Select
+ *  0b00..Input trigger is disabled.
+ *  0b01..Input trigger is used instead of RXD pin input.
+ *  0b10..Input trigger is used instead of CTS_B pin input.
+ *  0b11..Input trigger is used to modulate the TXD pin output. The TXD pin output (after TXINV configuration) is ANDed with the input trigger.
+ */
 #define LPUART_PINCFG_TRGSEL(x)                  (((uint32_t)(((uint32_t)(x)) << LPUART_PINCFG_TRGSEL_SHIFT)) & LPUART_PINCFG_TRGSEL_MASK)
 /*! @} */
 
@@ -16339,42 +25878,126 @@ typedef struct {
 #define LPUART_BAUD_SBR(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBR_SHIFT)) & LPUART_BAUD_SBR_MASK)
 #define LPUART_BAUD_SBNS_MASK                    (0x2000U)
 #define LPUART_BAUD_SBNS_SHIFT                   (13U)
+/*! SBNS - Stop Bit Number Select
+ *  0b0..One stop bit.
+ *  0b1..Two stop bits.
+ */
 #define LPUART_BAUD_SBNS(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBNS_SHIFT)) & LPUART_BAUD_SBNS_MASK)
 #define LPUART_BAUD_RXEDGIE_MASK                 (0x4000U)
 #define LPUART_BAUD_RXEDGIE_SHIFT                (14U)
+/*! RXEDGIE - RX Input Active Edge Interrupt Enable
+ *  0b0..Hardware interrupts from STAT[RXEDGIF] are disabled.
+ *  0b1..Hardware interrupt is requested when STAT[RXEDGIF] flag is 1.
+ */
 #define LPUART_BAUD_RXEDGIE(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RXEDGIE_SHIFT)) & LPUART_BAUD_RXEDGIE_MASK)
 #define LPUART_BAUD_LBKDIE_MASK                  (0x8000U)
 #define LPUART_BAUD_LBKDIE_SHIFT                 (15U)
+/*! LBKDIE - LIN Break Detect Interrupt Enable
+ *  0b0..Hardware interrupts from STAT[LBKDIF] flag are disabled (use polling).
+ *  0b1..Hardware interrupt requested when STAT[LBKDIF] flag is 1.
+ */
 #define LPUART_BAUD_LBKDIE(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_LBKDIE_SHIFT)) & LPUART_BAUD_LBKDIE_MASK)
 #define LPUART_BAUD_RESYNCDIS_MASK               (0x10000U)
 #define LPUART_BAUD_RESYNCDIS_SHIFT              (16U)
+/*! RESYNCDIS - Resynchronization Disable
+ *  0b0..Resynchronization during received data word is supported
+ *  0b1..Resynchronization during received data word is disabled
+ */
 #define LPUART_BAUD_RESYNCDIS(x)                 (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RESYNCDIS_SHIFT)) & LPUART_BAUD_RESYNCDIS_MASK)
 #define LPUART_BAUD_BOTHEDGE_MASK                (0x20000U)
 #define LPUART_BAUD_BOTHEDGE_SHIFT               (17U)
+/*! BOTHEDGE - Both Edge Sampling
+ *  0b0..Receiver samples input data using the rising edge of the baud rate clock.
+ *  0b1..Receiver samples input data using the rising and falling edge of the baud rate clock.
+ */
 #define LPUART_BAUD_BOTHEDGE(x)                  (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_BOTHEDGE_SHIFT)) & LPUART_BAUD_BOTHEDGE_MASK)
 #define LPUART_BAUD_MATCFG_MASK                  (0xC0000U)
 #define LPUART_BAUD_MATCFG_SHIFT                 (18U)
+/*! MATCFG - Match Configuration
+ *  0b00..Address Match Wakeup
+ *  0b01..Idle Match Wakeup
+ *  0b10..Match On and Match Off
+ *  0b11..Enables RWU on Data Match and Match On/Off for transmitter CTS input
+ */
 #define LPUART_BAUD_MATCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MATCFG_SHIFT)) & LPUART_BAUD_MATCFG_MASK)
 #define LPUART_BAUD_RIDMAE_MASK                  (0x100000U)
 #define LPUART_BAUD_RIDMAE_SHIFT                 (20U)
+/*! RIDMAE - Receiver Idle DMA Enable
+ *  0b0..DMA request disabled.
+ *  0b1..DMA request enabled.
+ */
 #define LPUART_BAUD_RIDMAE(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RIDMAE_SHIFT)) & LPUART_BAUD_RIDMAE_MASK)
 #define LPUART_BAUD_RDMAE_MASK                   (0x200000U)
 #define LPUART_BAUD_RDMAE_SHIFT                  (21U)
+/*! RDMAE - Receiver Full DMA Enable
+ *  0b0..DMA request disabled.
+ *  0b1..DMA request enabled.
+ */
 #define LPUART_BAUD_RDMAE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RDMAE_SHIFT)) & LPUART_BAUD_RDMAE_MASK)
 #define LPUART_BAUD_TDMAE_MASK                   (0x800000U)
 #define LPUART_BAUD_TDMAE_SHIFT                  (23U)
+/*! TDMAE - Transmitter DMA Enable
+ *  0b0..DMA request disabled.
+ *  0b1..DMA request enabled.
+ */
 #define LPUART_BAUD_TDMAE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_TDMAE_SHIFT)) & LPUART_BAUD_TDMAE_MASK)
 #define LPUART_BAUD_OSR_MASK                     (0x1F000000U)
 #define LPUART_BAUD_OSR_SHIFT                    (24U)
+/*! OSR - Oversampling Ratio
+ *  0b00000..Writing 0 to this field will result in an oversampling ratio of 16
+ *  0b00001..Reserved
+ *  0b00010..Reserved
+ *  0b00011..Oversampling ratio of 4, requires BOTHEDGE to be set.
+ *  0b00100..Oversampling ratio of 5, requires BOTHEDGE to be set.
+ *  0b00101..Oversampling ratio of 6, requires BOTHEDGE to be set.
+ *  0b00110..Oversampling ratio of 7, requires BOTHEDGE to be set.
+ *  0b00111..Oversampling ratio of 8.
+ *  0b01000..Oversampling ratio of 9.
+ *  0b01001..Oversampling ratio of 10.
+ *  0b01010..Oversampling ratio of 11.
+ *  0b01011..Oversampling ratio of 12.
+ *  0b01100..Oversampling ratio of 13.
+ *  0b01101..Oversampling ratio of 14.
+ *  0b01110..Oversampling ratio of 15.
+ *  0b01111..Oversampling ratio of 16.
+ *  0b10000..Oversampling ratio of 17.
+ *  0b10001..Oversampling ratio of 18.
+ *  0b10010..Oversampling ratio of 19.
+ *  0b10011..Oversampling ratio of 20.
+ *  0b10100..Oversampling ratio of 21.
+ *  0b10101..Oversampling ratio of 22.
+ *  0b10110..Oversampling ratio of 23.
+ *  0b10111..Oversampling ratio of 24.
+ *  0b11000..Oversampling ratio of 25.
+ *  0b11001..Oversampling ratio of 26.
+ *  0b11010..Oversampling ratio of 27.
+ *  0b11011..Oversampling ratio of 28.
+ *  0b11100..Oversampling ratio of 29.
+ *  0b11101..Oversampling ratio of 30.
+ *  0b11110..Oversampling ratio of 31.
+ *  0b11111..Oversampling ratio of 32.
+ */
 #define LPUART_BAUD_OSR(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_OSR_SHIFT)) & LPUART_BAUD_OSR_MASK)
 #define LPUART_BAUD_M10_MASK                     (0x20000000U)
 #define LPUART_BAUD_M10_SHIFT                    (29U)
+/*! M10 - 10-bit Mode select
+ *  0b0..Receiver and transmitter use 7-bit to 9-bit data characters.
+ *  0b1..Receiver and transmitter use 10-bit data characters.
+ */
 #define LPUART_BAUD_M10(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_M10_SHIFT)) & LPUART_BAUD_M10_MASK)
 #define LPUART_BAUD_MAEN2_MASK                   (0x40000000U)
 #define LPUART_BAUD_MAEN2_SHIFT                  (30U)
+/*! MAEN2 - Match Address Mode Enable 2
+ *  0b0..Normal operation.
+ *  0b1..Enables automatic address matching or data matching mode for MATCH[MA2].
+ */
 #define LPUART_BAUD_MAEN2(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN2_SHIFT)) & LPUART_BAUD_MAEN2_MASK)
 #define LPUART_BAUD_MAEN1_MASK                   (0x80000000U)
 #define LPUART_BAUD_MAEN1_SHIFT                  (31U)
+/*! MAEN1 - Match Address Mode Enable 1
+ *  0b0..Normal operation.
+ *  0b1..Enables automatic address matching or data matching mode for MATCH[MA1].
+ */
 #define LPUART_BAUD_MAEN1(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN1_SHIFT)) & LPUART_BAUD_MAEN1_MASK)
 /*! @} */
 
@@ -16382,57 +26005,134 @@ typedef struct {
 /*! @{ */
 #define LPUART_STAT_MA2F_MASK                    (0x4000U)
 #define LPUART_STAT_MA2F_SHIFT                   (14U)
+/*! MA2F - Match 2 Flag
+ *  0b0..Received data is not equal to MA2
+ *  0b1..Received data is equal to MA2
+ */
 #define LPUART_STAT_MA2F(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA2F_SHIFT)) & LPUART_STAT_MA2F_MASK)
 #define LPUART_STAT_MA1F_MASK                    (0x8000U)
 #define LPUART_STAT_MA1F_SHIFT                   (15U)
+/*! MA1F - Match 1 Flag
+ *  0b0..Received data is not equal to MA1
+ *  0b1..Received data is equal to MA1
+ */
 #define LPUART_STAT_MA1F(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA1F_SHIFT)) & LPUART_STAT_MA1F_MASK)
 #define LPUART_STAT_PF_MASK                      (0x10000U)
 #define LPUART_STAT_PF_SHIFT                     (16U)
+/*! PF - Parity Error Flag
+ *  0b0..No parity error.
+ *  0b1..Parity error.
+ */
 #define LPUART_STAT_PF(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_PF_SHIFT)) & LPUART_STAT_PF_MASK)
 #define LPUART_STAT_FE_MASK                      (0x20000U)
 #define LPUART_STAT_FE_SHIFT                     (17U)
+/*! FE - Framing Error Flag
+ *  0b0..No framing error detected. This does not guarantee the framing is correct.
+ *  0b1..Framing error.
+ */
 #define LPUART_STAT_FE(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_FE_SHIFT)) & LPUART_STAT_FE_MASK)
 #define LPUART_STAT_NF_MASK                      (0x40000U)
 #define LPUART_STAT_NF_SHIFT                     (18U)
+/*! NF - Noise Flag
+ *  0b0..No noise detected.
+ *  0b1..Noise detected in the received character in the DATA register.
+ */
 #define LPUART_STAT_NF(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_NF_SHIFT)) & LPUART_STAT_NF_MASK)
 #define LPUART_STAT_OR_MASK                      (0x80000U)
 #define LPUART_STAT_OR_SHIFT                     (19U)
+/*! OR - Receiver Overrun Flag
+ *  0b0..No overrun.
+ *  0b1..Receive overrun (new LPUART data lost).
+ */
 #define LPUART_STAT_OR(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_OR_SHIFT)) & LPUART_STAT_OR_MASK)
 #define LPUART_STAT_IDLE_MASK                    (0x100000U)
 #define LPUART_STAT_IDLE_SHIFT                   (20U)
+/*! IDLE - Idle Line Flag
+ *  0b0..No idle line detected.
+ *  0b1..Idle line was detected.
+ */
 #define LPUART_STAT_IDLE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_IDLE_SHIFT)) & LPUART_STAT_IDLE_MASK)
 #define LPUART_STAT_RDRF_MASK                    (0x200000U)
 #define LPUART_STAT_RDRF_SHIFT                   (21U)
+/*! RDRF - Receive Data Register Full Flag
+ *  0b0..Receive data buffer empty.
+ *  0b1..Receive data buffer full.
+ */
 #define LPUART_STAT_RDRF(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RDRF_SHIFT)) & LPUART_STAT_RDRF_MASK)
 #define LPUART_STAT_TC_MASK                      (0x400000U)
 #define LPUART_STAT_TC_SHIFT                     (22U)
+/*! TC - Transmission Complete Flag
+ *  0b0..Transmitter active (sending data, a preamble, or a break).
+ *  0b1..Transmitter idle (transmission activity complete).
+ */
 #define LPUART_STAT_TC(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TC_SHIFT)) & LPUART_STAT_TC_MASK)
 #define LPUART_STAT_TDRE_MASK                    (0x800000U)
 #define LPUART_STAT_TDRE_SHIFT                   (23U)
+/*! TDRE - Transmit Data Register Empty Flag
+ *  0b0..Transmit data buffer full.
+ *  0b1..Transmit data buffer empty.
+ */
 #define LPUART_STAT_TDRE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TDRE_SHIFT)) & LPUART_STAT_TDRE_MASK)
 #define LPUART_STAT_RAF_MASK                     (0x1000000U)
 #define LPUART_STAT_RAF_SHIFT                    (24U)
+/*! RAF - Receiver Active Flag
+ *  0b0..LPUART receiver idle waiting for a start bit.
+ *  0b1..LPUART receiver active (RXD input not idle).
+ */
 #define LPUART_STAT_RAF(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RAF_SHIFT)) & LPUART_STAT_RAF_MASK)
 #define LPUART_STAT_LBKDE_MASK                   (0x2000000U)
 #define LPUART_STAT_LBKDE_SHIFT                  (25U)
+/*! LBKDE - LIN Break Detection Enable
+ *  0b0..LIN break detect is disabled, normal break character can be detected.
+ *  0b1..LIN break detect is enabled. LIN break character is detected at length of 11 bit times (if M = 0) or 12 (if M = 1) or 13 (M10 = 1).
+ */
 #define LPUART_STAT_LBKDE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDE_SHIFT)) & LPUART_STAT_LBKDE_MASK)
 #define LPUART_STAT_BRK13_MASK                   (0x4000000U)
 #define LPUART_STAT_BRK13_SHIFT                  (26U)
+/*! BRK13 - Break Character Generation Length
+ *  0b0..Break character is transmitted with length of 9 to 13 bit times.
+ *  0b1..Break character is transmitted with length of 12 to 15 bit times.
+ */
 #define LPUART_STAT_BRK13(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_BRK13_SHIFT)) & LPUART_STAT_BRK13_MASK)
 #define LPUART_STAT_RWUID_MASK                   (0x8000000U)
 #define LPUART_STAT_RWUID_SHIFT                  (27U)
+/*! RWUID - Receive Wake Up Idle Detect
+ *  0b0..During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle
+ *       character. During address match wakeup, the IDLE bit does not set when an address does not match.
+ *  0b1..During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character. During
+ *       address match wakeup, the IDLE bit does set when an address does not match.
+ */
 #define LPUART_STAT_RWUID(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RWUID_SHIFT)) & LPUART_STAT_RWUID_MASK)
 #define LPUART_STAT_RXINV_MASK                   (0x10000000U)
 #define LPUART_STAT_RXINV_SHIFT                  (28U)
+/*! RXINV - Receive Data Inversion
+ *  0b0..Receive data not inverted.
+ *  0b1..Receive data inverted.
+ */
 #define LPUART_STAT_RXINV(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXINV_SHIFT)) & LPUART_STAT_RXINV_MASK)
 #define LPUART_STAT_MSBF_MASK                    (0x20000000U)
 #define LPUART_STAT_MSBF_SHIFT                   (29U)
+/*! MSBF - MSB First
+ *  0b0..LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received
+ *       after the start bit is identified as bit0.
+ *  0b1..MSB (bit9, bit8, bit7 or bit6) is the first bit that is transmitted following the start bit depending on
+ *       the setting of CTRL[M], CTRL[PE] and BAUD[M10]. Further, the first bit received after the start bit is
+ *       identified as bit9, bit8, bit7 or bit6 depending on the setting of CTRL[M] and CTRL[PE].
+ */
 #define LPUART_STAT_MSBF(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MSBF_SHIFT)) & LPUART_STAT_MSBF_MASK)
 #define LPUART_STAT_RXEDGIF_MASK                 (0x40000000U)
 #define LPUART_STAT_RXEDGIF_SHIFT                (30U)
+/*! RXEDGIF - RXD Pin Active Edge Interrupt Flag
+ *  0b0..No active edge on the receive pin has occurred.
+ *  0b1..An active edge on the receive pin has occurred.
+ */
 #define LPUART_STAT_RXEDGIF(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXEDGIF_SHIFT)) & LPUART_STAT_RXEDGIF_MASK)
 #define LPUART_STAT_LBKDIF_MASK                  (0x80000000U)
 #define LPUART_STAT_LBKDIF_SHIFT                 (31U)
+/*! LBKDIF - LIN Break Detect Interrupt Flag
+ *  0b0..No LIN break character has been detected.
+ *  0b1..LIN break character has been detected.
+ */
 #define LPUART_STAT_LBKDIF(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDIF_SHIFT)) & LPUART_STAT_LBKDIF_MASK)
 /*! @} */
 
@@ -16440,81 +26140,191 @@ typedef struct {
 /*! @{ */
 #define LPUART_CTRL_PT_MASK                      (0x1U)
 #define LPUART_CTRL_PT_SHIFT                     (0U)
+/*! PT - Parity Type
+ *  0b0..Even parity.
+ *  0b1..Odd parity.
+ */
 #define LPUART_CTRL_PT(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PT_SHIFT)) & LPUART_CTRL_PT_MASK)
 #define LPUART_CTRL_PE_MASK                      (0x2U)
 #define LPUART_CTRL_PE_SHIFT                     (1U)
+/*! PE - Parity Enable
+ *  0b0..No hardware parity generation or checking.
+ *  0b1..Parity enabled.
+ */
 #define LPUART_CTRL_PE(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PE_SHIFT)) & LPUART_CTRL_PE_MASK)
 #define LPUART_CTRL_ILT_MASK                     (0x4U)
 #define LPUART_CTRL_ILT_SHIFT                    (2U)
+/*! ILT - Idle Line Type Select
+ *  0b0..Idle character bit count starts after start bit.
+ *  0b1..Idle character bit count starts after stop bit.
+ */
 #define LPUART_CTRL_ILT(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILT_SHIFT)) & LPUART_CTRL_ILT_MASK)
 #define LPUART_CTRL_WAKE_MASK                    (0x8U)
 #define LPUART_CTRL_WAKE_SHIFT                   (3U)
+/*! WAKE - Receiver Wakeup Method Select
+ *  0b0..Configures RWU for idle-line wakeup.
+ *  0b1..Configures RWU with address-mark wakeup.
+ */
 #define LPUART_CTRL_WAKE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_WAKE_SHIFT)) & LPUART_CTRL_WAKE_MASK)
 #define LPUART_CTRL_M_MASK                       (0x10U)
 #define LPUART_CTRL_M_SHIFT                      (4U)
+/*! M - 9-Bit or 8-Bit Mode Select
+ *  0b0..Receiver and transmitter use 8-bit data characters.
+ *  0b1..Receiver and transmitter use 9-bit data characters.
+ */
 #define LPUART_CTRL_M(x)                         (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M_SHIFT)) & LPUART_CTRL_M_MASK)
 #define LPUART_CTRL_RSRC_MASK                    (0x20U)
 #define LPUART_CTRL_RSRC_SHIFT                   (5U)
+/*! RSRC - Receiver Source Select
+ *  0b0..Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the LPUART does not use the RXD pin.
+ *  0b1..Single-wire LPUART mode where the TXD pin is connected to the transmitter output and receiver input.
+ */
 #define LPUART_CTRL_RSRC(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RSRC_SHIFT)) & LPUART_CTRL_RSRC_MASK)
 #define LPUART_CTRL_DOZEEN_MASK                  (0x40U)
 #define LPUART_CTRL_DOZEEN_SHIFT                 (6U)
+/*! DOZEEN - Doze Enable
+ *  0b0..LPUART is enabled in Doze mode.
+ *  0b1..LPUART is disabled in Doze mode.
+ */
 #define LPUART_CTRL_DOZEEN(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_DOZEEN_SHIFT)) & LPUART_CTRL_DOZEEN_MASK)
 #define LPUART_CTRL_LOOPS_MASK                   (0x80U)
 #define LPUART_CTRL_LOOPS_SHIFT                  (7U)
+/*! LOOPS - Loop Mode Select
+ *  0b0..Normal operation - RXD and TXD use separate pins.
+ *  0b1..Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input (see RSRC bit).
+ */
 #define LPUART_CTRL_LOOPS(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_LOOPS_SHIFT)) & LPUART_CTRL_LOOPS_MASK)
 #define LPUART_CTRL_IDLECFG_MASK                 (0x700U)
 #define LPUART_CTRL_IDLECFG_SHIFT                (8U)
+/*! IDLECFG - Idle Configuration
+ *  0b000..1 idle character
+ *  0b001..2 idle characters
+ *  0b010..4 idle characters
+ *  0b011..8 idle characters
+ *  0b100..16 idle characters
+ *  0b101..32 idle characters
+ *  0b110..64 idle characters
+ *  0b111..128 idle characters
+ */
 #define LPUART_CTRL_IDLECFG(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_IDLECFG_SHIFT)) & LPUART_CTRL_IDLECFG_MASK)
 #define LPUART_CTRL_M7_MASK                      (0x800U)
 #define LPUART_CTRL_M7_SHIFT                     (11U)
+/*! M7 - 7-Bit Mode Select
+ *  0b0..Receiver and transmitter use 8-bit to 10-bit data characters.
+ *  0b1..Receiver and transmitter use 7-bit data characters.
+ */
 #define LPUART_CTRL_M7(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M7_SHIFT)) & LPUART_CTRL_M7_MASK)
 #define LPUART_CTRL_MA2IE_MASK                   (0x4000U)
 #define LPUART_CTRL_MA2IE_SHIFT                  (14U)
+/*! MA2IE - Match 2 Interrupt Enable
+ *  0b0..MA2F interrupt disabled
+ *  0b1..MA2F interrupt enabled
+ */
 #define LPUART_CTRL_MA2IE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA2IE_SHIFT)) & LPUART_CTRL_MA2IE_MASK)
 #define LPUART_CTRL_MA1IE_MASK                   (0x8000U)
 #define LPUART_CTRL_MA1IE_SHIFT                  (15U)
+/*! MA1IE - Match 1 Interrupt Enable
+ *  0b0..MA1F interrupt disabled
+ *  0b1..MA1F interrupt enabled
+ */
 #define LPUART_CTRL_MA1IE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA1IE_SHIFT)) & LPUART_CTRL_MA1IE_MASK)
 #define LPUART_CTRL_SBK_MASK                     (0x10000U)
 #define LPUART_CTRL_SBK_SHIFT                    (16U)
+/*! SBK - Send Break
+ *  0b0..Normal transmitter operation.
+ *  0b1..Queue break character(s) to be sent.
+ */
 #define LPUART_CTRL_SBK(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_SBK_SHIFT)) & LPUART_CTRL_SBK_MASK)
 #define LPUART_CTRL_RWU_MASK                     (0x20000U)
 #define LPUART_CTRL_RWU_SHIFT                    (17U)
+/*! RWU - Receiver Wakeup Control
+ *  0b0..Normal receiver operation.
+ *  0b1..LPUART receiver in standby waiting for wakeup condition.
+ */
 #define LPUART_CTRL_RWU(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RWU_SHIFT)) & LPUART_CTRL_RWU_MASK)
 #define LPUART_CTRL_RE_MASK                      (0x40000U)
 #define LPUART_CTRL_RE_SHIFT                     (18U)
+/*! RE - Receiver Enable
+ *  0b0..Receiver disabled.
+ *  0b1..Receiver enabled.
+ */
 #define LPUART_CTRL_RE(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RE_SHIFT)) & LPUART_CTRL_RE_MASK)
 #define LPUART_CTRL_TE_MASK                      (0x80000U)
 #define LPUART_CTRL_TE_SHIFT                     (19U)
+/*! TE - Transmitter Enable
+ *  0b0..Transmitter disabled.
+ *  0b1..Transmitter enabled.
+ */
 #define LPUART_CTRL_TE(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TE_SHIFT)) & LPUART_CTRL_TE_MASK)
 #define LPUART_CTRL_ILIE_MASK                    (0x100000U)
 #define LPUART_CTRL_ILIE_SHIFT                   (20U)
+/*! ILIE - Idle Line Interrupt Enable
+ *  0b0..Hardware interrupts from IDLE disabled; use polling.
+ *  0b1..Hardware interrupt requested when IDLE flag is 1.
+ */
 #define LPUART_CTRL_ILIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILIE_SHIFT)) & LPUART_CTRL_ILIE_MASK)
 #define LPUART_CTRL_RIE_MASK                     (0x200000U)
 #define LPUART_CTRL_RIE_SHIFT                    (21U)
+/*! RIE - Receiver Interrupt Enable
+ *  0b0..Hardware interrupts from RDRF disabled; use polling.
+ *  0b1..Hardware interrupt requested when RDRF flag is 1.
+ */
 #define LPUART_CTRL_RIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RIE_SHIFT)) & LPUART_CTRL_RIE_MASK)
 #define LPUART_CTRL_TCIE_MASK                    (0x400000U)
 #define LPUART_CTRL_TCIE_SHIFT                   (22U)
+/*! TCIE - Transmission Complete Interrupt Enable for
+ *  0b0..Hardware interrupts from TC disabled; use polling.
+ *  0b1..Hardware interrupt requested when TC flag is 1.
+ */
 #define LPUART_CTRL_TCIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TCIE_SHIFT)) & LPUART_CTRL_TCIE_MASK)
 #define LPUART_CTRL_TIE_MASK                     (0x800000U)
 #define LPUART_CTRL_TIE_SHIFT                    (23U)
+/*! TIE - Transmit Interrupt Enable
+ *  0b0..Hardware interrupts from TDRE disabled; use polling.
+ *  0b1..Hardware interrupt requested when TDRE flag is 1.
+ */
 #define LPUART_CTRL_TIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TIE_SHIFT)) & LPUART_CTRL_TIE_MASK)
 #define LPUART_CTRL_PEIE_MASK                    (0x1000000U)
 #define LPUART_CTRL_PEIE_SHIFT                   (24U)
+/*! PEIE - Parity Error Interrupt Enable
+ *  0b0..PF interrupts disabled; use polling).
+ *  0b1..Hardware interrupt requested when PF is set.
+ */
 #define LPUART_CTRL_PEIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PEIE_SHIFT)) & LPUART_CTRL_PEIE_MASK)
 #define LPUART_CTRL_FEIE_MASK                    (0x2000000U)
 #define LPUART_CTRL_FEIE_SHIFT                   (25U)
+/*! FEIE - Framing Error Interrupt Enable
+ *  0b0..FE interrupts disabled; use polling.
+ *  0b1..Hardware interrupt requested when FE is set.
+ */
 #define LPUART_CTRL_FEIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_FEIE_SHIFT)) & LPUART_CTRL_FEIE_MASK)
 #define LPUART_CTRL_NEIE_MASK                    (0x4000000U)
 #define LPUART_CTRL_NEIE_SHIFT                   (26U)
+/*! NEIE - Noise Error Interrupt Enable
+ *  0b0..NF interrupts disabled; use polling.
+ *  0b1..Hardware interrupt requested when NF is set.
+ */
 #define LPUART_CTRL_NEIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_NEIE_SHIFT)) & LPUART_CTRL_NEIE_MASK)
 #define LPUART_CTRL_ORIE_MASK                    (0x8000000U)
 #define LPUART_CTRL_ORIE_SHIFT                   (27U)
+/*! ORIE - Overrun Interrupt Enable
+ *  0b0..OR interrupts disabled; use polling.
+ *  0b1..Hardware interrupt requested when OR is set.
+ */
 #define LPUART_CTRL_ORIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ORIE_SHIFT)) & LPUART_CTRL_ORIE_MASK)
 #define LPUART_CTRL_TXINV_MASK                   (0x10000000U)
 #define LPUART_CTRL_TXINV_SHIFT                  (28U)
+/*! TXINV - Transmit Data Inversion
+ *  0b0..Transmit data not inverted.
+ *  0b1..Transmit data inverted.
+ */
 #define LPUART_CTRL_TXINV(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXINV_SHIFT)) & LPUART_CTRL_TXINV_MASK)
 #define LPUART_CTRL_TXDIR_MASK                   (0x20000000U)
 #define LPUART_CTRL_TXDIR_SHIFT                  (29U)
+/*! TXDIR - TXD Pin Direction in Single-Wire Mode
+ *  0b0..TXD pin is an input in single-wire mode.
+ *  0b1..TXD pin is an output in single-wire mode.
+ */
 #define LPUART_CTRL_TXDIR(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXDIR_SHIFT)) & LPUART_CTRL_TXDIR_MASK)
 #define LPUART_CTRL_R9T8_MASK                    (0x40000000U)
 #define LPUART_CTRL_R9T8_SHIFT                   (30U)
@@ -16558,18 +26368,38 @@ typedef struct {
 #define LPUART_DATA_R9T9(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R9T9_SHIFT)) & LPUART_DATA_R9T9_MASK)
 #define LPUART_DATA_IDLINE_MASK                  (0x800U)
 #define LPUART_DATA_IDLINE_SHIFT                 (11U)
+/*! IDLINE - Idle Line
+ *  0b0..Receiver was not idle before receiving this character.
+ *  0b1..Receiver was idle before receiving this character.
+ */
 #define LPUART_DATA_IDLINE(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_IDLINE_SHIFT)) & LPUART_DATA_IDLINE_MASK)
 #define LPUART_DATA_RXEMPT_MASK                  (0x1000U)
 #define LPUART_DATA_RXEMPT_SHIFT                 (12U)
+/*! RXEMPT - Receive Buffer Empty
+ *  0b0..Receive buffer contains valid data.
+ *  0b1..Receive buffer is empty, data returned on read is not valid.
+ */
 #define LPUART_DATA_RXEMPT(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_RXEMPT_SHIFT)) & LPUART_DATA_RXEMPT_MASK)
 #define LPUART_DATA_FRETSC_MASK                  (0x2000U)
 #define LPUART_DATA_FRETSC_SHIFT                 (13U)
+/*! FRETSC - Frame Error / Transmit Special Character
+ *  0b0..The dataword was received without a frame error on read, or transmit a normal character on write.
+ *  0b1..The dataword was received with a frame error, or transmit an idle or break character on transmit.
+ */
 #define LPUART_DATA_FRETSC(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_FRETSC_SHIFT)) & LPUART_DATA_FRETSC_MASK)
 #define LPUART_DATA_PARITYE_MASK                 (0x4000U)
 #define LPUART_DATA_PARITYE_SHIFT                (14U)
+/*! PARITYE - PARITYE
+ *  0b0..The dataword was received without a parity error.
+ *  0b1..The dataword was received with a parity error.
+ */
 #define LPUART_DATA_PARITYE(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_PARITYE_SHIFT)) & LPUART_DATA_PARITYE_MASK)
 #define LPUART_DATA_NOISY_MASK                   (0x8000U)
 #define LPUART_DATA_NOISY_SHIFT                  (15U)
+/*! NOISY - NOISY
+ *  0b0..The dataword was received without noise.
+ *  0b1..The data was received with noise.
+ */
 #define LPUART_DATA_NOISY(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_NOISY_SHIFT)) & LPUART_DATA_NOISY_MASK)
 /*! @} */
 
@@ -16587,30 +26417,71 @@ typedef struct {
 /*! @{ */
 #define LPUART_MODIR_TXCTSE_MASK                 (0x1U)
 #define LPUART_MODIR_TXCTSE_SHIFT                (0U)
+/*! TXCTSE - Transmitter clear-to-send enable
+ *  0b0..CTS has no effect on the transmitter.
+ *  0b1..Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a
+ *       character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the
+ *       mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent
+ *       do not affect its transmission.
+ */
 #define LPUART_MODIR_TXCTSE(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSE_SHIFT)) & LPUART_MODIR_TXCTSE_MASK)
 #define LPUART_MODIR_TXRTSE_MASK                 (0x2U)
 #define LPUART_MODIR_TXRTSE_SHIFT                (1U)
+/*! TXRTSE - Transmitter request-to-send enable
+ *  0b0..The transmitter has no effect on RTS.
+ *  0b1..When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the
+ *       start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and
+ *       shift register are completely sent, including the last stop bit.
+ */
 #define LPUART_MODIR_TXRTSE(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSE_SHIFT)) & LPUART_MODIR_TXRTSE_MASK)
 #define LPUART_MODIR_TXRTSPOL_MASK               (0x4U)
 #define LPUART_MODIR_TXRTSPOL_SHIFT              (2U)
+/*! TXRTSPOL - Transmitter request-to-send polarity
+ *  0b0..Transmitter RTS is active low.
+ *  0b1..Transmitter RTS is active high.
+ */
 #define LPUART_MODIR_TXRTSPOL(x)                 (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSPOL_SHIFT)) & LPUART_MODIR_TXRTSPOL_MASK)
 #define LPUART_MODIR_RXRTSE_MASK                 (0x8U)
 #define LPUART_MODIR_RXRTSE_SHIFT                (3U)
+/*! RXRTSE - Receiver request-to-send enable
+ *  0b0..The receiver has no effect on RTS.
+ *  0b1..RTS is deasserted if the receiver data register is full or a start bit has been detected that would cause
+ *       the receiver data register to become full. RTS is asserted if the receiver data register is not full and
+ *       has not detected a start bit that would cause the receiver data register to become full.
+ */
 #define LPUART_MODIR_RXRTSE(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RXRTSE_SHIFT)) & LPUART_MODIR_RXRTSE_MASK)
 #define LPUART_MODIR_TXCTSC_MASK                 (0x10U)
 #define LPUART_MODIR_TXCTSC_SHIFT                (4U)
+/*! TXCTSC - Transmit CTS Configuration
+ *  0b0..CTS input is sampled at the start of each character.
+ *  0b1..CTS input is sampled when the transmitter is idle.
+ */
 #define LPUART_MODIR_TXCTSC(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSC_SHIFT)) & LPUART_MODIR_TXCTSC_MASK)
 #define LPUART_MODIR_TXCTSSRC_MASK               (0x20U)
 #define LPUART_MODIR_TXCTSSRC_SHIFT              (5U)
+/*! TXCTSSRC - Transmit CTS Source
+ *  0b0..CTS input is the CTS_B pin.
+ *  0b1..CTS input is the inverted Receiver Match result.
+ */
 #define LPUART_MODIR_TXCTSSRC(x)                 (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSSRC_SHIFT)) & LPUART_MODIR_TXCTSSRC_MASK)
 #define LPUART_MODIR_RTSWATER_MASK               (0x300U)
 #define LPUART_MODIR_RTSWATER_SHIFT              (8U)
 #define LPUART_MODIR_RTSWATER(x)                 (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RTSWATER_SHIFT)) & LPUART_MODIR_RTSWATER_MASK)
 #define LPUART_MODIR_TNP_MASK                    (0x30000U)
 #define LPUART_MODIR_TNP_SHIFT                   (16U)
+/*! TNP - Transmitter narrow pulse
+ *  0b00..1/OSR.
+ *  0b01..2/OSR.
+ *  0b10..3/OSR.
+ *  0b11..4/OSR.
+ */
 #define LPUART_MODIR_TNP(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TNP_SHIFT)) & LPUART_MODIR_TNP_MASK)
 #define LPUART_MODIR_IREN_MASK                   (0x40000U)
 #define LPUART_MODIR_IREN_SHIFT                  (18U)
+/*! IREN - Infrared enable
+ *  0b0..IR disabled.
+ *  0b1..IR enabled.
+ */
 #define LPUART_MODIR_IREN(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_IREN_SHIFT)) & LPUART_MODIR_IREN_MASK)
 /*! @} */
 
@@ -16618,42 +26489,112 @@ typedef struct {
 /*! @{ */
 #define LPUART_FIFO_RXFIFOSIZE_MASK              (0x7U)
 #define LPUART_FIFO_RXFIFOSIZE_SHIFT             (0U)
+/*! RXFIFOSIZE - Receive FIFO Buffer Depth
+ *  0b000..Receive FIFO/Buffer depth = 1 dataword.
+ *  0b001..Receive FIFO/Buffer depth = 4 datawords.
+ *  0b010..Receive FIFO/Buffer depth = 8 datawords.
+ *  0b011..Receive FIFO/Buffer depth = 16 datawords.
+ *  0b100..Receive FIFO/Buffer depth = 32 datawords.
+ *  0b101..Receive FIFO/Buffer depth = 64 datawords.
+ *  0b110..Receive FIFO/Buffer depth = 128 datawords.
+ *  0b111..Receive FIFO/Buffer depth = 256 datawords.
+ */
 #define LPUART_FIFO_RXFIFOSIZE(x)                (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFIFOSIZE_SHIFT)) & LPUART_FIFO_RXFIFOSIZE_MASK)
 #define LPUART_FIFO_RXFE_MASK                    (0x8U)
 #define LPUART_FIFO_RXFE_SHIFT                   (3U)
+/*! RXFE - Receive FIFO Enable
+ *  0b0..Receive FIFO is not enabled. Buffer is depth 1.
+ *  0b1..Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE.
+ */
 #define LPUART_FIFO_RXFE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFE_SHIFT)) & LPUART_FIFO_RXFE_MASK)
 #define LPUART_FIFO_TXFIFOSIZE_MASK              (0x70U)
 #define LPUART_FIFO_TXFIFOSIZE_SHIFT             (4U)
+/*! TXFIFOSIZE - Transmit FIFO Buffer Depth
+ *  0b000..Transmit FIFO/Buffer depth = 1 dataword.
+ *  0b001..Transmit FIFO/Buffer depth = 4 datawords.
+ *  0b010..Transmit FIFO/Buffer depth = 8 datawords.
+ *  0b011..Transmit FIFO/Buffer depth = 16 datawords.
+ *  0b100..Transmit FIFO/Buffer depth = 32 datawords.
+ *  0b101..Transmit FIFO/Buffer depth = 64 datawords.
+ *  0b110..Transmit FIFO/Buffer depth = 128 datawords.
+ *  0b111..Transmit FIFO/Buffer depth = 256 datawords
+ */
 #define LPUART_FIFO_TXFIFOSIZE(x)                (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFIFOSIZE_SHIFT)) & LPUART_FIFO_TXFIFOSIZE_MASK)
 #define LPUART_FIFO_TXFE_MASK                    (0x80U)
 #define LPUART_FIFO_TXFE_SHIFT                   (7U)
+/*! TXFE - Transmit FIFO Enable
+ *  0b0..Transmit FIFO is not enabled. Buffer is depth 1.
+ *  0b1..Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE.
+ */
 #define LPUART_FIFO_TXFE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFE_SHIFT)) & LPUART_FIFO_TXFE_MASK)
 #define LPUART_FIFO_RXUFE_MASK                   (0x100U)
 #define LPUART_FIFO_RXUFE_SHIFT                  (8U)
+/*! RXUFE - Receive FIFO Underflow Interrupt Enable
+ *  0b0..RXUF flag does not generate an interrupt to the host.
+ *  0b1..RXUF flag generates an interrupt to the host.
+ */
 #define LPUART_FIFO_RXUFE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUFE_SHIFT)) & LPUART_FIFO_RXUFE_MASK)
 #define LPUART_FIFO_TXOFE_MASK                   (0x200U)
 #define LPUART_FIFO_TXOFE_SHIFT                  (9U)
+/*! TXOFE - Transmit FIFO Overflow Interrupt Enable
+ *  0b0..TXOF flag does not generate an interrupt to the host.
+ *  0b1..TXOF flag generates an interrupt to the host.
+ */
 #define LPUART_FIFO_TXOFE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOFE_SHIFT)) & LPUART_FIFO_TXOFE_MASK)
 #define LPUART_FIFO_RXIDEN_MASK                  (0x1C00U)
 #define LPUART_FIFO_RXIDEN_SHIFT                 (10U)
+/*! RXIDEN - Receiver Idle Empty Enable
+ *  0b000..Disable RDRF assertion due to partially filled FIFO when receiver is idle.
+ *  0b001..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 1 character.
+ *  0b010..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 2 characters.
+ *  0b011..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 4 characters.
+ *  0b100..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 8 characters.
+ *  0b101..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 16 characters.
+ *  0b110..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 32 characters.
+ *  0b111..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 64 characters.
+ */
 #define LPUART_FIFO_RXIDEN(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXIDEN_SHIFT)) & LPUART_FIFO_RXIDEN_MASK)
 #define LPUART_FIFO_RXFLUSH_MASK                 (0x4000U)
 #define LPUART_FIFO_RXFLUSH_SHIFT                (14U)
+/*! RXFLUSH - Receive FIFO/Buffer Flush
+ *  0b0..No flush operation occurs.
+ *  0b1..All data in the receive FIFO/buffer is cleared out.
+ */
 #define LPUART_FIFO_RXFLUSH(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFLUSH_SHIFT)) & LPUART_FIFO_RXFLUSH_MASK)
 #define LPUART_FIFO_TXFLUSH_MASK                 (0x8000U)
 #define LPUART_FIFO_TXFLUSH_SHIFT                (15U)
+/*! TXFLUSH - Transmit FIFO/Buffer Flush
+ *  0b0..No flush operation occurs.
+ *  0b1..All data in the transmit FIFO/Buffer is cleared out.
+ */
 #define LPUART_FIFO_TXFLUSH(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFLUSH_SHIFT)) & LPUART_FIFO_TXFLUSH_MASK)
 #define LPUART_FIFO_RXUF_MASK                    (0x10000U)
 #define LPUART_FIFO_RXUF_SHIFT                   (16U)
+/*! RXUF - Receiver Buffer Underflow Flag
+ *  0b0..No receive buffer underflow has occurred since the last time the flag was cleared.
+ *  0b1..At least one receive buffer underflow has occurred since the last time the flag was cleared.
+ */
 #define LPUART_FIFO_RXUF(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUF_SHIFT)) & LPUART_FIFO_RXUF_MASK)
 #define LPUART_FIFO_TXOF_MASK                    (0x20000U)
 #define LPUART_FIFO_TXOF_SHIFT                   (17U)
+/*! TXOF - Transmitter Buffer Overflow Flag
+ *  0b0..No transmit buffer overflow has occurred since the last time the flag was cleared.
+ *  0b1..At least one transmit buffer overflow has occurred since the last time the flag was cleared.
+ */
 #define LPUART_FIFO_TXOF(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOF_SHIFT)) & LPUART_FIFO_TXOF_MASK)
 #define LPUART_FIFO_RXEMPT_MASK                  (0x400000U)
 #define LPUART_FIFO_RXEMPT_SHIFT                 (22U)
+/*! RXEMPT - Receive Buffer/FIFO Empty
+ *  0b0..Receive buffer is not empty.
+ *  0b1..Receive buffer is empty.
+ */
 #define LPUART_FIFO_RXEMPT(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXEMPT_SHIFT)) & LPUART_FIFO_RXEMPT_MASK)
 #define LPUART_FIFO_TXEMPT_MASK                  (0x800000U)
 #define LPUART_FIFO_TXEMPT_SHIFT                 (23U)
+/*! TXEMPT - Transmit Buffer/FIFO Empty
+ *  0b0..Transmit buffer is not empty.
+ *  0b1..Transmit buffer is empty.
+ */
 #define LPUART_FIFO_TXEMPT(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXEMPT_SHIFT)) & LPUART_FIFO_TXEMPT_MASK)
 /*! @} */
 
@@ -17079,9 +27020,6 @@ typedef struct {
 #define OCOTP_LOCK_GP2_MASK                      (0x3000U)
 #define OCOTP_LOCK_GP2_SHIFT                     (12U)
 #define OCOTP_LOCK_GP2(x)                        (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_GP2_SHIFT)) & OCOTP_LOCK_GP2_MASK)
-#define OCOTP_LOCK_SRK_MASK                      (0x4000U)
-#define OCOTP_LOCK_SRK_SHIFT                     (14U)
-#define OCOTP_LOCK_SRK(x)                        (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_SRK_SHIFT)) & OCOTP_LOCK_SRK_MASK)
 #define OCOTP_LOCK_OTPMK_MSB_MASK                (0x8000U)
 #define OCOTP_LOCK_OTPMK_MSB_SHIFT               (15U)
 #define OCOTP_LOCK_OTPMK_MSB(x)                  (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_OTPMK_MSB_SHIFT)) & OCOTP_LOCK_OTPMK_MSB_MASK)
@@ -17437,6 +27375,10 @@ typedef struct {
 /*! @{ */
 #define PGC_MEGA_CTRL_PCR_MASK                   (0x1U)
 #define PGC_MEGA_CTRL_PCR_SHIFT                  (0U)
+/*! PCR
+ *  0b0..Do not switch off power even if pdn_req is asserted.
+ *  0b1..Switch off power when pdn_req is asserted.
+ */
 #define PGC_MEGA_CTRL_PCR(x)                     (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_CTRL_PCR_SHIFT)) & PGC_MEGA_CTRL_PCR_MASK)
 /*! @} */
 
@@ -17464,6 +27406,10 @@ typedef struct {
 /*! @{ */
 #define PGC_MEGA_SR_PSR_MASK                     (0x1U)
 #define PGC_MEGA_SR_PSR_SHIFT                    (0U)
+/*! PSR
+ *  0b0..The target subsystem was not powered down for the previous power-down request.
+ *  0b1..The target subsystem was powered down for the previous power-down request.
+ */
 #define PGC_MEGA_SR_PSR(x)                       (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_SR_PSR_SHIFT)) & PGC_MEGA_SR_PSR_MASK)
 /*! @} */
 
@@ -17471,6 +27417,10 @@ typedef struct {
 /*! @{ */
 #define PGC_CPU_CTRL_PCR_MASK                    (0x1U)
 #define PGC_CPU_CTRL_PCR_SHIFT                   (0U)
+/*! PCR
+ *  0b0..Do not switch off power even if pdn_req is asserted.
+ *  0b1..Switch off power when pdn_req is asserted.
+ */
 #define PGC_CPU_CTRL_PCR(x)                      (((uint32_t)(((uint32_t)(x)) << PGC_CPU_CTRL_PCR_SHIFT)) & PGC_CPU_CTRL_PCR_MASK)
 /*! @} */
 
@@ -17498,6 +27448,10 @@ typedef struct {
 /*! @{ */
 #define PGC_CPU_SR_PSR_MASK                      (0x1U)
 #define PGC_CPU_SR_PSR_SHIFT                     (0U)
+/*! PSR
+ *  0b0..The target subsystem was not powered down for the previous power-down request.
+ *  0b1..The target subsystem was powered down for the previous power-down request.
+ */
 #define PGC_CPU_SR_PSR(x)                        (((uint32_t)(((uint32_t)(x)) << PGC_CPU_SR_PSR_SHIFT)) & PGC_CPU_SR_PSR_MASK)
 /*! @} */
 
@@ -17559,9 +27513,17 @@ typedef struct {
 /*! @{ */
 #define PIT_MCR_FRZ_MASK                         (0x1U)
 #define PIT_MCR_FRZ_SHIFT                        (0U)
+/*! FRZ - Freeze
+ *  0b0..Timers continue to run in Debug mode.
+ *  0b1..Timers are stopped in Debug mode.
+ */
 #define PIT_MCR_FRZ(x)                           (((uint32_t)(((uint32_t)(x)) << PIT_MCR_FRZ_SHIFT)) & PIT_MCR_FRZ_MASK)
 #define PIT_MCR_MDIS_MASK                        (0x2U)
 #define PIT_MCR_MDIS_SHIFT                       (1U)
+/*! MDIS - Module Disable - (PIT section)
+ *  0b0..Clock for standard PIT timers is enabled.
+ *  0b1..Clock for standard PIT timers is disabled.
+ */
 #define PIT_MCR_MDIS(x)                          (((uint32_t)(((uint32_t)(x)) << PIT_MCR_MDIS_SHIFT)) & PIT_MCR_MDIS_MASK)
 /*! @} */
 
@@ -17603,12 +27565,24 @@ typedef struct {
 /*! @{ */
 #define PIT_TCTRL_TEN_MASK                       (0x1U)
 #define PIT_TCTRL_TEN_SHIFT                      (0U)
+/*! TEN - Timer Enable
+ *  0b0..Timer n is disabled.
+ *  0b1..Timer n is enabled.
+ */
 #define PIT_TCTRL_TEN(x)                         (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK)
 #define PIT_TCTRL_TIE_MASK                       (0x2U)
 #define PIT_TCTRL_TIE_SHIFT                      (1U)
+/*! TIE - Timer Interrupt Enable
+ *  0b0..Interrupt requests from Timer n are disabled.
+ *  0b1..Interrupt will be requested whenever TIF is set.
+ */
 #define PIT_TCTRL_TIE(x)                         (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TIE_SHIFT)) & PIT_TCTRL_TIE_MASK)
 #define PIT_TCTRL_CHN_MASK                       (0x4U)
 #define PIT_TCTRL_CHN_SHIFT                      (2U)
+/*! CHN - Chain Mode
+ *  0b0..Timer is not chained.
+ *  0b1..Timer is chained to previous timer. For example, for Channel 2, if this field is set, Timer 2 is chained to Timer 1.
+ */
 #define PIT_TCTRL_CHN(x)                         (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK)
 /*! @} */
 
@@ -17619,6 +27593,10 @@ typedef struct {
 /*! @{ */
 #define PIT_TFLG_TIF_MASK                        (0x1U)
 #define PIT_TFLG_TIF_SHIFT                       (0U)
+/*! TIF - Timer Interrupt Flag
+ *  0b0..Timeout has not yet occurred.
+ *  0b1..Timeout has occurred.
+ */
 #define PIT_TFLG_TIF(x)                          (((uint32_t)(((uint32_t)(x)) << PIT_TFLG_TIF_SHIFT)) & PIT_TFLG_TIF_MASK)
 /*! @} */
 
@@ -17718,6 +27696,11 @@ typedef struct {
 #define PMU_REG_1P1_BO_OFFSET(x)                 (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_BO_OFFSET_SHIFT)) & PMU_REG_1P1_BO_OFFSET_MASK)
 #define PMU_REG_1P1_OUTPUT_TRG_MASK              (0x1F00U)
 #define PMU_REG_1P1_OUTPUT_TRG_SHIFT             (8U)
+/*! OUTPUT_TRG
+ *  0b00100..0.8V
+ *  0b10000..1.1V
+ *  0b000x1..1.375V
+ */
 #define PMU_REG_1P1_OUTPUT_TRG(x)                (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_OUTPUT_TRG_MASK)
 #define PMU_REG_1P1_BO_VDD1P1_MASK               (0x10000U)
 #define PMU_REG_1P1_BO_VDD1P1_SHIFT              (16U)
@@ -17730,6 +27713,10 @@ typedef struct {
 #define PMU_REG_1P1_ENABLE_WEAK_LINREG(x)        (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_ENABLE_WEAK_LINREG_MASK)
 #define PMU_REG_1P1_SELREF_WEAK_LINREG_MASK      (0x80000U)
 #define PMU_REG_1P1_SELREF_WEAK_LINREG_SHIFT     (19U)
+/*! SELREF_WEAK_LINREG
+ *  0b0..Weak-linreg output tracks low-power-bandgap voltage
+ *  0b1..Weak-linreg output tracks VDD_SOC_IN voltage
+ */
 #define PMU_REG_1P1_SELREF_WEAK_LINREG(x)        (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_SELREF_WEAK_LINREG_MASK)
 /*! @} */
 
@@ -17752,6 +27739,11 @@ typedef struct {
 #define PMU_REG_1P1_SET_BO_OFFSET(x)             (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_BO_OFFSET_SHIFT)) & PMU_REG_1P1_SET_BO_OFFSET_MASK)
 #define PMU_REG_1P1_SET_OUTPUT_TRG_MASK          (0x1F00U)
 #define PMU_REG_1P1_SET_OUTPUT_TRG_SHIFT         (8U)
+/*! OUTPUT_TRG
+ *  0b00100..0.8V
+ *  0b10000..1.1V
+ *  0b000x1..1.375V
+ */
 #define PMU_REG_1P1_SET_OUTPUT_TRG(x)            (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_SET_OUTPUT_TRG_MASK)
 #define PMU_REG_1P1_SET_BO_VDD1P1_MASK           (0x10000U)
 #define PMU_REG_1P1_SET_BO_VDD1P1_SHIFT          (16U)
@@ -17764,6 +27756,10 @@ typedef struct {
 #define PMU_REG_1P1_SET_ENABLE_WEAK_LINREG(x)    (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_SET_ENABLE_WEAK_LINREG_MASK)
 #define PMU_REG_1P1_SET_SELREF_WEAK_LINREG_MASK  (0x80000U)
 #define PMU_REG_1P1_SET_SELREF_WEAK_LINREG_SHIFT (19U)
+/*! SELREF_WEAK_LINREG
+ *  0b0..Weak-linreg output tracks low-power-bandgap voltage
+ *  0b1..Weak-linreg output tracks VDD_SOC_IN voltage
+ */
 #define PMU_REG_1P1_SET_SELREF_WEAK_LINREG(x)    (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_SET_SELREF_WEAK_LINREG_MASK)
 /*! @} */
 
@@ -17786,6 +27782,11 @@ typedef struct {
 #define PMU_REG_1P1_CLR_BO_OFFSET(x)             (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_BO_OFFSET_SHIFT)) & PMU_REG_1P1_CLR_BO_OFFSET_MASK)
 #define PMU_REG_1P1_CLR_OUTPUT_TRG_MASK          (0x1F00U)
 #define PMU_REG_1P1_CLR_OUTPUT_TRG_SHIFT         (8U)
+/*! OUTPUT_TRG
+ *  0b00100..0.8V
+ *  0b10000..1.1V
+ *  0b000x1..1.375V
+ */
 #define PMU_REG_1P1_CLR_OUTPUT_TRG(x)            (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_CLR_OUTPUT_TRG_MASK)
 #define PMU_REG_1P1_CLR_BO_VDD1P1_MASK           (0x10000U)
 #define PMU_REG_1P1_CLR_BO_VDD1P1_SHIFT          (16U)
@@ -17798,6 +27799,10 @@ typedef struct {
 #define PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG(x)    (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG_MASK)
 #define PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_MASK  (0x80000U)
 #define PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_SHIFT (19U)
+/*! SELREF_WEAK_LINREG
+ *  0b0..Weak-linreg output tracks low-power-bandgap voltage
+ *  0b1..Weak-linreg output tracks VDD_SOC_IN voltage
+ */
 #define PMU_REG_1P1_CLR_SELREF_WEAK_LINREG(x)    (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_MASK)
 /*! @} */
 
@@ -17820,6 +27825,11 @@ typedef struct {
 #define PMU_REG_1P1_TOG_BO_OFFSET(x)             (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_BO_OFFSET_SHIFT)) & PMU_REG_1P1_TOG_BO_OFFSET_MASK)
 #define PMU_REG_1P1_TOG_OUTPUT_TRG_MASK          (0x1F00U)
 #define PMU_REG_1P1_TOG_OUTPUT_TRG_SHIFT         (8U)
+/*! OUTPUT_TRG
+ *  0b00100..0.8V
+ *  0b10000..1.1V
+ *  0b000x1..1.375V
+ */
 #define PMU_REG_1P1_TOG_OUTPUT_TRG(x)            (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_TOG_OUTPUT_TRG_MASK)
 #define PMU_REG_1P1_TOG_BO_VDD1P1_MASK           (0x10000U)
 #define PMU_REG_1P1_TOG_BO_VDD1P1_SHIFT          (16U)
@@ -17832,6 +27842,10 @@ typedef struct {
 #define PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG(x)    (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG_MASK)
 #define PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_MASK  (0x80000U)
 #define PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_SHIFT (19U)
+/*! SELREF_WEAK_LINREG
+ *  0b0..Weak-linreg output tracks low-power-bandgap voltage
+ *  0b1..Weak-linreg output tracks VDD_SOC_IN voltage
+ */
 #define PMU_REG_1P1_TOG_SELREF_WEAK_LINREG(x)    (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_MASK)
 /*! @} */
 
@@ -17851,9 +27865,18 @@ typedef struct {
 #define PMU_REG_3P0_BO_OFFSET(x)                 (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_BO_OFFSET_SHIFT)) & PMU_REG_3P0_BO_OFFSET_MASK)
 #define PMU_REG_3P0_VBUS_SEL_MASK                (0x80U)
 #define PMU_REG_3P0_VBUS_SEL_SHIFT               (7U)
+/*! VBUS_SEL
+ *  0b1..Utilize VBUS OTG1 power
+ *  0b0..Utilize VBUS OTG2 power
+ */
 #define PMU_REG_3P0_VBUS_SEL(x)                  (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_VBUS_SEL_SHIFT)) & PMU_REG_3P0_VBUS_SEL_MASK)
 #define PMU_REG_3P0_OUTPUT_TRG_MASK              (0x1F00U)
 #define PMU_REG_3P0_OUTPUT_TRG_SHIFT             (8U)
+/*! OUTPUT_TRG
+ *  0b00000..2.625V
+ *  0b01111..3.000V
+ *  0b11111..3.400V
+ */
 #define PMU_REG_3P0_OUTPUT_TRG(x)                (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_OUTPUT_TRG_MASK)
 #define PMU_REG_3P0_BO_VDD3P0_MASK               (0x10000U)
 #define PMU_REG_3P0_BO_VDD3P0_SHIFT              (16U)
@@ -17879,9 +27902,18 @@ typedef struct {
 #define PMU_REG_3P0_SET_BO_OFFSET(x)             (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_BO_OFFSET_SHIFT)) & PMU_REG_3P0_SET_BO_OFFSET_MASK)
 #define PMU_REG_3P0_SET_VBUS_SEL_MASK            (0x80U)
 #define PMU_REG_3P0_SET_VBUS_SEL_SHIFT           (7U)
+/*! VBUS_SEL
+ *  0b1..Utilize VBUS OTG1 power
+ *  0b0..Utilize VBUS OTG2 power
+ */
 #define PMU_REG_3P0_SET_VBUS_SEL(x)              (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_VBUS_SEL_SHIFT)) & PMU_REG_3P0_SET_VBUS_SEL_MASK)
 #define PMU_REG_3P0_SET_OUTPUT_TRG_MASK          (0x1F00U)
 #define PMU_REG_3P0_SET_OUTPUT_TRG_SHIFT         (8U)
+/*! OUTPUT_TRG
+ *  0b00000..2.625V
+ *  0b01111..3.000V
+ *  0b11111..3.400V
+ */
 #define PMU_REG_3P0_SET_OUTPUT_TRG(x)            (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_SET_OUTPUT_TRG_MASK)
 #define PMU_REG_3P0_SET_BO_VDD3P0_MASK           (0x10000U)
 #define PMU_REG_3P0_SET_BO_VDD3P0_SHIFT          (16U)
@@ -17907,9 +27939,18 @@ typedef struct {
 #define PMU_REG_3P0_CLR_BO_OFFSET(x)             (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_BO_OFFSET_SHIFT)) & PMU_REG_3P0_CLR_BO_OFFSET_MASK)
 #define PMU_REG_3P0_CLR_VBUS_SEL_MASK            (0x80U)
 #define PMU_REG_3P0_CLR_VBUS_SEL_SHIFT           (7U)
+/*! VBUS_SEL
+ *  0b1..Utilize VBUS OTG1 power
+ *  0b0..Utilize VBUS OTG2 power
+ */
 #define PMU_REG_3P0_CLR_VBUS_SEL(x)              (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_VBUS_SEL_SHIFT)) & PMU_REG_3P0_CLR_VBUS_SEL_MASK)
 #define PMU_REG_3P0_CLR_OUTPUT_TRG_MASK          (0x1F00U)
 #define PMU_REG_3P0_CLR_OUTPUT_TRG_SHIFT         (8U)
+/*! OUTPUT_TRG
+ *  0b00000..2.625V
+ *  0b01111..3.000V
+ *  0b11111..3.400V
+ */
 #define PMU_REG_3P0_CLR_OUTPUT_TRG(x)            (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_CLR_OUTPUT_TRG_MASK)
 #define PMU_REG_3P0_CLR_BO_VDD3P0_MASK           (0x10000U)
 #define PMU_REG_3P0_CLR_BO_VDD3P0_SHIFT          (16U)
@@ -17935,9 +27976,18 @@ typedef struct {
 #define PMU_REG_3P0_TOG_BO_OFFSET(x)             (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_BO_OFFSET_SHIFT)) & PMU_REG_3P0_TOG_BO_OFFSET_MASK)
 #define PMU_REG_3P0_TOG_VBUS_SEL_MASK            (0x80U)
 #define PMU_REG_3P0_TOG_VBUS_SEL_SHIFT           (7U)
+/*! VBUS_SEL
+ *  0b1..Utilize VBUS OTG1 power
+ *  0b0..Utilize VBUS OTG2 power
+ */
 #define PMU_REG_3P0_TOG_VBUS_SEL(x)              (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_VBUS_SEL_SHIFT)) & PMU_REG_3P0_TOG_VBUS_SEL_MASK)
 #define PMU_REG_3P0_TOG_OUTPUT_TRG_MASK          (0x1F00U)
 #define PMU_REG_3P0_TOG_OUTPUT_TRG_SHIFT         (8U)
+/*! OUTPUT_TRG
+ *  0b00000..2.625V
+ *  0b01111..3.000V
+ *  0b11111..3.400V
+ */
 #define PMU_REG_3P0_TOG_OUTPUT_TRG(x)            (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_TOG_OUTPUT_TRG_MASK)
 #define PMU_REG_3P0_TOG_BO_VDD3P0_MASK           (0x10000U)
 #define PMU_REG_3P0_TOG_BO_VDD3P0_SHIFT          (16U)
@@ -17966,6 +28016,11 @@ typedef struct {
 #define PMU_REG_2P5_BO_OFFSET(x)                 (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_BO_OFFSET_SHIFT)) & PMU_REG_2P5_BO_OFFSET_MASK)
 #define PMU_REG_2P5_OUTPUT_TRG_MASK              (0x1F00U)
 #define PMU_REG_2P5_OUTPUT_TRG_SHIFT             (8U)
+/*! OUTPUT_TRG
+ *  0b00000..2.10V
+ *  0b10000..2.50V
+ *  0b11111..2.875V
+ */
 #define PMU_REG_2P5_OUTPUT_TRG(x)                (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_OUTPUT_TRG_MASK)
 #define PMU_REG_2P5_BO_VDD2P5_MASK               (0x10000U)
 #define PMU_REG_2P5_BO_VDD2P5_SHIFT              (16U)
@@ -17997,6 +28052,11 @@ typedef struct {
 #define PMU_REG_2P5_SET_BO_OFFSET(x)             (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_BO_OFFSET_SHIFT)) & PMU_REG_2P5_SET_BO_OFFSET_MASK)
 #define PMU_REG_2P5_SET_OUTPUT_TRG_MASK          (0x1F00U)
 #define PMU_REG_2P5_SET_OUTPUT_TRG_SHIFT         (8U)
+/*! OUTPUT_TRG
+ *  0b00000..2.10V
+ *  0b10000..2.50V
+ *  0b11111..2.875V
+ */
 #define PMU_REG_2P5_SET_OUTPUT_TRG(x)            (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_SET_OUTPUT_TRG_MASK)
 #define PMU_REG_2P5_SET_BO_VDD2P5_MASK           (0x10000U)
 #define PMU_REG_2P5_SET_BO_VDD2P5_SHIFT          (16U)
@@ -18028,6 +28088,11 @@ typedef struct {
 #define PMU_REG_2P5_CLR_BO_OFFSET(x)             (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_BO_OFFSET_SHIFT)) & PMU_REG_2P5_CLR_BO_OFFSET_MASK)
 #define PMU_REG_2P5_CLR_OUTPUT_TRG_MASK          (0x1F00U)
 #define PMU_REG_2P5_CLR_OUTPUT_TRG_SHIFT         (8U)
+/*! OUTPUT_TRG
+ *  0b00000..2.10V
+ *  0b10000..2.50V
+ *  0b11111..2.875V
+ */
 #define PMU_REG_2P5_CLR_OUTPUT_TRG(x)            (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_CLR_OUTPUT_TRG_MASK)
 #define PMU_REG_2P5_CLR_BO_VDD2P5_MASK           (0x10000U)
 #define PMU_REG_2P5_CLR_BO_VDD2P5_SHIFT          (16U)
@@ -18059,6 +28124,11 @@ typedef struct {
 #define PMU_REG_2P5_TOG_BO_OFFSET(x)             (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_BO_OFFSET_SHIFT)) & PMU_REG_2P5_TOG_BO_OFFSET_MASK)
 #define PMU_REG_2P5_TOG_OUTPUT_TRG_MASK          (0x1F00U)
 #define PMU_REG_2P5_TOG_OUTPUT_TRG_SHIFT         (8U)
+/*! OUTPUT_TRG
+ *  0b00000..2.10V
+ *  0b10000..2.50V
+ *  0b11111..2.875V
+ */
 #define PMU_REG_2P5_TOG_OUTPUT_TRG(x)            (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_TOG_OUTPUT_TRG_MASK)
 #define PMU_REG_2P5_TOG_BO_VDD2P5_MASK           (0x10000U)
 #define PMU_REG_2P5_TOG_BO_VDD2P5_SHIFT          (16U)
@@ -18075,24 +28145,119 @@ typedef struct {
 /*! @{ */
 #define PMU_REG_CORE_REG0_TARG_MASK              (0x1FU)
 #define PMU_REG_CORE_REG0_TARG_SHIFT             (0U)
+/*! REG0_TARG
+ *  0b00000..Power gated off
+ *  0b00001..Target core voltage = 0.725V
+ *  0b00010..Target core voltage = 0.750V
+ *  0b00011..Target core voltage = 0.775V
+ *  0b10000..Target core voltage = 1.100V
+ *  0b11110..Target core voltage = 1.450V
+ *  0b11111..Power FET switched full on. No regulation.
+ */
 #define PMU_REG_CORE_REG0_TARG(x)                (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG0_TARG_SHIFT)) & PMU_REG_CORE_REG0_TARG_MASK)
 #define PMU_REG_CORE_REG0_ADJ_MASK               (0x1E0U)
 #define PMU_REG_CORE_REG0_ADJ_SHIFT              (5U)
+/*! REG0_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg0. The
+ *    adjustment is applied on top on any adjustment applied to the global reference in the misc0
+ *    register.
+ *  0b0000..No adjustment
+ *  0b0001..+ 0.25%
+ *  0b0010..+ 0.50%
+ *  0b0011..+ 0.75%
+ *  0b0100..+ 1.00%
+ *  0b0101..+ 1.25%
+ *  0b0110..+ 1.50%
+ *  0b0111..+ 1.75%
+ *  0b1000..- 0.25%
+ *  0b1001..- 0.50%
+ *  0b1010..- 0.75%
+ *  0b1011..- 1.00%
+ *  0b1100..- 1.25%
+ *  0b1101..- 1.50%
+ *  0b1110..- 1.75%
+ *  0b1111..- 2.00%
+ */
 #define PMU_REG_CORE_REG0_ADJ(x)                 (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG0_ADJ_SHIFT)) & PMU_REG_CORE_REG0_ADJ_MASK)
 #define PMU_REG_CORE_REG1_TARG_MASK              (0x3E00U)
 #define PMU_REG_CORE_REG1_TARG_SHIFT             (9U)
+/*! REG1_TARG - This bit field defines the target voltage for the vpu/gpu power domain. Single bit
+ *    increments reflect 25mV core voltage steps. Not all steps will make sense to use either because
+ *    of input supply limitations or load operation.
+ *  0b00000..Power gated off
+ *  0b00001..Target core voltage = 0.725V
+ *  0b00010..Target core voltage = 0.750V
+ *  0b00011..Target core voltage = 0.775V
+ *  0b10000..Target core voltage = 1.100V
+ *  0b11110..Target core voltage = 1.450V
+ *  0b11111..Power FET switched full on. No regulation.
+ */
 #define PMU_REG_CORE_REG1_TARG(x)                (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG1_TARG_SHIFT)) & PMU_REG_CORE_REG1_TARG_MASK)
 #define PMU_REG_CORE_REG1_ADJ_MASK               (0x3C000U)
 #define PMU_REG_CORE_REG1_ADJ_SHIFT              (14U)
+/*! REG1_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg1. The
+ *    adjustment is applied on top on any adjustment applied to the global reference in the misc0
+ *    register.
+ *  0b0000..No adjustment
+ *  0b0001..+ 0.25%
+ *  0b0010..+ 0.50%
+ *  0b0011..+ 0.75%
+ *  0b0100..+ 1.00%
+ *  0b0101..+ 1.25%
+ *  0b0110..+ 1.50%
+ *  0b0111..+ 1.75%
+ *  0b1000..- 0.25%
+ *  0b1001..- 0.50%
+ *  0b1010..- 0.75%
+ *  0b1011..- 1.00%
+ *  0b1100..- 1.25%
+ *  0b1101..- 1.50%
+ *  0b1110..- 1.75%
+ *  0b1111..- 2.00%
+ */
 #define PMU_REG_CORE_REG1_ADJ(x)                 (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG1_ADJ_SHIFT)) & PMU_REG_CORE_REG1_ADJ_MASK)
 #define PMU_REG_CORE_REG2_TARG_MASK              (0x7C0000U)
 #define PMU_REG_CORE_REG2_TARG_SHIFT             (18U)
+/*! REG2_TARG
+ *  0b00000..Power gated off
+ *  0b00001..Target core voltage = 0.725V
+ *  0b00010..Target core voltage = 0.750V
+ *  0b00011..Target core voltage = 0.775V
+ *  0b10000..Target core voltage = 1.100V
+ *  0b11110..Target core voltage = 1.450V
+ *  0b11111..Power FET switched full on. No regulation.
+ */
 #define PMU_REG_CORE_REG2_TARG(x)                (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG2_TARG_SHIFT)) & PMU_REG_CORE_REG2_TARG_MASK)
 #define PMU_REG_CORE_REG2_ADJ_MASK               (0x7800000U)
 #define PMU_REG_CORE_REG2_ADJ_SHIFT              (23U)
+/*! REG2_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg2. The
+ *    adjustment is applied on top on any adjustment applied to the global reference in the misc0
+ *    register.
+ *  0b0000..No adjustment
+ *  0b0001..+ 0.25%
+ *  0b0010..+ 0.50%
+ *  0b0011..+ 0.75%
+ *  0b0100..+ 1.00%
+ *  0b0101..+ 1.25%
+ *  0b0110..+ 1.50%
+ *  0b0111..+ 1.75%
+ *  0b1000..- 0.25%
+ *  0b1001..- 0.50%
+ *  0b1010..- 0.75%
+ *  0b1011..- 1.00%
+ *  0b1100..- 1.25%
+ *  0b1101..- 1.50%
+ *  0b1110..- 1.75%
+ *  0b1111..- 2.00%
+ */
 #define PMU_REG_CORE_REG2_ADJ(x)                 (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG2_ADJ_SHIFT)) & PMU_REG_CORE_REG2_ADJ_MASK)
 #define PMU_REG_CORE_RAMP_RATE_MASK              (0x18000000U)
 #define PMU_REG_CORE_RAMP_RATE_SHIFT             (27U)
+/*! RAMP_RATE
+ *  0b00..Fast
+ *  0b01..Medium Fast
+ *  0b10..Medium Slow
+ *  0b11..Slow
+ */
 #define PMU_REG_CORE_RAMP_RATE(x)                (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_RAMP_RATE_SHIFT)) & PMU_REG_CORE_RAMP_RATE_MASK)
 #define PMU_REG_CORE_FET_ODRIVE_MASK             (0x20000000U)
 #define PMU_REG_CORE_FET_ODRIVE_SHIFT            (29U)
@@ -18103,24 +28268,119 @@ typedef struct {
 /*! @{ */
 #define PMU_REG_CORE_SET_REG0_TARG_MASK          (0x1FU)
 #define PMU_REG_CORE_SET_REG0_TARG_SHIFT         (0U)
+/*! REG0_TARG
+ *  0b00000..Power gated off
+ *  0b00001..Target core voltage = 0.725V
+ *  0b00010..Target core voltage = 0.750V
+ *  0b00011..Target core voltage = 0.775V
+ *  0b10000..Target core voltage = 1.100V
+ *  0b11110..Target core voltage = 1.450V
+ *  0b11111..Power FET switched full on. No regulation.
+ */
 #define PMU_REG_CORE_SET_REG0_TARG(x)            (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG0_TARG_SHIFT)) & PMU_REG_CORE_SET_REG0_TARG_MASK)
 #define PMU_REG_CORE_SET_REG0_ADJ_MASK           (0x1E0U)
 #define PMU_REG_CORE_SET_REG0_ADJ_SHIFT          (5U)
+/*! REG0_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg0. The
+ *    adjustment is applied on top on any adjustment applied to the global reference in the misc0
+ *    register.
+ *  0b0000..No adjustment
+ *  0b0001..+ 0.25%
+ *  0b0010..+ 0.50%
+ *  0b0011..+ 0.75%
+ *  0b0100..+ 1.00%
+ *  0b0101..+ 1.25%
+ *  0b0110..+ 1.50%
+ *  0b0111..+ 1.75%
+ *  0b1000..- 0.25%
+ *  0b1001..- 0.50%
+ *  0b1010..- 0.75%
+ *  0b1011..- 1.00%
+ *  0b1100..- 1.25%
+ *  0b1101..- 1.50%
+ *  0b1110..- 1.75%
+ *  0b1111..- 2.00%
+ */
 #define PMU_REG_CORE_SET_REG0_ADJ(x)             (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG0_ADJ_SHIFT)) & PMU_REG_CORE_SET_REG0_ADJ_MASK)
 #define PMU_REG_CORE_SET_REG1_TARG_MASK          (0x3E00U)
 #define PMU_REG_CORE_SET_REG1_TARG_SHIFT         (9U)
+/*! REG1_TARG - This bit field defines the target voltage for the vpu/gpu power domain. Single bit
+ *    increments reflect 25mV core voltage steps. Not all steps will make sense to use either because
+ *    of input supply limitations or load operation.
+ *  0b00000..Power gated off
+ *  0b00001..Target core voltage = 0.725V
+ *  0b00010..Target core voltage = 0.750V
+ *  0b00011..Target core voltage = 0.775V
+ *  0b10000..Target core voltage = 1.100V
+ *  0b11110..Target core voltage = 1.450V
+ *  0b11111..Power FET switched full on. No regulation.
+ */
 #define PMU_REG_CORE_SET_REG1_TARG(x)            (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG1_TARG_SHIFT)) & PMU_REG_CORE_SET_REG1_TARG_MASK)
 #define PMU_REG_CORE_SET_REG1_ADJ_MASK           (0x3C000U)
 #define PMU_REG_CORE_SET_REG1_ADJ_SHIFT          (14U)
+/*! REG1_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg1. The
+ *    adjustment is applied on top on any adjustment applied to the global reference in the misc0
+ *    register.
+ *  0b0000..No adjustment
+ *  0b0001..+ 0.25%
+ *  0b0010..+ 0.50%
+ *  0b0011..+ 0.75%
+ *  0b0100..+ 1.00%
+ *  0b0101..+ 1.25%
+ *  0b0110..+ 1.50%
+ *  0b0111..+ 1.75%
+ *  0b1000..- 0.25%
+ *  0b1001..- 0.50%
+ *  0b1010..- 0.75%
+ *  0b1011..- 1.00%
+ *  0b1100..- 1.25%
+ *  0b1101..- 1.50%
+ *  0b1110..- 1.75%
+ *  0b1111..- 2.00%
+ */
 #define PMU_REG_CORE_SET_REG1_ADJ(x)             (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG1_ADJ_SHIFT)) & PMU_REG_CORE_SET_REG1_ADJ_MASK)
 #define PMU_REG_CORE_SET_REG2_TARG_MASK          (0x7C0000U)
 #define PMU_REG_CORE_SET_REG2_TARG_SHIFT         (18U)
+/*! REG2_TARG
+ *  0b00000..Power gated off
+ *  0b00001..Target core voltage = 0.725V
+ *  0b00010..Target core voltage = 0.750V
+ *  0b00011..Target core voltage = 0.775V
+ *  0b10000..Target core voltage = 1.100V
+ *  0b11110..Target core voltage = 1.450V
+ *  0b11111..Power FET switched full on. No regulation.
+ */
 #define PMU_REG_CORE_SET_REG2_TARG(x)            (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG2_TARG_SHIFT)) & PMU_REG_CORE_SET_REG2_TARG_MASK)
 #define PMU_REG_CORE_SET_REG2_ADJ_MASK           (0x7800000U)
 #define PMU_REG_CORE_SET_REG2_ADJ_SHIFT          (23U)
+/*! REG2_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg2. The
+ *    adjustment is applied on top on any adjustment applied to the global reference in the misc0
+ *    register.
+ *  0b0000..No adjustment
+ *  0b0001..+ 0.25%
+ *  0b0010..+ 0.50%
+ *  0b0011..+ 0.75%
+ *  0b0100..+ 1.00%
+ *  0b0101..+ 1.25%
+ *  0b0110..+ 1.50%
+ *  0b0111..+ 1.75%
+ *  0b1000..- 0.25%
+ *  0b1001..- 0.50%
+ *  0b1010..- 0.75%
+ *  0b1011..- 1.00%
+ *  0b1100..- 1.25%
+ *  0b1101..- 1.50%
+ *  0b1110..- 1.75%
+ *  0b1111..- 2.00%
+ */
 #define PMU_REG_CORE_SET_REG2_ADJ(x)             (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG2_ADJ_SHIFT)) & PMU_REG_CORE_SET_REG2_ADJ_MASK)
 #define PMU_REG_CORE_SET_RAMP_RATE_MASK          (0x18000000U)
 #define PMU_REG_CORE_SET_RAMP_RATE_SHIFT         (27U)
+/*! RAMP_RATE
+ *  0b00..Fast
+ *  0b01..Medium Fast
+ *  0b10..Medium Slow
+ *  0b11..Slow
+ */
 #define PMU_REG_CORE_SET_RAMP_RATE(x)            (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_RAMP_RATE_SHIFT)) & PMU_REG_CORE_SET_RAMP_RATE_MASK)
 #define PMU_REG_CORE_SET_FET_ODRIVE_MASK         (0x20000000U)
 #define PMU_REG_CORE_SET_FET_ODRIVE_SHIFT        (29U)
@@ -18131,24 +28391,119 @@ typedef struct {
 /*! @{ */
 #define PMU_REG_CORE_CLR_REG0_TARG_MASK          (0x1FU)
 #define PMU_REG_CORE_CLR_REG0_TARG_SHIFT         (0U)
+/*! REG0_TARG
+ *  0b00000..Power gated off
+ *  0b00001..Target core voltage = 0.725V
+ *  0b00010..Target core voltage = 0.750V
+ *  0b00011..Target core voltage = 0.775V
+ *  0b10000..Target core voltage = 1.100V
+ *  0b11110..Target core voltage = 1.450V
+ *  0b11111..Power FET switched full on. No regulation.
+ */
 #define PMU_REG_CORE_CLR_REG0_TARG(x)            (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG0_TARG_SHIFT)) & PMU_REG_CORE_CLR_REG0_TARG_MASK)
 #define PMU_REG_CORE_CLR_REG0_ADJ_MASK           (0x1E0U)
 #define PMU_REG_CORE_CLR_REG0_ADJ_SHIFT          (5U)
+/*! REG0_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg0. The
+ *    adjustment is applied on top on any adjustment applied to the global reference in the misc0
+ *    register.
+ *  0b0000..No adjustment
+ *  0b0001..+ 0.25%
+ *  0b0010..+ 0.50%
+ *  0b0011..+ 0.75%
+ *  0b0100..+ 1.00%
+ *  0b0101..+ 1.25%
+ *  0b0110..+ 1.50%
+ *  0b0111..+ 1.75%
+ *  0b1000..- 0.25%
+ *  0b1001..- 0.50%
+ *  0b1010..- 0.75%
+ *  0b1011..- 1.00%
+ *  0b1100..- 1.25%
+ *  0b1101..- 1.50%
+ *  0b1110..- 1.75%
+ *  0b1111..- 2.00%
+ */
 #define PMU_REG_CORE_CLR_REG0_ADJ(x)             (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG0_ADJ_SHIFT)) & PMU_REG_CORE_CLR_REG0_ADJ_MASK)
 #define PMU_REG_CORE_CLR_REG1_TARG_MASK          (0x3E00U)
 #define PMU_REG_CORE_CLR_REG1_TARG_SHIFT         (9U)
+/*! REG1_TARG - This bit field defines the target voltage for the vpu/gpu power domain. Single bit
+ *    increments reflect 25mV core voltage steps. Not all steps will make sense to use either because
+ *    of input supply limitations or load operation.
+ *  0b00000..Power gated off
+ *  0b00001..Target core voltage = 0.725V
+ *  0b00010..Target core voltage = 0.750V
+ *  0b00011..Target core voltage = 0.775V
+ *  0b10000..Target core voltage = 1.100V
+ *  0b11110..Target core voltage = 1.450V
+ *  0b11111..Power FET switched full on. No regulation.
+ */
 #define PMU_REG_CORE_CLR_REG1_TARG(x)            (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG1_TARG_SHIFT)) & PMU_REG_CORE_CLR_REG1_TARG_MASK)
 #define PMU_REG_CORE_CLR_REG1_ADJ_MASK           (0x3C000U)
 #define PMU_REG_CORE_CLR_REG1_ADJ_SHIFT          (14U)
+/*! REG1_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg1. The
+ *    adjustment is applied on top on any adjustment applied to the global reference in the misc0
+ *    register.
+ *  0b0000..No adjustment
+ *  0b0001..+ 0.25%
+ *  0b0010..+ 0.50%
+ *  0b0011..+ 0.75%
+ *  0b0100..+ 1.00%
+ *  0b0101..+ 1.25%
+ *  0b0110..+ 1.50%
+ *  0b0111..+ 1.75%
+ *  0b1000..- 0.25%
+ *  0b1001..- 0.50%
+ *  0b1010..- 0.75%
+ *  0b1011..- 1.00%
+ *  0b1100..- 1.25%
+ *  0b1101..- 1.50%
+ *  0b1110..- 1.75%
+ *  0b1111..- 2.00%
+ */
 #define PMU_REG_CORE_CLR_REG1_ADJ(x)             (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG1_ADJ_SHIFT)) & PMU_REG_CORE_CLR_REG1_ADJ_MASK)
 #define PMU_REG_CORE_CLR_REG2_TARG_MASK          (0x7C0000U)
 #define PMU_REG_CORE_CLR_REG2_TARG_SHIFT         (18U)
+/*! REG2_TARG
+ *  0b00000..Power gated off
+ *  0b00001..Target core voltage = 0.725V
+ *  0b00010..Target core voltage = 0.750V
+ *  0b00011..Target core voltage = 0.775V
+ *  0b10000..Target core voltage = 1.100V
+ *  0b11110..Target core voltage = 1.450V
+ *  0b11111..Power FET switched full on. No regulation.
+ */
 #define PMU_REG_CORE_CLR_REG2_TARG(x)            (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG2_TARG_SHIFT)) & PMU_REG_CORE_CLR_REG2_TARG_MASK)
 #define PMU_REG_CORE_CLR_REG2_ADJ_MASK           (0x7800000U)
 #define PMU_REG_CORE_CLR_REG2_ADJ_SHIFT          (23U)
+/*! REG2_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg2. The
+ *    adjustment is applied on top on any adjustment applied to the global reference in the misc0
+ *    register.
+ *  0b0000..No adjustment
+ *  0b0001..+ 0.25%
+ *  0b0010..+ 0.50%
+ *  0b0011..+ 0.75%
+ *  0b0100..+ 1.00%
+ *  0b0101..+ 1.25%
+ *  0b0110..+ 1.50%
+ *  0b0111..+ 1.75%
+ *  0b1000..- 0.25%
+ *  0b1001..- 0.50%
+ *  0b1010..- 0.75%
+ *  0b1011..- 1.00%
+ *  0b1100..- 1.25%
+ *  0b1101..- 1.50%
+ *  0b1110..- 1.75%
+ *  0b1111..- 2.00%
+ */
 #define PMU_REG_CORE_CLR_REG2_ADJ(x)             (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG2_ADJ_SHIFT)) & PMU_REG_CORE_CLR_REG2_ADJ_MASK)
 #define PMU_REG_CORE_CLR_RAMP_RATE_MASK          (0x18000000U)
 #define PMU_REG_CORE_CLR_RAMP_RATE_SHIFT         (27U)
+/*! RAMP_RATE
+ *  0b00..Fast
+ *  0b01..Medium Fast
+ *  0b10..Medium Slow
+ *  0b11..Slow
+ */
 #define PMU_REG_CORE_CLR_RAMP_RATE(x)            (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_RAMP_RATE_SHIFT)) & PMU_REG_CORE_CLR_RAMP_RATE_MASK)
 #define PMU_REG_CORE_CLR_FET_ODRIVE_MASK         (0x20000000U)
 #define PMU_REG_CORE_CLR_FET_ODRIVE_SHIFT        (29U)
@@ -18159,24 +28514,119 @@ typedef struct {
 /*! @{ */
 #define PMU_REG_CORE_TOG_REG0_TARG_MASK          (0x1FU)
 #define PMU_REG_CORE_TOG_REG0_TARG_SHIFT         (0U)
+/*! REG0_TARG
+ *  0b00000..Power gated off
+ *  0b00001..Target core voltage = 0.725V
+ *  0b00010..Target core voltage = 0.750V
+ *  0b00011..Target core voltage = 0.775V
+ *  0b10000..Target core voltage = 1.100V
+ *  0b11110..Target core voltage = 1.450V
+ *  0b11111..Power FET switched full on. No regulation.
+ */
 #define PMU_REG_CORE_TOG_REG0_TARG(x)            (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG0_TARG_SHIFT)) & PMU_REG_CORE_TOG_REG0_TARG_MASK)
 #define PMU_REG_CORE_TOG_REG0_ADJ_MASK           (0x1E0U)
 #define PMU_REG_CORE_TOG_REG0_ADJ_SHIFT          (5U)
+/*! REG0_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg0. The
+ *    adjustment is applied on top on any adjustment applied to the global reference in the misc0
+ *    register.
+ *  0b0000..No adjustment
+ *  0b0001..+ 0.25%
+ *  0b0010..+ 0.50%
+ *  0b0011..+ 0.75%
+ *  0b0100..+ 1.00%
+ *  0b0101..+ 1.25%
+ *  0b0110..+ 1.50%
+ *  0b0111..+ 1.75%
+ *  0b1000..- 0.25%
+ *  0b1001..- 0.50%
+ *  0b1010..- 0.75%
+ *  0b1011..- 1.00%
+ *  0b1100..- 1.25%
+ *  0b1101..- 1.50%
+ *  0b1110..- 1.75%
+ *  0b1111..- 2.00%
+ */
 #define PMU_REG_CORE_TOG_REG0_ADJ(x)             (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG0_ADJ_SHIFT)) & PMU_REG_CORE_TOG_REG0_ADJ_MASK)
 #define PMU_REG_CORE_TOG_REG1_TARG_MASK          (0x3E00U)
 #define PMU_REG_CORE_TOG_REG1_TARG_SHIFT         (9U)
+/*! REG1_TARG - This bit field defines the target voltage for the vpu/gpu power domain. Single bit
+ *    increments reflect 25mV core voltage steps. Not all steps will make sense to use either because
+ *    of input supply limitations or load operation.
+ *  0b00000..Power gated off
+ *  0b00001..Target core voltage = 0.725V
+ *  0b00010..Target core voltage = 0.750V
+ *  0b00011..Target core voltage = 0.775V
+ *  0b10000..Target core voltage = 1.100V
+ *  0b11110..Target core voltage = 1.450V
+ *  0b11111..Power FET switched full on. No regulation.
+ */
 #define PMU_REG_CORE_TOG_REG1_TARG(x)            (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG1_TARG_SHIFT)) & PMU_REG_CORE_TOG_REG1_TARG_MASK)
 #define PMU_REG_CORE_TOG_REG1_ADJ_MASK           (0x3C000U)
 #define PMU_REG_CORE_TOG_REG1_ADJ_SHIFT          (14U)
+/*! REG1_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg1. The
+ *    adjustment is applied on top on any adjustment applied to the global reference in the misc0
+ *    register.
+ *  0b0000..No adjustment
+ *  0b0001..+ 0.25%
+ *  0b0010..+ 0.50%
+ *  0b0011..+ 0.75%
+ *  0b0100..+ 1.00%
+ *  0b0101..+ 1.25%
+ *  0b0110..+ 1.50%
+ *  0b0111..+ 1.75%
+ *  0b1000..- 0.25%
+ *  0b1001..- 0.50%
+ *  0b1010..- 0.75%
+ *  0b1011..- 1.00%
+ *  0b1100..- 1.25%
+ *  0b1101..- 1.50%
+ *  0b1110..- 1.75%
+ *  0b1111..- 2.00%
+ */
 #define PMU_REG_CORE_TOG_REG1_ADJ(x)             (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG1_ADJ_SHIFT)) & PMU_REG_CORE_TOG_REG1_ADJ_MASK)
 #define PMU_REG_CORE_TOG_REG2_TARG_MASK          (0x7C0000U)
 #define PMU_REG_CORE_TOG_REG2_TARG_SHIFT         (18U)
+/*! REG2_TARG
+ *  0b00000..Power gated off
+ *  0b00001..Target core voltage = 0.725V
+ *  0b00010..Target core voltage = 0.750V
+ *  0b00011..Target core voltage = 0.775V
+ *  0b10000..Target core voltage = 1.100V
+ *  0b11110..Target core voltage = 1.450V
+ *  0b11111..Power FET switched full on. No regulation.
+ */
 #define PMU_REG_CORE_TOG_REG2_TARG(x)            (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG2_TARG_SHIFT)) & PMU_REG_CORE_TOG_REG2_TARG_MASK)
 #define PMU_REG_CORE_TOG_REG2_ADJ_MASK           (0x7800000U)
 #define PMU_REG_CORE_TOG_REG2_ADJ_SHIFT          (23U)
+/*! REG2_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg2. The
+ *    adjustment is applied on top on any adjustment applied to the global reference in the misc0
+ *    register.
+ *  0b0000..No adjustment
+ *  0b0001..+ 0.25%
+ *  0b0010..+ 0.50%
+ *  0b0011..+ 0.75%
+ *  0b0100..+ 1.00%
+ *  0b0101..+ 1.25%
+ *  0b0110..+ 1.50%
+ *  0b0111..+ 1.75%
+ *  0b1000..- 0.25%
+ *  0b1001..- 0.50%
+ *  0b1010..- 0.75%
+ *  0b1011..- 1.00%
+ *  0b1100..- 1.25%
+ *  0b1101..- 1.50%
+ *  0b1110..- 1.75%
+ *  0b1111..- 2.00%
+ */
 #define PMU_REG_CORE_TOG_REG2_ADJ(x)             (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG2_ADJ_SHIFT)) & PMU_REG_CORE_TOG_REG2_ADJ_MASK)
 #define PMU_REG_CORE_TOG_RAMP_RATE_MASK          (0x18000000U)
 #define PMU_REG_CORE_TOG_RAMP_RATE_SHIFT         (27U)
+/*! RAMP_RATE
+ *  0b00..Fast
+ *  0b01..Medium Fast
+ *  0b10..Medium Slow
+ *  0b11..Slow
+ */
 #define PMU_REG_CORE_TOG_RAMP_RATE(x)            (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_RAMP_RATE_SHIFT)) & PMU_REG_CORE_TOG_RAMP_RATE_MASK)
 #define PMU_REG_CORE_TOG_FET_ODRIVE_MASK         (0x20000000U)
 #define PMU_REG_CORE_TOG_FET_ODRIVE_SHIFT        (29U)
@@ -18190,21 +28640,51 @@ typedef struct {
 #define PMU_MISC0_REFTOP_PWD(x)                  (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_PWD_SHIFT)) & PMU_MISC0_REFTOP_PWD_MASK)
 #define PMU_MISC0_REFTOP_SELFBIASOFF_MASK        (0x8U)
 #define PMU_MISC0_REFTOP_SELFBIASOFF_SHIFT       (3U)
+/*! REFTOP_SELFBIASOFF
+ *  0b0..Uses coarse bias currents for startup
+ *  0b1..Uses bandgap-based bias currents for best performance.
+ */
 #define PMU_MISC0_REFTOP_SELFBIASOFF(x)          (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_REFTOP_SELFBIASOFF_MASK)
 #define PMU_MISC0_REFTOP_VBGADJ_MASK             (0x70U)
 #define PMU_MISC0_REFTOP_VBGADJ_SHIFT            (4U)
+/*! REFTOP_VBGADJ
+ *  0b000..Nominal VBG
+ *  0b001..VBG+0.78%
+ *  0b010..VBG+1.56%
+ *  0b011..VBG+2.34%
+ *  0b100..VBG-0.78%
+ *  0b101..VBG-1.56%
+ *  0b110..VBG-2.34%
+ *  0b111..VBG-3.12%
+ */
 #define PMU_MISC0_REFTOP_VBGADJ(x)               (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_REFTOP_VBGADJ_MASK)
 #define PMU_MISC0_REFTOP_VBGUP_MASK              (0x80U)
 #define PMU_MISC0_REFTOP_VBGUP_SHIFT             (7U)
 #define PMU_MISC0_REFTOP_VBGUP(x)                (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_REFTOP_VBGUP_MASK)
 #define PMU_MISC0_STOP_MODE_CONFIG_MASK          (0xC00U)
 #define PMU_MISC0_STOP_MODE_CONFIG_SHIFT         (10U)
+/*! STOP_MODE_CONFIG
+ *  0b00..SUSPEND (DSM)
+ *  0b01..Analog regulators are ON.
+ *  0b10..STOP (lower power)
+ *  0b11..STOP (very lower power)
+ */
 #define PMU_MISC0_STOP_MODE_CONFIG(x)            (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_STOP_MODE_CONFIG_MASK)
 #define PMU_MISC0_DISCON_HIGH_SNVS_MASK          (0x1000U)
 #define PMU_MISC0_DISCON_HIGH_SNVS_SHIFT         (12U)
+/*! DISCON_HIGH_SNVS
+ *  0b0..Turn on the switch
+ *  0b1..Turn off the switch
+ */
 #define PMU_MISC0_DISCON_HIGH_SNVS(x)            (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_DISCON_HIGH_SNVS_SHIFT)) & PMU_MISC0_DISCON_HIGH_SNVS_MASK)
 #define PMU_MISC0_OSC_I_MASK                     (0x6000U)
 #define PMU_MISC0_OSC_I_SHIFT                    (13U)
+/*! OSC_I
+ *  0b00..Nominal
+ *  0b01..Decrease current by 12.5%
+ *  0b10..Decrease current by 25.0%
+ *  0b11..Decrease current by 37.5%
+ */
 #define PMU_MISC0_OSC_I(x)                       (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_OSC_I_SHIFT)) & PMU_MISC0_OSC_I_MASK)
 #define PMU_MISC0_OSC_XTALOK_MASK                (0x8000U)
 #define PMU_MISC0_OSC_XTALOK_SHIFT               (15U)
@@ -18214,18 +28694,40 @@ typedef struct {
 #define PMU_MISC0_OSC_XTALOK_EN(x)               (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_OSC_XTALOK_EN_MASK)
 #define PMU_MISC0_CLKGATE_CTRL_MASK              (0x2000000U)
 #define PMU_MISC0_CLKGATE_CTRL_SHIFT             (25U)
+/*! CLKGATE_CTRL
+ *  0b0..Allow the logic to automatically gate the clock when the XTAL is powered down.
+ *  0b1..Prevent the logic from ever gating off the clock.
+ */
 #define PMU_MISC0_CLKGATE_CTRL(x)                (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_CLKGATE_CTRL_MASK)
 #define PMU_MISC0_CLKGATE_DELAY_MASK             (0x1C000000U)
 #define PMU_MISC0_CLKGATE_DELAY_SHIFT            (26U)
+/*! CLKGATE_DELAY
+ *  0b000..0.5ms
+ *  0b001..1.0ms
+ *  0b010..2.0ms
+ *  0b011..3.0ms
+ *  0b100..4.0ms
+ *  0b101..5.0ms
+ *  0b110..6.0ms
+ *  0b111..7.0ms
+ */
 #define PMU_MISC0_CLKGATE_DELAY(x)               (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_CLKGATE_DELAY_MASK)
 #define PMU_MISC0_RTC_XTAL_SOURCE_MASK           (0x20000000U)
 #define PMU_MISC0_RTC_XTAL_SOURCE_SHIFT          (29U)
+/*! RTC_XTAL_SOURCE
+ *  0b0..Internal ring oscillator
+ *  0b1..RTC_XTAL
+ */
 #define PMU_MISC0_RTC_XTAL_SOURCE(x)             (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_RTC_XTAL_SOURCE_MASK)
 #define PMU_MISC0_XTAL_24M_PWD_MASK              (0x40000000U)
 #define PMU_MISC0_XTAL_24M_PWD_SHIFT             (30U)
 #define PMU_MISC0_XTAL_24M_PWD(x)                (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_XTAL_24M_PWD_MASK)
 #define PMU_MISC0_VID_PLL_PREDIV_MASK            (0x80000000U)
 #define PMU_MISC0_VID_PLL_PREDIV_SHIFT           (31U)
+/*! VID_PLL_PREDIV
+ *  0b0..Divide by 1
+ *  0b1..Divide by 2
+ */
 #define PMU_MISC0_VID_PLL_PREDIV(x)              (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_VID_PLL_PREDIV_SHIFT)) & PMU_MISC0_VID_PLL_PREDIV_MASK)
 /*! @} */
 
@@ -18236,21 +28738,51 @@ typedef struct {
 #define PMU_MISC0_SET_REFTOP_PWD(x)              (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_PWD_SHIFT)) & PMU_MISC0_SET_REFTOP_PWD_MASK)
 #define PMU_MISC0_SET_REFTOP_SELFBIASOFF_MASK    (0x8U)
 #define PMU_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT   (3U)
+/*! REFTOP_SELFBIASOFF
+ *  0b0..Uses coarse bias currents for startup
+ *  0b1..Uses bandgap-based bias currents for best performance.
+ */
 #define PMU_MISC0_SET_REFTOP_SELFBIASOFF(x)      (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_SET_REFTOP_SELFBIASOFF_MASK)
 #define PMU_MISC0_SET_REFTOP_VBGADJ_MASK         (0x70U)
 #define PMU_MISC0_SET_REFTOP_VBGADJ_SHIFT        (4U)
+/*! REFTOP_VBGADJ
+ *  0b000..Nominal VBG
+ *  0b001..VBG+0.78%
+ *  0b010..VBG+1.56%
+ *  0b011..VBG+2.34%
+ *  0b100..VBG-0.78%
+ *  0b101..VBG-1.56%
+ *  0b110..VBG-2.34%
+ *  0b111..VBG-3.12%
+ */
 #define PMU_MISC0_SET_REFTOP_VBGADJ(x)           (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_SET_REFTOP_VBGADJ_MASK)
 #define PMU_MISC0_SET_REFTOP_VBGUP_MASK          (0x80U)
 #define PMU_MISC0_SET_REFTOP_VBGUP_SHIFT         (7U)
 #define PMU_MISC0_SET_REFTOP_VBGUP(x)            (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_SET_REFTOP_VBGUP_MASK)
 #define PMU_MISC0_SET_STOP_MODE_CONFIG_MASK      (0xC00U)
 #define PMU_MISC0_SET_STOP_MODE_CONFIG_SHIFT     (10U)
+/*! STOP_MODE_CONFIG
+ *  0b00..SUSPEND (DSM)
+ *  0b01..Analog regulators are ON.
+ *  0b10..STOP (lower power)
+ *  0b11..STOP (very lower power)
+ */
 #define PMU_MISC0_SET_STOP_MODE_CONFIG(x)        (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_SET_STOP_MODE_CONFIG_MASK)
 #define PMU_MISC0_SET_DISCON_HIGH_SNVS_MASK      (0x1000U)
 #define PMU_MISC0_SET_DISCON_HIGH_SNVS_SHIFT     (12U)
+/*! DISCON_HIGH_SNVS
+ *  0b0..Turn on the switch
+ *  0b1..Turn off the switch
+ */
 #define PMU_MISC0_SET_DISCON_HIGH_SNVS(x)        (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_DISCON_HIGH_SNVS_SHIFT)) & PMU_MISC0_SET_DISCON_HIGH_SNVS_MASK)
 #define PMU_MISC0_SET_OSC_I_MASK                 (0x6000U)
 #define PMU_MISC0_SET_OSC_I_SHIFT                (13U)
+/*! OSC_I
+ *  0b00..Nominal
+ *  0b01..Decrease current by 12.5%
+ *  0b10..Decrease current by 25.0%
+ *  0b11..Decrease current by 37.5%
+ */
 #define PMU_MISC0_SET_OSC_I(x)                   (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_OSC_I_SHIFT)) & PMU_MISC0_SET_OSC_I_MASK)
 #define PMU_MISC0_SET_OSC_XTALOK_MASK            (0x8000U)
 #define PMU_MISC0_SET_OSC_XTALOK_SHIFT           (15U)
@@ -18260,18 +28792,40 @@ typedef struct {
 #define PMU_MISC0_SET_OSC_XTALOK_EN(x)           (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_SET_OSC_XTALOK_EN_MASK)
 #define PMU_MISC0_SET_CLKGATE_CTRL_MASK          (0x2000000U)
 #define PMU_MISC0_SET_CLKGATE_CTRL_SHIFT         (25U)
+/*! CLKGATE_CTRL
+ *  0b0..Allow the logic to automatically gate the clock when the XTAL is powered down.
+ *  0b1..Prevent the logic from ever gating off the clock.
+ */
 #define PMU_MISC0_SET_CLKGATE_CTRL(x)            (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_SET_CLKGATE_CTRL_MASK)
 #define PMU_MISC0_SET_CLKGATE_DELAY_MASK         (0x1C000000U)
 #define PMU_MISC0_SET_CLKGATE_DELAY_SHIFT        (26U)
+/*! CLKGATE_DELAY
+ *  0b000..0.5ms
+ *  0b001..1.0ms
+ *  0b010..2.0ms
+ *  0b011..3.0ms
+ *  0b100..4.0ms
+ *  0b101..5.0ms
+ *  0b110..6.0ms
+ *  0b111..7.0ms
+ */
 #define PMU_MISC0_SET_CLKGATE_DELAY(x)           (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_SET_CLKGATE_DELAY_MASK)
 #define PMU_MISC0_SET_RTC_XTAL_SOURCE_MASK       (0x20000000U)
 #define PMU_MISC0_SET_RTC_XTAL_SOURCE_SHIFT      (29U)
+/*! RTC_XTAL_SOURCE
+ *  0b0..Internal ring oscillator
+ *  0b1..RTC_XTAL
+ */
 #define PMU_MISC0_SET_RTC_XTAL_SOURCE(x)         (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_SET_RTC_XTAL_SOURCE_MASK)
 #define PMU_MISC0_SET_XTAL_24M_PWD_MASK          (0x40000000U)
 #define PMU_MISC0_SET_XTAL_24M_PWD_SHIFT         (30U)
 #define PMU_MISC0_SET_XTAL_24M_PWD(x)            (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_SET_XTAL_24M_PWD_MASK)
 #define PMU_MISC0_SET_VID_PLL_PREDIV_MASK        (0x80000000U)
 #define PMU_MISC0_SET_VID_PLL_PREDIV_SHIFT       (31U)
+/*! VID_PLL_PREDIV
+ *  0b0..Divide by 1
+ *  0b1..Divide by 2
+ */
 #define PMU_MISC0_SET_VID_PLL_PREDIV(x)          (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_VID_PLL_PREDIV_SHIFT)) & PMU_MISC0_SET_VID_PLL_PREDIV_MASK)
 /*! @} */
 
@@ -18282,21 +28836,51 @@ typedef struct {
 #define PMU_MISC0_CLR_REFTOP_PWD(x)              (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_PWD_SHIFT)) & PMU_MISC0_CLR_REFTOP_PWD_MASK)
 #define PMU_MISC0_CLR_REFTOP_SELFBIASOFF_MASK    (0x8U)
 #define PMU_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT   (3U)
+/*! REFTOP_SELFBIASOFF
+ *  0b0..Uses coarse bias currents for startup
+ *  0b1..Uses bandgap-based bias currents for best performance.
+ */
 #define PMU_MISC0_CLR_REFTOP_SELFBIASOFF(x)      (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_CLR_REFTOP_SELFBIASOFF_MASK)
 #define PMU_MISC0_CLR_REFTOP_VBGADJ_MASK         (0x70U)
 #define PMU_MISC0_CLR_REFTOP_VBGADJ_SHIFT        (4U)
+/*! REFTOP_VBGADJ
+ *  0b000..Nominal VBG
+ *  0b001..VBG+0.78%
+ *  0b010..VBG+1.56%
+ *  0b011..VBG+2.34%
+ *  0b100..VBG-0.78%
+ *  0b101..VBG-1.56%
+ *  0b110..VBG-2.34%
+ *  0b111..VBG-3.12%
+ */
 #define PMU_MISC0_CLR_REFTOP_VBGADJ(x)           (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_CLR_REFTOP_VBGADJ_MASK)
 #define PMU_MISC0_CLR_REFTOP_VBGUP_MASK          (0x80U)
 #define PMU_MISC0_CLR_REFTOP_VBGUP_SHIFT         (7U)
 #define PMU_MISC0_CLR_REFTOP_VBGUP(x)            (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_CLR_REFTOP_VBGUP_MASK)
 #define PMU_MISC0_CLR_STOP_MODE_CONFIG_MASK      (0xC00U)
 #define PMU_MISC0_CLR_STOP_MODE_CONFIG_SHIFT     (10U)
+/*! STOP_MODE_CONFIG
+ *  0b00..SUSPEND (DSM)
+ *  0b01..Analog regulators are ON.
+ *  0b10..STOP (lower power)
+ *  0b11..STOP (very lower power)
+ */
 #define PMU_MISC0_CLR_STOP_MODE_CONFIG(x)        (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_CLR_STOP_MODE_CONFIG_MASK)
 #define PMU_MISC0_CLR_DISCON_HIGH_SNVS_MASK      (0x1000U)
 #define PMU_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT     (12U)
+/*! DISCON_HIGH_SNVS
+ *  0b0..Turn on the switch
+ *  0b1..Turn off the switch
+ */
 #define PMU_MISC0_CLR_DISCON_HIGH_SNVS(x)        (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT)) & PMU_MISC0_CLR_DISCON_HIGH_SNVS_MASK)
 #define PMU_MISC0_CLR_OSC_I_MASK                 (0x6000U)
 #define PMU_MISC0_CLR_OSC_I_SHIFT                (13U)
+/*! OSC_I
+ *  0b00..Nominal
+ *  0b01..Decrease current by 12.5%
+ *  0b10..Decrease current by 25.0%
+ *  0b11..Decrease current by 37.5%
+ */
 #define PMU_MISC0_CLR_OSC_I(x)                   (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_OSC_I_SHIFT)) & PMU_MISC0_CLR_OSC_I_MASK)
 #define PMU_MISC0_CLR_OSC_XTALOK_MASK            (0x8000U)
 #define PMU_MISC0_CLR_OSC_XTALOK_SHIFT           (15U)
@@ -18306,18 +28890,40 @@ typedef struct {
 #define PMU_MISC0_CLR_OSC_XTALOK_EN(x)           (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_CLR_OSC_XTALOK_EN_MASK)
 #define PMU_MISC0_CLR_CLKGATE_CTRL_MASK          (0x2000000U)
 #define PMU_MISC0_CLR_CLKGATE_CTRL_SHIFT         (25U)
+/*! CLKGATE_CTRL
+ *  0b0..Allow the logic to automatically gate the clock when the XTAL is powered down.
+ *  0b1..Prevent the logic from ever gating off the clock.
+ */
 #define PMU_MISC0_CLR_CLKGATE_CTRL(x)            (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_CLR_CLKGATE_CTRL_MASK)
 #define PMU_MISC0_CLR_CLKGATE_DELAY_MASK         (0x1C000000U)
 #define PMU_MISC0_CLR_CLKGATE_DELAY_SHIFT        (26U)
+/*! CLKGATE_DELAY
+ *  0b000..0.5ms
+ *  0b001..1.0ms
+ *  0b010..2.0ms
+ *  0b011..3.0ms
+ *  0b100..4.0ms
+ *  0b101..5.0ms
+ *  0b110..6.0ms
+ *  0b111..7.0ms
+ */
 #define PMU_MISC0_CLR_CLKGATE_DELAY(x)           (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_CLR_CLKGATE_DELAY_MASK)
 #define PMU_MISC0_CLR_RTC_XTAL_SOURCE_MASK       (0x20000000U)
 #define PMU_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT      (29U)
+/*! RTC_XTAL_SOURCE
+ *  0b0..Internal ring oscillator
+ *  0b1..RTC_XTAL
+ */
 #define PMU_MISC0_CLR_RTC_XTAL_SOURCE(x)         (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_CLR_RTC_XTAL_SOURCE_MASK)
 #define PMU_MISC0_CLR_XTAL_24M_PWD_MASK          (0x40000000U)
 #define PMU_MISC0_CLR_XTAL_24M_PWD_SHIFT         (30U)
 #define PMU_MISC0_CLR_XTAL_24M_PWD(x)            (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_CLR_XTAL_24M_PWD_MASK)
 #define PMU_MISC0_CLR_VID_PLL_PREDIV_MASK        (0x80000000U)
 #define PMU_MISC0_CLR_VID_PLL_PREDIV_SHIFT       (31U)
+/*! VID_PLL_PREDIV
+ *  0b0..Divide by 1
+ *  0b1..Divide by 2
+ */
 #define PMU_MISC0_CLR_VID_PLL_PREDIV(x)          (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_VID_PLL_PREDIV_SHIFT)) & PMU_MISC0_CLR_VID_PLL_PREDIV_MASK)
 /*! @} */
 
@@ -18328,21 +28934,51 @@ typedef struct {
 #define PMU_MISC0_TOG_REFTOP_PWD(x)              (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_PWD_SHIFT)) & PMU_MISC0_TOG_REFTOP_PWD_MASK)
 #define PMU_MISC0_TOG_REFTOP_SELFBIASOFF_MASK    (0x8U)
 #define PMU_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT   (3U)
+/*! REFTOP_SELFBIASOFF
+ *  0b0..Uses coarse bias currents for startup
+ *  0b1..Uses bandgap-based bias currents for best performance.
+ */
 #define PMU_MISC0_TOG_REFTOP_SELFBIASOFF(x)      (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_TOG_REFTOP_SELFBIASOFF_MASK)
 #define PMU_MISC0_TOG_REFTOP_VBGADJ_MASK         (0x70U)
 #define PMU_MISC0_TOG_REFTOP_VBGADJ_SHIFT        (4U)
+/*! REFTOP_VBGADJ
+ *  0b000..Nominal VBG
+ *  0b001..VBG+0.78%
+ *  0b010..VBG+1.56%
+ *  0b011..VBG+2.34%
+ *  0b100..VBG-0.78%
+ *  0b101..VBG-1.56%
+ *  0b110..VBG-2.34%
+ *  0b111..VBG-3.12%
+ */
 #define PMU_MISC0_TOG_REFTOP_VBGADJ(x)           (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_TOG_REFTOP_VBGADJ_MASK)
 #define PMU_MISC0_TOG_REFTOP_VBGUP_MASK          (0x80U)
 #define PMU_MISC0_TOG_REFTOP_VBGUP_SHIFT         (7U)
 #define PMU_MISC0_TOG_REFTOP_VBGUP(x)            (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_TOG_REFTOP_VBGUP_MASK)
 #define PMU_MISC0_TOG_STOP_MODE_CONFIG_MASK      (0xC00U)
 #define PMU_MISC0_TOG_STOP_MODE_CONFIG_SHIFT     (10U)
+/*! STOP_MODE_CONFIG
+ *  0b00..SUSPEND (DSM)
+ *  0b01..Analog regulators are ON.
+ *  0b10..STOP (lower power)
+ *  0b11..STOP (very lower power)
+ */
 #define PMU_MISC0_TOG_STOP_MODE_CONFIG(x)        (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_TOG_STOP_MODE_CONFIG_MASK)
 #define PMU_MISC0_TOG_DISCON_HIGH_SNVS_MASK      (0x1000U)
 #define PMU_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT     (12U)
+/*! DISCON_HIGH_SNVS
+ *  0b0..Turn on the switch
+ *  0b1..Turn off the switch
+ */
 #define PMU_MISC0_TOG_DISCON_HIGH_SNVS(x)        (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT)) & PMU_MISC0_TOG_DISCON_HIGH_SNVS_MASK)
 #define PMU_MISC0_TOG_OSC_I_MASK                 (0x6000U)
 #define PMU_MISC0_TOG_OSC_I_SHIFT                (13U)
+/*! OSC_I
+ *  0b00..Nominal
+ *  0b01..Decrease current by 12.5%
+ *  0b10..Decrease current by 25.0%
+ *  0b11..Decrease current by 37.5%
+ */
 #define PMU_MISC0_TOG_OSC_I(x)                   (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_OSC_I_SHIFT)) & PMU_MISC0_TOG_OSC_I_MASK)
 #define PMU_MISC0_TOG_OSC_XTALOK_MASK            (0x8000U)
 #define PMU_MISC0_TOG_OSC_XTALOK_SHIFT           (15U)
@@ -18352,18 +28988,40 @@ typedef struct {
 #define PMU_MISC0_TOG_OSC_XTALOK_EN(x)           (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_TOG_OSC_XTALOK_EN_MASK)
 #define PMU_MISC0_TOG_CLKGATE_CTRL_MASK          (0x2000000U)
 #define PMU_MISC0_TOG_CLKGATE_CTRL_SHIFT         (25U)
+/*! CLKGATE_CTRL
+ *  0b0..Allow the logic to automatically gate the clock when the XTAL is powered down.
+ *  0b1..Prevent the logic from ever gating off the clock.
+ */
 #define PMU_MISC0_TOG_CLKGATE_CTRL(x)            (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_TOG_CLKGATE_CTRL_MASK)
 #define PMU_MISC0_TOG_CLKGATE_DELAY_MASK         (0x1C000000U)
 #define PMU_MISC0_TOG_CLKGATE_DELAY_SHIFT        (26U)
+/*! CLKGATE_DELAY
+ *  0b000..0.5ms
+ *  0b001..1.0ms
+ *  0b010..2.0ms
+ *  0b011..3.0ms
+ *  0b100..4.0ms
+ *  0b101..5.0ms
+ *  0b110..6.0ms
+ *  0b111..7.0ms
+ */
 #define PMU_MISC0_TOG_CLKGATE_DELAY(x)           (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_TOG_CLKGATE_DELAY_MASK)
 #define PMU_MISC0_TOG_RTC_XTAL_SOURCE_MASK       (0x20000000U)
 #define PMU_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT      (29U)
+/*! RTC_XTAL_SOURCE
+ *  0b0..Internal ring oscillator
+ *  0b1..RTC_XTAL
+ */
 #define PMU_MISC0_TOG_RTC_XTAL_SOURCE(x)         (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_TOG_RTC_XTAL_SOURCE_MASK)
 #define PMU_MISC0_TOG_XTAL_24M_PWD_MASK          (0x40000000U)
 #define PMU_MISC0_TOG_XTAL_24M_PWD_SHIFT         (30U)
 #define PMU_MISC0_TOG_XTAL_24M_PWD(x)            (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_TOG_XTAL_24M_PWD_MASK)
 #define PMU_MISC0_TOG_VID_PLL_PREDIV_MASK        (0x80000000U)
 #define PMU_MISC0_TOG_VID_PLL_PREDIV_SHIFT       (31U)
+/*! VID_PLL_PREDIV
+ *  0b0..Divide by 1
+ *  0b1..Divide by 2
+ */
 #define PMU_MISC0_TOG_VID_PLL_PREDIV(x)          (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_VID_PLL_PREDIV_SHIFT)) & PMU_MISC0_TOG_VID_PLL_PREDIV_MASK)
 /*! @} */
 
@@ -18371,9 +29029,50 @@ typedef struct {
 /*! @{ */
 #define PMU_MISC1_LVDS1_CLK_SEL_MASK             (0x1FU)
 #define PMU_MISC1_LVDS1_CLK_SEL_SHIFT            (0U)
+/*! LVDS1_CLK_SEL
+ *  0b00000..Arm PLL
+ *  0b00001..System PLL
+ *  0b00010..ref_pfd4_clk == pll2_pfd0_clk
+ *  0b00011..ref_pfd5_clk == pll2_pfd1_clk
+ *  0b00100..ref_pfd6_clk == pll2_pfd2_clk
+ *  0b00101..ref_pfd7_clk == pll2_pfd3_clk
+ *  0b00110..Audio PLL
+ *  0b00111..Video PLL
+ *  0b01001..ethernet ref clock (ENET_PLL)
+ *  0b01100..USB1 PLL clock
+ *  0b01101..USB2 PLL clock
+ *  0b01110..ref_pfd0_clk == pll3_pfd0_clk
+ *  0b01111..ref_pfd1_clk == pll3_pfd1_clk
+ *  0b10000..ref_pfd2_clk == pll3_pfd2_clk
+ *  0b10001..ref_pfd3_clk == pll3_pfd3_clk
+ *  0b10010..xtal (24M)
+ */
 #define PMU_MISC1_LVDS1_CLK_SEL(x)               (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_LVDS1_CLK_SEL_MASK)
 #define PMU_MISC1_LVDS2_CLK_SEL_MASK             (0x3E0U)
 #define PMU_MISC1_LVDS2_CLK_SEL_SHIFT            (5U)
+/*! LVDS2_CLK_SEL
+ *  0b00000..Arm PLL
+ *  0b00001..System PLL
+ *  0b00010..ref_pfd4_clk == pll2_pfd0_clk
+ *  0b00011..ref_pfd5_clk == pll2_pfd1_clk
+ *  0b00100..ref_pfd6_clk == pll2_pfd2_clk
+ *  0b00101..ref_pfd7_clk == pll2_pfd3_clk
+ *  0b00110..Audio PLL
+ *  0b00111..Video PLL
+ *  0b01000..MLB PLL
+ *  0b01001..ethernet ref clock (ENET_PLL)
+ *  0b01010..PCIe ref clock (125M)
+ *  0b01011..SATA ref clock (100M)
+ *  0b01100..USB1 PLL clock
+ *  0b01101..USB2 PLL clock
+ *  0b01110..ref_pfd0_clk == pll3_pfd0_clk
+ *  0b01111..ref_pfd1_clk == pll3_pfd1_clk
+ *  0b10000..ref_pfd2_clk == pll3_pfd2_clk
+ *  0b10001..ref_pfd3_clk == pll3_pfd3_clk
+ *  0b10010..xtal (24M)
+ *  0b10011..LVDS1 (loopback)
+ *  0b10100..LVDS2 (not useful)
+ */
 #define PMU_MISC1_LVDS2_CLK_SEL(x)               (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_LVDS2_CLK_SEL_MASK)
 #define PMU_MISC1_LVDSCLK1_OBEN_MASK             (0x400U)
 #define PMU_MISC1_LVDSCLK1_OBEN_SHIFT            (10U)
@@ -18414,9 +29113,50 @@ typedef struct {
 /*! @{ */
 #define PMU_MISC1_SET_LVDS1_CLK_SEL_MASK         (0x1FU)
 #define PMU_MISC1_SET_LVDS1_CLK_SEL_SHIFT        (0U)
+/*! LVDS1_CLK_SEL
+ *  0b00000..Arm PLL
+ *  0b00001..System PLL
+ *  0b00010..ref_pfd4_clk == pll2_pfd0_clk
+ *  0b00011..ref_pfd5_clk == pll2_pfd1_clk
+ *  0b00100..ref_pfd6_clk == pll2_pfd2_clk
+ *  0b00101..ref_pfd7_clk == pll2_pfd3_clk
+ *  0b00110..Audio PLL
+ *  0b00111..Video PLL
+ *  0b01001..ethernet ref clock (ENET_PLL)
+ *  0b01100..USB1 PLL clock
+ *  0b01101..USB2 PLL clock
+ *  0b01110..ref_pfd0_clk == pll3_pfd0_clk
+ *  0b01111..ref_pfd1_clk == pll3_pfd1_clk
+ *  0b10000..ref_pfd2_clk == pll3_pfd2_clk
+ *  0b10001..ref_pfd3_clk == pll3_pfd3_clk
+ *  0b10010..xtal (24M)
+ */
 #define PMU_MISC1_SET_LVDS1_CLK_SEL(x)           (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_SET_LVDS1_CLK_SEL_MASK)
 #define PMU_MISC1_SET_LVDS2_CLK_SEL_MASK         (0x3E0U)
 #define PMU_MISC1_SET_LVDS2_CLK_SEL_SHIFT        (5U)
+/*! LVDS2_CLK_SEL
+ *  0b00000..Arm PLL
+ *  0b00001..System PLL
+ *  0b00010..ref_pfd4_clk == pll2_pfd0_clk
+ *  0b00011..ref_pfd5_clk == pll2_pfd1_clk
+ *  0b00100..ref_pfd6_clk == pll2_pfd2_clk
+ *  0b00101..ref_pfd7_clk == pll2_pfd3_clk
+ *  0b00110..Audio PLL
+ *  0b00111..Video PLL
+ *  0b01000..MLB PLL
+ *  0b01001..ethernet ref clock (ENET_PLL)
+ *  0b01010..PCIe ref clock (125M)
+ *  0b01011..SATA ref clock (100M)
+ *  0b01100..USB1 PLL clock
+ *  0b01101..USB2 PLL clock
+ *  0b01110..ref_pfd0_clk == pll3_pfd0_clk
+ *  0b01111..ref_pfd1_clk == pll3_pfd1_clk
+ *  0b10000..ref_pfd2_clk == pll3_pfd2_clk
+ *  0b10001..ref_pfd3_clk == pll3_pfd3_clk
+ *  0b10010..xtal (24M)
+ *  0b10011..LVDS1 (loopback)
+ *  0b10100..LVDS2 (not useful)
+ */
 #define PMU_MISC1_SET_LVDS2_CLK_SEL(x)           (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_SET_LVDS2_CLK_SEL_MASK)
 #define PMU_MISC1_SET_LVDSCLK1_OBEN_MASK         (0x400U)
 #define PMU_MISC1_SET_LVDSCLK1_OBEN_SHIFT        (10U)
@@ -18457,9 +29197,50 @@ typedef struct {
 /*! @{ */
 #define PMU_MISC1_CLR_LVDS1_CLK_SEL_MASK         (0x1FU)
 #define PMU_MISC1_CLR_LVDS1_CLK_SEL_SHIFT        (0U)
+/*! LVDS1_CLK_SEL
+ *  0b00000..Arm PLL
+ *  0b00001..System PLL
+ *  0b00010..ref_pfd4_clk == pll2_pfd0_clk
+ *  0b00011..ref_pfd5_clk == pll2_pfd1_clk
+ *  0b00100..ref_pfd6_clk == pll2_pfd2_clk
+ *  0b00101..ref_pfd7_clk == pll2_pfd3_clk
+ *  0b00110..Audio PLL
+ *  0b00111..Video PLL
+ *  0b01001..ethernet ref clock (ENET_PLL)
+ *  0b01100..USB1 PLL clock
+ *  0b01101..USB2 PLL clock
+ *  0b01110..ref_pfd0_clk == pll3_pfd0_clk
+ *  0b01111..ref_pfd1_clk == pll3_pfd1_clk
+ *  0b10000..ref_pfd2_clk == pll3_pfd2_clk
+ *  0b10001..ref_pfd3_clk == pll3_pfd3_clk
+ *  0b10010..xtal (24M)
+ */
 #define PMU_MISC1_CLR_LVDS1_CLK_SEL(x)           (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_CLR_LVDS1_CLK_SEL_MASK)
 #define PMU_MISC1_CLR_LVDS2_CLK_SEL_MASK         (0x3E0U)
 #define PMU_MISC1_CLR_LVDS2_CLK_SEL_SHIFT        (5U)
+/*! LVDS2_CLK_SEL
+ *  0b00000..Arm PLL
+ *  0b00001..System PLL
+ *  0b00010..ref_pfd4_clk == pll2_pfd0_clk
+ *  0b00011..ref_pfd5_clk == pll2_pfd1_clk
+ *  0b00100..ref_pfd6_clk == pll2_pfd2_clk
+ *  0b00101..ref_pfd7_clk == pll2_pfd3_clk
+ *  0b00110..Audio PLL
+ *  0b00111..Video PLL
+ *  0b01000..MLB PLL
+ *  0b01001..ethernet ref clock (ENET_PLL)
+ *  0b01010..PCIe ref clock (125M)
+ *  0b01011..SATA ref clock (100M)
+ *  0b01100..USB1 PLL clock
+ *  0b01101..USB2 PLL clock
+ *  0b01110..ref_pfd0_clk == pll3_pfd0_clk
+ *  0b01111..ref_pfd1_clk == pll3_pfd1_clk
+ *  0b10000..ref_pfd2_clk == pll3_pfd2_clk
+ *  0b10001..ref_pfd3_clk == pll3_pfd3_clk
+ *  0b10010..xtal (24M)
+ *  0b10011..LVDS1 (loopback)
+ *  0b10100..LVDS2 (not useful)
+ */
 #define PMU_MISC1_CLR_LVDS2_CLK_SEL(x)           (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_CLR_LVDS2_CLK_SEL_MASK)
 #define PMU_MISC1_CLR_LVDSCLK1_OBEN_MASK         (0x400U)
 #define PMU_MISC1_CLR_LVDSCLK1_OBEN_SHIFT        (10U)
@@ -18500,9 +29281,50 @@ typedef struct {
 /*! @{ */
 #define PMU_MISC1_TOG_LVDS1_CLK_SEL_MASK         (0x1FU)
 #define PMU_MISC1_TOG_LVDS1_CLK_SEL_SHIFT        (0U)
+/*! LVDS1_CLK_SEL
+ *  0b00000..Arm PLL
+ *  0b00001..System PLL
+ *  0b00010..ref_pfd4_clk == pll2_pfd0_clk
+ *  0b00011..ref_pfd5_clk == pll2_pfd1_clk
+ *  0b00100..ref_pfd6_clk == pll2_pfd2_clk
+ *  0b00101..ref_pfd7_clk == pll2_pfd3_clk
+ *  0b00110..Audio PLL
+ *  0b00111..Video PLL
+ *  0b01001..ethernet ref clock (ENET_PLL)
+ *  0b01100..USB1 PLL clock
+ *  0b01101..USB2 PLL clock
+ *  0b01110..ref_pfd0_clk == pll3_pfd0_clk
+ *  0b01111..ref_pfd1_clk == pll3_pfd1_clk
+ *  0b10000..ref_pfd2_clk == pll3_pfd2_clk
+ *  0b10001..ref_pfd3_clk == pll3_pfd3_clk
+ *  0b10010..xtal (24M)
+ */
 #define PMU_MISC1_TOG_LVDS1_CLK_SEL(x)           (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_TOG_LVDS1_CLK_SEL_MASK)
 #define PMU_MISC1_TOG_LVDS2_CLK_SEL_MASK         (0x3E0U)
 #define PMU_MISC1_TOG_LVDS2_CLK_SEL_SHIFT        (5U)
+/*! LVDS2_CLK_SEL
+ *  0b00000..Arm PLL
+ *  0b00001..System PLL
+ *  0b00010..ref_pfd4_clk == pll2_pfd0_clk
+ *  0b00011..ref_pfd5_clk == pll2_pfd1_clk
+ *  0b00100..ref_pfd6_clk == pll2_pfd2_clk
+ *  0b00101..ref_pfd7_clk == pll2_pfd3_clk
+ *  0b00110..Audio PLL
+ *  0b00111..Video PLL
+ *  0b01000..MLB PLL
+ *  0b01001..ethernet ref clock (ENET_PLL)
+ *  0b01010..PCIe ref clock (125M)
+ *  0b01011..SATA ref clock (100M)
+ *  0b01100..USB1 PLL clock
+ *  0b01101..USB2 PLL clock
+ *  0b01110..ref_pfd0_clk == pll3_pfd0_clk
+ *  0b01111..ref_pfd1_clk == pll3_pfd1_clk
+ *  0b10000..ref_pfd2_clk == pll3_pfd2_clk
+ *  0b10001..ref_pfd3_clk == pll3_pfd3_clk
+ *  0b10010..xtal (24M)
+ *  0b10011..LVDS1 (loopback)
+ *  0b10100..LVDS2 (not useful)
+ */
 #define PMU_MISC1_TOG_LVDS2_CLK_SEL(x)           (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_TOG_LVDS2_CLK_SEL_MASK)
 #define PMU_MISC1_TOG_LVDSCLK1_OBEN_MASK         (0x400U)
 #define PMU_MISC1_TOG_LVDSCLK1_OBEN_SHIFT        (10U)
@@ -18543,9 +29365,16 @@ typedef struct {
 /*! @{ */
 #define PMU_MISC2_REG0_BO_OFFSET_MASK            (0x7U)
 #define PMU_MISC2_REG0_BO_OFFSET_SHIFT           (0U)
+/*! REG0_BO_OFFSET
+ *  0b100..Brownout offset = 0.100V
+ *  0b111..Brownout offset = 0.175V
+ */
 #define PMU_MISC2_REG0_BO_OFFSET(x)              (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_REG0_BO_OFFSET_MASK)
 #define PMU_MISC2_REG0_BO_STATUS_MASK            (0x8U)
 #define PMU_MISC2_REG0_BO_STATUS_SHIFT           (3U)
+/*! REG0_BO_STATUS
+ *  0b1..Brownout, supply is below target minus brownout offset.
+ */
 #define PMU_MISC2_REG0_BO_STATUS(x)              (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG0_BO_STATUS_SHIFT)) & PMU_MISC2_REG0_BO_STATUS_MASK)
 #define PMU_MISC2_REG0_ENABLE_BO_MASK            (0x20U)
 #define PMU_MISC2_REG0_ENABLE_BO_SHIFT           (5U)
@@ -18555,18 +29384,33 @@ typedef struct {
 #define PMU_MISC2_PLL3_disable(x)                (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_PLL3_disable_SHIFT)) & PMU_MISC2_PLL3_disable_MASK)
 #define PMU_MISC2_REG1_BO_OFFSET_MASK            (0x700U)
 #define PMU_MISC2_REG1_BO_OFFSET_SHIFT           (8U)
+/*! REG1_BO_OFFSET
+ *  0b100..Brownout offset = 0.100V
+ *  0b111..Brownout offset = 0.175V
+ */
 #define PMU_MISC2_REG1_BO_OFFSET(x)              (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_REG1_BO_OFFSET_MASK)
 #define PMU_MISC2_REG1_BO_STATUS_MASK            (0x800U)
 #define PMU_MISC2_REG1_BO_STATUS_SHIFT           (11U)
+/*! REG1_BO_STATUS
+ *  0b1..Brownout, supply is below target minus brownout offset.
+ */
 #define PMU_MISC2_REG1_BO_STATUS(x)              (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG1_BO_STATUS_SHIFT)) & PMU_MISC2_REG1_BO_STATUS_MASK)
 #define PMU_MISC2_REG1_ENABLE_BO_MASK            (0x2000U)
 #define PMU_MISC2_REG1_ENABLE_BO_SHIFT           (13U)
 #define PMU_MISC2_REG1_ENABLE_BO(x)              (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG1_ENABLE_BO_SHIFT)) & PMU_MISC2_REG1_ENABLE_BO_MASK)
 #define PMU_MISC2_AUDIO_DIV_LSB_MASK             (0x8000U)
 #define PMU_MISC2_AUDIO_DIV_LSB_SHIFT            (15U)
+/*! AUDIO_DIV_LSB
+ *  0b0..divide by 1 (Default)
+ *  0b1..divide by 2
+ */
 #define PMU_MISC2_AUDIO_DIV_LSB(x)               (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_AUDIO_DIV_LSB_MASK)
 #define PMU_MISC2_REG2_BO_OFFSET_MASK            (0x70000U)
 #define PMU_MISC2_REG2_BO_OFFSET_SHIFT           (16U)
+/*! REG2_BO_OFFSET
+ *  0b100..Brownout offset = 0.100V
+ *  0b111..Brownout offset = 0.175V
+ */
 #define PMU_MISC2_REG2_BO_OFFSET(x)              (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_REG2_BO_OFFSET_MASK)
 #define PMU_MISC2_REG2_BO_STATUS_MASK            (0x80000U)
 #define PMU_MISC2_REG2_BO_STATUS_SHIFT           (19U)
@@ -18579,18 +29423,46 @@ typedef struct {
 #define PMU_MISC2_REG2_OK(x)                     (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_OK_SHIFT)) & PMU_MISC2_REG2_OK_MASK)
 #define PMU_MISC2_AUDIO_DIV_MSB_MASK             (0x800000U)
 #define PMU_MISC2_AUDIO_DIV_MSB_SHIFT            (23U)
+/*! AUDIO_DIV_MSB
+ *  0b0..divide by 1 (Default)
+ *  0b1..divide by 2
+ */
 #define PMU_MISC2_AUDIO_DIV_MSB(x)               (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_AUDIO_DIV_MSB_SHIFT)) & PMU_MISC2_AUDIO_DIV_MSB_MASK)
 #define PMU_MISC2_REG0_STEP_TIME_MASK            (0x3000000U)
 #define PMU_MISC2_REG0_STEP_TIME_SHIFT           (24U)
+/*! REG0_STEP_TIME
+ *  0b00..64
+ *  0b01..128
+ *  0b10..256
+ *  0b11..512
+ */
 #define PMU_MISC2_REG0_STEP_TIME(x)              (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_REG0_STEP_TIME_MASK)
 #define PMU_MISC2_REG1_STEP_TIME_MASK            (0xC000000U)
 #define PMU_MISC2_REG1_STEP_TIME_SHIFT           (26U)
+/*! REG1_STEP_TIME
+ *  0b00..64
+ *  0b01..128
+ *  0b10..256
+ *  0b11..512
+ */
 #define PMU_MISC2_REG1_STEP_TIME(x)              (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG1_STEP_TIME_SHIFT)) & PMU_MISC2_REG1_STEP_TIME_MASK)
 #define PMU_MISC2_REG2_STEP_TIME_MASK            (0x30000000U)
 #define PMU_MISC2_REG2_STEP_TIME_SHIFT           (28U)
+/*! REG2_STEP_TIME
+ *  0b00..64
+ *  0b01..128
+ *  0b10..256
+ *  0b11..512
+ */
 #define PMU_MISC2_REG2_STEP_TIME(x)              (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_REG2_STEP_TIME_MASK)
 #define PMU_MISC2_VIDEO_DIV_MASK                 (0xC0000000U)
 #define PMU_MISC2_VIDEO_DIV_SHIFT                (30U)
+/*! VIDEO_DIV
+ *  0b00..divide by 1 (Default)
+ *  0b01..divide by 2
+ *  0b10..divide by 1
+ *  0b11..divide by 4
+ */
 #define PMU_MISC2_VIDEO_DIV(x)                   (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_VIDEO_DIV_SHIFT)) & PMU_MISC2_VIDEO_DIV_MASK)
 /*! @} */
 
@@ -18598,9 +29470,16 @@ typedef struct {
 /*! @{ */
 #define PMU_MISC2_SET_REG0_BO_OFFSET_MASK        (0x7U)
 #define PMU_MISC2_SET_REG0_BO_OFFSET_SHIFT       (0U)
+/*! REG0_BO_OFFSET
+ *  0b100..Brownout offset = 0.100V
+ *  0b111..Brownout offset = 0.175V
+ */
 #define PMU_MISC2_SET_REG0_BO_OFFSET(x)          (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_SET_REG0_BO_OFFSET_MASK)
 #define PMU_MISC2_SET_REG0_BO_STATUS_MASK        (0x8U)
 #define PMU_MISC2_SET_REG0_BO_STATUS_SHIFT       (3U)
+/*! REG0_BO_STATUS
+ *  0b1..Brownout, supply is below target minus brownout offset.
+ */
 #define PMU_MISC2_SET_REG0_BO_STATUS(x)          (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_BO_STATUS_SHIFT)) & PMU_MISC2_SET_REG0_BO_STATUS_MASK)
 #define PMU_MISC2_SET_REG0_ENABLE_BO_MASK        (0x20U)
 #define PMU_MISC2_SET_REG0_ENABLE_BO_SHIFT       (5U)
@@ -18610,18 +29489,33 @@ typedef struct {
 #define PMU_MISC2_SET_PLL3_disable(x)            (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_PLL3_disable_SHIFT)) & PMU_MISC2_SET_PLL3_disable_MASK)
 #define PMU_MISC2_SET_REG1_BO_OFFSET_MASK        (0x700U)
 #define PMU_MISC2_SET_REG1_BO_OFFSET_SHIFT       (8U)
+/*! REG1_BO_OFFSET
+ *  0b100..Brownout offset = 0.100V
+ *  0b111..Brownout offset = 0.175V
+ */
 #define PMU_MISC2_SET_REG1_BO_OFFSET(x)          (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_SET_REG1_BO_OFFSET_MASK)
 #define PMU_MISC2_SET_REG1_BO_STATUS_MASK        (0x800U)
 #define PMU_MISC2_SET_REG1_BO_STATUS_SHIFT       (11U)
+/*! REG1_BO_STATUS
+ *  0b1..Brownout, supply is below target minus brownout offset.
+ */
 #define PMU_MISC2_SET_REG1_BO_STATUS(x)          (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG1_BO_STATUS_SHIFT)) & PMU_MISC2_SET_REG1_BO_STATUS_MASK)
 #define PMU_MISC2_SET_REG1_ENABLE_BO_MASK        (0x2000U)
 #define PMU_MISC2_SET_REG1_ENABLE_BO_SHIFT       (13U)
 #define PMU_MISC2_SET_REG1_ENABLE_BO(x)          (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG1_ENABLE_BO_SHIFT)) & PMU_MISC2_SET_REG1_ENABLE_BO_MASK)
 #define PMU_MISC2_SET_AUDIO_DIV_LSB_MASK         (0x8000U)
 #define PMU_MISC2_SET_AUDIO_DIV_LSB_SHIFT        (15U)
+/*! AUDIO_DIV_LSB
+ *  0b0..divide by 1 (Default)
+ *  0b1..divide by 2
+ */
 #define PMU_MISC2_SET_AUDIO_DIV_LSB(x)           (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_SET_AUDIO_DIV_LSB_MASK)
 #define PMU_MISC2_SET_REG2_BO_OFFSET_MASK        (0x70000U)
 #define PMU_MISC2_SET_REG2_BO_OFFSET_SHIFT       (16U)
+/*! REG2_BO_OFFSET
+ *  0b100..Brownout offset = 0.100V
+ *  0b111..Brownout offset = 0.175V
+ */
 #define PMU_MISC2_SET_REG2_BO_OFFSET(x)          (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_SET_REG2_BO_OFFSET_MASK)
 #define PMU_MISC2_SET_REG2_BO_STATUS_MASK        (0x80000U)
 #define PMU_MISC2_SET_REG2_BO_STATUS_SHIFT       (19U)
@@ -18634,18 +29528,46 @@ typedef struct {
 #define PMU_MISC2_SET_REG2_OK(x)                 (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_OK_SHIFT)) & PMU_MISC2_SET_REG2_OK_MASK)
 #define PMU_MISC2_SET_AUDIO_DIV_MSB_MASK         (0x800000U)
 #define PMU_MISC2_SET_AUDIO_DIV_MSB_SHIFT        (23U)
+/*! AUDIO_DIV_MSB
+ *  0b0..divide by 1 (Default)
+ *  0b1..divide by 2
+ */
 #define PMU_MISC2_SET_AUDIO_DIV_MSB(x)           (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_AUDIO_DIV_MSB_SHIFT)) & PMU_MISC2_SET_AUDIO_DIV_MSB_MASK)
 #define PMU_MISC2_SET_REG0_STEP_TIME_MASK        (0x3000000U)
 #define PMU_MISC2_SET_REG0_STEP_TIME_SHIFT       (24U)
+/*! REG0_STEP_TIME
+ *  0b00..64
+ *  0b01..128
+ *  0b10..256
+ *  0b11..512
+ */
 #define PMU_MISC2_SET_REG0_STEP_TIME(x)          (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_SET_REG0_STEP_TIME_MASK)
 #define PMU_MISC2_SET_REG1_STEP_TIME_MASK        (0xC000000U)
 #define PMU_MISC2_SET_REG1_STEP_TIME_SHIFT       (26U)
+/*! REG1_STEP_TIME
+ *  0b00..64
+ *  0b01..128
+ *  0b10..256
+ *  0b11..512
+ */
 #define PMU_MISC2_SET_REG1_STEP_TIME(x)          (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG1_STEP_TIME_SHIFT)) & PMU_MISC2_SET_REG1_STEP_TIME_MASK)
 #define PMU_MISC2_SET_REG2_STEP_TIME_MASK        (0x30000000U)
 #define PMU_MISC2_SET_REG2_STEP_TIME_SHIFT       (28U)
+/*! REG2_STEP_TIME
+ *  0b00..64
+ *  0b01..128
+ *  0b10..256
+ *  0b11..512
+ */
 #define PMU_MISC2_SET_REG2_STEP_TIME(x)          (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_SET_REG2_STEP_TIME_MASK)
 #define PMU_MISC2_SET_VIDEO_DIV_MASK             (0xC0000000U)
 #define PMU_MISC2_SET_VIDEO_DIV_SHIFT            (30U)
+/*! VIDEO_DIV
+ *  0b00..divide by 1 (Default)
+ *  0b01..divide by 2
+ *  0b10..divide by 1
+ *  0b11..divide by 4
+ */
 #define PMU_MISC2_SET_VIDEO_DIV(x)               (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_VIDEO_DIV_SHIFT)) & PMU_MISC2_SET_VIDEO_DIV_MASK)
 /*! @} */
 
@@ -18653,9 +29575,16 @@ typedef struct {
 /*! @{ */
 #define PMU_MISC2_CLR_REG0_BO_OFFSET_MASK        (0x7U)
 #define PMU_MISC2_CLR_REG0_BO_OFFSET_SHIFT       (0U)
+/*! REG0_BO_OFFSET
+ *  0b100..Brownout offset = 0.100V
+ *  0b111..Brownout offset = 0.175V
+ */
 #define PMU_MISC2_CLR_REG0_BO_OFFSET(x)          (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_CLR_REG0_BO_OFFSET_MASK)
 #define PMU_MISC2_CLR_REG0_BO_STATUS_MASK        (0x8U)
 #define PMU_MISC2_CLR_REG0_BO_STATUS_SHIFT       (3U)
+/*! REG0_BO_STATUS
+ *  0b1..Brownout, supply is below target minus brownout offset.
+ */
 #define PMU_MISC2_CLR_REG0_BO_STATUS(x)          (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG0_BO_STATUS_SHIFT)) & PMU_MISC2_CLR_REG0_BO_STATUS_MASK)
 #define PMU_MISC2_CLR_REG0_ENABLE_BO_MASK        (0x20U)
 #define PMU_MISC2_CLR_REG0_ENABLE_BO_SHIFT       (5U)
@@ -18665,18 +29594,33 @@ typedef struct {
 #define PMU_MISC2_CLR_PLL3_disable(x)            (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_PLL3_disable_SHIFT)) & PMU_MISC2_CLR_PLL3_disable_MASK)
 #define PMU_MISC2_CLR_REG1_BO_OFFSET_MASK        (0x700U)
 #define PMU_MISC2_CLR_REG1_BO_OFFSET_SHIFT       (8U)
+/*! REG1_BO_OFFSET
+ *  0b100..Brownout offset = 0.100V
+ *  0b111..Brownout offset = 0.175V
+ */
 #define PMU_MISC2_CLR_REG1_BO_OFFSET(x)          (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_CLR_REG1_BO_OFFSET_MASK)
 #define PMU_MISC2_CLR_REG1_BO_STATUS_MASK        (0x800U)
 #define PMU_MISC2_CLR_REG1_BO_STATUS_SHIFT       (11U)
+/*! REG1_BO_STATUS
+ *  0b1..Brownout, supply is below target minus brownout offset.
+ */
 #define PMU_MISC2_CLR_REG1_BO_STATUS(x)          (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG1_BO_STATUS_SHIFT)) & PMU_MISC2_CLR_REG1_BO_STATUS_MASK)
 #define PMU_MISC2_CLR_REG1_ENABLE_BO_MASK        (0x2000U)
 #define PMU_MISC2_CLR_REG1_ENABLE_BO_SHIFT       (13U)
 #define PMU_MISC2_CLR_REG1_ENABLE_BO(x)          (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG1_ENABLE_BO_SHIFT)) & PMU_MISC2_CLR_REG1_ENABLE_BO_MASK)
 #define PMU_MISC2_CLR_AUDIO_DIV_LSB_MASK         (0x8000U)
 #define PMU_MISC2_CLR_AUDIO_DIV_LSB_SHIFT        (15U)
+/*! AUDIO_DIV_LSB
+ *  0b0..divide by 1 (Default)
+ *  0b1..divide by 2
+ */
 #define PMU_MISC2_CLR_AUDIO_DIV_LSB(x)           (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_CLR_AUDIO_DIV_LSB_MASK)
 #define PMU_MISC2_CLR_REG2_BO_OFFSET_MASK        (0x70000U)
 #define PMU_MISC2_CLR_REG2_BO_OFFSET_SHIFT       (16U)
+/*! REG2_BO_OFFSET
+ *  0b100..Brownout offset = 0.100V
+ *  0b111..Brownout offset = 0.175V
+ */
 #define PMU_MISC2_CLR_REG2_BO_OFFSET(x)          (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_CLR_REG2_BO_OFFSET_MASK)
 #define PMU_MISC2_CLR_REG2_BO_STATUS_MASK        (0x80000U)
 #define PMU_MISC2_CLR_REG2_BO_STATUS_SHIFT       (19U)
@@ -18689,18 +29633,46 @@ typedef struct {
 #define PMU_MISC2_CLR_REG2_OK(x)                 (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_OK_SHIFT)) & PMU_MISC2_CLR_REG2_OK_MASK)
 #define PMU_MISC2_CLR_AUDIO_DIV_MSB_MASK         (0x800000U)
 #define PMU_MISC2_CLR_AUDIO_DIV_MSB_SHIFT        (23U)
+/*! AUDIO_DIV_MSB
+ *  0b0..divide by 1 (Default)
+ *  0b1..divide by 2
+ */
 #define PMU_MISC2_CLR_AUDIO_DIV_MSB(x)           (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_AUDIO_DIV_MSB_SHIFT)) & PMU_MISC2_CLR_AUDIO_DIV_MSB_MASK)
 #define PMU_MISC2_CLR_REG0_STEP_TIME_MASK        (0x3000000U)
 #define PMU_MISC2_CLR_REG0_STEP_TIME_SHIFT       (24U)
+/*! REG0_STEP_TIME
+ *  0b00..64
+ *  0b01..128
+ *  0b10..256
+ *  0b11..512
+ */
 #define PMU_MISC2_CLR_REG0_STEP_TIME(x)          (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_CLR_REG0_STEP_TIME_MASK)
 #define PMU_MISC2_CLR_REG1_STEP_TIME_MASK        (0xC000000U)
 #define PMU_MISC2_CLR_REG1_STEP_TIME_SHIFT       (26U)
+/*! REG1_STEP_TIME
+ *  0b00..64
+ *  0b01..128
+ *  0b10..256
+ *  0b11..512
+ */
 #define PMU_MISC2_CLR_REG1_STEP_TIME(x)          (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG1_STEP_TIME_SHIFT)) & PMU_MISC2_CLR_REG1_STEP_TIME_MASK)
 #define PMU_MISC2_CLR_REG2_STEP_TIME_MASK        (0x30000000U)
 #define PMU_MISC2_CLR_REG2_STEP_TIME_SHIFT       (28U)
+/*! REG2_STEP_TIME
+ *  0b00..64
+ *  0b01..128
+ *  0b10..256
+ *  0b11..512
+ */
 #define PMU_MISC2_CLR_REG2_STEP_TIME(x)          (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_CLR_REG2_STEP_TIME_MASK)
 #define PMU_MISC2_CLR_VIDEO_DIV_MASK             (0xC0000000U)
 #define PMU_MISC2_CLR_VIDEO_DIV_SHIFT            (30U)
+/*! VIDEO_DIV
+ *  0b00..divide by 1 (Default)
+ *  0b01..divide by 2
+ *  0b10..divide by 1
+ *  0b11..divide by 4
+ */
 #define PMU_MISC2_CLR_VIDEO_DIV(x)               (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_VIDEO_DIV_SHIFT)) & PMU_MISC2_CLR_VIDEO_DIV_MASK)
 /*! @} */
 
@@ -18708,9 +29680,16 @@ typedef struct {
 /*! @{ */
 #define PMU_MISC2_TOG_REG0_BO_OFFSET_MASK        (0x7U)
 #define PMU_MISC2_TOG_REG0_BO_OFFSET_SHIFT       (0U)
+/*! REG0_BO_OFFSET
+ *  0b100..Brownout offset = 0.100V
+ *  0b111..Brownout offset = 0.175V
+ */
 #define PMU_MISC2_TOG_REG0_BO_OFFSET(x)          (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_TOG_REG0_BO_OFFSET_MASK)
 #define PMU_MISC2_TOG_REG0_BO_STATUS_MASK        (0x8U)
 #define PMU_MISC2_TOG_REG0_BO_STATUS_SHIFT       (3U)
+/*! REG0_BO_STATUS
+ *  0b1..Brownout, supply is below target minus brownout offset.
+ */
 #define PMU_MISC2_TOG_REG0_BO_STATUS(x)          (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG0_BO_STATUS_SHIFT)) & PMU_MISC2_TOG_REG0_BO_STATUS_MASK)
 #define PMU_MISC2_TOG_REG0_ENABLE_BO_MASK        (0x20U)
 #define PMU_MISC2_TOG_REG0_ENABLE_BO_SHIFT       (5U)
@@ -18720,18 +29699,33 @@ typedef struct {
 #define PMU_MISC2_TOG_PLL3_disable(x)            (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_PLL3_disable_SHIFT)) & PMU_MISC2_TOG_PLL3_disable_MASK)
 #define PMU_MISC2_TOG_REG1_BO_OFFSET_MASK        (0x700U)
 #define PMU_MISC2_TOG_REG1_BO_OFFSET_SHIFT       (8U)
+/*! REG1_BO_OFFSET
+ *  0b100..Brownout offset = 0.100V
+ *  0b111..Brownout offset = 0.175V
+ */
 #define PMU_MISC2_TOG_REG1_BO_OFFSET(x)          (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_TOG_REG1_BO_OFFSET_MASK)
 #define PMU_MISC2_TOG_REG1_BO_STATUS_MASK        (0x800U)
 #define PMU_MISC2_TOG_REG1_BO_STATUS_SHIFT       (11U)
+/*! REG1_BO_STATUS
+ *  0b1..Brownout, supply is below target minus brownout offset.
+ */
 #define PMU_MISC2_TOG_REG1_BO_STATUS(x)          (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_BO_STATUS_SHIFT)) & PMU_MISC2_TOG_REG1_BO_STATUS_MASK)
 #define PMU_MISC2_TOG_REG1_ENABLE_BO_MASK        (0x2000U)
 #define PMU_MISC2_TOG_REG1_ENABLE_BO_SHIFT       (13U)
 #define PMU_MISC2_TOG_REG1_ENABLE_BO(x)          (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_ENABLE_BO_SHIFT)) & PMU_MISC2_TOG_REG1_ENABLE_BO_MASK)
 #define PMU_MISC2_TOG_AUDIO_DIV_LSB_MASK         (0x8000U)
 #define PMU_MISC2_TOG_AUDIO_DIV_LSB_SHIFT        (15U)
+/*! AUDIO_DIV_LSB
+ *  0b0..divide by 1 (Default)
+ *  0b1..divide by 2
+ */
 #define PMU_MISC2_TOG_AUDIO_DIV_LSB(x)           (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_TOG_AUDIO_DIV_LSB_MASK)
 #define PMU_MISC2_TOG_REG2_BO_OFFSET_MASK        (0x70000U)
 #define PMU_MISC2_TOG_REG2_BO_OFFSET_SHIFT       (16U)
+/*! REG2_BO_OFFSET
+ *  0b100..Brownout offset = 0.100V
+ *  0b111..Brownout offset = 0.175V
+ */
 #define PMU_MISC2_TOG_REG2_BO_OFFSET(x)          (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_TOG_REG2_BO_OFFSET_MASK)
 #define PMU_MISC2_TOG_REG2_BO_STATUS_MASK        (0x80000U)
 #define PMU_MISC2_TOG_REG2_BO_STATUS_SHIFT       (19U)
@@ -18744,18 +29738,46 @@ typedef struct {
 #define PMU_MISC2_TOG_REG2_OK(x)                 (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_OK_SHIFT)) & PMU_MISC2_TOG_REG2_OK_MASK)
 #define PMU_MISC2_TOG_AUDIO_DIV_MSB_MASK         (0x800000U)
 #define PMU_MISC2_TOG_AUDIO_DIV_MSB_SHIFT        (23U)
+/*! AUDIO_DIV_MSB
+ *  0b0..divide by 1 (Default)
+ *  0b1..divide by 2
+ */
 #define PMU_MISC2_TOG_AUDIO_DIV_MSB(x)           (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_AUDIO_DIV_MSB_SHIFT)) & PMU_MISC2_TOG_AUDIO_DIV_MSB_MASK)
 #define PMU_MISC2_TOG_REG0_STEP_TIME_MASK        (0x3000000U)
 #define PMU_MISC2_TOG_REG0_STEP_TIME_SHIFT       (24U)
+/*! REG0_STEP_TIME
+ *  0b00..64
+ *  0b01..128
+ *  0b10..256
+ *  0b11..512
+ */
 #define PMU_MISC2_TOG_REG0_STEP_TIME(x)          (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_TOG_REG0_STEP_TIME_MASK)
 #define PMU_MISC2_TOG_REG1_STEP_TIME_MASK        (0xC000000U)
 #define PMU_MISC2_TOG_REG1_STEP_TIME_SHIFT       (26U)
+/*! REG1_STEP_TIME
+ *  0b00..64
+ *  0b01..128
+ *  0b10..256
+ *  0b11..512
+ */
 #define PMU_MISC2_TOG_REG1_STEP_TIME(x)          (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_STEP_TIME_SHIFT)) & PMU_MISC2_TOG_REG1_STEP_TIME_MASK)
 #define PMU_MISC2_TOG_REG2_STEP_TIME_MASK        (0x30000000U)
 #define PMU_MISC2_TOG_REG2_STEP_TIME_SHIFT       (28U)
+/*! REG2_STEP_TIME
+ *  0b00..64
+ *  0b01..128
+ *  0b10..256
+ *  0b11..512
+ */
 #define PMU_MISC2_TOG_REG2_STEP_TIME(x)          (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_TOG_REG2_STEP_TIME_MASK)
 #define PMU_MISC2_TOG_VIDEO_DIV_MASK             (0xC0000000U)
 #define PMU_MISC2_TOG_VIDEO_DIV_SHIFT            (30U)
+/*! VIDEO_DIV
+ *  0b00..divide by 1 (Default)
+ *  0b01..divide by 2
+ *  0b10..divide by 1
+ *  0b11..divide by 4
+ */
 #define PMU_MISC2_TOG_VIDEO_DIV(x)               (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_VIDEO_DIV_SHIFT)) & PMU_MISC2_TOG_VIDEO_DIV_MASK)
 /*! @} */
 
@@ -18883,21 +29905,59 @@ typedef struct {
 /*! @{ */
 #define PWM_CTRL2_CLK_SEL_MASK                   (0x3U)
 #define PWM_CTRL2_CLK_SEL_SHIFT                  (0U)
+/*! CLK_SEL - Clock Source Select
+ *  0b00..The IPBus clock is used as the clock for the local prescaler and counter.
+ *  0b01..EXT_CLK is used as the clock for the local prescaler and counter.
+ *  0b10..Submodule 0's clock (AUX_CLK) is used as the source clock for the local prescaler and counter. This
+ *        setting should not be used in submodule 0 as it will force the clock to logic 0.
+ *  0b11..reserved
+ */
 #define PWM_CTRL2_CLK_SEL(x)                     (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_CLK_SEL_SHIFT)) & PWM_CTRL2_CLK_SEL_MASK)
 #define PWM_CTRL2_RELOAD_SEL_MASK                (0x4U)
 #define PWM_CTRL2_RELOAD_SEL_SHIFT               (2U)
+/*! RELOAD_SEL - Reload Source Select
+ *  0b0..The local RELOAD signal is used to reload registers.
+ *  0b1..The master RELOAD signal (from submodule 0) is used to reload registers. This setting should not be used
+ *       in submodule 0 as it will force the RELOAD signal to logic 0.
+ */
 #define PWM_CTRL2_RELOAD_SEL(x)                  (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_RELOAD_SEL_SHIFT)) & PWM_CTRL2_RELOAD_SEL_MASK)
 #define PWM_CTRL2_FORCE_SEL_MASK                 (0x38U)
 #define PWM_CTRL2_FORCE_SEL_SHIFT                (3U)
+/*! FORCE_SEL - This read/write bit determines the source of the FORCE OUTPUT signal for this submodule.
+ *  0b000..The local force signal, CTRL2[FORCE], from this submodule is used to force updates.
+ *  0b001..The master force signal from submodule 0 is used to force updates. This setting should not be used in
+ *         submodule 0 as it will hold the FORCE OUTPUT signal to logic 0.
+ *  0b010..The local reload signal from this submodule is used to force updates without regard to the state of LDOK.
+ *  0b011..The master reload signal from submodule0 is used to force updates if LDOK is set. This setting should
+ *         not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0.
+ *  0b100..The local sync signal from this submodule is used to force updates.
+ *  0b101..The master sync signal from submodule0 is used to force updates. This setting should not be used in
+ *         submodule0 as it will hold the FORCE OUTPUT signal to logic 0.
+ *  0b110..The external force signal, EXT_FORCE, from outside the PWM module causes updates.
+ *  0b111..The external sync signal, EXT_SYNC, from outside the PWM module causes updates.
+ */
 #define PWM_CTRL2_FORCE_SEL(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SEL_SHIFT)) & PWM_CTRL2_FORCE_SEL_MASK)
 #define PWM_CTRL2_FORCE_MASK                     (0x40U)
 #define PWM_CTRL2_FORCE_SHIFT                    (6U)
 #define PWM_CTRL2_FORCE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SHIFT)) & PWM_CTRL2_FORCE_MASK)
 #define PWM_CTRL2_FRCEN_MASK                     (0x80U)
 #define PWM_CTRL2_FRCEN_SHIFT                    (7U)
+/*! FRCEN - FRCEN
+ *  0b0..Initialization from a FORCE_OUT is disabled.
+ *  0b1..Initialization from a FORCE_OUT is enabled.
+ */
 #define PWM_CTRL2_FRCEN(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FRCEN_SHIFT)) & PWM_CTRL2_FRCEN_MASK)
 #define PWM_CTRL2_INIT_SEL_MASK                  (0x300U)
 #define PWM_CTRL2_INIT_SEL_SHIFT                 (8U)
+/*! INIT_SEL - Initialization Control Select
+ *  0b00..Local sync (PWM_X) causes initialization.
+ *  0b01..Master reload from submodule 0 causes initialization. This setting should not be used in submodule 0 as
+ *        it will force the INIT signal to logic 0. The submodule counter will only reinitialize when a master
+ *        reload occurs.
+ *  0b10..Master sync from submodule 0 causes initialization. This setting should not be used in submodule 0 as it
+ *        will force the INIT signal to logic 0.
+ *  0b11..EXT_SYNC causes initialization.
+ */
 #define PWM_CTRL2_INIT_SEL(x)                    (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INIT_SEL_SHIFT)) & PWM_CTRL2_INIT_SEL_MASK)
 #define PWM_CTRL2_PWMX_INIT_MASK                 (0x400U)
 #define PWM_CTRL2_PWMX_INIT_SHIFT                (10U)
@@ -18910,6 +29970,10 @@ typedef struct {
 #define PWM_CTRL2_PWM23_INIT(x)                  (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWM23_INIT_SHIFT)) & PWM_CTRL2_PWM23_INIT_MASK)
 #define PWM_CTRL2_INDEP_MASK                     (0x2000U)
 #define PWM_CTRL2_INDEP_SHIFT                    (13U)
+/*! INDEP - Independent or Complementary Pair Operation
+ *  0b0..PWM_A and PWM_B form a complementary PWM pair.
+ *  0b1..PWM_A and PWM_B outputs are independent PWMs.
+ */
 #define PWM_CTRL2_INDEP(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INDEP_SHIFT)) & PWM_CTRL2_INDEP_MASK)
 #define PWM_CTRL2_WAITEN_MASK                    (0x4000U)
 #define PWM_CTRL2_WAITEN_SHIFT                   (14U)
@@ -18926,33 +29990,96 @@ typedef struct {
 /*! @{ */
 #define PWM_CTRL_DBLEN_MASK                      (0x1U)
 #define PWM_CTRL_DBLEN_SHIFT                     (0U)
+/*! DBLEN - Double Switching Enable
+ *  0b0..Double switching disabled.
+ *  0b1..Double switching enabled.
+ */
 #define PWM_CTRL_DBLEN(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLEN_SHIFT)) & PWM_CTRL_DBLEN_MASK)
 #define PWM_CTRL_DBLX_MASK                       (0x2U)
 #define PWM_CTRL_DBLX_SHIFT                      (1U)
+/*! DBLX - PWMX Double Switching Enable
+ *  0b0..PWMX double pulse disabled.
+ *  0b1..PWMX double pulse enabled.
+ */
 #define PWM_CTRL_DBLX(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLX_SHIFT)) & PWM_CTRL_DBLX_MASK)
 #define PWM_CTRL_LDMOD_MASK                      (0x4U)
 #define PWM_CTRL_LDMOD_SHIFT                     (2U)
+/*! LDMOD - Load Mode Select
+ *  0b0..Buffered registers of this submodule are loaded and take effect at the next PWM reload if MCTRL[LDOK] is set.
+ *  0b1..Buffered registers of this submodule are loaded and take effect immediately upon MCTRL[LDOK] being set.
+ *       In this case it is not necessary to set CTRL[FULL] or CTRL[HALF].
+ */
 #define PWM_CTRL_LDMOD(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDMOD_SHIFT)) & PWM_CTRL_LDMOD_MASK)
 #define PWM_CTRL_SPLIT_MASK                      (0x8U)
 #define PWM_CTRL_SPLIT_SHIFT                     (3U)
+/*! SPLIT - Split the DBLPWM signal to PWMA and PWMB
+ *  0b0..DBLPWM is not split. PWMA and PWMB each have double pulses.
+ *  0b1..DBLPWM is split to PWMA and PWMB.
+ */
 #define PWM_CTRL_SPLIT(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_SPLIT_SHIFT)) & PWM_CTRL_SPLIT_MASK)
 #define PWM_CTRL_PRSC_MASK                       (0x70U)
 #define PWM_CTRL_PRSC_SHIFT                      (4U)
+/*! PRSC - Prescaler
+ *  0b000..PWM clock frequency = fclk
+ *  0b001..PWM clock frequency = fclk/2
+ *  0b010..PWM clock frequency = fclk/4
+ *  0b011..PWM clock frequency = fclk/8
+ *  0b100..PWM clock frequency = fclk/16
+ *  0b101..PWM clock frequency = fclk/32
+ *  0b110..PWM clock frequency = fclk/64
+ *  0b111..PWM clock frequency = fclk/128
+ */
 #define PWM_CTRL_PRSC(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_PRSC_SHIFT)) & PWM_CTRL_PRSC_MASK)
 #define PWM_CTRL_COMPMODE_MASK                   (0x80U)
 #define PWM_CTRL_COMPMODE_SHIFT                  (7U)
+/*! COMPMODE - Compare Mode
+ *  0b0..The VAL* registers and the PWM counter are compared using an "equal to" method. This means that PWM edges
+ *       are only produced when the counter is equal to one of the VAL* register values. This implies that a PWMA
+ *       output that is high at the end of a period will maintain this state until a match with VAL3 clears the
+ *       output in the following period.
+ *  0b1..The VAL* registers and the PWM counter are compared using an "equal to or greater than" method. This
+ *       means that PWM edges are produced when the counter is equal to or greater than one of the VAL* register
+ *       values. This implies that a PWMA output that is high at the end of a period could go low at the start of the
+ *       next period if the starting counter value is greater than (but not necessarily equal to) the new VAL3 value.
+ */
 #define PWM_CTRL_COMPMODE(x)                     (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_COMPMODE_SHIFT)) & PWM_CTRL_COMPMODE_MASK)
 #define PWM_CTRL_DT_MASK                         (0x300U)
 #define PWM_CTRL_DT_SHIFT                        (8U)
 #define PWM_CTRL_DT(x)                           (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DT_SHIFT)) & PWM_CTRL_DT_MASK)
 #define PWM_CTRL_FULL_MASK                       (0x400U)
 #define PWM_CTRL_FULL_SHIFT                      (10U)
+/*! FULL - Full Cycle Reload
+ *  0b0..Full-cycle reloads disabled.
+ *  0b1..Full-cycle reloads enabled.
+ */
 #define PWM_CTRL_FULL(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_FULL_SHIFT)) & PWM_CTRL_FULL_MASK)
 #define PWM_CTRL_HALF_MASK                       (0x800U)
 #define PWM_CTRL_HALF_SHIFT                      (11U)
+/*! HALF - Half Cycle Reload
+ *  0b0..Half-cycle reloads disabled.
+ *  0b1..Half-cycle reloads enabled.
+ */
 #define PWM_CTRL_HALF(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_HALF_SHIFT)) & PWM_CTRL_HALF_MASK)
 #define PWM_CTRL_LDFQ_MASK                       (0xF000U)
 #define PWM_CTRL_LDFQ_SHIFT                      (12U)
+/*! LDFQ - Load Frequency
+ *  0b0000..Every PWM opportunity
+ *  0b0001..Every 2 PWM opportunities
+ *  0b0010..Every 3 PWM opportunities
+ *  0b0011..Every 4 PWM opportunities
+ *  0b0100..Every 5 PWM opportunities
+ *  0b0101..Every 6 PWM opportunities
+ *  0b0110..Every 7 PWM opportunities
+ *  0b0111..Every 8 PWM opportunities
+ *  0b1000..Every 9 PWM opportunities
+ *  0b1001..Every 10 PWM opportunities
+ *  0b1010..Every 11 PWM opportunities
+ *  0b1011..Every 12 PWM opportunities
+ *  0b1100..Every 13 PWM opportunities
+ *  0b1101..Every 14 PWM opportunities
+ *  0b1110..Every 15 PWM opportunities
+ *  0b1111..Every 16 PWM opportunities
+ */
 #define PWM_CTRL_LDFQ(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDFQ_SHIFT)) & PWM_CTRL_LDFQ_MASK)
 /*! @} */
 
@@ -19073,15 +30200,31 @@ typedef struct {
 /*! @{ */
 #define PWM_FRCTRL_FRAC1_EN_MASK                 (0x2U)
 #define PWM_FRCTRL_FRAC1_EN_SHIFT                (1U)
+/*! FRAC1_EN - Fractional Cycle PWM Period Enable
+ *  0b0..Disable fractional cycle length for the PWM period.
+ *  0b1..Enable fractional cycle length for the PWM period.
+ */
 #define PWM_FRCTRL_FRAC1_EN(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC1_EN_SHIFT)) & PWM_FRCTRL_FRAC1_EN_MASK)
 #define PWM_FRCTRL_FRAC23_EN_MASK                (0x4U)
 #define PWM_FRCTRL_FRAC23_EN_SHIFT               (2U)
+/*! FRAC23_EN - Fractional Cycle Placement Enable for PWM_A
+ *  0b0..Disable fractional cycle placement for PWM_A.
+ *  0b1..Enable fractional cycle placement for PWM_A.
+ */
 #define PWM_FRCTRL_FRAC23_EN(x)                  (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC23_EN_SHIFT)) & PWM_FRCTRL_FRAC23_EN_MASK)
 #define PWM_FRCTRL_FRAC45_EN_MASK                (0x10U)
 #define PWM_FRCTRL_FRAC45_EN_SHIFT               (4U)
+/*! FRAC45_EN - Fractional Cycle Placement Enable for PWM_B
+ *  0b0..Disable fractional cycle placement for PWM_B.
+ *  0b1..Enable fractional cycle placement for PWM_B.
+ */
 #define PWM_FRCTRL_FRAC45_EN(x)                  (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC45_EN_SHIFT)) & PWM_FRCTRL_FRAC45_EN_MASK)
 #define PWM_FRCTRL_FRAC_PU_MASK                  (0x100U)
 #define PWM_FRCTRL_FRAC_PU_SHIFT                 (8U)
+/*! FRAC_PU - Fractional Delay Circuit Power Up
+ *  0b0..Turn off fractional delay logic.
+ *  0b1..Power up fractional delay logic.
+ */
 #define PWM_FRCTRL_FRAC_PU(x)                    (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC_PU_SHIFT)) & PWM_FRCTRL_FRAC_PU_MASK)
 #define PWM_FRCTRL_TEST_MASK                     (0x8000U)
 #define PWM_FRCTRL_TEST_SHIFT                    (15U)
@@ -19095,21 +30238,51 @@ typedef struct {
 /*! @{ */
 #define PWM_OCTRL_PWMXFS_MASK                    (0x3U)
 #define PWM_OCTRL_PWMXFS_SHIFT                   (0U)
+/*! PWMXFS - PWM_X Fault State
+ *  0b00..Output is forced to logic 0 state prior to consideration of output polarity control.
+ *  0b01..Output is forced to logic 1 state prior to consideration of output polarity control.
+ *  0b10..Output is tristated.
+ *  0b11..Output is tristated.
+ */
 #define PWM_OCTRL_PWMXFS(x)                      (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMXFS_SHIFT)) & PWM_OCTRL_PWMXFS_MASK)
 #define PWM_OCTRL_PWMBFS_MASK                    (0xCU)
 #define PWM_OCTRL_PWMBFS_SHIFT                   (2U)
+/*! PWMBFS - PWM_B Fault State
+ *  0b00..Output is forced to logic 0 state prior to consideration of output polarity control.
+ *  0b01..Output is forced to logic 1 state prior to consideration of output polarity control.
+ *  0b10..Output is tristated.
+ *  0b11..Output is tristated.
+ */
 #define PWM_OCTRL_PWMBFS(x)                      (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMBFS_SHIFT)) & PWM_OCTRL_PWMBFS_MASK)
 #define PWM_OCTRL_PWMAFS_MASK                    (0x30U)
 #define PWM_OCTRL_PWMAFS_SHIFT                   (4U)
+/*! PWMAFS - PWM_A Fault State
+ *  0b00..Output is forced to logic 0 state prior to consideration of output polarity control.
+ *  0b01..Output is forced to logic 1 state prior to consideration of output polarity control.
+ *  0b10..Output is tristated.
+ *  0b11..Output is tristated.
+ */
 #define PWM_OCTRL_PWMAFS(x)                      (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMAFS_SHIFT)) & PWM_OCTRL_PWMAFS_MASK)
 #define PWM_OCTRL_POLX_MASK                      (0x100U)
 #define PWM_OCTRL_POLX_SHIFT                     (8U)
+/*! POLX - PWM_X Output Polarity
+ *  0b0..PWM_X output not inverted. A high level on the PWM_X pin represents the "on" or "active" state.
+ *  0b1..PWM_X output inverted. A low level on the PWM_X pin represents the "on" or "active" state.
+ */
 #define PWM_OCTRL_POLX(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLX_SHIFT)) & PWM_OCTRL_POLX_MASK)
 #define PWM_OCTRL_POLB_MASK                      (0x200U)
 #define PWM_OCTRL_POLB_SHIFT                     (9U)
+/*! POLB - PWM_B Output Polarity
+ *  0b0..PWM_B output not inverted. A high level on the PWM_B pin represents the "on" or "active" state.
+ *  0b1..PWM_B output inverted. A low level on the PWM_B pin represents the "on" or "active" state.
+ */
 #define PWM_OCTRL_POLB(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLB_SHIFT)) & PWM_OCTRL_POLB_MASK)
 #define PWM_OCTRL_POLA_MASK                      (0x400U)
 #define PWM_OCTRL_POLA_SHIFT                     (10U)
+/*! POLA - PWM_A Output Polarity
+ *  0b0..PWM_A output not inverted. A high level on the PWM_A pin represents the "on" or "active" state.
+ *  0b1..PWM_A output inverted. A low level on the PWM_A pin represents the "on" or "active" state.
+ */
 #define PWM_OCTRL_POLA(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLA_SHIFT)) & PWM_OCTRL_POLA_MASK)
 #define PWM_OCTRL_PWMX_IN_MASK                   (0x2000U)
 #define PWM_OCTRL_PWMX_IN_SHIFT                  (13U)
@@ -19129,6 +30302,10 @@ typedef struct {
 /*! @{ */
 #define PWM_STS_CMPF_MASK                        (0x3FU)
 #define PWM_STS_CMPF_SHIFT                       (0U)
+/*! CMPF - Compare Flags
+ *  0b000000..No compare event has occurred for a particular VALx value.
+ *  0b000001..A compare event has occurred for a particular VALx value.
+ */
 #define PWM_STS_CMPF(x)                          (((uint16_t)(((uint16_t)(x)) << PWM_STS_CMPF_SHIFT)) & PWM_STS_CMPF_MASK)
 #define PWM_STS_CFX0_MASK                        (0x40U)
 #define PWM_STS_CFX0_SHIFT                       (6U)
@@ -19150,12 +30327,24 @@ typedef struct {
 #define PWM_STS_CFA1(x)                          (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFA1_SHIFT)) & PWM_STS_CFA1_MASK)
 #define PWM_STS_RF_MASK                          (0x1000U)
 #define PWM_STS_RF_SHIFT                         (12U)
+/*! RF - Reload Flag
+ *  0b0..No new reload cycle since last STS[RF] clearing
+ *  0b1..New reload cycle since last STS[RF] clearing
+ */
 #define PWM_STS_RF(x)                            (((uint16_t)(((uint16_t)(x)) << PWM_STS_RF_SHIFT)) & PWM_STS_RF_MASK)
 #define PWM_STS_REF_MASK                         (0x2000U)
 #define PWM_STS_REF_SHIFT                        (13U)
+/*! REF - Reload Error Flag
+ *  0b0..No reload error occurred.
+ *  0b1..Reload signal occurred with non-coherent data and MCTRL[LDOK] = 0.
+ */
 #define PWM_STS_REF(x)                           (((uint16_t)(((uint16_t)(x)) << PWM_STS_REF_SHIFT)) & PWM_STS_REF_MASK)
 #define PWM_STS_RUF_MASK                         (0x4000U)
 #define PWM_STS_RUF_SHIFT                        (14U)
+/*! RUF - Registers Updated Flag
+ *  0b0..No register update has occurred since last reload.
+ *  0b1..At least one of the double buffered registers has been updated since the last reload.
+ */
 #define PWM_STS_RUF(x)                           (((uint16_t)(((uint16_t)(x)) << PWM_STS_RUF_SHIFT)) & PWM_STS_RUF_MASK)
 /*! @} */
 
@@ -19166,30 +30355,66 @@ typedef struct {
 /*! @{ */
 #define PWM_INTEN_CMPIE_MASK                     (0x3FU)
 #define PWM_INTEN_CMPIE_SHIFT                    (0U)
+/*! CMPIE - Compare Interrupt Enables
+ *  0b000000..The corresponding STS[CMPF] bit will not cause an interrupt request.
+ *  0b000001..The corresponding STS[CMPF] bit will cause an interrupt request.
+ */
 #define PWM_INTEN_CMPIE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CMPIE_SHIFT)) & PWM_INTEN_CMPIE_MASK)
 #define PWM_INTEN_CX0IE_MASK                     (0x40U)
 #define PWM_INTEN_CX0IE_SHIFT                    (6U)
+/*! CX0IE - Capture X 0 Interrupt Enable
+ *  0b0..Interrupt request disabled for STS[CFX0].
+ *  0b1..Interrupt request enabled for STS[CFX0].
+ */
 #define PWM_INTEN_CX0IE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CX0IE_SHIFT)) & PWM_INTEN_CX0IE_MASK)
 #define PWM_INTEN_CX1IE_MASK                     (0x80U)
 #define PWM_INTEN_CX1IE_SHIFT                    (7U)
+/*! CX1IE - Capture X 1 Interrupt Enable
+ *  0b0..Interrupt request disabled for STS[CFX1].
+ *  0b1..Interrupt request enabled for STS[CFX1].
+ */
 #define PWM_INTEN_CX1IE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CX1IE_SHIFT)) & PWM_INTEN_CX1IE_MASK)
 #define PWM_INTEN_CB0IE_MASK                     (0x100U)
 #define PWM_INTEN_CB0IE_SHIFT                    (8U)
+/*! CB0IE - Capture B 0 Interrupt Enable
+ *  0b0..Interrupt request disabled for STS[CFB0].
+ *  0b1..Interrupt request enabled for STS[CFB0].
+ */
 #define PWM_INTEN_CB0IE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CB0IE_SHIFT)) & PWM_INTEN_CB0IE_MASK)
 #define PWM_INTEN_CB1IE_MASK                     (0x200U)
 #define PWM_INTEN_CB1IE_SHIFT                    (9U)
+/*! CB1IE - Capture B 1 Interrupt Enable
+ *  0b0..Interrupt request disabled for STS[CFB1].
+ *  0b1..Interrupt request enabled for STS[CFB1].
+ */
 #define PWM_INTEN_CB1IE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CB1IE_SHIFT)) & PWM_INTEN_CB1IE_MASK)
 #define PWM_INTEN_CA0IE_MASK                     (0x400U)
 #define PWM_INTEN_CA0IE_SHIFT                    (10U)
+/*! CA0IE - Capture A 0 Interrupt Enable
+ *  0b0..Interrupt request disabled for STS[CFA0].
+ *  0b1..Interrupt request enabled for STS[CFA0].
+ */
 #define PWM_INTEN_CA0IE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CA0IE_SHIFT)) & PWM_INTEN_CA0IE_MASK)
 #define PWM_INTEN_CA1IE_MASK                     (0x800U)
 #define PWM_INTEN_CA1IE_SHIFT                    (11U)
+/*! CA1IE - Capture A 1 Interrupt Enable
+ *  0b0..Interrupt request disabled for STS[CFA1].
+ *  0b1..Interrupt request enabled for STS[CFA1].
+ */
 #define PWM_INTEN_CA1IE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CA1IE_SHIFT)) & PWM_INTEN_CA1IE_MASK)
 #define PWM_INTEN_RIE_MASK                       (0x1000U)
 #define PWM_INTEN_RIE_SHIFT                      (12U)
+/*! RIE - Reload Interrupt Enable
+ *  0b0..STS[RF] CPU interrupt requests disabled
+ *  0b1..STS[RF] CPU interrupt requests enabled
+ */
 #define PWM_INTEN_RIE(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_RIE_SHIFT)) & PWM_INTEN_RIE_MASK)
 #define PWM_INTEN_REIE_MASK                      (0x2000U)
 #define PWM_INTEN_REIE_SHIFT                     (13U)
+/*! REIE - Reload Error Interrupt Enable
+ *  0b0..STS[REF] CPU interrupt requests disabled
+ *  0b1..STS[REF] CPU interrupt requests enabled
+ */
 #define PWM_INTEN_REIE(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_REIE_SHIFT)) & PWM_INTEN_REIE_MASK)
 /*! @} */
 
@@ -19218,12 +30443,28 @@ typedef struct {
 #define PWM_DMAEN_CA1DE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CA1DE_SHIFT)) & PWM_DMAEN_CA1DE_MASK)
 #define PWM_DMAEN_CAPTDE_MASK                    (0xC0U)
 #define PWM_DMAEN_CAPTDE_SHIFT                   (6U)
+/*! CAPTDE - Capture DMA Enable Source Select
+ *  0b00..Read DMA requests disabled.
+ *  0b01..Exceeding a FIFO watermark sets the DMA read request. This requires at least one of DMAEN[CA1DE],
+ *        DMAEN[CA0DE], DMAEN[CB1DE], DMAEN[CB0DE], DMAEN[CX1DE], or DMAEN[CX0DE] to also be set in order to determine to
+ *        which watermark(s) the DMA request is sensitive.
+ *  0b10..A local sync (VAL1 matches counter) sets the read DMA request.
+ *  0b11..A local reload (STS[RF] being set) sets the read DMA request.
+ */
 #define PWM_DMAEN_CAPTDE(x)                      (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CAPTDE_SHIFT)) & PWM_DMAEN_CAPTDE_MASK)
 #define PWM_DMAEN_FAND_MASK                      (0x100U)
 #define PWM_DMAEN_FAND_SHIFT                     (8U)
+/*! FAND - FIFO Watermark AND Control
+ *  0b0..Selected FIFO watermarks are OR'ed together.
+ *  0b1..Selected FIFO watermarks are AND'ed together.
+ */
 #define PWM_DMAEN_FAND(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_FAND_SHIFT)) & PWM_DMAEN_FAND_MASK)
 #define PWM_DMAEN_VALDE_MASK                     (0x200U)
 #define PWM_DMAEN_VALDE_SHIFT                    (9U)
+/*! VALDE - Value Registers DMA Enable
+ *  0b0..DMA write requests disabled
+ *  0b1..DMA write requests for the VALx and FRACVALx registers enabled
+ */
 #define PWM_DMAEN_VALDE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_VALDE_SHIFT)) & PWM_DMAEN_VALDE_MASK)
 /*! @} */
 
@@ -19234,15 +30475,32 @@ typedef struct {
 /*! @{ */
 #define PWM_TCTRL_OUT_TRIG_EN_MASK               (0x3FU)
 #define PWM_TCTRL_OUT_TRIG_EN_SHIFT              (0U)
+/*! OUT_TRIG_EN - Output Trigger Enables
+ *  0b000000..PWM_OUT_TRIGx will not set when the counter value matches the VALx value.
+ *  0b000001..PWM_OUT_TRIGx will set when the counter value matches the VALx value.
+ */
 #define PWM_TCTRL_OUT_TRIG_EN(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_OUT_TRIG_EN_SHIFT)) & PWM_TCTRL_OUT_TRIG_EN_MASK)
 #define PWM_TCTRL_TRGFRQ_MASK                    (0x1000U)
 #define PWM_TCTRL_TRGFRQ_SHIFT                   (12U)
+/*! TRGFRQ - Trigger frequency
+ *  0b0..Trigger outputs are generated during every PWM period even if the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero.
+ *  0b1..Trigger outputs are generated only during the final PWM period prior to a reload opportunity when the PWM
+ *       is not reloaded every period due to CTRL[LDFQ] being non-zero.
+ */
 #define PWM_TCTRL_TRGFRQ(x)                      (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_TRGFRQ_SHIFT)) & PWM_TCTRL_TRGFRQ_MASK)
 #define PWM_TCTRL_PWBOT1_MASK                    (0x4000U)
 #define PWM_TCTRL_PWBOT1_SHIFT                   (14U)
+/*! PWBOT1 - Output Trigger 1 Source Select
+ *  0b0..Route the PWM_OUT_TRIG1 signal to PWM_OUT_TRIG1 port.
+ *  0b1..Route the PWMB output to the PWM_OUT_TRIG1 port.
+ */
 #define PWM_TCTRL_PWBOT1(x)                      (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_PWBOT1_SHIFT)) & PWM_TCTRL_PWBOT1_MASK)
 #define PWM_TCTRL_PWAOT0_MASK                    (0x8000U)
 #define PWM_TCTRL_PWAOT0_SHIFT                   (15U)
+/*! PWAOT0 - Output Trigger 0 Source Select
+ *  0b0..Route the PWM_OUT_TRIG0 signal to PWM_OUT_TRIG0 port.
+ *  0b1..Route the PWMA output to the PWM_OUT_TRIG0 port.
+ */
 #define PWM_TCTRL_PWAOT0(x)                      (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_PWAOT0_SHIFT)) & PWM_TCTRL_PWAOT0_MASK)
 /*! @} */
 
@@ -19301,21 +30559,60 @@ typedef struct {
 /*! @{ */
 #define PWM_CAPTCTRLA_ARMA_MASK                  (0x1U)
 #define PWM_CAPTCTRLA_ARMA_SHIFT                 (0U)
+/*! ARMA - Arm A
+ *  0b0..Input capture operation is disabled.
+ *  0b1..Input capture operation as specified by CAPTCTRLA[EDGAx] is enabled.
+ */
 #define PWM_CAPTCTRLA_ARMA(x)                    (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_ARMA_SHIFT)) & PWM_CAPTCTRLA_ARMA_MASK)
 #define PWM_CAPTCTRLA_ONESHOTA_MASK              (0x2U)
 #define PWM_CAPTCTRLA_ONESHOTA_SHIFT             (1U)
+/*! ONESHOTA - One Shot Mode A
+ *  0b0..Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed
+ *       first after CAPTCTRLA[ARMA] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1
+ *       is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed.
+ *       The process continues indefinitely.If only one of the capture circuits is enabled, then captures continue
+ *       indefinitely on the enabled capture circuit.
+ *  0b1..One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first
+ *       after CAPTCTRLA[ARMA] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is
+ *       armed. After capture circuit 1 performs a capture, it is disarmed and CAPTCTRLA[ARMA] is cleared. No
+ *       further captures will be performed until CAPTCTRLA[ARMA] is set again.If only one of the capture circuits is
+ *       enabled, then a single capture will occur on the enabled capture circuit and CAPTCTRLA[ARMA] is then cleared.
+ */
 #define PWM_CAPTCTRLA_ONESHOTA(x)                (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_ONESHOTA_SHIFT)) & PWM_CAPTCTRLA_ONESHOTA_MASK)
 #define PWM_CAPTCTRLA_EDGA0_MASK                 (0xCU)
 #define PWM_CAPTCTRLA_EDGA0_SHIFT                (2U)
+/*! EDGA0 - Edge A 0
+ *  0b00..Disabled
+ *  0b01..Capture falling edges
+ *  0b10..Capture rising edges
+ *  0b11..Capture any edge
+ */
 #define PWM_CAPTCTRLA_EDGA0(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGA0_SHIFT)) & PWM_CAPTCTRLA_EDGA0_MASK)
 #define PWM_CAPTCTRLA_EDGA1_MASK                 (0x30U)
 #define PWM_CAPTCTRLA_EDGA1_SHIFT                (4U)
+/*! EDGA1 - Edge A 1
+ *  0b00..Disabled
+ *  0b01..Capture falling edges
+ *  0b10..Capture rising edges
+ *  0b11..Capture any edge
+ */
 #define PWM_CAPTCTRLA_EDGA1(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGA1_SHIFT)) & PWM_CAPTCTRLA_EDGA1_MASK)
 #define PWM_CAPTCTRLA_INP_SELA_MASK              (0x40U)
 #define PWM_CAPTCTRLA_INP_SELA_SHIFT             (6U)
+/*! INP_SELA - Input Select A
+ *  0b0..Raw PWM_A input signal selected as source.
+ *  0b1..Output of edge counter/compare selected as source. Note that when this bitfield is set to 1, the internal
+ *       edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLA[EDGA0] and
+ *       CAPTCTRLA[EDGA1] fields are ignored. The software must still place a value other than 00 in either or both of the
+ *       CAPTCTLRA[EDGA0] and/or CAPTCTRLA[EDGA1] fields in order to enable one or both of the capture registers.
+ */
 #define PWM_CAPTCTRLA_INP_SELA(x)                (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_INP_SELA_SHIFT)) & PWM_CAPTCTRLA_INP_SELA_MASK)
 #define PWM_CAPTCTRLA_EDGCNTA_EN_MASK            (0x80U)
 #define PWM_CAPTCTRLA_EDGCNTA_EN_SHIFT           (7U)
+/*! EDGCNTA_EN - Edge Counter A Enable
+ *  0b0..Edge counter disabled and held in reset
+ *  0b1..Edge counter enabled
+ */
 #define PWM_CAPTCTRLA_EDGCNTA_EN(x)              (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGCNTA_EN_SHIFT)) & PWM_CAPTCTRLA_EDGCNTA_EN_MASK)
 #define PWM_CAPTCTRLA_CFAWM_MASK                 (0x300U)
 #define PWM_CAPTCTRLA_CFAWM_SHIFT                (8U)
@@ -19348,21 +30645,60 @@ typedef struct {
 /*! @{ */
 #define PWM_CAPTCTRLB_ARMB_MASK                  (0x1U)
 #define PWM_CAPTCTRLB_ARMB_SHIFT                 (0U)
+/*! ARMB - Arm B
+ *  0b0..Input capture operation is disabled.
+ *  0b1..Input capture operation as specified by CAPTCTRLB[EDGBx] is enabled.
+ */
 #define PWM_CAPTCTRLB_ARMB(x)                    (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_ARMB_SHIFT)) & PWM_CAPTCTRLB_ARMB_MASK)
 #define PWM_CAPTCTRLB_ONESHOTB_MASK              (0x2U)
 #define PWM_CAPTCTRLB_ONESHOTB_SHIFT             (1U)
+/*! ONESHOTB - One Shot Mode B
+ *  0b0..Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed
+ *       first after CAPTCTRLB[ARMB] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1
+ *       is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed.
+ *       The process continues indefinitely.If only one of the capture circuits is enabled, then captures continue
+ *       indefinitely on the enabled capture circuit.
+ *  0b1..One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first
+ *       after CAPTCTRLB[ARMB] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is
+ *       armed. After capture circuit 1 performs a capture, it is disarmed and CAPTCTRLB[ARMB] is cleared. No
+ *       further captures will be performed until CAPTCTRLB[ARMB] is set again.If only one of the capture circuits is
+ *       enabled, then a single capture will occur on the enabled capture circuit and CAPTCTRLB[ARMB] is then cleared.
+ */
 #define PWM_CAPTCTRLB_ONESHOTB(x)                (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_ONESHOTB_SHIFT)) & PWM_CAPTCTRLB_ONESHOTB_MASK)
 #define PWM_CAPTCTRLB_EDGB0_MASK                 (0xCU)
 #define PWM_CAPTCTRLB_EDGB0_SHIFT                (2U)
+/*! EDGB0 - Edge B 0
+ *  0b00..Disabled
+ *  0b01..Capture falling edges
+ *  0b10..Capture rising edges
+ *  0b11..Capture any edge
+ */
 #define PWM_CAPTCTRLB_EDGB0(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGB0_SHIFT)) & PWM_CAPTCTRLB_EDGB0_MASK)
 #define PWM_CAPTCTRLB_EDGB1_MASK                 (0x30U)
 #define PWM_CAPTCTRLB_EDGB1_SHIFT                (4U)
+/*! EDGB1 - Edge B 1
+ *  0b00..Disabled
+ *  0b01..Capture falling edges
+ *  0b10..Capture rising edges
+ *  0b11..Capture any edge
+ */
 #define PWM_CAPTCTRLB_EDGB1(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGB1_SHIFT)) & PWM_CAPTCTRLB_EDGB1_MASK)
 #define PWM_CAPTCTRLB_INP_SELB_MASK              (0x40U)
 #define PWM_CAPTCTRLB_INP_SELB_SHIFT             (6U)
+/*! INP_SELB - Input Select B
+ *  0b0..Raw PWM_B input signal selected as source.
+ *  0b1..Output of edge counter/compare selected as source. Note that when this bitfield is set to 1, the internal
+ *       edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLB[EDGB0] and
+ *       CAPTCTRLB[EDGB1] fields are ignored. The software must still place a value other than 00 in either or both of the
+ *       CAPTCTLRB[EDGB0] and/or CAPTCTRLB[EDGB1] fields in order to enable one or both of the capture registers.
+ */
 #define PWM_CAPTCTRLB_INP_SELB(x)                (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_INP_SELB_SHIFT)) & PWM_CAPTCTRLB_INP_SELB_MASK)
 #define PWM_CAPTCTRLB_EDGCNTB_EN_MASK            (0x80U)
 #define PWM_CAPTCTRLB_EDGCNTB_EN_SHIFT           (7U)
+/*! EDGCNTB_EN - Edge Counter B Enable
+ *  0b0..Edge counter disabled and held in reset
+ *  0b1..Edge counter enabled
+ */
 #define PWM_CAPTCTRLB_EDGCNTB_EN(x)              (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGCNTB_EN_SHIFT)) & PWM_CAPTCTRLB_EDGCNTB_EN_MASK)
 #define PWM_CAPTCTRLB_CFBWM_MASK                 (0x300U)
 #define PWM_CAPTCTRLB_CFBWM_SHIFT                (8U)
@@ -19395,21 +30731,60 @@ typedef struct {
 /*! @{ */
 #define PWM_CAPTCTRLX_ARMX_MASK                  (0x1U)
 #define PWM_CAPTCTRLX_ARMX_SHIFT                 (0U)
+/*! ARMX - Arm X
+ *  0b0..Input capture operation is disabled.
+ *  0b1..Input capture operation as specified by CAPTCTRLX[EDGXx] is enabled.
+ */
 #define PWM_CAPTCTRLX_ARMX(x)                    (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_ARMX_SHIFT)) & PWM_CAPTCTRLX_ARMX_MASK)
 #define PWM_CAPTCTRLX_ONESHOTX_MASK              (0x2U)
 #define PWM_CAPTCTRLX_ONESHOTX_SHIFT             (1U)
+/*! ONESHOTX - One Shot Mode Aux
+ *  0b0..Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed
+ *       first after the ARMX bit is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is
+ *       armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The
+ *       process continues indefinitely.If only one of the capture circuits is enabled, then captures continue
+ *       indefinitely on the enabled capture circuit.
+ *  0b1..One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first
+ *       after the ARMX bit is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is
+ *       armed. After capture circuit 1 performs a capture, it is disarmed and the ARMX bit is cleared. No further
+ *       captures will be performed until the ARMX bit is set again.If only one of the capture circuits is enabled,
+ *       then a single capture will occur on the enabled capture circuit and the ARMX bit is then cleared.
+ */
 #define PWM_CAPTCTRLX_ONESHOTX(x)                (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_ONESHOTX_SHIFT)) & PWM_CAPTCTRLX_ONESHOTX_MASK)
 #define PWM_CAPTCTRLX_EDGX0_MASK                 (0xCU)
 #define PWM_CAPTCTRLX_EDGX0_SHIFT                (2U)
+/*! EDGX0 - Edge X 0
+ *  0b00..Disabled
+ *  0b01..Capture falling edges
+ *  0b10..Capture rising edges
+ *  0b11..Capture any edge
+ */
 #define PWM_CAPTCTRLX_EDGX0(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGX0_SHIFT)) & PWM_CAPTCTRLX_EDGX0_MASK)
 #define PWM_CAPTCTRLX_EDGX1_MASK                 (0x30U)
 #define PWM_CAPTCTRLX_EDGX1_SHIFT                (4U)
+/*! EDGX1 - Edge X 1
+ *  0b00..Disabled
+ *  0b01..Capture falling edges
+ *  0b10..Capture rising edges
+ *  0b11..Capture any edge
+ */
 #define PWM_CAPTCTRLX_EDGX1(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGX1_SHIFT)) & PWM_CAPTCTRLX_EDGX1_MASK)
 #define PWM_CAPTCTRLX_INP_SELX_MASK              (0x40U)
 #define PWM_CAPTCTRLX_INP_SELX_SHIFT             (6U)
+/*! INP_SELX - Input Select X
+ *  0b0..Raw PWM_X input signal selected as source.
+ *  0b1..Output of edge counter/compare selected as source. Note that when this bitfield is set to 1, the internal
+ *       edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLX[EDGX0] and
+ *       CAPTCTRLX[EDGX1] fields are ignored. The software must still place a value other than 00 in either or both of the
+ *       CAPTCTLRX[EDGX0] and/or CAPTCTRLX[EDGX1] fields in order to enable one or both of the capture registers.
+ */
 #define PWM_CAPTCTRLX_INP_SELX(x)                (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_INP_SELX_SHIFT)) & PWM_CAPTCTRLX_INP_SELX_MASK)
 #define PWM_CAPTCTRLX_EDGCNTX_EN_MASK            (0x80U)
 #define PWM_CAPTCTRLX_EDGCNTX_EN_SHIFT           (7U)
+/*! EDGCNTX_EN - Edge Counter X Enable
+ *  0b0..Edge counter disabled and held in reset
+ *  0b1..Edge counter enabled
+ */
 #define PWM_CAPTCTRLX_EDGCNTX_EN(x)              (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGCNTX_EN_SHIFT)) & PWM_CAPTCTRLX_EDGCNTX_EN_MASK)
 #define PWM_CAPTCTRLX_CFXWM_MASK                 (0x300U)
 #define PWM_CAPTCTRLX_CFXWM_SHIFT                (8U)
@@ -19562,12 +30937,24 @@ typedef struct {
 /*! @{ */
 #define PWM_OUTEN_PWMX_EN_MASK                   (0xFU)
 #define PWM_OUTEN_PWMX_EN_SHIFT                  (0U)
+/*! PWMX_EN - PWM_X Output Enables
+ *  0b0000..PWM_X output disabled.
+ *  0b0001..PWM_X output enabled.
+ */
 #define PWM_OUTEN_PWMX_EN(x)                     (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMX_EN_SHIFT)) & PWM_OUTEN_PWMX_EN_MASK)
 #define PWM_OUTEN_PWMB_EN_MASK                   (0xF0U)
 #define PWM_OUTEN_PWMB_EN_SHIFT                  (4U)
+/*! PWMB_EN - PWM_B Output Enables
+ *  0b0000..PWM_B output disabled.
+ *  0b0001..PWM_B output enabled.
+ */
 #define PWM_OUTEN_PWMB_EN(x)                     (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMB_EN_SHIFT)) & PWM_OUTEN_PWMB_EN_MASK)
 #define PWM_OUTEN_PWMA_EN_MASK                   (0xF00U)
 #define PWM_OUTEN_PWMA_EN_SHIFT                  (8U)
+/*! PWMA_EN - PWM_A Output Enables
+ *  0b0000..PWM_A output disabled.
+ *  0b0001..PWM_A output enabled.
+ */
 #define PWM_OUTEN_PWMA_EN(x)                     (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMA_EN_SHIFT)) & PWM_OUTEN_PWMA_EN_MASK)
 /*! @} */
 
@@ -19575,15 +30962,31 @@ typedef struct {
 /*! @{ */
 #define PWM_MASK_MASKX_MASK                      (0xFU)
 #define PWM_MASK_MASKX_SHIFT                     (0U)
+/*! MASKX - PWM_X Masks
+ *  0b0000..PWM_X output normal.
+ *  0b0001..PWM_X output masked.
+ */
 #define PWM_MASK_MASKX(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKX_SHIFT)) & PWM_MASK_MASKX_MASK)
 #define PWM_MASK_MASKB_MASK                      (0xF0U)
 #define PWM_MASK_MASKB_SHIFT                     (4U)
+/*! MASKB - PWM_B Masks
+ *  0b0000..PWM_B output normal.
+ *  0b0001..PWM_B output masked.
+ */
 #define PWM_MASK_MASKB(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKB_SHIFT)) & PWM_MASK_MASKB_MASK)
 #define PWM_MASK_MASKA_MASK                      (0xF00U)
 #define PWM_MASK_MASKA_SHIFT                     (8U)
+/*! MASKA - PWM_A Masks
+ *  0b0000..PWM_A output normal.
+ *  0b0001..PWM_A output masked.
+ */
 #define PWM_MASK_MASKA(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKA_SHIFT)) & PWM_MASK_MASKA_MASK)
 #define PWM_MASK_UPDATE_MASK_MASK                (0xF000U)
 #define PWM_MASK_UPDATE_MASK_SHIFT               (12U)
+/*! UPDATE_MASK - Update Mask Bits Immediately
+ *  0b0000..Normal operation. MASK* bits within the corresponding submodule are not updated until a FORCE_OUT event occurs within the submodule.
+ *  0b0001..Immediate operation. MASK* bits within the corresponding submodule are updated on the following clock edge after setting this bit.
+ */
 #define PWM_MASK_UPDATE_MASK(x)                  (((uint16_t)(((uint16_t)(x)) << PWM_MASK_UPDATE_MASK_SHIFT)) & PWM_MASK_UPDATE_MASK_MASK)
 /*! @} */
 
@@ -19591,27 +30994,59 @@ typedef struct {
 /*! @{ */
 #define PWM_SWCOUT_SM0OUT45_MASK                 (0x1U)
 #define PWM_SWCOUT_SM0OUT45_SHIFT                (0U)
+/*! SM0OUT45 - Submodule 0 Software Controlled Output 45
+ *  0b0..A logic 0 is supplied to the deadtime generator of submodule 0 instead of PWM45.
+ *  0b1..A logic 1 is supplied to the deadtime generator of submodule 0 instead of PWM45.
+ */
 #define PWM_SWCOUT_SM0OUT45(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM0OUT45_SHIFT)) & PWM_SWCOUT_SM0OUT45_MASK)
 #define PWM_SWCOUT_SM0OUT23_MASK                 (0x2U)
 #define PWM_SWCOUT_SM0OUT23_SHIFT                (1U)
+/*! SM0OUT23 - Submodule 0 Software Controlled Output 23
+ *  0b0..A logic 0 is supplied to the deadtime generator of submodule 0 instead of PWM23.
+ *  0b1..A logic 1 is supplied to the deadtime generator of submodule 0 instead of PWM23.
+ */
 #define PWM_SWCOUT_SM0OUT23(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM0OUT23_SHIFT)) & PWM_SWCOUT_SM0OUT23_MASK)
 #define PWM_SWCOUT_SM1OUT45_MASK                 (0x4U)
 #define PWM_SWCOUT_SM1OUT45_SHIFT                (2U)
+/*! SM1OUT45 - Submodule 1 Software Controlled Output 45
+ *  0b0..A logic 0 is supplied to the deadtime generator of submodule 1 instead of PWM45.
+ *  0b1..A logic 1 is supplied to the deadtime generator of submodule 1 instead of PWM45.
+ */
 #define PWM_SWCOUT_SM1OUT45(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM1OUT45_SHIFT)) & PWM_SWCOUT_SM1OUT45_MASK)
 #define PWM_SWCOUT_SM1OUT23_MASK                 (0x8U)
 #define PWM_SWCOUT_SM1OUT23_SHIFT                (3U)
+/*! SM1OUT23 - Submodule 1 Software Controlled Output 23
+ *  0b0..A logic 0 is supplied to the deadtime generator of submodule 1 instead of PWM23.
+ *  0b1..A logic 1 is supplied to the deadtime generator of submodule 1 instead of PWM23.
+ */
 #define PWM_SWCOUT_SM1OUT23(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM1OUT23_SHIFT)) & PWM_SWCOUT_SM1OUT23_MASK)
 #define PWM_SWCOUT_SM2OUT45_MASK                 (0x10U)
 #define PWM_SWCOUT_SM2OUT45_SHIFT                (4U)
+/*! SM2OUT45 - Submodule 2 Software Controlled Output 45
+ *  0b0..A logic 0 is supplied to the deadtime generator of submodule 2 instead of PWM45.
+ *  0b1..A logic 1 is supplied to the deadtime generator of submodule 2 instead of PWM45.
+ */
 #define PWM_SWCOUT_SM2OUT45(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM2OUT45_SHIFT)) & PWM_SWCOUT_SM2OUT45_MASK)
 #define PWM_SWCOUT_SM2OUT23_MASK                 (0x20U)
 #define PWM_SWCOUT_SM2OUT23_SHIFT                (5U)
+/*! SM2OUT23 - Submodule 2 Software Controlled Output 23
+ *  0b0..A logic 0 is supplied to the deadtime generator of submodule 2 instead of PWM23.
+ *  0b1..A logic 1 is supplied to the deadtime generator of submodule 2 instead of PWM23.
+ */
 #define PWM_SWCOUT_SM2OUT23(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM2OUT23_SHIFT)) & PWM_SWCOUT_SM2OUT23_MASK)
 #define PWM_SWCOUT_SM3OUT45_MASK                 (0x40U)
 #define PWM_SWCOUT_SM3OUT45_SHIFT                (6U)
+/*! SM3OUT45 - Submodule 3 Software Controlled Output 45
+ *  0b0..A logic 0 is supplied to the deadtime generator of submodule 3 instead of PWM45.
+ *  0b1..A logic 1 is supplied to the deadtime generator of submodule 3 instead of PWM45.
+ */
 #define PWM_SWCOUT_SM3OUT45(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM3OUT45_SHIFT)) & PWM_SWCOUT_SM3OUT45_MASK)
 #define PWM_SWCOUT_SM3OUT23_MASK                 (0x80U)
 #define PWM_SWCOUT_SM3OUT23_SHIFT                (7U)
+/*! SM3OUT23 - Submodule 3 Software Controlled Output 23
+ *  0b0..A logic 0 is supplied to the deadtime generator of submodule 3 instead of PWM23.
+ *  0b1..A logic 1 is supplied to the deadtime generator of submodule 3 instead of PWM23.
+ */
 #define PWM_SWCOUT_SM3OUT23(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM3OUT23_SHIFT)) & PWM_SWCOUT_SM3OUT23_MASK)
 /*! @} */
 
@@ -19619,27 +31054,75 @@ typedef struct {
 /*! @{ */
 #define PWM_DTSRCSEL_SM0SEL45_MASK               (0x3U)
 #define PWM_DTSRCSEL_SM0SEL45_SHIFT              (0U)
+/*! SM0SEL45 - Submodule 0 PWM45 Control Select
+ *  0b00..Generated SM0PWM45 signal is used by the deadtime logic.
+ *  0b01..Inverted generated SM0PWM45 signal is used by the deadtime logic.
+ *  0b10..SWCOUT[SM0OUT45] is used by the deadtime logic.
+ *  0b11..PWM0_EXTB signal is used by the deadtime logic.
+ */
 #define PWM_DTSRCSEL_SM0SEL45(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM0SEL45_SHIFT)) & PWM_DTSRCSEL_SM0SEL45_MASK)
 #define PWM_DTSRCSEL_SM0SEL23_MASK               (0xCU)
 #define PWM_DTSRCSEL_SM0SEL23_SHIFT              (2U)
+/*! SM0SEL23 - Submodule 0 PWM23 Control Select
+ *  0b00..Generated SM0PWM23 signal is used by the deadtime logic.
+ *  0b01..Inverted generated SM0PWM23 signal is used by the deadtime logic.
+ *  0b10..SWCOUT[SM0OUT23] is used by the deadtime logic.
+ *  0b11..PWM0_EXTA signal is used by the deadtime logic.
+ */
 #define PWM_DTSRCSEL_SM0SEL23(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM0SEL23_SHIFT)) & PWM_DTSRCSEL_SM0SEL23_MASK)
 #define PWM_DTSRCSEL_SM1SEL45_MASK               (0x30U)
 #define PWM_DTSRCSEL_SM1SEL45_SHIFT              (4U)
+/*! SM1SEL45 - Submodule 1 PWM45 Control Select
+ *  0b00..Generated SM1PWM45 signal is used by the deadtime logic.
+ *  0b01..Inverted generated SM1PWM45 signal is used by the deadtime logic.
+ *  0b10..SWCOUT[SM1OUT45] is used by the deadtime logic.
+ *  0b11..PWM1_EXTB signal is used by the deadtime logic.
+ */
 #define PWM_DTSRCSEL_SM1SEL45(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM1SEL45_SHIFT)) & PWM_DTSRCSEL_SM1SEL45_MASK)
 #define PWM_DTSRCSEL_SM1SEL23_MASK               (0xC0U)
 #define PWM_DTSRCSEL_SM1SEL23_SHIFT              (6U)
+/*! SM1SEL23 - Submodule 1 PWM23 Control Select
+ *  0b00..Generated SM1PWM23 signal is used by the deadtime logic.
+ *  0b01..Inverted generated SM1PWM23 signal is used by the deadtime logic.
+ *  0b10..SWCOUT[SM1OUT23] is used by the deadtime logic.
+ *  0b11..PWM1_EXTA signal is used by the deadtime logic.
+ */
 #define PWM_DTSRCSEL_SM1SEL23(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM1SEL23_SHIFT)) & PWM_DTSRCSEL_SM1SEL23_MASK)
 #define PWM_DTSRCSEL_SM2SEL45_MASK               (0x300U)
 #define PWM_DTSRCSEL_SM2SEL45_SHIFT              (8U)
+/*! SM2SEL45 - Submodule 2 PWM45 Control Select
+ *  0b00..Generated SM2PWM45 signal is used by the deadtime logic.
+ *  0b01..Inverted generated SM2PWM45 signal is used by the deadtime logic.
+ *  0b10..SWCOUT[SM2OUT45] is used by the deadtime logic.
+ *  0b11..PWM2_EXTB signal is used by the deadtime logic.
+ */
 #define PWM_DTSRCSEL_SM2SEL45(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM2SEL45_SHIFT)) & PWM_DTSRCSEL_SM2SEL45_MASK)
 #define PWM_DTSRCSEL_SM2SEL23_MASK               (0xC00U)
 #define PWM_DTSRCSEL_SM2SEL23_SHIFT              (10U)
+/*! SM2SEL23 - Submodule 2 PWM23 Control Select
+ *  0b00..Generated SM2PWM23 signal is used by the deadtime logic.
+ *  0b01..Inverted generated SM2PWM23 signal is used by the deadtime logic.
+ *  0b10..SWCOUT[SM2OUT23] is used by the deadtime logic.
+ *  0b11..PWM2_EXTA signal is used by the deadtime logic.
+ */
 #define PWM_DTSRCSEL_SM2SEL23(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM2SEL23_SHIFT)) & PWM_DTSRCSEL_SM2SEL23_MASK)
 #define PWM_DTSRCSEL_SM3SEL45_MASK               (0x3000U)
 #define PWM_DTSRCSEL_SM3SEL45_SHIFT              (12U)
+/*! SM3SEL45 - Submodule 3 PWM45 Control Select
+ *  0b00..Generated SM3PWM45 signal is used by the deadtime logic.
+ *  0b01..Inverted generated SM3PWM45 signal is used by the deadtime logic.
+ *  0b10..SWCOUT[SM3OUT45] is used by the deadtime logic.
+ *  0b11..PWM3_EXTB signal is used by the deadtime logic.
+ */
 #define PWM_DTSRCSEL_SM3SEL45(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM3SEL45_SHIFT)) & PWM_DTSRCSEL_SM3SEL45_MASK)
 #define PWM_DTSRCSEL_SM3SEL23_MASK               (0xC000U)
 #define PWM_DTSRCSEL_SM3SEL23_SHIFT              (14U)
+/*! SM3SEL23 - Submodule 3 PWM23 Control Select
+ *  0b00..Generated SM3PWM23 signal is used by the deadtime logic.
+ *  0b01..Inverted generated SM3PWM23 signal is used by the deadtime logic.
+ *  0b10..SWCOUT[SM3OUT23] is used by the deadtime logic.
+ *  0b11..PWM3_EXTA signal is used by the deadtime logic.
+ */
 #define PWM_DTSRCSEL_SM3SEL23(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM3SEL23_SHIFT)) & PWM_DTSRCSEL_SM3SEL23_MASK)
 /*! @} */
 
@@ -19647,15 +31130,27 @@ typedef struct {
 /*! @{ */
 #define PWM_MCTRL_LDOK_MASK                      (0xFU)
 #define PWM_MCTRL_LDOK_SHIFT                     (0U)
+/*! LDOK - Load Okay
+ *  0b0000..Do not load new values.
+ *  0b0001..Load prescaler, modulus, and PWM values of the corresponding submodule.
+ */
 #define PWM_MCTRL_LDOK(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_LDOK_SHIFT)) & PWM_MCTRL_LDOK_MASK)
 #define PWM_MCTRL_CLDOK_MASK                     (0xF0U)
 #define PWM_MCTRL_CLDOK_SHIFT                    (4U)
 #define PWM_MCTRL_CLDOK(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_CLDOK_SHIFT)) & PWM_MCTRL_CLDOK_MASK)
 #define PWM_MCTRL_RUN_MASK                       (0xF00U)
 #define PWM_MCTRL_RUN_SHIFT                      (8U)
+/*! RUN - Run
+ *  0b0000..PWM generator is disabled in the corresponding submodule.
+ *  0b0001..PWM generator is enabled in the corresponding submodule.
+ */
 #define PWM_MCTRL_RUN(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_RUN_SHIFT)) & PWM_MCTRL_RUN_MASK)
 #define PWM_MCTRL_IPOL_MASK                      (0xF000U)
 #define PWM_MCTRL_IPOL_SHIFT                     (12U)
+/*! IPOL - Current Polarity
+ *  0b0000..PWM23 is used to generate complementary PWM pair in the corresponding submodule.
+ *  0b0001..PWM45 is used to generate complementary PWM pair in the corresponding submodule.
+ */
 #define PWM_MCTRL_IPOL(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_IPOL_SHIFT)) & PWM_MCTRL_IPOL_MASK)
 /*! @} */
 
@@ -19663,6 +31158,14 @@ typedef struct {
 /*! @{ */
 #define PWM_MCTRL2_MONPLL_MASK                   (0x3U)
 #define PWM_MCTRL2_MONPLL_SHIFT                  (0U)
+/*! MONPLL - Monitor PLL State
+ *  0b00..Not locked. Do not monitor PLL operation. Resetting of the fractional delay block in case of PLL losing lock will be controlled by software.
+ *  0b01..Not locked. Monitor PLL operation to automatically disable the fractional delay block when the PLL encounters problems.
+ *  0b10..Locked. Do not monitor PLL operation. Resetting of the fractional delay block in case of PLL losing lock
+ *        will be controlled by software. These bits are write protected until the next reset.
+ *  0b11..Locked. Monitor PLL operation to automatically disable the fractional delay block when the PLL
+ *        encounters problems. These bits are write protected until the next reset.
+ */
 #define PWM_MCTRL2_MONPLL(x)                     (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL2_MONPLL_SHIFT)) & PWM_MCTRL2_MONPLL_MASK)
 /*! @} */
 
@@ -19670,15 +31173,40 @@ typedef struct {
 /*! @{ */
 #define PWM_FCTRL_FIE_MASK                       (0xFU)
 #define PWM_FCTRL_FIE_SHIFT                      (0U)
+/*! FIE - Fault Interrupt Enables
+ *  0b0000..FAULTx CPU interrupt requests disabled.
+ *  0b0001..FAULTx CPU interrupt requests enabled.
+ */
 #define PWM_FCTRL_FIE(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FIE_SHIFT)) & PWM_FCTRL_FIE_MASK)
 #define PWM_FCTRL_FSAFE_MASK                     (0xF0U)
 #define PWM_FCTRL_FSAFE_SHIFT                    (4U)
+/*! FSAFE - Fault Safety Mode
+ *  0b0000..Normal mode. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear at the
+ *          start of a half cycle or full cycle depending on the state of FSTS[FFULL] without regard to the state of
+ *          FSTS[FFPINx]. The PWM outputs disabled by this fault input will not be re-enabled until the actual
+ *          FAULTx input signal de-asserts since the fault input will combinationally disable the PWM outputs (as
+ *          programmed in DISMAPn).
+ *  0b0001..Safe mode. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear and
+ *          FSTS[FFPINx] is clear at the start of a half cycle or full cycle depending on the state of FSTS[FFULL].
+ */
 #define PWM_FCTRL_FSAFE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FSAFE_SHIFT)) & PWM_FCTRL_FSAFE_MASK)
 #define PWM_FCTRL_FAUTO_MASK                     (0xF00U)
 #define PWM_FCTRL_FAUTO_SHIFT                    (8U)
+/*! FAUTO - Automatic Fault Clearing
+ *  0b0000..Manual fault clearing. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear
+ *          at the start of a half cycle or full cycle depending the state of FSTS[FFULL]. This is further
+ *          controlled by FCTRL[FSAFE].
+ *  0b0001..Automatic fault clearing. PWM outputs disabled by this fault are enabled when FSTS[FFPINx] is clear at
+ *          the start of a half cycle or full cycle depending on the state of FSTS[FFULL] without regard to the
+ *          state of FSTS[FFLAGx].
+ */
 #define PWM_FCTRL_FAUTO(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FAUTO_SHIFT)) & PWM_FCTRL_FAUTO_MASK)
 #define PWM_FCTRL_FLVL_MASK                      (0xF000U)
 #define PWM_FCTRL_FLVL_SHIFT                     (12U)
+/*! FLVL - Fault Level
+ *  0b0000..A logic 0 on the fault input indicates a fault condition.
+ *  0b0001..A logic 1 on the fault input indicates a fault condition.
+ */
 #define PWM_FCTRL_FLVL(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FLVL_SHIFT)) & PWM_FCTRL_FLVL_MASK)
 /*! @} */
 
@@ -19686,15 +31214,27 @@ typedef struct {
 /*! @{ */
 #define PWM_FSTS_FFLAG_MASK                      (0xFU)
 #define PWM_FSTS_FFLAG_SHIFT                     (0U)
+/*! FFLAG - Fault Flags
+ *  0b0000..No fault on the FAULTx pin.
+ *  0b0001..Fault on the FAULTx pin.
+ */
 #define PWM_FSTS_FFLAG(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFLAG_SHIFT)) & PWM_FSTS_FFLAG_MASK)
 #define PWM_FSTS_FFULL_MASK                      (0xF0U)
 #define PWM_FSTS_FFULL_SHIFT                     (4U)
+/*! FFULL - Full Cycle
+ *  0b0000..PWM outputs are not re-enabled at the start of a full cycle
+ *  0b0001..PWM outputs are re-enabled at the start of a full cycle
+ */
 #define PWM_FSTS_FFULL(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFULL_SHIFT)) & PWM_FSTS_FFULL_MASK)
 #define PWM_FSTS_FFPIN_MASK                      (0xF00U)
 #define PWM_FSTS_FFPIN_SHIFT                     (8U)
 #define PWM_FSTS_FFPIN(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFPIN_SHIFT)) & PWM_FSTS_FFPIN_MASK)
 #define PWM_FSTS_FHALF_MASK                      (0xF000U)
 #define PWM_FSTS_FHALF_SHIFT                     (12U)
+/*! FHALF - Half Cycle Fault Recovery
+ *  0b0000..PWM outputs are not re-enabled at the start of a half cycle.
+ *  0b0001..PWM outputs are re-enabled at the start of a half cycle (as defined by VAL0).
+ */
 #define PWM_FSTS_FHALF(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FHALF_SHIFT)) & PWM_FSTS_FHALF_MASK)
 /*! @} */
 
@@ -19708,6 +31248,10 @@ typedef struct {
 #define PWM_FFILT_FILT_CNT(x)                    (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_FILT_CNT_SHIFT)) & PWM_FFILT_FILT_CNT_MASK)
 #define PWM_FFILT_GSTR_MASK                      (0x8000U)
 #define PWM_FFILT_GSTR_SHIFT                     (15U)
+/*! GSTR - Fault Glitch Stretch Enable
+ *  0b0..Fault input glitch stretching is disabled.
+ *  0b1..Input fault signals will be stretched to at least 2 IPBus clock cycles.
+ */
 #define PWM_FFILT_GSTR(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_GSTR_SHIFT)) & PWM_FFILT_GSTR_MASK)
 /*! @} */
 
@@ -19715,6 +31259,10 @@ typedef struct {
 /*! @{ */
 #define PWM_FTST_FTEST_MASK                      (0x1U)
 #define PWM_FTST_FTEST_SHIFT                     (0U)
+/*! FTEST - Fault Test
+ *  0b0..No fault
+ *  0b1..Cause a simulated fault
+ */
 #define PWM_FTST_FTEST(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_FTST_FTEST_SHIFT)) & PWM_FTST_FTEST_MASK)
 /*! @} */
 
@@ -19722,6 +31270,12 @@ typedef struct {
 /*! @{ */
 #define PWM_FCTRL2_NOCOMB_MASK                   (0xFU)
 #define PWM_FCTRL2_NOCOMB_SHIFT                  (0U)
+/*! NOCOMB - No Combinational Path From Fault Input To PWM Output
+ *  0b0000..There is a combinational link from the fault inputs to the PWM outputs. The fault inputs are combined
+ *          with the filtered and latched fault signals to disable the PWM outputs.
+ *  0b0001..The direct combinational path from the fault inputs to the PWM outputs is disabled and the filtered
+ *          and latched fault signals are used to disable the PWM outputs.
+ */
 #define PWM_FCTRL2_NOCOMB(x)                     (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL2_NOCOMB_SHIFT)) & PWM_FCTRL2_NOCOMB_MASK)
 /*! @} */
 
@@ -19876,6 +31430,12 @@ typedef struct {
 #define PXP_CTRL_RSVD0(x)                        (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_RSVD0_SHIFT)) & PXP_CTRL_RSVD0_MASK)
 #define PXP_CTRL_ROTATE_MASK                     (0x300U)
 #define PXP_CTRL_ROTATE_SHIFT                    (8U)
+/*! ROTATE
+ *  0b00..ROT_0
+ *  0b01..ROT_90
+ *  0b10..ROT_180
+ *  0b11..ROT_270
+ */
 #define PXP_CTRL_ROTATE(x)                       (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ROTATE_SHIFT)) & PXP_CTRL_ROTATE_MASK)
 #define PXP_CTRL_HFLIP_MASK                      (0x400U)
 #define PXP_CTRL_HFLIP_SHIFT                     (10U)
@@ -19891,6 +31451,10 @@ typedef struct {
 #define PXP_CTRL_ROT_POS(x)                      (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ROT_POS_SHIFT)) & PXP_CTRL_ROT_POS_MASK)
 #define PXP_CTRL_BLOCK_SIZE_MASK                 (0x800000U)
 #define PXP_CTRL_BLOCK_SIZE_SHIFT                (23U)
+/*! BLOCK_SIZE
+ *  0b0..Process 8x8 pixel blocks.
+ *  0b1..Process 16x16 pixel blocks.
+ */
 #define PXP_CTRL_BLOCK_SIZE(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_BLOCK_SIZE_SHIFT)) & PXP_CTRL_BLOCK_SIZE_MASK)
 #define PXP_CTRL_RSVD3_MASK                      (0xF000000U)
 #define PXP_CTRL_RSVD3_SHIFT                     (24U)
@@ -19928,6 +31492,12 @@ typedef struct {
 #define PXP_CTRL_SET_RSVD0(x)                    (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_RSVD0_SHIFT)) & PXP_CTRL_SET_RSVD0_MASK)
 #define PXP_CTRL_SET_ROTATE_MASK                 (0x300U)
 #define PXP_CTRL_SET_ROTATE_SHIFT                (8U)
+/*! ROTATE
+ *  0b00..ROT_0
+ *  0b01..ROT_90
+ *  0b10..ROT_180
+ *  0b11..ROT_270
+ */
 #define PXP_CTRL_SET_ROTATE(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ROTATE_SHIFT)) & PXP_CTRL_SET_ROTATE_MASK)
 #define PXP_CTRL_SET_HFLIP_MASK                  (0x400U)
 #define PXP_CTRL_SET_HFLIP_SHIFT                 (10U)
@@ -19943,6 +31513,10 @@ typedef struct {
 #define PXP_CTRL_SET_ROT_POS(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ROT_POS_SHIFT)) & PXP_CTRL_SET_ROT_POS_MASK)
 #define PXP_CTRL_SET_BLOCK_SIZE_MASK             (0x800000U)
 #define PXP_CTRL_SET_BLOCK_SIZE_SHIFT            (23U)
+/*! BLOCK_SIZE
+ *  0b0..Process 8x8 pixel blocks.
+ *  0b1..Process 16x16 pixel blocks.
+ */
 #define PXP_CTRL_SET_BLOCK_SIZE(x)               (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_BLOCK_SIZE_SHIFT)) & PXP_CTRL_SET_BLOCK_SIZE_MASK)
 #define PXP_CTRL_SET_RSVD3_MASK                  (0xF000000U)
 #define PXP_CTRL_SET_RSVD3_SHIFT                 (24U)
@@ -19980,6 +31554,12 @@ typedef struct {
 #define PXP_CTRL_CLR_RSVD0(x)                    (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_RSVD0_SHIFT)) & PXP_CTRL_CLR_RSVD0_MASK)
 #define PXP_CTRL_CLR_ROTATE_MASK                 (0x300U)
 #define PXP_CTRL_CLR_ROTATE_SHIFT                (8U)
+/*! ROTATE
+ *  0b00..ROT_0
+ *  0b01..ROT_90
+ *  0b10..ROT_180
+ *  0b11..ROT_270
+ */
 #define PXP_CTRL_CLR_ROTATE(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ROTATE_SHIFT)) & PXP_CTRL_CLR_ROTATE_MASK)
 #define PXP_CTRL_CLR_HFLIP_MASK                  (0x400U)
 #define PXP_CTRL_CLR_HFLIP_SHIFT                 (10U)
@@ -19995,6 +31575,10 @@ typedef struct {
 #define PXP_CTRL_CLR_ROT_POS(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ROT_POS_SHIFT)) & PXP_CTRL_CLR_ROT_POS_MASK)
 #define PXP_CTRL_CLR_BLOCK_SIZE_MASK             (0x800000U)
 #define PXP_CTRL_CLR_BLOCK_SIZE_SHIFT            (23U)
+/*! BLOCK_SIZE
+ *  0b0..Process 8x8 pixel blocks.
+ *  0b1..Process 16x16 pixel blocks.
+ */
 #define PXP_CTRL_CLR_BLOCK_SIZE(x)               (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_BLOCK_SIZE_SHIFT)) & PXP_CTRL_CLR_BLOCK_SIZE_MASK)
 #define PXP_CTRL_CLR_RSVD3_MASK                  (0xF000000U)
 #define PXP_CTRL_CLR_RSVD3_SHIFT                 (24U)
@@ -20032,6 +31616,12 @@ typedef struct {
 #define PXP_CTRL_TOG_RSVD0(x)                    (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_RSVD0_SHIFT)) & PXP_CTRL_TOG_RSVD0_MASK)
 #define PXP_CTRL_TOG_ROTATE_MASK                 (0x300U)
 #define PXP_CTRL_TOG_ROTATE_SHIFT                (8U)
+/*! ROTATE
+ *  0b00..ROT_0
+ *  0b01..ROT_90
+ *  0b10..ROT_180
+ *  0b11..ROT_270
+ */
 #define PXP_CTRL_TOG_ROTATE(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ROTATE_SHIFT)) & PXP_CTRL_TOG_ROTATE_MASK)
 #define PXP_CTRL_TOG_HFLIP_MASK                  (0x400U)
 #define PXP_CTRL_TOG_HFLIP_SHIFT                 (10U)
@@ -20047,6 +31637,10 @@ typedef struct {
 #define PXP_CTRL_TOG_ROT_POS(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ROT_POS_SHIFT)) & PXP_CTRL_TOG_ROT_POS_MASK)
 #define PXP_CTRL_TOG_BLOCK_SIZE_MASK             (0x800000U)
 #define PXP_CTRL_TOG_BLOCK_SIZE_SHIFT            (23U)
+/*! BLOCK_SIZE
+ *  0b0..Process 8x8 pixel blocks.
+ *  0b1..Process 16x16 pixel blocks.
+ */
 #define PXP_CTRL_TOG_BLOCK_SIZE(x)               (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_BLOCK_SIZE_SHIFT)) & PXP_CTRL_TOG_BLOCK_SIZE_MASK)
 #define PXP_CTRL_TOG_RSVD3_MASK                  (0xF000000U)
 #define PXP_CTRL_TOG_RSVD3_SHIFT                 (24U)
@@ -20193,12 +31787,37 @@ typedef struct {
 /*! @{ */
 #define PXP_OUT_CTRL_FORMAT_MASK                 (0x1FU)
 #define PXP_OUT_CTRL_FORMAT_SHIFT                (0U)
+/*! FORMAT
+ *  0b00000..32-bit pixels
+ *  0b00100..32-bit pixels (unpacked 24-bit pixel in 32 bit DWORD.)
+ *  0b00101..24-bit pixels (packed 24-bit format)
+ *  0b01000..16-bit pixels
+ *  0b01001..16-bit pixels
+ *  0b01100..16-bit pixels
+ *  0b01101..16-bit pixels
+ *  0b01110..16-bit pixels
+ *  0b10000..32-bit pixels (1-plane XYUV unpacked)
+ *  0b10010..16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes)
+ *  0b10011..16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes)
+ *  0b10100..8-bit monochrome pixels (1-plane Y luma output)
+ *  0b10101..4-bit monochrome pixels (1-plane Y luma, 4 bit truncation)
+ *  0b11000..16-bit pixels (2-plane UV interleaved bytes)
+ *  0b11001..16-bit pixels (2-plane UV)
+ *  0b11010..16-bit pixels (2-plane VU interleaved bytes)
+ *  0b11011..16-bit pixels (2-plane VU)
+ */
 #define PXP_OUT_CTRL_FORMAT(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_FORMAT_SHIFT)) & PXP_OUT_CTRL_FORMAT_MASK)
 #define PXP_OUT_CTRL_RSVD0_MASK                  (0xE0U)
 #define PXP_OUT_CTRL_RSVD0_SHIFT                 (5U)
 #define PXP_OUT_CTRL_RSVD0(x)                    (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_RSVD0_SHIFT)) & PXP_OUT_CTRL_RSVD0_MASK)
 #define PXP_OUT_CTRL_INTERLACED_OUTPUT_MASK      (0x300U)
 #define PXP_OUT_CTRL_INTERLACED_OUTPUT_SHIFT     (8U)
+/*! INTERLACED_OUTPUT
+ *  0b00..All data written in progressive format to the OUTBUF Pointer.
+ *  0b01..Interlaced output: only data for field 0 is written to the OUTBUF Pointer.
+ *  0b10..Interlaced output: only data for field 1 is written to the OUTBUF2 Pointer.
+ *  0b11..Interlaced output: data for field 0 is written to OUTBUF and data for field 1 is written to OUTBUF2.
+ */
 #define PXP_OUT_CTRL_INTERLACED_OUTPUT(x)        (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_INTERLACED_OUTPUT_MASK)
 #define PXP_OUT_CTRL_RSVD1_MASK                  (0x7FFC00U)
 #define PXP_OUT_CTRL_RSVD1_SHIFT                 (10U)
@@ -20215,12 +31834,37 @@ typedef struct {
 /*! @{ */
 #define PXP_OUT_CTRL_SET_FORMAT_MASK             (0x1FU)
 #define PXP_OUT_CTRL_SET_FORMAT_SHIFT            (0U)
+/*! FORMAT
+ *  0b00000..32-bit pixels
+ *  0b00100..32-bit pixels (unpacked 24-bit pixel in 32 bit DWORD.)
+ *  0b00101..24-bit pixels (packed 24-bit format)
+ *  0b01000..16-bit pixels
+ *  0b01001..16-bit pixels
+ *  0b01100..16-bit pixels
+ *  0b01101..16-bit pixels
+ *  0b01110..16-bit pixels
+ *  0b10000..32-bit pixels (1-plane XYUV unpacked)
+ *  0b10010..16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes)
+ *  0b10011..16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes)
+ *  0b10100..8-bit monochrome pixels (1-plane Y luma output)
+ *  0b10101..4-bit monochrome pixels (1-plane Y luma, 4 bit truncation)
+ *  0b11000..16-bit pixels (2-plane UV interleaved bytes)
+ *  0b11001..16-bit pixels (2-plane UV)
+ *  0b11010..16-bit pixels (2-plane VU interleaved bytes)
+ *  0b11011..16-bit pixels (2-plane VU)
+ */
 #define PXP_OUT_CTRL_SET_FORMAT(x)               (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_FORMAT_SHIFT)) & PXP_OUT_CTRL_SET_FORMAT_MASK)
 #define PXP_OUT_CTRL_SET_RSVD0_MASK              (0xE0U)
 #define PXP_OUT_CTRL_SET_RSVD0_SHIFT             (5U)
 #define PXP_OUT_CTRL_SET_RSVD0(x)                (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_RSVD0_SHIFT)) & PXP_OUT_CTRL_SET_RSVD0_MASK)
 #define PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_MASK  (0x300U)
 #define PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_SHIFT (8U)
+/*! INTERLACED_OUTPUT
+ *  0b00..All data written in progressive format to the OUTBUF Pointer.
+ *  0b01..Interlaced output: only data for field 0 is written to the OUTBUF Pointer.
+ *  0b10..Interlaced output: only data for field 1 is written to the OUTBUF2 Pointer.
+ *  0b11..Interlaced output: data for field 0 is written to OUTBUF and data for field 1 is written to OUTBUF2.
+ */
 #define PXP_OUT_CTRL_SET_INTERLACED_OUTPUT(x)    (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_MASK)
 #define PXP_OUT_CTRL_SET_RSVD1_MASK              (0x7FFC00U)
 #define PXP_OUT_CTRL_SET_RSVD1_SHIFT             (10U)
@@ -20237,12 +31881,37 @@ typedef struct {
 /*! @{ */
 #define PXP_OUT_CTRL_CLR_FORMAT_MASK             (0x1FU)
 #define PXP_OUT_CTRL_CLR_FORMAT_SHIFT            (0U)
+/*! FORMAT
+ *  0b00000..32-bit pixels
+ *  0b00100..32-bit pixels (unpacked 24-bit pixel in 32 bit DWORD.)
+ *  0b00101..24-bit pixels (packed 24-bit format)
+ *  0b01000..16-bit pixels
+ *  0b01001..16-bit pixels
+ *  0b01100..16-bit pixels
+ *  0b01101..16-bit pixels
+ *  0b01110..16-bit pixels
+ *  0b10000..32-bit pixels (1-plane XYUV unpacked)
+ *  0b10010..16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes)
+ *  0b10011..16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes)
+ *  0b10100..8-bit monochrome pixels (1-plane Y luma output)
+ *  0b10101..4-bit monochrome pixels (1-plane Y luma, 4 bit truncation)
+ *  0b11000..16-bit pixels (2-plane UV interleaved bytes)
+ *  0b11001..16-bit pixels (2-plane UV)
+ *  0b11010..16-bit pixels (2-plane VU interleaved bytes)
+ *  0b11011..16-bit pixels (2-plane VU)
+ */
 #define PXP_OUT_CTRL_CLR_FORMAT(x)               (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_FORMAT_SHIFT)) & PXP_OUT_CTRL_CLR_FORMAT_MASK)
 #define PXP_OUT_CTRL_CLR_RSVD0_MASK              (0xE0U)
 #define PXP_OUT_CTRL_CLR_RSVD0_SHIFT             (5U)
 #define PXP_OUT_CTRL_CLR_RSVD0(x)                (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_RSVD0_SHIFT)) & PXP_OUT_CTRL_CLR_RSVD0_MASK)
 #define PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_MASK  (0x300U)
 #define PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_SHIFT (8U)
+/*! INTERLACED_OUTPUT
+ *  0b00..All data written in progressive format to the OUTBUF Pointer.
+ *  0b01..Interlaced output: only data for field 0 is written to the OUTBUF Pointer.
+ *  0b10..Interlaced output: only data for field 1 is written to the OUTBUF2 Pointer.
+ *  0b11..Interlaced output: data for field 0 is written to OUTBUF and data for field 1 is written to OUTBUF2.
+ */
 #define PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT(x)    (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_MASK)
 #define PXP_OUT_CTRL_CLR_RSVD1_MASK              (0x7FFC00U)
 #define PXP_OUT_CTRL_CLR_RSVD1_SHIFT             (10U)
@@ -20259,12 +31928,37 @@ typedef struct {
 /*! @{ */
 #define PXP_OUT_CTRL_TOG_FORMAT_MASK             (0x1FU)
 #define PXP_OUT_CTRL_TOG_FORMAT_SHIFT            (0U)
+/*! FORMAT
+ *  0b00000..32-bit pixels
+ *  0b00100..32-bit pixels (unpacked 24-bit pixel in 32 bit DWORD.)
+ *  0b00101..24-bit pixels (packed 24-bit format)
+ *  0b01000..16-bit pixels
+ *  0b01001..16-bit pixels
+ *  0b01100..16-bit pixels
+ *  0b01101..16-bit pixels
+ *  0b01110..16-bit pixels
+ *  0b10000..32-bit pixels (1-plane XYUV unpacked)
+ *  0b10010..16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes)
+ *  0b10011..16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes)
+ *  0b10100..8-bit monochrome pixels (1-plane Y luma output)
+ *  0b10101..4-bit monochrome pixels (1-plane Y luma, 4 bit truncation)
+ *  0b11000..16-bit pixels (2-plane UV interleaved bytes)
+ *  0b11001..16-bit pixels (2-plane UV)
+ *  0b11010..16-bit pixels (2-plane VU interleaved bytes)
+ *  0b11011..16-bit pixels (2-plane VU)
+ */
 #define PXP_OUT_CTRL_TOG_FORMAT(x)               (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_FORMAT_SHIFT)) & PXP_OUT_CTRL_TOG_FORMAT_MASK)
 #define PXP_OUT_CTRL_TOG_RSVD0_MASK              (0xE0U)
 #define PXP_OUT_CTRL_TOG_RSVD0_SHIFT             (5U)
 #define PXP_OUT_CTRL_TOG_RSVD0(x)                (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_RSVD0_SHIFT)) & PXP_OUT_CTRL_TOG_RSVD0_MASK)
 #define PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_MASK  (0x300U)
 #define PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_SHIFT (8U)
+/*! INTERLACED_OUTPUT
+ *  0b00..All data written in progressive format to the OUTBUF Pointer.
+ *  0b01..Interlaced output: only data for field 0 is written to the OUTBUF Pointer.
+ *  0b10..Interlaced output: only data for field 1 is written to the OUTBUF2 Pointer.
+ *  0b11..Interlaced output: data for field 0 is written to OUTBUF and data for field 1 is written to OUTBUF2.
+ */
 #define PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT(x)    (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_MASK)
 #define PXP_OUT_CTRL_TOG_RSVD1_MASK              (0x7FFC00U)
 #define PXP_OUT_CTRL_TOG_RSVD1_SHIFT             (10U)
@@ -20385,6 +32079,23 @@ typedef struct {
 /*! @{ */
 #define PXP_PS_CTRL_FORMAT_MASK                  (0x1FU)
 #define PXP_PS_CTRL_FORMAT_SHIFT                 (0U)
+/*! FORMAT
+ *  0b00100..32-bit pixels (unpacked 24-bit format)
+ *  0b01100..16-bit pixels
+ *  0b01101..16-bit pixels
+ *  0b01110..16-bit pixels
+ *  0b10000..32-bit pixels (1-plane XYUV unpacked)
+ *  0b10010..16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes)
+ *  0b10011..16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes)
+ *  0b10100..8-bit monochrome pixels (1-plane Y luma output)
+ *  0b10101..4-bit monochrome pixels (1-plane Y luma, 4 bit truncation)
+ *  0b11000..16-bit pixels (2-plane UV interleaved bytes)
+ *  0b11001..16-bit pixels (2-plane UV)
+ *  0b11010..16-bit pixels (2-plane VU interleaved bytes)
+ *  0b11011..16-bit pixels (2-plane VU)
+ *  0b11110..16-bit pixels (3-plane format)
+ *  0b11111..16-bit pixels (3-plane format)
+ */
 #define PXP_PS_CTRL_FORMAT(x)                    (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_FORMAT_SHIFT)) & PXP_PS_CTRL_FORMAT_MASK)
 #define PXP_PS_CTRL_WB_SWAP_MASK                 (0x20U)
 #define PXP_PS_CTRL_WB_SWAP_SHIFT                (5U)
@@ -20394,9 +32105,21 @@ typedef struct {
 #define PXP_PS_CTRL_RSVD0(x)                     (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_RSVD0_SHIFT)) & PXP_PS_CTRL_RSVD0_MASK)
 #define PXP_PS_CTRL_DECY_MASK                    (0x300U)
 #define PXP_PS_CTRL_DECY_SHIFT                   (8U)
+/*! DECY
+ *  0b00..Disable pre-decimation filter.
+ *  0b01..Decimate PS by 2.
+ *  0b10..Decimate PS by 4.
+ *  0b11..Decimate PS by 8.
+ */
 #define PXP_PS_CTRL_DECY(x)                      (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_DECY_SHIFT)) & PXP_PS_CTRL_DECY_MASK)
 #define PXP_PS_CTRL_DECX_MASK                    (0xC00U)
 #define PXP_PS_CTRL_DECX_SHIFT                   (10U)
+/*! DECX
+ *  0b00..Disable pre-decimation filter.
+ *  0b01..Decimate PS by 2.
+ *  0b10..Decimate PS by 4.
+ *  0b11..Decimate PS by 8.
+ */
 #define PXP_PS_CTRL_DECX(x)                      (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_DECX_SHIFT)) & PXP_PS_CTRL_DECX_MASK)
 #define PXP_PS_CTRL_RSVD1_MASK                   (0xFFFFF000U)
 #define PXP_PS_CTRL_RSVD1_SHIFT                  (12U)
@@ -20407,6 +32130,23 @@ typedef struct {
 /*! @{ */
 #define PXP_PS_CTRL_SET_FORMAT_MASK              (0x1FU)
 #define PXP_PS_CTRL_SET_FORMAT_SHIFT             (0U)
+/*! FORMAT
+ *  0b00100..32-bit pixels (unpacked 24-bit format)
+ *  0b01100..16-bit pixels
+ *  0b01101..16-bit pixels
+ *  0b01110..16-bit pixels
+ *  0b10000..32-bit pixels (1-plane XYUV unpacked)
+ *  0b10010..16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes)
+ *  0b10011..16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes)
+ *  0b10100..8-bit monochrome pixels (1-plane Y luma output)
+ *  0b10101..4-bit monochrome pixels (1-plane Y luma, 4 bit truncation)
+ *  0b11000..16-bit pixels (2-plane UV interleaved bytes)
+ *  0b11001..16-bit pixels (2-plane UV)
+ *  0b11010..16-bit pixels (2-plane VU interleaved bytes)
+ *  0b11011..16-bit pixels (2-plane VU)
+ *  0b11110..16-bit pixels (3-plane format)
+ *  0b11111..16-bit pixels (3-plane format)
+ */
 #define PXP_PS_CTRL_SET_FORMAT(x)                (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_FORMAT_SHIFT)) & PXP_PS_CTRL_SET_FORMAT_MASK)
 #define PXP_PS_CTRL_SET_WB_SWAP_MASK             (0x20U)
 #define PXP_PS_CTRL_SET_WB_SWAP_SHIFT            (5U)
@@ -20416,9 +32156,21 @@ typedef struct {
 #define PXP_PS_CTRL_SET_RSVD0(x)                 (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_RSVD0_SHIFT)) & PXP_PS_CTRL_SET_RSVD0_MASK)
 #define PXP_PS_CTRL_SET_DECY_MASK                (0x300U)
 #define PXP_PS_CTRL_SET_DECY_SHIFT               (8U)
+/*! DECY
+ *  0b00..Disable pre-decimation filter.
+ *  0b01..Decimate PS by 2.
+ *  0b10..Decimate PS by 4.
+ *  0b11..Decimate PS by 8.
+ */
 #define PXP_PS_CTRL_SET_DECY(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_DECY_SHIFT)) & PXP_PS_CTRL_SET_DECY_MASK)
 #define PXP_PS_CTRL_SET_DECX_MASK                (0xC00U)
 #define PXP_PS_CTRL_SET_DECX_SHIFT               (10U)
+/*! DECX
+ *  0b00..Disable pre-decimation filter.
+ *  0b01..Decimate PS by 2.
+ *  0b10..Decimate PS by 4.
+ *  0b11..Decimate PS by 8.
+ */
 #define PXP_PS_CTRL_SET_DECX(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_DECX_SHIFT)) & PXP_PS_CTRL_SET_DECX_MASK)
 #define PXP_PS_CTRL_SET_RSVD1_MASK               (0xFFFFF000U)
 #define PXP_PS_CTRL_SET_RSVD1_SHIFT              (12U)
@@ -20429,6 +32181,23 @@ typedef struct {
 /*! @{ */
 #define PXP_PS_CTRL_CLR_FORMAT_MASK              (0x1FU)
 #define PXP_PS_CTRL_CLR_FORMAT_SHIFT             (0U)
+/*! FORMAT
+ *  0b00100..32-bit pixels (unpacked 24-bit format)
+ *  0b01100..16-bit pixels
+ *  0b01101..16-bit pixels
+ *  0b01110..16-bit pixels
+ *  0b10000..32-bit pixels (1-plane XYUV unpacked)
+ *  0b10010..16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes)
+ *  0b10011..16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes)
+ *  0b10100..8-bit monochrome pixels (1-plane Y luma output)
+ *  0b10101..4-bit monochrome pixels (1-plane Y luma, 4 bit truncation)
+ *  0b11000..16-bit pixels (2-plane UV interleaved bytes)
+ *  0b11001..16-bit pixels (2-plane UV)
+ *  0b11010..16-bit pixels (2-plane VU interleaved bytes)
+ *  0b11011..16-bit pixels (2-plane VU)
+ *  0b11110..16-bit pixels (3-plane format)
+ *  0b11111..16-bit pixels (3-plane format)
+ */
 #define PXP_PS_CTRL_CLR_FORMAT(x)                (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_FORMAT_SHIFT)) & PXP_PS_CTRL_CLR_FORMAT_MASK)
 #define PXP_PS_CTRL_CLR_WB_SWAP_MASK             (0x20U)
 #define PXP_PS_CTRL_CLR_WB_SWAP_SHIFT            (5U)
@@ -20438,9 +32207,21 @@ typedef struct {
 #define PXP_PS_CTRL_CLR_RSVD0(x)                 (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_RSVD0_SHIFT)) & PXP_PS_CTRL_CLR_RSVD0_MASK)
 #define PXP_PS_CTRL_CLR_DECY_MASK                (0x300U)
 #define PXP_PS_CTRL_CLR_DECY_SHIFT               (8U)
+/*! DECY
+ *  0b00..Disable pre-decimation filter.
+ *  0b01..Decimate PS by 2.
+ *  0b10..Decimate PS by 4.
+ *  0b11..Decimate PS by 8.
+ */
 #define PXP_PS_CTRL_CLR_DECY(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_DECY_SHIFT)) & PXP_PS_CTRL_CLR_DECY_MASK)
 #define PXP_PS_CTRL_CLR_DECX_MASK                (0xC00U)
 #define PXP_PS_CTRL_CLR_DECX_SHIFT               (10U)
+/*! DECX
+ *  0b00..Disable pre-decimation filter.
+ *  0b01..Decimate PS by 2.
+ *  0b10..Decimate PS by 4.
+ *  0b11..Decimate PS by 8.
+ */
 #define PXP_PS_CTRL_CLR_DECX(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_DECX_SHIFT)) & PXP_PS_CTRL_CLR_DECX_MASK)
 #define PXP_PS_CTRL_CLR_RSVD1_MASK               (0xFFFFF000U)
 #define PXP_PS_CTRL_CLR_RSVD1_SHIFT              (12U)
@@ -20451,6 +32232,23 @@ typedef struct {
 /*! @{ */
 #define PXP_PS_CTRL_TOG_FORMAT_MASK              (0x1FU)
 #define PXP_PS_CTRL_TOG_FORMAT_SHIFT             (0U)
+/*! FORMAT
+ *  0b00100..32-bit pixels (unpacked 24-bit format)
+ *  0b01100..16-bit pixels
+ *  0b01101..16-bit pixels
+ *  0b01110..16-bit pixels
+ *  0b10000..32-bit pixels (1-plane XYUV unpacked)
+ *  0b10010..16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes)
+ *  0b10011..16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes)
+ *  0b10100..8-bit monochrome pixels (1-plane Y luma output)
+ *  0b10101..4-bit monochrome pixels (1-plane Y luma, 4 bit truncation)
+ *  0b11000..16-bit pixels (2-plane UV interleaved bytes)
+ *  0b11001..16-bit pixels (2-plane UV)
+ *  0b11010..16-bit pixels (2-plane VU interleaved bytes)
+ *  0b11011..16-bit pixels (2-plane VU)
+ *  0b11110..16-bit pixels (3-plane format)
+ *  0b11111..16-bit pixels (3-plane format)
+ */
 #define PXP_PS_CTRL_TOG_FORMAT(x)                (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_FORMAT_SHIFT)) & PXP_PS_CTRL_TOG_FORMAT_MASK)
 #define PXP_PS_CTRL_TOG_WB_SWAP_MASK             (0x20U)
 #define PXP_PS_CTRL_TOG_WB_SWAP_SHIFT            (5U)
@@ -20460,9 +32258,21 @@ typedef struct {
 #define PXP_PS_CTRL_TOG_RSVD0(x)                 (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_RSVD0_SHIFT)) & PXP_PS_CTRL_TOG_RSVD0_MASK)
 #define PXP_PS_CTRL_TOG_DECY_MASK                (0x300U)
 #define PXP_PS_CTRL_TOG_DECY_SHIFT               (8U)
+/*! DECY
+ *  0b00..Disable pre-decimation filter.
+ *  0b01..Decimate PS by 2.
+ *  0b10..Decimate PS by 4.
+ *  0b11..Decimate PS by 8.
+ */
 #define PXP_PS_CTRL_TOG_DECY(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_DECY_SHIFT)) & PXP_PS_CTRL_TOG_DECY_MASK)
 #define PXP_PS_CTRL_TOG_DECX_MASK                (0xC00U)
 #define PXP_PS_CTRL_TOG_DECX_SHIFT               (10U)
+/*! DECX
+ *  0b00..Disable pre-decimation filter.
+ *  0b01..Decimate PS by 2.
+ *  0b10..Decimate PS by 4.
+ *  0b11..Decimate PS by 8.
+ */
 #define PXP_PS_CTRL_TOG_DECX(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_DECX_SHIFT)) & PXP_PS_CTRL_TOG_DECX_MASK)
 #define PXP_PS_CTRL_TOG_RSVD1_MASK               (0xFFFFF000U)
 #define PXP_PS_CTRL_TOG_RSVD1_SHIFT              (12U)
@@ -20569,18 +32379,48 @@ typedef struct {
 #define PXP_AS_CTRL_RSVD0(x)                     (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_RSVD0_SHIFT)) & PXP_AS_CTRL_RSVD0_MASK)
 #define PXP_AS_CTRL_ALPHA_CTRL_MASK              (0x6U)
 #define PXP_AS_CTRL_ALPHA_CTRL_SHIFT             (1U)
+/*! ALPHA_CTRL
+ *  0b00..Indicates that the AS pixel alpha value will be used to blend the AS with PS. The ALPHA field is ignored.
+ *  0b01..Indicates that the value in the ALPHA field should be used instead of the alpha values present in the input pixels.
+ *  0b10..Indicates that the value in the ALPHA field should be used to scale all pixel alpha values. Each pixel
+ *        alpha is multiplied by the value in the ALPHA field.
+ *  0b11..Enable ROPs. The ROP field indicates an operation to be performed on the alpha surface and PS pixels.
+ */
 #define PXP_AS_CTRL_ALPHA_CTRL(x)                (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ALPHA_CTRL_SHIFT)) & PXP_AS_CTRL_ALPHA_CTRL_MASK)
 #define PXP_AS_CTRL_ENABLE_COLORKEY_MASK         (0x8U)
 #define PXP_AS_CTRL_ENABLE_COLORKEY_SHIFT        (3U)
 #define PXP_AS_CTRL_ENABLE_COLORKEY(x)           (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ENABLE_COLORKEY_SHIFT)) & PXP_AS_CTRL_ENABLE_COLORKEY_MASK)
 #define PXP_AS_CTRL_FORMAT_MASK                  (0xF0U)
 #define PXP_AS_CTRL_FORMAT_SHIFT                 (4U)
+/*! FORMAT
+ *  0b0000..32-bit pixels with alpha
+ *  0b0100..32-bit pixels without alpha (unpacked 24-bit format)
+ *  0b1000..16-bit pixels with alpha
+ *  0b1001..16-bit pixels with alpha
+ *  0b1100..16-bit pixels without alpha
+ *  0b1101..16-bit pixels without alpha
+ *  0b1110..16-bit pixels without alpha
+ */
 #define PXP_AS_CTRL_FORMAT(x)                    (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_FORMAT_SHIFT)) & PXP_AS_CTRL_FORMAT_MASK)
 #define PXP_AS_CTRL_ALPHA_MASK                   (0xFF00U)
 #define PXP_AS_CTRL_ALPHA_SHIFT                  (8U)
 #define PXP_AS_CTRL_ALPHA(x)                     (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ALPHA_SHIFT)) & PXP_AS_CTRL_ALPHA_MASK)
 #define PXP_AS_CTRL_ROP_MASK                     (0xF0000U)
 #define PXP_AS_CTRL_ROP_SHIFT                    (16U)
+/*! ROP
+ *  0b0000..AS AND PS
+ *  0b0001..nAS AND PS
+ *  0b0010..AS AND nPS
+ *  0b0011..AS OR PS
+ *  0b0100..nAS OR PS
+ *  0b0101..AS OR nPS
+ *  0b0110..nAS
+ *  0b0111..nPS
+ *  0b1000..AS NAND PS
+ *  0b1001..AS NOR PS
+ *  0b1010..AS XOR PS
+ *  0b1011..AS XNOR PS
+ */
 #define PXP_AS_CTRL_ROP(x)                       (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ROP_SHIFT)) & PXP_AS_CTRL_ROP_MASK)
 #define PXP_AS_CTRL_ALPHA_INVERT_MASK            (0x100000U)
 #define PXP_AS_CTRL_ALPHA_INVERT_SHIFT           (20U)
@@ -20685,6 +32525,12 @@ typedef struct {
 /*! @{ */
 #define PXP_POWER_ROT_MEM_LP_STATE_MASK          (0xE00U)
 #define PXP_POWER_ROT_MEM_LP_STATE_SHIFT         (9U)
+/*! ROT_MEM_LP_STATE
+ *  0b000..Memory is not in low power state.
+ *  0b001..Light Sleep Mode. Low leakage mode, maintain memory contents.
+ *  0b010..Deep Sleep Mode. Low leakage mode, maintain memory contents.
+ *  0b100..Shut Down Mode. Shut Down periphery and core, no memory retention.
+ */
 #define PXP_POWER_ROT_MEM_LP_STATE(x)            (((uint32_t)(((uint32_t)(x)) << PXP_POWER_ROT_MEM_LP_STATE_SHIFT)) & PXP_POWER_ROT_MEM_LP_STATE_MASK)
 #define PXP_POWER_CTRL_MASK                      (0xFFFFF000U)
 #define PXP_POWER_CTRL_SHIFT                     (12U)
@@ -20808,9 +32654,17 @@ typedef struct {
 /*! @{ */
 #define ROMC_ROMPATCHCNTL_DATAFIX_MASK           (0xFFU)
 #define ROMC_ROMPATCHCNTL_DATAFIX_SHIFT          (0U)
+/*! DATAFIX
+ *  0b00000000..Address comparator triggers a opcode patch
+ *  0b00000001..Address comparator triggers a data fix
+ */
 #define ROMC_ROMPATCHCNTL_DATAFIX(x)             (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHCNTL_DATAFIX_SHIFT)) & ROMC_ROMPATCHCNTL_DATAFIX_MASK)
 #define ROMC_ROMPATCHCNTL_DIS_MASK               (0x20000000U)
 #define ROMC_ROMPATCHCNTL_DIS_SHIFT              (29U)
+/*! DIS
+ *  0b0..Does not affect any ROMC functions (default)
+ *  0b1..Disable all ROMC functions: data fixing, and opcode patching
+ */
 #define ROMC_ROMPATCHCNTL_DIS(x)                 (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHCNTL_DIS_SHIFT)) & ROMC_ROMPATCHCNTL_DIS_MASK)
 /*! @} */
 
@@ -20818,6 +32672,10 @@ typedef struct {
 /*! @{ */
 #define ROMC_ROMPATCHENL_ENABLE_MASK             (0xFFFFU)
 #define ROMC_ROMPATCHENL_ENABLE_SHIFT            (0U)
+/*! ENABLE
+ *  0b0000000000000000..Address comparator disabled
+ *  0b0000000000000001..Address comparator enabled, ROMC will trigger a opcode patch or data fix event upon matching of the associated address
+ */
 #define ROMC_ROMPATCHENL_ENABLE(x)               (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHENL_ENABLE_SHIFT)) & ROMC_ROMPATCHENL_ENABLE_MASK)
 /*! @} */
 
@@ -20825,6 +32683,10 @@ typedef struct {
 /*! @{ */
 #define ROMC_ROMPATCHA_THUMBX_MASK               (0x1U)
 #define ROMC_ROMPATCHA_THUMBX_SHIFT              (0U)
+/*! THUMBX
+ *  0b0..Arm patch
+ *  0b1..THUMB patch (ignore if data fix)
+ */
 #define ROMC_ROMPATCHA_THUMBX(x)                 (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHA_THUMBX_SHIFT)) & ROMC_ROMPATCHA_THUMBX_MASK)
 #define ROMC_ROMPATCHA_ADDRX_MASK                (0x7FFFFEU)
 #define ROMC_ROMPATCHA_ADDRX_SHIFT               (1U)
@@ -20838,9 +32700,18 @@ typedef struct {
 /*! @{ */
 #define ROMC_ROMPATCHSR_SOURCE_MASK              (0x3FU)
 #define ROMC_ROMPATCHSR_SOURCE_SHIFT             (0U)
+/*! SOURCE
+ *  0b000000..Address Comparator 0 matched
+ *  0b000001..Address Comparator 1 matched
+ *  0b001111..Address Comparator 15 matched
+ */
 #define ROMC_ROMPATCHSR_SOURCE(x)                (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHSR_SOURCE_SHIFT)) & ROMC_ROMPATCHSR_SOURCE_MASK)
 #define ROMC_ROMPATCHSR_SW_MASK                  (0x20000U)
 #define ROMC_ROMPATCHSR_SW_SHIFT                 (17U)
+/*! SW
+ *  0b0..no event or comparator collisions
+ *  0b1..a collision has occurred
+ */
 #define ROMC_ROMPATCHSR_SW(x)                    (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHSR_SW_SHIFT)) & ROMC_ROMPATCHSR_SW_MASK)
 /*! @} */
 
@@ -20895,45 +32766,106 @@ typedef struct {
 /*! @{ */
 #define RTWDOG_CS_STOP_MASK                      (0x1U)
 #define RTWDOG_CS_STOP_SHIFT                     (0U)
+/*! STOP - Stop Enable
+ *  0b0..Watchdog disabled in chip stop mode.
+ *  0b1..Watchdog enabled in chip stop mode.
+ */
 #define RTWDOG_CS_STOP(x)                        (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_STOP_SHIFT)) & RTWDOG_CS_STOP_MASK)
 #define RTWDOG_CS_WAIT_MASK                      (0x2U)
 #define RTWDOG_CS_WAIT_SHIFT                     (1U)
+/*! WAIT - Wait Enable
+ *  0b0..Watchdog disabled in chip wait mode.
+ *  0b1..Watchdog enabled in chip wait mode.
+ */
 #define RTWDOG_CS_WAIT(x)                        (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_WAIT_SHIFT)) & RTWDOG_CS_WAIT_MASK)
 #define RTWDOG_CS_DBG_MASK                       (0x4U)
 #define RTWDOG_CS_DBG_SHIFT                      (2U)
+/*! DBG - Debug Enable
+ *  0b0..Watchdog disabled in chip debug mode.
+ *  0b1..Watchdog enabled in chip debug mode.
+ */
 #define RTWDOG_CS_DBG(x)                         (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_DBG_SHIFT)) & RTWDOG_CS_DBG_MASK)
 #define RTWDOG_CS_TST_MASK                       (0x18U)
 #define RTWDOG_CS_TST_SHIFT                      (3U)
+/*! TST - Watchdog Test
+ *  0b00..Watchdog test mode disabled.
+ *  0b01..Watchdog user mode enabled. (Watchdog test mode disabled.) After testing the watchdog, software should
+ *        use this setting to indicate that the watchdog is functioning normally in user mode.
+ *  0b10..Watchdog test mode enabled, only the low byte is used. CNT[CNTLOW] is compared with TOVAL[TOVALLOW].
+ *  0b11..Watchdog test mode enabled, only the high byte is used. CNT[CNTHIGH] is compared with TOVAL[TOVALHIGH].
+ */
 #define RTWDOG_CS_TST(x)                         (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_TST_SHIFT)) & RTWDOG_CS_TST_MASK)
 #define RTWDOG_CS_UPDATE_MASK                    (0x20U)
 #define RTWDOG_CS_UPDATE_SHIFT                   (5U)
+/*! UPDATE - Allow updates
+ *  0b0..Updates not allowed. After the initial configuration, the watchdog cannot be later modified without forcing a reset.
+ *  0b1..Updates allowed. Software can modify the watchdog configuration registers within 128 bus clocks after performing the unlock write sequence.
+ */
 #define RTWDOG_CS_UPDATE(x)                      (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_UPDATE_SHIFT)) & RTWDOG_CS_UPDATE_MASK)
 #define RTWDOG_CS_INT_MASK                       (0x40U)
 #define RTWDOG_CS_INT_SHIFT                      (6U)
+/*! INT - Watchdog Interrupt
+ *  0b0..Watchdog interrupts are disabled. Watchdog resets are not delayed.
+ *  0b1..Watchdog interrupts are enabled. Watchdog resets are delayed by 128 bus clocks from the interrupt vector fetch.
+ */
 #define RTWDOG_CS_INT(x)                         (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_INT_SHIFT)) & RTWDOG_CS_INT_MASK)
 #define RTWDOG_CS_EN_MASK                        (0x80U)
 #define RTWDOG_CS_EN_SHIFT                       (7U)
+/*! EN - Watchdog Enable
+ *  0b0..Watchdog disabled.
+ *  0b1..Watchdog enabled.
+ */
 #define RTWDOG_CS_EN(x)                          (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_EN_SHIFT)) & RTWDOG_CS_EN_MASK)
 #define RTWDOG_CS_CLK_MASK                       (0x300U)
 #define RTWDOG_CS_CLK_SHIFT                      (8U)
+/*! CLK - Watchdog Clock
+ *  0b00..Bus clock
+ *  0b01..LPO clock
+ *  0b10..INTCLK (internal clock)
+ *  0b11..ERCLK (external reference clock)
+ */
 #define RTWDOG_CS_CLK(x)                         (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_CLK_SHIFT)) & RTWDOG_CS_CLK_MASK)
 #define RTWDOG_CS_RCS_MASK                       (0x400U)
 #define RTWDOG_CS_RCS_SHIFT                      (10U)
+/*! RCS - Reconfiguration Success
+ *  0b0..Reconfiguring WDOG.
+ *  0b1..Reconfiguration is successful.
+ */
 #define RTWDOG_CS_RCS(x)                         (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_RCS_SHIFT)) & RTWDOG_CS_RCS_MASK)
 #define RTWDOG_CS_ULK_MASK                       (0x800U)
 #define RTWDOG_CS_ULK_SHIFT                      (11U)
+/*! ULK - Unlock status
+ *  0b0..WDOG is locked.
+ *  0b1..WDOG is unlocked.
+ */
 #define RTWDOG_CS_ULK(x)                         (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_ULK_SHIFT)) & RTWDOG_CS_ULK_MASK)
 #define RTWDOG_CS_PRES_MASK                      (0x1000U)
 #define RTWDOG_CS_PRES_SHIFT                     (12U)
+/*! PRES - Watchdog prescaler
+ *  0b0..256 prescaler disabled.
+ *  0b1..256 prescaler enabled.
+ */
 #define RTWDOG_CS_PRES(x)                        (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_PRES_SHIFT)) & RTWDOG_CS_PRES_MASK)
 #define RTWDOG_CS_CMD32EN_MASK                   (0x2000U)
 #define RTWDOG_CS_CMD32EN_SHIFT                  (13U)
+/*! CMD32EN - Enables or disables WDOG support for 32-bit (otherwise 16-bit or 8-bit) refresh/unlock command write words
+ *  0b0..Disables support for 32-bit refresh/unlock command write words. Only 16-bit or 8-bit is supported.
+ *  0b1..Enables support for 32-bit refresh/unlock command write words. 16-bit or 8-bit is NOT supported.
+ */
 #define RTWDOG_CS_CMD32EN(x)                     (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_CMD32EN_SHIFT)) & RTWDOG_CS_CMD32EN_MASK)
 #define RTWDOG_CS_FLG_MASK                       (0x4000U)
 #define RTWDOG_CS_FLG_SHIFT                      (14U)
+/*! FLG - Watchdog Interrupt Flag
+ *  0b0..No interrupt occurred.
+ *  0b1..An interrupt occurred.
+ */
 #define RTWDOG_CS_FLG(x)                         (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_FLG_SHIFT)) & RTWDOG_CS_FLG_MASK)
 #define RTWDOG_CS_WIN_MASK                       (0x8000U)
 #define RTWDOG_CS_WIN_SHIFT                      (15U)
+/*! WIN - Watchdog Window
+ *  0b0..Window mode disabled.
+ *  0b1..Window mode enabled.
+ */
 #define RTWDOG_CS_WIN(x)                         (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_WIN_SHIFT)) & RTWDOG_CS_WIN_MASK)
 /*! @} */
 
@@ -21074,21 +33006,42 @@ typedef struct {
 #define SEMC_MCR_SWRST(x)                        (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_SWRST_SHIFT)) & SEMC_MCR_SWRST_MASK)
 #define SEMC_MCR_MDIS_MASK                       (0x2U)
 #define SEMC_MCR_MDIS_SHIFT                      (1U)
+/*! MDIS - Module Disable
+ *  0b0..Module enabled
+ *  0b1..Module disabled.
+ */
 #define SEMC_MCR_MDIS(x)                         (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_MDIS_SHIFT)) & SEMC_MCR_MDIS_MASK)
 #define SEMC_MCR_DQSMD_MASK                      (0x4U)
 #define SEMC_MCR_DQSMD_SHIFT                     (2U)
+/*! DQSMD - DQS (read strobe) mode
+ *  0b0..Dummy read strobe loopbacked internally
+ *  0b1..Dummy read strobe loopbacked from DQS pad
+ */
 #define SEMC_MCR_DQSMD(x)                        (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_DQSMD_SHIFT)) & SEMC_MCR_DQSMD_MASK)
 #define SEMC_MCR_WPOL0_MASK                      (0x40U)
 #define SEMC_MCR_WPOL0_SHIFT                     (6U)
+/*! WPOL0 - WAIT/RDY# polarity for NOR/PSRAM
+ *  0b0..Low active
+ *  0b1..High active
+ */
 #define SEMC_MCR_WPOL0(x)                        (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_WPOL0_SHIFT)) & SEMC_MCR_WPOL0_MASK)
 #define SEMC_MCR_WPOL1_MASK                      (0x80U)
 #define SEMC_MCR_WPOL1_SHIFT                     (7U)
+/*! WPOL1 - WAIT/RDY# polarity for NAND
+ *  0b0..Low active
+ *  0b1..High active
+ */
 #define SEMC_MCR_WPOL1(x)                        (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_WPOL1_SHIFT)) & SEMC_MCR_WPOL1_MASK)
 #define SEMC_MCR_CTO_MASK                        (0xFF0000U)
 #define SEMC_MCR_CTO_SHIFT                       (16U)
 #define SEMC_MCR_CTO(x)                          (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_CTO_SHIFT)) & SEMC_MCR_CTO_MASK)
 #define SEMC_MCR_BTO_MASK                        (0x1F000000U)
 #define SEMC_MCR_BTO_SHIFT                       (24U)
+/*! BTO - Bus timeout cycles
+ *  0b00000..255*1
+ *  0b00001-0b11110..255*2 - 255*2^30
+ *  0b11111..255*2^31
+ */
 #define SEMC_MCR_BTO(x)                          (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_BTO_SHIFT)) & SEMC_MCR_BTO_MASK)
 /*! @} */
 
@@ -21096,21 +33049,81 @@ typedef struct {
 /*! @{ */
 #define SEMC_IOCR_MUX_A8_MASK                    (0x7U)
 #define SEMC_IOCR_MUX_A8_SHIFT                   (0U)
+/*! MUX_A8 - SEMC_A8 output selection
+ *  0b000..SDRAM Address bit (A8)
+ *  0b001..NAND CE#
+ *  0b010..NOR CE#
+ *  0b011..PSRAM CE#
+ *  0b100..DBI CSX
+ *  0b101..SDRAM Address bit (A8)
+ *  0b110..SDRAM Address bit (A8)
+ *  0b111..SDRAM Address bit (A8)
+ */
 #define SEMC_IOCR_MUX_A8(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_A8_SHIFT)) & SEMC_IOCR_MUX_A8_MASK)
 #define SEMC_IOCR_MUX_CSX0_MASK                  (0x38U)
 #define SEMC_IOCR_MUX_CSX0_SHIFT                 (3U)
+/*! MUX_CSX0 - SEMC_CSX0 output selection
+ *  0b000..NOR/PSRAM Address bit 24 (A24)
+ *  0b001..SDRAM CS1
+ *  0b010..SDRAM CS2
+ *  0b011..SDRAM CS3
+ *  0b100..NAND CE#
+ *  0b101..NOR CE#
+ *  0b110..PSRAM CE#
+ *  0b111..DBI CSX
+ */
 #define SEMC_IOCR_MUX_CSX0(x)                    (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX0_SHIFT)) & SEMC_IOCR_MUX_CSX0_MASK)
 #define SEMC_IOCR_MUX_CSX1_MASK                  (0x1C0U)
 #define SEMC_IOCR_MUX_CSX1_SHIFT                 (6U)
+/*! MUX_CSX1 - SEMC_CSX1 output selection
+ *  0b000..NOR/PSRAM Address bit 25 (A25)
+ *  0b001..SDRAM CS1
+ *  0b010..SDRAM CS2
+ *  0b011..SDRAM CS3
+ *  0b100..NAND CE#
+ *  0b101..NOR CE#
+ *  0b110..PSRAM CE#
+ *  0b111..DBI CSX
+ */
 #define SEMC_IOCR_MUX_CSX1(x)                    (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX1_SHIFT)) & SEMC_IOCR_MUX_CSX1_MASK)
 #define SEMC_IOCR_MUX_CSX2_MASK                  (0xE00U)
 #define SEMC_IOCR_MUX_CSX2_SHIFT                 (9U)
+/*! MUX_CSX2 - SEMC_CSX2 output selection
+ *  0b000..NOR/PSRAM Address bit 26 (A26)
+ *  0b001..SDRAM CS1
+ *  0b010..SDRAM CS2
+ *  0b011..SDRAM CS3
+ *  0b100..NAND CE#
+ *  0b101..NOR CE#
+ *  0b110..PSRAM CE#
+ *  0b111..DBI CSX
+ */
 #define SEMC_IOCR_MUX_CSX2(x)                    (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX2_SHIFT)) & SEMC_IOCR_MUX_CSX2_MASK)
 #define SEMC_IOCR_MUX_CSX3_MASK                  (0x7000U)
 #define SEMC_IOCR_MUX_CSX3_SHIFT                 (12U)
+/*! MUX_CSX3 - SEMC_CSX3 output selection
+ *  0b000..NOR/PSRAM Address bit 27 (A27)
+ *  0b001..SDRAM CS1
+ *  0b010..SDRAM CS2
+ *  0b011..SDRAM CS3
+ *  0b100..NAND CE#
+ *  0b101..NOR CE#
+ *  0b110..PSRAM CE#
+ *  0b111..DBI CSX
+ */
 #define SEMC_IOCR_MUX_CSX3(x)                    (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX3_SHIFT)) & SEMC_IOCR_MUX_CSX3_MASK)
 #define SEMC_IOCR_MUX_RDY_MASK                   (0x38000U)
 #define SEMC_IOCR_MUX_RDY_SHIFT                  (15U)
+/*! MUX_RDY - SEMC_RDY function selection
+ *  0b000..NAND Ready/Wait# input
+ *  0b001..SDRAM CS1
+ *  0b010..SDRAM CS2
+ *  0b011..SDRAM CS3
+ *  0b100..NOR CE#
+ *  0b101..PSRAM CE#
+ *  0b110..DBI CSX
+ *  0b111..NOR/PSRAM Address bit 27
+ */
 #define SEMC_IOCR_MUX_RDY(x)                     (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_RDY_SHIFT)) & SEMC_IOCR_MUX_RDY_MASK)
 /*! @} */
 
@@ -21156,6 +33169,40 @@ typedef struct {
 #define SEMC_BR_VLD(x)                           (((uint32_t)(((uint32_t)(x)) << SEMC_BR_VLD_SHIFT)) & SEMC_BR_VLD_MASK)
 #define SEMC_BR_MS_MASK                          (0x3EU)
 #define SEMC_BR_MS_SHIFT                         (1U)
+/*! MS - Memory size
+ *  0b00000..4KB
+ *  0b00001..8KB
+ *  0b00010..16KB
+ *  0b00011..32KB
+ *  0b00100..64KB
+ *  0b00101..128KB
+ *  0b00110..256KB
+ *  0b00111..512KB
+ *  0b01000..1MB
+ *  0b01001..2MB
+ *  0b01010..4MB
+ *  0b01011..8MB
+ *  0b01100..16MB
+ *  0b01101..32MB
+ *  0b01110..64MB
+ *  0b01111..128MB
+ *  0b10000..256MB
+ *  0b10001..512MB
+ *  0b10010..1GB
+ *  0b10011..2GB
+ *  0b10100..4GB
+ *  0b10101..4GB
+ *  0b10110..4GB
+ *  0b10111..4GB
+ *  0b11000..4GB
+ *  0b11001..4GB
+ *  0b11010..4GB
+ *  0b11011..4GB
+ *  0b11100..4GB
+ *  0b11101..4GB
+ *  0b11110..4GB
+ *  0b11111..4GB
+ */
 #define SEMC_BR_MS(x)                            (((uint32_t)(((uint32_t)(x)) << SEMC_BR_MS_SHIFT)) & SEMC_BR_MS_MASK)
 #define SEMC_BR_BA_MASK                          (0xFFFFF000U)
 #define SEMC_BR_BA_SHIFT                         (12U)
@@ -21181,9 +33228,17 @@ typedef struct {
 #define SEMC_INTEN_AXIBUSERREN(x)                (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_AXIBUSERREN_SHIFT)) & SEMC_INTEN_AXIBUSERREN_MASK)
 #define SEMC_INTEN_NDPAGEENDEN_MASK              (0x10U)
 #define SEMC_INTEN_NDPAGEENDEN_SHIFT             (4U)
+/*! NDPAGEENDEN - This bit enable/disable the NDPAGEEND interrupt generation.
+ *  0b0..Disable
+ *  0b1..Enable
+ */
 #define SEMC_INTEN_NDPAGEENDEN(x)                (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_NDPAGEENDEN_SHIFT)) & SEMC_INTEN_NDPAGEENDEN_MASK)
 #define SEMC_INTEN_NDNOPENDEN_MASK               (0x20U)
 #define SEMC_INTEN_NDNOPENDEN_SHIFT              (5U)
+/*! NDNOPENDEN - This bit enable/disable the NDNOPEND interrupt generation.
+ *  0b0..Disable
+ *  0b1..Enable
+ */
 #define SEMC_INTEN_NDNOPENDEN(x)                 (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_NDNOPENDEN_SHIFT)) & SEMC_INTEN_NDNOPENDEN_MASK)
 /*! @} */
 
@@ -21213,15 +33268,41 @@ typedef struct {
 /*! @{ */
 #define SEMC_SDRAMCR0_PS_MASK                    (0x1U)
 #define SEMC_SDRAMCR0_PS_SHIFT                   (0U)
+/*! PS - Port Size
+ *  0b0..8bit
+ *  0b1..16bit
+ */
 #define SEMC_SDRAMCR0_PS(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_PS_SHIFT)) & SEMC_SDRAMCR0_PS_MASK)
 #define SEMC_SDRAMCR0_BL_MASK                    (0x70U)
 #define SEMC_SDRAMCR0_BL_SHIFT                   (4U)
+/*! BL - Burst Length
+ *  0b000..1
+ *  0b001..2
+ *  0b010..4
+ *  0b011..8
+ *  0b100..8
+ *  0b101..8
+ *  0b110..8
+ *  0b111..8
+ */
 #define SEMC_SDRAMCR0_BL(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_BL_SHIFT)) & SEMC_SDRAMCR0_BL_MASK)
 #define SEMC_SDRAMCR0_COL_MASK                   (0x300U)
 #define SEMC_SDRAMCR0_COL_SHIFT                  (8U)
+/*! COL - Column address bit number
+ *  0b00..12 bit
+ *  0b01..11 bit
+ *  0b10..10 bit
+ *  0b11..9 bit
+ */
 #define SEMC_SDRAMCR0_COL(x)                     (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_COL_SHIFT)) & SEMC_SDRAMCR0_COL_MASK)
 #define SEMC_SDRAMCR0_CL_MASK                    (0xC00U)
 #define SEMC_SDRAMCR0_CL_SHIFT                   (10U)
+/*! CL - CAS Latency
+ *  0b00..1
+ *  0b01..1
+ *  0b10..2
+ *  0b11..3
+ */
 #define SEMC_SDRAMCR0_CL(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_CL_SHIFT)) & SEMC_SDRAMCR0_CL_MASK)
 /*! @} */
 
@@ -21260,6 +33341,10 @@ typedef struct {
 #define SEMC_SDRAMCR2_ACT2ACT(x)                 (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_ACT2ACT_SHIFT)) & SEMC_SDRAMCR2_ACT2ACT_MASK)
 #define SEMC_SDRAMCR2_ITO_MASK                   (0xFF000000U)
 #define SEMC_SDRAMCR2_ITO_SHIFT                  (24U)
+/*! ITO - SDRAM Idle timeout
+ *  0b00000000..IDLE timeout period is 256*Prescale period.
+ *  0b00000001-0b11111111..IDLE timeout period is ITO*Prescale period.
+ */
 #define SEMC_SDRAMCR2_ITO(x)                     (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_ITO_SHIFT)) & SEMC_SDRAMCR2_ITO_MASK)
 /*! @} */
 
@@ -21270,15 +33355,37 @@ typedef struct {
 #define SEMC_SDRAMCR3_REN(x)                     (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_REN_SHIFT)) & SEMC_SDRAMCR3_REN_MASK)
 #define SEMC_SDRAMCR3_REBL_MASK                  (0xEU)
 #define SEMC_SDRAMCR3_REBL_SHIFT                 (1U)
+/*! REBL - Refresh burst length
+ *  0b000..1
+ *  0b001..2
+ *  0b010..3
+ *  0b011..4
+ *  0b100..5
+ *  0b101..6
+ *  0b110..7
+ *  0b111..8
+ */
 #define SEMC_SDRAMCR3_REBL(x)                    (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_REBL_SHIFT)) & SEMC_SDRAMCR3_REBL_MASK)
 #define SEMC_SDRAMCR3_PRESCALE_MASK              (0xFF00U)
 #define SEMC_SDRAMCR3_PRESCALE_SHIFT             (8U)
+/*! PRESCALE - Prescaler timer period
+ *  0b00000000..256*16 cycle
+ *  0b00000001-0b11111111..PRESCALE*16 cycle
+ */
 #define SEMC_SDRAMCR3_PRESCALE(x)                (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_PRESCALE_SHIFT)) & SEMC_SDRAMCR3_PRESCALE_MASK)
 #define SEMC_SDRAMCR3_RT_MASK                    (0xFF0000U)
 #define SEMC_SDRAMCR3_RT_SHIFT                   (16U)
+/*! RT - Refresh timer period
+ *  0b00000000..256*Prescaler period
+ *  0b00000001-0b11111111..RT*Prescaler period
+ */
 #define SEMC_SDRAMCR3_RT(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_RT_SHIFT)) & SEMC_SDRAMCR3_RT_MASK)
 #define SEMC_SDRAMCR3_UT_MASK                    (0xFF000000U)
 #define SEMC_SDRAMCR3_UT_SHIFT                   (24U)
+/*! UT - Refresh urgent threshold
+ *  0b00000000..256*Prescaler period
+ *  0b00000001-0b11111111..UT*Prescaler period
+ */
 #define SEMC_SDRAMCR3_UT(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_UT_SHIFT)) & SEMC_SDRAMCR3_UT_MASK)
 /*! @} */
 
@@ -21286,15 +33393,43 @@ typedef struct {
 /*! @{ */
 #define SEMC_NANDCR0_PS_MASK                     (0x1U)
 #define SEMC_NANDCR0_PS_SHIFT                    (0U)
+/*! PS - Port Size
+ *  0b0..8bit
+ *  0b1..16bit
+ */
 #define SEMC_NANDCR0_PS(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_PS_SHIFT)) & SEMC_NANDCR0_PS_MASK)
 #define SEMC_NANDCR0_BL_MASK                     (0x70U)
 #define SEMC_NANDCR0_BL_SHIFT                    (4U)
+/*! BL - Burst Length
+ *  0b000..1
+ *  0b001..2
+ *  0b010..4
+ *  0b011..8
+ *  0b100..16
+ *  0b101..32
+ *  0b110..64
+ *  0b111..64
+ */
 #define SEMC_NANDCR0_BL(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_BL_SHIFT)) & SEMC_NANDCR0_BL_MASK)
 #define SEMC_NANDCR0_EDO_MASK                    (0x80U)
 #define SEMC_NANDCR0_EDO_SHIFT                   (7U)
+/*! EDO - EDO mode enabled
+ *  0b0..EDO mode disabled
+ *  0b1..EDO mode enabled
+ */
 #define SEMC_NANDCR0_EDO(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_EDO_SHIFT)) & SEMC_NANDCR0_EDO_MASK)
 #define SEMC_NANDCR0_COL_MASK                    (0x700U)
 #define SEMC_NANDCR0_COL_SHIFT                   (8U)
+/*! COL - Column address bit number
+ *  0b000..16
+ *  0b001..15
+ *  0b010..14
+ *  0b011..13
+ *  0b100..12
+ *  0b101..11
+ *  0b110..10
+ *  0b111..9
+ */
 #define SEMC_NANDCR0_COL(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_COL_SHIFT)) & SEMC_NANDCR0_COL_MASK)
 /*! @} */
 
@@ -21362,18 +33497,60 @@ typedef struct {
 /*! @{ */
 #define SEMC_NORCR0_PS_MASK                      (0x1U)
 #define SEMC_NORCR0_PS_SHIFT                     (0U)
+/*! PS - Port Size
+ *  0b0..8bit
+ *  0b1..16bit
+ */
 #define SEMC_NORCR0_PS(x)                        (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_PS_SHIFT)) & SEMC_NORCR0_PS_MASK)
 #define SEMC_NORCR0_BL_MASK                      (0x70U)
 #define SEMC_NORCR0_BL_SHIFT                     (4U)
+/*! BL - Burst Length
+ *  0b000..1
+ *  0b001..2
+ *  0b010..4
+ *  0b011..8
+ *  0b100..16
+ *  0b101..32
+ *  0b110..64
+ *  0b111..64
+ */
 #define SEMC_NORCR0_BL(x)                        (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_BL_SHIFT)) & SEMC_NORCR0_BL_MASK)
 #define SEMC_NORCR0_AM_MASK                      (0x300U)
 #define SEMC_NORCR0_AM_SHIFT                     (8U)
+/*! AM - Address Mode
+ *  0b00..Address/Data MUX mode
+ *  0b01..Advanced Address/Data MUX mode
+ *  0b10..Address/Data non-MUX mode
+ *  0b11..Address/Data non-MUX mode
+ */
 #define SEMC_NORCR0_AM(x)                        (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_AM_SHIFT)) & SEMC_NORCR0_AM_MASK)
 #define SEMC_NORCR0_ADVP_MASK                    (0x400U)
 #define SEMC_NORCR0_ADVP_SHIFT                   (10U)
+/*! ADVP - ADV# polarity
+ *  0b0..ADV# is Low Active. In ASYNC mode, device sample address with ADV# rise edge; In SYNC mode, device sample address when ADV# is LOW.
+ *  0b1..ADV# is High Active. In ASYNC mode, device sample address with ADV# fall edge; In SYNC mode, device sample address when ADV# is HIGH.
+ */
 #define SEMC_NORCR0_ADVP(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_ADVP_SHIFT)) & SEMC_NORCR0_ADVP_MASK)
 #define SEMC_NORCR0_COL_MASK                     (0xF000U)
 #define SEMC_NORCR0_COL_SHIFT                    (12U)
+/*! COL - Column Address bit width
+ *  0b0000..12 Bits
+ *  0b0001..11 Bits
+ *  0b0010..10 Bits
+ *  0b0011..9 Bits
+ *  0b0100..8 Bits
+ *  0b0101..7 Bits
+ *  0b0110..6 Bits
+ *  0b0111..5 Bits
+ *  0b1000..4 Bits
+ *  0b1001..3 Bits
+ *  0b1010..2 Bits
+ *  0b1011..12 Bits
+ *  0b1100..12 Bits
+ *  0b1101..12 Bits
+ *  0b1110..12 Bits
+ *  0b1111..12 Bits
+ */
 #define SEMC_NORCR0_COL(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_COL_SHIFT)) & SEMC_NORCR0_COL_MASK)
 /*! @} */
 
@@ -21434,18 +33611,60 @@ typedef struct {
 /*! @{ */
 #define SEMC_SRAMCR0_PS_MASK                     (0x1U)
 #define SEMC_SRAMCR0_PS_SHIFT                    (0U)
+/*! PS - Port Size
+ *  0b0..8bit
+ *  0b1..16bit
+ */
 #define SEMC_SRAMCR0_PS(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_PS_SHIFT)) & SEMC_SRAMCR0_PS_MASK)
 #define SEMC_SRAMCR0_BL_MASK                     (0x70U)
 #define SEMC_SRAMCR0_BL_SHIFT                    (4U)
+/*! BL - Burst Length
+ *  0b000..1
+ *  0b001..2
+ *  0b010..4
+ *  0b011..8
+ *  0b100..16
+ *  0b101..32
+ *  0b110..64
+ *  0b111..64
+ */
 #define SEMC_SRAMCR0_BL(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_BL_SHIFT)) & SEMC_SRAMCR0_BL_MASK)
 #define SEMC_SRAMCR0_AM_MASK                     (0x300U)
 #define SEMC_SRAMCR0_AM_SHIFT                    (8U)
+/*! AM - Address Mode
+ *  0b00..Address/Data MUX mode
+ *  0b01..Advanced Address/Data MUX mode
+ *  0b10..Address/Data non-MUX mode
+ *  0b11..Address/Data non-MUX mode
+ */
 #define SEMC_SRAMCR0_AM(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_AM_SHIFT)) & SEMC_SRAMCR0_AM_MASK)
 #define SEMC_SRAMCR0_ADVP_MASK                   (0x400U)
 #define SEMC_SRAMCR0_ADVP_SHIFT                  (10U)
+/*! ADVP - ADV# polarity
+ *  0b0..ADV# is Low Active. In ASYNC mode, device sample address with ADV# rise edge; In SYNC mode, device sample address when ADV# is LOW.
+ *  0b1..ADV# is High Active. In ASYNC mode, device sample address with ADV# fall edge; In SYNC mode, device sample address when ADV# is HIGH.
+ */
 #define SEMC_SRAMCR0_ADVP(x)                     (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_ADVP_SHIFT)) & SEMC_SRAMCR0_ADVP_MASK)
 #define SEMC_SRAMCR0_COL_MASK                    (0xF000U)
 #define SEMC_SRAMCR0_COL_SHIFT                   (12U)
+/*! COL - Column Address bit width
+ *  0b0000..12 Bits
+ *  0b0001..11 Bits
+ *  0b0010..10 Bits
+ *  0b0011..9 Bits
+ *  0b0100..8 Bits
+ *  0b0101..7 Bits
+ *  0b0110..6 Bits
+ *  0b0111..5 Bits
+ *  0b1000..4 Bits
+ *  0b1001..3 Bits
+ *  0b1010..2 Bits
+ *  0b1011..12 Bits
+ *  0b1100..12 Bits
+ *  0b1101..12 Bits
+ *  0b1110..12 Bits
+ *  0b1111..12 Bits
+ */
 #define SEMC_SRAMCR0_COL(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_COL_SHIFT)) & SEMC_SRAMCR0_COL_MASK)
 /*! @} */
 
@@ -21506,12 +33725,44 @@ typedef struct {
 /*! @{ */
 #define SEMC_DBICR0_PS_MASK                      (0x1U)
 #define SEMC_DBICR0_PS_SHIFT                     (0U)
+/*! PS - Port Size
+ *  0b0..8bit
+ *  0b1..16bit
+ */
 #define SEMC_DBICR0_PS(x)                        (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_PS_SHIFT)) & SEMC_DBICR0_PS_MASK)
 #define SEMC_DBICR0_BL_MASK                      (0x70U)
 #define SEMC_DBICR0_BL_SHIFT                     (4U)
+/*! BL - Burst Length
+ *  0b000..1
+ *  0b001..2
+ *  0b010..4
+ *  0b011..8
+ *  0b100..16
+ *  0b101..32
+ *  0b110..64
+ *  0b111..64
+ */
 #define SEMC_DBICR0_BL(x)                        (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_BL_SHIFT)) & SEMC_DBICR0_BL_MASK)
 #define SEMC_DBICR0_COL_MASK                     (0xF000U)
 #define SEMC_DBICR0_COL_SHIFT                    (12U)
+/*! COL - Column Address bit width
+ *  0b0000..12 Bits
+ *  0b0001..11 Bits
+ *  0b0010..10 Bits
+ *  0b0011..9 Bits
+ *  0b0100..8 Bits
+ *  0b0101..7 Bits
+ *  0b0110..6 Bits
+ *  0b0111..5 Bits
+ *  0b1000..4 Bits
+ *  0b1001..3 Bits
+ *  0b1010..2 Bits
+ *  0b1011..12 Bits
+ *  0b1100..12 Bits
+ *  0b1101..12 Bits
+ *  0b1110..12 Bits
+ *  0b1111..12 Bits
+ */
 #define SEMC_DBICR0_COL(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_COL_SHIFT)) & SEMC_DBICR0_COL_MASK)
 /*! @} */
 
@@ -21557,6 +33808,16 @@ typedef struct {
 /*! @{ */
 #define SEMC_IPCR1_DATSZ_MASK                    (0x7U)
 #define SEMC_IPCR1_DATSZ_SHIFT                   (0U)
+/*! DATSZ - Data Size in Byte
+ *  0b000..4
+ *  0b001..1
+ *  0b010..2
+ *  0b011..3
+ *  0b100..4
+ *  0b101..4
+ *  0b110..4
+ *  0b111..4
+ */
 #define SEMC_IPCR1_DATSZ(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR1_DATSZ_SHIFT)) & SEMC_IPCR1_DATSZ_MASK)
 /*! @} */
 
@@ -21564,15 +33825,31 @@ typedef struct {
 /*! @{ */
 #define SEMC_IPCR2_BM0_MASK                      (0x1U)
 #define SEMC_IPCR2_BM0_SHIFT                     (0U)
+/*! BM0 - Byte Mask for Byte 0 (IPTXD bit 7:0)
+ *  0b0..Byte Unmasked
+ *  0b1..Byte Masked
+ */
 #define SEMC_IPCR2_BM0(x)                        (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM0_SHIFT)) & SEMC_IPCR2_BM0_MASK)
 #define SEMC_IPCR2_BM1_MASK                      (0x2U)
 #define SEMC_IPCR2_BM1_SHIFT                     (1U)
+/*! BM1 - Byte Mask for Byte 1 (IPTXD bit 15:8)
+ *  0b0..Byte Unmasked
+ *  0b1..Byte Masked
+ */
 #define SEMC_IPCR2_BM1(x)                        (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM1_SHIFT)) & SEMC_IPCR2_BM1_MASK)
 #define SEMC_IPCR2_BM2_MASK                      (0x4U)
 #define SEMC_IPCR2_BM2_SHIFT                     (2U)
+/*! BM2 - Byte Mask for Byte 2 (IPTXD bit 23:16)
+ *  0b0..Byte Unmasked
+ *  0b1..Byte Masked
+ */
 #define SEMC_IPCR2_BM2(x)                        (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM2_SHIFT)) & SEMC_IPCR2_BM2_MASK)
 #define SEMC_IPCR2_BM3_MASK                      (0x8U)
 #define SEMC_IPCR2_BM3_SHIFT                     (3U)
+/*! BM3 - Byte Mask for Byte 3 (IPTXD bit 31:24)
+ *  0b0..Byte Unmasked
+ *  0b1..Byte Masked
+ */
 #define SEMC_IPCR2_BM3(x)                        (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM3_SHIFT)) & SEMC_IPCR2_BM3_MASK)
 /*! @} */
 
@@ -21607,6 +33884,10 @@ typedef struct {
 #define SEMC_STS0_IDLE(x)                        (((uint32_t)(((uint32_t)(x)) << SEMC_STS0_IDLE_SHIFT)) & SEMC_STS0_IDLE_MASK)
 #define SEMC_STS0_NARDY_MASK                     (0x2U)
 #define SEMC_STS0_NARDY_SHIFT                    (1U)
+/*! NARDY - Indicating NAND device Ready/WAIT# pin level.
+ *  0b0..NAND device is not ready
+ *  0b1..NAND device is ready
+ */
 #define SEMC_STS0_NARDY(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_STS0_NARDY_SHIFT)) & SEMC_STS0_NARDY_MASK)
 /*! @} */
 
@@ -21614,6 +33895,10 @@ typedef struct {
 /*! @{ */
 #define SEMC_STS2_NDWRPEND_MASK                  (0x8U)
 #define SEMC_STS2_NDWRPEND_SHIFT                 (3U)
+/*! NDWRPEND - This field indicating whether there is pending AXI command (write) to NAND device.
+ *  0b0..No pending
+ *  0b1..Pending
+ */
 #define SEMC_STS2_NDWRPEND(x)                    (((uint32_t)(((uint32_t)(x)) << SEMC_STS2_NDWRPEND_SHIFT)) & SEMC_STS2_NDWRPEND_MASK)
 /*! @} */
 
@@ -21708,39 +33993,87 @@ typedef struct {
 /*! @{ */
 #define SNVS_HPLR_ZMK_WSL_MASK                   (0x1U)
 #define SNVS_HPLR_ZMK_WSL_SHIFT                  (0U)
+/*! ZMK_WSL
+ *  0b0..Write access is allowed
+ *  0b1..Write access is not allowed
+ */
 #define SNVS_HPLR_ZMK_WSL(x)                     (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_ZMK_WSL_SHIFT)) & SNVS_HPLR_ZMK_WSL_MASK)
 #define SNVS_HPLR_ZMK_RSL_MASK                   (0x2U)
 #define SNVS_HPLR_ZMK_RSL_SHIFT                  (1U)
+/*! ZMK_RSL
+ *  0b0..Read access is allowed (only in software Programming mode)
+ *  0b1..Read access is not allowed
+ */
 #define SNVS_HPLR_ZMK_RSL(x)                     (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_ZMK_RSL_SHIFT)) & SNVS_HPLR_ZMK_RSL_MASK)
 #define SNVS_HPLR_SRTC_SL_MASK                   (0x4U)
 #define SNVS_HPLR_SRTC_SL_SHIFT                  (2U)
+/*! SRTC_SL
+ *  0b0..Write access is allowed
+ *  0b1..Write access is not allowed
+ */
 #define SNVS_HPLR_SRTC_SL(x)                     (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_SRTC_SL_SHIFT)) & SNVS_HPLR_SRTC_SL_MASK)
 #define SNVS_HPLR_LPCALB_SL_MASK                 (0x8U)
 #define SNVS_HPLR_LPCALB_SL_SHIFT                (3U)
+/*! LPCALB_SL
+ *  0b0..Write access is allowed
+ *  0b1..Write access is not allowed
+ */
 #define SNVS_HPLR_LPCALB_SL(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPCALB_SL_SHIFT)) & SNVS_HPLR_LPCALB_SL_MASK)
 #define SNVS_HPLR_MC_SL_MASK                     (0x10U)
 #define SNVS_HPLR_MC_SL_SHIFT                    (4U)
+/*! MC_SL
+ *  0b0..Write access (increment) is allowed
+ *  0b1..Write access (increment) is not allowed
+ */
 #define SNVS_HPLR_MC_SL(x)                       (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_MC_SL_SHIFT)) & SNVS_HPLR_MC_SL_MASK)
 #define SNVS_HPLR_GPR_SL_MASK                    (0x20U)
 #define SNVS_HPLR_GPR_SL_SHIFT                   (5U)
+/*! GPR_SL
+ *  0b0..Write access is allowed
+ *  0b1..Write access is not allowed
+ */
 #define SNVS_HPLR_GPR_SL(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_GPR_SL_SHIFT)) & SNVS_HPLR_GPR_SL_MASK)
 #define SNVS_HPLR_LPSVCR_SL_MASK                 (0x40U)
 #define SNVS_HPLR_LPSVCR_SL_SHIFT                (6U)
+/*! LPSVCR_SL
+ *  0b0..Write access is allowed
+ *  0b1..Write access is not allowed
+ */
 #define SNVS_HPLR_LPSVCR_SL(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPSVCR_SL_SHIFT)) & SNVS_HPLR_LPSVCR_SL_MASK)
 #define SNVS_HPLR_LPTDCR_SL_MASK                 (0x100U)
 #define SNVS_HPLR_LPTDCR_SL_SHIFT                (8U)
+/*! LPTDCR_SL
+ *  0b0..Write access is allowed
+ *  0b1..Write access is not allowed
+ */
 #define SNVS_HPLR_LPTDCR_SL(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPTDCR_SL_SHIFT)) & SNVS_HPLR_LPTDCR_SL_MASK)
 #define SNVS_HPLR_MKS_SL_MASK                    (0x200U)
 #define SNVS_HPLR_MKS_SL_SHIFT                   (9U)
+/*! MKS_SL
+ *  0b0..Write access is allowed
+ *  0b1..Write access is not allowed
+ */
 #define SNVS_HPLR_MKS_SL(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_MKS_SL_SHIFT)) & SNVS_HPLR_MKS_SL_MASK)
 #define SNVS_HPLR_HPSVCR_L_MASK                  (0x10000U)
 #define SNVS_HPLR_HPSVCR_L_SHIFT                 (16U)
+/*! HPSVCR_L
+ *  0b0..Write access is allowed
+ *  0b1..Write access is not allowed
+ */
 #define SNVS_HPLR_HPSVCR_L(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HPSVCR_L_SHIFT)) & SNVS_HPLR_HPSVCR_L_MASK)
 #define SNVS_HPLR_HPSICR_L_MASK                  (0x20000U)
 #define SNVS_HPLR_HPSICR_L_SHIFT                 (17U)
+/*! HPSICR_L
+ *  0b0..Write access is allowed
+ *  0b1..Write access is not allowed
+ */
 #define SNVS_HPLR_HPSICR_L(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HPSICR_L_SHIFT)) & SNVS_HPLR_HPSICR_L_MASK)
 #define SNVS_HPLR_HAC_L_MASK                     (0x40000U)
 #define SNVS_HPLR_HAC_L_SHIFT                    (18U)
+/*! HAC_L
+ *  0b0..Write access is allowed
+ *  0b1..Write access is not allowed
+ */
 #define SNVS_HPLR_HAC_L(x)                       (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HAC_L_SHIFT)) & SNVS_HPLR_HAC_L_MASK)
 /*! @} */
 
@@ -21751,15 +34084,31 @@ typedef struct {
 #define SNVS_HPCOMR_SSM_ST(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_ST_SHIFT)) & SNVS_HPCOMR_SSM_ST_MASK)
 #define SNVS_HPCOMR_SSM_ST_DIS_MASK              (0x2U)
 #define SNVS_HPCOMR_SSM_ST_DIS_SHIFT             (1U)
+/*! SSM_ST_DIS
+ *  0b0..Secure to Trusted State transition is enabled
+ *  0b1..Secure to Trusted State transition is disabled
+ */
 #define SNVS_HPCOMR_SSM_ST_DIS(x)                (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_ST_DIS_SHIFT)) & SNVS_HPCOMR_SSM_ST_DIS_MASK)
 #define SNVS_HPCOMR_SSM_SFNS_DIS_MASK            (0x4U)
 #define SNVS_HPCOMR_SSM_SFNS_DIS_SHIFT           (2U)
+/*! SSM_SFNS_DIS
+ *  0b0..Soft Fail to Non-Secure State transition is enabled
+ *  0b1..Soft Fail to Non-Secure State transition is disabled
+ */
 #define SNVS_HPCOMR_SSM_SFNS_DIS(x)              (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_SFNS_DIS_SHIFT)) & SNVS_HPCOMR_SSM_SFNS_DIS_MASK)
 #define SNVS_HPCOMR_LP_SWR_MASK                  (0x10U)
 #define SNVS_HPCOMR_LP_SWR_SHIFT                 (4U)
+/*! LP_SWR
+ *  0b0..No Action
+ *  0b1..Reset LP section
+ */
 #define SNVS_HPCOMR_LP_SWR(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_LP_SWR_SHIFT)) & SNVS_HPCOMR_LP_SWR_MASK)
 #define SNVS_HPCOMR_LP_SWR_DIS_MASK              (0x20U)
 #define SNVS_HPCOMR_LP_SWR_DIS_SHIFT             (5U)
+/*! LP_SWR_DIS
+ *  0b0..LP software reset is enabled
+ *  0b1..LP software reset is disabled
+ */
 #define SNVS_HPCOMR_LP_SWR_DIS(x)                (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_LP_SWR_DIS_SHIFT)) & SNVS_HPCOMR_LP_SWR_DIS_MASK)
 #define SNVS_HPCOMR_SW_SV_MASK                   (0x100U)
 #define SNVS_HPCOMR_SW_SV_SHIFT                  (8U)
@@ -21772,18 +34121,38 @@ typedef struct {
 #define SNVS_HPCOMR_SW_LPSV(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_LPSV_SHIFT)) & SNVS_HPCOMR_SW_LPSV_MASK)
 #define SNVS_HPCOMR_PROG_ZMK_MASK                (0x1000U)
 #define SNVS_HPCOMR_PROG_ZMK_SHIFT               (12U)
+/*! PROG_ZMK
+ *  0b0..No Action
+ *  0b1..Activate hardware key programming mechanism
+ */
 #define SNVS_HPCOMR_PROG_ZMK(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_PROG_ZMK_SHIFT)) & SNVS_HPCOMR_PROG_ZMK_MASK)
 #define SNVS_HPCOMR_MKS_EN_MASK                  (0x2000U)
 #define SNVS_HPCOMR_MKS_EN_SHIFT                 (13U)
+/*! MKS_EN
+ *  0b0..OTP master key is selected as an SNVS master key
+ *  0b1..SNVS master key is selected according to the setting of the MASTER_KEY_SEL field of LPMKCR
+ */
 #define SNVS_HPCOMR_MKS_EN(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_MKS_EN_SHIFT)) & SNVS_HPCOMR_MKS_EN_MASK)
 #define SNVS_HPCOMR_HAC_EN_MASK                  (0x10000U)
 #define SNVS_HPCOMR_HAC_EN_SHIFT                 (16U)
+/*! HAC_EN
+ *  0b0..High Assurance Counter is disabled
+ *  0b1..High Assurance Counter is enabled
+ */
 #define SNVS_HPCOMR_HAC_EN(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_EN_SHIFT)) & SNVS_HPCOMR_HAC_EN_MASK)
 #define SNVS_HPCOMR_HAC_LOAD_MASK                (0x20000U)
 #define SNVS_HPCOMR_HAC_LOAD_SHIFT               (17U)
+/*! HAC_LOAD
+ *  0b0..No Action
+ *  0b1..Load the HAC
+ */
 #define SNVS_HPCOMR_HAC_LOAD(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_LOAD_SHIFT)) & SNVS_HPCOMR_HAC_LOAD_MASK)
 #define SNVS_HPCOMR_HAC_CLEAR_MASK               (0x40000U)
 #define SNVS_HPCOMR_HAC_CLEAR_SHIFT              (18U)
+/*! HAC_CLEAR
+ *  0b0..No Action
+ *  0b1..Clear the HAC
+ */
 #define SNVS_HPCOMR_HAC_CLEAR(x)                 (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_CLEAR_SHIFT)) & SNVS_HPCOMR_HAC_CLEAR_MASK)
 #define SNVS_HPCOMR_HAC_STOP_MASK                (0x80000U)
 #define SNVS_HPCOMR_HAC_STOP_SHIFT               (19U)
@@ -21797,27 +34166,79 @@ typedef struct {
 /*! @{ */
 #define SNVS_HPCR_RTC_EN_MASK                    (0x1U)
 #define SNVS_HPCR_RTC_EN_SHIFT                   (0U)
+/*! RTC_EN
+ *  0b0..RTC is disabled
+ *  0b1..RTC is enabled
+ */
 #define SNVS_HPCR_RTC_EN(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_RTC_EN_SHIFT)) & SNVS_HPCR_RTC_EN_MASK)
 #define SNVS_HPCR_HPTA_EN_MASK                   (0x2U)
 #define SNVS_HPCR_HPTA_EN_SHIFT                  (1U)
+/*! HPTA_EN
+ *  0b0..HP Time Alarm Interrupt is disabled
+ *  0b1..HP Time Alarm Interrupt is enabled
+ */
 #define SNVS_HPCR_HPTA_EN(x)                     (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPTA_EN_SHIFT)) & SNVS_HPCR_HPTA_EN_MASK)
 #define SNVS_HPCR_DIS_PI_MASK                    (0x4U)
 #define SNVS_HPCR_DIS_PI_SHIFT                   (2U)
+/*! DIS_PI
+ *  0b0..Periodic interrupt will trigger a functional interrupt
+ *  0b1..Disable periodic interrupt in the function interrupt
+ */
 #define SNVS_HPCR_DIS_PI(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_DIS_PI_SHIFT)) & SNVS_HPCR_DIS_PI_MASK)
 #define SNVS_HPCR_PI_EN_MASK                     (0x8U)
 #define SNVS_HPCR_PI_EN_SHIFT                    (3U)
+/*! PI_EN
+ *  0b0..HP Periodic Interrupt is disabled
+ *  0b1..HP Periodic Interrupt is enabled
+ */
 #define SNVS_HPCR_PI_EN(x)                       (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_PI_EN_SHIFT)) & SNVS_HPCR_PI_EN_MASK)
 #define SNVS_HPCR_PI_FREQ_MASK                   (0xF0U)
 #define SNVS_HPCR_PI_FREQ_SHIFT                  (4U)
+/*! PI_FREQ
+ *  0b0000..- bit 0 of the HPRTCLR is selected as a source of the periodic interrupt
+ *  0b0001..- bit 1 of the HPRTCLR is selected as a source of the periodic interrupt
+ *  0b0010..- bit 2 of the HPRTCLR is selected as a source of the periodic interrupt
+ *  0b0011..- bit 3 of the HPRTCLR is selected as a source of the periodic interrupt
+ *  0b0100..- bit 4 of the HPRTCLR is selected as a source of the periodic interrupt
+ *  0b0101..- bit 5 of the HPRTCLR is selected as a source of the periodic interrupt
+ *  0b0110..- bit 6 of the HPRTCLR is selected as a source of the periodic interrupt
+ *  0b0111..- bit 7 of the HPRTCLR is selected as a source of the periodic interrupt
+ *  0b1000..- bit 8 of the HPRTCLR is selected as a source of the periodic interrupt
+ *  0b1001..- bit 9 of the HPRTCLR is selected as a source of the periodic interrupt
+ *  0b1010..- bit 10 of the HPRTCLR is selected as a source of the periodic interrupt
+ *  0b1011..- bit 11 of the HPRTCLR is selected as a source of the periodic interrupt
+ *  0b1100..- bit 12 of the HPRTCLR is selected as a source of the periodic interrupt
+ *  0b1101..- bit 13 of the HPRTCLR is selected as a source of the periodic interrupt
+ *  0b1110..- bit 14 of the HPRTCLR is selected as a source of the periodic interrupt
+ *  0b1111..- bit 15 of the HPRTCLR is selected as a source of the periodic interrupt
+ */
 #define SNVS_HPCR_PI_FREQ(x)                     (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_PI_FREQ_SHIFT)) & SNVS_HPCR_PI_FREQ_MASK)
 #define SNVS_HPCR_HPCALB_EN_MASK                 (0x100U)
 #define SNVS_HPCR_HPCALB_EN_SHIFT                (8U)
+/*! HPCALB_EN
+ *  0b0..HP Timer calibration disabled
+ *  0b1..HP Timer calibration enabled
+ */
 #define SNVS_HPCR_HPCALB_EN(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPCALB_EN_SHIFT)) & SNVS_HPCR_HPCALB_EN_MASK)
 #define SNVS_HPCR_HPCALB_VAL_MASK                (0x7C00U)
 #define SNVS_HPCR_HPCALB_VAL_SHIFT               (10U)
+/*! HPCALB_VAL
+ *  0b00000..+0 counts per each 32768 ticks of the counter
+ *  0b00001..+1 counts per each 32768 ticks of the counter
+ *  0b00010..+2 counts per each 32768 ticks of the counter
+ *  0b01111..+15 counts per each 32768 ticks of the counter
+ *  0b10000..-16 counts per each 32768 ticks of the counter
+ *  0b10001..-15 counts per each 32768 ticks of the counter
+ *  0b11110..-2 counts per each 32768 ticks of the counter
+ *  0b11111..-1 counts per each 32768 ticks of the counter
+ */
 #define SNVS_HPCR_HPCALB_VAL(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPCALB_VAL_SHIFT)) & SNVS_HPCR_HPCALB_VAL_MASK)
 #define SNVS_HPCR_HP_TS_MASK                     (0x10000U)
 #define SNVS_HPCR_HP_TS_SHIFT                    (16U)
+/*! HP_TS
+ *  0b0..No Action
+ *  0b1..Synchronize the HP Time Counter to the LP Time Counter
+ */
 #define SNVS_HPCR_HP_TS(x)                       (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HP_TS_SHIFT)) & SNVS_HPCR_HP_TS_MASK)
 #define SNVS_HPCR_BTN_CONFIG_MASK                (0x7000000U)
 #define SNVS_HPCR_BTN_CONFIG_SHIFT               (24U)
@@ -21831,24 +34252,52 @@ typedef struct {
 /*! @{ */
 #define SNVS_HPSICR_SV0_EN_MASK                  (0x1U)
 #define SNVS_HPSICR_SV0_EN_SHIFT                 (0U)
+/*! SV0_EN
+ *  0b0..Security Violation 0 Interrupt is Disabled
+ *  0b1..Security Violation 0 Interrupt is Enabled
+ */
 #define SNVS_HPSICR_SV0_EN(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV0_EN_SHIFT)) & SNVS_HPSICR_SV0_EN_MASK)
 #define SNVS_HPSICR_SV1_EN_MASK                  (0x2U)
 #define SNVS_HPSICR_SV1_EN_SHIFT                 (1U)
+/*! SV1_EN
+ *  0b0..Security Violation 1 Interrupt is Disabled
+ *  0b1..Security Violation 1 Interrupt is Enabled
+ */
 #define SNVS_HPSICR_SV1_EN(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV1_EN_SHIFT)) & SNVS_HPSICR_SV1_EN_MASK)
 #define SNVS_HPSICR_SV2_EN_MASK                  (0x4U)
 #define SNVS_HPSICR_SV2_EN_SHIFT                 (2U)
+/*! SV2_EN
+ *  0b0..Security Violation 2 Interrupt is Disabled
+ *  0b1..Security Violation 2 Interrupt is Enabled
+ */
 #define SNVS_HPSICR_SV2_EN(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV2_EN_SHIFT)) & SNVS_HPSICR_SV2_EN_MASK)
 #define SNVS_HPSICR_SV3_EN_MASK                  (0x8U)
 #define SNVS_HPSICR_SV3_EN_SHIFT                 (3U)
+/*! SV3_EN
+ *  0b0..Security Violation 3 Interrupt is Disabled
+ *  0b1..Security Violation 3 Interrupt is Enabled
+ */
 #define SNVS_HPSICR_SV3_EN(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV3_EN_SHIFT)) & SNVS_HPSICR_SV3_EN_MASK)
 #define SNVS_HPSICR_SV4_EN_MASK                  (0x10U)
 #define SNVS_HPSICR_SV4_EN_SHIFT                 (4U)
+/*! SV4_EN
+ *  0b0..Security Violation 4 Interrupt is Disabled
+ *  0b1..Security Violation 4 Interrupt is Enabled
+ */
 #define SNVS_HPSICR_SV4_EN(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV4_EN_SHIFT)) & SNVS_HPSICR_SV4_EN_MASK)
 #define SNVS_HPSICR_SV5_EN_MASK                  (0x20U)
 #define SNVS_HPSICR_SV5_EN_SHIFT                 (5U)
+/*! SV5_EN
+ *  0b0..Security Violation 5 Interrupt is Disabled
+ *  0b1..Security Violation 5 Interrupt is Enabled
+ */
 #define SNVS_HPSICR_SV5_EN(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV5_EN_SHIFT)) & SNVS_HPSICR_SV5_EN_MASK)
 #define SNVS_HPSICR_LPSVI_EN_MASK                (0x80000000U)
 #define SNVS_HPSICR_LPSVI_EN_SHIFT               (31U)
+/*! LPSVI_EN
+ *  0b0..LP Security Violation Interrupt is Disabled
+ *  0b1..LP Security Violation Interrupt is Enabled
+ */
 #define SNVS_HPSICR_LPSVI_EN(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_LPSVI_EN_SHIFT)) & SNVS_HPSICR_LPSVI_EN_MASK)
 /*! @} */
 
@@ -21856,24 +34305,54 @@ typedef struct {
 /*! @{ */
 #define SNVS_HPSVCR_SV0_CFG_MASK                 (0x1U)
 #define SNVS_HPSVCR_SV0_CFG_SHIFT                (0U)
+/*! SV0_CFG
+ *  0b0..Security Violation 0 is a non-fatal violation
+ *  0b1..Security Violation 0 is a fatal violation
+ */
 #define SNVS_HPSVCR_SV0_CFG(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV0_CFG_SHIFT)) & SNVS_HPSVCR_SV0_CFG_MASK)
 #define SNVS_HPSVCR_SV1_CFG_MASK                 (0x2U)
 #define SNVS_HPSVCR_SV1_CFG_SHIFT                (1U)
+/*! SV1_CFG
+ *  0b0..Security Violation 1 is a non-fatal violation
+ *  0b1..Security Violation 1 is a fatal violation
+ */
 #define SNVS_HPSVCR_SV1_CFG(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV1_CFG_SHIFT)) & SNVS_HPSVCR_SV1_CFG_MASK)
 #define SNVS_HPSVCR_SV2_CFG_MASK                 (0x4U)
 #define SNVS_HPSVCR_SV2_CFG_SHIFT                (2U)
+/*! SV2_CFG
+ *  0b0..Security Violation 2 is a non-fatal violation
+ *  0b1..Security Violation 2 is a fatal violation
+ */
 #define SNVS_HPSVCR_SV2_CFG(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV2_CFG_SHIFT)) & SNVS_HPSVCR_SV2_CFG_MASK)
 #define SNVS_HPSVCR_SV3_CFG_MASK                 (0x8U)
 #define SNVS_HPSVCR_SV3_CFG_SHIFT                (3U)
+/*! SV3_CFG
+ *  0b0..Security Violation 3 is a non-fatal violation
+ *  0b1..Security Violation 3 is a fatal violation
+ */
 #define SNVS_HPSVCR_SV3_CFG(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV3_CFG_SHIFT)) & SNVS_HPSVCR_SV3_CFG_MASK)
 #define SNVS_HPSVCR_SV4_CFG_MASK                 (0x10U)
 #define SNVS_HPSVCR_SV4_CFG_SHIFT                (4U)
+/*! SV4_CFG
+ *  0b0..Security Violation 4 is a non-fatal violation
+ *  0b1..Security Violation 4 is a fatal violation
+ */
 #define SNVS_HPSVCR_SV4_CFG(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV4_CFG_SHIFT)) & SNVS_HPSVCR_SV4_CFG_MASK)
 #define SNVS_HPSVCR_SV5_CFG_MASK                 (0x60U)
 #define SNVS_HPSVCR_SV5_CFG_SHIFT                (5U)
+/*! SV5_CFG
+ *  0b00..Security Violation 5 is disabled
+ *  0b01..Security Violation 5 is a non-fatal violation
+ *  0b1x..Security Violation 5 is a fatal violation
+ */
 #define SNVS_HPSVCR_SV5_CFG(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV5_CFG_SHIFT)) & SNVS_HPSVCR_SV5_CFG_MASK)
 #define SNVS_HPSVCR_LPSV_CFG_MASK                (0xC0000000U)
 #define SNVS_HPSVCR_LPSV_CFG_SHIFT               (30U)
+/*! LPSV_CFG
+ *  0b00..LP security violation is disabled
+ *  0b01..LP security violation is a non-fatal violation
+ *  0b1x..LP security violation is a fatal violation
+ */
 #define SNVS_HPSVCR_LPSV_CFG(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_LPSV_CFG_SHIFT)) & SNVS_HPSVCR_LPSV_CFG_MASK)
 /*! @} */
 
@@ -21881,9 +34360,17 @@ typedef struct {
 /*! @{ */
 #define SNVS_HPSR_HPTA_MASK                      (0x1U)
 #define SNVS_HPSR_HPTA_SHIFT                     (0U)
+/*! HPTA
+ *  0b0..No time alarm interrupt occurred.
+ *  0b1..A time alarm interrupt occurred.
+ */
 #define SNVS_HPSR_HPTA(x)                        (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_HPTA_SHIFT)) & SNVS_HPSR_HPTA_MASK)
 #define SNVS_HPSR_PI_MASK                        (0x2U)
 #define SNVS_HPSR_PI_SHIFT                       (1U)
+/*! PI
+ *  0b0..No periodic interrupt occurred.
+ *  0b1..A periodic interrupt occurred.
+ */
 #define SNVS_HPSR_PI(x)                          (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_PI_SHIFT)) & SNVS_HPSR_PI_MASK)
 #define SNVS_HPSR_LPDIS_MASK                     (0x10U)
 #define SNVS_HPSR_LPDIS_SHIFT                    (4U)
@@ -21896,18 +34383,42 @@ typedef struct {
 #define SNVS_HPSR_BI(x)                          (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_BI_SHIFT)) & SNVS_HPSR_BI_MASK)
 #define SNVS_HPSR_SSM_STATE_MASK                 (0xF00U)
 #define SNVS_HPSR_SSM_STATE_SHIFT                (8U)
+/*! SSM_STATE
+ *  0b0000..Init
+ *  0b0001..Hard Fail
+ *  0b0011..Soft Fail
+ *  0b1000..Init Intermediate (transition state between Init and Check - SSM stays in this state only one clock cycle)
+ *  0b1001..Check
+ *  0b1011..Non-Secure
+ *  0b1101..Trusted
+ *  0b1111..Secure
+ */
 #define SNVS_HPSR_SSM_STATE(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_SSM_STATE_SHIFT)) & SNVS_HPSR_SSM_STATE_MASK)
 #define SNVS_HPSR_SECURITY_CONFIG_MASK           (0xF000U)
 #define SNVS_HPSR_SECURITY_CONFIG_SHIFT          (12U)
+/*! SECURITY_CONFIG
+ *  0b0000, 0b1000..FAB configuration
+ *  0b0001, 0b0010, 0b0011..OPEN configuration
+ *  0b1010, 0b1001, 0b1011..CLOSED configuration
+ *  0bx1xx..FIELD RETURN configuration
+ */
 #define SNVS_HPSR_SECURITY_CONFIG(x)             (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_SECURITY_CONFIG_SHIFT)) & SNVS_HPSR_SECURITY_CONFIG_MASK)
 #define SNVS_HPSR_OTPMK_SYNDROME_MASK            (0x1FF0000U)
 #define SNVS_HPSR_OTPMK_SYNDROME_SHIFT           (16U)
 #define SNVS_HPSR_OTPMK_SYNDROME(x)              (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_OTPMK_SYNDROME_SHIFT)) & SNVS_HPSR_OTPMK_SYNDROME_MASK)
 #define SNVS_HPSR_OTPMK_ZERO_MASK                (0x8000000U)
 #define SNVS_HPSR_OTPMK_ZERO_SHIFT               (27U)
+/*! OTPMK_ZERO
+ *  0b0..The OTPMK is not zero.
+ *  0b1..The OTPMK is zero.
+ */
 #define SNVS_HPSR_OTPMK_ZERO(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_OTPMK_ZERO_SHIFT)) & SNVS_HPSR_OTPMK_ZERO_MASK)
 #define SNVS_HPSR_ZMK_ZERO_MASK                  (0x80000000U)
 #define SNVS_HPSR_ZMK_ZERO_SHIFT                 (31U)
+/*! ZMK_ZERO
+ *  0b0..The ZMK is not zero.
+ *  0b1..The ZMK is zero.
+ */
 #define SNVS_HPSR_ZMK_ZERO(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_ZMK_ZERO_SHIFT)) & SNVS_HPSR_ZMK_ZERO_MASK)
 /*! @} */
 
@@ -21915,21 +34426,45 @@ typedef struct {
 /*! @{ */
 #define SNVS_HPSVSR_SV0_MASK                     (0x1U)
 #define SNVS_HPSVSR_SV0_SHIFT                    (0U)
+/*! SV0
+ *  0b0..No Security Violation 0 security violation was detected.
+ *  0b1..Security Violation 0 security violation was detected.
+ */
 #define SNVS_HPSVSR_SV0(x)                       (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV0_SHIFT)) & SNVS_HPSVSR_SV0_MASK)
 #define SNVS_HPSVSR_SV1_MASK                     (0x2U)
 #define SNVS_HPSVSR_SV1_SHIFT                    (1U)
+/*! SV1
+ *  0b0..No Security Violation 1 security violation was detected.
+ *  0b1..Security Violation 1 security violation was detected.
+ */
 #define SNVS_HPSVSR_SV1(x)                       (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV1_SHIFT)) & SNVS_HPSVSR_SV1_MASK)
 #define SNVS_HPSVSR_SV2_MASK                     (0x4U)
 #define SNVS_HPSVSR_SV2_SHIFT                    (2U)
+/*! SV2
+ *  0b0..No Security Violation 2 security violation was detected.
+ *  0b1..Security Violation 2 security violation was detected.
+ */
 #define SNVS_HPSVSR_SV2(x)                       (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV2_SHIFT)) & SNVS_HPSVSR_SV2_MASK)
 #define SNVS_HPSVSR_SV3_MASK                     (0x8U)
 #define SNVS_HPSVSR_SV3_SHIFT                    (3U)
+/*! SV3
+ *  0b0..No Security Violation 3 security violation was detected.
+ *  0b1..Security Violation 3 security violation was detected.
+ */
 #define SNVS_HPSVSR_SV3(x)                       (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV3_SHIFT)) & SNVS_HPSVSR_SV3_MASK)
 #define SNVS_HPSVSR_SV4_MASK                     (0x10U)
 #define SNVS_HPSVSR_SV4_SHIFT                    (4U)
+/*! SV4
+ *  0b0..No Security Violation 4 security violation was detected.
+ *  0b1..Security Violation 4 security violation was detected.
+ */
 #define SNVS_HPSVSR_SV4(x)                       (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV4_SHIFT)) & SNVS_HPSVSR_SV4_MASK)
 #define SNVS_HPSVSR_SV5_MASK                     (0x20U)
 #define SNVS_HPSVSR_SV5_SHIFT                    (5U)
+/*! SV5
+ *  0b0..No Security Violation 5 security violation was detected.
+ *  0b1..Security Violation 5 security violation was detected.
+ */
 #define SNVS_HPSVSR_SV5(x)                       (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV5_SHIFT)) & SNVS_HPSVSR_SV5_MASK)
 #define SNVS_HPSVSR_SW_SV_MASK                   (0x2000U)
 #define SNVS_HPSVSR_SW_SV_SHIFT                  (13U)
@@ -21945,6 +34480,10 @@ typedef struct {
 #define SNVS_HPSVSR_ZMK_SYNDROME(x)              (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_ZMK_SYNDROME_SHIFT)) & SNVS_HPSVSR_ZMK_SYNDROME_MASK)
 #define SNVS_HPSVSR_ZMK_ECC_FAIL_MASK            (0x8000000U)
 #define SNVS_HPSVSR_ZMK_ECC_FAIL_SHIFT           (27U)
+/*! ZMK_ECC_FAIL
+ *  0b0..ZMK ECC Failure was not detected.
+ *  0b1..ZMK ECC Failure was detected.
+ */
 #define SNVS_HPSVSR_ZMK_ECC_FAIL(x)              (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_ZMK_ECC_FAIL_SHIFT)) & SNVS_HPSVSR_ZMK_ECC_FAIL_MASK)
 #define SNVS_HPSVSR_LP_SEC_VIO_MASK              (0x80000000U)
 #define SNVS_HPSVSR_LP_SEC_VIO_SHIFT             (31U)
@@ -21997,30 +34536,66 @@ typedef struct {
 /*! @{ */
 #define SNVS_LPLR_ZMK_WHL_MASK                   (0x1U)
 #define SNVS_LPLR_ZMK_WHL_SHIFT                  (0U)
+/*! ZMK_WHL
+ *  0b0..Write access is allowed.
+ *  0b1..Write access is not allowed.
+ */
 #define SNVS_LPLR_ZMK_WHL(x)                     (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_ZMK_WHL_SHIFT)) & SNVS_LPLR_ZMK_WHL_MASK)
 #define SNVS_LPLR_ZMK_RHL_MASK                   (0x2U)
 #define SNVS_LPLR_ZMK_RHL_SHIFT                  (1U)
+/*! ZMK_RHL
+ *  0b0..Read access is allowed (only in software programming mode).
+ *  0b1..Read access is not allowed.
+ */
 #define SNVS_LPLR_ZMK_RHL(x)                     (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_ZMK_RHL_SHIFT)) & SNVS_LPLR_ZMK_RHL_MASK)
 #define SNVS_LPLR_SRTC_HL_MASK                   (0x4U)
 #define SNVS_LPLR_SRTC_HL_SHIFT                  (2U)
+/*! SRTC_HL
+ *  0b0..Write access is allowed.
+ *  0b1..Write access is not allowed.
+ */
 #define SNVS_LPLR_SRTC_HL(x)                     (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_SRTC_HL_SHIFT)) & SNVS_LPLR_SRTC_HL_MASK)
 #define SNVS_LPLR_LPCALB_HL_MASK                 (0x8U)
 #define SNVS_LPLR_LPCALB_HL_SHIFT                (3U)
+/*! LPCALB_HL
+ *  0b0..Write access is allowed.
+ *  0b1..Write access is not allowed.
+ */
 #define SNVS_LPLR_LPCALB_HL(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPCALB_HL_SHIFT)) & SNVS_LPLR_LPCALB_HL_MASK)
 #define SNVS_LPLR_MC_HL_MASK                     (0x10U)
 #define SNVS_LPLR_MC_HL_SHIFT                    (4U)
+/*! MC_HL
+ *  0b0..Write access (increment) is allowed.
+ *  0b1..Write access (increment) is not allowed.
+ */
 #define SNVS_LPLR_MC_HL(x)                       (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_MC_HL_SHIFT)) & SNVS_LPLR_MC_HL_MASK)
 #define SNVS_LPLR_GPR_HL_MASK                    (0x20U)
 #define SNVS_LPLR_GPR_HL_SHIFT                   (5U)
+/*! GPR_HL
+ *  0b0..Write access is allowed.
+ *  0b1..Write access is not allowed.
+ */
 #define SNVS_LPLR_GPR_HL(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_GPR_HL_SHIFT)) & SNVS_LPLR_GPR_HL_MASK)
 #define SNVS_LPLR_LPSVCR_HL_MASK                 (0x40U)
 #define SNVS_LPLR_LPSVCR_HL_SHIFT                (6U)
+/*! LPSVCR_HL
+ *  0b0..Write access is allowed.
+ *  0b1..Write access is not allowed.
+ */
 #define SNVS_LPLR_LPSVCR_HL(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPSVCR_HL_SHIFT)) & SNVS_LPLR_LPSVCR_HL_MASK)
 #define SNVS_LPLR_LPTDCR_HL_MASK                 (0x100U)
 #define SNVS_LPLR_LPTDCR_HL_SHIFT                (8U)
+/*! LPTDCR_HL
+ *  0b0..Write access is allowed.
+ *  0b1..Write access is not allowed.
+ */
 #define SNVS_LPLR_LPTDCR_HL(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPTDCR_HL_SHIFT)) & SNVS_LPLR_LPTDCR_HL_MASK)
 #define SNVS_LPLR_MKS_HL_MASK                    (0x200U)
 #define SNVS_LPLR_MKS_HL_SHIFT                   (9U)
+/*! MKS_HL
+ *  0b0..Write access is allowed.
+ *  0b1..Write access is not allowed.
+ */
 #define SNVS_LPLR_MKS_HL(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_MKS_HL_SHIFT)) & SNVS_LPLR_MKS_HL_MASK)
 /*! @} */
 
@@ -22028,33 +34603,71 @@ typedef struct {
 /*! @{ */
 #define SNVS_LPCR_SRTC_ENV_MASK                  (0x1U)
 #define SNVS_LPCR_SRTC_ENV_SHIFT                 (0U)
+/*! SRTC_ENV
+ *  0b0..SRTC is disabled or invalid.
+ *  0b1..SRTC is enabled and valid.
+ */
 #define SNVS_LPCR_SRTC_ENV(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_SRTC_ENV_SHIFT)) & SNVS_LPCR_SRTC_ENV_MASK)
 #define SNVS_LPCR_LPTA_EN_MASK                   (0x2U)
 #define SNVS_LPCR_LPTA_EN_SHIFT                  (1U)
+/*! LPTA_EN
+ *  0b0..LP time alarm interrupt is disabled.
+ *  0b1..LP time alarm interrupt is enabled.
+ */
 #define SNVS_LPCR_LPTA_EN(x)                     (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPTA_EN_SHIFT)) & SNVS_LPCR_LPTA_EN_MASK)
 #define SNVS_LPCR_MC_ENV_MASK                    (0x4U)
 #define SNVS_LPCR_MC_ENV_SHIFT                   (2U)
+/*! MC_ENV
+ *  0b0..MC is disabled or invalid.
+ *  0b1..MC is enabled and valid.
+ */
 #define SNVS_LPCR_MC_ENV(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_MC_ENV_SHIFT)) & SNVS_LPCR_MC_ENV_MASK)
 #define SNVS_LPCR_LPWUI_EN_MASK                  (0x8U)
 #define SNVS_LPCR_LPWUI_EN_SHIFT                 (3U)
 #define SNVS_LPCR_LPWUI_EN(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPWUI_EN_SHIFT)) & SNVS_LPCR_LPWUI_EN_MASK)
 #define SNVS_LPCR_SRTC_INV_EN_MASK               (0x10U)
 #define SNVS_LPCR_SRTC_INV_EN_SHIFT              (4U)
+/*! SRTC_INV_EN
+ *  0b0..SRTC stays valid in the case of security violation.
+ *  0b1..SRTC is invalidated in the case of security violation.
+ */
 #define SNVS_LPCR_SRTC_INV_EN(x)                 (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_SRTC_INV_EN_SHIFT)) & SNVS_LPCR_SRTC_INV_EN_MASK)
 #define SNVS_LPCR_DP_EN_MASK                     (0x20U)
 #define SNVS_LPCR_DP_EN_SHIFT                    (5U)
+/*! DP_EN
+ *  0b0..Smart PMIC enabled.
+ *  0b1..Dumb PMIC enabled.
+ */
 #define SNVS_LPCR_DP_EN(x)                       (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_DP_EN_SHIFT)) & SNVS_LPCR_DP_EN_MASK)
 #define SNVS_LPCR_TOP_MASK                       (0x40U)
 #define SNVS_LPCR_TOP_SHIFT                      (6U)
+/*! TOP
+ *  0b0..Leave system power on.
+ *  0b1..Turn off system power.
+ */
 #define SNVS_LPCR_TOP(x)                         (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_TOP_SHIFT)) & SNVS_LPCR_TOP_MASK)
 #define SNVS_LPCR_PWR_GLITCH_EN_MASK             (0x80U)
 #define SNVS_LPCR_PWR_GLITCH_EN_SHIFT            (7U)
 #define SNVS_LPCR_PWR_GLITCH_EN(x)               (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PWR_GLITCH_EN_SHIFT)) & SNVS_LPCR_PWR_GLITCH_EN_MASK)
 #define SNVS_LPCR_LPCALB_EN_MASK                 (0x100U)
 #define SNVS_LPCR_LPCALB_EN_SHIFT                (8U)
+/*! LPCALB_EN
+ *  0b0..SRTC Time calibration is disabled.
+ *  0b1..SRTC Time calibration is enabled.
+ */
 #define SNVS_LPCR_LPCALB_EN(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPCALB_EN_SHIFT)) & SNVS_LPCR_LPCALB_EN_MASK)
 #define SNVS_LPCR_LPCALB_VAL_MASK                (0x7C00U)
 #define SNVS_LPCR_LPCALB_VAL_SHIFT               (10U)
+/*! LPCALB_VAL
+ *  0b00000..+0 counts per each 32768 ticks of the counter clock
+ *  0b00001..+1 counts per each 32768 ticks of the counter clock
+ *  0b00010..+2 counts per each 32768 ticks of the counter clock
+ *  0b01111..+15 counts per each 32768 ticks of the counter clock
+ *  0b10000..-16 counts per each 32768 ticks of the counter clock
+ *  0b10001..-15 counts per each 32768 ticks of the counter clock
+ *  0b11110..-2 counts per each 32768 ticks of the counter clock
+ *  0b11111..-1 counts per each 32768 ticks of the counter clock
+ */
 #define SNVS_LPCR_LPCALB_VAL(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPCALB_VAL_SHIFT)) & SNVS_LPCR_LPCALB_VAL_MASK)
 #define SNVS_LPCR_BTN_PRESS_TIME_MASK            (0x30000U)
 #define SNVS_LPCR_BTN_PRESS_TIME_SHIFT           (16U)
@@ -22080,15 +34693,32 @@ typedef struct {
 /*! @{ */
 #define SNVS_LPMKCR_MASTER_KEY_SEL_MASK          (0x3U)
 #define SNVS_LPMKCR_MASTER_KEY_SEL_SHIFT         (0U)
+/*! MASTER_KEY_SEL
+ *  0b0x..Select one time programmable master key.
+ *  0b10..Select zeroizable master key when MKS_EN bit is set .
+ *  0b11..Select combined master key when MKS_EN bit is set .
+ */
 #define SNVS_LPMKCR_MASTER_KEY_SEL(x)            (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_MASTER_KEY_SEL_SHIFT)) & SNVS_LPMKCR_MASTER_KEY_SEL_MASK)
 #define SNVS_LPMKCR_ZMK_HWP_MASK                 (0x4U)
 #define SNVS_LPMKCR_ZMK_HWP_SHIFT                (2U)
+/*! ZMK_HWP
+ *  0b0..ZMK is in the software programming mode.
+ *  0b1..ZMK is in the hardware programming mode.
+ */
 #define SNVS_LPMKCR_ZMK_HWP(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_HWP_SHIFT)) & SNVS_LPMKCR_ZMK_HWP_MASK)
 #define SNVS_LPMKCR_ZMK_VAL_MASK                 (0x8U)
 #define SNVS_LPMKCR_ZMK_VAL_SHIFT                (3U)
+/*! ZMK_VAL
+ *  0b0..ZMK is not valid.
+ *  0b1..ZMK is valid.
+ */
 #define SNVS_LPMKCR_ZMK_VAL(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_VAL_SHIFT)) & SNVS_LPMKCR_ZMK_VAL_MASK)
 #define SNVS_LPMKCR_ZMK_ECC_EN_MASK              (0x10U)
 #define SNVS_LPMKCR_ZMK_ECC_EN_SHIFT             (4U)
+/*! ZMK_ECC_EN
+ *  0b0..ZMK ECC check is disabled.
+ *  0b1..ZMK ECC check is enabled.
+ */
 #define SNVS_LPMKCR_ZMK_ECC_EN(x)                (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_ECC_EN_SHIFT)) & SNVS_LPMKCR_ZMK_ECC_EN_MASK)
 #define SNVS_LPMKCR_ZMK_ECC_VALUE_MASK           (0xFF80U)
 #define SNVS_LPMKCR_ZMK_ECC_VALUE_SHIFT          (7U)
@@ -22099,21 +34729,45 @@ typedef struct {
 /*! @{ */
 #define SNVS_LPSVCR_SV0_EN_MASK                  (0x1U)
 #define SNVS_LPSVCR_SV0_EN_SHIFT                 (0U)
+/*! SV0_EN
+ *  0b0..Security Violation 0 is disabled in the LP domain.
+ *  0b1..Security Violation 0 is enabled in the LP domain.
+ */
 #define SNVS_LPSVCR_SV0_EN(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV0_EN_SHIFT)) & SNVS_LPSVCR_SV0_EN_MASK)
 #define SNVS_LPSVCR_SV1_EN_MASK                  (0x2U)
 #define SNVS_LPSVCR_SV1_EN_SHIFT                 (1U)
+/*! SV1_EN
+ *  0b0..Security Violation 1 is disabled in the LP domain.
+ *  0b1..Security Violation 1 is enabled in the LP domain.
+ */
 #define SNVS_LPSVCR_SV1_EN(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV1_EN_SHIFT)) & SNVS_LPSVCR_SV1_EN_MASK)
 #define SNVS_LPSVCR_SV2_EN_MASK                  (0x4U)
 #define SNVS_LPSVCR_SV2_EN_SHIFT                 (2U)
+/*! SV2_EN
+ *  0b0..Security Violation 2 is disabled in the LP domain.
+ *  0b1..Security Violation 2 is enabled in the LP domain.
+ */
 #define SNVS_LPSVCR_SV2_EN(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV2_EN_SHIFT)) & SNVS_LPSVCR_SV2_EN_MASK)
 #define SNVS_LPSVCR_SV3_EN_MASK                  (0x8U)
 #define SNVS_LPSVCR_SV3_EN_SHIFT                 (3U)
+/*! SV3_EN
+ *  0b0..Security Violation 3 is disabled in the LP domain.
+ *  0b1..Security Violation 3 is enabled in the LP domain.
+ */
 #define SNVS_LPSVCR_SV3_EN(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV3_EN_SHIFT)) & SNVS_LPSVCR_SV3_EN_MASK)
 #define SNVS_LPSVCR_SV4_EN_MASK                  (0x10U)
 #define SNVS_LPSVCR_SV4_EN_SHIFT                 (4U)
+/*! SV4_EN
+ *  0b0..Security Violation 4 is disabled in the LP domain.
+ *  0b1..Security Violation 4 is enabled in the LP domain.
+ */
 #define SNVS_LPSVCR_SV4_EN(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV4_EN_SHIFT)) & SNVS_LPSVCR_SV4_EN_MASK)
 #define SNVS_LPSVCR_SV5_EN_MASK                  (0x20U)
 #define SNVS_LPSVCR_SV5_EN_SHIFT                 (5U)
+/*! SV5_EN
+ *  0b0..Security Violation 5 is disabled in the LP domain.
+ *  0b1..Security Violation 5 is enabled in the LP domain.
+ */
 #define SNVS_LPSVCR_SV5_EN(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV5_EN_SHIFT)) & SNVS_LPSVCR_SV5_EN_MASK)
 /*! @} */
 
@@ -22121,15 +34775,31 @@ typedef struct {
 /*! @{ */
 #define SNVS_LPTDCR_SRTCR_EN_MASK                (0x2U)
 #define SNVS_LPTDCR_SRTCR_EN_SHIFT               (1U)
+/*! SRTCR_EN
+ *  0b0..SRTC rollover is disabled.
+ *  0b1..SRTC rollover is enabled.
+ */
 #define SNVS_LPTDCR_SRTCR_EN(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_SRTCR_EN_SHIFT)) & SNVS_LPTDCR_SRTCR_EN_MASK)
 #define SNVS_LPTDCR_MCR_EN_MASK                  (0x4U)
 #define SNVS_LPTDCR_MCR_EN_SHIFT                 (2U)
+/*! MCR_EN
+ *  0b0..MC rollover is disabled.
+ *  0b1..MC rollover is enabled.
+ */
 #define SNVS_LPTDCR_MCR_EN(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_MCR_EN_SHIFT)) & SNVS_LPTDCR_MCR_EN_MASK)
 #define SNVS_LPTDCR_ET1_EN_MASK                  (0x200U)
 #define SNVS_LPTDCR_ET1_EN_SHIFT                 (9U)
+/*! ET1_EN
+ *  0b0..External tamper 1 is disabled.
+ *  0b1..External tamper 1 is enabled.
+ */
 #define SNVS_LPTDCR_ET1_EN(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_ET1_EN_SHIFT)) & SNVS_LPTDCR_ET1_EN_MASK)
 #define SNVS_LPTDCR_ET1P_MASK                    (0x800U)
 #define SNVS_LPTDCR_ET1P_SHIFT                   (11U)
+/*! ET1P
+ *  0b0..External tamper 1 is active low.
+ *  0b1..External tamper 1 is active high.
+ */
 #define SNVS_LPTDCR_ET1P(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_ET1P_SHIFT)) & SNVS_LPTDCR_ET1P_MASK)
 #define SNVS_LPTDCR_PFD_OBSERV_MASK              (0x4000U)
 #define SNVS_LPTDCR_PFD_OBSERV_SHIFT             (14U)
@@ -22139,6 +34809,10 @@ typedef struct {
 #define SNVS_LPTDCR_POR_OBSERV(x)                (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_POR_OBSERV_SHIFT)) & SNVS_LPTDCR_POR_OBSERV_MASK)
 #define SNVS_LPTDCR_OSCB_MASK                    (0x10000000U)
 #define SNVS_LPTDCR_OSCB_SHIFT                   (28U)
+/*! OSCB
+ *  0b0..Normal SRTC clock oscillator not bypassed.
+ *  0b1..Normal SRTC clock oscillator bypassed. Alternate clock can drive the SRTC clock source.
+ */
 #define SNVS_LPTDCR_OSCB(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_OSCB_SHIFT)) & SNVS_LPTDCR_OSCB_MASK)
 /*! @} */
 
@@ -22146,36 +34820,76 @@ typedef struct {
 /*! @{ */
 #define SNVS_LPSR_LPTA_MASK                      (0x1U)
 #define SNVS_LPSR_LPTA_SHIFT                     (0U)
+/*! LPTA
+ *  0b0..No time alarm interrupt occurred.
+ *  0b1..A time alarm interrupt occurred.
+ */
 #define SNVS_LPSR_LPTA(x)                        (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPTA_SHIFT)) & SNVS_LPSR_LPTA_MASK)
 #define SNVS_LPSR_SRTCR_MASK                     (0x2U)
 #define SNVS_LPSR_SRTCR_SHIFT                    (1U)
+/*! SRTCR
+ *  0b0..SRTC has not reached its maximum value.
+ *  0b1..SRTC has reached its maximum value.
+ */
 #define SNVS_LPSR_SRTCR(x)                       (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SRTCR_SHIFT)) & SNVS_LPSR_SRTCR_MASK)
 #define SNVS_LPSR_MCR_MASK                       (0x4U)
 #define SNVS_LPSR_MCR_SHIFT                      (2U)
+/*! MCR
+ *  0b0..MC has not reached its maximum value.
+ *  0b1..MC has reached its maximum value.
+ */
 #define SNVS_LPSR_MCR(x)                         (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_MCR_SHIFT)) & SNVS_LPSR_MCR_MASK)
 #define SNVS_LPSR_PGD_MASK                       (0x8U)
 #define SNVS_LPSR_PGD_SHIFT                      (3U)
 #define SNVS_LPSR_PGD(x)                         (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_PGD_SHIFT)) & SNVS_LPSR_PGD_MASK)
 #define SNVS_LPSR_ET1D_MASK                      (0x200U)
 #define SNVS_LPSR_ET1D_SHIFT                     (9U)
+/*! ET1D
+ *  0b0..External tampering 1 not detected.
+ *  0b1..External tampering 1 detected.
+ */
 #define SNVS_LPSR_ET1D(x)                        (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_ET1D_SHIFT)) & SNVS_LPSR_ET1D_MASK)
 #define SNVS_LPSR_ESVD_MASK                      (0x10000U)
 #define SNVS_LPSR_ESVD_SHIFT                     (16U)
+/*! ESVD
+ *  0b0..No external security violation.
+ *  0b1..External security violation is detected.
+ */
 #define SNVS_LPSR_ESVD(x)                        (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_ESVD_SHIFT)) & SNVS_LPSR_ESVD_MASK)
 #define SNVS_LPSR_EO_MASK                        (0x20000U)
 #define SNVS_LPSR_EO_SHIFT                       (17U)
+/*! EO
+ *  0b0..Emergency off was not detected.
+ *  0b1..Emergency off was detected.
+ */
 #define SNVS_LPSR_EO(x)                          (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_EO_SHIFT)) & SNVS_LPSR_EO_MASK)
 #define SNVS_LPSR_SPO_MASK                       (0x40000U)
 #define SNVS_LPSR_SPO_SHIFT                      (18U)
+/*! SPO
+ *  0b0..Set Power Off was not detected.
+ *  0b1..Set Power Off was detected.
+ */
 #define SNVS_LPSR_SPO(x)                         (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SPO_SHIFT)) & SNVS_LPSR_SPO_MASK)
 #define SNVS_LPSR_SED_MASK                       (0x100000U)
 #define SNVS_LPSR_SED_SHIFT                      (20U)
+/*! SED
+ *  0b0..Scan exit was not detected.
+ *  0b1..Scan exit was detected.
+ */
 #define SNVS_LPSR_SED(x)                         (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SED_SHIFT)) & SNVS_LPSR_SED_MASK)
 #define SNVS_LPSR_LPNS_MASK                      (0x40000000U)
 #define SNVS_LPSR_LPNS_SHIFT                     (30U)
+/*! LPNS
+ *  0b0..LP section was not programmed in the non-secure state.
+ *  0b1..LP section was programmed in the non-secure state.
+ */
 #define SNVS_LPSR_LPNS(x)                        (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPNS_SHIFT)) & SNVS_LPSR_LPNS_MASK)
 #define SNVS_LPSR_LPS_MASK                       (0x80000000U)
 #define SNVS_LPSR_LPS_SHIFT                      (31U)
+/*! LPS
+ *  0b0..LP section was not programmed in secure or trusted state.
+ *  0b1..LP section was programmed in secure or trusted state.
+ */
 #define SNVS_LPSR_LPS(x)                         (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPS_SHIFT)) & SNVS_LPSR_LPS_MASK)
 /*! @} */
 
@@ -22363,12 +35077,27 @@ typedef struct {
 /*! @{ */
 #define SPDIF_SCR_USRC_SEL_MASK                  (0x3U)
 #define SPDIF_SCR_USRC_SEL_SHIFT                 (0U)
+/*! USrc_Sel
+ *  0b00..No embedded U channel
+ *  0b01..U channel from SPDIF receive block (CD mode)
+ *  0b10..Reserved
+ *  0b11..U channel from on chip transmitter
+ */
 #define SPDIF_SCR_USRC_SEL(x)                    (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_USRC_SEL_SHIFT)) & SPDIF_SCR_USRC_SEL_MASK)
 #define SPDIF_SCR_TXSEL_MASK                     (0x1CU)
 #define SPDIF_SCR_TXSEL_SHIFT                    (2U)
+/*! TxSel
+ *  0b000..Off and output 0
+ *  0b001..Feed-through SPDIFIN
+ *  0b101..Tx Normal operation
+ */
 #define SPDIF_SCR_TXSEL(x)                       (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXSEL_SHIFT)) & SPDIF_SCR_TXSEL_MASK)
 #define SPDIF_SCR_VALCTRL_MASK                   (0x20U)
 #define SPDIF_SCR_VALCTRL_SHIFT                  (5U)
+/*! ValCtrl
+ *  0b0..Outgoing Validity always set
+ *  0b1..Outgoing Validity always clear
+ */
 #define SPDIF_SCR_VALCTRL(x)                     (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_VALCTRL_SHIFT)) & SPDIF_SCR_VALCTRL_MASK)
 #define SPDIF_SCR_DMA_TX_EN_MASK                 (0x100U)
 #define SPDIF_SCR_DMA_TX_EN_SHIFT                (8U)
@@ -22378,6 +35107,12 @@ typedef struct {
 #define SPDIF_SCR_DMA_RX_EN(x)                   (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_DMA_RX_EN_SHIFT)) & SPDIF_SCR_DMA_RX_EN_MASK)
 #define SPDIF_SCR_TXFIFO_CTRL_MASK               (0xC00U)
 #define SPDIF_SCR_TXFIFO_CTRL_SHIFT              (10U)
+/*! TxFIFO_Ctrl
+ *  0b00..Send out digital zero on SPDIF Tx
+ *  0b01..Tx Normal operation
+ *  0b10..Reset to 1 sample remaining
+ *  0b11..Reserved
+ */
 #define SPDIF_SCR_TXFIFO_CTRL(x)                 (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXFIFO_CTRL_SHIFT)) & SPDIF_SCR_TXFIFO_CTRL_MASK)
 #define SPDIF_SCR_SOFT_RESET_MASK                (0x1000U)
 #define SPDIF_SCR_SOFT_RESET_SHIFT               (12U)
@@ -22387,24 +35122,56 @@ typedef struct {
 #define SPDIF_SCR_LOW_POWER(x)                   (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_LOW_POWER_SHIFT)) & SPDIF_SCR_LOW_POWER_MASK)
 #define SPDIF_SCR_TXFIFOEMPTY_SEL_MASK           (0x18000U)
 #define SPDIF_SCR_TXFIFOEMPTY_SEL_SHIFT          (15U)
+/*! TxFIFOEmpty_Sel
+ *  0b00..Empty interrupt if 0 sample in Tx left and right FIFOs
+ *  0b01..Empty interrupt if at most 4 sample in Tx left and right FIFOs
+ *  0b10..Empty interrupt if at most 8 sample in Tx left and right FIFOs
+ *  0b11..Empty interrupt if at most 12 sample in Tx left and right FIFOs
+ */
 #define SPDIF_SCR_TXFIFOEMPTY_SEL(x)             (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXFIFOEMPTY_SEL_SHIFT)) & SPDIF_SCR_TXFIFOEMPTY_SEL_MASK)
 #define SPDIF_SCR_TXAUTOSYNC_MASK                (0x20000U)
 #define SPDIF_SCR_TXAUTOSYNC_SHIFT               (17U)
+/*! TxAutoSync
+ *  0b0..Tx FIFO auto sync off
+ *  0b1..Tx FIFO auto sync on
+ */
 #define SPDIF_SCR_TXAUTOSYNC(x)                  (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXAUTOSYNC_SHIFT)) & SPDIF_SCR_TXAUTOSYNC_MASK)
 #define SPDIF_SCR_RXAUTOSYNC_MASK                (0x40000U)
 #define SPDIF_SCR_RXAUTOSYNC_SHIFT               (18U)
+/*! RxAutoSync
+ *  0b0..Rx FIFO auto sync off
+ *  0b1..RxFIFO auto sync on
+ */
 #define SPDIF_SCR_RXAUTOSYNC(x)                  (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXAUTOSYNC_SHIFT)) & SPDIF_SCR_RXAUTOSYNC_MASK)
 #define SPDIF_SCR_RXFIFOFULL_SEL_MASK            (0x180000U)
 #define SPDIF_SCR_RXFIFOFULL_SEL_SHIFT           (19U)
+/*! RxFIFOFull_Sel
+ *  0b00..Full interrupt if at least 1 sample in Rx left and right FIFOs
+ *  0b01..Full interrupt if at least 4 sample in Rx left and right FIFOs
+ *  0b10..Full interrupt if at least 8 sample in Rx left and right FIFOs
+ *  0b11..Full interrupt if at least 16 sample in Rx left and right FIFO
+ */
 #define SPDIF_SCR_RXFIFOFULL_SEL(x)              (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFOFULL_SEL_SHIFT)) & SPDIF_SCR_RXFIFOFULL_SEL_MASK)
 #define SPDIF_SCR_RXFIFO_RST_MASK                (0x200000U)
 #define SPDIF_SCR_RXFIFO_RST_SHIFT               (21U)
+/*! RxFIFO_Rst
+ *  0b0..Normal operation
+ *  0b1..Reset register to 1 sample remaining
+ */
 #define SPDIF_SCR_RXFIFO_RST(x)                  (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_RST_SHIFT)) & SPDIF_SCR_RXFIFO_RST_MASK)
 #define SPDIF_SCR_RXFIFO_OFF_ON_MASK             (0x400000U)
 #define SPDIF_SCR_RXFIFO_OFF_ON_SHIFT            (22U)
+/*! RxFIFO_Off_On
+ *  0b0..SPDIF Rx FIFO is on
+ *  0b1..SPDIF Rx FIFO is off. Does not accept data from interface
+ */
 #define SPDIF_SCR_RXFIFO_OFF_ON(x)               (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_OFF_ON_SHIFT)) & SPDIF_SCR_RXFIFO_OFF_ON_MASK)
 #define SPDIF_SCR_RXFIFO_CTRL_MASK               (0x800000U)
 #define SPDIF_SCR_RXFIFO_CTRL_SHIFT              (23U)
+/*! RxFIFO_Ctrl
+ *  0b0..Normal operation
+ *  0b1..Always read zero from Rx data register
+ */
 #define SPDIF_SCR_RXFIFO_CTRL(x)                 (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_CTRL_SHIFT)) & SPDIF_SCR_RXFIFO_CTRL_MASK)
 /*! @} */
 
@@ -22412,6 +35179,10 @@ typedef struct {
 /*! @{ */
 #define SPDIF_SRCD_USYNCMODE_MASK                (0x2U)
 #define SPDIF_SRCD_USYNCMODE_SHIFT               (1U)
+/*! USyncMode
+ *  0b0..Non-CD data
+ *  0b1..CD user channel subcode
+ */
 #define SPDIF_SRCD_USYNCMODE(x)                  (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCD_USYNCMODE_SHIFT)) & SPDIF_SRCD_USYNCMODE_MASK)
 /*! @} */
 
@@ -22419,12 +35190,29 @@ typedef struct {
 /*! @{ */
 #define SPDIF_SRPC_GAINSEL_MASK                  (0x38U)
 #define SPDIF_SRPC_GAINSEL_SHIFT                 (3U)
+/*! GainSel
+ *  0b000..24*(2**10)
+ *  0b001..16*(2**10)
+ *  0b010..12*(2**10)
+ *  0b011..8*(2**10)
+ *  0b100..6*(2**10)
+ *  0b101..4*(2**10)
+ *  0b110..3*(2**10)
+ */
 #define SPDIF_SRPC_GAINSEL(x)                    (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_GAINSEL_SHIFT)) & SPDIF_SRPC_GAINSEL_MASK)
 #define SPDIF_SRPC_LOCK_MASK                     (0x40U)
 #define SPDIF_SRPC_LOCK_SHIFT                    (6U)
 #define SPDIF_SRPC_LOCK(x)                       (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_LOCK_SHIFT)) & SPDIF_SRPC_LOCK_MASK)
 #define SPDIF_SRPC_CLKSRC_SEL_MASK               (0x780U)
 #define SPDIF_SRPC_CLKSRC_SEL_SHIFT              (7U)
+/*! ClkSrc_Sel
+ *  0b0000..if (DPLL Locked) SPDIF_RxClk else REF_CLK_32K (XTALOSC)
+ *  0b0001..if (DPLL Locked) SPDIF_RxClk else tx_clk (SPDIF0_CLK_ROOT)
+ *  0b0011..if (DPLL Locked) SPDIF_RxClk else SPDIF_EXT_CLK
+ *  0b0101..REF_CLK_32K (XTALOSC)
+ *  0b0110..tx_clk (SPDIF0_CLK_ROOT)
+ *  0b1000..SPDIF_EXT_CLK
+ */
 #define SPDIF_SRPC_CLKSRC_SEL(x)                 (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_CLKSRC_SEL_SHIFT)) & SPDIF_SRPC_CLKSRC_SEL_MASK)
 /*! @} */
 
@@ -22671,15 +35459,35 @@ typedef struct {
 /*! @{ */
 #define SPDIF_STC_TXCLK_DF_MASK                  (0x7FU)
 #define SPDIF_STC_TXCLK_DF_SHIFT                 (0U)
+/*! TxClk_DF
+ *  0b0000000..divider factor is 1
+ *  0b0000001..divider factor is 2
+ *  0b1111111..divider factor is 128
+ */
 #define SPDIF_STC_TXCLK_DF(x)                    (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TXCLK_DF_SHIFT)) & SPDIF_STC_TXCLK_DF_MASK)
 #define SPDIF_STC_TX_ALL_CLK_EN_MASK             (0x80U)
 #define SPDIF_STC_TX_ALL_CLK_EN_SHIFT            (7U)
+/*! tx_all_clk_en
+ *  0b0..disable transfer clock.
+ *  0b1..enable transfer clock.
+ */
 #define SPDIF_STC_TX_ALL_CLK_EN(x)               (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TX_ALL_CLK_EN_SHIFT)) & SPDIF_STC_TX_ALL_CLK_EN_MASK)
 #define SPDIF_STC_TXCLK_SOURCE_MASK              (0x700U)
 #define SPDIF_STC_TXCLK_SOURCE_SHIFT             (8U)
+/*! TxClk_Source
+ *  0b000..REF_CLK_32K input (XTALOSC 32 kHz clock)
+ *  0b001..tx_clk input (from SPDIF0_CLK_ROOT. See CCM.)
+ *  0b011..SPDIF_EXT_CLK, from pads
+ *  0b101..ipg_clk input (frequency divided)
+ */
 #define SPDIF_STC_TXCLK_SOURCE(x)                (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TXCLK_SOURCE_SHIFT)) & SPDIF_STC_TXCLK_SOURCE_MASK)
 #define SPDIF_STC_SYSCLK_DF_MASK                 (0xFF800U)
 #define SPDIF_STC_SYSCLK_DF_SHIFT                (11U)
+/*! SYSCLK_DF
+ *  0b000000000..no clock signal
+ *  0b000000001..divider factor is 2
+ *  0b111111111..divider factor is 512
+ */
 #define SPDIF_STC_SYSCLK_DF(x)                   (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_SYSCLK_DF_SHIFT)) & SPDIF_STC_SYSCLK_DF_MASK)
 /*! @} */
 
@@ -22738,18 +35546,38 @@ typedef struct {
 /*! @{ */
 #define SRC_SCR_MASK_WDOG_RST_MASK               (0x780U)
 #define SRC_SCR_MASK_WDOG_RST_SHIFT              (7U)
+/*! mask_wdog_rst
+ *  0b0101..wdog_rst_b is masked
+ *  0b1010..wdog_rst_b is not masked (default)
+ */
 #define SRC_SCR_MASK_WDOG_RST(x)                 (((uint32_t)(((uint32_t)(x)) << SRC_SCR_MASK_WDOG_RST_SHIFT)) & SRC_SCR_MASK_WDOG_RST_MASK)
 #define SRC_SCR_CORE0_RST_MASK                   (0x2000U)
 #define SRC_SCR_CORE0_RST_SHIFT                  (13U)
+/*! core0_rst
+ *  0b0..do not assert core0 reset
+ *  0b1..assert core0 reset
+ */
 #define SRC_SCR_CORE0_RST(x)                     (((uint32_t)(((uint32_t)(x)) << SRC_SCR_CORE0_RST_SHIFT)) & SRC_SCR_CORE0_RST_MASK)
 #define SRC_SCR_CORE0_DBG_RST_MASK               (0x20000U)
 #define SRC_SCR_CORE0_DBG_RST_SHIFT              (17U)
+/*! core0_dbg_rst
+ *  0b0..do not assert core0 debug reset
+ *  0b1..assert core0 debug reset
+ */
 #define SRC_SCR_CORE0_DBG_RST(x)                 (((uint32_t)(((uint32_t)(x)) << SRC_SCR_CORE0_DBG_RST_SHIFT)) & SRC_SCR_CORE0_DBG_RST_MASK)
 #define SRC_SCR_DBG_RST_MSK_PG_MASK              (0x2000000U)
 #define SRC_SCR_DBG_RST_MSK_PG_SHIFT             (25U)
+/*! dbg_rst_msk_pg
+ *  0b0..do not mask core debug resets (debug resets will be asserted after power gating event)
+ *  0b1..mask core debug resets (debug resets won't be asserted after power gating event)
+ */
 #define SRC_SCR_DBG_RST_MSK_PG(x)                (((uint32_t)(((uint32_t)(x)) << SRC_SCR_DBG_RST_MSK_PG_SHIFT)) & SRC_SCR_DBG_RST_MSK_PG_MASK)
 #define SRC_SCR_MASK_WDOG3_RST_MASK              (0xF0000000U)
 #define SRC_SCR_MASK_WDOG3_RST_SHIFT             (28U)
+/*! mask_wdog3_rst
+ *  0b0101..wdog3_rst_b is masked
+ *  0b1010..wdog3_rst_b is not masked
+ */
 #define SRC_SCR_MASK_WDOG3_RST(x)                (((uint32_t)(((uint32_t)(x)) << SRC_SCR_MASK_WDOG3_RST_SHIFT)) & SRC_SCR_MASK_WDOG3_RST_MASK)
 /*! @} */
 
@@ -22773,30 +35601,66 @@ typedef struct {
 /*! @{ */
 #define SRC_SRSR_IPP_RESET_B_MASK                (0x1U)
 #define SRC_SRSR_IPP_RESET_B_SHIFT               (0U)
+/*! ipp_reset_b
+ *  0b0..Reset is not a result of ipp_reset_b pin.
+ *  0b1..Reset is a result of ipp_reset_b pin.
+ */
 #define SRC_SRSR_IPP_RESET_B(x)                  (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_RESET_B_SHIFT)) & SRC_SRSR_IPP_RESET_B_MASK)
 #define SRC_SRSR_LOCKUP_SYSRESETREQ_MASK         (0x2U)
 #define SRC_SRSR_LOCKUP_SYSRESETREQ_SHIFT        (1U)
+/*! lockup_sysresetreq
+ *  0b0..Reset is not a result of the mentioned case.
+ *  0b1..Reset is a result of the mentioned case.
+ */
 #define SRC_SRSR_LOCKUP_SYSRESETREQ(x)           (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_LOCKUP_SYSRESETREQ_SHIFT)) & SRC_SRSR_LOCKUP_SYSRESETREQ_MASK)
 #define SRC_SRSR_CSU_RESET_B_MASK                (0x4U)
 #define SRC_SRSR_CSU_RESET_B_SHIFT               (2U)
+/*! csu_reset_b
+ *  0b0..Reset is not a result of the csu_reset_b event.
+ *  0b1..Reset is a result of the csu_reset_b event.
+ */
 #define SRC_SRSR_CSU_RESET_B(x)                  (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_CSU_RESET_B_SHIFT)) & SRC_SRSR_CSU_RESET_B_MASK)
 #define SRC_SRSR_IPP_USER_RESET_B_MASK           (0x8U)
 #define SRC_SRSR_IPP_USER_RESET_B_SHIFT          (3U)
+/*! ipp_user_reset_b
+ *  0b0..Reset is not a result of the ipp_user_reset_b qualified as COLD reset event.
+ *  0b1..Reset is a result of the ipp_user_reset_b qualified as COLD reset event.
+ */
 #define SRC_SRSR_IPP_USER_RESET_B(x)             (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_USER_RESET_B_SHIFT)) & SRC_SRSR_IPP_USER_RESET_B_MASK)
 #define SRC_SRSR_WDOG_RST_B_MASK                 (0x10U)
 #define SRC_SRSR_WDOG_RST_B_SHIFT                (4U)
+/*! wdog_rst_b
+ *  0b0..Reset is not a result of the watchdog time-out event.
+ *  0b1..Reset is a result of the watchdog time-out event.
+ */
 #define SRC_SRSR_WDOG_RST_B(x)                   (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG_RST_B_SHIFT)) & SRC_SRSR_WDOG_RST_B_MASK)
 #define SRC_SRSR_JTAG_RST_B_MASK                 (0x20U)
 #define SRC_SRSR_JTAG_RST_B_SHIFT                (5U)
+/*! jtag_rst_b
+ *  0b0..Reset is not a result of HIGH-Z reset from JTAG.
+ *  0b1..Reset is a result of HIGH-Z reset from JTAG.
+ */
 #define SRC_SRSR_JTAG_RST_B(x)                   (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_RST_B_SHIFT)) & SRC_SRSR_JTAG_RST_B_MASK)
 #define SRC_SRSR_JTAG_SW_RST_MASK                (0x40U)
 #define SRC_SRSR_JTAG_SW_RST_SHIFT               (6U)
+/*! jtag_sw_rst
+ *  0b0..Reset is not a result of software reset from JTAG.
+ *  0b1..Reset is a result of software reset from JTAG.
+ */
 #define SRC_SRSR_JTAG_SW_RST(x)                  (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_SW_RST_SHIFT)) & SRC_SRSR_JTAG_SW_RST_MASK)
 #define SRC_SRSR_WDOG3_RST_B_MASK                (0x80U)
 #define SRC_SRSR_WDOG3_RST_B_SHIFT               (7U)
+/*! wdog3_rst_b
+ *  0b0..Reset is not a result of the watchdog3 time-out event.
+ *  0b1..Reset is a result of the watchdog3 time-out event.
+ */
 #define SRC_SRSR_WDOG3_RST_B(x)                  (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG3_RST_B_SHIFT)) & SRC_SRSR_WDOG3_RST_B_MASK)
 #define SRC_SRSR_TEMPSENSE_RST_B_MASK            (0x100U)
 #define SRC_SRSR_TEMPSENSE_RST_B_SHIFT           (8U)
+/*! tempsense_rst_b
+ *  0b0..Reset is not a result of software reset from Temperature Sensor.
+ *  0b1..Reset is a result of software reset from Temperature Sensor.
+ */
 #define SRC_SRSR_TEMPSENSE_RST_B(x)              (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_TEMPSENSE_RST_B_SHIFT)) & SRC_SRSR_TEMPSENSE_RST_B_MASK)
 /*! @} */
 
@@ -22918,12 +35782,24 @@ typedef struct {
 /*! @{ */
 #define TEMPMON_TEMPSENSE0_POWER_DOWN_MASK       (0x1U)
 #define TEMPMON_TEMPSENSE0_POWER_DOWN_SHIFT      (0U)
+/*! POWER_DOWN
+ *  0b0..Enable power to the temperature sensor.
+ *  0b1..Power down the temperature sensor.
+ */
 #define TEMPMON_TEMPSENSE0_POWER_DOWN(x)         (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_POWER_DOWN_MASK)
 #define TEMPMON_TEMPSENSE0_MEASURE_TEMP_MASK     (0x2U)
 #define TEMPMON_TEMPSENSE0_MEASURE_TEMP_SHIFT    (1U)
+/*! MEASURE_TEMP
+ *  0b0..Do not start the measurement process.
+ *  0b1..Start the measurement process.
+ */
 #define TEMPMON_TEMPSENSE0_MEASURE_TEMP(x)       (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_MEASURE_TEMP_SHIFT)) & TEMPMON_TEMPSENSE0_MEASURE_TEMP_MASK)
 #define TEMPMON_TEMPSENSE0_FINISHED_MASK         (0x4U)
 #define TEMPMON_TEMPSENSE0_FINISHED_SHIFT        (2U)
+/*! FINISHED
+ *  0b0..Last measurement is not ready yet.
+ *  0b1..Last measurement is valid.
+ */
 #define TEMPMON_TEMPSENSE0_FINISHED(x)           (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_FINISHED_MASK)
 #define TEMPMON_TEMPSENSE0_TEMP_CNT_MASK         (0xFFF00U)
 #define TEMPMON_TEMPSENSE0_TEMP_CNT_SHIFT        (8U)
@@ -22937,12 +35813,24 @@ typedef struct {
 /*! @{ */
 #define TEMPMON_TEMPSENSE0_SET_POWER_DOWN_MASK   (0x1U)
 #define TEMPMON_TEMPSENSE0_SET_POWER_DOWN_SHIFT  (0U)
+/*! POWER_DOWN
+ *  0b0..Enable power to the temperature sensor.
+ *  0b1..Power down the temperature sensor.
+ */
 #define TEMPMON_TEMPSENSE0_SET_POWER_DOWN(x)     (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_SET_POWER_DOWN_MASK)
 #define TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_MASK (0x2U)
 #define TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_SHIFT (1U)
+/*! MEASURE_TEMP
+ *  0b0..Do not start the measurement process.
+ *  0b1..Start the measurement process.
+ */
 #define TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP(x)   (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_SHIFT)) & TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_MASK)
 #define TEMPMON_TEMPSENSE0_SET_FINISHED_MASK     (0x4U)
 #define TEMPMON_TEMPSENSE0_SET_FINISHED_SHIFT    (2U)
+/*! FINISHED
+ *  0b0..Last measurement is not ready yet.
+ *  0b1..Last measurement is valid.
+ */
 #define TEMPMON_TEMPSENSE0_SET_FINISHED(x)       (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_SET_FINISHED_MASK)
 #define TEMPMON_TEMPSENSE0_SET_TEMP_CNT_MASK     (0xFFF00U)
 #define TEMPMON_TEMPSENSE0_SET_TEMP_CNT_SHIFT    (8U)
@@ -22956,12 +35844,24 @@ typedef struct {
 /*! @{ */
 #define TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_MASK   (0x1U)
 #define TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_SHIFT  (0U)
+/*! POWER_DOWN
+ *  0b0..Enable power to the temperature sensor.
+ *  0b1..Power down the temperature sensor.
+ */
 #define TEMPMON_TEMPSENSE0_CLR_POWER_DOWN(x)     (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_MASK)
 #define TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_MASK (0x2U)
 #define TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_SHIFT (1U)
+/*! MEASURE_TEMP
+ *  0b0..Do not start the measurement process.
+ *  0b1..Start the measurement process.
+ */
 #define TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP(x)   (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_MASK)
 #define TEMPMON_TEMPSENSE0_CLR_FINISHED_MASK     (0x4U)
 #define TEMPMON_TEMPSENSE0_CLR_FINISHED_SHIFT    (2U)
+/*! FINISHED
+ *  0b0..Last measurement is not ready yet.
+ *  0b1..Last measurement is valid.
+ */
 #define TEMPMON_TEMPSENSE0_CLR_FINISHED(x)       (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_FINISHED_MASK)
 #define TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_MASK     (0xFFF00U)
 #define TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_SHIFT    (8U)
@@ -22975,12 +35875,24 @@ typedef struct {
 /*! @{ */
 #define TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_MASK   (0x1U)
 #define TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_SHIFT  (0U)
+/*! POWER_DOWN
+ *  0b0..Enable power to the temperature sensor.
+ *  0b1..Power down the temperature sensor.
+ */
 #define TEMPMON_TEMPSENSE0_TOG_POWER_DOWN(x)     (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_MASK)
 #define TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_MASK (0x2U)
 #define TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_SHIFT (1U)
+/*! MEASURE_TEMP
+ *  0b0..Do not start the measurement process.
+ *  0b1..Start the measurement process.
+ */
 #define TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP(x)   (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_MASK)
 #define TEMPMON_TEMPSENSE0_TOG_FINISHED_MASK     (0x4U)
 #define TEMPMON_TEMPSENSE0_TOG_FINISHED_SHIFT    (2U)
+/*! FINISHED
+ *  0b0..Last measurement is not ready yet.
+ *  0b1..Last measurement is valid.
+ */
 #define TEMPMON_TEMPSENSE0_TOG_FINISHED(x)       (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_FINISHED_MASK)
 #define TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_MASK     (0xFFF00U)
 #define TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_SHIFT    (8U)
@@ -23182,27 +36094,97 @@ typedef struct {
 /*! @{ */
 #define TMR_CTRL_OUTMODE_MASK                    (0x7U)
 #define TMR_CTRL_OUTMODE_SHIFT                   (0U)
+/*! OUTMODE - Output Mode
+ *  0b000..Asserted while counter is active
+ *  0b001..Clear OFLAG output on successful compare
+ *  0b010..Set OFLAG output on successful compare
+ *  0b011..Toggle OFLAG output on successful compare
+ *  0b100..Toggle OFLAG output using alternating compare registers
+ *  0b101..Set on compare, cleared on secondary source input edge
+ *  0b110..Set on compare, cleared on counter rollover
+ *  0b111..Enable gated clock output while counter is active
+ */
 #define TMR_CTRL_OUTMODE(x)                      (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_OUTMODE_SHIFT)) & TMR_CTRL_OUTMODE_MASK)
 #define TMR_CTRL_COINIT_MASK                     (0x8U)
 #define TMR_CTRL_COINIT_SHIFT                    (3U)
+/*! COINIT - Co-Channel Initialization
+ *  0b0..Co-channel counter/timers cannot force a re-initialization of this counter/timer
+ *  0b1..Co-channel counter/timers may force a re-initialization of this counter/timer
+ */
 #define TMR_CTRL_COINIT(x)                       (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_COINIT_SHIFT)) & TMR_CTRL_COINIT_MASK)
 #define TMR_CTRL_DIR_MASK                        (0x10U)
 #define TMR_CTRL_DIR_SHIFT                       (4U)
+/*! DIR - Count Direction
+ *  0b0..Count up.
+ *  0b1..Count down.
+ */
 #define TMR_CTRL_DIR(x)                          (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_DIR_SHIFT)) & TMR_CTRL_DIR_MASK)
 #define TMR_CTRL_LENGTH_MASK                     (0x20U)
 #define TMR_CTRL_LENGTH_SHIFT                    (5U)
+/*! LENGTH - Count Length
+ *  0b0..Count until roll over at $FFFF and continue from $0000.
+ *  0b1..Count until compare, then re-initialize. If counting up, a successful compare occurs when the counter
+ *       reaches a COMP1 value. If counting down, a successful compare occurs when the counter reaches a COMP2 value.
+ *       When output mode $4 is used, alternating values of COMP1 and COMP2 are used to generate successful
+ *       comparisons. For example, the counter counts until a COMP1 value is reached, re-initializes, counts until COMP2
+ *       value is reached, re-initializes, counts until COMP1 value is reached, and so on.
+ */
 #define TMR_CTRL_LENGTH(x)                       (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_LENGTH_SHIFT)) & TMR_CTRL_LENGTH_MASK)
 #define TMR_CTRL_ONCE_MASK                       (0x40U)
 #define TMR_CTRL_ONCE_SHIFT                      (6U)
+/*! ONCE - Count Once
+ *  0b0..Count repeatedly.
+ *  0b1..Count until compare and then stop. If counting up, a successful compare occurs when the counter reaches a
+ *       COMP1 value. If counting down, a successful compare occurs when the counter reaches a COMP2 value. When
+ *       output mode $4 is used, the counter re-initializes after reaching the COMP1 value, continues to count to
+ *       the COMP2 value, and then stops.
+ */
 #define TMR_CTRL_ONCE(x)                         (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_ONCE_SHIFT)) & TMR_CTRL_ONCE_MASK)
 #define TMR_CTRL_SCS_MASK                        (0x180U)
 #define TMR_CTRL_SCS_SHIFT                       (7U)
+/*! SCS - Secondary Count Source
+ *  0b00..Counter 0 input pin
+ *  0b01..Counter 1 input pin
+ *  0b10..Counter 2 input pin
+ *  0b11..Counter 3 input pin
+ */
 #define TMR_CTRL_SCS(x)                          (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_SCS_SHIFT)) & TMR_CTRL_SCS_MASK)
 #define TMR_CTRL_PCS_MASK                        (0x1E00U)
 #define TMR_CTRL_PCS_SHIFT                       (9U)
+/*! PCS - Primary Count Source
+ *  0b0000..Counter 0 input pin
+ *  0b0001..Counter 1 input pin
+ *  0b0010..Counter 2 input pin
+ *  0b0011..Counter 3 input pin
+ *  0b0100..Counter 0 output
+ *  0b0101..Counter 1 output
+ *  0b0110..Counter 2 output
+ *  0b0111..Counter 3 output
+ *  0b1000..IP bus clock divide by 1 prescaler
+ *  0b1001..IP bus clock divide by 2 prescaler
+ *  0b1010..IP bus clock divide by 4 prescaler
+ *  0b1011..IP bus clock divide by 8 prescaler
+ *  0b1100..IP bus clock divide by 16 prescaler
+ *  0b1101..IP bus clock divide by 32 prescaler
+ *  0b1110..IP bus clock divide by 64 prescaler
+ *  0b1111..IP bus clock divide by 128 prescaler
+ */
 #define TMR_CTRL_PCS(x)                          (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_PCS_SHIFT)) & TMR_CTRL_PCS_MASK)
 #define TMR_CTRL_CM_MASK                         (0xE000U)
 #define TMR_CTRL_CM_SHIFT                        (13U)
+/*! CM - Count Mode
+ *  0b000..No operation
+ *  0b001..Count rising edges of primary sourceRising edges are counted only when SCTRL[IPS] = 0. Falling edges
+ *         are counted when SCTRL[IPS] = 1. If the primary count source is IP bus clock divide by 1, only rising
+ *         edges are counted regardless of the value of SCTRL[IPS].
+ *  0b010..Count rising and falling edges of primary sourceIP bus clock divide by 1 cannot be used as a primary count source in edge count mode.
+ *  0b011..Count rising edges of primary source while secondary input high active
+ *  0b100..Quadrature count mode, uses primary and secondary sources
+ *  0b101..Count rising edges of primary source; secondary source specifies directionRising edges are counted only
+ *         when SCTRL[IPS] = 0. Falling edges are counted when SCTRL[IPS] = 1.
+ *  0b110..Edge of secondary source triggers primary count until compare
+ *  0b111..Cascaded counter mode (up/down)The primary count source must be set to one of the counter outputs.
+ */
 #define TMR_CTRL_CM(x)                           (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_CM_SHIFT)) & TMR_CTRL_CM_MASK)
 /*! @} */
 
@@ -23213,9 +36195,18 @@ typedef struct {
 /*! @{ */
 #define TMR_SCTRL_OEN_MASK                       (0x1U)
 #define TMR_SCTRL_OEN_SHIFT                      (0U)
+/*! OEN - Output Enable
+ *  0b0..The external pin is configured as an input.
+ *  0b1..The OFLAG output signal is driven on the external pin. Other timer groups using this external pin as
+ *       their input see the driven value. The polarity of the signal is determined by OPS.
+ */
 #define TMR_SCTRL_OEN(x)                         (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_OEN_SHIFT)) & TMR_SCTRL_OEN_MASK)
 #define TMR_SCTRL_OPS_MASK                       (0x2U)
 #define TMR_SCTRL_OPS_SHIFT                      (1U)
+/*! OPS - Output Polarity Select
+ *  0b0..True polarity.
+ *  0b1..Inverted polarity.
+ */
 #define TMR_SCTRL_OPS(x)                         (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_OPS_SHIFT)) & TMR_SCTRL_OPS_MASK)
 #define TMR_SCTRL_FORCE_MASK                     (0x4U)
 #define TMR_SCTRL_FORCE_SHIFT                    (2U)
@@ -23231,6 +36222,12 @@ typedef struct {
 #define TMR_SCTRL_MSTR(x)                        (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_MSTR_SHIFT)) & TMR_SCTRL_MSTR_MASK)
 #define TMR_SCTRL_CAPTURE_MODE_MASK              (0xC0U)
 #define TMR_SCTRL_CAPTURE_MODE_SHIFT             (6U)
+/*! CAPTURE_MODE - Input Capture Mode
+ *  0b00..Capture function is disabled
+ *  0b01..Load capture register on rising edge (when IPS=0) or falling edge (when IPS=1) of input
+ *  0b10..Load capture register on falling edge (when IPS=0) or rising edge (when IPS=1) of input
+ *  0b11..Load capture register on both edges of input
+ */
 #define TMR_SCTRL_CAPTURE_MODE(x)                (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_CAPTURE_MODE_SHIFT)) & TMR_SCTRL_CAPTURE_MODE_MASK)
 #define TMR_SCTRL_INPUT_MASK                     (0x100U)
 #define TMR_SCTRL_INPUT_SHIFT                    (8U)
@@ -23285,9 +36282,21 @@ typedef struct {
 /*! @{ */
 #define TMR_CSCTRL_CL1_MASK                      (0x3U)
 #define TMR_CSCTRL_CL1_SHIFT                     (0U)
+/*! CL1 - Compare Load Control 1
+ *  0b00..Never preload
+ *  0b01..Load upon successful compare with the value in COMP1
+ *  0b10..Load upon successful compare with the value in COMP2
+ *  0b11..Reserved
+ */
 #define TMR_CSCTRL_CL1(x)                        (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_CL1_SHIFT)) & TMR_CSCTRL_CL1_MASK)
 #define TMR_CSCTRL_CL2_MASK                      (0xCU)
 #define TMR_CSCTRL_CL2_SHIFT                     (2U)
+/*! CL2 - Compare Load Control 2
+ *  0b00..Never preload
+ *  0b01..Load upon successful compare with the value in COMP1
+ *  0b10..Load upon successful compare with the value in COMP2
+ *  0b11..Reserved
+ */
 #define TMR_CSCTRL_CL2(x)                        (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_CL2_SHIFT)) & TMR_CSCTRL_CL2_MASK)
 #define TMR_CSCTRL_TCF1_MASK                     (0x10U)
 #define TMR_CSCTRL_TCF1_SHIFT                    (4U)
@@ -23303,21 +36312,47 @@ typedef struct {
 #define TMR_CSCTRL_TCF2EN(x)                     (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF2EN_SHIFT)) & TMR_CSCTRL_TCF2EN_MASK)
 #define TMR_CSCTRL_UP_MASK                       (0x200U)
 #define TMR_CSCTRL_UP_SHIFT                      (9U)
+/*! UP - Counting Direction Indicator
+ *  0b0..The last count was in the DOWN direction.
+ *  0b1..The last count was in the UP direction.
+ */
 #define TMR_CSCTRL_UP(x)                         (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_UP_SHIFT)) & TMR_CSCTRL_UP_MASK)
 #define TMR_CSCTRL_TCI_MASK                      (0x400U)
 #define TMR_CSCTRL_TCI_SHIFT                     (10U)
+/*! TCI - Triggered Count Initialization Control
+ *  0b0..Stop counter upon receiving a second trigger event while still counting from the first trigger event.
+ *  0b1..Reload the counter upon receiving a second trigger event while still counting from the first trigger event.
+ */
 #define TMR_CSCTRL_TCI(x)                        (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCI_SHIFT)) & TMR_CSCTRL_TCI_MASK)
 #define TMR_CSCTRL_ROC_MASK                      (0x800U)
 #define TMR_CSCTRL_ROC_SHIFT                     (11U)
+/*! ROC - Reload on Capture
+ *  0b0..Do not reload the counter on a capture event.
+ *  0b1..Reload the counter on a capture event.
+ */
 #define TMR_CSCTRL_ROC(x)                        (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_ROC_SHIFT)) & TMR_CSCTRL_ROC_MASK)
 #define TMR_CSCTRL_ALT_LOAD_MASK                 (0x1000U)
 #define TMR_CSCTRL_ALT_LOAD_SHIFT                (12U)
+/*! ALT_LOAD - Alternative Load Enable
+ *  0b0..Counter can be re-initialized only with the LOAD register.
+ *  0b1..Counter can be re-initialized with the LOAD or CMPLD2 registers depending on count direction.
+ */
 #define TMR_CSCTRL_ALT_LOAD(x)                   (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_ALT_LOAD_SHIFT)) & TMR_CSCTRL_ALT_LOAD_MASK)
 #define TMR_CSCTRL_FAULT_MASK                    (0x2000U)
 #define TMR_CSCTRL_FAULT_SHIFT                   (13U)
+/*! FAULT - Fault Enable
+ *  0b0..Fault function disabled.
+ *  0b1..Fault function enabled.
+ */
 #define TMR_CSCTRL_FAULT(x)                      (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_FAULT_SHIFT)) & TMR_CSCTRL_FAULT_MASK)
 #define TMR_CSCTRL_DBG_EN_MASK                   (0xC000U)
 #define TMR_CSCTRL_DBG_EN_SHIFT                  (14U)
+/*! DBG_EN - Debug Actions Enable
+ *  0b00..Continue with normal operation during debug mode. (default)
+ *  0b01..Halt TMR counter during debug mode.
+ *  0b10..Force TMR output to logic 0 (prior to consideration of SCTRL[OPS]).
+ *  0b11..Both halt counter and force output to 0 during debug mode.
+ */
 #define TMR_CSCTRL_DBG_EN(x)                     (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_DBG_EN_SHIFT)) & TMR_CSCTRL_DBG_EN_MASK)
 /*! @} */
 
@@ -23357,6 +36392,10 @@ typedef struct {
 /*! @{ */
 #define TMR_ENBL_ENBL_MASK                       (0xFU)
 #define TMR_ENBL_ENBL_SHIFT                      (0U)
+/*! ENBL - Timer Channel Enable
+ *  0b0000..Timer channel is disabled.
+ *  0b0001..Timer channel is enabled. (default)
+ */
 #define TMR_ENBL_ENBL(x)                         (((uint16_t)(((uint16_t)(x)) << TMR_ENBL_ENBL_SHIFT)) & TMR_ENBL_ENBL_MASK)
 /*! @} */
 
@@ -23486,9 +36525,21 @@ typedef struct {
 /*! @{ */
 #define TRNG_MCTL_SAMP_MODE_MASK                 (0x3U)
 #define TRNG_MCTL_SAMP_MODE_SHIFT                (0U)
+/*! SAMP_MODE
+ *  0b00..use Von Neumann data into both Entropy shifter and Statistical Checker
+ *  0b01..use raw data into both Entropy shifter and Statistical Checker
+ *  0b10..use Von Neumann data into Entropy shifter. Use raw data into Statistical Checker
+ *  0b11..undefined/reserved.
+ */
 #define TRNG_MCTL_SAMP_MODE(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_SAMP_MODE_SHIFT)) & TRNG_MCTL_SAMP_MODE_MASK)
 #define TRNG_MCTL_OSC_DIV_MASK                   (0xCU)
 #define TRNG_MCTL_OSC_DIV_SHIFT                  (2U)
+/*! OSC_DIV
+ *  0b00..use ring oscillator with no divide
+ *  0b01..use ring oscillator divided-by-2
+ *  0b10..use ring oscillator divided-by-4
+ *  0b11..use ring oscillator divided-by-8
+ */
 #define TRNG_MCTL_OSC_DIV(x)                     (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_OSC_DIV_SHIFT)) & TRNG_MCTL_OSC_DIV_MASK)
 #define TRNG_MCTL_UNUSED4_MASK                   (0x10U)
 #define TRNG_MCTL_UNUSED4_SHIFT                  (4U)
@@ -23893,6 +36944,10 @@ typedef struct {
 #define TRNG_SEC_CFG_UNUSED0(x)                  (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_UNUSED0_SHIFT)) & TRNG_SEC_CFG_UNUSED0_MASK)
 #define TRNG_SEC_CFG_NO_PRGM_MASK                (0x2U)
 #define TRNG_SEC_CFG_NO_PRGM_SHIFT               (1U)
+/*! NO_PRGM
+ *  0b0..Programability of registers controlled only by the Miscellaneous Control Register's access mode bit.
+ *  0b1..Overides Miscellaneous Control Register access mode and prevents TRNG register programming.
+ */
 #define TRNG_SEC_CFG_NO_PRGM(x)                  (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_NO_PRGM_SHIFT)) & TRNG_SEC_CFG_NO_PRGM_MASK)
 #define TRNG_SEC_CFG_UNUSED2_MASK                (0x4U)
 #define TRNG_SEC_CFG_UNUSED2_SHIFT               (2U)
@@ -23903,12 +36958,24 @@ typedef struct {
 /*! @{ */
 #define TRNG_INT_CTRL_HW_ERR_MASK                (0x1U)
 #define TRNG_INT_CTRL_HW_ERR_SHIFT               (0U)
+/*! HW_ERR
+ *  0b0..Corresponding bit of INT_STATUS register cleared.
+ *  0b1..Corresponding bit of INT_STATUS register active.
+ */
 #define TRNG_INT_CTRL_HW_ERR(x)                  (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_HW_ERR_SHIFT)) & TRNG_INT_CTRL_HW_ERR_MASK)
 #define TRNG_INT_CTRL_ENT_VAL_MASK               (0x2U)
 #define TRNG_INT_CTRL_ENT_VAL_SHIFT              (1U)
+/*! ENT_VAL
+ *  0b0..Same behavior as bit 0 of this register.
+ *  0b1..Same behavior as bit 0 of this register.
+ */
 #define TRNG_INT_CTRL_ENT_VAL(x)                 (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_ENT_VAL_SHIFT)) & TRNG_INT_CTRL_ENT_VAL_MASK)
 #define TRNG_INT_CTRL_FRQ_CT_FAIL_MASK           (0x4U)
 #define TRNG_INT_CTRL_FRQ_CT_FAIL_SHIFT          (2U)
+/*! FRQ_CT_FAIL
+ *  0b0..Same behavior as bit 0 of this register.
+ *  0b1..Same behavior as bit 0 of this register.
+ */
 #define TRNG_INT_CTRL_FRQ_CT_FAIL(x)             (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_CTRL_FRQ_CT_FAIL_MASK)
 #define TRNG_INT_CTRL_UNUSED_MASK                (0xFFFFFFF8U)
 #define TRNG_INT_CTRL_UNUSED_SHIFT               (3U)
@@ -23919,12 +36986,24 @@ typedef struct {
 /*! @{ */
 #define TRNG_INT_MASK_HW_ERR_MASK                (0x1U)
 #define TRNG_INT_MASK_HW_ERR_SHIFT               (0U)
+/*! HW_ERR
+ *  0b0..Corresponding interrupt of INT_STATUS is masked.
+ *  0b1..Corresponding bit of INT_STATUS is active.
+ */
 #define TRNG_INT_MASK_HW_ERR(x)                  (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_HW_ERR_SHIFT)) & TRNG_INT_MASK_HW_ERR_MASK)
 #define TRNG_INT_MASK_ENT_VAL_MASK               (0x2U)
 #define TRNG_INT_MASK_ENT_VAL_SHIFT              (1U)
+/*! ENT_VAL
+ *  0b0..Same behavior as bit 0 of this register.
+ *  0b1..Same behavior as bit 0 of this register.
+ */
 #define TRNG_INT_MASK_ENT_VAL(x)                 (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_ENT_VAL_SHIFT)) & TRNG_INT_MASK_ENT_VAL_MASK)
 #define TRNG_INT_MASK_FRQ_CT_FAIL_MASK           (0x4U)
 #define TRNG_INT_MASK_FRQ_CT_FAIL_SHIFT          (2U)
+/*! FRQ_CT_FAIL
+ *  0b0..Same behavior as bit 0 of this register.
+ *  0b1..Same behavior as bit 0 of this register.
+ */
 #define TRNG_INT_MASK_FRQ_CT_FAIL(x)             (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_MASK_FRQ_CT_FAIL_MASK)
 /*! @} */
 
@@ -23932,12 +37011,24 @@ typedef struct {
 /*! @{ */
 #define TRNG_INT_STATUS_HW_ERR_MASK              (0x1U)
 #define TRNG_INT_STATUS_HW_ERR_SHIFT             (0U)
+/*! HW_ERR
+ *  0b0..no error
+ *  0b1..error detected.
+ */
 #define TRNG_INT_STATUS_HW_ERR(x)                (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_HW_ERR_SHIFT)) & TRNG_INT_STATUS_HW_ERR_MASK)
 #define TRNG_INT_STATUS_ENT_VAL_MASK             (0x2U)
 #define TRNG_INT_STATUS_ENT_VAL_SHIFT            (1U)
+/*! ENT_VAL
+ *  0b0..Busy generation entropy. Any value read is invalid.
+ *  0b1..TRNG can be stopped and entropy is valid if read.
+ */
 #define TRNG_INT_STATUS_ENT_VAL(x)               (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_ENT_VAL_SHIFT)) & TRNG_INT_STATUS_ENT_VAL_MASK)
 #define TRNG_INT_STATUS_FRQ_CT_FAIL_MASK         (0x4U)
 #define TRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT        (2U)
+/*! FRQ_CT_FAIL
+ *  0b0..No hardware nor self test frequency errors.
+ *  0b1..The frequency counter has detected a failure.
+ */
 #define TRNG_INT_STATUS_FRQ_CT_FAIL(x)           (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_STATUS_FRQ_CT_FAIL_MASK)
 /*! @} */
 
@@ -23945,12 +37036,21 @@ typedef struct {
 /*! @{ */
 #define TRNG_VID1_MIN_REV_MASK                   (0xFFU)
 #define TRNG_VID1_MIN_REV_SHIFT                  (0U)
+/*! MIN_REV
+ *  0b00000000..Minor revision number for TRNG.
+ */
 #define TRNG_VID1_MIN_REV(x)                     (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_MIN_REV_SHIFT)) & TRNG_VID1_MIN_REV_MASK)
 #define TRNG_VID1_MAJ_REV_MASK                   (0xFF00U)
 #define TRNG_VID1_MAJ_REV_SHIFT                  (8U)
+/*! MAJ_REV
+ *  0b00000001..Major revision number for TRNG.
+ */
 #define TRNG_VID1_MAJ_REV(x)                     (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_MAJ_REV_SHIFT)) & TRNG_VID1_MAJ_REV_MASK)
 #define TRNG_VID1_IP_ID_MASK                     (0xFFFF0000U)
 #define TRNG_VID1_IP_ID_SHIFT                    (16U)
+/*! IP_ID
+ *  0b0000000000110000..ID for TRNG.
+ */
 #define TRNG_VID1_IP_ID(x)                       (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_IP_ID_SHIFT)) & TRNG_VID1_IP_ID_MASK)
 /*! @} */
 
@@ -23958,15 +37058,27 @@ typedef struct {
 /*! @{ */
 #define TRNG_VID2_CONFIG_OPT_MASK                (0xFFU)
 #define TRNG_VID2_CONFIG_OPT_SHIFT               (0U)
+/*! CONFIG_OPT
+ *  0b00000000..TRNG_CONFIG_OPT for TRNG.
+ */
 #define TRNG_VID2_CONFIG_OPT(x)                  (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_CONFIG_OPT_SHIFT)) & TRNG_VID2_CONFIG_OPT_MASK)
 #define TRNG_VID2_ECO_REV_MASK                   (0xFF00U)
 #define TRNG_VID2_ECO_REV_SHIFT                  (8U)
+/*! ECO_REV
+ *  0b00000000..TRNG_ECO_REV for TRNG.
+ */
 #define TRNG_VID2_ECO_REV(x)                     (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_ECO_REV_SHIFT)) & TRNG_VID2_ECO_REV_MASK)
 #define TRNG_VID2_INTG_OPT_MASK                  (0xFF0000U)
 #define TRNG_VID2_INTG_OPT_SHIFT                 (16U)
+/*! INTG_OPT
+ *  0b00000000..INTG_OPT for TRNG.
+ */
 #define TRNG_VID2_INTG_OPT(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_INTG_OPT_SHIFT)) & TRNG_VID2_INTG_OPT_MASK)
 #define TRNG_VID2_ERA_MASK                       (0xFF000000U)
 #define TRNG_VID2_ERA_SHIFT                      (24U)
+/*! ERA
+ *  0b00000000..COMPILE_OPT for TRNG.
+ */
 #define TRNG_VID2_ERA(x)                         (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_ERA_SHIFT)) & TRNG_VID2_ERA_MASK)
 /*! @} */
 
@@ -24036,9 +37148,17 @@ typedef struct {
 /*! @{ */
 #define TSC_BASIC_SETTING_AUTO_MEASURE_MASK      (0x1U)
 #define TSC_BASIC_SETTING_AUTO_MEASURE_SHIFT     (0U)
+/*! AUTO_MEASURE - Auto Measure
+ *  0b0..Disable Auto Measure
+ *  0b1..Auto Measure
+ */
 #define TSC_BASIC_SETTING_AUTO_MEASURE(x)        (((uint32_t)(((uint32_t)(x)) << TSC_BASIC_SETTING_AUTO_MEASURE_SHIFT)) & TSC_BASIC_SETTING_AUTO_MEASURE_MASK)
 #define TSC_BASIC_SETTING_4_5_WIRE_MASK          (0x10U)
 #define TSC_BASIC_SETTING_4_5_WIRE_SHIFT         (4U)
+/*! 4_5_WIRE - 4/5 Wire detection
+ *  0b0..4-Wire Detection Mode
+ *  0b1..5-Wire Detection Mode
+ */
 #define TSC_BASIC_SETTING_4_5_WIRE(x)            (((uint32_t)(((uint32_t)(x)) << TSC_BASIC_SETTING_4_5_WIRE_SHIFT)) & TSC_BASIC_SETTING_4_5_WIRE_MASK)
 #define TSC_BASIC_SETTING_MEASURE_DELAY_TIME_MASK (0xFFFFFF00U)
 #define TSC_BASIC_SETTING_MEASURE_DELAY_TIME_SHIFT (8U)
@@ -24059,15 +37179,31 @@ typedef struct {
 #define TSC_FLOW_CONTROL_SW_RST(x)               (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_SW_RST_SHIFT)) & TSC_FLOW_CONTROL_SW_RST_MASK)
 #define TSC_FLOW_CONTROL_START_MEASURE_MASK      (0x10U)
 #define TSC_FLOW_CONTROL_START_MEASURE_SHIFT     (4U)
+/*! START_MEASURE - Start Measure
+ *  0b0..Do not start measure for now
+ *  0b1..Start measure the X/Y coordinate value
+ */
 #define TSC_FLOW_CONTROL_START_MEASURE(x)        (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_START_MEASURE_SHIFT)) & TSC_FLOW_CONTROL_START_MEASURE_MASK)
 #define TSC_FLOW_CONTROL_DROP_MEASURE_MASK       (0x100U)
 #define TSC_FLOW_CONTROL_DROP_MEASURE_SHIFT      (8U)
+/*! DROP_MEASURE - Drop Measure
+ *  0b0..Do not drop measure for now
+ *  0b1..Drop the measure and controller return to idle status
+ */
 #define TSC_FLOW_CONTROL_DROP_MEASURE(x)         (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_DROP_MEASURE_SHIFT)) & TSC_FLOW_CONTROL_DROP_MEASURE_MASK)
 #define TSC_FLOW_CONTROL_START_SENSE_MASK        (0x1000U)
 #define TSC_FLOW_CONTROL_START_SENSE_SHIFT       (12U)
+/*! START_SENSE - Start Sense
+ *  0b0..Stay at idle status
+ *  0b1..Start sense detection and (if auto_measure set to 1) measure after detect a touch
+ */
 #define TSC_FLOW_CONTROL_START_SENSE(x)          (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_START_SENSE_SHIFT)) & TSC_FLOW_CONTROL_START_SENSE_MASK)
 #define TSC_FLOW_CONTROL_DISABLE_MASK            (0x10000U)
 #define TSC_FLOW_CONTROL_DISABLE_SHIFT           (16U)
+/*! DISABLE
+ *  0b0..Leave HW state machine control
+ *  0b1..SW set to idle status
+ */
 #define TSC_FLOW_CONTROL_DISABLE(x)              (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_DISABLE_SHIFT)) & TSC_FLOW_CONTROL_DISABLE_MASK)
 /*! @} */
 
@@ -24085,12 +37221,24 @@ typedef struct {
 /*! @{ */
 #define TSC_INT_EN_MEASURE_INT_EN_MASK           (0x1U)
 #define TSC_INT_EN_MEASURE_INT_EN_SHIFT          (0U)
+/*! MEASURE_INT_EN - Measure Interrupt Enable
+ *  0b0..Disable measure interrupt
+ *  0b1..Enable measure interrupt
+ */
 #define TSC_INT_EN_MEASURE_INT_EN(x)             (((uint32_t)(((uint32_t)(x)) << TSC_INT_EN_MEASURE_INT_EN_SHIFT)) & TSC_INT_EN_MEASURE_INT_EN_MASK)
 #define TSC_INT_EN_DETECT_INT_EN_MASK            (0x10U)
 #define TSC_INT_EN_DETECT_INT_EN_SHIFT           (4U)
+/*! DETECT_INT_EN - Detect Interrupt Enable
+ *  0b0..Disable detect interrupt
+ *  0b1..Enable detect interrupt
+ */
 #define TSC_INT_EN_DETECT_INT_EN(x)              (((uint32_t)(((uint32_t)(x)) << TSC_INT_EN_DETECT_INT_EN_SHIFT)) & TSC_INT_EN_DETECT_INT_EN_MASK)
 #define TSC_INT_EN_IDLE_SW_INT_EN_MASK           (0x1000U)
 #define TSC_INT_EN_IDLE_SW_INT_EN_SHIFT          (12U)
+/*! IDLE_SW_INT_EN - Idle Software Interrupt Enable
+ *  0b0..Disable idle software interrupt
+ *  0b1..Enable idle software interrupt
+ */
 #define TSC_INT_EN_IDLE_SW_INT_EN(x)             (((uint32_t)(((uint32_t)(x)) << TSC_INT_EN_IDLE_SW_INT_EN_SHIFT)) & TSC_INT_EN_IDLE_SW_INT_EN_MASK)
 /*! @} */
 
@@ -24101,12 +37249,24 @@ typedef struct {
 #define TSC_INT_SIG_EN_MEASURE_SIG_EN(x)         (((uint32_t)(((uint32_t)(x)) << TSC_INT_SIG_EN_MEASURE_SIG_EN_SHIFT)) & TSC_INT_SIG_EN_MEASURE_SIG_EN_MASK)
 #define TSC_INT_SIG_EN_DETECT_SIG_EN_MASK        (0x10U)
 #define TSC_INT_SIG_EN_DETECT_SIG_EN_SHIFT       (4U)
+/*! DETECT_SIG_EN - Detect Signal Enable
+ *  0b0..Disable detect signal
+ *  0b1..Enable detect signal
+ */
 #define TSC_INT_SIG_EN_DETECT_SIG_EN(x)          (((uint32_t)(((uint32_t)(x)) << TSC_INT_SIG_EN_DETECT_SIG_EN_SHIFT)) & TSC_INT_SIG_EN_DETECT_SIG_EN_MASK)
 #define TSC_INT_SIG_EN_VALID_SIG_EN_MASK         (0x100U)
 #define TSC_INT_SIG_EN_VALID_SIG_EN_SHIFT        (8U)
+/*! VALID_SIG_EN - Valid Signal Enable
+ *  0b0..Disable valid signal
+ *  0b1..Enable valid signal
+ */
 #define TSC_INT_SIG_EN_VALID_SIG_EN(x)           (((uint32_t)(((uint32_t)(x)) << TSC_INT_SIG_EN_VALID_SIG_EN_SHIFT)) & TSC_INT_SIG_EN_VALID_SIG_EN_MASK)
 #define TSC_INT_SIG_EN_IDLE_SW_SIG_EN_MASK       (0x1000U)
 #define TSC_INT_SIG_EN_IDLE_SW_SIG_EN_SHIFT      (12U)
+/*! IDLE_SW_SIG_EN - Idle Software Signal Enable
+ *  0b0..Disable idle software signal
+ *  0b1..Enable idle software signal
+ */
 #define TSC_INT_SIG_EN_IDLE_SW_SIG_EN(x)         (((uint32_t)(((uint32_t)(x)) << TSC_INT_SIG_EN_IDLE_SW_SIG_EN_SHIFT)) & TSC_INT_SIG_EN_IDLE_SW_SIG_EN_MASK)
 /*! @} */
 
@@ -24114,15 +37274,31 @@ typedef struct {
 /*! @{ */
 #define TSC_INT_STATUS_MEASURE_MASK              (0x1U)
 #define TSC_INT_STATUS_MEASURE_SHIFT             (0U)
+/*! MEASURE - Measure Signal
+ *  0b0..Does not exist a measure signal
+ *  0b1..Exist a measure signal
+ */
 #define TSC_INT_STATUS_MEASURE(x)                (((uint32_t)(((uint32_t)(x)) << TSC_INT_STATUS_MEASURE_SHIFT)) & TSC_INT_STATUS_MEASURE_MASK)
 #define TSC_INT_STATUS_DETECT_MASK               (0x10U)
 #define TSC_INT_STATUS_DETECT_SHIFT              (4U)
+/*! DETECT - Detect Signal
+ *  0b0..Does not exist a detect signal
+ *  0b1..Exist detect signal
+ */
 #define TSC_INT_STATUS_DETECT(x)                 (((uint32_t)(((uint32_t)(x)) << TSC_INT_STATUS_DETECT_SHIFT)) & TSC_INT_STATUS_DETECT_MASK)
 #define TSC_INT_STATUS_VALID_MASK                (0x100U)
 #define TSC_INT_STATUS_VALID_SHIFT               (8U)
+/*! VALID - Valid Signal
+ *  0b0..There is no touch detected after measurement, indicates that the measured value is not valid
+ *  0b1..There is touch detection after measurement, indicates that the measure is valid
+ */
 #define TSC_INT_STATUS_VALID(x)                  (((uint32_t)(((uint32_t)(x)) << TSC_INT_STATUS_VALID_SHIFT)) & TSC_INT_STATUS_VALID_MASK)
 #define TSC_INT_STATUS_IDLE_SW_MASK              (0x1000U)
 #define TSC_INT_STATUS_IDLE_SW_SHIFT             (12U)
+/*! IDLE_SW - Idle Software
+ *  0b0..Haven't return to idle status
+ *  0b1..Already return to idle status
+ */
 #define TSC_INT_STATUS_IDLE_SW(x)                (((uint32_t)(((uint32_t)(x)) << TSC_INT_STATUS_IDLE_SW_SHIFT)) & TSC_INT_STATUS_IDLE_SW_MASK)
 /*! @} */
 
@@ -24139,15 +37315,31 @@ typedef struct {
 #define TSC_DEBUG_MODE_EXT_HWTS(x)               (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_EXT_HWTS_SHIFT)) & TSC_DEBUG_MODE_EXT_HWTS_MASK)
 #define TSC_DEBUG_MODE_TRIGGER_MASK              (0x1000000U)
 #define TSC_DEBUG_MODE_TRIGGER_SHIFT             (24U)
+/*! TRIGGER - Trigger
+ *  0b0..No hardware trigger signal
+ *  0b1..Hardware trigger signal, the signal must last at least 1 ips clock period
+ */
 #define TSC_DEBUG_MODE_TRIGGER(x)                (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_TRIGGER_SHIFT)) & TSC_DEBUG_MODE_TRIGGER_MASK)
 #define TSC_DEBUG_MODE_ADC_COCO_CLEAR_MASK       (0x2000000U)
 #define TSC_DEBUG_MODE_ADC_COCO_CLEAR_SHIFT      (25U)
+/*! ADC_COCO_CLEAR - ADC Coco Clear
+ *  0b0..No ADC COCO clear
+ *  0b1..Set ADC COCO clear
+ */
 #define TSC_DEBUG_MODE_ADC_COCO_CLEAR(x)         (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_ADC_COCO_CLEAR_SHIFT)) & TSC_DEBUG_MODE_ADC_COCO_CLEAR_MASK)
 #define TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE_MASK (0x4000000U)
 #define TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE_SHIFT (26U)
+/*! ADC_COCO_CLEAR_DISABLE - ADC COCO Clear Disable
+ *  0b0..Allow TSC hardware generates ADC COCO clear
+ *  0b1..Prevent TSC from generate ADC COCO clear signal
+ */
 #define TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE_SHIFT)) & TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE_MASK)
 #define TSC_DEBUG_MODE_DEBUG_EN_MASK             (0x10000000U)
 #define TSC_DEBUG_MODE_DEBUG_EN_SHIFT            (28U)
+/*! DEBUG_EN - Debug Enable
+ *  0b0..Enable debug mode
+ *  0b1..Disable debug mode
+ */
 #define TSC_DEBUG_MODE_DEBUG_EN(x)               (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_DEBUG_EN_SHIFT)) & TSC_DEBUG_MODE_DEBUG_EN_MASK)
 /*! @} */
 
@@ -24155,69 +37347,164 @@ typedef struct {
 /*! @{ */
 #define TSC_DEBUG_MODE2_XPUL_PULL_DOWN_MASK      (0x1U)
 #define TSC_DEBUG_MODE2_XPUL_PULL_DOWN_SHIFT     (0U)
+/*! XPUL_PULL_DOWN - XPUL Wire Pull Down Switch
+ *  0b0..Close the switch
+ *  0b1..Open up the switch
+ */
 #define TSC_DEBUG_MODE2_XPUL_PULL_DOWN(x)        (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XPUL_PULL_DOWN_SHIFT)) & TSC_DEBUG_MODE2_XPUL_PULL_DOWN_MASK)
 #define TSC_DEBUG_MODE2_XPUL_PULL_UP_MASK        (0x2U)
 #define TSC_DEBUG_MODE2_XPUL_PULL_UP_SHIFT       (1U)
+/*! XPUL_PULL_UP - XPUL Wire Pull Up Switch
+ *  0b0..Close the switch
+ *  0b1..Open up the switch
+ */
 #define TSC_DEBUG_MODE2_XPUL_PULL_UP(x)          (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XPUL_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_XPUL_PULL_UP_MASK)
 #define TSC_DEBUG_MODE2_XPUL_200K_PULL_UP_MASK   (0x4U)
 #define TSC_DEBUG_MODE2_XPUL_200K_PULL_UP_SHIFT  (2U)
+/*! XPUL_200K_PULL_UP - XPUL Wire 200K Pull Up Switch
+ *  0b0..Close the switch
+ *  0b1..Open up the switch
+ */
 #define TSC_DEBUG_MODE2_XPUL_200K_PULL_UP(x)     (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XPUL_200K_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_XPUL_200K_PULL_UP_MASK)
 #define TSC_DEBUG_MODE2_XNUR_PULL_DOWN_MASK      (0x8U)
 #define TSC_DEBUG_MODE2_XNUR_PULL_DOWN_SHIFT     (3U)
+/*! XNUR_PULL_DOWN - XNUR Wire Pull Down Switch
+ *  0b0..Close the switch
+ *  0b1..Open up the switch
+ */
 #define TSC_DEBUG_MODE2_XNUR_PULL_DOWN(x)        (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XNUR_PULL_DOWN_SHIFT)) & TSC_DEBUG_MODE2_XNUR_PULL_DOWN_MASK)
 #define TSC_DEBUG_MODE2_XNUR_PULL_UP_MASK        (0x10U)
 #define TSC_DEBUG_MODE2_XNUR_PULL_UP_SHIFT       (4U)
+/*! XNUR_PULL_UP - XNUR Wire Pull Up Switch
+ *  0b0..Close the switch
+ *  0b1..Open up the switch
+ */
 #define TSC_DEBUG_MODE2_XNUR_PULL_UP(x)          (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XNUR_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_XNUR_PULL_UP_MASK)
 #define TSC_DEBUG_MODE2_XNUR_200K_PULL_UP_MASK   (0x20U)
 #define TSC_DEBUG_MODE2_XNUR_200K_PULL_UP_SHIFT  (5U)
+/*! XNUR_200K_PULL_UP - XNUR Wire 200K Pull Up Switch
+ *  0b0..Close the switch
+ *  0b1..Open up the switch
+ */
 #define TSC_DEBUG_MODE2_XNUR_200K_PULL_UP(x)     (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XNUR_200K_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_XNUR_200K_PULL_UP_MASK)
 #define TSC_DEBUG_MODE2_YPLL_PULL_DOWN_MASK      (0x40U)
 #define TSC_DEBUG_MODE2_YPLL_PULL_DOWN_SHIFT     (6U)
+/*! YPLL_PULL_DOWN - YPLL Wire Pull Down Switch
+ *  0b0..Close the switch
+ *  0b1..Open up the switch
+ */
 #define TSC_DEBUG_MODE2_YPLL_PULL_DOWN(x)        (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YPLL_PULL_DOWN_SHIFT)) & TSC_DEBUG_MODE2_YPLL_PULL_DOWN_MASK)
 #define TSC_DEBUG_MODE2_YPLL_PULL_UP_MASK        (0x80U)
 #define TSC_DEBUG_MODE2_YPLL_PULL_UP_SHIFT       (7U)
+/*! YPLL_PULL_UP - YPLL Wire Pull Up Switch
+ *  0b0..Close the switch
+ *  0b1..Open the switch
+ */
 #define TSC_DEBUG_MODE2_YPLL_PULL_UP(x)          (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YPLL_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_YPLL_PULL_UP_MASK)
 #define TSC_DEBUG_MODE2_YPLL_200K_PULL_UP_MASK   (0x100U)
 #define TSC_DEBUG_MODE2_YPLL_200K_PULL_UP_SHIFT  (8U)
+/*! YPLL_200K_PULL_UP - YPLL Wire 200K Pull Up Switch
+ *  0b0..Close the switch
+ *  0b1..Open up the switch
+ */
 #define TSC_DEBUG_MODE2_YPLL_200K_PULL_UP(x)     (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YPLL_200K_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_YPLL_200K_PULL_UP_MASK)
 #define TSC_DEBUG_MODE2_YNLR_PULL_DOWN_MASK      (0x200U)
 #define TSC_DEBUG_MODE2_YNLR_PULL_DOWN_SHIFT     (9U)
+/*! YNLR_PULL_DOWN - YNLR Wire Pull Down Switch
+ *  0b0..Close the switch
+ *  0b1..Open up the switch
+ */
 #define TSC_DEBUG_MODE2_YNLR_PULL_DOWN(x)        (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YNLR_PULL_DOWN_SHIFT)) & TSC_DEBUG_MODE2_YNLR_PULL_DOWN_MASK)
 #define TSC_DEBUG_MODE2_YNLR_PULL_UP_MASK        (0x400U)
 #define TSC_DEBUG_MODE2_YNLR_PULL_UP_SHIFT       (10U)
+/*! YNLR_PULL_UP - YNLR Wire Pull Up Switch
+ *  0b0..Close the switch
+ *  0b1..Open up the switch
+ */
 #define TSC_DEBUG_MODE2_YNLR_PULL_UP(x)          (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YNLR_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_YNLR_PULL_UP_MASK)
 #define TSC_DEBUG_MODE2_YNLR_200K_PULL_UP_MASK   (0x800U)
 #define TSC_DEBUG_MODE2_YNLR_200K_PULL_UP_SHIFT  (11U)
+/*! YNLR_200K_PULL_UP - YNLR Wire 200K Pull Up Switch
+ *  0b0..Close the switch
+ *  0b1..Open up the switch
+ */
 #define TSC_DEBUG_MODE2_YNLR_200K_PULL_UP(x)     (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YNLR_200K_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_YNLR_200K_PULL_UP_MASK)
 #define TSC_DEBUG_MODE2_WIPER_PULL_DOWN_MASK     (0x1000U)
 #define TSC_DEBUG_MODE2_WIPER_PULL_DOWN_SHIFT    (12U)
+/*! WIPER_PULL_DOWN - Wiper Wire Pull Down Switch
+ *  0b0..Close the switch
+ *  0b1..Open up the switch
+ */
 #define TSC_DEBUG_MODE2_WIPER_PULL_DOWN(x)       (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_WIPER_PULL_DOWN_SHIFT)) & TSC_DEBUG_MODE2_WIPER_PULL_DOWN_MASK)
 #define TSC_DEBUG_MODE2_WIPER_PULL_UP_MASK       (0x2000U)
 #define TSC_DEBUG_MODE2_WIPER_PULL_UP_SHIFT      (13U)
+/*! WIPER_PULL_UP - Wiper Wire Pull Up Switch
+ *  0b0..Close the switch
+ *  0b1..Open up the switch
+ */
 #define TSC_DEBUG_MODE2_WIPER_PULL_UP(x)         (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_WIPER_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_WIPER_PULL_UP_MASK)
 #define TSC_DEBUG_MODE2_WIPER_200K_PULL_UP_MASK  (0x4000U)
 #define TSC_DEBUG_MODE2_WIPER_200K_PULL_UP_SHIFT (14U)
+/*! WIPER_200K_PULL_UP - Wiper Wire 200K Pull Up Switch
+ *  0b0..Close the switch
+ *  0b1..Open up the switch
+ */
 #define TSC_DEBUG_MODE2_WIPER_200K_PULL_UP(x)    (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_WIPER_200K_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_WIPER_200K_PULL_UP_MASK)
 #define TSC_DEBUG_MODE2_DETECT_FOUR_WIRE_MASK    (0x10000U)
 #define TSC_DEBUG_MODE2_DETECT_FOUR_WIRE_SHIFT   (16U)
+/*! DETECT_FOUR_WIRE - Detect Four Wire
+ *  0b0..No detect signal
+ *  0b1..Yes, there is a detect on the touch screen.
+ */
 #define TSC_DEBUG_MODE2_DETECT_FOUR_WIRE(x)      (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_DETECT_FOUR_WIRE_SHIFT)) & TSC_DEBUG_MODE2_DETECT_FOUR_WIRE_MASK)
 #define TSC_DEBUG_MODE2_DETECT_FIVE_WIRE_MASK    (0x20000U)
 #define TSC_DEBUG_MODE2_DETECT_FIVE_WIRE_SHIFT   (17U)
+/*! DETECT_FIVE_WIRE - Detect Five Wire
+ *  0b0..No detect signal
+ *  0b1..Yes, there is a detect on the touch screen.
+ */
 #define TSC_DEBUG_MODE2_DETECT_FIVE_WIRE(x)      (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_DETECT_FIVE_WIRE_SHIFT)) & TSC_DEBUG_MODE2_DETECT_FIVE_WIRE_MASK)
 #define TSC_DEBUG_MODE2_STATE_MACHINE_MASK       (0x700000U)
 #define TSC_DEBUG_MODE2_STATE_MACHINE_SHIFT      (20U)
+/*! STATE_MACHINE - State Machine
+ *  0b000..Idle
+ *  0b001..Pre-charge
+ *  0b010..Detect
+ *  0b011..X-measure
+ *  0b100..Y-measure
+ *  0b101..Pre-charge
+ *  0b110..Detect
+ */
 #define TSC_DEBUG_MODE2_STATE_MACHINE(x)         (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_STATE_MACHINE_SHIFT)) & TSC_DEBUG_MODE2_STATE_MACHINE_MASK)
 #define TSC_DEBUG_MODE2_INTERMEDIATE_MASK        (0x800000U)
 #define TSC_DEBUG_MODE2_INTERMEDIATE_SHIFT       (23U)
+/*! INTERMEDIATE - Intermediate State
+ *  0b0..Not in intermedia
+ *  0b1..Intermedia
+ */
 #define TSC_DEBUG_MODE2_INTERMEDIATE(x)          (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_INTERMEDIATE_SHIFT)) & TSC_DEBUG_MODE2_INTERMEDIATE_MASK)
 #define TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE_MASK (0x1000000U)
 #define TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE_SHIFT (24U)
+/*! DETECT_ENABLE_FOUR_WIRE - Detect Enable Four Wire
+ *  0b0..Do not read four wire detect value, read default value from analogue
+ *  0b1..Read four wire detect status from analogue
+ */
 #define TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE_SHIFT)) & TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE_MASK)
 #define TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE_MASK (0x10000000U)
 #define TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE_SHIFT (28U)
+/*! DETECT_ENABLE_FIVE_WIRE - Detect Enable Five Wire
+ *  0b0..Do not read five wire detect value, read default value from analogue
+ *  0b1..Read five wire detect status from analogue
+ */
 #define TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE_SHIFT)) & TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE_MASK)
 #define TSC_DEBUG_MODE2_DE_GLITCH_MASK           (0x60000000U)
 #define TSC_DEBUG_MODE2_DE_GLITCH_SHIFT          (29U)
+/*! DE_GLITCH
+ *  0b00..Normal function: 0x1fff ipg clock cycles; Low power mode: 0x9 low power clock cycles
+ *  0b01..Normal function: 0xfff ipg clock cycles; Low power mode: :0x7 low power clock cycles
+ *  0b10..Normal function: 0x7ff ipg clock cycles; Low power mode:0x5 low power clock cycles
+ *  0b11..Normal function: 0x3 ipg clock cycles; Low power mode:0x3 low power clock cycles
+ */
 #define TSC_DEBUG_MODE2_DE_GLITCH(x)             (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_DE_GLITCH_SHIFT)) & TSC_DEBUG_MODE2_DE_GLITCH_MASK)
 /*! @} */
 
@@ -24342,12 +37629,34 @@ typedef struct {
 /*! @{ */
 #define USB_HWGENERAL_PHYW_MASK                  (0x30U)
 #define USB_HWGENERAL_PHYW_SHIFT                 (4U)
+/*! PHYW
+ *  0b00..8 bit wide data bus Software non-programmable
+ *  0b01..16 bit wide data bus Software non-programmable
+ *  0b10..Reset to 8 bit wide data bus Software programmable
+ *  0b11..Reset to 16 bit wide data bus Software programmable
+ */
 #define USB_HWGENERAL_PHYW(x)                    (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_PHYW_SHIFT)) & USB_HWGENERAL_PHYW_MASK)
 #define USB_HWGENERAL_PHYM_MASK                  (0x1C0U)
 #define USB_HWGENERAL_PHYM_SHIFT                 (6U)
+/*! PHYM
+ *  0b000..UTMI/UMTI+
+ *  0b001..ULPI DDR
+ *  0b010..ULPI
+ *  0b011..Serial Only
+ *  0b100..Software programmable - reset to UTMI/UTMI+
+ *  0b101..Software programmable - reset to ULPI DDR
+ *  0b110..Software programmable - reset to ULPI
+ *  0b111..Software programmable - reset to Serial
+ */
 #define USB_HWGENERAL_PHYM(x)                    (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_PHYM_SHIFT)) & USB_HWGENERAL_PHYM_MASK)
 #define USB_HWGENERAL_SM_MASK                    (0x600U)
 #define USB_HWGENERAL_SM_SHIFT                   (9U)
+/*! SM
+ *  0b00..No Serial Engine, always use parallel signalling.
+ *  0b01..Serial Engine present, always use serial signalling for FS/LS.
+ *  0b10..Software programmable - Reset to use parallel signalling for FS/LS
+ *  0b11..Software programmable - Reset to use serial signalling for FS/LS
+ */
 #define USB_HWGENERAL_SM(x)                      (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_SM_SHIFT)) & USB_HWGENERAL_SM_MASK)
 /*! @} */
 
@@ -24355,6 +37664,10 @@ typedef struct {
 /*! @{ */
 #define USB_HWHOST_HC_MASK                       (0x1U)
 #define USB_HWHOST_HC_SHIFT                      (0U)
+/*! HC
+ *  0b1..Supported
+ *  0b0..Not supported
+ */
 #define USB_HWHOST_HC(x)                         (((uint32_t)(((uint32_t)(x)) << USB_HWHOST_HC_SHIFT)) & USB_HWHOST_HC_MASK)
 #define USB_HWHOST_NPORT_MASK                    (0xEU)
 #define USB_HWHOST_NPORT_SHIFT                   (1U)
@@ -24365,6 +37678,10 @@ typedef struct {
 /*! @{ */
 #define USB_HWDEVICE_DC_MASK                     (0x1U)
 #define USB_HWDEVICE_DC_SHIFT                    (0U)
+/*! DC
+ *  0b1..Supported
+ *  0b0..Not supported
+ */
 #define USB_HWDEVICE_DC(x)                       (((uint32_t)(((uint32_t)(x)) << USB_HWDEVICE_DC_SHIFT)) & USB_HWDEVICE_DC_MASK)
 #define USB_HWDEVICE_DEVEP_MASK                  (0x3EU)
 #define USB_HWDEVICE_DEVEP_SHIFT                 (1U)
@@ -24405,12 +37722,24 @@ typedef struct {
 #define USB_GPTIMER0CTRL_GPTCNT(x)               (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTCNT_SHIFT)) & USB_GPTIMER0CTRL_GPTCNT_MASK)
 #define USB_GPTIMER0CTRL_GPTMODE_MASK            (0x1000000U)
 #define USB_GPTIMER0CTRL_GPTMODE_SHIFT           (24U)
+/*! GPTMODE
+ *  0b0..One Shot Mode
+ *  0b1..Repeat Mode
+ */
 #define USB_GPTIMER0CTRL_GPTMODE(x)              (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTMODE_SHIFT)) & USB_GPTIMER0CTRL_GPTMODE_MASK)
 #define USB_GPTIMER0CTRL_GPTRST_MASK             (0x40000000U)
 #define USB_GPTIMER0CTRL_GPTRST_SHIFT            (30U)
+/*! GPTRST
+ *  0b0..No action
+ *  0b1..Load counter value from GPTLD bits in n_GPTIMER0LD
+ */
 #define USB_GPTIMER0CTRL_GPTRST(x)               (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTRST_SHIFT)) & USB_GPTIMER0CTRL_GPTRST_MASK)
 #define USB_GPTIMER0CTRL_GPTRUN_MASK             (0x80000000U)
 #define USB_GPTIMER0CTRL_GPTRUN_SHIFT            (31U)
+/*! GPTRUN
+ *  0b0..Stop counting
+ *  0b1..Run
+ */
 #define USB_GPTIMER0CTRL_GPTRUN(x)               (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTRUN_SHIFT)) & USB_GPTIMER0CTRL_GPTRUN_MASK)
 /*! @} */
 
@@ -24428,12 +37757,24 @@ typedef struct {
 #define USB_GPTIMER1CTRL_GPTCNT(x)               (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTCNT_SHIFT)) & USB_GPTIMER1CTRL_GPTCNT_MASK)
 #define USB_GPTIMER1CTRL_GPTMODE_MASK            (0x1000000U)
 #define USB_GPTIMER1CTRL_GPTMODE_SHIFT           (24U)
+/*! GPTMODE
+ *  0b0..One Shot Mode
+ *  0b1..Repeat Mode
+ */
 #define USB_GPTIMER1CTRL_GPTMODE(x)              (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTMODE_SHIFT)) & USB_GPTIMER1CTRL_GPTMODE_MASK)
 #define USB_GPTIMER1CTRL_GPTRST_MASK             (0x40000000U)
 #define USB_GPTIMER1CTRL_GPTRST_SHIFT            (30U)
+/*! GPTRST
+ *  0b0..No action
+ *  0b1..Load counter value from GPTLD bits in USB_n_GPTIMER0LD
+ */
 #define USB_GPTIMER1CTRL_GPTRST(x)               (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTRST_SHIFT)) & USB_GPTIMER1CTRL_GPTRST_MASK)
 #define USB_GPTIMER1CTRL_GPTRUN_MASK             (0x80000000U)
 #define USB_GPTIMER1CTRL_GPTRUN_SHIFT            (31U)
+/*! GPTRUN
+ *  0b0..Stop counting
+ *  0b1..Run
+ */
 #define USB_GPTIMER1CTRL_GPTRUN(x)               (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTRUN_SHIFT)) & USB_GPTIMER1CTRL_GPTRUN_MASK)
 /*! @} */
 
@@ -24441,6 +37782,16 @@ typedef struct {
 /*! @{ */
 #define USB_SBUSCFG_AHBBRST_MASK                 (0x7U)
 #define USB_SBUSCFG_AHBBRST_SHIFT                (0U)
+/*! AHBBRST
+ *  0b000..Incremental burst of unspecified length only
+ *  0b001..INCR4 burst, then single transfer
+ *  0b010..INCR8 burst, INCR4 burst, then single transfer
+ *  0b011..INCR16 burst, INCR8 burst, INCR4 burst, then single transfer
+ *  0b100..Reserved, don't use
+ *  0b101..INCR4 burst, then incremental burst of unspecified length
+ *  0b110..INCR8 burst, INCR4 burst, then incremental burst of unspecified length
+ *  0b111..INCR16 burst, INCR8 burst, INCR4 burst, then incremental burst of unspecified length
+ */
 #define USB_SBUSCFG_AHBBRST(x)                   (((uint32_t)(((uint32_t)(x)) << USB_SBUSCFG_AHBBRST_SHIFT)) & USB_SBUSCFG_AHBBRST_MASK)
 /*! @} */
 
@@ -24471,6 +37822,10 @@ typedef struct {
 #define USB_HCSPARAMS_N_PCC(x)                   (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PCC_SHIFT)) & USB_HCSPARAMS_N_PCC_MASK)
 #define USB_HCSPARAMS_N_CC_MASK                  (0xF000U)
 #define USB_HCSPARAMS_N_CC_SHIFT                 (12U)
+/*! N_CC
+ *  0b0000..There is no internal Companion Controller and port-ownership hand-off is not supported.
+ *  0b0001..There are internal companion controller(s) and port-ownership hand-offs is supported.
+ */
 #define USB_HCSPARAMS_N_CC(x)                    (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_CC_SHIFT)) & USB_HCSPARAMS_N_CC_MASK)
 #define USB_HCSPARAMS_PI_MASK                    (0x10000U)
 #define USB_HCSPARAMS_PI_SHIFT                   (16U)
@@ -24535,9 +37890,17 @@ typedef struct {
 #define USB_USBCMD_FS_1(x)                       (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_FS_1_SHIFT)) & USB_USBCMD_FS_1_MASK)
 #define USB_USBCMD_PSE_MASK                      (0x10U)
 #define USB_USBCMD_PSE_SHIFT                     (4U)
+/*! PSE
+ *  0b0..Do not process the Periodic Schedule
+ *  0b1..Use the PERIODICLISTBASE register to access the Periodic Schedule.
+ */
 #define USB_USBCMD_PSE(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_PSE_SHIFT)) & USB_USBCMD_PSE_MASK)
 #define USB_USBCMD_ASE_MASK                      (0x20U)
 #define USB_USBCMD_ASE_SHIFT                     (5U)
+/*! ASE
+ *  0b0..Do not process the Asynchronous Schedule.
+ *  0b1..Use the ASYNCLISTADDR register to access the Asynchronous Schedule.
+ */
 #define USB_USBCMD_ASE(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASE_SHIFT)) & USB_USBCMD_ASE_MASK)
 #define USB_USBCMD_IAA_MASK                      (0x40U)
 #define USB_USBCMD_IAA_SHIFT                     (6U)
@@ -24556,9 +37919,23 @@ typedef struct {
 #define USB_USBCMD_SUTW(x)                       (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_SUTW_SHIFT)) & USB_USBCMD_SUTW_MASK)
 #define USB_USBCMD_FS_2_MASK                     (0x8000U)
 #define USB_USBCMD_FS_2_SHIFT                    (15U)
+/*! FS_2
+ *  0b0..1024 elements (4096 bytes) Default value
+ *  0b1..512 elements (2048 bytes)
+ */
 #define USB_USBCMD_FS_2(x)                       (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_FS_2_SHIFT)) & USB_USBCMD_FS_2_MASK)
 #define USB_USBCMD_ITC_MASK                      (0xFF0000U)
 #define USB_USBCMD_ITC_SHIFT                     (16U)
+/*! ITC
+ *  0b00000000..Immediate (no threshold)
+ *  0b00000001..1 micro-frame
+ *  0b00000010..2 micro-frames
+ *  0b00000100..4 micro-frames
+ *  0b00001000..8 micro-frames
+ *  0b00010000..16 micro-frames
+ *  0b00100000..32 micro-frames
+ *  0b01000000..64 micro-frames
+ */
 #define USB_USBCMD_ITC(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ITC_SHIFT)) & USB_USBCMD_ITC_MASK)
 /*! @} */
 
@@ -24670,6 +38047,16 @@ typedef struct {
 /*! @{ */
 #define USB_FRINDEX_FRINDEX_MASK                 (0x3FFFU)
 #define USB_FRINDEX_FRINDEX_SHIFT                (0U)
+/*! FRINDEX
+ *  0b00000000000000..(1024) 12
+ *  0b00000000000001..(512) 11
+ *  0b00000000000010..(256) 10
+ *  0b00000000000011..(128) 9
+ *  0b00000000000100..(64) 8
+ *  0b00000000000101..(32) 7
+ *  0b00000000000110..(16) 6
+ *  0b00000000000111..(8) 5
+ */
 #define USB_FRINDEX_FRINDEX(x)                   (((uint32_t)(((uint32_t)(x)) << USB_FRINDEX_FRINDEX_SHIFT)) & USB_FRINDEX_FRINDEX_MASK)
 /*! @} */
 
@@ -24751,6 +38138,10 @@ typedef struct {
 /*! @{ */
 #define USB_CONFIGFLAG_CF_MASK                   (0x1U)
 #define USB_CONFIGFLAG_CF_SHIFT                  (0U)
+/*! CF
+ *  0b0..Port routing control logic default-routes each port to an implementation dependent classic host controller.
+ *  0b1..Port routing control logic default-routes all ports to this host controller.
+ */
 #define USB_CONFIGFLAG_CF(x)                     (((uint32_t)(((uint32_t)(x)) << USB_CONFIGFLAG_CF_SHIFT)) & USB_CONFIGFLAG_CF_MASK)
 /*! @} */
 
@@ -24770,6 +38161,10 @@ typedef struct {
 #define USB_PORTSC1_PEC(x)                       (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PEC_SHIFT)) & USB_PORTSC1_PEC_MASK)
 #define USB_PORTSC1_OCA_MASK                     (0x10U)
 #define USB_PORTSC1_OCA_SHIFT                    (4U)
+/*! OCA
+ *  0b1..This port currently has an over-current condition
+ *  0b0..This port does not have an over-current condition.
+ */
 #define USB_PORTSC1_OCA(x)                       (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_OCA_SHIFT)) & USB_PORTSC1_OCA_MASK)
 #define USB_PORTSC1_OCC_MASK                     (0x20U)
 #define USB_PORTSC1_OCC_SHIFT                    (5U)
@@ -24788,6 +38183,12 @@ typedef struct {
 #define USB_PORTSC1_HSP(x)                       (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_HSP_SHIFT)) & USB_PORTSC1_HSP_MASK)
 #define USB_PORTSC1_LS_MASK                      (0xC00U)
 #define USB_PORTSC1_LS_SHIFT                     (10U)
+/*! LS
+ *  0b00..SE0
+ *  0b10..J-state
+ *  0b01..K-state
+ *  0b11..Undefined
+ */
 #define USB_PORTSC1_LS(x)                        (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_LS_SHIFT)) & USB_PORTSC1_LS_MASK)
 #define USB_PORTSC1_PP_MASK                      (0x1000U)
 #define USB_PORTSC1_PP_SHIFT                     (12U)
@@ -24797,9 +38198,25 @@ typedef struct {
 #define USB_PORTSC1_PO(x)                        (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PO_SHIFT)) & USB_PORTSC1_PO_MASK)
 #define USB_PORTSC1_PIC_MASK                     (0xC000U)
 #define USB_PORTSC1_PIC_SHIFT                    (14U)
+/*! PIC
+ *  0b00..Port indicators are off
+ *  0b01..Amber
+ *  0b10..Green
+ *  0b11..Undefined
+ */
 #define USB_PORTSC1_PIC(x)                       (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PIC_SHIFT)) & USB_PORTSC1_PIC_MASK)
 #define USB_PORTSC1_PTC_MASK                     (0xF0000U)
 #define USB_PORTSC1_PTC_SHIFT                    (16U)
+/*! PTC
+ *  0b0000..TEST_MODE_DISABLE
+ *  0b0001..J_STATE
+ *  0b0010..K_STATE
+ *  0b0011..SE0 (host) / NAK (device)
+ *  0b0100..Packet
+ *  0b0101..FORCE_ENABLE_HS
+ *  0b0110..FORCE_ENABLE_FS
+ *  0b0111..FORCE_ENABLE_LS
+ */
 #define USB_PORTSC1_PTC(x)                       (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTC_SHIFT)) & USB_PORTSC1_PTC_MASK)
 #define USB_PORTSC1_WKCN_MASK                    (0x100000U)
 #define USB_PORTSC1_WKCN_SHIFT                   (20U)
@@ -24812,18 +38229,36 @@ typedef struct {
 #define USB_PORTSC1_WKOC(x)                      (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKOC_SHIFT)) & USB_PORTSC1_WKOC_MASK)
 #define USB_PORTSC1_PHCD_MASK                    (0x800000U)
 #define USB_PORTSC1_PHCD_SHIFT                   (23U)
+/*! PHCD
+ *  0b1..Disable PHY clock
+ *  0b0..Enable PHY clock
+ */
 #define USB_PORTSC1_PHCD(x)                      (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PHCD_SHIFT)) & USB_PORTSC1_PHCD_MASK)
 #define USB_PORTSC1_PFSC_MASK                    (0x1000000U)
 #define USB_PORTSC1_PFSC_SHIFT                   (24U)
+/*! PFSC
+ *  0b1..Forced to full speed
+ *  0b0..Normal operation
+ */
 #define USB_PORTSC1_PFSC(x)                      (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PFSC_SHIFT)) & USB_PORTSC1_PFSC_MASK)
 #define USB_PORTSC1_PTS_2_MASK                   (0x2000000U)
 #define USB_PORTSC1_PTS_2_SHIFT                  (25U)
 #define USB_PORTSC1_PTS_2(x)                     (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTS_2_SHIFT)) & USB_PORTSC1_PTS_2_MASK)
 #define USB_PORTSC1_PSPD_MASK                    (0xC000000U)
 #define USB_PORTSC1_PSPD_SHIFT                   (26U)
+/*! PSPD
+ *  0b00..Full Speed
+ *  0b01..Low Speed
+ *  0b10..High Speed
+ *  0b11..Undefined
+ */
 #define USB_PORTSC1_PSPD(x)                      (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PSPD_SHIFT)) & USB_PORTSC1_PSPD_MASK)
 #define USB_PORTSC1_PTW_MASK                     (0x10000000U)
 #define USB_PORTSC1_PTW_SHIFT                    (28U)
+/*! PTW
+ *  0b0..Select the 8-bit UTMI interface [60MHz]
+ *  0b1..Select the 16-bit UTMI interface [30MHz]
+ */
 #define USB_PORTSC1_PTW(x)                       (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTW_SHIFT)) & USB_PORTSC1_PTW_MASK)
 #define USB_PORTSC1_STS_MASK                     (0x20000000U)
 #define USB_PORTSC1_STS_SHIFT                    (29U)
@@ -24919,12 +38354,26 @@ typedef struct {
 /*! @{ */
 #define USB_USBMODE_CM_MASK                      (0x3U)
 #define USB_USBMODE_CM_SHIFT                     (0U)
+/*! CM
+ *  0b00..Idle [Default for combination host/device]
+ *  0b01..Reserved
+ *  0b10..Device Controller [Default for device only controller]
+ *  0b11..Host Controller [Default for host only controller]
+ */
 #define USB_USBMODE_CM(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_CM_SHIFT)) & USB_USBMODE_CM_MASK)
 #define USB_USBMODE_ES_MASK                      (0x4U)
 #define USB_USBMODE_ES_SHIFT                     (2U)
+/*! ES
+ *  0b0..Little Endian [Default]
+ *  0b1..Big Endian
+ */
 #define USB_USBMODE_ES(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_ES_SHIFT)) & USB_USBMODE_ES_MASK)
 #define USB_USBMODE_SLOM_MASK                    (0x8U)
 #define USB_USBMODE_SLOM_SHIFT                   (3U)
+/*! SLOM
+ *  0b0..Setup Lockouts On (default);
+ *  0b1..Setup Lockouts Off (DCD requires use of Setup Data Buffer Tripwire in USBCMDUSB Command Register .
+ */
 #define USB_USBMODE_SLOM(x)                      (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_SLOM_SHIFT)) & USB_USBMODE_SLOM_MASK)
 #define USB_USBMODE_SDIS_MASK                    (0x10U)
 #define USB_USBMODE_SDIS_SHIFT                   (4U)
@@ -25671,33 +39120,73 @@ typedef struct {
 /*! @{ */
 #define USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_MASK    (0x80U)
 #define USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_SHIFT   (7U)
+/*! OVER_CUR_DIS
+ *  0b1..Disables overcurrent detection
+ *  0b0..Enables overcurrent detection
+ */
 #define USBNC_USB_OTGn_CTRL_OVER_CUR_DIS(x)      (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_SHIFT)) & USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_MASK)
 #define USBNC_USB_OTGn_CTRL_OVER_CUR_POL_MASK    (0x100U)
 #define USBNC_USB_OTGn_CTRL_OVER_CUR_POL_SHIFT   (8U)
+/*! OVER_CUR_POL
+ *  0b1..Low active (low on this signal represents an overcurrent condition)
+ *  0b0..High active (high on this signal represents an overcurrent condition)
+ */
 #define USBNC_USB_OTGn_CTRL_OVER_CUR_POL(x)      (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_OVER_CUR_POL_SHIFT)) & USBNC_USB_OTGn_CTRL_OVER_CUR_POL_MASK)
 #define USBNC_USB_OTGn_CTRL_PWR_POL_MASK         (0x200U)
 #define USBNC_USB_OTGn_CTRL_PWR_POL_SHIFT        (9U)
+/*! PWR_POL
+ *  0b1..PMIC Power Pin is High active.
+ *  0b0..PMIC Power Pin is Low active.
+ */
 #define USBNC_USB_OTGn_CTRL_PWR_POL(x)           (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_PWR_POL_SHIFT)) & USBNC_USB_OTGn_CTRL_PWR_POL_MASK)
 #define USBNC_USB_OTGn_CTRL_WIE_MASK             (0x400U)
 #define USBNC_USB_OTGn_CTRL_WIE_SHIFT            (10U)
+/*! WIE
+ *  0b1..Interrupt Enabled
+ *  0b0..Interrupt Disabled
+ */
 #define USBNC_USB_OTGn_CTRL_WIE(x)               (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WIE_SHIFT)) & USBNC_USB_OTGn_CTRL_WIE_MASK)
 #define USBNC_USB_OTGn_CTRL_WKUP_SW_EN_MASK      (0x4000U)
 #define USBNC_USB_OTGn_CTRL_WKUP_SW_EN_SHIFT     (14U)
+/*! WKUP_SW_EN
+ *  0b1..Enable
+ *  0b0..Disable
+ */
 #define USBNC_USB_OTGn_CTRL_WKUP_SW_EN(x)        (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_SW_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_SW_EN_MASK)
 #define USBNC_USB_OTGn_CTRL_WKUP_SW_MASK         (0x8000U)
 #define USBNC_USB_OTGn_CTRL_WKUP_SW_SHIFT        (15U)
+/*! WKUP_SW
+ *  0b1..Force wake-up
+ *  0b0..Inactive
+ */
 #define USBNC_USB_OTGn_CTRL_WKUP_SW(x)           (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_SW_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_SW_MASK)
 #define USBNC_USB_OTGn_CTRL_WKUP_ID_EN_MASK      (0x10000U)
 #define USBNC_USB_OTGn_CTRL_WKUP_ID_EN_SHIFT     (16U)
+/*! WKUP_ID_EN
+ *  0b1..Enable
+ *  0b0..Disable
+ */
 #define USBNC_USB_OTGn_CTRL_WKUP_ID_EN(x)        (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_ID_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_ID_EN_MASK)
 #define USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_MASK    (0x20000U)
 #define USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_SHIFT   (17U)
+/*! WKUP_VBUS_EN
+ *  0b1..Enable
+ *  0b0..Disable
+ */
 #define USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN(x)      (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_MASK)
 #define USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_MASK    (0x20000000U)
 #define USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_SHIFT   (29U)
+/*! WKUP_DPDM_EN
+ *  0b1..(Default) DPDM changes wake-up to be enabled, it is for device only.
+ *  0b0..DPDM changes wake-up to be disabled only when VBUS is 0.
+ */
 #define USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN(x)      (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_MASK)
 #define USBNC_USB_OTGn_CTRL_WIR_MASK             (0x80000000U)
 #define USBNC_USB_OTGn_CTRL_WIR_SHIFT            (31U)
+/*! WIR
+ *  0b1..Wake-up Interrupt Request received
+ *  0b0..No wake-up interrupt request received
+ */
 #define USBNC_USB_OTGn_CTRL_WIR(x)               (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WIR_SHIFT)) & USBNC_USB_OTGn_CTRL_WIR_MASK)
 /*! @} */
 
@@ -25705,6 +39194,10 @@ typedef struct {
 /*! @{ */
 #define USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_MASK (0x80000000U)
 #define USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_SHIFT (31U)
+/*! UTMI_CLK_VLD
+ *  0b1..Valid
+ *  0b0..Invalid
+ */
 #define USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_SHIFT)) & USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_MASK)
 /*! @} */
 
@@ -26894,6 +40387,16 @@ typedef struct {
 /*! @{ */
 #define USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_MASK (0x7U)
 #define USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_SHIFT (0U)
+/*! VBUSVALID_THRESH
+ *  0b000..4.0V
+ *  0b001..4.1V
+ *  0b010..4.2V
+ *  0b011..4.3V
+ *  0b100..4.4V (default)
+ *  0b101..4.5V
+ *  0b110..4.6V
+ *  0b111..4.7V
+ */
 #define USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_MASK)
 #define USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_MASK (0x100000U)
 #define USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_SHIFT (20U)
@@ -26913,6 +40416,16 @@ typedef struct {
 /*! @{ */
 #define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK (0x7U)
 #define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT (0U)
+/*! VBUSVALID_THRESH
+ *  0b000..4.0V
+ *  0b001..4.1V
+ *  0b010..4.2V
+ *  0b011..4.3V
+ *  0b100..4.4V (default)
+ *  0b101..4.5V
+ *  0b110..4.6V
+ *  0b111..4.7V
+ */
 #define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK)
 #define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_MASK (0x100000U)
 #define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_SHIFT (20U)
@@ -26932,6 +40445,16 @@ typedef struct {
 /*! @{ */
 #define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK (0x7U)
 #define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT (0U)
+/*! VBUSVALID_THRESH
+ *  0b000..4.0V
+ *  0b001..4.1V
+ *  0b010..4.2V
+ *  0b011..4.3V
+ *  0b100..4.4V (default)
+ *  0b101..4.5V
+ *  0b110..4.6V
+ *  0b111..4.7V
+ */
 #define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK)
 #define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_MASK (0x100000U)
 #define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_SHIFT (20U)
@@ -26951,6 +40474,16 @@ typedef struct {
 /*! @{ */
 #define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK (0x7U)
 #define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT (0U)
+/*! VBUSVALID_THRESH
+ *  0b000..4.0V
+ *  0b001..4.1V
+ *  0b010..4.2V
+ *  0b011..4.3V
+ *  0b100..4.4V (default)
+ *  0b101..4.5V
+ *  0b110..4.6V
+ *  0b111..4.7V
+ */
 #define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK)
 #define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_MASK (0x100000U)
 #define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_SHIFT (20U)
@@ -26970,12 +40503,24 @@ typedef struct {
 /*! @{ */
 #define USB_ANALOG_CHRG_DETECT_CHK_CONTACT_MASK  (0x40000U)
 #define USB_ANALOG_CHRG_DETECT_CHK_CONTACT_SHIFT (18U)
+/*! CHK_CONTACT - Check the contact of USB plug
+ *  0b0..Do not check the contact of USB plug.
+ *  0b1..Check whether the USB plug has been in contact with each other
+ */
 #define USB_ANALOG_CHRG_DETECT_CHK_CONTACT(x)    (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_CHK_CONTACT_MASK)
 #define USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_MASK   (0x80000U)
 #define USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_SHIFT  (19U)
+/*! CHK_CHRG_B - Check the charger connection
+ *  0b0..Check whether a charger (either a dedicated charger or a host charger) is connected to USB port.
+ *  0b1..Do not check whether a charger is connected to the USB port.
+ */
 #define USB_ANALOG_CHRG_DETECT_CHK_CHRG_B(x)     (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_MASK)
 #define USB_ANALOG_CHRG_DETECT_EN_B_MASK         (0x100000U)
 #define USB_ANALOG_CHRG_DETECT_EN_B_SHIFT        (20U)
+/*! EN_B
+ *  0b0..Enable the charger detector.
+ *  0b1..Disable the charger detector.
+ */
 #define USB_ANALOG_CHRG_DETECT_EN_B(x)           (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_EN_B_MASK)
 /*! @} */
 
@@ -26986,12 +40531,24 @@ typedef struct {
 /*! @{ */
 #define USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_MASK (0x40000U)
 #define USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_SHIFT (18U)
+/*! CHK_CONTACT - Check the contact of USB plug
+ *  0b0..Do not check the contact of USB plug.
+ *  0b1..Check whether the USB plug has been in contact with each other
+ */
 #define USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_MASK)
 #define USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_MASK (0x80000U)
 #define USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_SHIFT (19U)
+/*! CHK_CHRG_B - Check the charger connection
+ *  0b0..Check whether a charger (either a dedicated charger or a host charger) is connected to USB port.
+ *  0b1..Do not check whether a charger is connected to the USB port.
+ */
 #define USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_MASK)
 #define USB_ANALOG_CHRG_DETECT_SET_EN_B_MASK     (0x100000U)
 #define USB_ANALOG_CHRG_DETECT_SET_EN_B_SHIFT    (20U)
+/*! EN_B
+ *  0b0..Enable the charger detector.
+ *  0b1..Disable the charger detector.
+ */
 #define USB_ANALOG_CHRG_DETECT_SET_EN_B(x)       (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_SET_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_SET_EN_B_MASK)
 /*! @} */
 
@@ -27002,12 +40559,24 @@ typedef struct {
 /*! @{ */
 #define USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_MASK (0x40000U)
 #define USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_SHIFT (18U)
+/*! CHK_CONTACT - Check the contact of USB plug
+ *  0b0..Do not check the contact of USB plug.
+ *  0b1..Check whether the USB plug has been in contact with each other
+ */
 #define USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_MASK)
 #define USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_MASK (0x80000U)
 #define USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_SHIFT (19U)
+/*! CHK_CHRG_B - Check the charger connection
+ *  0b0..Check whether a charger (either a dedicated charger or a host charger) is connected to USB port.
+ *  0b1..Do not check whether a charger is connected to the USB port.
+ */
 #define USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_MASK)
 #define USB_ANALOG_CHRG_DETECT_CLR_EN_B_MASK     (0x100000U)
 #define USB_ANALOG_CHRG_DETECT_CLR_EN_B_SHIFT    (20U)
+/*! EN_B
+ *  0b0..Enable the charger detector.
+ *  0b1..Disable the charger detector.
+ */
 #define USB_ANALOG_CHRG_DETECT_CLR_EN_B(x)       (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CLR_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_CLR_EN_B_MASK)
 /*! @} */
 
@@ -27018,12 +40587,24 @@ typedef struct {
 /*! @{ */
 #define USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_MASK (0x40000U)
 #define USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_SHIFT (18U)
+/*! CHK_CONTACT - Check the contact of USB plug
+ *  0b0..Do not check the contact of USB plug.
+ *  0b1..Check whether the USB plug has been in contact with each other
+ */
 #define USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_MASK)
 #define USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_MASK (0x80000U)
 #define USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_SHIFT (19U)
+/*! CHK_CHRG_B - Check the charger connection
+ *  0b0..Check whether a charger (either a dedicated charger or a host charger) is connected to USB port.
+ *  0b1..Do not check whether a charger is connected to the USB port.
+ */
 #define USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_MASK)
 #define USB_ANALOG_CHRG_DETECT_TOG_EN_B_MASK     (0x100000U)
 #define USB_ANALOG_CHRG_DETECT_TOG_EN_B_SHIFT    (20U)
+/*! EN_B
+ *  0b0..Enable the charger detector.
+ *  0b1..Disable the charger detector.
+ */
 #define USB_ANALOG_CHRG_DETECT_TOG_EN_B(x)       (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_TOG_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_TOG_EN_B_MASK)
 /*! @} */
 
@@ -27053,9 +40634,17 @@ typedef struct {
 /*! @{ */
 #define USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_MASK (0x1U)
 #define USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_SHIFT (0U)
+/*! PLUG_CONTACT
+ *  0b0..The USB plug has not made contact.
+ *  0b1..The USB plug has made good contact.
+ */
 #define USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_MASK)
 #define USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_MASK (0x2U)
 #define USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_SHIFT (1U)
+/*! CHRG_DETECTED
+ *  0b0..The USB port is not connected to a charger.
+ *  0b1..A charger (either a dedicated charger or a host charger) is connected to the USB port.
+ */
 #define USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_SHIFT)) & USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_MASK)
 #define USB_ANALOG_CHRG_DETECT_STAT_DM_STATE_MASK (0x4U)
 #define USB_ANALOG_CHRG_DETECT_STAT_DM_STATE_SHIFT (2U)
@@ -27136,6 +40725,9 @@ typedef struct {
 /*! @{ */
 #define USB_ANALOG_DIGPROG_SILICON_REVISION_MASK (0xFFFFFFFFU)
 #define USB_ANALOG_DIGPROG_SILICON_REVISION_SHIFT (0U)
+/*! SILICON_REVISION
+ *  0b00000000011010100000000000000001..Silicon revision 1.1
+ */
 #define USB_ANALOG_DIGPROG_SILICON_REVISION(x)   (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_DIGPROG_SILICON_REVISION_SHIFT)) & USB_ANALOG_DIGPROG_SILICON_REVISION_MASK)
 /*! @} */
 
@@ -27225,9 +40817,26 @@ typedef struct {
 /*! @{ */
 #define USDHC_BLK_ATT_BLKSIZE_MASK               (0x1FFFU)
 #define USDHC_BLK_ATT_BLKSIZE_SHIFT              (0U)
+/*! BLKSIZE - Block Size
+ *  0b1000000000000..4096 Bytes
+ *  0b0100000000000..2048 Bytes
+ *  0b0001000000000..512 Bytes
+ *  0b0000111111111..511 Bytes
+ *  0b0000000000100..4 Bytes
+ *  0b0000000000011..3 Bytes
+ *  0b0000000000010..2 Bytes
+ *  0b0000000000001..1 Byte
+ *  0b0000000000000..No data transfer
+ */
 #define USDHC_BLK_ATT_BLKSIZE(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKSIZE_SHIFT)) & USDHC_BLK_ATT_BLKSIZE_MASK)
 #define USDHC_BLK_ATT_BLKCNT_MASK                (0xFFFF0000U)
 #define USDHC_BLK_ATT_BLKCNT_SHIFT               (16U)
+/*! BLKCNT - Block Count
+ *  0b1111111111111111..65535 blocks
+ *  0b0000000000000010..2 blocks
+ *  0b0000000000000001..1 block
+ *  0b0000000000000000..Stop Count
+ */
 #define USDHC_BLK_ATT_BLKCNT(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKCNT_SHIFT)) & USDHC_BLK_ATT_BLKCNT_MASK)
 /*! @} */
 
@@ -27242,18 +40851,42 @@ typedef struct {
 /*! @{ */
 #define USDHC_CMD_XFR_TYP_RSPTYP_MASK            (0x30000U)
 #define USDHC_CMD_XFR_TYP_RSPTYP_SHIFT           (16U)
+/*! RSPTYP - Response Type Select
+ *  0b00..No Response
+ *  0b01..Response Length 136
+ *  0b10..Response Length 48
+ *  0b11..Response Length 48, check Busy after response
+ */
 #define USDHC_CMD_XFR_TYP_RSPTYP(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_RSPTYP_SHIFT)) & USDHC_CMD_XFR_TYP_RSPTYP_MASK)
 #define USDHC_CMD_XFR_TYP_CCCEN_MASK             (0x80000U)
 #define USDHC_CMD_XFR_TYP_CCCEN_SHIFT            (19U)
+/*! CCCEN - Command CRC Check Enable
+ *  0b1..Enable
+ *  0b0..Disable
+ */
 #define USDHC_CMD_XFR_TYP_CCCEN(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CCCEN_SHIFT)) & USDHC_CMD_XFR_TYP_CCCEN_MASK)
 #define USDHC_CMD_XFR_TYP_CICEN_MASK             (0x100000U)
 #define USDHC_CMD_XFR_TYP_CICEN_SHIFT            (20U)
+/*! CICEN - Command Index Check Enable
+ *  0b1..Enable
+ *  0b0..Disable
+ */
 #define USDHC_CMD_XFR_TYP_CICEN(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CICEN_SHIFT)) & USDHC_CMD_XFR_TYP_CICEN_MASK)
 #define USDHC_CMD_XFR_TYP_DPSEL_MASK             (0x200000U)
 #define USDHC_CMD_XFR_TYP_DPSEL_SHIFT            (21U)
+/*! DPSEL - Data Present Select
+ *  0b1..Data Present
+ *  0b0..No Data Present
+ */
 #define USDHC_CMD_XFR_TYP_DPSEL(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_DPSEL_SHIFT)) & USDHC_CMD_XFR_TYP_DPSEL_MASK)
 #define USDHC_CMD_XFR_TYP_CMDTYP_MASK            (0xC00000U)
 #define USDHC_CMD_XFR_TYP_CMDTYP_SHIFT           (22U)
+/*! CMDTYP - Command Type
+ *  0b11..Abort CMD12, CMD52 for writing I/O Abort in CCCR
+ *  0b10..Resume CMD52 for writing Function Select in CCCR
+ *  0b01..Suspend CMD52 for writing Bus Suspend in CCCR
+ *  0b00..Normal Other commands
+ */
 #define USDHC_CMD_XFR_TYP_CMDTYP(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDTYP_SHIFT)) & USDHC_CMD_XFR_TYP_CMDTYP_MASK)
 #define USDHC_CMD_XFR_TYP_CMDINX_MASK            (0x3F000000U)
 #define USDHC_CMD_XFR_TYP_CMDINX_SHIFT           (24U)
@@ -27299,60 +40932,138 @@ typedef struct {
 /*! @{ */
 #define USDHC_PRES_STATE_CIHB_MASK               (0x1U)
 #define USDHC_PRES_STATE_CIHB_SHIFT              (0U)
+/*! CIHB - Command Inhibit (CMD)
+ *  0b1..Cannot issue command
+ *  0b0..Can issue command using only CMD line
+ */
 #define USDHC_PRES_STATE_CIHB(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CIHB_SHIFT)) & USDHC_PRES_STATE_CIHB_MASK)
 #define USDHC_PRES_STATE_CDIHB_MASK              (0x2U)
 #define USDHC_PRES_STATE_CDIHB_SHIFT             (1U)
+/*! CDIHB - Command Inhibit (DATA)
+ *  0b1..Cannot issue command which uses the DATA line
+ *  0b0..Can issue command which uses the DATA line
+ */
 #define USDHC_PRES_STATE_CDIHB(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDIHB_SHIFT)) & USDHC_PRES_STATE_CDIHB_MASK)
 #define USDHC_PRES_STATE_DLA_MASK                (0x4U)
 #define USDHC_PRES_STATE_DLA_SHIFT               (2U)
+/*! DLA - Data Line Active
+ *  0b1..DATA Line Active
+ *  0b0..DATA Line Inactive
+ */
 #define USDHC_PRES_STATE_DLA(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLA_SHIFT)) & USDHC_PRES_STATE_DLA_MASK)
 #define USDHC_PRES_STATE_SDSTB_MASK              (0x8U)
 #define USDHC_PRES_STATE_SDSTB_SHIFT             (3U)
+/*! SDSTB - SD Clock Stable
+ *  0b1..Clock is stable.
+ *  0b0..Clock is changing frequency and not stable.
+ */
 #define USDHC_PRES_STATE_SDSTB(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDSTB_SHIFT)) & USDHC_PRES_STATE_SDSTB_MASK)
 #define USDHC_PRES_STATE_IPGOFF_MASK             (0x10U)
 #define USDHC_PRES_STATE_IPGOFF_SHIFT            (4U)
+/*! IPGOFF - IPG_CLK Gated Off Internally
+ *  0b1..IPG_CLK is gated off.
+ *  0b0..IPG_CLK is active.
+ */
 #define USDHC_PRES_STATE_IPGOFF(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_IPGOFF_SHIFT)) & USDHC_PRES_STATE_IPGOFF_MASK)
 #define USDHC_PRES_STATE_HCKOFF_MASK             (0x20U)
 #define USDHC_PRES_STATE_HCKOFF_SHIFT            (5U)
+/*! HCKOFF - HCLK Gated Off Internally
+ *  0b1..HCLK is gated off.
+ *  0b0..HCLK is active.
+ */
 #define USDHC_PRES_STATE_HCKOFF(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_HCKOFF_SHIFT)) & USDHC_PRES_STATE_HCKOFF_MASK)
 #define USDHC_PRES_STATE_PEROFF_MASK             (0x40U)
 #define USDHC_PRES_STATE_PEROFF_SHIFT            (6U)
+/*! PEROFF - IPG_PERCLK Gated Off Internally
+ *  0b1..IPG_PERCLK is gated off.
+ *  0b0..IPG_PERCLK is active.
+ */
 #define USDHC_PRES_STATE_PEROFF(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_PEROFF_SHIFT)) & USDHC_PRES_STATE_PEROFF_MASK)
 #define USDHC_PRES_STATE_SDOFF_MASK              (0x80U)
 #define USDHC_PRES_STATE_SDOFF_SHIFT             (7U)
+/*! SDOFF - SD Clock Gated Off Internally
+ *  0b1..SD Clock is gated off.
+ *  0b0..SD Clock is active.
+ */
 #define USDHC_PRES_STATE_SDOFF(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDOFF_SHIFT)) & USDHC_PRES_STATE_SDOFF_MASK)
 #define USDHC_PRES_STATE_WTA_MASK                (0x100U)
 #define USDHC_PRES_STATE_WTA_SHIFT               (8U)
+/*! WTA - Write Transfer Active
+ *  0b1..Transferring data
+ *  0b0..No valid data
+ */
 #define USDHC_PRES_STATE_WTA(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WTA_SHIFT)) & USDHC_PRES_STATE_WTA_MASK)
 #define USDHC_PRES_STATE_RTA_MASK                (0x200U)
 #define USDHC_PRES_STATE_RTA_SHIFT               (9U)
+/*! RTA - Read Transfer Active
+ *  0b1..Transferring data
+ *  0b0..No valid data
+ */
 #define USDHC_PRES_STATE_RTA(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTA_SHIFT)) & USDHC_PRES_STATE_RTA_MASK)
 #define USDHC_PRES_STATE_BWEN_MASK               (0x400U)
 #define USDHC_PRES_STATE_BWEN_SHIFT              (10U)
+/*! BWEN - Buffer Write Enable
+ *  0b1..Write enable
+ *  0b0..Write disable
+ */
 #define USDHC_PRES_STATE_BWEN(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BWEN_SHIFT)) & USDHC_PRES_STATE_BWEN_MASK)
 #define USDHC_PRES_STATE_BREN_MASK               (0x800U)
 #define USDHC_PRES_STATE_BREN_SHIFT              (11U)
+/*! BREN - Buffer Read Enable
+ *  0b1..Read enable
+ *  0b0..Read disable
+ */
 #define USDHC_PRES_STATE_BREN(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BREN_SHIFT)) & USDHC_PRES_STATE_BREN_MASK)
 #define USDHC_PRES_STATE_RTR_MASK                (0x1000U)
 #define USDHC_PRES_STATE_RTR_SHIFT               (12U)
+/*! RTR - Re-Tuning Request (only for SD3.0 SDR104 mode and EMMC HS200 mode)
+ *  0b1..Sampling clock needs re-tuning
+ *  0b0..Fixed or well tuned sampling clock
+ */
 #define USDHC_PRES_STATE_RTR(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTR_SHIFT)) & USDHC_PRES_STATE_RTR_MASK)
 #define USDHC_PRES_STATE_TSCD_MASK               (0x8000U)
 #define USDHC_PRES_STATE_TSCD_SHIFT              (15U)
+/*! TSCD - Tape Select Change Done
+ *  0b1..Delay cell select change is finished.
+ *  0b0..Delay cell select change is not finished.
+ */
 #define USDHC_PRES_STATE_TSCD(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_TSCD_SHIFT)) & USDHC_PRES_STATE_TSCD_MASK)
 #define USDHC_PRES_STATE_CINST_MASK              (0x10000U)
 #define USDHC_PRES_STATE_CINST_SHIFT             (16U)
+/*! CINST - Card Inserted
+ *  0b1..Card Inserted
+ *  0b0..Power on Reset or No Card
+ */
 #define USDHC_PRES_STATE_CINST(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CINST_SHIFT)) & USDHC_PRES_STATE_CINST_MASK)
 #define USDHC_PRES_STATE_CDPL_MASK               (0x40000U)
 #define USDHC_PRES_STATE_CDPL_SHIFT              (18U)
+/*! CDPL - Card Detect Pin Level
+ *  0b1..Card present (CD_B = 0)
+ *  0b0..No card present (CD_B = 1)
+ */
 #define USDHC_PRES_STATE_CDPL(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDPL_SHIFT)) & USDHC_PRES_STATE_CDPL_MASK)
 #define USDHC_PRES_STATE_WPSPL_MASK              (0x80000U)
 #define USDHC_PRES_STATE_WPSPL_SHIFT             (19U)
+/*! WPSPL - Write Protect Switch Pin Level
+ *  0b1..Write enabled (WP = 0)
+ *  0b0..Write protected (WP = 1)
+ */
 #define USDHC_PRES_STATE_WPSPL(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WPSPL_SHIFT)) & USDHC_PRES_STATE_WPSPL_MASK)
 #define USDHC_PRES_STATE_CLSL_MASK               (0x800000U)
 #define USDHC_PRES_STATE_CLSL_SHIFT              (23U)
 #define USDHC_PRES_STATE_CLSL(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CLSL_SHIFT)) & USDHC_PRES_STATE_CLSL_MASK)
 #define USDHC_PRES_STATE_DLSL_MASK               (0xFF000000U)
 #define USDHC_PRES_STATE_DLSL_SHIFT              (24U)
+/*! DLSL - DATA[7:0] Line Signal Level
+ *  0b00000111..Data 7 line signal level
+ *  0b00000110..Data 6 line signal level
+ *  0b00000101..Data 5 line signal level
+ *  0b00000100..Data 4 line signal level
+ *  0b00000011..Data 3 line signal level
+ *  0b00000010..Data 2 line signal level
+ *  0b00000001..Data 1 line signal level
+ *  0b00000000..Data 0 line signal level
+ */
 #define USDHC_PRES_STATE_DLSL(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLSL_SHIFT)) & USDHC_PRES_STATE_DLSL_MASK)
 /*! @} */
 
@@ -27360,54 +41071,125 @@ typedef struct {
 /*! @{ */
 #define USDHC_PROT_CTRL_LCTL_MASK                (0x1U)
 #define USDHC_PROT_CTRL_LCTL_SHIFT               (0U)
+/*! LCTL - LED Control
+ *  0b1..LED on
+ *  0b0..LED off
+ */
 #define USDHC_PROT_CTRL_LCTL(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_LCTL_SHIFT)) & USDHC_PROT_CTRL_LCTL_MASK)
 #define USDHC_PROT_CTRL_DTW_MASK                 (0x6U)
 #define USDHC_PROT_CTRL_DTW_SHIFT                (1U)
+/*! DTW - Data Transfer Width
+ *  0b10..8-bit mode
+ *  0b01..4-bit mode
+ *  0b00..1-bit mode
+ *  0b11..Reserved
+ */
 #define USDHC_PROT_CTRL_DTW(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DTW_SHIFT)) & USDHC_PROT_CTRL_DTW_MASK)
 #define USDHC_PROT_CTRL_D3CD_MASK                (0x8U)
 #define USDHC_PROT_CTRL_D3CD_SHIFT               (3U)
+/*! D3CD - DATA3 as Card Detection Pin
+ *  0b1..DATA3 as Card Detection Pin
+ *  0b0..DATA3 does not monitor Card Insertion
+ */
 #define USDHC_PROT_CTRL_D3CD(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_D3CD_SHIFT)) & USDHC_PROT_CTRL_D3CD_MASK)
 #define USDHC_PROT_CTRL_EMODE_MASK               (0x30U)
 #define USDHC_PROT_CTRL_EMODE_SHIFT              (4U)
+/*! EMODE - Endian Mode
+ *  0b00..Big Endian Mode
+ *  0b01..Half Word Big Endian Mode
+ *  0b10..Little Endian Mode
+ *  0b11..Reserved
+ */
 #define USDHC_PROT_CTRL_EMODE(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_EMODE_SHIFT)) & USDHC_PROT_CTRL_EMODE_MASK)
 #define USDHC_PROT_CTRL_CDTL_MASK                (0x40U)
 #define USDHC_PROT_CTRL_CDTL_SHIFT               (6U)
+/*! CDTL - Card Detect Test Level
+ *  0b1..Card Detect Test Level is 1, card inserted
+ *  0b0..Card Detect Test Level is 0, no card inserted
+ */
 #define USDHC_PROT_CTRL_CDTL(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDTL_SHIFT)) & USDHC_PROT_CTRL_CDTL_MASK)
 #define USDHC_PROT_CTRL_CDSS_MASK                (0x80U)
 #define USDHC_PROT_CTRL_CDSS_SHIFT               (7U)
+/*! CDSS - Card Detect Signal Selection
+ *  0b1..Card Detection Test Level is selected (for test purpose).
+ *  0b0..Card Detection Level is selected (for normal purpose).
+ */
 #define USDHC_PROT_CTRL_CDSS(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDSS_SHIFT)) & USDHC_PROT_CTRL_CDSS_MASK)
 #define USDHC_PROT_CTRL_DMASEL_MASK              (0x300U)
 #define USDHC_PROT_CTRL_DMASEL_SHIFT             (8U)
+/*! DMASEL - DMA Select
+ *  0b00..No DMA or Simple DMA is selected
+ *  0b01..ADMA1 is selected
+ *  0b10..ADMA2 is selected
+ *  0b11..reserved
+ */
 #define USDHC_PROT_CTRL_DMASEL(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DMASEL_SHIFT)) & USDHC_PROT_CTRL_DMASEL_MASK)
 #define USDHC_PROT_CTRL_SABGREQ_MASK             (0x10000U)
 #define USDHC_PROT_CTRL_SABGREQ_SHIFT            (16U)
+/*! SABGREQ - Stop At Block Gap Request
+ *  0b1..Stop
+ *  0b0..Transfer
+ */
 #define USDHC_PROT_CTRL_SABGREQ(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_SABGREQ_SHIFT)) & USDHC_PROT_CTRL_SABGREQ_MASK)
 #define USDHC_PROT_CTRL_CREQ_MASK                (0x20000U)
 #define USDHC_PROT_CTRL_CREQ_SHIFT               (17U)
+/*! CREQ - Continue Request
+ *  0b1..Restart
+ *  0b0..No effect
+ */
 #define USDHC_PROT_CTRL_CREQ(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CREQ_SHIFT)) & USDHC_PROT_CTRL_CREQ_MASK)
 #define USDHC_PROT_CTRL_RWCTL_MASK               (0x40000U)
 #define USDHC_PROT_CTRL_RWCTL_SHIFT              (18U)
+/*! RWCTL - Read Wait Control
+ *  0b1..Enable Read Wait Control, and assert Read Wait without stopping SD Clock at block gap when SABGREQ bit is set
+ *  0b0..Disable Read Wait Control, and stop SD Clock at block gap when SABGREQ bit is set
+ */
 #define USDHC_PROT_CTRL_RWCTL(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RWCTL_SHIFT)) & USDHC_PROT_CTRL_RWCTL_MASK)
 #define USDHC_PROT_CTRL_IABG_MASK                (0x80000U)
 #define USDHC_PROT_CTRL_IABG_SHIFT               (19U)
+/*! IABG - Interrupt At Block Gap
+ *  0b1..Enabled
+ *  0b0..Disabled
+ */
 #define USDHC_PROT_CTRL_IABG(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_IABG_SHIFT)) & USDHC_PROT_CTRL_IABG_MASK)
 #define USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK     (0x100000U)
 #define USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT    (20U)
 #define USDHC_PROT_CTRL_RD_DONE_NO_8CLK(x)       (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT)) & USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK)
 #define USDHC_PROT_CTRL_WECINT_MASK              (0x1000000U)
 #define USDHC_PROT_CTRL_WECINT_SHIFT             (24U)
+/*! WECINT - Wakeup Event Enable On Card Interrupt
+ *  0b1..Enable
+ *  0b0..Disable
+ */
 #define USDHC_PROT_CTRL_WECINT(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINT_SHIFT)) & USDHC_PROT_CTRL_WECINT_MASK)
 #define USDHC_PROT_CTRL_WECINS_MASK              (0x2000000U)
 #define USDHC_PROT_CTRL_WECINS_SHIFT             (25U)
+/*! WECINS - Wakeup Event Enable On SD Card Insertion
+ *  0b1..Enable
+ *  0b0..Disable
+ */
 #define USDHC_PROT_CTRL_WECINS(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINS_SHIFT)) & USDHC_PROT_CTRL_WECINS_MASK)
 #define USDHC_PROT_CTRL_WECRM_MASK               (0x4000000U)
 #define USDHC_PROT_CTRL_WECRM_SHIFT              (26U)
+/*! WECRM - Wakeup Event Enable On SD Card Removal
+ *  0b1..Enable
+ *  0b0..Disable
+ */
 #define USDHC_PROT_CTRL_WECRM(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECRM_SHIFT)) & USDHC_PROT_CTRL_WECRM_MASK)
 #define USDHC_PROT_CTRL_BURST_LEN_EN_MASK        (0x38000000U)
 #define USDHC_PROT_CTRL_BURST_LEN_EN_SHIFT       (27U)
+/*! BURST_LEN_EN - BURST length enable for INCR, INCR4 / INCR8 / INCR16, INCR4-WRAP / INCR8-WRAP / INCR16-WRAP
+ *  0bxx1..Burst length is enabled for INCR
+ *  0bx1x..Burst length is enabled for INCR4 / INCR8 / INCR16
+ *  0b1xx..Burst length is enabled for INCR4-WRAP / INCR8-WRAP / INCR16-WRAP
+ */
 #define USDHC_PROT_CTRL_BURST_LEN_EN(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_BURST_LEN_EN_SHIFT)) & USDHC_PROT_CTRL_BURST_LEN_EN_MASK)
 #define USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK    (0x40000000U)
 #define USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT   (30U)
+/*! NON_EXACT_BLK_RD - NON_EXACT_BLK_RD
+ *  0b1..The block read is non-exact block read. Host driver needs to issue abort command to terminate this multi-block read.
+ *  0b0..The block read is exact block read. Host driver doesn't need to issue abort command to terminate this multi-block read.
+ */
 #define USDHC_PROT_CTRL_NON_EXACT_BLK_RD(x)      (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT)) & USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK)
 /*! @} */
 
@@ -27415,24 +41197,49 @@ typedef struct {
 /*! @{ */
 #define USDHC_SYS_CTRL_DVS_MASK                  (0xF0U)
 #define USDHC_SYS_CTRL_DVS_SHIFT                 (4U)
+/*! DVS - Divisor
+ *  0b0000..Divide-by-1
+ *  0b0001..Divide-by-2
+ *  0b1110..Divide-by-15
+ *  0b1111..Divide-by-16
+ */
 #define USDHC_SYS_CTRL_DVS(x)                    (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DVS_SHIFT)) & USDHC_SYS_CTRL_DVS_MASK)
 #define USDHC_SYS_CTRL_SDCLKFS_MASK              (0xFF00U)
 #define USDHC_SYS_CTRL_SDCLKFS_SHIFT             (8U)
 #define USDHC_SYS_CTRL_SDCLKFS(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_SDCLKFS_SHIFT)) & USDHC_SYS_CTRL_SDCLKFS_MASK)
 #define USDHC_SYS_CTRL_DTOCV_MASK                (0xF0000U)
 #define USDHC_SYS_CTRL_DTOCV_SHIFT               (16U)
+/*! DTOCV - Data Timeout Counter Value
+ *  0b1111..SDCLK x 2 29
+ *  0b1110..SDCLK x 2 28
+ *  0b1101..SDCLK x 2 27
+ *  0b0001..SDCLK x 2 15
+ *  0b0000..SDCLK x 2 14
+ */
 #define USDHC_SYS_CTRL_DTOCV(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DTOCV_SHIFT)) & USDHC_SYS_CTRL_DTOCV_MASK)
 #define USDHC_SYS_CTRL_IPP_RST_N_MASK            (0x800000U)
 #define USDHC_SYS_CTRL_IPP_RST_N_SHIFT           (23U)
 #define USDHC_SYS_CTRL_IPP_RST_N(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_IPP_RST_N_SHIFT)) & USDHC_SYS_CTRL_IPP_RST_N_MASK)
 #define USDHC_SYS_CTRL_RSTA_MASK                 (0x1000000U)
 #define USDHC_SYS_CTRL_RSTA_SHIFT                (24U)
+/*! RSTA - Software Reset For ALL
+ *  0b1..Reset
+ *  0b0..No Reset
+ */
 #define USDHC_SYS_CTRL_RSTA(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTA_SHIFT)) & USDHC_SYS_CTRL_RSTA_MASK)
 #define USDHC_SYS_CTRL_RSTC_MASK                 (0x2000000U)
 #define USDHC_SYS_CTRL_RSTC_SHIFT                (25U)
+/*! RSTC - Software Reset For CMD Line
+ *  0b1..Reset
+ *  0b0..No Reset
+ */
 #define USDHC_SYS_CTRL_RSTC(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTC_SHIFT)) & USDHC_SYS_CTRL_RSTC_MASK)
 #define USDHC_SYS_CTRL_RSTD_MASK                 (0x4000000U)
 #define USDHC_SYS_CTRL_RSTD_SHIFT                (26U)
+/*! RSTD - Software Reset For DATA Line
+ *  0b1..Reset
+ *  0b0..No Reset
+ */
 #define USDHC_SYS_CTRL_RSTD(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTD_SHIFT)) & USDHC_SYS_CTRL_RSTD_MASK)
 #define USDHC_SYS_CTRL_INITA_MASK                (0x8000000U)
 #define USDHC_SYS_CTRL_INITA_SHIFT               (27U)
@@ -27446,66 +41253,142 @@ typedef struct {
 /*! @{ */
 #define USDHC_INT_STATUS_CC_MASK                 (0x1U)
 #define USDHC_INT_STATUS_CC_SHIFT                (0U)
+/*! CC - Command Complete
+ *  0b1..Command complete
+ *  0b0..Command not complete
+ */
 #define USDHC_INT_STATUS_CC(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CC_SHIFT)) & USDHC_INT_STATUS_CC_MASK)
 #define USDHC_INT_STATUS_TC_MASK                 (0x2U)
 #define USDHC_INT_STATUS_TC_SHIFT                (1U)
+/*! TC - Transfer Complete
+ *  0b1..Transfer complete
+ *  0b0..Transfer not complete
+ */
 #define USDHC_INT_STATUS_TC(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TC_SHIFT)) & USDHC_INT_STATUS_TC_MASK)
 #define USDHC_INT_STATUS_BGE_MASK                (0x4U)
 #define USDHC_INT_STATUS_BGE_SHIFT               (2U)
+/*! BGE - Block Gap Event
+ *  0b1..Transaction stopped at block gap
+ *  0b0..No block gap event
+ */
 #define USDHC_INT_STATUS_BGE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BGE_SHIFT)) & USDHC_INT_STATUS_BGE_MASK)
 #define USDHC_INT_STATUS_DINT_MASK               (0x8U)
 #define USDHC_INT_STATUS_DINT_SHIFT              (3U)
+/*! DINT - DMA Interrupt
+ *  0b1..DMA Interrupt is generated
+ *  0b0..No DMA Interrupt
+ */
 #define USDHC_INT_STATUS_DINT(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DINT_SHIFT)) & USDHC_INT_STATUS_DINT_MASK)
 #define USDHC_INT_STATUS_BWR_MASK                (0x10U)
 #define USDHC_INT_STATUS_BWR_SHIFT               (4U)
+/*! BWR - Buffer Write Ready
+ *  0b1..Ready to write buffer:
+ *  0b0..Not ready to write buffer
+ */
 #define USDHC_INT_STATUS_BWR(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BWR_SHIFT)) & USDHC_INT_STATUS_BWR_MASK)
 #define USDHC_INT_STATUS_BRR_MASK                (0x20U)
 #define USDHC_INT_STATUS_BRR_SHIFT               (5U)
+/*! BRR - Buffer Read Ready
+ *  0b1..Ready to read buffer
+ *  0b0..Not ready to read buffer
+ */
 #define USDHC_INT_STATUS_BRR(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BRR_SHIFT)) & USDHC_INT_STATUS_BRR_MASK)
 #define USDHC_INT_STATUS_CINS_MASK               (0x40U)
 #define USDHC_INT_STATUS_CINS_SHIFT              (6U)
+/*! CINS - Card Insertion
+ *  0b1..Card inserted
+ *  0b0..Card state unstable or removed
+ */
 #define USDHC_INT_STATUS_CINS(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINS_SHIFT)) & USDHC_INT_STATUS_CINS_MASK)
 #define USDHC_INT_STATUS_CRM_MASK                (0x80U)
 #define USDHC_INT_STATUS_CRM_SHIFT               (7U)
+/*! CRM - Card Removal
+ *  0b1..Card removed
+ *  0b0..Card state unstable or inserted
+ */
 #define USDHC_INT_STATUS_CRM(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CRM_SHIFT)) & USDHC_INT_STATUS_CRM_MASK)
 #define USDHC_INT_STATUS_CINT_MASK               (0x100U)
 #define USDHC_INT_STATUS_CINT_SHIFT              (8U)
+/*! CINT - Card Interrupt
+ *  0b1..Generate Card Interrupt
+ *  0b0..No Card Interrupt
+ */
 #define USDHC_INT_STATUS_CINT(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINT_SHIFT)) & USDHC_INT_STATUS_CINT_MASK)
 #define USDHC_INT_STATUS_RTE_MASK                (0x1000U)
 #define USDHC_INT_STATUS_RTE_SHIFT               (12U)
+/*! RTE - Re-Tuning Event: (only for SD3.0 SDR104 mode and EMMC HS200 mode)
+ *  0b1..Re-Tuning should be performed
+ *  0b0..Re-Tuning is not required
+ */
 #define USDHC_INT_STATUS_RTE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_RTE_SHIFT)) & USDHC_INT_STATUS_RTE_MASK)
 #define USDHC_INT_STATUS_TP_MASK                 (0x4000U)
 #define USDHC_INT_STATUS_TP_SHIFT                (14U)
 #define USDHC_INT_STATUS_TP(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TP_SHIFT)) & USDHC_INT_STATUS_TP_MASK)
 #define USDHC_INT_STATUS_CTOE_MASK               (0x10000U)
 #define USDHC_INT_STATUS_CTOE_SHIFT              (16U)
+/*! CTOE - Command Timeout Error
+ *  0b1..Time out
+ *  0b0..No Error
+ */
 #define USDHC_INT_STATUS_CTOE(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CTOE_SHIFT)) & USDHC_INT_STATUS_CTOE_MASK)
 #define USDHC_INT_STATUS_CCE_MASK                (0x20000U)
 #define USDHC_INT_STATUS_CCE_SHIFT               (17U)
+/*! CCE - Command CRC Error
+ *  0b1..CRC Error Generated.
+ *  0b0..No Error
+ */
 #define USDHC_INT_STATUS_CCE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CCE_SHIFT)) & USDHC_INT_STATUS_CCE_MASK)
 #define USDHC_INT_STATUS_CEBE_MASK               (0x40000U)
 #define USDHC_INT_STATUS_CEBE_SHIFT              (18U)
+/*! CEBE - Command End Bit Error
+ *  0b1..End Bit Error Generated
+ *  0b0..No Error
+ */
 #define USDHC_INT_STATUS_CEBE(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CEBE_SHIFT)) & USDHC_INT_STATUS_CEBE_MASK)
 #define USDHC_INT_STATUS_CIE_MASK                (0x80000U)
 #define USDHC_INT_STATUS_CIE_SHIFT               (19U)
+/*! CIE - Command Index Error
+ *  0b1..Error
+ *  0b0..No Error
+ */
 #define USDHC_INT_STATUS_CIE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CIE_SHIFT)) & USDHC_INT_STATUS_CIE_MASK)
 #define USDHC_INT_STATUS_DTOE_MASK               (0x100000U)
 #define USDHC_INT_STATUS_DTOE_SHIFT              (20U)
+/*! DTOE - Data Timeout Error
+ *  0b1..Time out
+ *  0b0..No Error
+ */
 #define USDHC_INT_STATUS_DTOE(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DTOE_SHIFT)) & USDHC_INT_STATUS_DTOE_MASK)
 #define USDHC_INT_STATUS_DCE_MASK                (0x200000U)
 #define USDHC_INT_STATUS_DCE_SHIFT               (21U)
+/*! DCE - Data CRC Error
+ *  0b1..Error
+ *  0b0..No Error
+ */
 #define USDHC_INT_STATUS_DCE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DCE_SHIFT)) & USDHC_INT_STATUS_DCE_MASK)
 #define USDHC_INT_STATUS_DEBE_MASK               (0x400000U)
 #define USDHC_INT_STATUS_DEBE_SHIFT              (22U)
+/*! DEBE - Data End Bit Error
+ *  0b1..Error
+ *  0b0..No Error
+ */
 #define USDHC_INT_STATUS_DEBE(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DEBE_SHIFT)) & USDHC_INT_STATUS_DEBE_MASK)
 #define USDHC_INT_STATUS_AC12E_MASK              (0x1000000U)
 #define USDHC_INT_STATUS_AC12E_SHIFT             (24U)
+/*! AC12E - Auto CMD12 Error
+ *  0b1..Error
+ *  0b0..No Error
+ */
 #define USDHC_INT_STATUS_AC12E(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_AC12E_SHIFT)) & USDHC_INT_STATUS_AC12E_MASK)
 #define USDHC_INT_STATUS_TNE_MASK                (0x4000000U)
 #define USDHC_INT_STATUS_TNE_SHIFT               (26U)
 #define USDHC_INT_STATUS_TNE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TNE_SHIFT)) & USDHC_INT_STATUS_TNE_MASK)
 #define USDHC_INT_STATUS_DMAE_MASK               (0x10000000U)
 #define USDHC_INT_STATUS_DMAE_SHIFT              (28U)
+/*! DMAE - DMA Error
+ *  0b1..Error
+ *  0b0..No Error
+ */
 #define USDHC_INT_STATUS_DMAE(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DMAE_SHIFT)) & USDHC_INT_STATUS_DMAE_MASK)
 /*! @} */
 
@@ -27513,66 +41396,150 @@ typedef struct {
 /*! @{ */
 #define USDHC_INT_STATUS_EN_CCSEN_MASK           (0x1U)
 #define USDHC_INT_STATUS_EN_CCSEN_SHIFT          (0U)
+/*! CCSEN - Command Complete Status Enable
+ *  0b1..Enabled
+ *  0b0..Masked
+ */
 #define USDHC_INT_STATUS_EN_CCSEN(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCSEN_SHIFT)) & USDHC_INT_STATUS_EN_CCSEN_MASK)
 #define USDHC_INT_STATUS_EN_TCSEN_MASK           (0x2U)
 #define USDHC_INT_STATUS_EN_TCSEN_SHIFT          (1U)
+/*! TCSEN - Transfer Complete Status Enable
+ *  0b1..Enabled
+ *  0b0..Masked
+ */
 #define USDHC_INT_STATUS_EN_TCSEN(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TCSEN_SHIFT)) & USDHC_INT_STATUS_EN_TCSEN_MASK)
 #define USDHC_INT_STATUS_EN_BGESEN_MASK          (0x4U)
 #define USDHC_INT_STATUS_EN_BGESEN_SHIFT         (2U)
+/*! BGESEN - Block Gap Event Status Enable
+ *  0b1..Enabled
+ *  0b0..Masked
+ */
 #define USDHC_INT_STATUS_EN_BGESEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BGESEN_SHIFT)) & USDHC_INT_STATUS_EN_BGESEN_MASK)
 #define USDHC_INT_STATUS_EN_DINTSEN_MASK         (0x8U)
 #define USDHC_INT_STATUS_EN_DINTSEN_SHIFT        (3U)
+/*! DINTSEN - DMA Interrupt Status Enable
+ *  0b1..Enabled
+ *  0b0..Masked
+ */
 #define USDHC_INT_STATUS_EN_DINTSEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_DINTSEN_MASK)
 #define USDHC_INT_STATUS_EN_BWRSEN_MASK          (0x10U)
 #define USDHC_INT_STATUS_EN_BWRSEN_SHIFT         (4U)
+/*! BWRSEN - Buffer Write Ready Status Enable
+ *  0b1..Enabled
+ *  0b0..Masked
+ */
 #define USDHC_INT_STATUS_EN_BWRSEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BWRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BWRSEN_MASK)
 #define USDHC_INT_STATUS_EN_BRRSEN_MASK          (0x20U)
 #define USDHC_INT_STATUS_EN_BRRSEN_SHIFT         (5U)
+/*! BRRSEN - Buffer Read Ready Status Enable
+ *  0b1..Enabled
+ *  0b0..Masked
+ */
 #define USDHC_INT_STATUS_EN_BRRSEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BRRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BRRSEN_MASK)
 #define USDHC_INT_STATUS_EN_CINSSEN_MASK         (0x40U)
 #define USDHC_INT_STATUS_EN_CINSSEN_SHIFT        (6U)
+/*! CINSSEN - Card Insertion Status Enable
+ *  0b1..Enabled
+ *  0b0..Masked
+ */
 #define USDHC_INT_STATUS_EN_CINSSEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINSSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINSSEN_MASK)
 #define USDHC_INT_STATUS_EN_CRMSEN_MASK          (0x80U)
 #define USDHC_INT_STATUS_EN_CRMSEN_SHIFT         (7U)
+/*! CRMSEN - Card Removal Status Enable
+ *  0b1..Enabled
+ *  0b0..Masked
+ */
 #define USDHC_INT_STATUS_EN_CRMSEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CRMSEN_SHIFT)) & USDHC_INT_STATUS_EN_CRMSEN_MASK)
 #define USDHC_INT_STATUS_EN_CINTSEN_MASK         (0x100U)
 #define USDHC_INT_STATUS_EN_CINTSEN_SHIFT        (8U)
+/*! CINTSEN - Card Interrupt Status Enable
+ *  0b1..Enabled
+ *  0b0..Masked
+ */
 #define USDHC_INT_STATUS_EN_CINTSEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINTSEN_MASK)
 #define USDHC_INT_STATUS_EN_RTESEN_MASK          (0x1000U)
 #define USDHC_INT_STATUS_EN_RTESEN_SHIFT         (12U)
+/*! RTESEN - Re-Tuning Event Status Enable
+ *  0b1..Enabled
+ *  0b0..Masked
+ */
 #define USDHC_INT_STATUS_EN_RTESEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_RTESEN_SHIFT)) & USDHC_INT_STATUS_EN_RTESEN_MASK)
 #define USDHC_INT_STATUS_EN_TPSEN_MASK           (0x4000U)
 #define USDHC_INT_STATUS_EN_TPSEN_SHIFT          (14U)
+/*! TPSEN - Tuning Pass Status Enable
+ *  0b1..Enabled
+ *  0b0..Masked
+ */
 #define USDHC_INT_STATUS_EN_TPSEN(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TPSEN_SHIFT)) & USDHC_INT_STATUS_EN_TPSEN_MASK)
 #define USDHC_INT_STATUS_EN_CTOESEN_MASK         (0x10000U)
 #define USDHC_INT_STATUS_EN_CTOESEN_SHIFT        (16U)
+/*! CTOESEN - Command Timeout Error Status Enable
+ *  0b1..Enabled
+ *  0b0..Masked
+ */
 #define USDHC_INT_STATUS_EN_CTOESEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_CTOESEN_MASK)
 #define USDHC_INT_STATUS_EN_CCESEN_MASK          (0x20000U)
 #define USDHC_INT_STATUS_EN_CCESEN_SHIFT         (17U)
+/*! CCESEN - Command CRC Error Status Enable
+ *  0b1..Enabled
+ *  0b0..Masked
+ */
 #define USDHC_INT_STATUS_EN_CCESEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCESEN_SHIFT)) & USDHC_INT_STATUS_EN_CCESEN_MASK)
 #define USDHC_INT_STATUS_EN_CEBESEN_MASK         (0x40000U)
 #define USDHC_INT_STATUS_EN_CEBESEN_SHIFT        (18U)
+/*! CEBESEN - Command End Bit Error Status Enable
+ *  0b1..Enabled
+ *  0b0..Masked
+ */
 #define USDHC_INT_STATUS_EN_CEBESEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_CEBESEN_MASK)
 #define USDHC_INT_STATUS_EN_CIESEN_MASK          (0x80000U)
 #define USDHC_INT_STATUS_EN_CIESEN_SHIFT         (19U)
+/*! CIESEN - Command Index Error Status Enable
+ *  0b1..Enabled
+ *  0b0..Masked
+ */
 #define USDHC_INT_STATUS_EN_CIESEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CIESEN_SHIFT)) & USDHC_INT_STATUS_EN_CIESEN_MASK)
 #define USDHC_INT_STATUS_EN_DTOESEN_MASK         (0x100000U)
 #define USDHC_INT_STATUS_EN_DTOESEN_SHIFT        (20U)
+/*! DTOESEN - Data Timeout Error Status Enable
+ *  0b1..Enabled
+ *  0b0..Masked
+ */
 #define USDHC_INT_STATUS_EN_DTOESEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_DTOESEN_MASK)
 #define USDHC_INT_STATUS_EN_DCESEN_MASK          (0x200000U)
 #define USDHC_INT_STATUS_EN_DCESEN_SHIFT         (21U)
+/*! DCESEN - Data CRC Error Status Enable
+ *  0b1..Enabled
+ *  0b0..Masked
+ */
 #define USDHC_INT_STATUS_EN_DCESEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DCESEN_SHIFT)) & USDHC_INT_STATUS_EN_DCESEN_MASK)
 #define USDHC_INT_STATUS_EN_DEBESEN_MASK         (0x400000U)
 #define USDHC_INT_STATUS_EN_DEBESEN_SHIFT        (22U)
+/*! DEBESEN - Data End Bit Error Status Enable
+ *  0b1..Enabled
+ *  0b0..Masked
+ */
 #define USDHC_INT_STATUS_EN_DEBESEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_DEBESEN_MASK)
 #define USDHC_INT_STATUS_EN_AC12ESEN_MASK        (0x1000000U)
 #define USDHC_INT_STATUS_EN_AC12ESEN_SHIFT       (24U)
+/*! AC12ESEN - Auto CMD12 Error Status Enable
+ *  0b1..Enabled
+ *  0b0..Masked
+ */
 #define USDHC_INT_STATUS_EN_AC12ESEN(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_AC12ESEN_SHIFT)) & USDHC_INT_STATUS_EN_AC12ESEN_MASK)
 #define USDHC_INT_STATUS_EN_TNESEN_MASK          (0x4000000U)
 #define USDHC_INT_STATUS_EN_TNESEN_SHIFT         (26U)
+/*! TNESEN - Tuning Error Status Enable
+ *  0b1..Enabled
+ *  0b0..Masked
+ */
 #define USDHC_INT_STATUS_EN_TNESEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TNESEN_SHIFT)) & USDHC_INT_STATUS_EN_TNESEN_MASK)
 #define USDHC_INT_STATUS_EN_DMAESEN_MASK         (0x10000000U)
 #define USDHC_INT_STATUS_EN_DMAESEN_SHIFT        (28U)
+/*! DMAESEN - DMA Error Status Enable
+ *  0b1..Enabled
+ *  0b0..Masked
+ */
 #define USDHC_INT_STATUS_EN_DMAESEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DMAESEN_SHIFT)) & USDHC_INT_STATUS_EN_DMAESEN_MASK)
 /*! @} */
 
@@ -27580,66 +41547,150 @@ typedef struct {
 /*! @{ */
 #define USDHC_INT_SIGNAL_EN_CCIEN_MASK           (0x1U)
 #define USDHC_INT_SIGNAL_EN_CCIEN_SHIFT          (0U)
+/*! CCIEN - Command Complete Interrupt Enable
+ *  0b1..Enabled
+ *  0b0..Masked
+ */
 #define USDHC_INT_SIGNAL_EN_CCIEN(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCIEN_MASK)
 #define USDHC_INT_SIGNAL_EN_TCIEN_MASK           (0x2U)
 #define USDHC_INT_SIGNAL_EN_TCIEN_SHIFT          (1U)
+/*! TCIEN - Transfer Complete Interrupt Enable
+ *  0b1..Enabled
+ *  0b0..Masked
+ */
 #define USDHC_INT_SIGNAL_EN_TCIEN(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TCIEN_MASK)
 #define USDHC_INT_SIGNAL_EN_BGEIEN_MASK          (0x4U)
 #define USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT         (2U)
+/*! BGEIEN - Block Gap Event Interrupt Enable
+ *  0b1..Enabled
+ *  0b0..Masked
+ */
 #define USDHC_INT_SIGNAL_EN_BGEIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BGEIEN_MASK)
 #define USDHC_INT_SIGNAL_EN_DINTIEN_MASK         (0x8U)
 #define USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT        (3U)
+/*! DINTIEN - DMA Interrupt Enable
+ *  0b1..Enabled
+ *  0b0..Masked
+ */
 #define USDHC_INT_SIGNAL_EN_DINTIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DINTIEN_MASK)
 #define USDHC_INT_SIGNAL_EN_BWRIEN_MASK          (0x10U)
 #define USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT         (4U)
+/*! BWRIEN - Buffer Write Ready Interrupt Enable
+ *  0b1..Enabled
+ *  0b0..Masked
+ */
 #define USDHC_INT_SIGNAL_EN_BWRIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BWRIEN_MASK)
 #define USDHC_INT_SIGNAL_EN_BRRIEN_MASK          (0x20U)
 #define USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT         (5U)
+/*! BRRIEN - Buffer Read Ready Interrupt Enable
+ *  0b1..Enabled
+ *  0b0..Masked
+ */
 #define USDHC_INT_SIGNAL_EN_BRRIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BRRIEN_MASK)
 #define USDHC_INT_SIGNAL_EN_CINSIEN_MASK         (0x40U)
 #define USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT        (6U)
+/*! CINSIEN - Card Insertion Interrupt Enable
+ *  0b1..Enabled
+ *  0b0..Masked
+ */
 #define USDHC_INT_SIGNAL_EN_CINSIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINSIEN_MASK)
 #define USDHC_INT_SIGNAL_EN_CRMIEN_MASK          (0x80U)
 #define USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT         (7U)
+/*! CRMIEN - Card Removal Interrupt Enable
+ *  0b1..Enabled
+ *  0b0..Masked
+ */
 #define USDHC_INT_SIGNAL_EN_CRMIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CRMIEN_MASK)
 #define USDHC_INT_SIGNAL_EN_CINTIEN_MASK         (0x100U)
 #define USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT        (8U)
+/*! CINTIEN - Card Interrupt Interrupt Enable
+ *  0b1..Enabled
+ *  0b0..Masked
+ */
 #define USDHC_INT_SIGNAL_EN_CINTIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINTIEN_MASK)
 #define USDHC_INT_SIGNAL_EN_RTEIEN_MASK          (0x1000U)
 #define USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT         (12U)
+/*! RTEIEN - Re-Tuning Event Interrupt Enable
+ *  0b1..Enabled
+ *  0b0..Masked
+ */
 #define USDHC_INT_SIGNAL_EN_RTEIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_RTEIEN_MASK)
 #define USDHC_INT_SIGNAL_EN_TPIEN_MASK           (0x4000U)
 #define USDHC_INT_SIGNAL_EN_TPIEN_SHIFT          (14U)
+/*! TPIEN - Tuning Pass Interrupt Enable
+ *  0b1..Enabled
+ *  0b0..Masked
+ */
 #define USDHC_INT_SIGNAL_EN_TPIEN(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TPIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TPIEN_MASK)
 #define USDHC_INT_SIGNAL_EN_CTOEIEN_MASK         (0x10000U)
 #define USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT        (16U)
+/*! CTOEIEN - Command Timeout Error Interrupt Enable
+ *  0b1..Enabled
+ *  0b0..Masked
+ */
 #define USDHC_INT_SIGNAL_EN_CTOEIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CTOEIEN_MASK)
 #define USDHC_INT_SIGNAL_EN_CCEIEN_MASK          (0x20000U)
 #define USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT         (17U)
+/*! CCEIEN - Command CRC Error Interrupt Enable
+ *  0b1..Enabled
+ *  0b0..Masked
+ */
 #define USDHC_INT_SIGNAL_EN_CCEIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCEIEN_MASK)
 #define USDHC_INT_SIGNAL_EN_CEBEIEN_MASK         (0x40000U)
 #define USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT        (18U)
+/*! CEBEIEN - Command End Bit Error Interrupt Enable
+ *  0b1..Enabled
+ *  0b0..Masked
+ */
 #define USDHC_INT_SIGNAL_EN_CEBEIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CEBEIEN_MASK)
 #define USDHC_INT_SIGNAL_EN_CIEIEN_MASK          (0x80000U)
 #define USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT         (19U)
+/*! CIEIEN - Command Index Error Interrupt Enable
+ *  0b1..Enabled
+ *  0b0..Masked
+ */
 #define USDHC_INT_SIGNAL_EN_CIEIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CIEIEN_MASK)
 #define USDHC_INT_SIGNAL_EN_DTOEIEN_MASK         (0x100000U)
 #define USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT        (20U)
+/*! DTOEIEN - Data Timeout Error Interrupt Enable
+ *  0b1..Enabled
+ *  0b0..Masked
+ */
 #define USDHC_INT_SIGNAL_EN_DTOEIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DTOEIEN_MASK)
 #define USDHC_INT_SIGNAL_EN_DCEIEN_MASK          (0x200000U)
 #define USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT         (21U)
+/*! DCEIEN - Data CRC Error Interrupt Enable
+ *  0b1..Enabled
+ *  0b0..Masked
+ */
 #define USDHC_INT_SIGNAL_EN_DCEIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DCEIEN_MASK)
 #define USDHC_INT_SIGNAL_EN_DEBEIEN_MASK         (0x400000U)
 #define USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT        (22U)
+/*! DEBEIEN - Data End Bit Error Interrupt Enable
+ *  0b1..Enabled
+ *  0b0..Masked
+ */
 #define USDHC_INT_SIGNAL_EN_DEBEIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DEBEIEN_MASK)
 #define USDHC_INT_SIGNAL_EN_AC12EIEN_MASK        (0x1000000U)
 #define USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT       (24U)
+/*! AC12EIEN - Auto CMD12 Error Interrupt Enable
+ *  0b1..Enabled
+ *  0b0..Masked
+ */
 #define USDHC_INT_SIGNAL_EN_AC12EIEN(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_AC12EIEN_MASK)
 #define USDHC_INT_SIGNAL_EN_TNEIEN_MASK          (0x4000000U)
 #define USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT         (26U)
+/*! TNEIEN - Tuning Error Interrupt Enable
+ *  0b1..Enabled
+ *  0b0..Masked
+ */
 #define USDHC_INT_SIGNAL_EN_TNEIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TNEIEN_MASK)
 #define USDHC_INT_SIGNAL_EN_DMAEIEN_MASK         (0x10000000U)
 #define USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT        (28U)
+/*! DMAEIEN - DMA Error Interrupt Enable
+ *  0b1..Enable
+ *  0b0..Masked
+ */
 #define USDHC_INT_SIGNAL_EN_DMAEIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DMAEIEN_MASK)
 /*! @} */
 
@@ -27647,27 +41698,55 @@ typedef struct {
 /*! @{ */
 #define USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK   (0x1U)
 #define USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT  (0U)
+/*! AC12NE - Auto CMD12 Not Executed
+ *  0b1..Not executed
+ *  0b0..Executed
+ */
 #define USDHC_AUTOCMD12_ERR_STATUS_AC12NE(x)     (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK)
 #define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK  (0x2U)
 #define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT (1U)
+/*! AC12TOE - Auto CMD12 / 23 Timeout Error
+ *  0b1..Time out
+ *  0b0..No error
+ */
 #define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE(x)    (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK)
 #define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK  (0x4U)
 #define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT (2U)
+/*! AC12EBE - Auto CMD12 / 23 End Bit Error
+ *  0b1..End Bit Error Generated
+ *  0b0..No error
+ */
 #define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE(x)    (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK)
 #define USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK   (0x8U)
 #define USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT  (3U)
+/*! AC12CE - Auto CMD12 / 23 CRC Error
+ *  0b1..CRC Error Met in Auto CMD12/23 Response
+ *  0b0..No CRC error
+ */
 #define USDHC_AUTOCMD12_ERR_STATUS_AC12CE(x)     (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK)
 #define USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK   (0x10U)
 #define USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT  (4U)
+/*! AC12IE - Auto CMD12 / 23 Index Error
+ *  0b1..Error, the CMD index in response is not CMD12/23
+ *  0b0..No error
+ */
 #define USDHC_AUTOCMD12_ERR_STATUS_AC12IE(x)     (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK)
 #define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK (0x80U)
 #define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT (7U)
+/*! CNIBAC12E - Command Not Issued By Auto CMD12 Error
+ *  0b1..Not Issued
+ *  0b0..No error
+ */
 #define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E(x)  (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK)
 #define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK (0x400000U)
 #define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT (22U)
 #define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK)
 #define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK (0x800000U)
 #define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT (23U)
+/*! SMP_CLK_SEL - Sample Clock Select
+ *  0b1..Tuned clock is used to sample data
+ *  0b0..Fixed clock is used to sample data
+ */
 #define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK)
 /*! @} */
 
@@ -27687,33 +41766,77 @@ typedef struct {
 #define USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_SHIFT)) & USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_MASK)
 #define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK (0x2000U)
 #define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT (13U)
+/*! USE_TUNING_SDR50 - Use Tuning for SDR50
+ *  0b1..SDR50 requires tuning
+ *  0b0..SDR does not require tuning
+ */
 #define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50(x)  (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT)) & USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK)
 #define USDHC_HOST_CTRL_CAP_RETUNING_MODE_MASK   (0xC000U)
 #define USDHC_HOST_CTRL_CAP_RETUNING_MODE_SHIFT  (14U)
+/*! RETUNING_MODE - Retuning Mode
+ *  0b00..Mode 1
+ *  0b01..Mode 2
+ *  0b10..Mode 3
+ *  0b11..Reserved
+ */
 #define USDHC_HOST_CTRL_CAP_RETUNING_MODE(x)     (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_RETUNING_MODE_SHIFT)) & USDHC_HOST_CTRL_CAP_RETUNING_MODE_MASK)
 #define USDHC_HOST_CTRL_CAP_MBL_MASK             (0x70000U)
 #define USDHC_HOST_CTRL_CAP_MBL_SHIFT            (16U)
+/*! MBL - Max Block Length
+ *  0b000..512 bytes
+ *  0b001..1024 bytes
+ *  0b010..2048 bytes
+ *  0b011..4096 bytes
+ */
 #define USDHC_HOST_CTRL_CAP_MBL(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_MBL_SHIFT)) & USDHC_HOST_CTRL_CAP_MBL_MASK)
 #define USDHC_HOST_CTRL_CAP_ADMAS_MASK           (0x100000U)
 #define USDHC_HOST_CTRL_CAP_ADMAS_SHIFT          (20U)
+/*! ADMAS - ADMA Support
+ *  0b1..Advanced DMA Supported
+ *  0b0..Advanced DMA Not supported
+ */
 #define USDHC_HOST_CTRL_CAP_ADMAS(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_ADMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_ADMAS_MASK)
 #define USDHC_HOST_CTRL_CAP_HSS_MASK             (0x200000U)
 #define USDHC_HOST_CTRL_CAP_HSS_SHIFT            (21U)
+/*! HSS - High Speed Support
+ *  0b1..High Speed Supported
+ *  0b0..High Speed Not Supported
+ */
 #define USDHC_HOST_CTRL_CAP_HSS(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_HSS_SHIFT)) & USDHC_HOST_CTRL_CAP_HSS_MASK)
 #define USDHC_HOST_CTRL_CAP_DMAS_MASK            (0x400000U)
 #define USDHC_HOST_CTRL_CAP_DMAS_SHIFT           (22U)
+/*! DMAS - DMA Support
+ *  0b1..DMA Supported
+ *  0b0..DMA not supported
+ */
 #define USDHC_HOST_CTRL_CAP_DMAS(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_DMAS_MASK)
 #define USDHC_HOST_CTRL_CAP_SRS_MASK             (0x800000U)
 #define USDHC_HOST_CTRL_CAP_SRS_SHIFT            (23U)
+/*! SRS - Suspend / Resume Support
+ *  0b1..Supported
+ *  0b0..Not supported
+ */
 #define USDHC_HOST_CTRL_CAP_SRS(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SRS_SHIFT)) & USDHC_HOST_CTRL_CAP_SRS_MASK)
 #define USDHC_HOST_CTRL_CAP_VS33_MASK            (0x1000000U)
 #define USDHC_HOST_CTRL_CAP_VS33_SHIFT           (24U)
+/*! VS33 - Voltage Support 3.3V
+ *  0b1..3.3V supported
+ *  0b0..3.3V not supported
+ */
 #define USDHC_HOST_CTRL_CAP_VS33(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS33_SHIFT)) & USDHC_HOST_CTRL_CAP_VS33_MASK)
 #define USDHC_HOST_CTRL_CAP_VS30_MASK            (0x2000000U)
 #define USDHC_HOST_CTRL_CAP_VS30_SHIFT           (25U)
+/*! VS30 - Voltage Support 3.0 V
+ *  0b1..3.0V supported
+ *  0b0..3.0V not supported
+ */
 #define USDHC_HOST_CTRL_CAP_VS30(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS30_SHIFT)) & USDHC_HOST_CTRL_CAP_VS30_MASK)
 #define USDHC_HOST_CTRL_CAP_VS18_MASK            (0x4000000U)
 #define USDHC_HOST_CTRL_CAP_VS18_SHIFT           (26U)
+/*! VS18 - Voltage Support 1.8 V
+ *  0b1..1.8V supported
+ *  0b0..1.8V not supported
+ */
 #define USDHC_HOST_CTRL_CAP_VS18(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS18_SHIFT)) & USDHC_HOST_CTRL_CAP_VS18_MASK)
 /*! @} */
 
@@ -27737,21 +41860,41 @@ typedef struct {
 /*! @{ */
 #define USDHC_MIX_CTRL_DMAEN_MASK                (0x1U)
 #define USDHC_MIX_CTRL_DMAEN_SHIFT               (0U)
+/*! DMAEN - DMA Enable
+ *  0b1..Enable
+ *  0b0..Disable
+ */
 #define USDHC_MIX_CTRL_DMAEN(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DMAEN_SHIFT)) & USDHC_MIX_CTRL_DMAEN_MASK)
 #define USDHC_MIX_CTRL_BCEN_MASK                 (0x2U)
 #define USDHC_MIX_CTRL_BCEN_SHIFT                (1U)
+/*! BCEN - Block Count Enable
+ *  0b1..Enable
+ *  0b0..Disable
+ */
 #define USDHC_MIX_CTRL_BCEN(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_BCEN_SHIFT)) & USDHC_MIX_CTRL_BCEN_MASK)
 #define USDHC_MIX_CTRL_AC12EN_MASK               (0x4U)
 #define USDHC_MIX_CTRL_AC12EN_SHIFT              (2U)
+/*! AC12EN - Auto CMD12 Enable
+ *  0b1..Enable
+ *  0b0..Disable
+ */
 #define USDHC_MIX_CTRL_AC12EN(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC12EN_SHIFT)) & USDHC_MIX_CTRL_AC12EN_MASK)
 #define USDHC_MIX_CTRL_DDR_EN_MASK               (0x8U)
 #define USDHC_MIX_CTRL_DDR_EN_SHIFT              (3U)
 #define USDHC_MIX_CTRL_DDR_EN(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DDR_EN_SHIFT)) & USDHC_MIX_CTRL_DDR_EN_MASK)
 #define USDHC_MIX_CTRL_DTDSEL_MASK               (0x10U)
 #define USDHC_MIX_CTRL_DTDSEL_SHIFT              (4U)
+/*! DTDSEL - Data Transfer Direction Select
+ *  0b1..Read (Card to Host)
+ *  0b0..Write (Host to Card)
+ */
 #define USDHC_MIX_CTRL_DTDSEL(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DTDSEL_SHIFT)) & USDHC_MIX_CTRL_DTDSEL_MASK)
 #define USDHC_MIX_CTRL_MSBSEL_MASK               (0x20U)
 #define USDHC_MIX_CTRL_MSBSEL_SHIFT              (5U)
+/*! MSBSEL - Multi / Single Block Select
+ *  0b1..Multiple Blocks
+ *  0b0..Single Block
+ */
 #define USDHC_MIX_CTRL_MSBSEL(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_MSBSEL_SHIFT)) & USDHC_MIX_CTRL_MSBSEL_MASK)
 #define USDHC_MIX_CTRL_NIBBLE_POS_MASK           (0x40U)
 #define USDHC_MIX_CTRL_NIBBLE_POS_SHIFT          (6U)
@@ -27761,15 +41904,31 @@ typedef struct {
 #define USDHC_MIX_CTRL_AC23EN(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC23EN_SHIFT)) & USDHC_MIX_CTRL_AC23EN_MASK)
 #define USDHC_MIX_CTRL_EXE_TUNE_MASK             (0x400000U)
 #define USDHC_MIX_CTRL_EXE_TUNE_SHIFT            (22U)
+/*! EXE_TUNE - Execute Tuning: (Only used for SD3.0, SDR104 mode and EMMC HS200 mode)
+ *  0b1..Execute Tuning
+ *  0b0..Not Tuned or Tuning Completed
+ */
 #define USDHC_MIX_CTRL_EXE_TUNE(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_EXE_TUNE_SHIFT)) & USDHC_MIX_CTRL_EXE_TUNE_MASK)
 #define USDHC_MIX_CTRL_SMP_CLK_SEL_MASK          (0x800000U)
 #define USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT         (23U)
+/*! SMP_CLK_SEL - SMP_CLK_SEL
+ *  0b1..Tuned clock is used to sample data / cmd
+ *  0b0..Fixed clock is used to sample data / cmd
+ */
 #define USDHC_MIX_CTRL_SMP_CLK_SEL(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT)) & USDHC_MIX_CTRL_SMP_CLK_SEL_MASK)
 #define USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK         (0x1000000U)
 #define USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT        (24U)
+/*! AUTO_TUNE_EN - Auto Tuning Enable (Only used for SD3.0, SDR104 mode and and EMMC HS200 mode)
+ *  0b1..Enable auto tuning
+ *  0b0..Disable auto tuning
+ */
 #define USDHC_MIX_CTRL_AUTO_TUNE_EN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT)) & USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK)
 #define USDHC_MIX_CTRL_FBCLK_SEL_MASK            (0x2000000U)
 #define USDHC_MIX_CTRL_FBCLK_SEL_SHIFT           (25U)
+/*! FBCLK_SEL - Feedback Clock Source Selection (Only used for SD3.0, SDR104 mode and EMMC HS200 mode)
+ *  0b1..Feedback clock comes from the ipp_card_clk_out
+ *  0b0..Feedback clock comes from the loopback CLK
+ */
 #define USDHC_MIX_CTRL_FBCLK_SEL(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_FBCLK_SEL_SHIFT)) & USDHC_MIX_CTRL_FBCLK_SEL_MASK)
 /*! @} */
 
@@ -27835,9 +41994,17 @@ typedef struct {
 #define USDHC_ADMA_ERR_STATUS_ADMAES(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMAES_MASK)
 #define USDHC_ADMA_ERR_STATUS_ADMALME_MASK       (0x4U)
 #define USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT      (2U)
+/*! ADMALME - ADMA Length Mismatch Error
+ *  0b1..Error
+ *  0b0..No Error
+ */
 #define USDHC_ADMA_ERR_STATUS_ADMALME(x)         (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMALME_MASK)
 #define USDHC_ADMA_ERR_STATUS_ADMADCE_MASK       (0x8U)
 #define USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT      (3U)
+/*! ADMADCE - ADMA Descriptor Error
+ *  0b1..Error
+ *  0b0..No Error
+ */
 #define USDHC_ADMA_ERR_STATUS_ADMADCE(x)         (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMADCE_MASK)
 /*! @} */
 
@@ -27930,21 +42097,45 @@ typedef struct {
 /*! @{ */
 #define USDHC_VEND_SPEC_VSELECT_MASK             (0x2U)
 #define USDHC_VEND_SPEC_VSELECT_SHIFT            (1U)
+/*! VSELECT - Voltage Selection
+ *  0b1..Change the voltage to low voltage range, around 1.8 V
+ *  0b0..Change the voltage to high voltage range, around 3.0 V
+ */
 #define USDHC_VEND_SPEC_VSELECT(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_VSELECT_SHIFT)) & USDHC_VEND_SPEC_VSELECT_MASK)
 #define USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK     (0x4U)
 #define USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT    (2U)
+/*! CONFLICT_CHK_EN - Conflict check enable.
+ *  0b0..Conflict check disable
+ *  0b1..Conflict check enable
+ */
 #define USDHC_VEND_SPEC_CONFLICT_CHK_EN(x)       (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT)) & USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK)
 #define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK  (0x8U)
 #define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT (3U)
+/*! AC12_WR_CHKBUSY_EN - AC12_WR_CHKBUSY_EN
+ *  0b0..Do not check busy after auto CMD12 for write data packet
+ *  0b1..Check busy after auto CMD12 for write data packet
+ */
 #define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN(x)    (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT)) & USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK)
 #define USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK        (0x100U)
 #define USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT       (8U)
+/*! FRC_SDCLK_ON - FRC_SDCLK_ON
+ *  0b0..CLK active or inactive is fully controlled by the hardware.
+ *  0b1..Force CLK active.
+ */
 #define USDHC_VEND_SPEC_FRC_SDCLK_ON(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT)) & USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK)
 #define USDHC_VEND_SPEC_CRC_CHK_DIS_MASK         (0x8000U)
 #define USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT        (15U)
+/*! CRC_CHK_DIS - CRC Check Disable
+ *  0b0..Check CRC16 for every read data packet and check CRC bits for every write data packet
+ *  0b1..Ignore CRC16 check for every read data packet and ignore CRC bits check for every write data packet
+ */
 #define USDHC_VEND_SPEC_CRC_CHK_DIS(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT)) & USDHC_VEND_SPEC_CRC_CHK_DIS_MASK)
 #define USDHC_VEND_SPEC_CMD_BYTE_EN_MASK         (0x80000000U)
 #define USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT        (31U)
+/*! CMD_BYTE_EN - CMD_BYTE_EN
+ *  0b0..Disable
+ *  0b1..Enable
+ */
 #define USDHC_VEND_SPEC_CMD_BYTE_EN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT)) & USDHC_VEND_SPEC_CMD_BYTE_EN_MASK)
 /*! @} */
 
@@ -27952,21 +42143,49 @@ typedef struct {
 /*! @{ */
 #define USDHC_MMC_BOOT_DTOCV_ACK_MASK            (0xFU)
 #define USDHC_MMC_BOOT_DTOCV_ACK_SHIFT           (0U)
+/*! DTOCV_ACK - DTOCV_ACK
+ *  0b0000..SDCLK x 2^14
+ *  0b0001..SDCLK x 2^15
+ *  0b0010..SDCLK x 2^16
+ *  0b0011..SDCLK x 2^17
+ *  0b0100..SDCLK x 2^18
+ *  0b0101..SDCLK x 2^19
+ *  0b0110..SDCLK x 2^20
+ *  0b0111..SDCLK x 2^21
+ *  0b1110..SDCLK x 2^28
+ *  0b1111..SDCLK x 2^29
+ */
 #define USDHC_MMC_BOOT_DTOCV_ACK(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DTOCV_ACK_SHIFT)) & USDHC_MMC_BOOT_DTOCV_ACK_MASK)
 #define USDHC_MMC_BOOT_BOOT_ACK_MASK             (0x10U)
 #define USDHC_MMC_BOOT_BOOT_ACK_SHIFT            (4U)
+/*! BOOT_ACK - BOOT_ACK
+ *  0b0..No ack
+ *  0b1..Ack
+ */
 #define USDHC_MMC_BOOT_BOOT_ACK(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_ACK_SHIFT)) & USDHC_MMC_BOOT_BOOT_ACK_MASK)
 #define USDHC_MMC_BOOT_BOOT_MODE_MASK            (0x20U)
 #define USDHC_MMC_BOOT_BOOT_MODE_SHIFT           (5U)
+/*! BOOT_MODE - BOOT_MODE
+ *  0b0..Normal boot
+ *  0b1..Alternative boot
+ */
 #define USDHC_MMC_BOOT_BOOT_MODE(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_MODE_SHIFT)) & USDHC_MMC_BOOT_BOOT_MODE_MASK)
 #define USDHC_MMC_BOOT_BOOT_EN_MASK              (0x40U)
 #define USDHC_MMC_BOOT_BOOT_EN_SHIFT             (6U)
+/*! BOOT_EN - BOOT_EN
+ *  0b0..Fast boot disable
+ *  0b1..Fast boot enable
+ */
 #define USDHC_MMC_BOOT_BOOT_EN(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_EN_SHIFT)) & USDHC_MMC_BOOT_BOOT_EN_MASK)
 #define USDHC_MMC_BOOT_AUTO_SABG_EN_MASK         (0x80U)
 #define USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT        (7U)
 #define USDHC_MMC_BOOT_AUTO_SABG_EN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT)) & USDHC_MMC_BOOT_AUTO_SABG_EN_MASK)
 #define USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK     (0x100U)
 #define USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT    (8U)
+/*! DISABLE_TIME_OUT - Disable Time Out
+ *  0b0..Enable time out
+ *  0b1..Disable time out
+ */
 #define USDHC_MMC_BOOT_DISABLE_TIME_OUT(x)       (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT)) & USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK)
 #define USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK         (0xFFFF0000U)
 #define USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT        (16U)
@@ -27977,6 +42196,10 @@ typedef struct {
 /*! @{ */
 #define USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK   (0x8U)
 #define USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT  (3U)
+/*! CARD_INT_D3_TEST - Card Interrupt Detection Test
+ *  0b0..Check the card interrupt only when DATA3 is high.
+ *  0b1..Check the card interrupt by ignoring the status of DATA3.
+ */
 #define USDHC_VEND_SPEC2_CARD_INT_D3_TEST(x)     (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT)) & USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK)
 #define USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK     (0x10U)
 #define USDHC_VEND_SPEC2_TUNING_8bit_EN_SHIFT    (4U)
@@ -27986,9 +42209,17 @@ typedef struct {
 #define USDHC_VEND_SPEC2_TUNING_1bit_EN(x)       (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_1bit_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK)
 #define USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK      (0x40U)
 #define USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT     (6U)
+/*! TUNING_CMD_EN - TUNING_CMD_EN
+ *  0b0..Auto tuning circuit does not check the CMD line.
+ *  0b1..Auto tuning circuit checks the CMD line.
+ */
 #define USDHC_VEND_SPEC2_TUNING_CMD_EN(x)        (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK)
 #define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK    (0x1000U)
 #define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT   (12U)
+/*! ACMD23_ARGU2_EN - Argument2 register enable for ACMD23
+ *  0b1..Argument2 register enable for ACMD23 sharing with SDMA system address register. Default is enable.
+ *  0b0..Disable
+ */
 #define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN(x)      (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT)) & USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK)
 #define USDHC_VEND_SPEC2_PART_DLL_DEBUG_MASK     (0x2000U)
 #define USDHC_VEND_SPEC2_PART_DLL_DEBUG_SHIFT    (13U)
@@ -28075,30 +42306,69 @@ typedef struct {
 /*! @{ */
 #define WDOG_WCR_WDZST_MASK                      (0x1U)
 #define WDOG_WCR_WDZST_SHIFT                     (0U)
+/*! WDZST - WDZST
+ *  0b0..Continue timer operation (Default).
+ *  0b1..Suspend the watchdog timer.
+ */
 #define WDOG_WCR_WDZST(x)                        (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDZST_SHIFT)) & WDOG_WCR_WDZST_MASK)
 #define WDOG_WCR_WDBG_MASK                       (0x2U)
 #define WDOG_WCR_WDBG_SHIFT                      (1U)
+/*! WDBG - WDBG
+ *  0b0..Continue WDOG timer operation (Default).
+ *  0b1..Suspend the watchdog timer.
+ */
 #define WDOG_WCR_WDBG(x)                         (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDBG_SHIFT)) & WDOG_WCR_WDBG_MASK)
 #define WDOG_WCR_WDE_MASK                        (0x4U)
 #define WDOG_WCR_WDE_SHIFT                       (2U)
+/*! WDE - WDE
+ *  0b0..Disable the Watchdog (Default).
+ *  0b1..Enable the Watchdog.
+ */
 #define WDOG_WCR_WDE(x)                          (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDE_SHIFT)) & WDOG_WCR_WDE_MASK)
 #define WDOG_WCR_WDT_MASK                        (0x8U)
 #define WDOG_WCR_WDT_SHIFT                       (3U)
+/*! WDT - WDT
+ *  0b0..No effect on WDOG_B (Default).
+ *  0b1..Assert WDOG_B upon a Watchdog Time-out event.
+ */
 #define WDOG_WCR_WDT(x)                          (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDT_SHIFT)) & WDOG_WCR_WDT_MASK)
 #define WDOG_WCR_SRS_MASK                        (0x10U)
 #define WDOG_WCR_SRS_SHIFT                       (4U)
+/*! SRS - SRS
+ *  0b0..Assert system reset signal.
+ *  0b1..No effect on the system (Default).
+ */
 #define WDOG_WCR_SRS(x)                          (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_SRS_SHIFT)) & WDOG_WCR_SRS_MASK)
 #define WDOG_WCR_WDA_MASK                        (0x20U)
 #define WDOG_WCR_WDA_SHIFT                       (5U)
+/*! WDA - WDA
+ *  0b0..Assert WDOG_B output.
+ *  0b1..No effect on system (Default).
+ */
 #define WDOG_WCR_WDA(x)                          (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDA_SHIFT)) & WDOG_WCR_WDA_MASK)
 #define WDOG_WCR_SRE_MASK                        (0x40U)
 #define WDOG_WCR_SRE_SHIFT                       (6U)
+/*! SRE - software reset extension, an option way to generate software reset
+ *  0b0..using original way to generate software reset (default)
+ *  0b1..using new way to generate software reset.
+ */
 #define WDOG_WCR_SRE(x)                          (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_SRE_SHIFT)) & WDOG_WCR_SRE_MASK)
 #define WDOG_WCR_WDW_MASK                        (0x80U)
 #define WDOG_WCR_WDW_SHIFT                       (7U)
+/*! WDW - WDW
+ *  0b0..Continue WDOG timer operation (Default).
+ *  0b1..Suspend WDOG timer operation.
+ */
 #define WDOG_WCR_WDW(x)                          (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDW_SHIFT)) & WDOG_WCR_WDW_MASK)
 #define WDOG_WCR_WT_MASK                         (0xFF00U)
 #define WDOG_WCR_WT_SHIFT                        (8U)
+/*! WT - WT
+ *  0b00000000..- 0.5 Seconds (Default).
+ *  0b00000001..- 1.0 Seconds.
+ *  0b00000010..- 1.5 Seconds.
+ *  0b00000011..- 2.0 Seconds.
+ *  0b11111111..- 128 Seconds.
+ */
 #define WDOG_WCR_WT(x)                           (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WT_SHIFT)) & WDOG_WCR_WT_MASK)
 /*! @} */
 
@@ -28106,6 +42376,10 @@ typedef struct {
 /*! @{ */
 #define WDOG_WSR_WSR_MASK                        (0xFFFFU)
 #define WDOG_WSR_WSR_SHIFT                       (0U)
+/*! WSR - WSR
+ *  0b0101010101010101..Write to the Watchdog Service Register (WDOG_WSR).
+ *  0b1010101010101010..Write to the Watchdog Service Register (WDOG_WSR).
+ */
 #define WDOG_WSR_WSR(x)                          (((uint16_t)(((uint16_t)(x)) << WDOG_WSR_WSR_SHIFT)) & WDOG_WSR_WSR_MASK)
 /*! @} */
 
@@ -28113,12 +42387,24 @@ typedef struct {
 /*! @{ */
 #define WDOG_WRSR_SFTW_MASK                      (0x1U)
 #define WDOG_WRSR_SFTW_SHIFT                     (0U)
+/*! SFTW - SFTW
+ *  0b0..Reset is not the result of a software reset.
+ *  0b1..Reset is the result of a software reset.
+ */
 #define WDOG_WRSR_SFTW(x)                        (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_SFTW_SHIFT)) & WDOG_WRSR_SFTW_MASK)
 #define WDOG_WRSR_TOUT_MASK                      (0x2U)
 #define WDOG_WRSR_TOUT_SHIFT                     (1U)
+/*! TOUT - TOUT
+ *  0b0..Reset is not the result of a WDOG timeout.
+ *  0b1..Reset is the result of a WDOG timeout.
+ */
 #define WDOG_WRSR_TOUT(x)                        (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_TOUT_SHIFT)) & WDOG_WRSR_TOUT_MASK)
 #define WDOG_WRSR_POR_MASK                       (0x10U)
 #define WDOG_WRSR_POR_SHIFT                      (4U)
+/*! POR - POR
+ *  0b0..Reset is not the result of a power on reset.
+ *  0b1..Reset is the result of a power on reset.
+ */
 #define WDOG_WRSR_POR(x)                         (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_POR_SHIFT)) & WDOG_WRSR_POR_MASK)
 /*! @} */
 
@@ -28126,12 +42412,26 @@ typedef struct {
 /*! @{ */
 #define WDOG_WICR_WICT_MASK                      (0xFFU)
 #define WDOG_WICR_WICT_SHIFT                     (0U)
+/*! WICT - WICT
+ *  0b00000000..WICT[7:0] = Time duration between interrupt and time-out is 0 seconds.
+ *  0b00000001..WICT[7:0] = Time duration between interrupt and time-out is 0.5 seconds.
+ *  0b00000100..WICT[7:0] = Time duration between interrupt and time-out is 2 seconds (Default).
+ *  0b11111111..WICT[7:0] = Time duration between interrupt and time-out is 127.5 seconds.
+ */
 #define WDOG_WICR_WICT(x)                        (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WICT_SHIFT)) & WDOG_WICR_WICT_MASK)
 #define WDOG_WICR_WTIS_MASK                      (0x4000U)
 #define WDOG_WICR_WTIS_SHIFT                     (14U)
+/*! WTIS - WTIS
+ *  0b0..No interrupt has occurred (Default).
+ *  0b1..Interrupt has occurred
+ */
 #define WDOG_WICR_WTIS(x)                        (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WTIS_SHIFT)) & WDOG_WICR_WTIS_MASK)
 #define WDOG_WICR_WIE_MASK                       (0x8000U)
 #define WDOG_WICR_WIE_SHIFT                      (15U)
+/*! WIE - WIE
+ *  0b0..Disable Interrupt (Default).
+ *  0b1..Enable Interrupt.
+ */
 #define WDOG_WICR_WIE(x)                         (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WIE_SHIFT)) & WDOG_WICR_WIE_MASK)
 /*! @} */
 
@@ -28139,6 +42439,10 @@ typedef struct {
 /*! @{ */
 #define WDOG_WMCR_PDE_MASK                       (0x1U)
 #define WDOG_WMCR_PDE_SHIFT                      (0U)
+/*! PDE - PDE
+ *  0b0..Power Down Counter of WDOG is disabled.
+ *  0b1..Power Down Counter of WDOG is enabled (Default).
+ */
 #define WDOG_WMCR_PDE(x)                         (((uint16_t)(((uint16_t)(x)) << WDOG_WMCR_PDE_SHIFT)) & WDOG_WMCR_PDE_MASK)
 /*! @} */
 
@@ -28923,27 +43227,63 @@ typedef struct {
 /*! @{ */
 #define XBARA_CTRL0_DEN0_MASK                    (0x1U)
 #define XBARA_CTRL0_DEN0_SHIFT                   (0U)
+/*! DEN0 - DMA Enable for XBAR_OUT0
+ *  0b0..DMA disabled
+ *  0b1..DMA enabled
+ */
 #define XBARA_CTRL0_DEN0(x)                      (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_DEN0_SHIFT)) & XBARA_CTRL0_DEN0_MASK)
 #define XBARA_CTRL0_IEN0_MASK                    (0x2U)
 #define XBARA_CTRL0_IEN0_SHIFT                   (1U)
+/*! IEN0 - Interrupt Enable for XBAR_OUT0
+ *  0b0..Interrupt disabled
+ *  0b1..Interrupt enabled
+ */
 #define XBARA_CTRL0_IEN0(x)                      (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_IEN0_SHIFT)) & XBARA_CTRL0_IEN0_MASK)
 #define XBARA_CTRL0_EDGE0_MASK                   (0xCU)
 #define XBARA_CTRL0_EDGE0_SHIFT                  (2U)
+/*! EDGE0 - Active edge for edge detection on XBAR_OUT0
+ *  0b00..STS0 never asserts
+ *  0b01..STS0 asserts on rising edges of XBAR_OUT0
+ *  0b10..STS0 asserts on falling edges of XBAR_OUT0
+ *  0b11..STS0 asserts on rising and falling edges of XBAR_OUT0
+ */
 #define XBARA_CTRL0_EDGE0(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_EDGE0_SHIFT)) & XBARA_CTRL0_EDGE0_MASK)
 #define XBARA_CTRL0_STS0_MASK                    (0x10U)
 #define XBARA_CTRL0_STS0_SHIFT                   (4U)
+/*! STS0 - Edge detection status for XBAR_OUT0
+ *  0b0..Active edge not yet detected on XBAR_OUT0
+ *  0b1..Active edge detected on XBAR_OUT0
+ */
 #define XBARA_CTRL0_STS0(x)                      (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_STS0_SHIFT)) & XBARA_CTRL0_STS0_MASK)
 #define XBARA_CTRL0_DEN1_MASK                    (0x100U)
 #define XBARA_CTRL0_DEN1_SHIFT                   (8U)
+/*! DEN1 - DMA Enable for XBAR_OUT1
+ *  0b0..DMA disabled
+ *  0b1..DMA enabled
+ */
 #define XBARA_CTRL0_DEN1(x)                      (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_DEN1_SHIFT)) & XBARA_CTRL0_DEN1_MASK)
 #define XBARA_CTRL0_IEN1_MASK                    (0x200U)
 #define XBARA_CTRL0_IEN1_SHIFT                   (9U)
+/*! IEN1 - Interrupt Enable for XBAR_OUT1
+ *  0b0..Interrupt disabled
+ *  0b1..Interrupt enabled
+ */
 #define XBARA_CTRL0_IEN1(x)                      (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_IEN1_SHIFT)) & XBARA_CTRL0_IEN1_MASK)
 #define XBARA_CTRL0_EDGE1_MASK                   (0xC00U)
 #define XBARA_CTRL0_EDGE1_SHIFT                  (10U)
+/*! EDGE1 - Active edge for edge detection on XBAR_OUT1
+ *  0b00..STS1 never asserts
+ *  0b01..STS1 asserts on rising edges of XBAR_OUT1
+ *  0b10..STS1 asserts on falling edges of XBAR_OUT1
+ *  0b11..STS1 asserts on rising and falling edges of XBAR_OUT1
+ */
 #define XBARA_CTRL0_EDGE1(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_EDGE1_SHIFT)) & XBARA_CTRL0_EDGE1_MASK)
 #define XBARA_CTRL0_STS1_MASK                    (0x1000U)
 #define XBARA_CTRL0_STS1_SHIFT                   (12U)
+/*! STS1 - Edge detection status for XBAR_OUT1
+ *  0b0..Active edge not yet detected on XBAR_OUT1
+ *  0b1..Active edge detected on XBAR_OUT1
+ */
 #define XBARA_CTRL0_STS1(x)                      (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_STS1_SHIFT)) & XBARA_CTRL0_STS1_MASK)
 /*! @} */
 
@@ -28951,27 +43291,63 @@ typedef struct {
 /*! @{ */
 #define XBARA_CTRL1_DEN2_MASK                    (0x1U)
 #define XBARA_CTRL1_DEN2_SHIFT                   (0U)
+/*! DEN2 - DMA Enable for XBAR_OUT2
+ *  0b0..DMA disabled
+ *  0b1..DMA enabled
+ */
 #define XBARA_CTRL1_DEN2(x)                      (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_DEN2_SHIFT)) & XBARA_CTRL1_DEN2_MASK)
 #define XBARA_CTRL1_IEN2_MASK                    (0x2U)
 #define XBARA_CTRL1_IEN2_SHIFT                   (1U)
+/*! IEN2 - Interrupt Enable for XBAR_OUT2
+ *  0b0..Interrupt disabled
+ *  0b1..Interrupt enabled
+ */
 #define XBARA_CTRL1_IEN2(x)                      (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_IEN2_SHIFT)) & XBARA_CTRL1_IEN2_MASK)
 #define XBARA_CTRL1_EDGE2_MASK                   (0xCU)
 #define XBARA_CTRL1_EDGE2_SHIFT                  (2U)
+/*! EDGE2 - Active edge for edge detection on XBAR_OUT2
+ *  0b00..STS2 never asserts
+ *  0b01..STS2 asserts on rising edges of XBAR_OUT2
+ *  0b10..STS2 asserts on falling edges of XBAR_OUT2
+ *  0b11..STS2 asserts on rising and falling edges of XBAR_OUT2
+ */
 #define XBARA_CTRL1_EDGE2(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_EDGE2_SHIFT)) & XBARA_CTRL1_EDGE2_MASK)
 #define XBARA_CTRL1_STS2_MASK                    (0x10U)
 #define XBARA_CTRL1_STS2_SHIFT                   (4U)
+/*! STS2 - Edge detection status for XBAR_OUT2
+ *  0b0..Active edge not yet detected on XBAR_OUT2
+ *  0b1..Active edge detected on XBAR_OUT2
+ */
 #define XBARA_CTRL1_STS2(x)                      (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_STS2_SHIFT)) & XBARA_CTRL1_STS2_MASK)
 #define XBARA_CTRL1_DEN3_MASK                    (0x100U)
 #define XBARA_CTRL1_DEN3_SHIFT                   (8U)
+/*! DEN3 - DMA Enable for XBAR_OUT3
+ *  0b0..DMA disabled
+ *  0b1..DMA enabled
+ */
 #define XBARA_CTRL1_DEN3(x)                      (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_DEN3_SHIFT)) & XBARA_CTRL1_DEN3_MASK)
 #define XBARA_CTRL1_IEN3_MASK                    (0x200U)
 #define XBARA_CTRL1_IEN3_SHIFT                   (9U)
+/*! IEN3 - Interrupt Enable for XBAR_OUT3
+ *  0b0..Interrupt disabled
+ *  0b1..Interrupt enabled
+ */
 #define XBARA_CTRL1_IEN3(x)                      (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_IEN3_SHIFT)) & XBARA_CTRL1_IEN3_MASK)
 #define XBARA_CTRL1_EDGE3_MASK                   (0xC00U)
 #define XBARA_CTRL1_EDGE3_SHIFT                  (10U)
+/*! EDGE3 - Active edge for edge detection on XBAR_OUT3
+ *  0b00..STS3 never asserts
+ *  0b01..STS3 asserts on rising edges of XBAR_OUT3
+ *  0b10..STS3 asserts on falling edges of XBAR_OUT3
+ *  0b11..STS3 asserts on rising and falling edges of XBAR_OUT3
+ */
 #define XBARA_CTRL1_EDGE3(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_EDGE3_SHIFT)) & XBARA_CTRL1_EDGE3_MASK)
 #define XBARA_CTRL1_STS3_MASK                    (0x1000U)
 #define XBARA_CTRL1_STS3_SHIFT                   (12U)
+/*! STS3 - Edge detection status for XBAR_OUT3
+ *  0b0..Active edge not yet detected on XBAR_OUT3
+ *  0b1..Active edge detected on XBAR_OUT3
+ */
 #define XBARA_CTRL1_STS3(x)                      (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_STS3_SHIFT)) & XBARA_CTRL1_STS3_MASK)
 /*! @} */
 
@@ -29183,21 +43559,51 @@ typedef struct {
 #define XTALOSC24M_MISC0_REFTOP_PWD(x)           (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_REFTOP_PWD_SHIFT)) & XTALOSC24M_MISC0_REFTOP_PWD_MASK)
 #define XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_MASK (0x8U)
 #define XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_SHIFT (3U)
+/*! REFTOP_SELFBIASOFF
+ *  0b0..Uses coarse bias currents for startup
+ *  0b1..Uses bandgap-based bias currents for best performance.
+ */
 #define XTALOSC24M_MISC0_REFTOP_SELFBIASOFF(x)   (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_SHIFT)) & XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_MASK)
 #define XTALOSC24M_MISC0_REFTOP_VBGADJ_MASK      (0x70U)
 #define XTALOSC24M_MISC0_REFTOP_VBGADJ_SHIFT     (4U)
+/*! REFTOP_VBGADJ
+ *  0b000..Nominal VBG
+ *  0b001..VBG+0.78%
+ *  0b010..VBG+1.56%
+ *  0b011..VBG+2.34%
+ *  0b100..VBG-0.78%
+ *  0b101..VBG-1.56%
+ *  0b110..VBG-2.34%
+ *  0b111..VBG-3.12%
+ */
 #define XTALOSC24M_MISC0_REFTOP_VBGADJ(x)        (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_REFTOP_VBGADJ_SHIFT)) & XTALOSC24M_MISC0_REFTOP_VBGADJ_MASK)
 #define XTALOSC24M_MISC0_REFTOP_VBGUP_MASK       (0x80U)
 #define XTALOSC24M_MISC0_REFTOP_VBGUP_SHIFT      (7U)
 #define XTALOSC24M_MISC0_REFTOP_VBGUP(x)         (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_REFTOP_VBGUP_SHIFT)) & XTALOSC24M_MISC0_REFTOP_VBGUP_MASK)
 #define XTALOSC24M_MISC0_STOP_MODE_CONFIG_MASK   (0xC00U)
 #define XTALOSC24M_MISC0_STOP_MODE_CONFIG_SHIFT  (10U)
+/*! STOP_MODE_CONFIG
+ *  0b00..All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off;
+ *  0b01..Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off;
+ *  0b10..XtalOsc=off, RCOsc=on, Old BG=on, New BG=off.
+ *  0b11..XtalOsc=off, RCOsc=on, Old BG=off, New BG=on.
+ */
 #define XTALOSC24M_MISC0_STOP_MODE_CONFIG(x)     (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_STOP_MODE_CONFIG_SHIFT)) & XTALOSC24M_MISC0_STOP_MODE_CONFIG_MASK)
 #define XTALOSC24M_MISC0_DISCON_HIGH_SNVS_MASK   (0x1000U)
 #define XTALOSC24M_MISC0_DISCON_HIGH_SNVS_SHIFT  (12U)
+/*! DISCON_HIGH_SNVS
+ *  0b0..Turn on the switch
+ *  0b1..Turn off the switch
+ */
 #define XTALOSC24M_MISC0_DISCON_HIGH_SNVS(x)     (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_DISCON_HIGH_SNVS_SHIFT)) & XTALOSC24M_MISC0_DISCON_HIGH_SNVS_MASK)
 #define XTALOSC24M_MISC0_OSC_I_MASK              (0x6000U)
 #define XTALOSC24M_MISC0_OSC_I_SHIFT             (13U)
+/*! OSC_I
+ *  0b00..Nominal
+ *  0b01..Decrease current by 12.5%
+ *  0b10..Decrease current by 25.0%
+ *  0b11..Decrease current by 37.5%
+ */
 #define XTALOSC24M_MISC0_OSC_I(x)                (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_OSC_I_SHIFT)) & XTALOSC24M_MISC0_OSC_I_MASK)
 #define XTALOSC24M_MISC0_OSC_XTALOK_MASK         (0x8000U)
 #define XTALOSC24M_MISC0_OSC_XTALOK_SHIFT        (15U)
@@ -29207,18 +43613,40 @@ typedef struct {
 #define XTALOSC24M_MISC0_OSC_XTALOK_EN(x)        (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_OSC_XTALOK_EN_SHIFT)) & XTALOSC24M_MISC0_OSC_XTALOK_EN_MASK)
 #define XTALOSC24M_MISC0_CLKGATE_CTRL_MASK       (0x2000000U)
 #define XTALOSC24M_MISC0_CLKGATE_CTRL_SHIFT      (25U)
+/*! CLKGATE_CTRL
+ *  0b0..Allow the logic to automatically gate the clock when the XTAL is powered down.
+ *  0b1..Prevent the logic from ever gating off the clock.
+ */
 #define XTALOSC24M_MISC0_CLKGATE_CTRL(x)         (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLKGATE_CTRL_SHIFT)) & XTALOSC24M_MISC0_CLKGATE_CTRL_MASK)
 #define XTALOSC24M_MISC0_CLKGATE_DELAY_MASK      (0x1C000000U)
 #define XTALOSC24M_MISC0_CLKGATE_DELAY_SHIFT     (26U)
+/*! CLKGATE_DELAY
+ *  0b000..0.5ms
+ *  0b001..1.0ms
+ *  0b010..2.0ms
+ *  0b011..3.0ms
+ *  0b100..4.0ms
+ *  0b101..5.0ms
+ *  0b110..6.0ms
+ *  0b111..7.0ms
+ */
 #define XTALOSC24M_MISC0_CLKGATE_DELAY(x)        (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLKGATE_DELAY_SHIFT)) & XTALOSC24M_MISC0_CLKGATE_DELAY_MASK)
 #define XTALOSC24M_MISC0_RTC_XTAL_SOURCE_MASK    (0x20000000U)
 #define XTALOSC24M_MISC0_RTC_XTAL_SOURCE_SHIFT   (29U)
+/*! RTC_XTAL_SOURCE
+ *  0b0..Internal ring oscillator
+ *  0b1..RTC_XTAL
+ */
 #define XTALOSC24M_MISC0_RTC_XTAL_SOURCE(x)      (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_RTC_XTAL_SOURCE_SHIFT)) & XTALOSC24M_MISC0_RTC_XTAL_SOURCE_MASK)
 #define XTALOSC24M_MISC0_XTAL_24M_PWD_MASK       (0x40000000U)
 #define XTALOSC24M_MISC0_XTAL_24M_PWD_SHIFT      (30U)
 #define XTALOSC24M_MISC0_XTAL_24M_PWD(x)         (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_XTAL_24M_PWD_SHIFT)) & XTALOSC24M_MISC0_XTAL_24M_PWD_MASK)
 #define XTALOSC24M_MISC0_VID_PLL_PREDIV_MASK     (0x80000000U)
 #define XTALOSC24M_MISC0_VID_PLL_PREDIV_SHIFT    (31U)
+/*! VID_PLL_PREDIV
+ *  0b0..Divide by 1
+ *  0b1..Divide by 2
+ */
 #define XTALOSC24M_MISC0_VID_PLL_PREDIV(x)       (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_VID_PLL_PREDIV_SHIFT)) & XTALOSC24M_MISC0_VID_PLL_PREDIV_MASK)
 /*! @} */
 
@@ -29229,21 +43657,51 @@ typedef struct {
 #define XTALOSC24M_MISC0_SET_REFTOP_PWD(x)       (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_REFTOP_PWD_SHIFT)) & XTALOSC24M_MISC0_SET_REFTOP_PWD_MASK)
 #define XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF_MASK (0x8U)
 #define XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT (3U)
+/*! REFTOP_SELFBIASOFF
+ *  0b0..Uses coarse bias currents for startup
+ *  0b1..Uses bandgap-based bias currents for best performance.
+ */
 #define XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT)) & XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF_MASK)
 #define XTALOSC24M_MISC0_SET_REFTOP_VBGADJ_MASK  (0x70U)
 #define XTALOSC24M_MISC0_SET_REFTOP_VBGADJ_SHIFT (4U)
+/*! REFTOP_VBGADJ
+ *  0b000..Nominal VBG
+ *  0b001..VBG+0.78%
+ *  0b010..VBG+1.56%
+ *  0b011..VBG+2.34%
+ *  0b100..VBG-0.78%
+ *  0b101..VBG-1.56%
+ *  0b110..VBG-2.34%
+ *  0b111..VBG-3.12%
+ */
 #define XTALOSC24M_MISC0_SET_REFTOP_VBGADJ(x)    (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_REFTOP_VBGADJ_SHIFT)) & XTALOSC24M_MISC0_SET_REFTOP_VBGADJ_MASK)
 #define XTALOSC24M_MISC0_SET_REFTOP_VBGUP_MASK   (0x80U)
 #define XTALOSC24M_MISC0_SET_REFTOP_VBGUP_SHIFT  (7U)
 #define XTALOSC24M_MISC0_SET_REFTOP_VBGUP(x)     (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_REFTOP_VBGUP_SHIFT)) & XTALOSC24M_MISC0_SET_REFTOP_VBGUP_MASK)
 #define XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG_MASK (0xC00U)
 #define XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG_SHIFT (10U)
+/*! STOP_MODE_CONFIG
+ *  0b00..All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off;
+ *  0b01..Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off;
+ *  0b10..XtalOsc=off, RCOsc=on, Old BG=on, New BG=off.
+ *  0b11..XtalOsc=off, RCOsc=on, Old BG=off, New BG=on.
+ */
 #define XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG_SHIFT)) & XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG_MASK)
 #define XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS_MASK (0x1000U)
 #define XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS_SHIFT (12U)
+/*! DISCON_HIGH_SNVS
+ *  0b0..Turn on the switch
+ *  0b1..Turn off the switch
+ */
 #define XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS_SHIFT)) & XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS_MASK)
 #define XTALOSC24M_MISC0_SET_OSC_I_MASK          (0x6000U)
 #define XTALOSC24M_MISC0_SET_OSC_I_SHIFT         (13U)
+/*! OSC_I
+ *  0b00..Nominal
+ *  0b01..Decrease current by 12.5%
+ *  0b10..Decrease current by 25.0%
+ *  0b11..Decrease current by 37.5%
+ */
 #define XTALOSC24M_MISC0_SET_OSC_I(x)            (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_OSC_I_SHIFT)) & XTALOSC24M_MISC0_SET_OSC_I_MASK)
 #define XTALOSC24M_MISC0_SET_OSC_XTALOK_MASK     (0x8000U)
 #define XTALOSC24M_MISC0_SET_OSC_XTALOK_SHIFT    (15U)
@@ -29253,18 +43711,40 @@ typedef struct {
 #define XTALOSC24M_MISC0_SET_OSC_XTALOK_EN(x)    (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_OSC_XTALOK_EN_SHIFT)) & XTALOSC24M_MISC0_SET_OSC_XTALOK_EN_MASK)
 #define XTALOSC24M_MISC0_SET_CLKGATE_CTRL_MASK   (0x2000000U)
 #define XTALOSC24M_MISC0_SET_CLKGATE_CTRL_SHIFT  (25U)
+/*! CLKGATE_CTRL
+ *  0b0..Allow the logic to automatically gate the clock when the XTAL is powered down.
+ *  0b1..Prevent the logic from ever gating off the clock.
+ */
 #define XTALOSC24M_MISC0_SET_CLKGATE_CTRL(x)     (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_CLKGATE_CTRL_SHIFT)) & XTALOSC24M_MISC0_SET_CLKGATE_CTRL_MASK)
 #define XTALOSC24M_MISC0_SET_CLKGATE_DELAY_MASK  (0x1C000000U)
 #define XTALOSC24M_MISC0_SET_CLKGATE_DELAY_SHIFT (26U)
+/*! CLKGATE_DELAY
+ *  0b000..0.5ms
+ *  0b001..1.0ms
+ *  0b010..2.0ms
+ *  0b011..3.0ms
+ *  0b100..4.0ms
+ *  0b101..5.0ms
+ *  0b110..6.0ms
+ *  0b111..7.0ms
+ */
 #define XTALOSC24M_MISC0_SET_CLKGATE_DELAY(x)    (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_CLKGATE_DELAY_SHIFT)) & XTALOSC24M_MISC0_SET_CLKGATE_DELAY_MASK)
 #define XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE_MASK (0x20000000U)
 #define XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE_SHIFT (29U)
+/*! RTC_XTAL_SOURCE
+ *  0b0..Internal ring oscillator
+ *  0b1..RTC_XTAL
+ */
 #define XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE(x)  (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE_SHIFT)) & XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE_MASK)
 #define XTALOSC24M_MISC0_SET_XTAL_24M_PWD_MASK   (0x40000000U)
 #define XTALOSC24M_MISC0_SET_XTAL_24M_PWD_SHIFT  (30U)
 #define XTALOSC24M_MISC0_SET_XTAL_24M_PWD(x)     (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_XTAL_24M_PWD_SHIFT)) & XTALOSC24M_MISC0_SET_XTAL_24M_PWD_MASK)
 #define XTALOSC24M_MISC0_SET_VID_PLL_PREDIV_MASK (0x80000000U)
 #define XTALOSC24M_MISC0_SET_VID_PLL_PREDIV_SHIFT (31U)
+/*! VID_PLL_PREDIV
+ *  0b0..Divide by 1
+ *  0b1..Divide by 2
+ */
 #define XTALOSC24M_MISC0_SET_VID_PLL_PREDIV(x)   (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_VID_PLL_PREDIV_SHIFT)) & XTALOSC24M_MISC0_SET_VID_PLL_PREDIV_MASK)
 /*! @} */
 
@@ -29275,21 +43755,51 @@ typedef struct {
 #define XTALOSC24M_MISC0_CLR_REFTOP_PWD(x)       (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_REFTOP_PWD_SHIFT)) & XTALOSC24M_MISC0_CLR_REFTOP_PWD_MASK)
 #define XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF_MASK (0x8U)
 #define XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT (3U)
+/*! REFTOP_SELFBIASOFF
+ *  0b0..Uses coarse bias currents for startup
+ *  0b1..Uses bandgap-based bias currents for best performance.
+ */
 #define XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT)) & XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF_MASK)
 #define XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ_MASK  (0x70U)
 #define XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ_SHIFT (4U)
+/*! REFTOP_VBGADJ
+ *  0b000..Nominal VBG
+ *  0b001..VBG+0.78%
+ *  0b010..VBG+1.56%
+ *  0b011..VBG+2.34%
+ *  0b100..VBG-0.78%
+ *  0b101..VBG-1.56%
+ *  0b110..VBG-2.34%
+ *  0b111..VBG-3.12%
+ */
 #define XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ(x)    (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ_SHIFT)) & XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ_MASK)
 #define XTALOSC24M_MISC0_CLR_REFTOP_VBGUP_MASK   (0x80U)
 #define XTALOSC24M_MISC0_CLR_REFTOP_VBGUP_SHIFT  (7U)
 #define XTALOSC24M_MISC0_CLR_REFTOP_VBGUP(x)     (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_REFTOP_VBGUP_SHIFT)) & XTALOSC24M_MISC0_CLR_REFTOP_VBGUP_MASK)
 #define XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG_MASK (0xC00U)
 #define XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG_SHIFT (10U)
+/*! STOP_MODE_CONFIG
+ *  0b00..All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off;
+ *  0b01..Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off;
+ *  0b10..XtalOsc=off, RCOsc=on, Old BG=on, New BG=off.
+ *  0b11..XtalOsc=off, RCOsc=on, Old BG=off, New BG=on.
+ */
 #define XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG_SHIFT)) & XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG_MASK)
 #define XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS_MASK (0x1000U)
 #define XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT (12U)
+/*! DISCON_HIGH_SNVS
+ *  0b0..Turn on the switch
+ *  0b1..Turn off the switch
+ */
 #define XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT)) & XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS_MASK)
 #define XTALOSC24M_MISC0_CLR_OSC_I_MASK          (0x6000U)
 #define XTALOSC24M_MISC0_CLR_OSC_I_SHIFT         (13U)
+/*! OSC_I
+ *  0b00..Nominal
+ *  0b01..Decrease current by 12.5%
+ *  0b10..Decrease current by 25.0%
+ *  0b11..Decrease current by 37.5%
+ */
 #define XTALOSC24M_MISC0_CLR_OSC_I(x)            (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_OSC_I_SHIFT)) & XTALOSC24M_MISC0_CLR_OSC_I_MASK)
 #define XTALOSC24M_MISC0_CLR_OSC_XTALOK_MASK     (0x8000U)
 #define XTALOSC24M_MISC0_CLR_OSC_XTALOK_SHIFT    (15U)
@@ -29299,18 +43809,40 @@ typedef struct {
 #define XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN(x)    (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN_SHIFT)) & XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN_MASK)
 #define XTALOSC24M_MISC0_CLR_CLKGATE_CTRL_MASK   (0x2000000U)
 #define XTALOSC24M_MISC0_CLR_CLKGATE_CTRL_SHIFT  (25U)
+/*! CLKGATE_CTRL
+ *  0b0..Allow the logic to automatically gate the clock when the XTAL is powered down.
+ *  0b1..Prevent the logic from ever gating off the clock.
+ */
 #define XTALOSC24M_MISC0_CLR_CLKGATE_CTRL(x)     (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_CLKGATE_CTRL_SHIFT)) & XTALOSC24M_MISC0_CLR_CLKGATE_CTRL_MASK)
 #define XTALOSC24M_MISC0_CLR_CLKGATE_DELAY_MASK  (0x1C000000U)
 #define XTALOSC24M_MISC0_CLR_CLKGATE_DELAY_SHIFT (26U)
+/*! CLKGATE_DELAY
+ *  0b000..0.5ms
+ *  0b001..1.0ms
+ *  0b010..2.0ms
+ *  0b011..3.0ms
+ *  0b100..4.0ms
+ *  0b101..5.0ms
+ *  0b110..6.0ms
+ *  0b111..7.0ms
+ */
 #define XTALOSC24M_MISC0_CLR_CLKGATE_DELAY(x)    (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_CLKGATE_DELAY_SHIFT)) & XTALOSC24M_MISC0_CLR_CLKGATE_DELAY_MASK)
 #define XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE_MASK (0x20000000U)
 #define XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT (29U)
+/*! RTC_XTAL_SOURCE
+ *  0b0..Internal ring oscillator
+ *  0b1..RTC_XTAL
+ */
 #define XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE(x)  (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT)) & XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE_MASK)
 #define XTALOSC24M_MISC0_CLR_XTAL_24M_PWD_MASK   (0x40000000U)
 #define XTALOSC24M_MISC0_CLR_XTAL_24M_PWD_SHIFT  (30U)
 #define XTALOSC24M_MISC0_CLR_XTAL_24M_PWD(x)     (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_XTAL_24M_PWD_SHIFT)) & XTALOSC24M_MISC0_CLR_XTAL_24M_PWD_MASK)
 #define XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV_MASK (0x80000000U)
 #define XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV_SHIFT (31U)
+/*! VID_PLL_PREDIV
+ *  0b0..Divide by 1
+ *  0b1..Divide by 2
+ */
 #define XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV(x)   (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV_SHIFT)) & XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV_MASK)
 /*! @} */
 
@@ -29321,21 +43853,51 @@ typedef struct {
 #define XTALOSC24M_MISC0_TOG_REFTOP_PWD(x)       (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_REFTOP_PWD_SHIFT)) & XTALOSC24M_MISC0_TOG_REFTOP_PWD_MASK)
 #define XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF_MASK (0x8U)
 #define XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT (3U)
+/*! REFTOP_SELFBIASOFF
+ *  0b0..Uses coarse bias currents for startup
+ *  0b1..Uses bandgap-based bias currents for best performance.
+ */
 #define XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT)) & XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF_MASK)
 #define XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ_MASK  (0x70U)
 #define XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ_SHIFT (4U)
+/*! REFTOP_VBGADJ
+ *  0b000..Nominal VBG
+ *  0b001..VBG+0.78%
+ *  0b010..VBG+1.56%
+ *  0b011..VBG+2.34%
+ *  0b100..VBG-0.78%
+ *  0b101..VBG-1.56%
+ *  0b110..VBG-2.34%
+ *  0b111..VBG-3.12%
+ */
 #define XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ(x)    (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ_SHIFT)) & XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ_MASK)
 #define XTALOSC24M_MISC0_TOG_REFTOP_VBGUP_MASK   (0x80U)
 #define XTALOSC24M_MISC0_TOG_REFTOP_VBGUP_SHIFT  (7U)
 #define XTALOSC24M_MISC0_TOG_REFTOP_VBGUP(x)     (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_REFTOP_VBGUP_SHIFT)) & XTALOSC24M_MISC0_TOG_REFTOP_VBGUP_MASK)
 #define XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG_MASK (0xC00U)
 #define XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG_SHIFT (10U)
+/*! STOP_MODE_CONFIG
+ *  0b00..All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off;
+ *  0b01..Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off;
+ *  0b10..XtalOsc=off, RCOsc=on, Old BG=on, New BG=off.
+ *  0b11..XtalOsc=off, RCOsc=on, Old BG=off, New BG=on.
+ */
 #define XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG_SHIFT)) & XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG_MASK)
 #define XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS_MASK (0x1000U)
 #define XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT (12U)
+/*! DISCON_HIGH_SNVS
+ *  0b0..Turn on the switch
+ *  0b1..Turn off the switch
+ */
 #define XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT)) & XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS_MASK)
 #define XTALOSC24M_MISC0_TOG_OSC_I_MASK          (0x6000U)
 #define XTALOSC24M_MISC0_TOG_OSC_I_SHIFT         (13U)
+/*! OSC_I
+ *  0b00..Nominal
+ *  0b01..Decrease current by 12.5%
+ *  0b10..Decrease current by 25.0%
+ *  0b11..Decrease current by 37.5%
+ */
 #define XTALOSC24M_MISC0_TOG_OSC_I(x)            (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_OSC_I_SHIFT)) & XTALOSC24M_MISC0_TOG_OSC_I_MASK)
 #define XTALOSC24M_MISC0_TOG_OSC_XTALOK_MASK     (0x8000U)
 #define XTALOSC24M_MISC0_TOG_OSC_XTALOK_SHIFT    (15U)
@@ -29345,18 +43907,40 @@ typedef struct {
 #define XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN(x)    (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN_SHIFT)) & XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN_MASK)
 #define XTALOSC24M_MISC0_TOG_CLKGATE_CTRL_MASK   (0x2000000U)
 #define XTALOSC24M_MISC0_TOG_CLKGATE_CTRL_SHIFT  (25U)
+/*! CLKGATE_CTRL
+ *  0b0..Allow the logic to automatically gate the clock when the XTAL is powered down.
+ *  0b1..Prevent the logic from ever gating off the clock.
+ */
 #define XTALOSC24M_MISC0_TOG_CLKGATE_CTRL(x)     (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_CLKGATE_CTRL_SHIFT)) & XTALOSC24M_MISC0_TOG_CLKGATE_CTRL_MASK)
 #define XTALOSC24M_MISC0_TOG_CLKGATE_DELAY_MASK  (0x1C000000U)
 #define XTALOSC24M_MISC0_TOG_CLKGATE_DELAY_SHIFT (26U)
+/*! CLKGATE_DELAY
+ *  0b000..0.5ms
+ *  0b001..1.0ms
+ *  0b010..2.0ms
+ *  0b011..3.0ms
+ *  0b100..4.0ms
+ *  0b101..5.0ms
+ *  0b110..6.0ms
+ *  0b111..7.0ms
+ */
 #define XTALOSC24M_MISC0_TOG_CLKGATE_DELAY(x)    (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_CLKGATE_DELAY_SHIFT)) & XTALOSC24M_MISC0_TOG_CLKGATE_DELAY_MASK)
 #define XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE_MASK (0x20000000U)
 #define XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT (29U)
+/*! RTC_XTAL_SOURCE
+ *  0b0..Internal ring oscillator
+ *  0b1..RTC_XTAL
+ */
 #define XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE(x)  (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT)) & XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE_MASK)
 #define XTALOSC24M_MISC0_TOG_XTAL_24M_PWD_MASK   (0x40000000U)
 #define XTALOSC24M_MISC0_TOG_XTAL_24M_PWD_SHIFT  (30U)
 #define XTALOSC24M_MISC0_TOG_XTAL_24M_PWD(x)     (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_XTAL_24M_PWD_SHIFT)) & XTALOSC24M_MISC0_TOG_XTAL_24M_PWD_MASK)
 #define XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV_MASK (0x80000000U)
 #define XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV_SHIFT (31U)
+/*! VID_PLL_PREDIV
+ *  0b0..Divide by 1
+ *  0b1..Divide by 2
+ */
 #define XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV(x)   (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV_SHIFT)) & XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV_MASK)
 /*! @} */
 
@@ -29364,12 +43948,24 @@ typedef struct {
 /*! @{ */
 #define XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK    (0x1U)
 #define XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_SHIFT   (0U)
+/*! RC_OSC_EN
+ *  0b0..Use XTAL OSC to source the 24MHz clock
+ *  0b1..Use RC OSC
+ */
 #define XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN(x)      (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK)
 #define XTALOSC24M_LOWPWR_CTRL_OSC_SEL_MASK      (0x10U)
 #define XTALOSC24M_LOWPWR_CTRL_OSC_SEL_SHIFT     (4U)
+/*! OSC_SEL
+ *  0b0..XTAL OSC
+ *  0b1..RC OSC
+ */
 #define XTALOSC24M_LOWPWR_CTRL_OSC_SEL(x)        (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_OSC_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_OSC_SEL_MASK)
 #define XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_MASK     (0x20U)
 #define XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_SHIFT    (5U)
+/*! LPBG_SEL
+ *  0b0..Normal power bandgap
+ *  0b1..Low power bandgap
+ */
 #define XTALOSC24M_LOWPWR_CTRL_LPBG_SEL(x)       (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_MASK)
 #define XTALOSC24M_LOWPWR_CTRL_LPBG_TEST_MASK    (0x40U)
 #define XTALOSC24M_LOWPWR_CTRL_LPBG_TEST_SHIFT   (6U)
@@ -29394,9 +43990,19 @@ typedef struct {
 #define XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_MASK)
 #define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_MASK (0xC000U)
 #define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_SHIFT (14U)
+/*! XTALOSC_PWRUP_DELAY
+ *  0b00..0.25ms
+ *  0b01..0.5ms
+ *  0b10..1ms
+ *  0b11..2ms
+ */
 #define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_MASK)
 #define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_MASK (0x10000U)
 #define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_SHIFT (16U)
+/*! XTALOSC_PWRUP_STAT
+ *  0b0..Not stable
+ *  0b1..Stable and ready to use
+ */
 #define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_MASK)
 #define XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE_MASK  (0x20000U)
 #define XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE_SHIFT (17U)
@@ -29410,12 +44016,24 @@ typedef struct {
 /*! @{ */
 #define XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN_MASK (0x1U)
 #define XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN_SHIFT (0U)
+/*! RC_OSC_EN
+ *  0b0..Use XTAL OSC to source the 24MHz clock
+ *  0b1..Use RC OSC
+ */
 #define XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN(x)  (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN_MASK)
 #define XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_MASK  (0x10U)
 #define XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_SHIFT (4U)
+/*! OSC_SEL
+ *  0b0..XTAL OSC
+ *  0b1..RC OSC
+ */
 #define XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL(x)    (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_MASK)
 #define XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL_MASK (0x20U)
 #define XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL_SHIFT (5U)
+/*! LPBG_SEL
+ *  0b0..Normal power bandgap
+ *  0b1..Low power bandgap
+ */
 #define XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL(x)   (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL_MASK)
 #define XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST_MASK (0x40U)
 #define XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST_SHIFT (6U)
@@ -29440,9 +44058,19 @@ typedef struct {
 #define XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_MASK)
 #define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_MASK (0xC000U)
 #define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_SHIFT (14U)
+/*! XTALOSC_PWRUP_DELAY
+ *  0b00..0.25ms
+ *  0b01..0.5ms
+ *  0b10..1ms
+ *  0b11..2ms
+ */
 #define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_MASK)
 #define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_MASK (0x10000U)
 #define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_SHIFT (16U)
+/*! XTALOSC_PWRUP_STAT
+ *  0b0..Not stable
+ *  0b1..Stable and ready to use
+ */
 #define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_MASK)
 #define XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE_MASK (0x20000U)
 #define XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE_SHIFT (17U)
@@ -29456,12 +44084,24 @@ typedef struct {
 /*! @{ */
 #define XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN_MASK (0x1U)
 #define XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN_SHIFT (0U)
+/*! RC_OSC_EN
+ *  0b0..Use XTAL OSC to source the 24MHz clock
+ *  0b1..Use RC OSC
+ */
 #define XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN(x)  (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN_MASK)
 #define XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_MASK  (0x10U)
 #define XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_SHIFT (4U)
+/*! OSC_SEL
+ *  0b0..XTAL OSC
+ *  0b1..RC OSC
+ */
 #define XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL(x)    (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_MASK)
 #define XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL_MASK (0x20U)
 #define XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL_SHIFT (5U)
+/*! LPBG_SEL
+ *  0b0..Normal power bandgap
+ *  0b1..Low power bandgap
+ */
 #define XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL(x)   (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL_MASK)
 #define XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST_MASK (0x40U)
 #define XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST_SHIFT (6U)
@@ -29486,9 +44126,19 @@ typedef struct {
 #define XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_MASK)
 #define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_MASK (0xC000U)
 #define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_SHIFT (14U)
+/*! XTALOSC_PWRUP_DELAY
+ *  0b00..0.25ms
+ *  0b01..0.5ms
+ *  0b10..1ms
+ *  0b11..2ms
+ */
 #define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_MASK)
 #define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_MASK (0x10000U)
 #define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_SHIFT (16U)
+/*! XTALOSC_PWRUP_STAT
+ *  0b0..Not stable
+ *  0b1..Stable and ready to use
+ */
 #define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_MASK)
 #define XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE_MASK (0x20000U)
 #define XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE_SHIFT (17U)
@@ -29502,12 +44152,24 @@ typedef struct {
 /*! @{ */
 #define XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN_MASK (0x1U)
 #define XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN_SHIFT (0U)
+/*! RC_OSC_EN
+ *  0b0..Use XTAL OSC to source the 24MHz clock
+ *  0b1..Use RC OSC
+ */
 #define XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN(x)  (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN_MASK)
 #define XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL_MASK  (0x10U)
 #define XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL_SHIFT (4U)
+/*! OSC_SEL
+ *  0b0..XTAL OSC
+ *  0b1..RC OSC
+ */
 #define XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL(x)    (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL_MASK)
 #define XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL_MASK (0x20U)
 #define XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL_SHIFT (5U)
+/*! LPBG_SEL
+ *  0b0..Normal power bandgap
+ *  0b1..Low power bandgap
+ */
 #define XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL(x)   (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL_MASK)
 #define XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST_MASK (0x40U)
 #define XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST_SHIFT (6U)
@@ -29532,9 +44194,19 @@ typedef struct {
 #define XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_MASK)
 #define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_MASK (0xC000U)
 #define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_SHIFT (14U)
+/*! XTALOSC_PWRUP_DELAY
+ *  0b00..0.25ms
+ *  0b01..0.5ms
+ *  0b10..1ms
+ *  0b11..2ms
+ */
 #define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_MASK)
 #define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_MASK (0x10000U)
 #define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_SHIFT (16U)
+/*! XTALOSC_PWRUP_STAT
+ *  0b0..Not stable
+ *  0b1..Stable and ready to use
+ */
 #define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_MASK)
 #define XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE_MASK (0x20000U)
 #define XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE_SHIFT (17U)
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/MIMXRT1052_features.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/MIMXRT1052_features.h
index 765ebaddda3..fcd0ae3c5e6 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/MIMXRT1052_features.h
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/MIMXRT1052_features.h
@@ -1,44 +1,16 @@
 /*
 ** ###################################################################
-**     Version:             rev. 0.1, 2017-01-10
-**     Build:               b180509
+**     Version:             rev. 1.1, 2018-11-16
+**     Build:               b190319
 **
 **     Abstract:
 **         Chip specific module features.
 **
-**     The Clear BSD License
 **     Copyright 2016 Freescale Semiconductor, Inc.
-**     Copyright 2016-2018 NXP
+**     Copyright 2016-2019 NXP
 **     All rights reserved.
 **
-**     Redistribution and use in source and binary forms, with or without
-**     modification, are permitted (subject to the limitations in the
-**     disclaimer below) provided that the following conditions are met:
-**
-**     * Redistributions of source code must retain the above copyright
-**       notice, this list of conditions and the following disclaimer.
-**
-**     * Redistributions in binary form must reproduce the above copyright
-**       notice, this list of conditions and the following disclaimer in the
-**       documentation and/or other materials provided with the distribution.
-**
-**     * Neither the name of the copyright holder nor the names of its
-**       contributors may be used to endorse or promote products derived from
-**       this software without specific prior written permission.
-**
-**     NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
-**     GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
-**     HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
-**     WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-**     MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-**     LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-**     CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-**     SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
-**     BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-**     WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
-**     OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
-**     IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**     SPDX-License-Identifier: BSD-3-Clause
 **
 **     http:                 www.nxp.com
 **     mail:                 support@nxp.com
@@ -46,6 +18,12 @@
 **     Revisions:
 **     - rev. 0.1 (2017-01-10)
 **         Initial version.
+**     - rev. 1.0 (2018-09-21)
+**         Update interrupt vector table and dma request source.
+**         Update register BEE_ADDR_OFFSET1's bitfield name to ADDR_OFFSET1.
+**         Split GPIO_COMBINED_IRQS to GPIO_COMBINED_LOW_IRQS and GPIO_COMBINED_HIGH_IRQS.
+**     - rev. 1.1 (2018-11-16)
+**         Update feature files to align with IMXRT1050RM Rev.1.
 **
 ** ###################################################################
 */
@@ -166,6 +144,8 @@
 #define FSL_FEATURE_ADC_SUPPORT_HARDWARE_TRIGGER_REMOVE (0)
 /* @brief Remove ALT Clock selection feature. */
 #define FSL_FEATURE_ADC_SUPPORT_ALTCLK_REMOVE (1)
+/* @brief Conversion control count (related to number of registers HCn and Rn). */
+#define FSL_FEATURE_ADC_CONVERSION_CONTROL_COUNT (8)
 
 /* ADC_ETC module features */
 
@@ -185,20 +165,34 @@
 #define FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(x) (64)
 /* @brief Has doze mode support (register bit field MCR[DOZE]). */
 #define FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT (0)
+/* @brief Insatnce has doze mode support (register bit field MCR[DOZE]). */
+#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_DOZE_MODE_SUPPORTn(x) (0)
 /* @brief Has a glitch filter on the receive pin (register bit field MCR[WAKSRC]). */
 #define FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER (1)
 /* @brief Has extended interrupt mask and flag register (register IMASK2, IFLAG2). */
 #define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER (1)
-/* @brief Has extended bit timing register (register CBT). */
-#define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_TIMING_REGISTER (0)
+/* @brief Instance has extended bit timing register (register CBT). */
+#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_EXTENDED_TIMING_REGISTERn(x) (0)
 /* @brief Has a receive FIFO DMA feature (register bit field MCR[DMA]). */
 #define FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA (0)
+/* @brief Instance has a receive FIFO DMA feature (register bit field MCR[DMA]). */
+#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_RX_FIFO_DMAn(x) (0)
 /* @brief Remove CAN Engine Clock Source Selection from unsupported part. */
 #define FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE (1)
+/* @brief Instance remove CAN Engine Clock Source Selection from unsupported part. */
+#define FSL_FEATURE_FLEXCAN_INSTANCE_SUPPORT_ENGINE_CLK_SEL_REMOVEn(x) (1)
 /* @brief Is affected by errata with ID 5641 (Module does not transmit a message that is enabled to be transmitted at a specific moment during the arbitration process). */
 #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641 (0)
+/* @brief Is affected by errata with ID 5829 (FlexCAN: FlexCAN does not transmit a message that is enabled to be transmitted in a specific moment during the arbitration process). */
+#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829 (1)
+/* @brief Is affected by errata with ID 6032 (FlexCAN: A frame with wrong ID or payload is transmitted into the CAN bus when the Message Buffer under transmission is either aborted or deactivated while the CAN bus is in the Bus Idle state). */
+#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032 (1)
+/* @brief Is affected by errata with ID 9595 (FlexCAN: Corrupt frame possible if the Freeze Mode or the Low-Power Mode are entered during a Bus-Off state). */
+#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_9595 (1)
 /* @brief Has CAN with Flexible Data rate (CAN FD) protocol. */
 #define FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE (0)
+/* @brief CAN instance support Flexible Data rate (CAN FD) protocol. */
+#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_FLEXIBLE_DATA_RATEn(x) (0)
 /* @brief Has extra MB interrupt or common one. */
 #define FSL_FEATURE_FLEXCAN_HAS_EXTRA_MB_INT (1)
 
@@ -229,6 +223,12 @@
 #define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (1)
 /* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */
 #define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (32)
+/* @brief Channel IRQ entry shared offset. */
+#define FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SHARED_OFFSET (16)
+/* @brief If 8 bytes transfer supported. */
+#define FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER (1)
+/* @brief If 16 bytes transfer supported. */
+#define FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER (0)
 
 /* DMAMUX module features */
 
@@ -256,6 +256,13 @@
 /* @brief Has Additional 1588 Timer Channel Interrupt. */
 #define FSL_FEATURE_ENET_HAS_ADD_1588_TIMER_CHN_INT (0)
 
+/* EWM module features */
+
+/* @brief Has clock select (register CLKCTRL). */
+#define FSL_FEATURE_EWM_HAS_CLOCK_SELECT (1)
+/* @brief Has clock prescaler (register CLKPRESCALER). */
+#define FSL_FEATURE_EWM_HAS_PRESCALER (1)
+
 /* FLEXIO module features */
 
 /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */
@@ -278,11 +285,13 @@
 #define FSL_FEATURE_FLEXIO_VERID_RESET_VALUE (0x1010001)
 /* @brief Reset value of the FLEXIO_PARAM register */
 #define FSL_FEATURE_FLEXIO_PARAM_RESET_VALUE (0x2200404)
+/* @brief Flexio DMA request base channel */
+#define FSL_FEATURE_FLEXIO_DMA_REQUEST_BASE_CHANNEL (0)
 
 /* FLEXRAM module features */
 
 /* @brief Bank size */
-#define FSL_FEATURE_FLEXRAM_INTERNAL_RAM_BANK_SIZE (32 * 1024)
+#define FSL_FEATURE_FLEXRAM_INTERNAL_RAM_BANK_SIZE (32768)
 /* @brief Total Bank numbers */
 #define FSL_FEATURE_FLEXRAM_INTERNAL_RAM_TOTAL_BANK_NUMBERS (16)
 
@@ -418,7 +427,7 @@
 /* @brief Lowest interrupt request number. */
 #define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14)
 /* @brief Highest interrupt request number. */
-#define FSL_FEATURE_INTERRUPT_IRQ_MAX (159)
+#define FSL_FEATURE_INTERRUPT_IRQ_MAX (151)
 
 /* OCOTP module features */
 
@@ -488,7 +497,10 @@
 /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */
 #define FSL_FEATURE_SAI_FIFO_COUNT (32)
 /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */
-#define FSL_FEATURE_SAI_CHANNEL_COUNT (4)
+#define FSL_FEATURE_SAI_CHANNEL_COUNTn(x) \
+    (((x) == SAI1) ? (4) : \
+    (((x) == SAI2) ? (1) : \
+    (((x) == SAI3) ? (1) : (-1))))
 /* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ], RMR[RWM]). */
 #define FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME (32)
 /* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR], TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */
@@ -507,8 +519,23 @@
 #define FSL_FEATURE_SAI_INT_SOURCE_NUM (2)
 /* @brief Has register of MCR. */
 #define FSL_FEATURE_SAI_HAS_MCR (0)
+/* @brief Has bit field MICS of the MCR register. */
+#define FSL_FEATURE_SAI_HAS_NO_MCR_MICS (1)
 /* @brief Has register of MDR */
 #define FSL_FEATURE_SAI_HAS_MDR (0)
+/* @brief Has support the BCLK bypass mode when BCLK = MCLK. */
+#define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (0)
+/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */
+#define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (0)
+/* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */
+#define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1)
+
+/* SEMC module features */
+
+/* @brief Has WDH time in NOR controller (register bit field NORCR2[WDH]). */
+#define FSL_FEATURE_SEMC_HAS_NOR_WDH_TIME (1)
+/* @brief Has WDS time in NOR controller (register bit field NORCR2[WDS]).) */
+#define FSL_FEATURE_SEMC_HAS_NOR_WDS_TIME (1)
 
 /* SNVS module features */
 
@@ -602,14 +629,8 @@
 
 /* XBARA module features */
 
-/* @brief DMA_CH_MUX_REQ_30. */
-#define FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_30 (1)
-/* @brief DMA_CH_MUX_REQ_31. */
-#define FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_31 (1)
-/* @brief DMA_CH_MUX_REQ_94. */
-#define FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_94 (1)
-/* @brief DMA_CH_MUX_REQ_95. */
-#define FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_95 (1)
+/* @brief Number of interrupt requests. */
+#define FSL_FEATURE_XBARA_INTERRUPT_COUNT (4)
 
 #endif /* _MIMXRT1052_FEATURES_H_ */
 
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/TOOLCHAIN_ARM_STD/MIMXRT1052xxxxx.sct b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/TOOLCHAIN_ARM_STD/MIMXRT1052xxxxx.sct
index e379c37b1c9..632f0e1079d 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/TOOLCHAIN_ARM_STD/MIMXRT1052xxxxx.sct
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/TOOLCHAIN_ARM_STD/MIMXRT1052xxxxx.sct
@@ -8,45 +8,17 @@
 **
 **     Compiler:            Keil ARM C/C++ Compiler
 **     Reference manual:    IMXRT1050RM Rev.1, 03/2018
-**     Version:             rev. 0.1, 2017-01-10
-**     Build:               b180606
+**     Version:             rev. 1.0, 2018-09-21
+**     Build:               b180921
 **
 **     Abstract:
 **         Linker file for the Keil ARM C/C++ Compiler
 **
-**     The Clear BSD License
 **     Copyright 2016 Freescale Semiconductor, Inc.
 **     Copyright 2016-2018 NXP
 **     All rights reserved.
 **
-**     Redistribution and use in source and binary forms, with or without
-**     modification, are permitted (subject to the limitations in the
-**     disclaimer below) provided that the following conditions are met:
-**
-**     * Redistributions of source code must retain the above copyright
-**       notice, this list of conditions and the following disclaimer.
-**
-**     * Redistributions in binary form must reproduce the above copyright
-**       notice, this list of conditions and the following disclaimer in the
-**       documentation and/or other materials provided with the distribution.
-**
-**     * Neither the name of the copyright holder nor the names of its
-**       contributors may be used to endorse or promote products derived from
-**       this software without specific prior written permission.
-**
-**     NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
-**     GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
-**     HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
-**     WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-**     MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-**     LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-**     CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-**     SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
-**     BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-**     WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
-**     OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
-**     IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**     SPDX-License-Identifier: BSD-3-Clause
 **
 **     http:                 www.nxp.com
 **     mail:                 support@nxp.com
@@ -62,17 +34,33 @@
   #define __ram_vector_table_size__    0x00000000
 #endif
 
-#define m_flash_config_start           0x60000000
+#if !defined(MBED_APP_START)
+  #define MBED_APP_START 0x60000000
+#endif
+
+#if !defined(MBED_APP_SIZE)
+  #define MBED_APP_SIZE 0x400000
+#endif
+
+#if !defined(MBED_APP_COMPILE)
+#define m_flash_config_start           MBED_APP_START
 #define m_flash_config_size            0x00001000
 
-#define m_ivt_start                    0x60001000
+#define m_ivt_start                    MBED_APP_START + 0x1000
 #define m_ivt_size                     0x00001000
 
-#define m_interrupts_start             0x60002000
+#define m_interrupts_start             MBED_APP_START + 0x2000
+#define m_interrupts_size              0x00000400
+
+#define m_text_start                   MBED_APP_START + 0x2400
+#define m_text_size                    MBED_APP_SIZE - 0x2400
+#else
+#define m_interrupts_start             MBED_APP_START
 #define m_interrupts_size              0x00000400
 
-#define m_text_start                   0x60002400
-#define m_text_size                    0x03FFDC00
+#define m_text_start                   MBED_APP_START + 0x400
+#define m_text_size                    MBED_APP_SIZE - 0x400
+#endif
 
 #define m_text2_start                  0x00000000
 #define m_text2_size                   0x00020000
@@ -110,7 +98,8 @@
   #define Heap_Size                    0x0400
 #endif
 
-LR_IROM1 m_flash_config_start m_text_start+m_text_size-m_flash_config_start {   ; load region size_region
+LR_IROM1 MBED_APP_START m_text_start+m_text_size-MBED_APP_START {   ; load region size_region
+#if !defined(MBED_APP_COMPILE)
   RW_m_config_text m_flash_config_start FIXED m_flash_config_size { ; load address = execution address
     * (.boot_hdr.conf, +FIRST)
   }
@@ -120,6 +109,7 @@ LR_IROM1 m_flash_config_start m_text_start+m_text_size-m_flash_config_start {
     * (.boot_hdr.boot_data)
     * (.boot_hdr.dcd_data)
   }
+#endif
   VECTOR_ROM m_interrupts_start FIXED m_interrupts_size { ; load address = execution address
     * (RESET,+FIRST)
   }
@@ -146,8 +136,8 @@ LR_IROM1 m_flash_config_start m_text_start+m_text_size-m_flash_config_start {
   }
   ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size  { ; Stack region growing down
   }
-  RW_m_ram_text m_text2_start UNINIT m_text2_size { ; load address = execution address
-    * (RamFunction)
+  RW_m_ram_text m_text2_start m_text2_size {
+    * (CodeQuickAccess)
   }
   RW_m_ncache m_ncache_start m_ncache_size { ; ncache RW data
     * (NonCacheable.init)
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/TOOLCHAIN_ARM_STD/startup_MIMXRT1052.S b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/TOOLCHAIN_ARM_STD/startup_MIMXRT1052.S
index a40c03d6ac6..928f7d081de 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/TOOLCHAIN_ARM_STD/startup_MIMXRT1052.S
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/TOOLCHAIN_ARM_STD/startup_MIMXRT1052.S
@@ -2,44 +2,16 @@
 ; *  @file:    startup_MIMXRT1052.s
 ; *  @purpose: CMSIS Cortex-M7 Core Device Startup File
 ; *            MIMXRT1052
-; *  @version: 0.1
-; *  @date:    2017-1-10
-; *  @build:   b180509
+; *  @version: 1.2
+; *  @date:    2018-11-27
+; *  @build:   b190124
 ; * -------------------------------------------------------------------------
 ; *
-; * The Clear BSD License
 ; * Copyright 1997-2016 Freescale Semiconductor, Inc.
-; * Copyright 2016-2018 NXP
+; * Copyright 2016-2019 NXP
 ; * All rights reserved.
 ; *
-; * Redistribution and use in source and binary forms, with or without
-; * modification, are permitted (subject to the limitations in the
-; * disclaimer below) provided that the following conditions are met:
-; *
-; * * Redistributions of source code must retain the above copyright
-; *   notice, this list of conditions and the following disclaimer.
-; *
-; * * Redistributions in binary form must reproduce the above copyright
-; *   notice, this list of conditions and the following disclaimer in the
-; *   documentation and/or other materials provided with the distribution.
-; *
-; * * Neither the name of the copyright holder nor the names of its
-; *   contributors may be used to endorse or promote products derived from
-; *   this software without specific prior written permission.
-; *
-; * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
-; * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
-; * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
-; * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-; * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-; * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-; * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
-; * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-; * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
-; * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
-; * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+; * SPDX-License-Identifier: BSD-3-Clause
 ; *
 ; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
 ; *
@@ -137,10 +109,10 @@ __Vectors       DCD     |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
                 DCD     SAI3_RX_IRQHandler                  ;SAI3 interrupt
                 DCD     SAI3_TX_IRQHandler                  ;SAI3 interrupt
                 DCD     SPDIF_IRQHandler                    ;SPDIF interrupt
-                DCD     ANATOP_EVENT0_IRQHandler            ;ANATOP interrupt
-                DCD     ANATOP_EVENT1_IRQHandler            ;ANATOP interrupt
-                DCD     ANATOP_TAMP_LOW_HIGH_IRQHandler     ;ANATOP interrupt
-                DCD     ANATOP_TEMP_PANIC_IRQHandler        ;ANATOP interrupt
+                DCD     PMU_EVENT_IRQHandler                ;Brown-out event interrupt
+                DCD     Reserved78_IRQHandler               ;Reserved interrupt
+                DCD     TEMP_LOW_HIGH_IRQHandler            ;TempSensor low/high interrupt
+                DCD     TEMP_PANIC_IRQHandler               ;TempSensor panic interrupt
                 DCD     USB_PHY1_IRQHandler                 ;USBPHY (UTMI0), Interrupt
                 DCD     USB_PHY2_IRQHandler                 ;USBPHY (UTMI0), Interrupt
                 DCD     ADC1_IRQHandler                     ;ADC1 interrupt
@@ -228,14 +200,14 @@ __Vectors       DCD     |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
                 DCD     PWM4_2_IRQHandler                   ;PWM4 capture 2, compare 2, or reload 0 interrupt
                 DCD     PWM4_3_IRQHandler                   ;PWM4 capture 3, compare 3, or reload 0 interrupt
                 DCD     PWM4_FAULT_IRQHandler               ;PWM4 fault or reload error interrupt
-                DCD     Reserved168_IRQHandler              ;Reserved interrupt
-                DCD     Reserved169_IRQHandler              ;Reserved interrupt
-                DCD     Reserved170_IRQHandler              ;Reserved interrupt
-                DCD     Reserved171_IRQHandler              ;Reserved interrupt
-                DCD     Reserved172_IRQHandler              ;Reserved interrupt
-                DCD     Reserved173_IRQHandler              ;Reserved interrupt
-                DCD     SJC_ARM_DEBUG_IRQHandler            ;SJC ARM debug interrupt
-                DCD     NMI_WAKEUP_IRQHandler               ;NMI wake up
+                DCD     DefaultISR                          ;168
+                DCD     DefaultISR                          ;169
+                DCD     DefaultISR                          ;170
+                DCD     DefaultISR                          ;171
+                DCD     DefaultISR                          ;172
+                DCD     DefaultISR                          ;173
+                DCD     DefaultISR                          ;174
+                DCD     DefaultISR                          ;175
                 DCD     DefaultISR                          ;176
                 DCD     DefaultISR                          ;177
                 DCD     DefaultISR                          ;178
@@ -781,10 +753,10 @@ Default_Handler\
                 EXPORT  SAI3_RX_DriverIRQHandler         [WEAK]
                 EXPORT  SAI3_TX_DriverIRQHandler         [WEAK]
                 EXPORT  SPDIF_DriverIRQHandler         [WEAK]
-                EXPORT  ANATOP_EVENT0_IRQHandler         [WEAK]
-                EXPORT  ANATOP_EVENT1_IRQHandler         [WEAK]
-                EXPORT  ANATOP_TAMP_LOW_HIGH_IRQHandler         [WEAK]
-                EXPORT  ANATOP_TEMP_PANIC_IRQHandler         [WEAK]
+                EXPORT  PMU_EVENT_IRQHandler         [WEAK]
+                EXPORT  Reserved78_IRQHandler         [WEAK]
+                EXPORT  TEMP_LOW_HIGH_IRQHandler         [WEAK]
+                EXPORT  TEMP_PANIC_IRQHandler         [WEAK]
                 EXPORT  USB_PHY1_IRQHandler         [WEAK]
                 EXPORT  USB_PHY2_IRQHandler         [WEAK]
                 EXPORT  ADC1_IRQHandler         [WEAK]
@@ -872,14 +844,6 @@ Default_Handler\
                 EXPORT  PWM4_2_IRQHandler         [WEAK]
                 EXPORT  PWM4_3_IRQHandler         [WEAK]
                 EXPORT  PWM4_FAULT_IRQHandler         [WEAK]
-                EXPORT  Reserved168_IRQHandler         [WEAK]
-                EXPORT  Reserved169_IRQHandler         [WEAK]
-                EXPORT  Reserved170_IRQHandler         [WEAK]
-                EXPORT  Reserved171_IRQHandler         [WEAK]
-                EXPORT  Reserved172_IRQHandler         [WEAK]
-                EXPORT  Reserved173_IRQHandler         [WEAK]
-                EXPORT  SJC_ARM_DEBUG_IRQHandler         [WEAK]
-                EXPORT  NMI_WAKEUP_IRQHandler         [WEAK]
                 EXPORT  DefaultISR         [WEAK]
 DMA0_DMA16_DriverIRQHandler
 DMA1_DMA17_DriverIRQHandler
@@ -942,10 +906,10 @@ SAI2_DriverIRQHandler
 SAI3_RX_DriverIRQHandler
 SAI3_TX_DriverIRQHandler
 SPDIF_DriverIRQHandler
-ANATOP_EVENT0_IRQHandler
-ANATOP_EVENT1_IRQHandler
-ANATOP_TAMP_LOW_HIGH_IRQHandler
-ANATOP_TEMP_PANIC_IRQHandler
+PMU_EVENT_IRQHandler
+Reserved78_IRQHandler
+TEMP_LOW_HIGH_IRQHandler
+TEMP_PANIC_IRQHandler
 USB_PHY1_IRQHandler
 USB_PHY2_IRQHandler
 ADC1_IRQHandler
@@ -1033,14 +997,6 @@ PWM4_1_IRQHandler
 PWM4_2_IRQHandler
 PWM4_3_IRQHandler
 PWM4_FAULT_IRQHandler
-Reserved168_IRQHandler
-Reserved169_IRQHandler
-Reserved170_IRQHandler
-Reserved171_IRQHandler
-Reserved172_IRQHandler
-Reserved173_IRQHandler
-SJC_ARM_DEBUG_IRQHandler
-NMI_WAKEUP_IRQHandler
 DefaultISR
                 LDR    R0, =DefaultISR
                 BX     R0
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/TOOLCHAIN_GCC_ARM/MIMXRT1052xxxxx.ld b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/TOOLCHAIN_GCC_ARM/MIMXRT1052xxxxx.ld
index baa8999fc98..338edf26cff 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/TOOLCHAIN_GCC_ARM/MIMXRT1052xxxxx.ld
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/TOOLCHAIN_GCC_ARM/MIMXRT1052xxxxx.ld
@@ -7,45 +7,17 @@
 **
 **     Compiler:            GNU C Compiler
 **     Reference manual:    IMXRT1050RM Rev.1, 03/2018
-**     Version:             rev. 0.1, 2017-01-10
-**     Build:               b180509
+**     Version:             rev. 1.0, 2018-09-21
+**     Build:               b180921
 **
 **     Abstract:
 **         Linker file for the GNU C Compiler
 **
-**     The Clear BSD License
 **     Copyright 2016 Freescale Semiconductor, Inc.
 **     Copyright 2016-2018 NXP
 **     All rights reserved.
 **
-**     Redistribution and use in source and binary forms, with or without
-**     modification, are permitted (subject to the limitations in the
-**     disclaimer below) provided that the following conditions are met:
-**
-**     * Redistributions of source code must retain the above copyright
-**       notice, this list of conditions and the following disclaimer.
-**
-**     * Redistributions in binary form must reproduce the above copyright
-**       notice, this list of conditions and the following disclaimer in the
-**       documentation and/or other materials provided with the distribution.
-**
-**     * Neither the name of the copyright holder nor the names of its
-**       contributors may be used to endorse or promote products derived from
-**       this software without specific prior written permission.
-**
-**     NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
-**     GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
-**     HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
-**     WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-**     MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-**     LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-**     CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-**     SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
-**     BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-**     WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
-**     OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
-**     IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**     SPDX-License-Identifier: BSD-3-Clause
 **
 **     http:                 www.nxp.com
 **     mail:                 support@nxp.com
@@ -58,6 +30,14 @@ ENTRY(Reset_Handler)
 
 __ram_vector_table__ = 1;
 
+#if !defined(MBED_APP_START)
+  #define MBED_APP_START 0x60000000
+#endif
+
+#if !defined(MBED_APP_SIZE)
+  #define MBED_APP_SIZE 0x400000
+#endif
+
 #if !defined(MBED_BOOT_STACK_SIZE)
     #define MBED_BOOT_STACK_SIZE 0x400
 #endif
@@ -70,10 +50,15 @@ M_VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x0400 : 0x0;
 /* Specify the memory areas */
 MEMORY
 {
-  m_flash_config        (RX)  : ORIGIN = 0x60000000, LENGTH = 0x00001000
-  m_ivt                 (RX)  : ORIGIN = 0x60001000, LENGTH = 0x00001000
-  m_interrupts          (RX)  : ORIGIN = 0x60002000, LENGTH = 0x00000400
-  m_text                (RX)  : ORIGIN = 0x60002400, LENGTH = 0x03FFDC00
+#if !defined(MBED_APP_COMPILE)
+  m_flash_config        (RX)  : ORIGIN = MBED_APP_START, LENGTH = 0x00001000
+  m_ivt                 (RX)  : ORIGIN = MBED_APP_START + 0x1000, LENGTH = 0x00001000
+  m_interrupts          (RX)  : ORIGIN = MBED_APP_START + 0x2000, LENGTH = 0x00000400
+  m_text                (RX)  : ORIGIN = MBED_APP_START + 0x2400, LENGTH = MBED_APP_SIZE - 0x2400
+#else
+  m_interrupts          (RX)  : ORIGIN = MBED_APP_START, LENGTH = 0x00000400
+  m_text                (RX)  : ORIGIN = MBED_APP_START + 0x400, LENGTH = MBED_APP_SIZE - 0x400
+#endif
   m_text2               (RX)  : ORIGIN = 0x00000000, LENGTH = 0x00020000
   m_data                (RW)  : ORIGIN = 0x80000000, LENGTH = 0x01E00000
   m_ncache              (RW)  : ORIGIN = 0x81E00000, LENGTH = 0x00200000
@@ -84,6 +69,7 @@ MEMORY
 /* Define output sections */
 SECTIONS
 {
+#if !defined(MBED_APP_COMPILE)
   .flash_config :
   {
     . = ALIGN(8);
@@ -102,7 +88,7 @@ SECTIONS
     KEEP(* (.boot_hdr.dcd_data))      /* dcd section */
     . = ALIGN(8);
   } > m_ivt
-
+#endif
   /* The startup code goes first into internal RAM */
   .interrupts :
   {
@@ -227,16 +213,15 @@ SECTIONS
     . = ALIGN(8);
     __data_end__ = .;        /* define a global symbol at data end */
   } > m_data
-
   __ram_function_flash_start = __DATA_ROM + (__data_end__ - __data_start__); /* Symbol is used by startup for TCM data initialization */
 
   .ram_function : AT(__ram_function_flash_start)
   {
     . = ALIGN(32);
-    __ram_function_ram_start = .;
-    *(RamFunction)
+    __ram_function_start__ = .;
+    *(CodeQuickAccess)
     . = ALIGN(128);
-    __ram_function_ram_end = .;
+    __ram_function_end__ = .;
   } > m_text2
 
   __ram_function_size = SIZEOF(.ram_function);
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/TOOLCHAIN_GCC_ARM/startup_MIMXRT1052.S b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/TOOLCHAIN_GCC_ARM/startup_MIMXRT1052.S
index a35793b80b0..6eb7e3cdf06 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/TOOLCHAIN_GCC_ARM/startup_MIMXRT1052.S
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/TOOLCHAIN_GCC_ARM/startup_MIMXRT1052.S
@@ -2,44 +2,16 @@
 /*  @file:    startup_MIMXRT1052.s                                           */
 /*  @purpose: CMSIS Cortex-M7 Core Device Startup File                       */
 /*            MIMXRT1052                                                     */
-/*  @version: 0.1                                                            */
-/*  @date:    2017-1-10                                                      */
-/*  @build:   b180509                                                        */
+/*  @version: 1.2                                                            */
+/*  @date:    2018-11-27                                                     */
+/*  @build:   b190124                                                        */
 /* ------------------------------------------------------------------------- */
 /*                                                                           */
-/* The Clear BSD License                                                     */
 /* Copyright 1997-2016 Freescale Semiconductor, Inc.                         */
-/* Copyright 2016-2018 NXP                                                   */
+/* Copyright 2016-2019 NXP                                                   */
 /* All rights reserved.                                                      */
 /*                                                                           */
-/* Redistribution and use in source and binary forms, with or without        */
-/* modification, are permitted (subject to the limitations in the            */
-/* disclaimer below) provided that the following conditions are met:         */
-/*                                                                           */
-/* * Redistributions of source code must retain the above copyright          */
-/*   notice, this list of conditions and the following disclaimer.           */
-/*                                                                           */
-/* * Redistributions in binary form must reproduce the above copyright       */
-/*   notice, this list of conditions and the following disclaimer in the     */
-/*   documentation and/or other materials provided with the distribution.    */
-/*                                                                           */
-/* * Neither the name of the copyright holder nor the names of its           */
-/*   contributors may be used to endorse or promote products derived from    */
-/*   this software without specific prior written permission.                */
-/*                                                                           */
-/* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE           */
-/* GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT       */
-/* HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED               */
-/* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF      */
-/* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE                  */
-/* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE     */
-/* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR       */
-/* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF      */
-/* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR           */
-/* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,     */
-/* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE      */
-/* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN    */
-/* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                             */
+/* SPDX-License-Identifier: BSD-3-Clause                                     */
 /*****************************************************************************/
 /* Version: GCC for ARM Embedded Processors                                  */
 /*****************************************************************************/
@@ -129,10 +101,10 @@ __isr_vector:
     .long   SAI3_RX_IRQHandler                              /* SAI3 interrupt*/
     .long   SAI3_TX_IRQHandler                              /* SAI3 interrupt*/
     .long   SPDIF_IRQHandler                                /* SPDIF interrupt*/
-    .long   ANATOP_EVENT0_IRQHandler                        /* ANATOP interrupt*/
-    .long   ANATOP_EVENT1_IRQHandler                        /* ANATOP interrupt*/
-    .long   ANATOP_TAMP_LOW_HIGH_IRQHandler                 /* ANATOP interrupt*/
-    .long   ANATOP_TEMP_PANIC_IRQHandler                    /* ANATOP interrupt*/
+    .long   PMU_EVENT_IRQHandler                            /* Brown-out event interrupt*/
+    .long   Reserved78_IRQHandler                           /* Reserved interrupt*/
+    .long   TEMP_LOW_HIGH_IRQHandler                        /* TempSensor low/high interrupt*/
+    .long   TEMP_PANIC_IRQHandler                           /* TempSensor panic interrupt*/
     .long   USB_PHY1_IRQHandler                             /* USBPHY (UTMI0), Interrupt*/
     .long   USB_PHY2_IRQHandler                             /* USBPHY (UTMI0), Interrupt*/
     .long   ADC1_IRQHandler                                 /* ADC1 interrupt*/
@@ -220,14 +192,14 @@ __isr_vector:
     .long   PWM4_2_IRQHandler                               /* PWM4 capture 2, compare 2, or reload 0 interrupt*/
     .long   PWM4_3_IRQHandler                               /* PWM4 capture 3, compare 3, or reload 0 interrupt*/
     .long   PWM4_FAULT_IRQHandler                           /* PWM4 fault or reload error interrupt*/
-    .long   Reserved168_IRQHandler                          /* Reserved interrupt*/
-    .long   Reserved169_IRQHandler                          /* Reserved interrupt*/
-    .long   Reserved170_IRQHandler                          /* Reserved interrupt*/
-    .long   Reserved171_IRQHandler                          /* Reserved interrupt*/
-    .long   Reserved172_IRQHandler                          /* Reserved interrupt*/
-    .long   Reserved173_IRQHandler                          /* Reserved interrupt*/
-    .long   SJC_ARM_DEBUG_IRQHandler                        /* SJC ARM debug interrupt*/
-    .long   NMI_WAKEUP_IRQHandler                           /* NMI wake up*/
+    .long   DefaultISR                                      /* 168*/
+    .long   DefaultISR                                      /* 169*/
+    .long   DefaultISR                                      /* 170*/
+    .long   DefaultISR                                      /* 171*/
+    .long   DefaultISR                                      /* 172*/
+    .long   DefaultISR                                      /* 173*/
+    .long   DefaultISR                                      /* 174*/
+    .long   DefaultISR                                      /* 175*/
     .long   DefaultISR                                      /* 176*/
     .long   DefaultISR                                      /* 177*/
     .long   DefaultISR                                      /* 178*/
@@ -339,43 +311,64 @@ Reset_Handler:
  *      __etext: End of code section, i.e., begin of data sections to copy from.
  *      __data_start__/__data_end__: RAM address range that data should be
  *      __noncachedata_start__/__noncachedata_end__ : none cachable region
+ *      __ram_function_start__/__ram_function_end__ : ramfunction region
  *      copied to. Both must be aligned to 4 bytes boundary.  */
 
     ldr    r1, =__etext
     ldr    r2, =__data_start__
     ldr    r3, =__data_end__
 
-#if 1
-/* Here are two copies of loop implemenations. First one favors code size
- * and the second one favors performance. Default uses the first one.
- * Change to "#if 0" to use the second one */
+#ifdef __PERFORMANCE_IMPLEMENTATION
+/* Here are two copies of loop implementations. First one favors performance
+ * and the second one favors code size. Default uses the second one.
+ * Define macro "__PERFORMANCE_IMPLEMENTATION" in project to use the first one */
+    subs    r3, r2
+    ble    .LC1
+.LC0:
+    subs    r3, #4
+    ldr    r0, [r1, r3]
+    str    r0, [r2, r3]
+    bgt    .LC0
+.LC1:
+#else  /* code size implemenation */
 .LC0:
     cmp     r2, r3
     ittt    lt
     ldrlt   r0, [r1], #4
     strlt   r0, [r2], #4
     blt    .LC0
-#else
+#endif
+#ifdef __STARTUP_INITIALIZE_RAMFUNCTION
+    ldr    r2, =__ram_function_start__
+    ldr    r3, =__ram_function_end__
+#ifdef __PERFORMANCE_IMPLEMENTATION
+/* Here are two copies of loop implementations. First one favors performance
+ * and the second one favors code size. Default uses the second one.
+ * Define macro "__PERFORMANCE_IMPLEMENTATION" in project to use the first one */
     subs    r3, r2
-    ble    .LC1
-.LC0:
+    ble    .LC_ramfunc_copy_end
+.LC_ramfunc_copy_start:
     subs    r3, #4
     ldr    r0, [r1, r3]
     str    r0, [r2, r3]
-    bgt    .LC0
-.LC1:
-#endif
-#ifdef __STARTUP_INITIALIZE_NONCACHEDATA
-    ldr    r2, =__noncachedata_start__
-    ldr    r3, =__noncachedata_init_end__
-#if 1
-.LC2:
+    bgt    .LC_ramfunc_copy_start
+.LC_ramfunc_copy_end:
+#else  /* code size implemenation */
+.LC_ramfunc_copy_start:
     cmp     r2, r3
     ittt    lt
     ldrlt   r0, [r1], #4
     strlt   r0, [r2], #4
-    blt    .LC2
-#else
+    blt    .LC_ramfunc_copy_start
+#endif
+#endif /* __STARTUP_INITIALIZE_RAMFUNCTION */
+#ifdef __STARTUP_INITIALIZE_NONCACHEDATA
+    ldr    r2, =__noncachedata_start__
+    ldr    r3, =__noncachedata_init_end__
+#ifdef __PERFORMANCE_IMPLEMENTATION
+/* Here are two copies of loop implementations. First one favors performance
+ * and the second one favors code size. Default uses the second one.
+ * Define macro "__PERFORMANCE_IMPLEMENTATION" in project to use the first one */
     subs    r3, r2
     ble    .LC3
 .LC2:
@@ -384,6 +377,13 @@ Reset_Handler:
     str    r0, [r2, r3]
     bgt    .LC2
 .LC3:
+#else  /* code size implemenation */
+.LC2:
+    cmp     r2, r3
+    ittt    lt
+    ldrlt   r0, [r1], #4
+    strlt   r0, [r2], #4
+    blt    .LC2
 #endif
 /* zero inited ncache section initialization */
     ldr r3, =__noncachedata_end__
@@ -484,15 +484,6 @@ SysTick_Handler:
     bx    r0
     .size SysTick_Handler, . - SysTick_Handler
 
-    .align 1
-    .thumb_func
-    .weak NMI_WAKEUP_IRQHandler
-    .type NMI_WAKEUP_IRQHandler, %function
-NMI_WAKEUP_IRQHandler:
-    ldr   r0,=NMI_WAKEUP_IRQHandler
-    bx    r0
-    .size NMI_WAKEUP_IRQHandler, . - NMI_WAKEUP_IRQHandler
-
     .align 1
     .thumb_func
     .weak DMA0_DMA16_IRQHandler
@@ -991,10 +982,10 @@ ENET_1588_Timer_IRQHandler:
     def_irq_handler    SAI3_RX_DriverIRQHandler
     def_irq_handler    SAI3_TX_DriverIRQHandler
     def_irq_handler    SPDIF_DriverIRQHandler
-    def_irq_handler    ANATOP_EVENT0_IRQHandler
-    def_irq_handler    ANATOP_EVENT1_IRQHandler
-    def_irq_handler    ANATOP_TAMP_LOW_HIGH_IRQHandler
-    def_irq_handler    ANATOP_TEMP_PANIC_IRQHandler
+    def_irq_handler    PMU_EVENT_IRQHandler
+    def_irq_handler    Reserved78_IRQHandler
+    def_irq_handler    TEMP_LOW_HIGH_IRQHandler
+    def_irq_handler    TEMP_PANIC_IRQHandler
     def_irq_handler    USB_PHY1_IRQHandler
     def_irq_handler    USB_PHY2_IRQHandler
     def_irq_handler    ADC1_IRQHandler
@@ -1082,12 +1073,5 @@ ENET_1588_Timer_IRQHandler:
     def_irq_handler    PWM4_2_IRQHandler
     def_irq_handler    PWM4_3_IRQHandler
     def_irq_handler    PWM4_FAULT_IRQHandler
-    def_irq_handler    Reserved168_IRQHandler
-    def_irq_handler    Reserved169_IRQHandler
-    def_irq_handler    Reserved170_IRQHandler
-    def_irq_handler    Reserved171_IRQHandler
-    def_irq_handler    Reserved172_IRQHandler
-    def_irq_handler    Reserved173_IRQHandler
-    def_irq_handler    SJC_ARM_DEBUG_IRQHandler
 
     .end
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/TOOLCHAIN_IAR/MIMXRT1052xxxxx.icf b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/TOOLCHAIN_IAR/MIMXRT1052xxxxx.icf
index 2842fee8d64..aa0a3adfd0c 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/TOOLCHAIN_IAR/MIMXRT1052xxxxx.icf
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/TOOLCHAIN_IAR/MIMXRT1052xxxxx.icf
@@ -7,45 +7,17 @@
 **
 **     Compiler:            IAR ANSI C/C++ Compiler for ARM
 **     Reference manual:    IMXRT1050RM Rev.1, 03/2018
-**     Version:             rev. 0.1, 2017-01-10
-**     Build:               b180509
+**     Version:             rev. 1.0, 2018-09-21
+**     Build:               b180921
 **
 **     Abstract:
 **         Linker file for the IAR ANSI C/C++ Compiler for ARM
 **
-**     The Clear BSD License
 **     Copyright 2016 Freescale Semiconductor, Inc.
 **     Copyright 2016-2018 NXP
 **     All rights reserved.
 **
-**     Redistribution and use in source and binary forms, with or without
-**     modification, are permitted (subject to the limitations in the
-**     disclaimer below) provided that the following conditions are met:
-**
-**     * Redistributions of source code must retain the above copyright
-**       notice, this list of conditions and the following disclaimer.
-**
-**     * Redistributions in binary form must reproduce the above copyright
-**       notice, this list of conditions and the following disclaimer in the
-**       documentation and/or other materials provided with the distribution.
-**
-**     * Neither the name of the copyright holder nor the names of its
-**       contributors may be used to endorse or promote products derived from
-**       this software without specific prior written permission.
-**
-**     NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
-**     GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
-**     HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
-**     WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-**     MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-**     LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-**     CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-**     SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
-**     BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-**     WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
-**     OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
-**     IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**     SPDX-License-Identifier: BSD-3-Clause
 **
 **     http:                 www.nxp.com
 **     mail:                 support@nxp.com
@@ -55,6 +27,14 @@
 
 define symbol __ram_vector_table__ = 1;
 
+if (!isdefinedsymbol(MBED_APP_START)) {
+    define symbol MBED_APP_START = 0x60000000;
+}
+
+if (!isdefinedsymbol(MBED_APP_SIZE)) {
+    define symbol MBED_APP_SIZE = 0x400000;
+}
+
 /* Sizes */
 if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) {
     define symbol MBED_BOOT_STACK_SIZE = 0x400;
@@ -66,11 +46,19 @@ define symbol __heap_size__=0x10000;
 define symbol __ram_vector_table_size__ =  isdefinedsymbol(__ram_vector_table__) ? 0x00000400 : 0;
 define symbol __ram_vector_table_offset__ =  isdefinedsymbol(__ram_vector_table__) ? 0x000003FF : 0;
 
-define symbol m_interrupts_start       = 0x60002000;
-define symbol m_interrupts_end         = 0x600023FF;
+if (!isdefinedsymbol(MBED_APP_COMPILE)) {
+    define symbol m_interrupts_start       = MBED_APP_START + 0x2000;
+    define symbol m_interrupts_end         = MBED_APP_START + 0x23FF;
+
+    define symbol m_text_start             = MBED_APP_START + 0x2400;
+    define symbol m_text_end               = MBED_APP_START + MBED_APP_SIZE - 1;
+} else {
+    define symbol m_interrupts_start       = MBED_APP_START;
+    define symbol m_interrupts_end         = MBED_APP_START + 0x3FF;
 
-define symbol m_text_start             = 0x60002400;
-define symbol m_text_end               = 0x63FFFFFF;
+    define symbol m_text_start             = MBED_APP_START + 0x400;
+    define symbol m_text_end               = MBED_APP_START + MBED_APP_SIZE - 1;
+}
 
 define symbol m_text2_start            = 0x00000000;
 define symbol m_text2_end              = 0x0001FFFF;
@@ -90,11 +78,14 @@ define symbol m_data3_end              = 0x81DFFFFF;
 define symbol m_ncache_start           = 0x81E00000;
 define symbol m_ncache_end             = 0x81FFFFFF;
 
-define exported symbol m_boot_hdr_conf_start = 0x60000000;
-define symbol m_boot_hdr_ivt_start           = 0x60001000;
-define symbol m_boot_hdr_boot_data_start     = 0x60001020;
-define symbol m_boot_hdr_dcd_data_start      = 0x60001030;
+if (!isdefinedsymbol(MBED_APP_COMPILE)) {
+    define exported symbol m_boot_hdr_conf_start = MBED_APP_START;
+    define symbol m_boot_hdr_ivt_start           = MBED_APP_START + 0x1000;
+    define symbol m_boot_hdr_boot_data_start     = MBED_APP_START + 0x1020;
+    define symbol m_boot_hdr_dcd_data_start      = MBED_APP_START + 0x1030;
+}
 
+/* Sizes */
 if (isdefinedsymbol(__stack_size__)) {
   define symbol __size_cstack__        = __stack_size__;
 } else {
@@ -129,24 +120,27 @@ define block HEAP      with alignment = 8, size = __size_heap__     { };
 define block RW        { first readwrite, section m_usb_dma_init_data  };
 define block ZI        with alignment = 32  { first  zi, section m_usb_dma_noninit_data };
 define block NCACHE_VAR with size = 0x200000 , alignment = 0x100000  { section NonCacheable , section NonCacheable.init };
+define block QACCESS_FUNC {section .textrw};
 
-initialize by copy { readwrite, section .textrw };
+initialize by copy { readwrite };
 do not initialize  { section .noinit };
 
 place at address mem: m_interrupts_start    { readonly section .intvec };
 
-place at address mem:m_boot_hdr_conf_start { section .boot_hdr.conf };
-place at address mem:m_boot_hdr_ivt_start { section .boot_hdr.ivt };
-place at address mem:m_boot_hdr_boot_data_start { readonly section .boot_hdr.boot_data };
-place at address mem:m_boot_hdr_dcd_data_start { readonly section .boot_hdr.dcd_data };
+if (!isdefinedsymbol(MBED_APP_COMPILE)) {
+    place at address mem:m_boot_hdr_conf_start { section .boot_hdr.conf };
+    place at address mem:m_boot_hdr_ivt_start { section .boot_hdr.ivt };
+    place at address mem:m_boot_hdr_boot_data_start { readonly section .boot_hdr.boot_data };
+    place at address mem:m_boot_hdr_dcd_data_start { readonly section .boot_hdr.dcd_data };
+    keep{ section .boot_hdr.conf, section .boot_hdr.ivt, section .boot_hdr.boot_data, section .boot_hdr.dcd_data };
+}
 
-keep{ section .boot_hdr.conf, section .boot_hdr.ivt, section .boot_hdr.boot_data, section .boot_hdr.dcd_data };
 
 place in TEXT_region                        { readonly };
-place in DATA3_region                        { block RW };
-place in DATA3_region                        { block ZI };
-place in DATA3_region                        { last block HEAP };
+place in DATA3_region                       { block RW };
+place in DATA3_region                       { block ZI };
+place in DATA3_region                       { last block HEAP };
 place in CSTACK_region                      { block CSTACK };
 place in NCACHE_region                      { block NCACHE_VAR };
-place in TEXT2_region                       { section .textrw};
+place in TEXT2_region                       { block QACCESS_FUNC };
 place in m_interrupts_ram_region            { section m_interrupts_ram };
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/TOOLCHAIN_IAR/startup_MIMXRT1052.S b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/TOOLCHAIN_IAR/startup_MIMXRT1052.S
index 620c96ee709..247f46540ce 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/TOOLCHAIN_IAR/startup_MIMXRT1052.S
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/TOOLCHAIN_IAR/startup_MIMXRT1052.S
@@ -2,44 +2,16 @@
 ;  @file:    startup_MIMXRT1052.s
 ;  @purpose: CMSIS Cortex-M7 Core Device Startup File
 ;            MIMXRT1052
-;  @version: 0.1
-;  @date:    2017-1-10
-;  @build:   b180509
+;  @version: 1.2
+;  @date:    2018-11-27
+;  @build:   b190124
 ; -------------------------------------------------------------------------
 ;
-; The Clear BSD License
 ; Copyright 1997-2016 Freescale Semiconductor, Inc.
-; Copyright 2016-2018 NXP
+; Copyright 2016-2019 NXP
 ; All rights reserved.
 ;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted (subject to the limitations in the
-; disclaimer below) provided that the following conditions are met:
-;
-; * Redistributions of source code must retain the above copyright
-;   notice, this list of conditions and the following disclaimer.
-;
-; * Redistributions in binary form must reproduce the above copyright
-;   notice, this list of conditions and the following disclaimer in the
-;   documentation and/or other materials provided with the distribution.
-;
-; * Neither the name of the copyright holder nor the names of its
-;   contributors may be used to endorse or promote products derived from
-;   this software without specific prior written permission.
-;
-; NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
-; GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
-; HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
-; WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-; MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
-; BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-; WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
-; OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
-; IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+; SPDX-License-Identifier: BSD-3-Clause
 ;
 ; The modules in this file are included in the libraries, and may be replaced
 ; by any user-defined modules that define the PUBLIC symbol _program_start or
@@ -155,10 +127,10 @@ __vector_table_0x1c
         DCD     SAI3_RX_IRQHandler                            ;SAI3 interrupt
         DCD     SAI3_TX_IRQHandler                            ;SAI3 interrupt
         DCD     SPDIF_IRQHandler                              ;SPDIF interrupt
-        DCD     ANATOP_EVENT0_IRQHandler                      ;ANATOP interrupt
-        DCD     ANATOP_EVENT1_IRQHandler                      ;ANATOP interrupt
-        DCD     ANATOP_TAMP_LOW_HIGH_IRQHandler               ;ANATOP interrupt
-        DCD     ANATOP_TEMP_PANIC_IRQHandler                  ;ANATOP interrupt
+        DCD     PMU_EVENT_IRQHandler                          ;Brown-out event interrupt
+        DCD     Reserved78_IRQHandler                         ;Reserved interrupt
+        DCD     TEMP_LOW_HIGH_IRQHandler                      ;TempSensor low/high interrupt
+        DCD     TEMP_PANIC_IRQHandler                         ;TempSensor panic interrupt
         DCD     USB_PHY1_IRQHandler                           ;USBPHY (UTMI0), Interrupt
         DCD     USB_PHY2_IRQHandler                           ;USBPHY (UTMI0), Interrupt
         DCD     ADC1_IRQHandler                               ;ADC1 interrupt
@@ -246,14 +218,14 @@ __vector_table_0x1c
         DCD     PWM4_2_IRQHandler                             ;PWM4 capture 2, compare 2, or reload 0 interrupt
         DCD     PWM4_3_IRQHandler                             ;PWM4 capture 3, compare 3, or reload 0 interrupt
         DCD     PWM4_FAULT_IRQHandler                         ;PWM4 fault or reload error interrupt
-        DCD     Reserved168_IRQHandler                        ;Reserved interrupt
-        DCD     Reserved169_IRQHandler                        ;Reserved interrupt
-        DCD     Reserved170_IRQHandler                        ;Reserved interrupt
-        DCD     Reserved171_IRQHandler                        ;Reserved interrupt
-        DCD     Reserved172_IRQHandler                        ;Reserved interrupt
-        DCD     Reserved173_IRQHandler                        ;Reserved interrupt
-        DCD     SJC_ARM_DEBUG_IRQHandler                      ;SJC ARM debug interrupt
-        DCD     NMI_WAKEUP_IRQHandler                         ;NMI wake up
+        DCD     DefaultISR                                    ;168
+        DCD     DefaultISR                                    ;169
+        DCD     DefaultISR                                    ;170
+        DCD     DefaultISR                                    ;171
+        DCD     DefaultISR                                    ;172
+        DCD     DefaultISR                                    ;173
+        DCD     DefaultISR                                    ;174
+        DCD     DefaultISR                                    ;175
         DCD     DefaultISR                                    ;176
         DCD     DefaultISR                                    ;177
         DCD     DefaultISR                                    ;178
@@ -707,10 +679,10 @@ SPDIF_IRQHandler
         LDR     R0, =SPDIF_DriverIRQHandler
         BX      R0
 
-        PUBWEAK ANATOP_EVENT0_IRQHandler
-        PUBWEAK ANATOP_EVENT1_IRQHandler
-        PUBWEAK ANATOP_TAMP_LOW_HIGH_IRQHandler
-        PUBWEAK ANATOP_TEMP_PANIC_IRQHandler
+        PUBWEAK PMU_EVENT_IRQHandler
+        PUBWEAK Reserved78_IRQHandler
+        PUBWEAK TEMP_LOW_HIGH_IRQHandler
+        PUBWEAK TEMP_PANIC_IRQHandler
         PUBWEAK USB_PHY1_IRQHandler
         PUBWEAK USB_PHY2_IRQHandler
         PUBWEAK ADC1_IRQHandler
@@ -840,14 +812,6 @@ ENET_1588_Timer_IRQHandler
         PUBWEAK PWM4_2_IRQHandler
         PUBWEAK PWM4_3_IRQHandler
         PUBWEAK PWM4_FAULT_IRQHandler
-        PUBWEAK Reserved168_IRQHandler
-        PUBWEAK Reserved169_IRQHandler
-        PUBWEAK Reserved170_IRQHandler
-        PUBWEAK Reserved171_IRQHandler
-        PUBWEAK Reserved172_IRQHandler
-        PUBWEAK Reserved173_IRQHandler
-        PUBWEAK SJC_ARM_DEBUG_IRQHandler
-        PUBWEAK NMI_WAKEUP_IRQHandler
         PUBWEAK DefaultISR
         SECTION .text:CODE:REORDER:NOROOT(1)
 DMA0_DMA16_DriverIRQHandler
@@ -911,10 +875,10 @@ SAI2_DriverIRQHandler
 SAI3_RX_DriverIRQHandler
 SAI3_TX_DriverIRQHandler
 SPDIF_DriverIRQHandler
-ANATOP_EVENT0_IRQHandler
-ANATOP_EVENT1_IRQHandler
-ANATOP_TAMP_LOW_HIGH_IRQHandler
-ANATOP_TEMP_PANIC_IRQHandler
+PMU_EVENT_IRQHandler
+Reserved78_IRQHandler
+TEMP_LOW_HIGH_IRQHandler
+TEMP_PANIC_IRQHandler
 USB_PHY1_IRQHandler
 USB_PHY2_IRQHandler
 ADC1_IRQHandler
@@ -1002,14 +966,6 @@ PWM4_1_IRQHandler
 PWM4_2_IRQHandler
 PWM4_3_IRQHandler
 PWM4_FAULT_IRQHandler
-Reserved168_IRQHandler
-Reserved169_IRQHandler
-Reserved170_IRQHandler
-Reserved171_IRQHandler
-Reserved172_IRQHandler
-Reserved173_IRQHandler
-SJC_ARM_DEBUG_IRQHandler
-NMI_WAKEUP_IRQHandler
 DefaultISR
         B DefaultISR
 
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/fsl_device_registers.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/fsl_device_registers.h
index f546a9df0ee..54caf43ca6c 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/fsl_device_registers.h
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/fsl_device_registers.h
@@ -1,37 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright 2014-2016 Freescale Semiconductor, Inc.
  * Copyright 2016-2018 NXP
  * All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted (subject to the limitations in the
- * disclaimer below) provided that the following conditions are met:
- *
- * * Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in the
- *   documentation and/or other materials provided with the distribution.
- *
- * * Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from
- *   this software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
- * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
- * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
- * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
- * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  *
  */
 
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/system_MIMXRT1052.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/system_MIMXRT1052.c
index c9e37381b8d..477091c3aa6 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/system_MIMXRT1052.c
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/system_MIMXRT1052.c
@@ -5,54 +5,26 @@
 **                          MIMXRT1052DVJ6B
 **                          MIMXRT1052DVL6B
 **
-**     Compilers:           Keil ARM C/C++ Compiler
-**                          Freescale C/C++ for Embedded ARM
+**     Compilers:           Freescale C/C++ for Embedded ARM
 **                          GNU C Compiler
 **                          IAR ANSI C/C++ Compiler for ARM
+**                          Keil ARM C/C++ Compiler
 **                          MCUXpresso Compiler
 **
-**     Reference manual:    IMXRT1050RM Rev.1, 03/2018
-**     Version:             rev. 0.1, 2017-01-10
-**     Build:               b180509
+**     Reference manual:    IMXRT1050RM Rev.2.1, 12/2018
+**     Version:             rev. 1.2, 2018-11-27
+**     Build:               b190329
 **
 **     Abstract:
 **         Provides a system configuration function and a global variable that
 **         contains the system frequency. It configures the device and initializes
 **         the oscillator (PLL) that is part of the microcontroller device.
 **
-**     The Clear BSD License
 **     Copyright 2016 Freescale Semiconductor, Inc.
-**     Copyright 2016-2018 NXP
+**     Copyright 2016-2019 NXP
 **     All rights reserved.
 **
-**     Redistribution and use in source and binary forms, with or without
-**     modification, are permitted (subject to the limitations in the
-**     disclaimer below) provided that the following conditions are met:
-**
-**     * Redistributions of source code must retain the above copyright
-**       notice, this list of conditions and the following disclaimer.
-**
-**     * Redistributions in binary form must reproduce the above copyright
-**       notice, this list of conditions and the following disclaimer in the
-**       documentation and/or other materials provided with the distribution.
-**
-**     * Neither the name of the copyright holder nor the names of its
-**       contributors may be used to endorse or promote products derived from
-**       this software without specific prior written permission.
-**
-**     NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
-**     GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
-**     HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
-**     WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-**     MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-**     LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-**     CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-**     SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
-**     BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-**     WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
-**     OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
-**     IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**     SPDX-License-Identifier: BSD-3-Clause
 **
 **     http:                 www.nxp.com
 **     mail:                 support@nxp.com
@@ -60,14 +32,22 @@
 **     Revisions:
 **     - rev. 0.1 (2017-01-10)
 **         Initial version.
+**     - rev. 1.0 (2018-09-21)
+**         Update interrupt vector table and dma request source.
+**         Update register BEE_ADDR_OFFSET1's bitfield name to ADDR_OFFSET1.
+**         Split GPIO_COMBINED_IRQS to GPIO_COMBINED_LOW_IRQS and GPIO_COMBINED_HIGH_IRQS.
+**     - rev. 1.1 (2018-11-16)
+**         Update header files to align with IMXRT1050RM Rev.1.
+**     - rev. 1.2 (2018-11-27)
+**         Update header files to align with IMXRT1050RM Rev.2.1.
 **
 ** ###################################################################
 */
 
 /*!
  * @file MIMXRT1052
- * @version 0.1
- * @date 2017-01-10
+ * @version 1.2
+ * @date 2018-11-27
  * @brief Device specific configuration file for MIMXRT1052 (implementation file)
  *
  * Provides a system configuration function and a global variable that contains
@@ -177,6 +157,7 @@ void SystemCoreClockUpdate (void) {
             case CCM_CBCMR_PERIPH_CLK2_SEL(2U):
                 freq = (((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK) >> CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT) == 0U) ?
                    CPU_XTAL_CLK_HZ : CPU_CLK1_HZ;
+                break;
 
             case CCM_CBCMR_PERIPH_CLK2_SEL(3U):
             default:
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/system_MIMXRT1052.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/system_MIMXRT1052.h
index 8d9f2073d80..74941f9fbda 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/system_MIMXRT1052.h
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/system_MIMXRT1052.h
@@ -5,54 +5,26 @@
 **                          MIMXRT1052DVJ6B
 **                          MIMXRT1052DVL6B
 **
-**     Compilers:           Keil ARM C/C++ Compiler
-**                          Freescale C/C++ for Embedded ARM
+**     Compilers:           Freescale C/C++ for Embedded ARM
 **                          GNU C Compiler
 **                          IAR ANSI C/C++ Compiler for ARM
+**                          Keil ARM C/C++ Compiler
 **                          MCUXpresso Compiler
 **
-**     Reference manual:    IMXRT1050RM Rev.1, 03/2018
-**     Version:             rev. 0.1, 2017-01-10
-**     Build:               b180509
+**     Reference manual:    IMXRT1050RM Rev.2.1, 12/2018
+**     Version:             rev. 1.2, 2018-11-27
+**     Build:               b181205
 **
 **     Abstract:
 **         Provides a system configuration function and a global variable that
 **         contains the system frequency. It configures the device and initializes
 **         the oscillator (PLL) that is part of the microcontroller device.
 **
-**     The Clear BSD License
 **     Copyright 2016 Freescale Semiconductor, Inc.
 **     Copyright 2016-2018 NXP
 **     All rights reserved.
 **
-**     Redistribution and use in source and binary forms, with or without
-**     modification, are permitted (subject to the limitations in the
-**     disclaimer below) provided that the following conditions are met:
-**
-**     * Redistributions of source code must retain the above copyright
-**       notice, this list of conditions and the following disclaimer.
-**
-**     * Redistributions in binary form must reproduce the above copyright
-**       notice, this list of conditions and the following disclaimer in the
-**       documentation and/or other materials provided with the distribution.
-**
-**     * Neither the name of the copyright holder nor the names of its
-**       contributors may be used to endorse or promote products derived from
-**       this software without specific prior written permission.
-**
-**     NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
-**     GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
-**     HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
-**     WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-**     MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-**     LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-**     CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-**     SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
-**     BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-**     WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
-**     OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
-**     IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**     SPDX-License-Identifier: BSD-3-Clause
 **
 **     http:                 www.nxp.com
 **     mail:                 support@nxp.com
@@ -60,14 +32,22 @@
 **     Revisions:
 **     - rev. 0.1 (2017-01-10)
 **         Initial version.
+**     - rev. 1.0 (2018-09-21)
+**         Update interrupt vector table and dma request source.
+**         Update register BEE_ADDR_OFFSET1's bitfield name to ADDR_OFFSET1.
+**         Split GPIO_COMBINED_IRQS to GPIO_COMBINED_LOW_IRQS and GPIO_COMBINED_HIGH_IRQS.
+**     - rev. 1.1 (2018-11-16)
+**         Update header files to align with IMXRT1050RM Rev.1.
+**     - rev. 1.2 (2018-11-27)
+**         Update header files to align with IMXRT1050RM Rev.2.1.
 **
 ** ###################################################################
 */
 
 /*!
  * @file MIMXRT1052
- * @version 0.1
- * @date 2017-01-10
+ * @version 1.2
+ * @date 2018-11-27
  * @brief Device specific configuration file for MIMXRT1052 (header file)
  *
  * Provides a system configuration function and a global variable that contains
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_adc.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_adc.c
index d3cdb6f645f..b2fa29b7185 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_adc.c
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_adc.c
@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2016, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
  * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
  *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include "fsl_adc.h"
@@ -39,7 +13,6 @@
 #define FSL_COMPONENT_ID "platform.drivers.adc_12b1msps_sar"
 #endif
 
-
 /*******************************************************************************
  * Prototypes
  ******************************************************************************/
@@ -56,8 +29,10 @@ static uint32_t ADC_GetInstance(ADC_Type *base);
 /*! @brief Pointers to ADC bases for each instance. */
 static ADC_Type *const s_adcBases[] = ADC_BASE_PTRS;
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
 /*! @brief Pointers to ADC clocks for each instance. */
 static const clock_ip_name_t s_adcClocks[] = ADC_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
 /*******************************************************************************
  * Code
@@ -80,14 +55,22 @@ static uint32_t ADC_GetInstance(ADC_Type *base)
     return instance;
 }
 
+/*!
+ * brief Initialize the ADC module.
+ *
+ * param base ADC peripheral base address.
+ * param config Pointer to "adc_config_t" structure.
+ */
 void ADC_Init(ADC_Type *base, const adc_config_t *config)
 {
     assert(NULL != config);
 
     uint32_t tmp32;
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* Enable the clock. */
     CLOCK_EnableClock(s_adcClocks[ADC_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
     /* ADCx_CFG */
     tmp32 = base->CFG & (ADC_CFG_AVGS_MASK | ADC_CFG_ADTRG_MASK); /* Reserve AVGS and ADTRG bits. */
     tmp32 |= ADC_CFG_REFSEL(config->referenceVoltageSource) | ADC_CFG_ADSTS(config->samplePeriodMode) |
@@ -123,33 +106,90 @@ void ADC_Init(ADC_Type *base, const adc_config_t *config)
     base->GC = tmp32;
 }
 
+/*!
+ * brief De-initializes the ADC module.
+ *
+ * param base ADC peripheral base address.
+ */
 void ADC_Deinit(ADC_Type *base)
 {
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* Disable the clock. */
     CLOCK_DisableClock(s_adcClocks[ADC_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }
 
+/*!
+ * brief Gets an available pre-defined settings for the converter's configuration.
+ *
+ * This function initializes the converter configuration structure with available settings. The default values are:
+ * code
+ *  config->enableAsynchronousClockOutput = true;
+ *  config->enableOverWrite =               false;
+ *  config->enableContinuousConversion =    false;
+ *  config->enableHighSpeed =               false;
+ *  config->enableLowPower =                false;
+ *  config->enableLongSample =              false;
+ *  config->referenceVoltageSource =        kADC_ReferenceVoltageSourceAlt0;
+ *  config->samplePeriodMode =              kADC_SamplePeriod2or12Clocks;
+ *  config->clockSource =                   kADC_ClockSourceAD;
+ *  config->clockDriver =                   kADC_ClockDriver1;
+ *  config->resolution =                    kADC_Resolution12Bit;
+ * endcode
+ * param base   ADC peripheral base address.
+ * param config Pointer to the configuration structure.
+ */
 void ADC_GetDefaultConfig(adc_config_t *config)
 {
     assert(NULL != config);
 
+    /* Initializes the configure structure to zero. */
+    memset(config, 0, sizeof(*config));
+
     config->enableAsynchronousClockOutput = true;
-    config->enableOverWrite = false;
-    config->enableContinuousConversion = false;
-    config->enableHighSpeed = false;
-    config->enableLowPower = false;
-    config->enableLongSample = false;
-    config->referenceVoltageSource = kADC_ReferenceVoltageSourceAlt0;
-    config->samplePeriodMode = kADC_SamplePeriod2or12Clocks;
-    config->clockSource = kADC_ClockSourceAD;
-    config->clockDriver = kADC_ClockDriver1;
-    config->resolution = kADC_Resolution12Bit;
+    config->enableOverWrite               = false;
+    config->enableContinuousConversion    = false;
+    config->enableHighSpeed               = false;
+    config->enableLowPower                = false;
+    config->enableLongSample              = false;
+    config->referenceVoltageSource        = kADC_ReferenceVoltageSourceAlt0;
+    config->samplePeriodMode              = kADC_SamplePeriod2or12Clocks;
+    config->clockSource                   = kADC_ClockSourceAD;
+    config->clockDriver                   = kADC_ClockDriver1;
+    config->resolution                    = kADC_Resolution12Bit;
 }
 
+/*!
+ * brief Configures the conversion channel.
+ *
+ * This operation triggers the conversion when in software trigger mode. When in hardware trigger mode, this API
+ * configures the channel while the external trigger source helps to trigger the conversion.
+ *
+ * Note that the "Channel Group" has a detailed description.
+ * To allow sequential conversions of the ADC to be triggered by internal peripherals, the ADC has more than one
+ * group of status and control registers, one for each conversion. The channel group parameter indicates which group of
+ * registers are used, for example channel group 0 is for Group A registers and channel group 1 is for Group B
+ * registers. The
+ * channel groups are used in a "ping-pong" approach to control the ADC operation.  At any point, only one of
+ * the channel groups is actively controlling ADC conversions. The channel group 0 is used for both software and
+ * hardware
+ * trigger modes. Channel groups 1 and greater indicate potentially multiple channel group registers for
+ * use only in hardware trigger mode. See the chip configuration information in the appropriate MCU reference manual
+ * about the
+ * number of SC1n registers (channel groups) specific to this device.  None of the channel groups 1 or greater are used
+ * for software trigger operation. Therefore, writing to these channel groups does not initiate a new conversion.
+ * Updating the channel group 0 while a different channel group is actively controlling a conversion is allowed and
+ * vice versa. Writing any of the channel group registers while that specific channel group is actively controlling a
+ * conversion aborts the current conversion.
+ *
+ * param base          ADC peripheral base address.
+ * param channelGroup  Channel group index.
+ * param config        Pointer to the "adc_channel_config_t" structure for the conversion channel.
+ */
 void ADC_SetChannelConfig(ADC_Type *base, uint32_t channelGroup, const adc_channel_config_t *config)
 {
     assert(NULL != config);
-    assert(channelGroup < ADC_HC_COUNT);
+    assert(channelGroup < FSL_FEATURE_ADC_CONVERSION_CONTROL_COUNT);
 
     uint32_t tmp32;
 
@@ -168,6 +208,19 @@ void ADC_SetChannelConfig(ADC_Type *base, uint32_t channelGroup, const adc_chann
  *  3. Check the status of CALF bit in ADC_GS and the CAL bit in ADC_GC.
  *  4. When CAL bit becomes '0' then check the CALF status and COCO[0] bit status.
  */
+/*!
+ * brief  Automates the hardware calibration.
+ *
+ * This auto calibration helps to adjust the plus/minus side gain automatically.
+ * Execute the calibration before using the converter. Note that the software trigger should be used
+ * during calibration.
+ *
+ * param  base ADC peripheral base address.
+ *
+ * return                 Execution status.
+ * retval kStatus_Success Calibration is done successfully.
+ * retval kStatus_Fail    Calibration has failed.
+ */
 status_t ADC_DoAutoCalibration(ADC_Type *base)
 {
     status_t status = kStatus_Success;
@@ -222,6 +275,12 @@ status_t ADC_DoAutoCalibration(ADC_Type *base)
     return status;
 }
 
+/*!
+ * brief Set user defined offset.
+ *
+ * param base   ADC peripheral base address.
+ * param config Pointer to "adc_offest_config_t" structure.
+ */
 void ADC_SetOffsetConfig(ADC_Type *base, const adc_offest_config_t *config)
 {
     assert(NULL != config);
@@ -236,6 +295,19 @@ void ADC_SetOffsetConfig(ADC_Type *base, const adc_offest_config_t *config)
     base->OFS = tmp32;
 }
 
+/*!
+ * brief Configures the hardware compare mode.
+ *
+ * The hardware compare mode provides a way to process the conversion result automatically by using hardware. Only the
+ * result
+ * in the compare range is available. To compare the range, see "adc_hardware_compare_mode_t" or the appopriate
+ * reference
+ * manual for more information.
+ *
+ * param base ADC peripheral base address.
+ * param Pointer to "adc_hardware_compare_config_t" structure.
+ *
+ */
 void ADC_SetHardwareCompareConfig(ADC_Type *base, const adc_hardware_compare_config_t *config)
 {
     uint32_t tmp32;
@@ -269,10 +341,20 @@ void ADC_SetHardwareCompareConfig(ADC_Type *base, const adc_hardware_compare_con
     base->GC = tmp32;
 
     /* Load the compare values. */
-    tmp32 = ADC_CV_CV1(config->value1) | ADC_CV_CV2(config->value2);
+    tmp32    = ADC_CV_CV1(config->value1) | ADC_CV_CV2(config->value2);
     base->CV = tmp32;
 }
 
+/*!
+ * brief Configures the hardware average mode.
+ *
+ * The hardware average mode provides a way to process the conversion result automatically by using hardware. The
+ * multiple
+ * conversion results are accumulated and averaged internally making them easier to read.
+ *
+ * param base ADC peripheral base address.
+ * param mode Setting the hardware average mode. See "adc_hardware_average_mode_t".
+ */
 void ADC_SetHardwareAverageConfig(ADC_Type *base, adc_hardware_average_mode_t mode)
 {
     uint32_t tmp32;
@@ -290,6 +372,12 @@ void ADC_SetHardwareAverageConfig(ADC_Type *base, adc_hardware_average_mode_t mo
     }
 }
 
+/*!
+ * brief Clears the converter's status falgs.
+ *
+ * param base ADC peripheral base address.
+ * param mask Mask value for the cleared flags. See "adc_status_flags_t".
+ */
 void ADC_ClearStatusFlags(ADC_Type *base, uint32_t mask)
 {
     uint32_t tmp32 = 0;
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_adc.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_adc.h
index 8b46fb1ba5c..645e22e3f63 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_adc.h
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_adc.h
@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2016, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
  * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
  *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #ifndef _FSL_ADC_H_
@@ -43,20 +17,20 @@
  */
 
 /*******************************************************************************
-* Definitions
-******************************************************************************/
+ * Definitions
+ ******************************************************************************/
 /*! @brief ADC driver version */
-#define FSL_ADC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */
+#define FSL_ADC_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) /*!< Version 2.0.2. */
 
 /*!
  * @brief Converter's status flags.
  */
 typedef enum _adc_status_flags
 {
-    kADC_ConversionActiveFlag = ADC_GS_ADACT_MASK, /*!< Conversion is active,not support w1c. */
-    kADC_CalibrationFailedFlag = ADC_GS_CALF_MASK, /*!< Calibration is failed,support w1c. */
+    kADC_ConversionActiveFlag  = ADC_GS_ADACT_MASK, /*!< Conversion is active,not support w1c. */
+    kADC_CalibrationFailedFlag = ADC_GS_CALF_MASK,  /*!< Calibration is failed,support w1c. */
     kADC_AsynchronousWakeupInterruptFlag =
-        ADC_GS_AWKST_MASK, /*!< Asynchronous wakeup interrupt occured, support w1c. */
+        ADC_GS_AWKST_MASK, /*!< Asynchronous wakeup interrupt occurred, support w1c. */
 } adc_status_flags_t;
 
 /*!
@@ -95,7 +69,7 @@ typedef enum _adc_sample_period_mode
  */
 typedef enum _adc_clock_source
 {
-    kADC_ClockSourceIPG = 0U,     /*!< Select IPG clock to generate ADCK. */
+    kADC_ClockSourceIPG     = 0U, /*!< Select IPG clock to generate ADCK. */
     kADC_ClockSourceIPGDiv2 = 1U, /*!< Select IPG clock divided by 2 to generate ADCK. */
 #if !(defined(FSL_FEATURE_ADC_SUPPORT_ALTCLK_REMOVE) && FSL_FEATURE_ADC_SUPPORT_ALTCLK_REMOVE)
     kADC_ClockSourceALT = 2U, /*!< Select alternate clock to generate ADCK. */
@@ -119,7 +93,7 @@ typedef enum _adc_clock_drvier
  */
 typedef enum _adc_resolution
 {
-    kADC_Resolution8Bit = 0U,  /*!< Single End 8-bit resolution. */
+    kADC_Resolution8Bit  = 0U, /*!< Single End 8-bit resolution. */
     kADC_Resolution10Bit = 1U, /*!< Single End 10-bit resolution. */
     kADC_Resolution12Bit = 2U, /*!< Single End 12-bit resolution. */
 } adc_resolution_t;
@@ -146,10 +120,10 @@ typedef enum _adc_hardware_compare_mode
  */
 typedef enum _adc_hardware_average_mode
 {
-    kADC_HardwareAverageCount4 = 0U,   /*!< For hardware average with 4 samples. */
-    kADC_HardwareAverageCount8 = 1U,   /*!< For hardware average with 8 samples. */
-    kADC_HardwareAverageCount16 = 2U,  /*!< For hardware average with 16 samples. */
-    kADC_HardwareAverageCount32 = 3U,  /*!< For hardware average with 32 samples. */
+    kADC_HardwareAverageCount4   = 0U, /*!< For hardware average with 4 samples. */
+    kADC_HardwareAverageCount8   = 1U, /*!< For hardware average with 8 samples. */
+    kADC_HardwareAverageCount16  = 2U, /*!< For hardware average with 16 samples. */
+    kADC_HardwareAverageCount32  = 3U, /*!< For hardware average with 32 samples. */
     kADC_HardwareAverageDiasable = 4U, /*!< Disable the hardware average function. */
 } adc_hardware_average_mode_t;
 
@@ -214,8 +188,8 @@ typedef struct _adc_channel_config
     bool enableInterruptOnConversionCompleted; /*!< Generate an interrupt request once the conversion is completed. */
 } adc_channel_config_t;
 /*******************************************************************************
-* API
-******************************************************************************/
+ * API
+ ******************************************************************************/
 #if defined(__cplusplus)
 extern "C" {
 #endif
@@ -301,7 +275,7 @@ void ADC_SetChannelConfig(ADC_Type *base, uint32_t channelGroup, const adc_chann
  */
 static inline uint32_t ADC_GetChannelConversionValue(ADC_Type *base, uint32_t channelGroup)
 {
-    assert(channelGroup < ADC_R_COUNT);
+    assert(channelGroup < FSL_FEATURE_ADC_CONVERSION_CONTROL_COUNT);
 
     return base->R[channelGroup];
 }
@@ -325,7 +299,7 @@ static inline uint32_t ADC_GetChannelConversionValue(ADC_Type *base, uint32_t ch
  */
 static inline uint32_t ADC_GetChannelStatusFlags(ADC_Type *base, uint32_t channelGroup)
 {
-    assert(channelGroup < ADC_HC_COUNT);
+    assert(channelGroup < FSL_FEATURE_ADC_CONVERSION_CONTROL_COUNT);
 
     /* If flag is set,return 1,otherwise, return 0. */
     return (((base->HS) & (1U << channelGroup)) >> channelGroup);
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_adc_etc.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_adc_etc.c
index f17dcc3ba7a..cdd5db1f9dd 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_adc_etc.c
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_adc_etc.c
@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2016, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
  * All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- * that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include "fsl_adc_etc.h"
@@ -55,16 +29,17 @@ static uint32_t ADC_ETC_GetInstance(ADC_ETC_Type *base);
  ******************************************************************************/
 /*! @brief Pointers to ADC_ETC bases for each instance. */
 static ADC_ETC_Type *const s_adcetcBases[] = ADC_ETC_BASE_PTRS;
-
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
 /*! @brief Pointers to ADC_ETC clocks for each instance. */
 static const clock_ip_name_t s_adcetcClocks[] = ADC_ETC_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
 /*******************************************************************************
  * Code
  ******************************************************************************/
 static uint32_t ADC_ETC_GetInstance(ADC_ETC_Type *base)
 {
-    uint32_t instance = 0U;
+    uint32_t instance         = 0U;
     uint32_t adcetcArrayCount = (sizeof(s_adcetcBases) / sizeof(s_adcetcBases[0]));
 
     /* Find the instance index from base address mappings. */
@@ -80,6 +55,12 @@ static uint32_t ADC_ETC_GetInstance(ADC_ETC_Type *base)
 }
 #endif /* ADC_ETC_CLOCKS */
 
+/*!
+ * brief Initialize the ADC_ETC module.
+ *
+ * param base ADC_ETC peripheral base address.
+ * param config Pointer to "adc_etc_config_t" structure.
+ */
 void ADC_ETC_Init(ADC_ETC_Type *base, const adc_etc_config_t *config)
 {
     assert(NULL != config);
@@ -119,6 +100,11 @@ void ADC_ETC_Init(ADC_ETC_Type *base, const adc_etc_config_t *config)
     base->CTRL = tmp32;
 }
 
+/*!
+ * brief De-Initialize the ADC_ETC module.
+ *
+ * param base ADC_ETC peripheral base address.
+ */
 void ADC_ETC_Deinit(ADC_ETC_Type *base)
 {
     /* Do software reset to clear all logical. */
@@ -132,9 +118,27 @@ void ADC_ETC_Deinit(ADC_ETC_Type *base)
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }
 
+/*!
+ * brief Gets an available pre-defined settings for the ADC_ETC's configuration.
+ * This function initializes the ADC_ETC's configuration structure with available settings. The default values are:
+ * code
+ *   config->enableTSCBypass = true;
+ *   config->enableTSC0Trigger = false;
+ *   config->enableTSC1Trigger = false;
+ *   config->TSC0triggerPriority = 0U;
+ *   config->TSC1triggerPriority = 0U;
+ *   config->clockPreDivider = 0U;
+ *   config->XBARtriggerMask = 0U;
+ * endCode
+ *
+ * param config Pointer to "adc_etc_config_t" structure.
+ */
 void ADC_ETC_GetDefaultConfig(adc_etc_config_t *config)
 {
-    config->enableTSCBypass = true;
+    /* Initializes the configure structure to zero. */
+    memset(config, 0, sizeof(*config));
+
+    config->enableTSCBypass   = true;
     config->enableTSC0Trigger = false;
     config->enableTSC1Trigger = false;
 #if defined(FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL) && FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL
@@ -142,10 +146,17 @@ void ADC_ETC_GetDefaultConfig(adc_etc_config_t *config)
 #endif /*FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL*/
     config->TSC0triggerPriority = 0U;
     config->TSC1triggerPriority = 0U;
-    config->clockPreDivider = 0U;
-    config->XBARtriggerMask = 0U;
+    config->clockPreDivider     = 0U;
+    config->XBARtriggerMask     = 0U;
 }
 
+/*!
+ * brief Set the external XBAR trigger configuration.
+ *
+ * param base ADC_ETC peripheral base address.
+ * param triggerGroup Trigger group index.
+ * param config Pointer to "adc_etc_trigger_config_t" structure.
+ */
 void ADC_ETC_SetTriggerConfig(ADC_ETC_Type *base, uint32_t triggerGroup, const adc_etc_trigger_config_t *config)
 {
     assert(triggerGroup < ADC_ETC_TRIGn_CTRL_COUNT);
@@ -172,6 +183,16 @@ void ADC_ETC_SetTriggerConfig(ADC_ETC_Type *base, uint32_t triggerGroup, const a
     base->TRIG[triggerGroup].TRIGn_COUNTER = tmp32;
 }
 
+/*!
+ * brief Set the external XBAR trigger chain configuration.
+ * For example, if triggerGroup is set to 0U and chainGroup is set to 1U, which means Trigger0 source's chain1 would be
+ * configurated.
+ *
+ * param base ADC_ETC peripheral base address.
+ * param triggerGroup Trigger group index. Available number is 0~7.
+ * param chainGroup Trigger chain group index. Available number is 0~7.
+ * param config Pointer to "adc_etc_trigger_chain_config_t" structure.
+ */
 void ADC_ETC_SetTriggerChainConfig(ADC_ETC_Type *base,
                                    uint32_t triggerGroup,
                                    uint32_t chainGroup,
@@ -262,6 +283,14 @@ void ADC_ETC_SetTriggerChainConfig(ADC_ETC_Type *base,
     }
 }
 
+/*!
+ * brief Gets the interrupt status flags of external XBAR and TSC triggers.
+ *
+ * param base ADC_ETC peripheral base address.
+ * param sourceIndex trigger source index.
+ *
+ * return Status flags mask of trigger. Refer to "_adc_etc_status_flag_mask".
+ */
 uint32_t ADC_ETC_GetInterruptStatusFlags(ADC_ETC_Type *base, adc_etc_external_trigger_source_t sourceIndex)
 {
     uint32_t tmp32 = 0U;
@@ -289,6 +318,13 @@ uint32_t ADC_ETC_GetInterruptStatusFlags(ADC_ETC_Type *base, adc_etc_external_tr
     return tmp32;
 }
 
+/*!
+ * brief Clears the ADC_ETC's interrupt status falgs.
+ *
+ * param base ADC_ETC peripheral base address.
+ * param sourceIndex trigger source index.
+ * param mask Status flags mask of trigger. Refer to "_adc_etc_status_flag_mask".
+ */
 void ADC_ETC_ClearInterruptStatusFlags(ADC_ETC_Type *base, adc_etc_external_trigger_source_t sourceIndex, uint32_t mask)
 {
     if (0U != (mask & kADC_ETC_Done0StatusFlagMask)) /* Write 1 to clear DONE0 status flags. */
@@ -309,6 +345,16 @@ void ADC_ETC_ClearInterruptStatusFlags(ADC_ETC_Type *base, adc_etc_external_trig
     }
 }
 
+/*!
+ * brief Get ADC conversion result from external XBAR sources.
+ * For example, if triggerGroup is set to 0U and chainGroup is set to 1U, which means the API would
+ * return Trigger0 source's chain1 conversion result.
+ *
+ * param base ADC_ETC peripheral base address.
+ * param triggerGroup Trigger group index. Available number is 0~7.
+ * param chainGroup Trigger chain group index. Available number is 0~7.
+ * return ADC conversion result value.
+ */
 uint32_t ADC_ETC_GetADCConversionValue(ADC_ETC_Type *base, uint32_t triggerGroup, uint32_t chainGroup)
 {
     assert(triggerGroup < ADC_ETC_TRIGn_RESULT_1_0_COUNT);
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_adc_etc.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_adc_etc.h
index 06cb5675b06..4b43f1aa157 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_adc_etc.h
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_adc_etc.h
@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2016, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
  * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
  *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #ifndef _FSL_ADC_ETC_H_
@@ -43,16 +17,16 @@
  */
 
 /*******************************************************************************
-* Definitions
-******************************************************************************/
+ * Definitions
+ ******************************************************************************/
 /*! @brief ADC_ETC driver version */
-#define FSL_ADC_ETC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */
+#define FSL_ADC_ETC_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) /*!< Version 2.0.1. */
 /*! @brief The mask of status flags cleared by writing 1. */
 #define ADC_ETC_DMA_CTRL_TRGn_REQ_MASK 0xFF0000U
 
 /*!
-* @brief ADC_ETC customized status flags mask.
-*/
+ * @brief ADC_ETC customized status flags mask.
+ */
 enum _adc_etc_status_flag_mask
 {
     kADC_ETC_Done0StatusFlagMask = 1U,
@@ -62,8 +36,8 @@ enum _adc_etc_status_flag_mask
 };
 
 /*!
-* @brief External triggers sources.
-*/
+ * @brief External triggers sources.
+ */
 typedef enum _adc_etc_external_trigger_source
 {
     /* External XBAR sources. Support HW or SW mode. */
@@ -81,11 +55,11 @@ typedef enum _adc_etc_external_trigger_source
 } adc_etc_external_trigger_source_t;
 
 /*!
-* @brief Interrupt enable/disable mask.
-*/
+ * @brief Interrupt enable/disable mask.
+ */
 typedef enum _adc_etc_interrupt_enable
 {
-    kADC_ETC_InterruptDisable = 0U,     /* Disable the ADC_ETC interrupt. */
+    kADC_ETC_InterruptDisable     = 0U, /* Disable the ADC_ETC interrupt. */
     kADC_ETC_Done0InterruptEnable = 1U, /* Enable the DONE0 interrupt when ADC conversions complete. */
     kADC_ETC_Done1InterruptEnable = 2U, /* Enable the DONE1 interrupt when ADC conversions complete. */
     kADC_ETC_Done2InterruptEnable = 3U, /* Enable the DONE2 interrupt when ADC conversions complete. */
@@ -93,12 +67,13 @@ typedef enum _adc_etc_interrupt_enable
 
 #if defined(FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL) && FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL
 /*!
-* @brief DMA mode selection.
-*/
+ * @brief DMA mode selection.
+ */
 typedef enum _adc_etc_dma_mode_selection
 {
-    kADC_ETC_TrigDMAWithLatchedSignal = 0U,  /* Trig DMA_REQ with latched signal, REQ will be cleared when ACK and source request cleared. */
-    kADC_ETC_TrigDMAWithPulsedSignal = 1U,   /* Trig DMA_REQ with pulsed signal, REQ will be cleared by ACK only. */
+    kADC_ETC_TrigDMAWithLatchedSignal =
+        0U, /* Trig DMA_REQ with latched signal, REQ will be cleared when ACK and source request cleared. */
+    kADC_ETC_TrigDMAWithPulsedSignal = 1U, /* Trig DMA_REQ with pulsed signal, REQ will be cleared by ACK only. */
 } adc_etc_dma_mode_selection_t;
 #endif /*FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL*/
 
@@ -107,26 +82,26 @@ typedef enum _adc_etc_dma_mode_selection
  */
 typedef struct _adc_etc_config
 {
-    bool enableTSCBypass;         /* If bypass TSC, TSC would trigger ADC directly.
-                                     Otherwise TSC would trigger ADC through ADC_ETC. */
-    bool enableTSC0Trigger;       /* Enable external TSC0 trigger. It is valid when enableTSCBypass = false. */
-    bool enableTSC1Trigger;       /* Enable external TSC1 trigger. It is valid when enableTSCBypass = false.*/
+    bool enableTSCBypass;   /* If bypass TSC, TSC would trigger ADC directly.
+                               Otherwise TSC would trigger ADC through ADC_ETC. */
+    bool enableTSC0Trigger; /* Enable external TSC0 trigger. It is valid when enableTSCBypass = false. */
+    bool enableTSC1Trigger; /* Enable external TSC1 trigger. It is valid when enableTSCBypass = false.*/
 #if defined(FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL) && FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL
-    adc_etc_dma_mode_selection_t dmaMode; /* Select the ADC_ETC DMA mode. */ 
-#endif /*FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL*/
-    uint32_t TSC0triggerPriority; /* External TSC0 trigger priority, 7 is highest, 0 is lowest. */
-    uint32_t TSC1triggerPriority; /* External TSC1 trigger priority, 7 is highest, 0 is lowest. */
-    uint32_t clockPreDivider;     /* Pre-divider for trig delay and interval. Available range is 0-255.
-                                    Clock would be divided by (clockPreDivider+1). */
-    uint32_t XBARtriggerMask;     /* Enable the corresponding trigger source. Available range is trigger0:0x01 to
-                                     trigger7:0x80
-                                     For example, XBARtriggerMask = 0x7U, which means trigger0, trigger1 and trigger2 is
-                                     enabled. */
+    adc_etc_dma_mode_selection_t dmaMode; /* Select the ADC_ETC DMA mode. */
+#endif                                    /*FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL*/
+    uint32_t TSC0triggerPriority;         /* External TSC0 trigger priority, 7 is highest, 0 is lowest. */
+    uint32_t TSC1triggerPriority;         /* External TSC1 trigger priority, 7 is highest, 0 is lowest. */
+    uint32_t clockPreDivider;             /* Pre-divider for trig delay and interval. Available range is 0-255.
+                                            Clock would be divided by (clockPreDivider+1). */
+    uint32_t XBARtriggerMask; /* Enable the corresponding trigger source. Available range is trigger0:0x01 to
+                                 trigger7:0x80
+                                 For example, XBARtriggerMask = 0x7U, which means trigger0, trigger1 and trigger2 is
+                                 enabled. */
 } adc_etc_config_t;
 
 /*!
-* @brief ADC_ETC trigger chain configuration.
-*/
+ * @brief ADC_ETC trigger chain configuration.
+ */
 typedef struct _adc_etc_trigger_chain_config
 {
     bool enableB2BMode;           /* Enable ADC_ETC BackToBack mode. when not enabled B2B mode,
@@ -137,8 +112,8 @@ typedef struct _adc_etc_trigger_chain_config
 } adc_etc_trigger_chain_config_t;
 
 /*!
-* @brief ADC_ETC trigger configuration.
-*/
+ * @brief ADC_ETC trigger configuration.
+ */
 typedef struct _adc_etc_trigger_config
 {
     bool enableSyncMode; /* Enable the sync Mode, In SyncMode ADC1 and ADC2 are controlled by the same trigger source.
@@ -151,8 +126,8 @@ typedef struct _adc_etc_trigger_config
 } adc_etc_trigger_config_t;
 
 /*******************************************************************************
-* API
-******************************************************************************/
+ * API
+ ******************************************************************************/
 #if defined(__cplusplus)
 extern "C" {
 #endif
@@ -163,88 +138,88 @@ extern "C" {
  */
 
 /*!
-* @brief Initialize the ADC_ETC module.
-*
-* @param base ADC_ETC peripheral base address.
-* @param config Pointer to "adc_etc_config_t" structure.
-*/
+ * @brief Initialize the ADC_ETC module.
+ *
+ * @param base ADC_ETC peripheral base address.
+ * @param config Pointer to "adc_etc_config_t" structure.
+ */
 void ADC_ETC_Init(ADC_ETC_Type *base, const adc_etc_config_t *config);
 
 /*!
-* @brief De-Initialize the ADC_ETC module.
-*
-* @param base ADC_ETC peripheral base address.
-*/
+ * @brief De-Initialize the ADC_ETC module.
+ *
+ * @param base ADC_ETC peripheral base address.
+ */
 void ADC_ETC_Deinit(ADC_ETC_Type *base);
 
 /*!
-* @brief Gets an available pre-defined settings for the ADC_ETC's configuration.
-* This function initializes the ADC_ETC's configuration structure with available settings. The default values are:
-* @code
-*   config->enableTSCBypass = true;
-*   config->enableTSC0Trigger = false;
-*   config->enableTSC1Trigger = false;
-*   config->TSC0triggerPriority = 0U;
-*   config->TSC1triggerPriority = 0U;
-*   config->clockPreDivider = 0U;
-*   config->XBARtriggerMask = 0U;
-* @endCode
-*
-* @param config Pointer to "adc_etc_config_t" structure.
-*/
+ * @brief Gets an available pre-defined settings for the ADC_ETC's configuration.
+ * This function initializes the ADC_ETC's configuration structure with available settings. The default values are:
+ * @code
+ *   config->enableTSCBypass = true;
+ *   config->enableTSC0Trigger = false;
+ *   config->enableTSC1Trigger = false;
+ *   config->TSC0triggerPriority = 0U;
+ *   config->TSC1triggerPriority = 0U;
+ *   config->clockPreDivider = 0U;
+ *   config->XBARtriggerMask = 0U;
+ * @endCode
+ *
+ * @param config Pointer to "adc_etc_config_t" structure.
+ */
 void ADC_ETC_GetDefaultConfig(adc_etc_config_t *config);
 
 /*!
-* @brief Set the external XBAR trigger configuration.
-*
-* @param base ADC_ETC peripheral base address.
-* @param triggerGroup Trigger group index.
-* @param config Pointer to "adc_etc_trigger_config_t" structure.
-*/
+ * @brief Set the external XBAR trigger configuration.
+ *
+ * @param base ADC_ETC peripheral base address.
+ * @param triggerGroup Trigger group index.
+ * @param config Pointer to "adc_etc_trigger_config_t" structure.
+ */
 void ADC_ETC_SetTriggerConfig(ADC_ETC_Type *base, uint32_t triggerGroup, const adc_etc_trigger_config_t *config);
 
 /*!
-* @brief Set the external XBAR trigger chain configuration.
-* For example, if triggerGroup is set to 0U and chainGroup is set to 1U, which means Trigger0 source's chain1 would be
-* configurated.
-*
-* @param base ADC_ETC peripheral base address.
-* @param triggerGroup Trigger group index. Available number is 0~7.
-* @param chainGroup Trigger chain group index. Available number is 0~7.
-* @param config Pointer to "adc_etc_trigger_chain_config_t" structure.
-*/
+ * @brief Set the external XBAR trigger chain configuration.
+ * For example, if triggerGroup is set to 0U and chainGroup is set to 1U, which means Trigger0 source's chain1 would be
+ * configurated.
+ *
+ * @param base ADC_ETC peripheral base address.
+ * @param triggerGroup Trigger group index. Available number is 0~7.
+ * @param chainGroup Trigger chain group index. Available number is 0~7.
+ * @param config Pointer to "adc_etc_trigger_chain_config_t" structure.
+ */
 void ADC_ETC_SetTriggerChainConfig(ADC_ETC_Type *base,
                                    uint32_t triggerGroup,
                                    uint32_t chainGroup,
                                    const adc_etc_trigger_chain_config_t *config);
 
 /*!
-* @brief Gets the interrupt status flags of external XBAR and TSC triggers.
-*
-* @param base ADC_ETC peripheral base address.
-* @param sourceIndex trigger source index.
-*
-* @return Status flags mask of trigger. Refer to "_adc_etc_status_flag_mask".
-*/
+ * @brief Gets the interrupt status flags of external XBAR and TSC triggers.
+ *
+ * @param base ADC_ETC peripheral base address.
+ * @param sourceIndex trigger source index.
+ *
+ * @return Status flags mask of trigger. Refer to "_adc_etc_status_flag_mask".
+ */
 uint32_t ADC_ETC_GetInterruptStatusFlags(ADC_ETC_Type *base, adc_etc_external_trigger_source_t sourceIndex);
 
 /*!
-* @brief Clears the ADC_ETC's interrupt status falgs.
-*
-* @param base ADC_ETC peripheral base address.
-* @param sourceIndex trigger source index.
-* @param mask Status flags mask of trigger. Refer to "_adc_etc_status_flag_mask".
-*/
+ * @brief Clears the ADC_ETC's interrupt status falgs.
+ *
+ * @param base ADC_ETC peripheral base address.
+ * @param sourceIndex trigger source index.
+ * @param mask Status flags mask of trigger. Refer to "_adc_etc_status_flag_mask".
+ */
 void ADC_ETC_ClearInterruptStatusFlags(ADC_ETC_Type *base,
                                        adc_etc_external_trigger_source_t sourceIndex,
                                        uint32_t mask);
 
 /*!
-* @brief Enable the DMA corresponding to each trigger source.
-*
-* @param base ADC_ETC peripheral base address.
-* @param triggerGroup Trigger group index. Available number is 0~7.
-*/
+ * @brief Enable the DMA corresponding to each trigger source.
+ *
+ * @param base ADC_ETC peripheral base address.
+ * @param triggerGroup Trigger group index. Available number is 0~7.
+ */
 static inline void ADC_ETC_EnableDMA(ADC_ETC_Type *base, uint32_t triggerGroup)
 {
     /* Avoid clearing status flags at the same time. */
@@ -253,11 +228,11 @@ static inline void ADC_ETC_EnableDMA(ADC_ETC_Type *base, uint32_t triggerGroup)
 }
 
 /*!
-* @brief Disable the DMA corresponding to each trigger sources.
-*
-* @param base ADC_ETC peripheral base address.
-* @param triggerGroup Trigger group index. Available number is 0~7.
-*/
+ * @brief Disable the DMA corresponding to each trigger sources.
+ *
+ * @param base ADC_ETC peripheral base address.
+ * @param triggerGroup Trigger group index. Available number is 0~7.
+ */
 static inline void ADC_ETC_DisableDMA(ADC_ETC_Type *base, uint32_t triggerGroup)
 {
     /* Avoid clearing status flags at the same time. */
@@ -290,11 +265,11 @@ static inline void ADC_ETC_ClearDMAStatusFlags(ADC_ETC_Type *base, uint32_t mask
 }
 
 /*!
-* @brief When enable ,all logical will be reset.
-*
-* @param base ADC_ETC peripheral base address.
-* @param enable Enable/Disable the software reset.
-*/
+ * @brief When enable ,all logical will be reset.
+ *
+ * @param base ADC_ETC peripheral base address.
+ * @param enable Enable/Disable the software reset.
+ */
 static inline void ADC_ETC_DoSoftwareReset(ADC_ETC_Type *base, bool enable)
 {
     if (enable)
@@ -308,14 +283,14 @@ static inline void ADC_ETC_DoSoftwareReset(ADC_ETC_Type *base, bool enable)
 }
 
 /*!
-* @brief Do software trigger corresponding to each XBAR trigger sources.
-* Each XBAR trigger sources can be configured as HW or SW trigger mode. In hardware trigger mode,
-* trigger source is from XBAR. In software mode, trigger source is from software tigger. TSC trigger sources
-* can only work in hardware trigger mode.
-*
-* @param base ADC_ETC peripheral base address.
-* @param triggerGroup Trigger group index. Available number is 0~7.
-*/
+ * @brief Do software trigger corresponding to each XBAR trigger sources.
+ * Each XBAR trigger sources can be configured as HW or SW trigger mode. In hardware trigger mode,
+ * trigger source is from XBAR. In software mode, trigger source is from software tigger. TSC trigger sources
+ * can only work in hardware trigger mode.
+ *
+ * @param base ADC_ETC peripheral base address.
+ * @param triggerGroup Trigger group index. Available number is 0~7.
+ */
 static inline void ADC_ETC_DoSoftwareTrigger(ADC_ETC_Type *base, uint32_t triggerGroup)
 {
     assert(triggerGroup < ADC_ETC_TRIGn_CTRL_COUNT);
@@ -324,15 +299,15 @@ static inline void ADC_ETC_DoSoftwareTrigger(ADC_ETC_Type *base, uint32_t trigge
 }
 
 /*!
-* @brief Get ADC conversion result from external XBAR sources.
-* For example, if triggerGroup is set to 0U and chainGroup is set to 1U, which means the API would
-* return Trigger0 source's chain1 conversion result.
-*
-* @param base ADC_ETC peripheral base address.
-* @param triggerGroup Trigger group index. Available number is 0~7.
-* @param chainGroup Trigger chain group index. Available number is 0~7.
-* @return ADC conversion result value.
-*/
+ * @brief Get ADC conversion result from external XBAR sources.
+ * For example, if triggerGroup is set to 0U and chainGroup is set to 1U, which means the API would
+ * return Trigger0 source's chain1 conversion result.
+ *
+ * @param base ADC_ETC peripheral base address.
+ * @param triggerGroup Trigger group index. Available number is 0~7.
+ * @param chainGroup Trigger chain group index. Available number is 0~7.
+ * @return ADC conversion result value.
+ */
 uint32_t ADC_ETC_GetADCConversionValue(ADC_ETC_Type *base, uint32_t triggerGroup, uint32_t chainGroup);
 
 #if defined(__cplusplus)
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_aipstz.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_aipstz.c
index 91c091c75e2..cef69975955 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_aipstz.c
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_aipstz.c
@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
  * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
  *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include "fsl_aipstz.h"
@@ -43,24 +17,35 @@
 #define FSL_COMPONENT_ID "platform.drivers.aipstz"
 #endif
 
-
 /*******************************************************************************
  * Prototypes
  ******************************************************************************/
+/*!
+ * brief Configure the privilege level for master.
+ *
+ * param base    AIPSTZ peripheral base pointer
+ * param master  Masters for AIPSTZ.
+ * param privilegeConfig Configuration is ORed from aipstz_master_privilege_level_t.
+ */
 void AIPSTZ_SetMasterPriviledgeLevel(AIPSTZ_Type *base, aipstz_master_t master, uint32_t privilegeConfig)
 {
-    uint32_t mask = ((uint32_t)master >> 8) - 1;
+    uint32_t mask  = ((uint32_t)master >> 8) - 1;
     uint32_t shift = (uint32_t)master & 0xFF;
-    base->MPR = (base->MPR & (~(mask << shift))) | (privilegeConfig << shift);
+    base->MPR      = (base->MPR & (~(mask << shift))) | (privilegeConfig << shift);
 }
 
+/*!
+ * brief Configure the access for peripheral.
+ *
+ * param base    AIPSTZ peripheral base pointer
+ * param master  Peripheral for AIPSTZ.
+ * param accessControl Configuration is ORed from aipstz_peripheral_access_control_t.
+ */
 void AIPSTZ_SetPeripheralAccessControl(AIPSTZ_Type *base, aipstz_peripheral_t peripheral, uint32_t accessControl)
 {
     volatile uint32_t *reg = (uint32_t *)((uint32_t)base + ((uint32_t)peripheral >> 16));
-    uint32_t mask = (((uint32_t)peripheral & 0xFF00U) >> 8) - 1;
-    uint32_t shift = (uint32_t)peripheral & 0xFF;
+    uint32_t mask          = (((uint32_t)peripheral & 0xFF00U) >> 8) - 1;
+    uint32_t shift         = (uint32_t)peripheral & 0xFF;
 
     *reg = (*reg & (~(mask << shift))) | ((accessControl & mask) << shift);
 }
-
-
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_aipstz.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_aipstz.h
index 9d46f2e6a56..432e0d52efb 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_aipstz.h
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_aipstz.h
@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
  * Copyright 2017 NXP
  * All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 #ifndef _FSL_AIPSTZ_H_
 #define _FSL_AIPSTZ_H_
@@ -51,15 +25,17 @@
 /*@}*/
 
 /*! @brief List of AIPSTZ privilege configuration.*/
-typedef enum _aipstz_master_privilege_level {
-    kAIPSTZ_MasterBufferedWriteEnable = (1U << 3),  /*!< Write accesses from this master are allowed to be buffered. */
-    kAIPSTZ_MasterTrustedForReadEnable = (1U << 2), /*!< This master is trusted for read accesses. */
+typedef enum _aipstz_master_privilege_level
+{
+    kAIPSTZ_MasterBufferedWriteEnable   = (1U << 3), /*!< Write accesses from this master are allowed to be buffered. */
+    kAIPSTZ_MasterTrustedForReadEnable  = (1U << 2), /*!< This master is trusted for read accesses. */
     kAIPSTZ_MasterTrustedForWriteEnable = (1U << 1), /*!< This master is trusted for write accesses. */
-    kAIPSTZ_MasterForceUserModeEnable = 1U /*!< Accesses from this master are forced to user-mode. */
+    kAIPSTZ_MasterForceUserModeEnable   = 1U         /*!< Accesses from this master are forced to user-mode. */
 } aipstz_master_privilege_level_t;
 
 /*! @brief List of AIPSTZ masters. Organized by width for the 8-15 bits and shift for lower 8 bits.*/
-typedef enum _aipstz_master {
+typedef enum _aipstz_master
+{
     kAIPSTZ_Master0 = (0x400U | 28U),
     kAIPSTZ_Master1 = (0x400U | 24U),
     kAIPSTZ_Master2 = (0x400U | 20U),
@@ -68,47 +44,50 @@ typedef enum _aipstz_master {
 } aipstz_master_t;
 
 /*! @brief List of AIPSTZ peripheral access control configuration.*/
-typedef enum _aipstz_peripheral_access_control {
+typedef enum _aipstz_peripheral_access_control
+{
     kAIPSTZ_PeripheralAllowUntrustedMaster = 1U,
-    kAIPSTZ_PeripheralWriteProtected = (1U << 1),
-    kAIPSTZ_PeripheralRequireSupervisor = (1U << 2),
-    kAIPSTZ_PeripheralAllowBufferedWrite = (1U << 3)
+    kAIPSTZ_PeripheralWriteProtected       = (1U << 1),
+    kAIPSTZ_PeripheralRequireSupervisor    = (1U << 2),
+    kAIPSTZ_PeripheralAllowBufferedWrite   = (1U << 3)
 } aipstz_peripheral_access_control_t;
 
-/*! @brief List of AIPSTZ peripherals. Organized by register offset for higher 32 bits, width for the 8-15 bits and shift for lower 8 bits.*/
-typedef enum _aipstz_peripheral {
+/*! @brief List of AIPSTZ peripherals. Organized by register offset for higher 32 bits, width for the 8-15 bits and
+ * shift for lower 8 bits.*/
+typedef enum _aipstz_peripheral
+{
     kAIPSTZ_Peripheral0  = ((0x40 << 16) | (4 << 8) | 28),
     kAIPSTZ_Peripheral1  = ((0x40 << 16) | (4 << 8) | 24),
     kAIPSTZ_Peripheral2  = ((0x40 << 16) | (4 << 8) | 20),
     kAIPSTZ_Peripheral3  = ((0x40 << 16) | (4 << 8) | 16),
     kAIPSTZ_Peripheral4  = ((0x40 << 16) | (4 << 8) | 12),
-    kAIPSTZ_Peripheral5  = ((0x40 << 16) | (4 << 8) |  8),
-    kAIPSTZ_Peripheral6  = ((0x40 << 16) | (4 << 8) |  4),
-    kAIPSTZ_Peripheral7  = ((0x40 << 16) | (4 << 8) |  0),
+    kAIPSTZ_Peripheral5  = ((0x40 << 16) | (4 << 8) | 8),
+    kAIPSTZ_Peripheral6  = ((0x40 << 16) | (4 << 8) | 4),
+    kAIPSTZ_Peripheral7  = ((0x40 << 16) | (4 << 8) | 0),
     kAIPSTZ_Peripheral8  = ((0x44 << 16) | (4 << 8) | 28),
     kAIPSTZ_Peripheral9  = ((0x44 << 16) | (4 << 8) | 24),
     kAIPSTZ_Peripheral10 = ((0x44 << 16) | (4 << 8) | 20),
     kAIPSTZ_Peripheral11 = ((0x44 << 16) | (4 << 8) | 16),
     kAIPSTZ_Peripheral12 = ((0x44 << 16) | (4 << 8) | 12),
-    kAIPSTZ_Peripheral13 = ((0x44 << 16) | (4 << 8) |  8),
-    kAIPSTZ_Peripheral14 = ((0x44 << 16) | (4 << 8) |  4),
-    kAIPSTZ_Peripheral15 = ((0x44 << 16) | (4 << 8) |  0),
+    kAIPSTZ_Peripheral13 = ((0x44 << 16) | (4 << 8) | 8),
+    kAIPSTZ_Peripheral14 = ((0x44 << 16) | (4 << 8) | 4),
+    kAIPSTZ_Peripheral15 = ((0x44 << 16) | (4 << 8) | 0),
     kAIPSTZ_Peripheral16 = ((0x48 << 16) | (4 << 8) | 28),
     kAIPSTZ_Peripheral17 = ((0x48 << 16) | (4 << 8) | 24),
     kAIPSTZ_Peripheral18 = ((0x48 << 16) | (4 << 8) | 20),
     kAIPSTZ_Peripheral19 = ((0x48 << 16) | (4 << 8) | 16),
     kAIPSTZ_Peripheral20 = ((0x48 << 16) | (4 << 8) | 12),
-    kAIPSTZ_Peripheral21 = ((0x48 << 16) | (4 << 8) |  8),
-    kAIPSTZ_Peripheral22 = ((0x48 << 16) | (4 << 8) |  4),
-    kAIPSTZ_Peripheral23 = ((0x48 << 16) | (4 << 8) |  0),
+    kAIPSTZ_Peripheral21 = ((0x48 << 16) | (4 << 8) | 8),
+    kAIPSTZ_Peripheral22 = ((0x48 << 16) | (4 << 8) | 4),
+    kAIPSTZ_Peripheral23 = ((0x48 << 16) | (4 << 8) | 0),
     kAIPSTZ_Peripheral24 = ((0x4C << 16) | (4 << 8) | 28),
     kAIPSTZ_Peripheral25 = ((0x4C << 16) | (4 << 8) | 24),
     kAIPSTZ_Peripheral26 = ((0x4C << 16) | (4 << 8) | 20),
     kAIPSTZ_Peripheral27 = ((0x4C << 16) | (4 << 8) | 16),
     kAIPSTZ_Peripheral28 = ((0x4C << 16) | (4 << 8) | 12),
-    kAIPSTZ_Peripheral29 = ((0x4C << 16) | (4 << 8) |  8),
-    kAIPSTZ_Peripheral30 = ((0x4C << 16) | (4 << 8) |  4),
-    kAIPSTZ_Peripheral31 = ((0x4C << 16) | (4 << 8) |  0),
+    kAIPSTZ_Peripheral29 = ((0x4C << 16) | (4 << 8) | 8),
+    kAIPSTZ_Peripheral30 = ((0x4C << 16) | (4 << 8) | 4),
+    kAIPSTZ_Peripheral31 = ((0x4C << 16) | (4 << 8) | 0),
     kAIPSTZ_Peripheral32 = ((0x50 << 16) | (4 << 8) | 28),
     kAIPSTZ_Peripheral33 = ((0x50 << 16) | (4 << 8) | 24)
 } aipstz_peripheral_t;
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_aoi.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_aoi.c
index c20f13c9286..85d8b1fe974 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_aoi.c
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_aoi.c
@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
  * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
  *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 #include "fsl_aoi.h"
 
@@ -38,7 +12,6 @@
 #define FSL_COMPONENT_ID "platform.drivers.aoi"
 #endif
 
-
 /*******************************************************************************
  * Variables
  ******************************************************************************/
@@ -49,9 +22,9 @@ static AOI_Type *const s_aoiBases[] = AOI_BASE_PTRS;
 /*! @brief Pointers to aoi clocks for each instance. */
 static const clock_ip_name_t s_aoiClocks[] = AOI_CLOCKS;
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
-/*******************************************************************************
- * Prototypes
- ******************************************************************************/
+       /*******************************************************************************
+        * Prototypes
+        ******************************************************************************/
 /*!
  * @brief Get instance number for AOI module.
  *
@@ -82,6 +55,13 @@ static uint32_t AOI_GetInstance(AOI_Type *base)
     return instance;
 }
 
+/*!
+ * brief Initializes an AOI instance for operation.
+ *
+ * This function un-gates the AOI clock.
+ *
+ * param base AOI peripheral address.
+ */
 void AOI_Init(AOI_Type *base)
 {
 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
@@ -90,6 +70,13 @@ void AOI_Init(AOI_Type *base)
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }
 
+/*!
+ * brief Deinitializes an AOI instance for operation.
+ *
+ * This function shutdowns AOI module.
+ *
+ * param  base AOI peripheral address.
+ */
 void AOI_Deinit(AOI_Type *base)
 {
 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
@@ -98,6 +85,22 @@ void AOI_Deinit(AOI_Type *base)
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }
 
+/*!
+ * brief Gets the Boolean evaluation associated.
+ *
+ * This function returns the Boolean evaluation associated.
+ *
+ * Example:
+  code
+    aoi_event_config_t demoEventLogicStruct;
+
+    AOI_GetEventLogicConfig(AOI, kAOI_Event0, &demoEventLogicStruct);
+  endcode
+ *
+ * param  base AOI peripheral address.
+ * param  event Index of the event which will be set of type aoi_event_t.
+ * param  config Selected input configuration .
+ */
 void AOI_GetEventLogicConfig(AOI_Type *base, aoi_event_t event, aoi_event_config_t *config)
 {
     assert(event < FSL_FEATURE_AOI_EVENT_COUNT);
@@ -132,6 +135,45 @@ void AOI_GetEventLogicConfig(AOI_Type *base, aoi_event_t event, aoi_event_config
     config->PT3DC = (aoi_input_config_t)((value & AOI_BFCRT23_PT3_DC_MASK) >> AOI_BFCRT23_PT3_DC_SHIFT);
 }
 
+/*!
+ * brief Configures an AOI event.
+ *
+ * This function configures an AOI event according
+ * to the aoiEventConfig structure. This function configures all  inputs (A, B, C, and D)
+ * of all  product terms (0, 1, 2, and 3) of a desired event.
+ *
+ * Example:
+  code
+    aoi_event_config_t demoEventLogicStruct;
+
+    demoEventLogicStruct.PT0AC = kAOI_InvInputSignal;
+    demoEventLogicStruct.PT0BC = kAOI_InputSignal;
+    demoEventLogicStruct.PT0CC = kAOI_LogicOne;
+    demoEventLogicStruct.PT0DC = kAOI_LogicOne;
+
+    demoEventLogicStruct.PT1AC = kAOI_LogicZero;
+    demoEventLogicStruct.PT1BC = kAOI_LogicOne;
+    demoEventLogicStruct.PT1CC = kAOI_LogicOne;
+    demoEventLogicStruct.PT1DC = kAOI_LogicOne;
+
+    demoEventLogicStruct.PT2AC = kAOI_LogicZero;
+    demoEventLogicStruct.PT2BC = kAOI_LogicOne;
+    demoEventLogicStruct.PT2CC = kAOI_LogicOne;
+    demoEventLogicStruct.PT2DC = kAOI_LogicOne;
+
+    demoEventLogicStruct.PT3AC = kAOI_LogicZero;
+    demoEventLogicStruct.PT3BC = kAOI_LogicOne;
+    demoEventLogicStruct.PT3CC = kAOI_LogicOne;
+    demoEventLogicStruct.PT3DC = kAOI_LogicOne;
+
+    AOI_SetEventLogicConfig(AOI, kAOI_Event0, demoEventLogicStruct);
+  endcode
+ *
+ * param  base AOI peripheral address.
+ * param  event Event which will be configured of type aoi_event_t.
+ * param  eventConfig Pointer to type aoi_event_config_t structure. The user is responsible for
+ * filling out the members of this structure and passing the pointer to this function.
+ */
 void AOI_SetEventLogicConfig(AOI_Type *base, aoi_event_t event, const aoi_event_config_t *eventConfig)
 {
     assert(eventConfig != NULL);
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_aoi.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_aoi.h
index 47dbd9b9ca7..ca6cd73b791 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_aoi.h
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_aoi.h
@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
  * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
  *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 #ifndef _FSL_AOI_H_
 #define _FSL_AOI_H_
@@ -41,7 +15,6 @@
  * @{
  */
 
-
 /*******************************************************************************
  * Definitions
  ******************************************************************************/
@@ -58,13 +31,13 @@
  * @brief AOI input configurations.
  *
  * The selection item represents the Boolean evaluations.
-*/
+ */
 typedef enum _aoi_input_config
 {
-    kAOI_LogicZero = 0x0U,      /*!< Forces the input to logical zero. */
-    kAOI_InputSignal = 0x1U,    /*!< Passes the input signal. */
+    kAOI_LogicZero      = 0x0U, /*!< Forces the input to logical zero. */
+    kAOI_InputSignal    = 0x1U, /*!< Passes the input signal. */
     kAOI_InvInputSignal = 0x2U, /*!< Inverts the input signal. */
-    kAOI_LogicOne = 0x3U        /*!< Forces the input to logical one. */
+    kAOI_LogicOne       = 0x3U  /*!< Forces the input to logical one. */
 } aoi_input_config_t;
 
 /*!
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_bee.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_bee.c
index 15a804b0c5c..3632743903d 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_bee.c
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_bee.c
@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright 2017 NXP
  * All rights reserved.
  *
- * 
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include "fsl_bee.h"
@@ -43,7 +17,6 @@
 #define FSL_COMPONENT_ID "platform.drivers.bee"
 #endif
 
-
 /*******************************************************************************
  * Variables
  ******************************************************************************/
@@ -54,7 +27,7 @@
 
 static void aligned_memcpy(void *dst, const void *src, size_t size)
 {
-    register uint32_t *to32 = (uint32_t *)(uintptr_t)dst;
+    register uint32_t *to32         = (uint32_t *)(uintptr_t)dst;
     register const uint32_t *from32 = (const uint32_t *)(uintptr_t)src;
 
     while (size >= sizeof(uint32_t))
@@ -66,6 +39,13 @@ static void aligned_memcpy(void *dst, const void *src, size_t size)
     }
 }
 
+/*!
+ * brief Resets BEE module to factory default values.
+ *
+ * This function performs hardware reset of BEE module. Attributes and keys from software for both regions are cleared.
+ *
+ * param base BEE peripheral address.
+ */
 void BEE_Init(BEE_Type *base)
 {
 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
@@ -75,6 +55,14 @@ void BEE_Init(BEE_Type *base)
     base->CTRL = BEE_CTRL_CTRL_SFTRST_N_MASK | BEE_CTRL_CTRL_CLK_EN_MASK;
 }
 
+/*!
+ * brief Resets BEE module, clears keys for both regions and disables clock to the BEE.
+ *
+ * This function performs hardware reset of BEE module and disables clocks. Attributes and keys from software for both
+ * regions are cleared.
+ *
+ * param base BEE peripheral address.
+ */
 void BEE_Deinit(BEE_Type *base)
 {
     base->CTRL &=
@@ -85,20 +73,55 @@ void BEE_Deinit(BEE_Type *base)
 #endif
 }
 
+/*!
+ * brief Loads default values to the BEE region configuration structure.
+ *
+ * Loads default values to the BEE region configuration structure. The default values are as follows:
+ * code
+ *   config->region0Mode = kBEE_AesCtrMode;
+ *   config->region1Mode = kBEE_AesCtrMode;
+ *   config->region0AddrOffset = 0U;
+ *   config->region1AddrOffset = 0U;
+ *   config->region0SecLevel = kBEE_SecurityLevel3;
+ *   config->region1SecLevel = kBEE_SecurityLevel3;
+ *   config->region1Bot = 0U;
+ *   config->region1Top = 0U;
+ *   config->accessPermission = kBEE_AccessProtDisabled;
+ *   config->endianSwapEn = kBEE_EndianSwapEnabled;
+ * endcode
+ *
+ * param config Configuration structure for BEE peripheral.
+ */
 void BEE_GetDefaultConfig(bee_region_config_t *config)
 {
     assert(config);
 
-    config->mode = kBEE_AesEcbMode;
-    config->regionBot = 0U;
-    config->regionTop = 0U;
-    config->addrOffset = 0xF0000000U;
-    config->regionEn = kBEE_RegionDisabled;
+    /* Initializes the configure structure to zero. */
+    memset(config, 0, sizeof(*config));
+
+    config->region0Mode       = kBEE_AesCtrMode;
+    config->region1Mode       = kBEE_AesCtrMode;
+    config->region0AddrOffset = 0U;
+    config->region1AddrOffset = 0U;
+    config->region0SecLevel   = kBEE_SecurityLevel3;
+    config->region1SecLevel   = kBEE_SecurityLevel3;
+    config->region1Bot        = 0U;
+    config->region1Top        = 0U;
+    config->accessPermission  = kBEE_AccessProtDisabled;
+    config->endianSwapEn      = kBEE_EndianSwapEnabled;
 }
 
-status_t BEE_SetRegionConfig(BEE_Type *base, bee_region_t region, const bee_region_config_t *config)
+/*!
+ * brief Sets BEE configuration.
+ *
+ * This function sets BEE peripheral and BEE region settings accorging to given configuration structure.
+ *
+ * param base BEE peripheral address.
+ * param config Configuration structure for BEE.
+ */
+void BEE_SetConfig(BEE_Type *base, const bee_region_config_t *config)
 {
-    IOMUXC_GPR_Type *iomuxc = IOMUXC_GPR;
+    uint32_t beeCtrlVal;
     bool reenable = false;
 
     /* Wait until BEE is in idle state */
@@ -107,62 +130,51 @@ status_t BEE_SetRegionConfig(BEE_Type *base, bee_region_t region, const bee_regi
     }
 
     /* Disable BEE before region configuration in case it is enabled. */
-    if ((base->CTRL >> BEE_CTRL_BEE_ENABLE_SHIFT) & 1)
+    if (base->CTRL & BEE_CTRL_BEE_ENABLE_MASK)
     {
         BEE_Disable(base);
         reenable = true;
     }
 
-    if (region == kBEE_Region0)
-    {
-        /* Region 0 config */
-        iomuxc->GPR18 = config->regionBot;
-        iomuxc->GPR19 = config->regionTop;
-
-        base->CTRL |= BEE_CTRL_CTRL_AES_MODE_R0(config->mode);
-        base->ADDR_OFFSET0 = BEE_ADDR_OFFSET0_ADDR_OFFSET0(config->addrOffset);
-    }
-
-    else if (region == kBEE_Region1)
-    {
-        /* Region 1 config */
-        iomuxc->GPR20 = config->regionBot;
-        iomuxc->GPR21 = config->regionTop;
-
-        base->CTRL |= BEE_CTRL_CTRL_AES_MODE_R1(config->mode);
-        base->ADDR_OFFSET1 = BEE_ADDR_OFFSET1_ADDR_OFFSET0(config->addrOffset);
-        base->REGION1_BOT = BEE_REGION1_BOT_REGION1_BOT(config->regionBot);
-        base->REGION1_TOP = BEE_REGION1_TOP_REGION1_TOP(config->regionTop);
-    }
+    /* Preserve CTRL bit values that are not set by this function */
+    beeCtrlVal = base->CTRL & 0xFFFF0037;
 
-    else
-    {
-        return kStatus_InvalidArgument;
-    }
+    /* Set variable according to configuration */
+    beeCtrlVal |= BEE_CTRL_AC_PROT_EN(config->accessPermission) | BEE_CTRL_LITTLE_ENDIAN(config->endianSwapEn) |
+                  BEE_CTRL_SECURITY_LEVEL_R0(config->region0SecLevel) | BEE_CTRL_CTRL_AES_MODE_R0(config->region0Mode) |
+                  BEE_CTRL_SECURITY_LEVEL_R1(config->region1SecLevel) | BEE_CTRL_CTRL_AES_MODE_R1(config->region1Mode);
 
-    /* Enable/disable region if desired */
-    if (config->regionEn == kBEE_RegionEnabled)
-    {
-        iomuxc->GPR11 |= IOMUXC_GPR_GPR11_BEE_DE_RX_EN(1 << region);
-    }
-    else
-    {
-        iomuxc->GPR11 &= ~IOMUXC_GPR_GPR11_BEE_DE_RX_EN(1 << region);
-    }
+    /* Load values to registers */
+    base->CTRL         = beeCtrlVal;
+    base->ADDR_OFFSET0 = config->region0AddrOffset;
+    base->ADDR_OFFSET1 = config->region1AddrOffset;
+    base->REGION1_BOT  = config->region1Bot;
+    base->REGION1_TOP  = config->region1Top;
 
     /* Reenable BEE if it was enabled before. */
     if (reenable)
     {
         BEE_Enable(base);
     }
-
-    return kStatus_Success;
 }
 
-status_t BEE_SetRegionKey(
-    BEE_Type *base, bee_region_t region, const uint8_t *key, size_t keySize, const uint8_t *nonce, size_t nonceSize)
+/*!
+ * brief Loads the AES key for selected region into BEE key registers.
+ *
+ * This function loads given AES key to BEE register for the given region.
+ * The key must be 32-bit aligned and stored in little-endian format.
+ *
+ * Please note, that eFuse BEE_KEYx_SEL must be set accordingly to be able to load and use key loaded in BEE registers.
+ * Otherwise, key cannot loaded and BEE will use key from OTPMK or SW_GP2.
+ *
+ * param base BEE peripheral address.
+ * param region Selection of the BEE region to be configured.
+ * param key AES key (in little-endian format).
+ * param keySize Size of AES key.
+ */
+status_t BEE_SetRegionKey(BEE_Type *base, bee_region_t region, const uint8_t *key, size_t keySize)
 {
-    bool reenable = false;
+    bool redisable = false;
 
     /* Key must be 32-bit aligned */
     if (((uintptr_t)key & 0x3u) || (keySize != 16))
@@ -175,39 +187,27 @@ status_t BEE_SetRegionKey(
     {
     }
 
-    /* Disable BEE before region configuration in case it is enabled. */
-    if ((base->CTRL >> BEE_CTRL_BEE_ENABLE_SHIFT) & 1)
+    /* Clear KEY_VALID bit before new key is loaded */
+    base->CTRL &= ~BEE_CTRL_KEY_VALID_MASK;
+
+    /* Write key registers, key is stored in little-endian format in memory */
+    aligned_memcpy((uint32_t *)&base->AES_KEY0_W0, key, keySize);
+
+    /* Enable BEE before key configuration. */
+    if (!(base->CTRL & BEE_CTRL_BEE_ENABLE_MASK))
     {
-        BEE_Disable(base);
-        reenable = true;
+        BEE_Enable(base);
+        redisable = true;
     }
 
     if (region == kBEE_Region0)
     {
         base->CTRL &= ~BEE_CTRL_KEY_REGION_SEL_MASK;
-
-        if (nonce)
-        {
-            if (nonceSize != 16)
-            {
-                return kStatus_InvalidArgument;
-            }
-            memcpy((uint32_t *)&base->CTR_NONCE0_W0, nonce, nonceSize);
-        }
     }
 
     else if (region == kBEE_Region1)
     {
         base->CTRL |= BEE_CTRL_KEY_REGION_SEL_MASK;
-
-        if (nonce)
-        {
-            if (nonceSize != 16)
-            {
-                return kStatus_InvalidArgument;
-            }
-            memcpy((uint32_t *)&base->CTR_NONCE1_W0, nonce, nonceSize);
-        }
     }
 
     else
@@ -215,28 +215,87 @@ status_t BEE_SetRegionKey(
         return kStatus_InvalidArgument;
     }
 
-    /* Try to load key. If BEE key selection fuse is programmed to use OTMP key on this device, this operation should
-     * fail. */
-    aligned_memcpy((uint32_t *)&base->AES_KEY0_W0, key, keySize);
-    if (memcmp((uint32_t *)&base->AES_KEY0_W0, key, keySize) != 0)
+    /* Set KEY_VALID bit to trigger key loading */
+    base->CTRL |= BEE_CTRL_KEY_VALID_MASK;
+    /* Wait until key is ready */
+    while (!(base->CTRL & BEE_CTRL_KEY_VALID_MASK))
     {
-        return kStatus_Fail;
     }
 
-    /* Reenable BEE if it was enabled before. */
-    if (reenable)
+    /* Redisable BEE if it was disabled before this function call. */
+    if (redisable)
     {
-        BEE_Enable(base);
+        BEE_Disable(base);
+    }
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Loads the nonce for selected region into BEE nonce registers.
+ *
+ * This function loads given nonce(only AES CTR mode) to BEE register for the given region.
+ * The nonce must be 32-bit aligned and stored in little-endian format.
+ *
+ * param base BEE peripheral address.
+ * param region Selection of the BEE region to be configured.
+ * param nonce AES nonce (in little-endian format).
+ * param nonceSize Size of AES nonce.
+ */
+status_t BEE_SetRegionNonce(BEE_Type *base, bee_region_t region, const uint8_t *nonce, size_t nonceSize)
+{
+    /* Nonce must be 32-bit aligned */
+    if (((uintptr_t)nonce & 0x3u) || (nonceSize != 16))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* Wait until BEE is in idle state */
+    while (!(BEE_GetStatusFlags(base) & kBEE_IdleFlag))
+    {
+    }
+
+    /* Write nonce registers, nonce is stored in little-endian format in memory */
+    if (region == kBEE_Region0)
+    {
+        aligned_memcpy((uint32_t *)&base->CTR_NONCE0_W0, nonce, nonceSize);
+    }
+
+    else if (region == kBEE_Region1)
+    {
+        aligned_memcpy((uint32_t *)&base->CTR_NONCE1_W0, nonce, nonceSize);
+    }
+
+    else
+    {
+        return kStatus_InvalidArgument;
     }
 
     return kStatus_Success;
 }
 
+/*!
+ * brief Gets the BEE status flags.
+ *
+ * This function returns status of BEE peripheral.
+ *
+ * param base BEE peripheral address.
+ *
+ * return The status flags. This is the logical OR of members of the
+ *         enumeration ::bee_status_flags_t
+ */
 uint32_t BEE_GetStatusFlags(BEE_Type *base)
 {
     return base->STATUS;
 }
 
+/*!
+ * brief Clears the BEE status flags.
+ *
+ * param base BEE peripheral base address.
+ * param mask The status flags to clear. This is a logical OR of members of the
+ *             enumeration ::bee_status_flags_t
+ */
 void BEE_ClearStatusFlags(BEE_Type *base, uint32_t mask)
 {
     /* w1c */
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_bee.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_bee.h
index 1eb6ae1ed6d..77068a7ab64 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_bee.h
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_bee.h
@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright 2017 NXP
  * All rights reserved.
  *
- * 
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #ifndef _FSL_BEE_H_
@@ -37,21 +11,26 @@
 
 #include "fsl_common.h"
 
+/*!
+ * @addtogroup bee
+ * @{
+ */
+
 /*******************************************************************************
  * Definitions
  *******************************************************************************/
 
 /*! @name Driver version */
 /*@{*/
-/*! @brief BEE driver version. Version 2.0.0.
+/*! @brief BEE driver version. Version 2.0.1.
  *
- * Current version: 2.0.0
+ * Current version: 2.0.1
  *
  * Change log:
- * - Version 2.0.0
+ * - Version 2.0.1
  *   - Initial version
  */
-#define FSL_BEE_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+#define FSL_BEE_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
 /*@}*/
 
 typedef enum _bee_aes_mode
@@ -66,31 +45,50 @@ typedef enum _bee_region
     kBEE_Region1 = 1U  /*!< BEE region 1 */
 } bee_region_t;
 
-typedef enum _bee_region_enable
+typedef enum _bee_ac_prot_enable
+{
+    kBEE_AccessProtDisabled = 0U, /*!< BEE access permission control disabled */
+    kBEE_AccessProtEnabled  = 1U  /*!< BEE access permission control enabled */
+} bee_ac_prot_enable;
+
+typedef enum _bee_endian_swap_enable
 {
-    kBEE_RegionDisabled = 0U, /*!< BEE region disabled */
-    kBEE_RegionEnabled = 1U   /*!< BEE region enabled */
-} bee_region_enable_t;
+    kBEE_EndianSwapDisabled = 1U, /*!< BEE endian swap disabled */
+    kBEE_EndianSwapEnabled  = 0U  /*!< BEE endian swap enabled */
+} bee_endian_swap_enable;
+
+typedef enum _bee_security_level
+{
+    kBEE_SecurityLevel0 = 0U, /*!< BEE security level 0 */
+    kBEE_SecurityLevel1 = 1U, /*!< BEE security level 1 */
+    kBEE_SecurityLevel2 = 2U, /*!< BEE security level 2 */
+    kBEE_SecurityLevel3 = 3U  /*!< BEE security level 3 */
+} bee_security_level;
 
 typedef enum _bee_status_flags
 {
-    kBEE_DisableAbortFlag = 1U,              /*!< Disable abort flag. */
-    kBEE_Reg0ReadSecViolation = 2U,          /*!< Region-0 read channel security violation */
-    kBEE_ReadIllegalAccess = 4U,             /*!< Read channel illegal access detected */
-    kBEE_Reg1ReadSecViolation = 8U,          /*!< Region-1 read channel security violation */
-    kBEE_Reg0AccessViolation = 16U,          /*!< Protected region-0 access violation */
-    kBEE_Reg1AccessViolation = 32U,          /*!< Protected region-1 access violation */
-    kBEE_IdleFlag = BEE_STATUS_BEE_IDLE_MASK /*!< Idle flag */
+    kBEE_DisableAbortFlag     = 1U,                      /*!< Disable abort flag. */
+    kBEE_Reg0ReadSecViolation = 2U,                      /*!< Region-0 read channel security violation */
+    kBEE_ReadIllegalAccess    = 4U,                      /*!< Read channel illegal access detected */
+    kBEE_Reg1ReadSecViolation = 8U,                      /*!< Region-1 read channel security violation */
+    kBEE_Reg0AccessViolation  = 16U,                     /*!< Protected region-0 access violation */
+    kBEE_Reg1AccessViolation  = 32U,                     /*!< Protected region-1 access violation */
+    kBEE_IdleFlag             = BEE_STATUS_BEE_IDLE_MASK /*!< Idle flag */
 } bee_status_flags_t;
 
 /*! @brief BEE region configuration structure. */
 typedef struct _bee_region_config
 {
-    bee_aes_mode_t mode;          /*!< AES mode used for encryption/decryption */
-    uint32_t regionBot;           /*!< Region bottom address */
-    uint32_t regionTop;           /*!< Region top address */
-    uint32_t addrOffset;          /*!< Region address offset */
-    bee_region_enable_t regionEn; /*!< Region enable/disable */
+    bee_aes_mode_t region0Mode;          /*!< AES mode used for encryption/decryption for region 0 */
+    bee_aes_mode_t region1Mode;          /*!< AES mode used for encryption/decryption for region 1 */
+    uint32_t region0AddrOffset;          /*!< Region 0 address offset */
+    uint32_t region1AddrOffset;          /*!< Region 1 address offset */
+    bee_security_level region0SecLevel;  /*!< Region 0 security level */
+    bee_security_level region1SecLevel;  /*!< Region 1 security level */
+    uint32_t region1Bot;                 /*!< Region 1 bottom address */
+    uint32_t region1Top;                 /*!< Region 1 top address */
+    bee_ac_prot_enable accessPermission; /*!< Access permission control enable/disable */
+    bee_endian_swap_enable endianSwapEn; /*!< Endian swap enable/disable */
 } bee_region_config_t;
 
 /*******************************************************************************
@@ -128,7 +126,7 @@ void BEE_Deinit(BEE_Type *base);
  */
 static inline void BEE_Enable(BEE_Type *base)
 {
-    base->CTRL |= BEE_CTRL_BEE_ENABLE_MASK | BEE_CTRL_KEY_VALID_MASK;
+    base->CTRL |= BEE_CTRL_BEE_ENABLE_MASK;
 }
 
 /*!
@@ -140,7 +138,7 @@ static inline void BEE_Enable(BEE_Type *base)
  */
 static inline void BEE_Disable(BEE_Type *base)
 {
-    base->CTRL &= ~BEE_CTRL_BEE_ENABLE_MASK | BEE_CTRL_KEY_VALID_MASK;
+    base->CTRL &= ~BEE_CTRL_BEE_ENABLE_MASK;
 }
 
 /*!
@@ -148,45 +146,60 @@ static inline void BEE_Disable(BEE_Type *base)
  *
  * Loads default values to the BEE region configuration structure. The default values are as follows:
  * @code
- *   config->mode = kBEE_AesCbcMode;
- *   config->regionBot = 0U;
- *   config->regionTop = 0U;
- *   config->addrOffset = 0xF0000000U;
- *   config->regionEn = kBEE_RegionDisabled;
+ *   config->region0Mode = kBEE_AesCtrMode;
+ *   config->region1Mode = kBEE_AesCtrMode;
+ *   config->region0AddrOffset = 0U;
+ *   config->region1AddrOffset = 0U;
+ *   config->region0SecLevel = kBEE_SecurityLevel3;
+ *   config->region1SecLevel = kBEE_SecurityLevel3;
+ *   config->region1Bot = 0U;
+ *   config->region1Top = 0U;
+ *   config->accessPermission = kBEE_AccessProtDisabled;
+ *   config->endianSwapEn = kBEE_EndianSwapEnabled;
  * @endcode
  *
- * @param config Configuration structure for BEE region.
+ * @param config Configuration structure for BEE peripheral.
  */
 void BEE_GetDefaultConfig(bee_region_config_t *config);
 
 /*!
- * @brief Sets BEE region configuration.
+ * @brief Sets BEE configuration.
  *
- * This function sets BEE region settings accorging to given configuration structure.
+ * This function sets BEE peripheral and BEE region settings accorging to given configuration structure.
  *
  * @param base BEE peripheral address.
- * @param region Selection of the BEE region to be configured.
- * @param config Configuration structure for BEE region.
+ * @param config Configuration structure for BEE.
  */
-status_t BEE_SetRegionConfig(BEE_Type *base, bee_region_t region, const bee_region_config_t *config);
+void BEE_SetConfig(BEE_Type *base, const bee_region_config_t *config);
 
 /*!
- * @brief Loads the AES key and nonce for selected region into BEE key registers.
+ * @brief Loads the AES key for selected region into BEE key registers.
  *
- * This function loads given AES key and nonce(only AES CTR mode) to BEE register for the given region.
+ * This function loads given AES key to BEE register for the given region.
+ * The key must be 32-bit aligned and stored in little-endian format.
  *
  * Please note, that eFuse BEE_KEYx_SEL must be set accordingly to be able to load and use key loaded in BEE registers.
  * Otherwise, key cannot loaded and BEE will use key from OTPMK or SW_GP2.
  *
  * @param base BEE peripheral address.
  * @param region Selection of the BEE region to be configured.
- * @param key AES key.
+ * @param key AES key (in little-endian format).
  * @param keySize Size of AES key.
- * @param nonce AES nonce.
+ */
+status_t BEE_SetRegionKey(BEE_Type *base, bee_region_t region, const uint8_t *key, size_t keySize);
+
+/*!
+ * @brief Loads the nonce for selected region into BEE nonce registers.
+ *
+ * This function loads given nonce(only AES CTR mode) to BEE register for the given region.
+ * The nonce must be 32-bit aligned and stored in little-endian format.
+ *
+ * @param base BEE peripheral address.
+ * @param region Selection of the BEE region to be configured.
+ * @param nonce AES nonce (in little-endian format).
  * @param nonceSize Size of AES nonce.
  */
-status_t BEE_SetRegionKey(
-    BEE_Type *base, bee_region_t region, const uint8_t *key, size_t keySize, const uint8_t *nonce, size_t nonceSize);
+status_t BEE_SetRegionNonce(BEE_Type *base, bee_region_t region, const uint8_t *nonce, size_t nonceSize);
 
 /*!
  * @brief Gets the BEE status flags.
@@ -209,18 +222,6 @@ uint32_t BEE_GetStatusFlags(BEE_Type *base);
  */
 void BEE_ClearStatusFlags(BEE_Type *base, uint32_t mask);
 
-/*!
- * @brief Computes offset to be set for specifed memory location.
- *
- * This function calculates offset that must be set for BEE region to access physical memory location.
- *
- * @param addressMemory Address of physical memory location.
- */
-static inline uint32_t BEE_GetOffset(uint32_t addressMemory)
-{
-    return (addressMemory >> 16);
-}
-
 #if defined(__cplusplus)
 }
 #endif
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_cache.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_cache.c
index 595fefe7335..259f299466b 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_cache.c
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_cache.c
@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2016, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
  * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
  *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include "fsl_cache.h"
@@ -50,10 +24,10 @@
 #define L2CACHE_SMALLWAYS_NUM 8U
 #define L2CACHE_1KBCOVERTOB 1024U
 #define L2CACHE_SAMLLWAYS_SIZE 16U
-#define L2CACHE_LOCKDOWN_REGNUM 8  /*!< Lock down register numbers.*/
-/*******************************************************************************
-* Prototypes
-******************************************************************************/
+#define L2CACHE_LOCKDOWN_REGNUM 8 /*!< Lock down register numbers.*/
+                                  /*******************************************************************************
+                                   * Prototypes
+                                   ******************************************************************************/
 /*!
  * @brief Set for all ways and waiting for the operation finished.
  *  This is provided for all the background operations.
@@ -124,7 +98,7 @@ static void L2CACHE_GetWayNumSize(uint32_t *num_ways, uint32_t *size_way);
  ******************************************************************************/
 static void L2CACHE_SetAndWaitBackGroundOperate(uint32_t auxCtlReg, uint32_t regAddr)
 {
-    uint16_t mask = L2CACHE_8WAYS_MASK;
+    uint16_t mask    = L2CACHE_8WAYS_MASK;
     uint32_t timeout = L2CACHE_OPERATION_TIMEOUT;
 
     /* Check the ways used at first. */
@@ -192,10 +166,15 @@ static void L2CACHE_GetWayNumSize(uint32_t *num_ways, uint32_t *size_way)
     *size_way = (1 << (size - 1)) * L2CACHE_SAMLLWAYS_SIZE * L2CACHE_1KBCOVERTOB;
 }
 
+/*!
+ * brief Initializes the level 2 cache controller module.
+ *
+ * param config Pointer to configuration structure. See "l2cache_config_t".
+ */
 void L2CACHE_Init(l2cache_config_t *config)
 {
-    assert (config);
-    
+    assert(config);
+
     uint16_t waysNum = 0xFFU; /* Default use the 8-way mask. */
     uint8_t count;
     uint32_t auxReg = 0;
@@ -206,7 +185,7 @@ void L2CACHE_Init(l2cache_config_t *config)
     if (L2CACHEC->REG1_CONTROL & L2CACHEC_REG1_CONTROL_CE_MASK)
     {
         L2CACHE_Disable();
-    }    
+    }
 
     /* Unlock all entries. */
     if (L2CACHEC->REG1_AUX_CONTROL & L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY_MASK)
@@ -214,20 +193,18 @@ void L2CACHE_Init(l2cache_config_t *config)
         waysNum = 0xFFFFU;
     }
 
-    for (count = 0; count < L2CACHE_LOCKDOWN_REGNUM; count ++)
+    for (count = 0; count < L2CACHE_LOCKDOWN_REGNUM; count++)
     {
-        L2CACHE_LockdownByWayEnable(count, waysNum, false);    
+        L2CACHE_LockdownByWayEnable(count, waysNum, false);
     }
-    
+
     /* Set the ways and way-size etc. */
     auxReg = L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY(config->wayNum) |
-            L2CACHEC_REG1_AUX_CONTROL_WAYSIZE(config->waySize) | 
-            L2CACHEC_REG1_AUX_CONTROL_CRP(config->repacePolicy) |
-            L2CACHEC_REG1_AUX_CONTROL_IPE(config->istrPrefetchEnable) |
-            L2CACHEC_REG1_AUX_CONTROL_DPE(config->dataPrefetchEnable) |
-            L2CACHEC_REG1_AUX_CONTROL_NLE(config->nsLockdownEnable) |
-            L2CACHEC_REG1_AUX_CONTROL_FWA(config->writeAlloc) |
-            L2CACHEC_REG1_AUX_CONTROL_HPSDRE(config->writeAlloc);
+             L2CACHEC_REG1_AUX_CONTROL_WAYSIZE(config->waySize) | L2CACHEC_REG1_AUX_CONTROL_CRP(config->repacePolicy) |
+             L2CACHEC_REG1_AUX_CONTROL_IPE(config->istrPrefetchEnable) |
+             L2CACHEC_REG1_AUX_CONTROL_DPE(config->dataPrefetchEnable) |
+             L2CACHEC_REG1_AUX_CONTROL_NLE(config->nsLockdownEnable) |
+             L2CACHEC_REG1_AUX_CONTROL_FWA(config->writeAlloc) | L2CACHEC_REG1_AUX_CONTROL_HPSDRE(config->writeAlloc);
     L2CACHEC->REG1_AUX_CONTROL = auxReg;
 
     /* Set the tag/data ram latency. */
@@ -235,39 +212,66 @@ void L2CACHE_Init(l2cache_config_t *config)
     {
         uint32_t data = 0;
         /* Tag latency. */
-        data = L2CACHEC_REG1_TAG_RAM_CONTROL_SL(config->lateConfig->tagSetupLate)|
-            L2CACHEC_REG1_TAG_RAM_CONTROL_SL(config->lateConfig->tagSetupLate)|
-            L2CACHEC_REG1_TAG_RAM_CONTROL_RAL(config->lateConfig->tagReadLate)|
-            L2CACHEC_REG1_TAG_RAM_CONTROL_WAL(config->lateConfig->dataWriteLate);
+        data = L2CACHEC_REG1_TAG_RAM_CONTROL_SL(config->lateConfig->tagSetupLate) |
+               L2CACHEC_REG1_TAG_RAM_CONTROL_SL(config->lateConfig->tagSetupLate) |
+               L2CACHEC_REG1_TAG_RAM_CONTROL_RAL(config->lateConfig->tagReadLate) |
+               L2CACHEC_REG1_TAG_RAM_CONTROL_WAL(config->lateConfig->dataWriteLate);
         L2CACHEC->REG1_TAG_RAM_CONTROL = data;
         /* Data latency. */
-        data = L2CACHEC_REG1_DATA_RAM_CONTROL_SL(config->lateConfig->dataSetupLate)|
-            L2CACHEC_REG1_DATA_RAM_CONTROL_SL(config->lateConfig->dataSetupLate)|
-            L2CACHEC_REG1_DATA_RAM_CONTROL_RAL(config->lateConfig->dataReadLate)|
-            L2CACHEC_REG1_DATA_RAM_CONTROL_WAL(config->lateConfig->dataWriteLate);
+        data = L2CACHEC_REG1_DATA_RAM_CONTROL_SL(config->lateConfig->dataSetupLate) |
+               L2CACHEC_REG1_DATA_RAM_CONTROL_SL(config->lateConfig->dataSetupLate) |
+               L2CACHEC_REG1_DATA_RAM_CONTROL_RAL(config->lateConfig->dataReadLate) |
+               L2CACHEC_REG1_DATA_RAM_CONTROL_WAL(config->lateConfig->dataWriteLate);
         L2CACHEC->REG1_DATA_RAM_CONTROL = data;
     }
 }
 
+/*!
+ * brief Gets an available default settings for the cache controller.
+ *
+ * This function initializes the cache controller configuration structure with default settings.
+ * The default values are:
+ * code
+ *   config->waysNum = kL2CACHE_8ways;
+ *   config->waySize = kL2CACHE_32KbSize;
+ *   config->repacePolicy = kL2CACHE_Roundrobin;
+ *   config->lateConfig = NULL;
+ *   config->istrPrefetchEnable = false;
+ *   config->dataPrefetchEnable = false;
+ *   config->nsLockdownEnable = false;
+ *   config->writeAlloc = kL2CACHE_UseAwcache;
+ * endcode
+ * param config Pointer to the configuration structure.
+ */
 void L2CACHE_GetDefaultConfig(l2cache_config_t *config)
 {
     assert(config);
+
+    /* Initializes the configure structure to zero. */
+    memset(config, 0, sizeof(*config));
+
     uint32_t number = (L2CACHEC->REG1_AUX_CONTROL & L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY_MASK) >>
                       L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY_SHIFT;
     uint32_t size = (L2CACHEC->REG1_AUX_CONTROL & L2CACHEC_REG1_AUX_CONTROL_WAYSIZE_MASK) >>
                     L2CACHEC_REG1_AUX_CONTROL_WAYSIZE_SHIFT;
 
     /* Get the default value */
-    config->wayNum = (l2cache_way_num_t)number;
-    config->waySize = (l2cache_way_size)size;
-    config->repacePolicy = kL2CACHE_Roundrobin;
-    config->lateConfig = NULL;
+    config->wayNum             = (l2cache_way_num_t)number;
+    config->waySize            = (l2cache_way_size)size;
+    config->repacePolicy       = kL2CACHE_Roundrobin;
+    config->lateConfig         = NULL;
     config->istrPrefetchEnable = false;
     config->dataPrefetchEnable = false;
-    config->nsLockdownEnable = false;
-    config->writeAlloc = kL2CACHE_UseAwcache; 
+    config->nsLockdownEnable   = false;
+    config->writeAlloc         = kL2CACHE_UseAwcache;
 }
 
+/*!
+ * brief Enables the level 2 cache controller.
+ * This function enables the cache controller. Must be written using a secure access.
+ * If write with a Non-secure access will cause a DECERR response.
+ *
+ */
 void L2CACHE_Enable(void)
 {
     /* Invalidate first. */
@@ -276,6 +280,12 @@ void L2CACHE_Enable(void)
     L2CACHEC->REG1_CONTROL = L2CACHEC_REG1_CONTROL_CE_MASK;
 }
 
+/*!
+ * brief Disables the level 2 cache controller.
+ * This function disables the cache controller. Must be written using a secure access.
+ * If write with a Non-secure access will cause a DECERR response.
+ *
+ */
 void L2CACHE_Disable(void)
 {
     /* First CleanInvalidate all enties in the cache. */
@@ -286,6 +296,11 @@ void L2CACHE_Disable(void)
     __DSB();
 }
 
+/*!
+ * brief Invalidates the Level 2 cache.
+ * This function invalidates all entries in cache.
+ *
+ */
 void L2CACHE_Invalidate(void)
 {
     /* Invalidate all entries in cache. */
@@ -294,6 +309,11 @@ void L2CACHE_Invalidate(void)
     L2CACHEC->REG7_CACHE_SYNC = 0;
 }
 
+/*!
+ * brief Cleans the level 2 cache controller.
+ * This function cleans all entries in the level 2 cache controller.
+ *
+ */
 void L2CACHE_Clean(void)
 {
     /* Clean all entries of the cache. */
@@ -302,6 +322,11 @@ void L2CACHE_Clean(void)
     L2CACHEC->REG7_CACHE_SYNC = 0;
 }
 
+/*!
+ * brief Cleans and invalidates the level 2 cache controller.
+ * This function cleans and invalidates all entries in the level 2 cache controller.
+ *
+ */
 void L2CACHE_CleanInvalidate(void)
 {
     /* Clean all entries of the cache. */
@@ -310,6 +335,17 @@ void L2CACHE_CleanInvalidate(void)
     L2CACHEC->REG7_CACHE_SYNC = 0;
 }
 
+/*!
+ * brief Invalidates the Level 2 cache lines in the range of two physical addresses.
+ * This function invalidates all cache lines between two physical addresses.
+ *
+ * param address  The start address of the memory to be invalidated.
+ * param size_byte  The memory size.
+ * note The start address and size_byte should be 32-byte(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) aligned.
+ * The startAddr here will be forced to align to L2 line size if startAddr
+ * is not aligned. For the size_byte, application should make sure the
+ * alignment or make sure the right operation order if the size_byte is not aligned.
+ */
 void L2CACHE_InvalidateByRange(uint32_t address, uint32_t size_byte)
 {
     uint32_t endAddr = address + size_byte;
@@ -326,11 +362,22 @@ void L2CACHE_InvalidateByRange(uint32_t address, uint32_t size_byte)
     L2CACHEC->REG7_CACHE_SYNC = 0;
 }
 
+/*!
+ * brief Cleans the Level 2 cache lines in the range of two physical addresses.
+ * This function cleans all cache lines between two physical addresses.
+ *
+ * param address  The start address of the memory to be cleaned.
+ * param size_byte  The memory size.
+ * note The start address and size_byte should be 32-byte(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) aligned.
+ * The startAddr here will be forced to align to L2 line size if startAddr
+ * is not aligned. For the size_byte, application should make sure the
+ * alignment or make sure the right operation order if the size_byte is not aligned.
+ */
 void L2CACHE_CleanByRange(uint32_t address, uint32_t size_byte)
 {
     uint32_t num_ways = 0;
     uint32_t size_way = 0;
-    uint32_t endAddr = address + size_byte;
+    uint32_t endAddr  = address + size_byte;
 
     /* Get the number and size of the cache way. */
     L2CACHE_GetWayNumSize(&num_ways, &size_way);
@@ -353,11 +400,22 @@ void L2CACHE_CleanByRange(uint32_t address, uint32_t size_byte)
     L2CACHEC->REG7_CACHE_SYNC = 0;
 }
 
+/*!
+ * brief Cleans and invalidates the Level 2 cache lines in the range of two physical addresses.
+ * This function cleans and invalidates all cache lines between two physical addresses.
+ *
+ * param address  The start address of the memory to be cleaned and invalidated.
+ * param size_byte  The memory size.
+ * note The start address and size_byte should be 32-byte(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) aligned.
+ * The startAddr here will be forced to align to L2 line size if startAddr
+ * is not aligned. For the size_byte, application should make sure the
+ * alignment or make sure the right operation order if the size_byte is not aligned.
+ */
 void L2CACHE_CleanInvalidateByRange(uint32_t address, uint32_t size_byte)
 {
     uint32_t num_ways = 0;
     uint32_t size_way = 0;
-    uint32_t endAddr = address + size_byte;
+    uint32_t endAddr  = address + size_byte;
 
     /* Get the number and size of the cache way. */
     L2CACHE_GetWayNumSize(&num_ways, &size_way);
@@ -380,6 +438,23 @@ void L2CACHE_CleanInvalidateByRange(uint32_t address, uint32_t size_byte)
     L2CACHEC->REG7_CACHE_SYNC = 0;
 }
 
+/*!
+ * brief Enables or disables to lock down the data and instruction by way.
+ * This function locks down the cached instruction/data by way and prevent the adresses from
+ * being allocated and prevent dara from being evicted out of the level 2 cache.
+ * But the normal cache maintenance operations that invalidate, clean or clean
+ * and validate cache contents affect the locked-down cache lines as normal.
+ *
+ * param masterId  The master id, range from 0 ~ 7.
+ * param mask  The ways to be enabled or disabled to lockdown.
+ *               each bit in value is related to each way of the cache. for example:
+ *               value: bit 0  ------ way 0.
+ *               value: bit 1  ------ way 1.
+ *               --------------------------
+ *               value: bit 15 ------ way 15.
+ * Note: please make sure the value setting is align with your supported ways.
+ * param enable  True enable the lockdown, false to disable the lockdown.
+ */
 void L2CACHE_LockdownByWayEnable(uint32_t masterId, uint32_t mask, bool enable)
 {
     uint8_t num_ways = (L2CACHEC->REG1_AUX_CONTROL & L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY_MASK) >>
@@ -407,13 +482,23 @@ void L2CACHE_LockdownByWayEnable(uint32_t masterId, uint32_t mask, bool enable)
         L2CACHEC->LOCKDOWN[masterId].REG9_I_LOCKDOWN = istrReg & ~mask;
     }
 }
-#endif  /* FSL_FEATURE_SOC_L2CACHEC_COUNT */
+#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */
 
+/*!
+ * brief Invalidate cortex-m7 L1 instruction cache by range.
+ *
+ * param address  The start address of the memory to be invalidated.
+ * param size_byte  The memory size.
+ * note The start address and size_byte should be 32-byte(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE) aligned.
+ * The startAddr here will be forced to align to L1 I-cache line size if
+ * startAddr is not aligned. For the size_byte, application should make sure the
+ * alignment or make sure the right operation order if the size_byte is not aligned.
+ */
 void L1CACHE_InvalidateICacheByRange(uint32_t address, uint32_t size_byte)
 {
 #if (__DCACHE_PRESENT == 1U)
-    uint32_t addr = address & (uint32_t)~(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE - 1);
-    int32_t size = size_byte + address - addr;
+    uint32_t addr     = address & (uint32_t) ~(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE - 1);
+    int32_t size      = size_byte + address - addr;
     uint32_t linesize = 32U;
 
     __DSB();
@@ -425,9 +510,21 @@ void L1CACHE_InvalidateICacheByRange(uint32_t address, uint32_t size_byte)
     }
     __DSB();
     __ISB();
-#endif    
+#endif
 }
 
+/*!
+ * brief Invalidates all instruction caches by range.
+ *
+ * Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte.
+ *
+ * param address The physical address.
+ * param size_byte size of the memory to be invalidated.
+ * note address and size should be aligned to cache line size
+ *  32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced
+ * to align to the cache line size if startAddr is not aligned. For the size_byte, application should
+ * make sure the alignment or make sure the right operation order if the size_byte is not aligned.
+ */
 void ICACHE_InvalidateByRange(uint32_t address, uint32_t size_byte)
 {
 #if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT
@@ -436,9 +533,21 @@ void ICACHE_InvalidateByRange(uint32_t address, uint32_t size_byte)
 #endif /* !FSL_SDK_DISBLE_L2CACHE_PRESENT */
 #endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */
 
-   L1CACHE_InvalidateICacheByRange(address, size_byte);
+    L1CACHE_InvalidateICacheByRange(address, size_byte);
 }
 
+/*!
+ * brief Invalidates all data caches by range.
+ *
+ * Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte.
+ *
+ * param address The physical address.
+ * param size_byte size of the memory to be invalidated.
+ * note address and size should be aligned to cache line size
+ *  32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced
+ * to align to the cache line size if startAddr is not aligned. For the size_byte, application should
+ * make sure the alignment or make sure the right operation order if the size_byte is not aligned.
+ */
 void DCACHE_InvalidateByRange(uint32_t address, uint32_t size_byte)
 {
 #if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT
@@ -449,6 +558,18 @@ void DCACHE_InvalidateByRange(uint32_t address, uint32_t size_byte)
     L1CACHE_InvalidateDCacheByRange(address, size_byte);
 }
 
+/*!
+ * brief Cleans all data caches by range.
+ *
+ * Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte.
+ *
+ * param address The physical address.
+ * param size_byte size of the memory to be cleaned.
+ * note address and size should be aligned to cache line size
+ *  32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced
+ * to align to the cache line size if startAddr is not aligned. For the size_byte, application should
+ * make sure the alignment or make sure the right operation order if the size_byte is not aligned.
+ */
 void DCACHE_CleanByRange(uint32_t address, uint32_t size_byte)
 {
     L1CACHE_CleanDCacheByRange(address, size_byte);
@@ -459,6 +580,18 @@ void DCACHE_CleanByRange(uint32_t address, uint32_t size_byte)
 #endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */
 }
 
+/*!
+ * brief Cleans and Invalidates all data caches by range.
+ *
+ * Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte.
+ *
+ * param address The physical address.
+ * param size_byte size of the memory to be cleaned and invalidated.
+ * note address and size should be aligned to cache line size
+ *  32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced
+ * to align to the cache line size if startAddr is not aligned. For the size_byte, application should
+ * make sure the alignment or make sure the right operation order if the size_byte is not aligned.
+ */
 void DCACHE_CleanInvalidateByRange(uint32_t address, uint32_t size_byte)
 {
     L1CACHE_CleanInvalidateDCacheByRange(address, size_byte);
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_cache.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_cache.h
index a041ea2a34a..17e30a61d2e 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_cache.h
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_cache.h
@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2016, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
  * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 #ifndef _FSL_CACHE_H_
 #define _FSL_CACHE_H_
@@ -53,7 +27,7 @@
 
 #if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT
 #ifndef FSL_SDK_DISBLE_L2CACHE_PRESENT
-#define FSL_SDK_DISBLE_L2CACHE_PRESENT   0
+#define FSL_SDK_DISBLE_L2CACHE_PRESENT 0
 #endif
 #endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */
 /*******************************************************************************
@@ -64,80 +38,80 @@
 /*! @brief Number of level 2 cache controller ways. */
 typedef enum _l2cache_way_num
 {
-    kL2CACHE_8ways = 0,         /*!< 8 ways. */
+    kL2CACHE_8ways = 0, /*!< 8 ways. */
 #if defined(FSL_FEATURE_L2CACHE_SUPPORT_16_WAY_ASSOCIATIVITY) && FSL_FEATURE_L2CACHE_SUPPORT_16_WAY_ASSOCIATIVITY
-    kL2CACHE_16ways             /*!< 16 ways. */
-#endif /* FSL_FEATURE_L2CACHE_SUPPORT_16_WAY_ASSOCIATIVITY */
+    kL2CACHE_16ways /*!< 16 ways. */
+#endif              /* FSL_FEATURE_L2CACHE_SUPPORT_16_WAY_ASSOCIATIVITY */
 } l2cache_way_num_t;
 
 /*! @brief Level 2 cache controller way size. */
 typedef enum _l2cache_way_size
 {
-    kL2CACHE_16KBSize  = 1,      /*!< 16 KB way size. */
-    kL2CACHE_32KBSize  = 2,      /*!< 32 KB way size. */
-    kL2CACHE_64KBSize  = 3,      /*!< 64 KB way size. */
-    kL2CACHE_128KBSize = 4,      /*!< 128 KB way size. */
-    kL2CACHE_256KBSize = 5,      /*!< 256 KB way size. */
-    kL2CACHE_512KBSize = 6       /*!< 512 KB way size. */
+    kL2CACHE_16KBSize  = 1, /*!< 16 KB way size. */
+    kL2CACHE_32KBSize  = 2, /*!< 32 KB way size. */
+    kL2CACHE_64KBSize  = 3, /*!< 64 KB way size. */
+    kL2CACHE_128KBSize = 4, /*!< 128 KB way size. */
+    kL2CACHE_256KBSize = 5, /*!< 256 KB way size. */
+    kL2CACHE_512KBSize = 6  /*!< 512 KB way size. */
 } l2cache_way_size;
 
 /*! @brief Level 2 cache controller replacement policy. */
 typedef enum _l2cache_replacement
 {
-    kL2CACHE_Pseudorandom = 0U,    /*!< Peseudo-random replacement policy using an lfsr. */
-    kL2CACHE_Roundrobin            /*!< Round-robin replacemnt policy. */
+    kL2CACHE_Pseudorandom = 0U, /*!< Peseudo-random replacement policy using an lfsr. */
+    kL2CACHE_Roundrobin         /*!< Round-robin replacemnt policy. */
 } l2cache_replacement_t;
 
 /*! @brief Level 2 cache controller force write allocate options. */
 typedef enum _l2cache_writealloc
 {
-    kL2CACHE_UseAwcache = 0,      /*!< Use AWCAHE attribute for the write allocate. */
-    kL2CACHE_NoWriteallocate,     /*!< Force no write allocate. */
-    kL2CACHE_forceWriteallocate   /*!< Force write allocate when write misses. */
+    kL2CACHE_UseAwcache = 0,    /*!< Use AWCAHE attribute for the write allocate. */
+    kL2CACHE_NoWriteallocate,   /*!< Force no write allocate. */
+    kL2CACHE_forceWriteallocate /*!< Force write allocate when write misses. */
 } l2cache_writealloc_t;
 
 /*! @brief Level 2 cache controller tag/data ram latency. */
 typedef enum _l2cache_latency
 {
-    kL2CACHE_1CycleLate = 0,   /*!< 1 cycle of latency. */
-    kL2CACHE_2CycleLate,       /*!< 2 cycle of latency. */
-    kL2CACHE_3CycleLate,       /*!< 3 cycle of latency. */
-    kL2CACHE_4CycleLate,       /*!< 4 cycle of latency. */
-    kL2CACHE_5CycleLate,       /*!< 5 cycle of latency. */
-    kL2CACHE_6CycleLate,       /*!< 6 cycle of latency. */
-    kL2CACHE_7CycleLate,       /*!< 7 cycle of latency. */
-    kL2CACHE_8CycleLate        /*!< 8 cycle of latency. */
+    kL2CACHE_1CycleLate = 0, /*!< 1 cycle of latency. */
+    kL2CACHE_2CycleLate,     /*!< 2 cycle of latency. */
+    kL2CACHE_3CycleLate,     /*!< 3 cycle of latency. */
+    kL2CACHE_4CycleLate,     /*!< 4 cycle of latency. */
+    kL2CACHE_5CycleLate,     /*!< 5 cycle of latency. */
+    kL2CACHE_6CycleLate,     /*!< 6 cycle of latency. */
+    kL2CACHE_7CycleLate,     /*!< 7 cycle of latency. */
+    kL2CACHE_8CycleLate      /*!< 8 cycle of latency. */
 } l2cache_latency_t;
 
 /*! @brief Level 2 cache controller tag/data ram latency configure structure. */
 typedef struct _l2cache_latency_config
 {
-    l2cache_latency_t tagWriteLate;   /*!< Tag write latency. */
-    l2cache_latency_t tagReadLate;    /*!< Tag Read latency. */
-    l2cache_latency_t tagSetupLate;   /*!< Tag setup latency. */
-    l2cache_latency_t dataWriteLate;  /*!< Data write latency. */
-    l2cache_latency_t dataReadLate;   /*!< Data Read latency. */
-    l2cache_latency_t dataSetupLate;  /*!< Data setup latency. */
+    l2cache_latency_t tagWriteLate;  /*!< Tag write latency. */
+    l2cache_latency_t tagReadLate;   /*!< Tag Read latency. */
+    l2cache_latency_t tagSetupLate;  /*!< Tag setup latency. */
+    l2cache_latency_t dataWriteLate; /*!< Data write latency. */
+    l2cache_latency_t dataReadLate;  /*!< Data Read latency. */
+    l2cache_latency_t dataSetupLate; /*!< Data setup latency. */
 } L2cache_latency_config_t;
 
 /*! @brief Level 2 cache controller configure structure. */
 typedef struct _l2cache_config
 {
     /* ------------------------ l2 cachec basic settings ---------------------------- */
-    l2cache_way_num_t wayNum;        /*!< The number of ways. */
-    l2cache_way_size  waySize;        /*!< The way size = Cache Ram size / wayNum. */ 
-    l2cache_replacement_t repacePolicy;/*!< Replacemnet policy. */
+    l2cache_way_num_t wayNum;           /*!< The number of ways. */
+    l2cache_way_size waySize;           /*!< The way size = Cache Ram size / wayNum. */
+    l2cache_replacement_t repacePolicy; /*!< Replacemnet policy. */
     /* ------------------------ tag/data ram latency settings ----------------------- */
     L2cache_latency_config_t *lateConfig; /*!< Tag/data latency configure. Set NUll if not required. */
     /* ------------------------ Prefetch enable settings ---------------------------- */
-    bool istrPrefetchEnable;          /*!< Instruction prefetch enable. */
-    bool dataPrefetchEnable;          /*!< Data prefetch enable. */
+    bool istrPrefetchEnable; /*!< Instruction prefetch enable. */
+    bool dataPrefetchEnable; /*!< Data prefetch enable. */
     /* ------------------------ Non-secure access settings -------------------------- */
-    bool nsLockdownEnable;            /*!< None-secure lockdown enable. */
+    bool nsLockdownEnable; /*!< None-secure lockdown enable. */
     /* ------------------------ other settings -------------------------------------- */
-    l2cache_writealloc_t  writeAlloc;/*!< Write allcoate force option. */     
+    l2cache_writealloc_t writeAlloc; /*!< Write allcoate force option. */
 } l2cache_config_t;
-#endif  /* FSL_FEATURE_SOC_L2CACHEC_COUNT */
+#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */
 /*******************************************************************************
  * API
  ******************************************************************************/
@@ -183,7 +157,7 @@ static inline void L1CACHE_InvalidateICache(void)
  *
  * @param address  The start address of the memory to be invalidated.
  * @param size_byte  The memory size.
- * @note The start address and size_byte should be 32-byte(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE) aligned. 
+ * @note The start address and size_byte should be 32-byte(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE) aligned.
  * The startAddr here will be forced to align to L1 I-cache line size if
  * startAddr is not aligned. For the size_byte, application should make sure the
  * alignment or make sure the right operation order if the size_byte is not aligned.
@@ -240,15 +214,15 @@ static inline void L1CACHE_CleanInvalidateDCache(void)
  *
  * @param address  The start address of the memory to be invalidated.
  * @param size_byte  The memory size.
- * @note The start address and size_byte should be 32-byte(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) aligned. 
+ * @note The start address and size_byte should be 32-byte(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) aligned.
  * The startAddr here will be forced to align to L1 D-cache line size if
  * startAddr is not aligned. For the size_byte, application should make sure the
  * alignment or make sure the right operation order if the size_byte is not aligned.
  */
 static inline void L1CACHE_InvalidateDCacheByRange(uint32_t address, uint32_t size_byte)
 {
-    uint32_t startAddr = address & (uint32_t)~(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE - 1);
-    uint32_t size = size_byte + address - startAddr;
+    uint32_t startAddr = address & (uint32_t) ~(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE - 1);
+    uint32_t size      = size_byte + address - startAddr;
 
     SCB_InvalidateDCache_by_Addr((uint32_t *)startAddr, size);
 }
@@ -265,8 +239,8 @@ static inline void L1CACHE_InvalidateDCacheByRange(uint32_t address, uint32_t si
  */
 static inline void L1CACHE_CleanDCacheByRange(uint32_t address, uint32_t size_byte)
 {
-    uint32_t startAddr = address & (uint32_t)~(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE - 1);
-    uint32_t size = size_byte + address - startAddr;
+    uint32_t startAddr = address & (uint32_t) ~(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE - 1);
+    uint32_t size      = size_byte + address - startAddr;
 
     SCB_CleanDCache_by_Addr((uint32_t *)startAddr, size);
 }
@@ -283,8 +257,8 @@ static inline void L1CACHE_CleanDCacheByRange(uint32_t address, uint32_t size_by
  */
 static inline void L1CACHE_CleanInvalidateDCacheByRange(uint32_t address, uint32_t size_byte)
 {
-    uint32_t startAddr = address & (uint32_t)~(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE - 1);
-    uint32_t size = size_byte + address - startAddr;
+    uint32_t startAddr = address & (uint32_t) ~(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE - 1);
+    uint32_t size      = size_byte + address - startAddr;
 
     SCB_CleanInvalidateDCache_by_Addr((uint32_t *)startAddr, size);
 }
@@ -306,7 +280,7 @@ void L2CACHE_Init(l2cache_config_t *config);
 /*!
  * @brief Gets an available default settings for the cache controller.
  *
- * This function initializes the cache controller configuration structure with default settings. 
+ * This function initializes the cache controller configuration structure with default settings.
  * The default values are:
  * @code
  *   config->waysNum = kL2CACHE_8ways;
@@ -316,7 +290,7 @@ void L2CACHE_Init(l2cache_config_t *config);
  *   config->istrPrefetchEnable = false;
  *   config->dataPrefetchEnable = false;
  *   config->nsLockdownEnable = false;
- *   config->writeAlloc = kL2CACHE_UseAwcache; 
+ *   config->writeAlloc = kL2CACHE_UseAwcache;
  * @endcode
  * @param config Pointer to the configuration structure.
  */
@@ -484,7 +458,6 @@ void DCACHE_CleanInvalidateByRange(uint32_t address, uint32_t size_byte);
 
 /*@}*/
 
-
 #if defined(__cplusplus)
 }
 #endif
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_clock.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_clock.c
index e12179b96fb..6a0bf8b3c6a 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_clock.c
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_clock.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2017 NXP
+ * Copyright 2017 - 2019 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
@@ -520,7 +520,7 @@ void CLOCK_InitSysPll(const clock_sys_pll_config_t *config)
         CCM_ANALOG_PLL_SYS_ENABLE_MASK | CCM_ANALOG_PLL_SYS_DIV_SELECT(config->loopDivider);
 
     /* Initialize the fractional mode */
-    CCM_ANALOG->PLL_SYS_NUM = CCM_ANALOG_PLL_SYS_NUM_A(config->numerator);
+    CCM_ANALOG->PLL_SYS_NUM   = CCM_ANALOG_PLL_SYS_NUM_A(config->numerator);
     CCM_ANALOG->PLL_SYS_DENOM = CCM_ANALOG_PLL_SYS_DENOM_B(config->denominator);
 
     /* Initialize the spread spectrum mode */
@@ -626,7 +626,7 @@ void CLOCK_InitAudioPll(const clock_audio_pll_config_t *config)
     CCM_ANALOG->PLL_AUDIO = (CCM_ANALOG->PLL_AUDIO & (~CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK)) |
                             CCM_ANALOG_PLL_AUDIO_BYPASS_MASK | CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC(config->src);
 
-    CCM_ANALOG->PLL_AUDIO_NUM = CCM_ANALOG_PLL_AUDIO_NUM_A(config->numerator);
+    CCM_ANALOG->PLL_AUDIO_NUM   = CCM_ANALOG_PLL_AUDIO_NUM_A(config->numerator);
     CCM_ANALOG->PLL_AUDIO_DENOM = CCM_ANALOG_PLL_AUDIO_DENOM_B(config->denominator);
 
     /*
@@ -713,7 +713,7 @@ void CLOCK_InitVideoPll(const clock_video_pll_config_t *config)
     CCM_ANALOG->PLL_VIDEO = (CCM_ANALOG->PLL_VIDEO & (~CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK)) |
                             CCM_ANALOG_PLL_VIDEO_BYPASS_MASK | CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(config->src);
 
-    CCM_ANALOG->PLL_VIDEO_NUM = CCM_ANALOG_PLL_VIDEO_NUM_A(config->numerator);
+    CCM_ANALOG->PLL_VIDEO_NUM   = CCM_ANALOG_PLL_VIDEO_NUM_A(config->numerator);
     CCM_ANALOG->PLL_VIDEO_DENOM = CCM_ANALOG_PLL_VIDEO_DENOM_B(config->denominator);
 
     /*
@@ -1209,3 +1209,51 @@ void CLOCK_DisableUsbhs1PhyPllClock(void)
     CCM_ANALOG->PLL_USB2 &= ~CCM_ANALOG_PLL_USB2_EN_USB_CLKS_MASK;
     USBPHY2->CTRL |= USBPHY_CTRL_CLKGATE_MASK; /* Set to 1U to gate clocks */
 }
+
+/*!
+ * brief Use DWT to delay at least for some time.
+ * Please note that, this API will calculate the microsecond period with the maximum devices
+ * supported CPU frequency, so this API will only delay for at least the given microseconds, if precise
+ * delay count was needed, please implement a new timer count to achieve this function.
+ *
+ * param delay_us  Delay time in unit of microsecond.
+ */
+__attribute__((weak)) void SDK_DelayAtLeastUs(uint32_t delay_us)
+{
+    assert(0U != delay_us);
+    uint64_t count  = 0U;
+    uint32_t period = SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY / 1000000;
+
+    /* Make sure the DWT trace fucntion is enabled. */
+    if (CoreDebug_DEMCR_TRCENA_Msk != (CoreDebug_DEMCR_TRCENA_Msk & CoreDebug->DEMCR))
+    {
+        CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
+    }
+
+    /* CYCCNT not supported on this device. */
+    assert(DWT_CTRL_NOCYCCNT_Msk != (DWT->CTRL & DWT_CTRL_NOCYCCNT_Msk));
+
+    /* If CYCCENT has already been enabled, read directly, otherwise, need enable it. */
+    if (DWT_CTRL_CYCCNTENA_Msk != (DWT_CTRL_CYCCNTENA_Msk & DWT->CTRL))
+    {
+        DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk;
+    }
+
+    /* Calculate the count ticks. */
+    count = DWT->CYCCNT;
+    count += (uint64_t)period * delay_us;
+
+    if (count > 0xFFFFFFFFUL)
+    {
+        count -= 0xFFFFFFFFUL;
+        /* wait for cyccnt overflow. */
+        while (count < DWT->CYCCNT)
+        {
+        }
+    }
+
+    /* Wait for cyccnt reach count value. */
+    while (count > DWT->CYCCNT)
+    {
+    }
+}
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_clock.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_clock.h
index 915ad1e355b..bab4f215924 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_clock.h
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_clock.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2017 NXP
+ * Copyright 2017 - 2019 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
@@ -39,15 +39,19 @@
 
 /*! @name Driver version */
 /*@{*/
-/*! @brief CLOCK driver version 2.1.5. */
-#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 1, 5))
+/*! @brief CLOCK driver version 2.2.0. */
+#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 2, 0))
+
+/* Definition for delay API in clock driver, users can redefine it to the real application. */
+#ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY
+#define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (600000000UL)
+#endif
 
 /* analog pll definition */
 #define CCM_ANALOG_PLL_BYPASS_SHIFT (16U)
 #define CCM_ANALOG_PLL_BYPASS_CLK_SRC_MASK (0xC000U)
 #define CCM_ANALOG_PLL_BYPASS_CLK_SRC_SHIFT (14U)
 
-
 /*@}*/
 
 /*!
@@ -75,11 +79,10 @@
 #define PLL_AUDIO_OFFSET 0x70
 #define PLL_VIDEO_OFFSET 0xA0
 #define PLL_ENET_OFFSET 0xE0
-#define PLL_USB2_OFFSET 0x20    
+#define PLL_USB2_OFFSET 0x20
 
-#define CCM_TUPLE(reg, shift, mask, busyShift)                               \
-    (int)((reg & 0xFFU) | ((shift) << 8U) | \
-         ((((mask) >> (shift)) & 0x1FFFU) << 13U) | ((busyShift) << 26U))
+#define CCM_TUPLE(reg, shift, mask, busyShift) \
+    (int)((reg & 0xFFU) | ((shift) << 8U) | ((((mask) >> (shift)) & 0x1FFFU) << 13U) | ((busyShift) << 26U))
 #define CCM_TUPLE_REG(base, tuple) (*((volatile uint32_t *)(((uint32_t)(base)) + ((tuple)&0xFFU))))
 #define CCM_TUPLE_SHIFT(tuple) (((tuple) >> 8U) & 0x1FU)
 #define CCM_TUPLE_MASK(tuple) ((uint32_t)((((tuple) >> 13U) & 0x1FFFU) << ((((tuple) >> 8U) & 0x1FU))))
@@ -100,7 +103,7 @@
  * @brief clock1PN frequency.
  */
 #define CLKPN_FREQ 0U
-      
+
 /*! @brief External XTAL (24M OSC/SYSOSC) clock frequency.
  *
  * The XTAL (24M OSC/SYSOSC) clock frequency in Hz, when the clock is setup, use the
@@ -300,16 +303,15 @@ extern volatile uint32_t g_rtcXtalFreq;
     }
 
 /*! @brief Clock ip name array for PWM. */
-#define PWM_CLOCKS                                                                                                    \
-    {                                                                                                                 \
-        {                                                                                                             \
-            kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid                                    \
-        }                                                                                                             \
-        , {kCLOCK_Pwm1, kCLOCK_Pwm1, kCLOCK_Pwm1, kCLOCK_Pwm1}, {kCLOCK_Pwm2, kCLOCK_Pwm2, kCLOCK_Pwm2, kCLOCK_Pwm2}, \
-            {kCLOCK_Pwm3, kCLOCK_Pwm3, kCLOCK_Pwm3, kCLOCK_Pwm3},                                                     \
-        {                                                                                                             \
-            kCLOCK_Pwm4, kCLOCK_Pwm4, kCLOCK_Pwm4, kCLOCK_Pwm4                                                        \
-        }                                                                                                             \
+#define PWM_CLOCKS                                                                \
+    {                                                                             \
+        {kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid}, \
+            {kCLOCK_Pwm1, kCLOCK_Pwm1, kCLOCK_Pwm1, kCLOCK_Pwm1},                 \
+            {kCLOCK_Pwm2, kCLOCK_Pwm2, kCLOCK_Pwm2, kCLOCK_Pwm2},                 \
+            {kCLOCK_Pwm3, kCLOCK_Pwm3, kCLOCK_Pwm3, kCLOCK_Pwm3},                 \
+        {                                                                         \
+            kCLOCK_Pwm4, kCLOCK_Pwm4, kCLOCK_Pwm4, kCLOCK_Pwm4                    \
+        }                                                                         \
     }
 
 /*! @brief Clock ip name array for PXP. */
@@ -393,18 +395,18 @@ extern volatile uint32_t g_rtcXtalFreq;
 /*! @brief Clock name used to get clock frequency. */
 typedef enum _clock_name
 {
-    kCLOCK_CpuClk = 0x0U,  /*!< CPU clock */
-    kCLOCK_AhbClk = 0x1U,  /*!< AHB clock */
+    kCLOCK_CpuClk  = 0x0U, /*!< CPU clock */
+    kCLOCK_AhbClk  = 0x1U, /*!< AHB clock */
     kCLOCK_SemcClk = 0x2U, /*!< SEMC clock */
-    kCLOCK_IpgClk = 0x3U,  /*!< IPG clock */
-    kCLOCK_PerClk = 0x4U,  /*!< PER clock */
+    kCLOCK_IpgClk  = 0x3U, /*!< IPG clock */
+    kCLOCK_PerClk  = 0x4U, /*!< PER clock */
 
     kCLOCK_OscClk = 0x5U, /*!< OSC clock selected by PMU_LOWPWR_CTRL[OSC_SEL]. */
     kCLOCK_RtcClk = 0x6U, /*!< RTC clock. (RTCCLK) */
 
     kCLOCK_ArmPllClk = 0x7U, /*!< ARMPLLCLK. */
 
-    kCLOCK_Usb1PllClk = 0x8U,     /*!< USB1PLLCLK. */
+    kCLOCK_Usb1PllClk     = 0x8U, /*!< USB1PLLCLK. */
     kCLOCK_Usb1PllPfd0Clk = 0x9U, /*!< USB1PLLPDF0CLK. */
     kCLOCK_Usb1PllPfd1Clk = 0xAU, /*!< USB1PLLPFD1CLK. */
     kCLOCK_Usb1PllPfd2Clk = 0xBU, /*!< USB1PLLPFD2CLK. */
@@ -412,7 +414,7 @@ typedef enum _clock_name
 
     kCLOCK_Usb2PllClk = 0xDU, /*!< USB2PLLCLK. */
 
-    kCLOCK_SysPllClk = 0xEU,      /*!< SYSPLLCLK. */
+    kCLOCK_SysPllClk     = 0xEU,  /*!< SYSPLLCLK. */
     kCLOCK_SysPllPfd0Clk = 0xFU,  /*!< SYSPLLPDF0CLK. */
     kCLOCK_SysPllPfd1Clk = 0x10U, /*!< SYSPLLPFD1CLK. */
     kCLOCK_SysPllPfd2Clk = 0x11U, /*!< SYSPLLPFD2CLK. */
@@ -436,151 +438,151 @@ typedef enum _clock_ip_name
     kCLOCK_IpInvalid = -1,
 
     /* CCM CCGR0 */
-    kCLOCK_Aips_tz1 = (0U << 8U) | CCM_CCGR0_CG0_SHIFT,    /*!< CCGR0, CG0   */
-    kCLOCK_Aips_tz2 = (0U << 8U) | CCM_CCGR0_CG1_SHIFT,    /*!< CCGR0, CG1   */
-    kCLOCK_Mqs = (0U << 8U) | CCM_CCGR0_CG2_SHIFT,         /*!< CCGR0, CG2   */
-    kCLOCK_FlexSpiExsc = (0U << 8U) | CCM_CCGR0_CG3_SHIFT, /*!< CCGR0, CG3   */
-    kCLOCK_Sim_M_Main = (0U << 8U) | CCM_CCGR0_CG4_SHIFT,  /*!< CCGR0, CG4   */
-    kCLOCK_Dcp = (0U << 8U) | CCM_CCGR0_CG5_SHIFT,         /*!< CCGR0, CG5   */
-    kCLOCK_Lpuart3 = (0U << 8U) | CCM_CCGR0_CG6_SHIFT,     /*!< CCGR0, CG6   */
-    kCLOCK_Can1 = (0U << 8U) | CCM_CCGR0_CG7_SHIFT,        /*!< CCGR0, CG7   */
-    kCLOCK_Can1S = (0U << 8U) | CCM_CCGR0_CG8_SHIFT,       /*!< CCGR0, CG8   */
-    kCLOCK_Can2 = (0U << 8U) | CCM_CCGR0_CG9_SHIFT,        /*!< CCGR0, CG9   */
-    kCLOCK_Can2S = (0U << 8U) | CCM_CCGR0_CG10_SHIFT,      /*!< CCGR0, CG10  */
-    kCLOCK_Trace = (0U << 8U) | CCM_CCGR0_CG11_SHIFT,      /*!< CCGR0, CG11  */
-    kCLOCK_Gpt2 = (0U << 8U) | CCM_CCGR0_CG12_SHIFT,       /*!< CCGR0, CG12  */
-    kCLOCK_Gpt2S = (0U << 8U) | CCM_CCGR0_CG13_SHIFT,      /*!< CCGR0, CG13  */
-    kCLOCK_Lpuart2 = (0U << 8U) | CCM_CCGR0_CG14_SHIFT,    /*!< CCGR0, CG14  */
-    kCLOCK_Gpio2 = (0U << 8U) | CCM_CCGR0_CG15_SHIFT,      /*!< CCGR0, CG15  */
+    kCLOCK_Aips_tz1    = (0U << 8U) | CCM_CCGR0_CG0_SHIFT,  /*!< CCGR0, CG0   */
+    kCLOCK_Aips_tz2    = (0U << 8U) | CCM_CCGR0_CG1_SHIFT,  /*!< CCGR0, CG1   */
+    kCLOCK_Mqs         = (0U << 8U) | CCM_CCGR0_CG2_SHIFT,  /*!< CCGR0, CG2   */
+    kCLOCK_FlexSpiExsc = (0U << 8U) | CCM_CCGR0_CG3_SHIFT,  /*!< CCGR0, CG3   */
+    kCLOCK_Sim_M_Main  = (0U << 8U) | CCM_CCGR0_CG4_SHIFT,  /*!< CCGR0, CG4   */
+    kCLOCK_Dcp         = (0U << 8U) | CCM_CCGR0_CG5_SHIFT,  /*!< CCGR0, CG5   */
+    kCLOCK_Lpuart3     = (0U << 8U) | CCM_CCGR0_CG6_SHIFT,  /*!< CCGR0, CG6   */
+    kCLOCK_Can1        = (0U << 8U) | CCM_CCGR0_CG7_SHIFT,  /*!< CCGR0, CG7   */
+    kCLOCK_Can1S       = (0U << 8U) | CCM_CCGR0_CG8_SHIFT,  /*!< CCGR0, CG8   */
+    kCLOCK_Can2        = (0U << 8U) | CCM_CCGR0_CG9_SHIFT,  /*!< CCGR0, CG9   */
+    kCLOCK_Can2S       = (0U << 8U) | CCM_CCGR0_CG10_SHIFT, /*!< CCGR0, CG10  */
+    kCLOCK_Trace       = (0U << 8U) | CCM_CCGR0_CG11_SHIFT, /*!< CCGR0, CG11  */
+    kCLOCK_Gpt2        = (0U << 8U) | CCM_CCGR0_CG12_SHIFT, /*!< CCGR0, CG12  */
+    kCLOCK_Gpt2S       = (0U << 8U) | CCM_CCGR0_CG13_SHIFT, /*!< CCGR0, CG13  */
+    kCLOCK_Lpuart2     = (0U << 8U) | CCM_CCGR0_CG14_SHIFT, /*!< CCGR0, CG14  */
+    kCLOCK_Gpio2       = (0U << 8U) | CCM_CCGR0_CG15_SHIFT, /*!< CCGR0, CG15  */
 
     /* CCM CCGR1 */
-    kCLOCK_Lpspi1 = (1U << 8U) | CCM_CCGR1_CG0_SHIFT,   /*!< CCGR1, CG0   */
-    kCLOCK_Lpspi2 = (1U << 8U) | CCM_CCGR1_CG1_SHIFT,   /*!< CCGR1, CG1   */
-    kCLOCK_Lpspi3 = (1U << 8U) | CCM_CCGR1_CG2_SHIFT,   /*!< CCGR1, CG2   */
-    kCLOCK_Lpspi4 = (1U << 8U) | CCM_CCGR1_CG3_SHIFT,   /*!< CCGR1, CG3   */
-    kCLOCK_Adc2 = (1U << 8U) | CCM_CCGR1_CG4_SHIFT,     /*!< CCGR1, CG4   */
-    kCLOCK_Enet = (1U << 8U) | CCM_CCGR1_CG5_SHIFT,     /*!< CCGR1, CG5   */
-    kCLOCK_Pit = (1U << 8U) | CCM_CCGR1_CG6_SHIFT,      /*!< CCGR1, CG6   */
-    kCLOCK_Aoi2 = (1U << 8U) | CCM_CCGR1_CG7_SHIFT,     /*!< CCGR1, CG7   */
-    kCLOCK_Adc1 = (1U << 8U) | CCM_CCGR1_CG8_SHIFT,     /*!< CCGR1, CG8   */
-    kCLOCK_SemcExsc = (1U << 8U) | CCM_CCGR1_CG9_SHIFT, /*!< CCGR1, CG9   */
-    kCLOCK_Gpt1 = (1U << 8U) | CCM_CCGR1_CG10_SHIFT,    /*!< CCGR1, CG10  */
-    kCLOCK_Gpt1S = (1U << 8U) | CCM_CCGR1_CG11_SHIFT,   /*!< CCGR1, CG11  */
-    kCLOCK_Lpuart4 = (1U << 8U) | CCM_CCGR1_CG12_SHIFT, /*!< CCGR1, CG12  */
-    kCLOCK_Gpio1 = (1U << 8U) | CCM_CCGR1_CG13_SHIFT,   /*!< CCGR1, CG13  */
-    kCLOCK_Csu = (1U << 8U) | CCM_CCGR1_CG14_SHIFT,     /*!< CCGR1, CG14  */
-    kCLOCK_Gpio5 = (1U << 8U) | CCM_CCGR1_CG15_SHIFT,   /*!< CCGR1, CG15  */
+    kCLOCK_Lpspi1   = (1U << 8U) | CCM_CCGR1_CG0_SHIFT,  /*!< CCGR1, CG0   */
+    kCLOCK_Lpspi2   = (1U << 8U) | CCM_CCGR1_CG1_SHIFT,  /*!< CCGR1, CG1   */
+    kCLOCK_Lpspi3   = (1U << 8U) | CCM_CCGR1_CG2_SHIFT,  /*!< CCGR1, CG2   */
+    kCLOCK_Lpspi4   = (1U << 8U) | CCM_CCGR1_CG3_SHIFT,  /*!< CCGR1, CG3   */
+    kCLOCK_Adc2     = (1U << 8U) | CCM_CCGR1_CG4_SHIFT,  /*!< CCGR1, CG4   */
+    kCLOCK_Enet     = (1U << 8U) | CCM_CCGR1_CG5_SHIFT,  /*!< CCGR1, CG5   */
+    kCLOCK_Pit      = (1U << 8U) | CCM_CCGR1_CG6_SHIFT,  /*!< CCGR1, CG6   */
+    kCLOCK_Aoi2     = (1U << 8U) | CCM_CCGR1_CG7_SHIFT,  /*!< CCGR1, CG7   */
+    kCLOCK_Adc1     = (1U << 8U) | CCM_CCGR1_CG8_SHIFT,  /*!< CCGR1, CG8   */
+    kCLOCK_SemcExsc = (1U << 8U) | CCM_CCGR1_CG9_SHIFT,  /*!< CCGR1, CG9   */
+    kCLOCK_Gpt1     = (1U << 8U) | CCM_CCGR1_CG10_SHIFT, /*!< CCGR1, CG10  */
+    kCLOCK_Gpt1S    = (1U << 8U) | CCM_CCGR1_CG11_SHIFT, /*!< CCGR1, CG11  */
+    kCLOCK_Lpuart4  = (1U << 8U) | CCM_CCGR1_CG12_SHIFT, /*!< CCGR1, CG12  */
+    kCLOCK_Gpio1    = (1U << 8U) | CCM_CCGR1_CG13_SHIFT, /*!< CCGR1, CG13  */
+    kCLOCK_Csu      = (1U << 8U) | CCM_CCGR1_CG14_SHIFT, /*!< CCGR1, CG14  */
+    kCLOCK_Gpio5    = (1U << 8U) | CCM_CCGR1_CG15_SHIFT, /*!< CCGR1, CG15  */
 
     /* CCM CCGR2 */
-    kCLOCK_OcramExsc = (2U << 8U) | CCM_CCGR2_CG0_SHIFT,  /*!< CCGR2, CG0   */
-    kCLOCK_Csi = (2U << 8U) | CCM_CCGR2_CG1_SHIFT,        /*!< CCGR2, CG1   */
-    kCLOCK_IomuxcSnvs = (2U << 8U) | CCM_CCGR2_CG2_SHIFT, /*!< CCGR2, CG2   */
-    kCLOCK_Lpi2c1 = (2U << 8U) | CCM_CCGR2_CG3_SHIFT,     /*!< CCGR2, CG3   */
-    kCLOCK_Lpi2c2 = (2U << 8U) | CCM_CCGR2_CG4_SHIFT,     /*!< CCGR2, CG4   */
-    kCLOCK_Lpi2c3 = (2U << 8U) | CCM_CCGR2_CG5_SHIFT,     /*!< CCGR2, CG5   */
-    kCLOCK_Ocotp = (2U << 8U) | CCM_CCGR2_CG6_SHIFT,      /*!< CCGR2, CG6   */
-    kCLOCK_Xbar3 = (2U << 8U) | CCM_CCGR2_CG7_SHIFT,      /*!< CCGR2, CG7   */
-    kCLOCK_Ipmux1 = (2U << 8U) | CCM_CCGR2_CG8_SHIFT,     /*!< CCGR2, CG8   */
-    kCLOCK_Ipmux2 = (2U << 8U) | CCM_CCGR2_CG9_SHIFT,     /*!< CCGR2, CG9   */
-    kCLOCK_Ipmux3 = (2U << 8U) | CCM_CCGR2_CG10_SHIFT,    /*!< CCGR2, CG10  */
-    kCLOCK_Xbar1 = (2U << 8U) | CCM_CCGR2_CG11_SHIFT,     /*!< CCGR2, CG11  */
-    kCLOCK_Xbar2 = (2U << 8U) | CCM_CCGR2_CG12_SHIFT,     /*!< CCGR2, CG12  */
-    kCLOCK_Gpio3 = (2U << 8U) | CCM_CCGR2_CG13_SHIFT,     /*!< CCGR2, CG13  */
-    kCLOCK_Lcd = (2U << 8U) | CCM_CCGR2_CG14_SHIFT,       /*!< CCGR2, CG14  */
-    kCLOCK_Pxp = (2U << 8U) | CCM_CCGR2_CG15_SHIFT,       /*!< CCGR2, CG15  */
+    kCLOCK_OcramExsc  = (2U << 8U) | CCM_CCGR2_CG0_SHIFT,  /*!< CCGR2, CG0   */
+    kCLOCK_Csi        = (2U << 8U) | CCM_CCGR2_CG1_SHIFT,  /*!< CCGR2, CG1   */
+    kCLOCK_IomuxcSnvs = (2U << 8U) | CCM_CCGR2_CG2_SHIFT,  /*!< CCGR2, CG2   */
+    kCLOCK_Lpi2c1     = (2U << 8U) | CCM_CCGR2_CG3_SHIFT,  /*!< CCGR2, CG3   */
+    kCLOCK_Lpi2c2     = (2U << 8U) | CCM_CCGR2_CG4_SHIFT,  /*!< CCGR2, CG4   */
+    kCLOCK_Lpi2c3     = (2U << 8U) | CCM_CCGR2_CG5_SHIFT,  /*!< CCGR2, CG5   */
+    kCLOCK_Ocotp      = (2U << 8U) | CCM_CCGR2_CG6_SHIFT,  /*!< CCGR2, CG6   */
+    kCLOCK_Xbar3      = (2U << 8U) | CCM_CCGR2_CG7_SHIFT,  /*!< CCGR2, CG7   */
+    kCLOCK_Ipmux1     = (2U << 8U) | CCM_CCGR2_CG8_SHIFT,  /*!< CCGR2, CG8   */
+    kCLOCK_Ipmux2     = (2U << 8U) | CCM_CCGR2_CG9_SHIFT,  /*!< CCGR2, CG9   */
+    kCLOCK_Ipmux3     = (2U << 8U) | CCM_CCGR2_CG10_SHIFT, /*!< CCGR2, CG10  */
+    kCLOCK_Xbar1      = (2U << 8U) | CCM_CCGR2_CG11_SHIFT, /*!< CCGR2, CG11  */
+    kCLOCK_Xbar2      = (2U << 8U) | CCM_CCGR2_CG12_SHIFT, /*!< CCGR2, CG12  */
+    kCLOCK_Gpio3      = (2U << 8U) | CCM_CCGR2_CG13_SHIFT, /*!< CCGR2, CG13  */
+    kCLOCK_Lcd        = (2U << 8U) | CCM_CCGR2_CG14_SHIFT, /*!< CCGR2, CG14  */
+    kCLOCK_Pxp        = (2U << 8U) | CCM_CCGR2_CG15_SHIFT, /*!< CCGR2, CG15  */
 
     /* CCM CCGR3 */
-    kCLOCK_Flexio2 = (3U << 8U) | CCM_CCGR3_CG0_SHIFT,        /*!< CCGR3, CG0   */
-    kCLOCK_Lpuart5 = (3U << 8U) | CCM_CCGR3_CG1_SHIFT,        /*!< CCGR3, CG1   */
-    kCLOCK_Semc = (3U << 8U) | CCM_CCGR3_CG2_SHIFT,           /*!< CCGR3, CG2   */
-    kCLOCK_Lpuart6 = (3U << 8U) | CCM_CCGR3_CG3_SHIFT,        /*!< CCGR3, CG3   */
-    kCLOCK_Aoi1 = (3U << 8U) | CCM_CCGR3_CG4_SHIFT,           /*!< CCGR3, CG4   */
-    kCLOCK_LcdPixel = (3U << 8U) | CCM_CCGR3_CG5_SHIFT,       /*!< CCGR3, CG5   */
-    kCLOCK_Gpio4 = (3U << 8U) | CCM_CCGR3_CG6_SHIFT,          /*!< CCGR3, CG6   */
-    kCLOCK_Ewm0 = (3U << 8U) | CCM_CCGR3_CG7_SHIFT,           /*!< CCGR3, CG7   */
-    kCLOCK_Wdog1 = (3U << 8U) | CCM_CCGR3_CG8_SHIFT,          /*!< CCGR3, CG8   */
-    kCLOCK_FlexRam = (3U << 8U) | CCM_CCGR3_CG9_SHIFT,        /*!< CCGR3, CG9   */
-    kCLOCK_Acmp1 = (3U << 8U) | CCM_CCGR3_CG10_SHIFT,         /*!< CCGR3, CG10  */
-    kCLOCK_Acmp2 = (3U << 8U) | CCM_CCGR3_CG11_SHIFT,         /*!< CCGR3, CG11  */
-    kCLOCK_Acmp3 = (3U << 8U) | CCM_CCGR3_CG12_SHIFT,         /*!< CCGR3, CG12  */
-    kCLOCK_Acmp4 = (3U << 8U) | CCM_CCGR3_CG13_SHIFT,         /*!< CCGR3, CG13  */
-    kCLOCK_Ocram = (3U << 8U) | CCM_CCGR3_CG14_SHIFT,         /*!< CCGR3, CG14  */
+    kCLOCK_Flexio2       = (3U << 8U) | CCM_CCGR3_CG0_SHIFT,  /*!< CCGR3, CG0   */
+    kCLOCK_Lpuart5       = (3U << 8U) | CCM_CCGR3_CG1_SHIFT,  /*!< CCGR3, CG1   */
+    kCLOCK_Semc          = (3U << 8U) | CCM_CCGR3_CG2_SHIFT,  /*!< CCGR3, CG2   */
+    kCLOCK_Lpuart6       = (3U << 8U) | CCM_CCGR3_CG3_SHIFT,  /*!< CCGR3, CG3   */
+    kCLOCK_Aoi1          = (3U << 8U) | CCM_CCGR3_CG4_SHIFT,  /*!< CCGR3, CG4   */
+    kCLOCK_LcdPixel      = (3U << 8U) | CCM_CCGR3_CG5_SHIFT,  /*!< CCGR3, CG5   */
+    kCLOCK_Gpio4         = (3U << 8U) | CCM_CCGR3_CG6_SHIFT,  /*!< CCGR3, CG6   */
+    kCLOCK_Ewm0          = (3U << 8U) | CCM_CCGR3_CG7_SHIFT,  /*!< CCGR3, CG7   */
+    kCLOCK_Wdog1         = (3U << 8U) | CCM_CCGR3_CG8_SHIFT,  /*!< CCGR3, CG8   */
+    kCLOCK_FlexRam       = (3U << 8U) | CCM_CCGR3_CG9_SHIFT,  /*!< CCGR3, CG9   */
+    kCLOCK_Acmp1         = (3U << 8U) | CCM_CCGR3_CG10_SHIFT, /*!< CCGR3, CG10  */
+    kCLOCK_Acmp2         = (3U << 8U) | CCM_CCGR3_CG11_SHIFT, /*!< CCGR3, CG11  */
+    kCLOCK_Acmp3         = (3U << 8U) | CCM_CCGR3_CG12_SHIFT, /*!< CCGR3, CG12  */
+    kCLOCK_Acmp4         = (3U << 8U) | CCM_CCGR3_CG13_SHIFT, /*!< CCGR3, CG13  */
+    kCLOCK_Ocram         = (3U << 8U) | CCM_CCGR3_CG14_SHIFT, /*!< CCGR3, CG14  */
     kCLOCK_IomuxcSnvsGpr = (3U << 8U) | CCM_CCGR3_CG15_SHIFT, /*!< CCGR3, CG15  */
 
     /* CCM CCGR4 */
-    kCLOCK_Iomuxc = (4U << 8U) | CCM_CCGR4_CG1_SHIFT,    /*!< CCGR4, CG1   */
-    kCLOCK_IomuxcGpr = (4U << 8U) | CCM_CCGR4_CG2_SHIFT, /*!< CCGR4, CG2   */
-    kCLOCK_Bee = (4U << 8U) | CCM_CCGR4_CG3_SHIFT,       /*!< CCGR4, CG3   */
-    kCLOCK_SimM7 = (4U << 8U) | CCM_CCGR4_CG4_SHIFT,     /*!< CCGR4, CG4   */
-    kCLOCK_Tsc = (4U << 8U) | CCM_CCGR4_CG5_SHIFT,       /*!< CCGR4, CG5   */
-    kCLOCK_SimM = (4U << 8U) | CCM_CCGR4_CG6_SHIFT,      /*!< CCGR4, CG6   */
-    kCLOCK_SimEms = (4U << 8U) | CCM_CCGR4_CG7_SHIFT,    /*!< CCGR4, CG7   */
-    kCLOCK_Pwm1 = (4U << 8U) | CCM_CCGR4_CG8_SHIFT,      /*!< CCGR4, CG8   */
-    kCLOCK_Pwm2 = (4U << 8U) | CCM_CCGR4_CG9_SHIFT,      /*!< CCGR4, CG9   */
-    kCLOCK_Pwm3 = (4U << 8U) | CCM_CCGR4_CG10_SHIFT,     /*!< CCGR4, CG10  */
-    kCLOCK_Pwm4 = (4U << 8U) | CCM_CCGR4_CG11_SHIFT,     /*!< CCGR4, CG11  */
-    kCLOCK_Enc1 = (4U << 8U) | CCM_CCGR4_CG12_SHIFT,     /*!< CCGR4, CG12  */
-    kCLOCK_Enc2 = (4U << 8U) | CCM_CCGR4_CG13_SHIFT,     /*!< CCGR4, CG13  */
-    kCLOCK_Enc3 = (4U << 8U) | CCM_CCGR4_CG14_SHIFT,     /*!< CCGR4, CG14  */
-    kCLOCK_Enc4 = (4U << 8U) | CCM_CCGR4_CG15_SHIFT,     /*!< CCGR4, CG15  */
+    kCLOCK_Iomuxc    = (4U << 8U) | CCM_CCGR4_CG1_SHIFT,  /*!< CCGR4, CG1   */
+    kCLOCK_IomuxcGpr = (4U << 8U) | CCM_CCGR4_CG2_SHIFT,  /*!< CCGR4, CG2   */
+    kCLOCK_Bee       = (4U << 8U) | CCM_CCGR4_CG3_SHIFT,  /*!< CCGR4, CG3   */
+    kCLOCK_SimM7     = (4U << 8U) | CCM_CCGR4_CG4_SHIFT,  /*!< CCGR4, CG4   */
+    kCLOCK_Tsc       = (4U << 8U) | CCM_CCGR4_CG5_SHIFT,  /*!< CCGR4, CG5   */
+    kCLOCK_SimM      = (4U << 8U) | CCM_CCGR4_CG6_SHIFT,  /*!< CCGR4, CG6   */
+    kCLOCK_SimEms    = (4U << 8U) | CCM_CCGR4_CG7_SHIFT,  /*!< CCGR4, CG7   */
+    kCLOCK_Pwm1      = (4U << 8U) | CCM_CCGR4_CG8_SHIFT,  /*!< CCGR4, CG8   */
+    kCLOCK_Pwm2      = (4U << 8U) | CCM_CCGR4_CG9_SHIFT,  /*!< CCGR4, CG9   */
+    kCLOCK_Pwm3      = (4U << 8U) | CCM_CCGR4_CG10_SHIFT, /*!< CCGR4, CG10  */
+    kCLOCK_Pwm4      = (4U << 8U) | CCM_CCGR4_CG11_SHIFT, /*!< CCGR4, CG11  */
+    kCLOCK_Enc1      = (4U << 8U) | CCM_CCGR4_CG12_SHIFT, /*!< CCGR4, CG12  */
+    kCLOCK_Enc2      = (4U << 8U) | CCM_CCGR4_CG13_SHIFT, /*!< CCGR4, CG13  */
+    kCLOCK_Enc3      = (4U << 8U) | CCM_CCGR4_CG14_SHIFT, /*!< CCGR4, CG14  */
+    kCLOCK_Enc4      = (4U << 8U) | CCM_CCGR4_CG15_SHIFT, /*!< CCGR4, CG15  */
 
     /* CCM CCGR5 */
-    kCLOCK_Rom = (5U << 8U) | CCM_CCGR5_CG0_SHIFT,      /*!< CCGR5, CG0   */
-    kCLOCK_Flexio1 = (5U << 8U) | CCM_CCGR5_CG1_SHIFT,  /*!< CCGR5, CG1   */
-    kCLOCK_Wdog3 = (5U << 8U) | CCM_CCGR5_CG2_SHIFT,    /*!< CCGR5, CG2   */
-    kCLOCK_Dma = (5U << 8U) | CCM_CCGR5_CG3_SHIFT,      /*!< CCGR5, CG3   */
-    kCLOCK_Kpp = (5U << 8U) | CCM_CCGR5_CG4_SHIFT,      /*!< CCGR5, CG4   */
-    kCLOCK_Wdog2 = (5U << 8U) | CCM_CCGR5_CG5_SHIFT,    /*!< CCGR5, CG5   */
-    kCLOCK_Aips_tz4 = (5U << 8U) | CCM_CCGR5_CG6_SHIFT, /*!< CCGR5, CG6   */
-    kCLOCK_Spdif = (5U << 8U) | CCM_CCGR5_CG7_SHIFT,    /*!< CCGR5, CG7   */
-    kCLOCK_SimMain = (5U << 8U) | CCM_CCGR5_CG8_SHIFT,  /*!< CCGR5, CG8   */
-    kCLOCK_Sai1 = (5U << 8U) | CCM_CCGR5_CG9_SHIFT,     /*!< CCGR5, CG9   */
-    kCLOCK_Sai2 = (5U << 8U) | CCM_CCGR5_CG10_SHIFT,    /*!< CCGR5, CG10  */
-    kCLOCK_Sai3 = (5U << 8U) | CCM_CCGR5_CG11_SHIFT,    /*!< CCGR5, CG11  */
-    kCLOCK_Lpuart1 = (5U << 8U) | CCM_CCGR5_CG12_SHIFT, /*!< CCGR5, CG12  */
-    kCLOCK_Lpuart7 = (5U << 8U) | CCM_CCGR5_CG13_SHIFT, /*!< CCGR5, CG13  */
-    kCLOCK_SnvsHp = (5U << 8U) | CCM_CCGR5_CG14_SHIFT,  /*!< CCGR5, CG14  */
-    kCLOCK_SnvsLp = (5U << 8U) | CCM_CCGR5_CG15_SHIFT,  /*!< CCGR5, CG15  */
+    kCLOCK_Rom      = (5U << 8U) | CCM_CCGR5_CG0_SHIFT,  /*!< CCGR5, CG0   */
+    kCLOCK_Flexio1  = (5U << 8U) | CCM_CCGR5_CG1_SHIFT,  /*!< CCGR5, CG1   */
+    kCLOCK_Wdog3    = (5U << 8U) | CCM_CCGR5_CG2_SHIFT,  /*!< CCGR5, CG2   */
+    kCLOCK_Dma      = (5U << 8U) | CCM_CCGR5_CG3_SHIFT,  /*!< CCGR5, CG3   */
+    kCLOCK_Kpp      = (5U << 8U) | CCM_CCGR5_CG4_SHIFT,  /*!< CCGR5, CG4   */
+    kCLOCK_Wdog2    = (5U << 8U) | CCM_CCGR5_CG5_SHIFT,  /*!< CCGR5, CG5   */
+    kCLOCK_Aips_tz4 = (5U << 8U) | CCM_CCGR5_CG6_SHIFT,  /*!< CCGR5, CG6   */
+    kCLOCK_Spdif    = (5U << 8U) | CCM_CCGR5_CG7_SHIFT,  /*!< CCGR5, CG7   */
+    kCLOCK_SimMain  = (5U << 8U) | CCM_CCGR5_CG8_SHIFT,  /*!< CCGR5, CG8   */
+    kCLOCK_Sai1     = (5U << 8U) | CCM_CCGR5_CG9_SHIFT,  /*!< CCGR5, CG9   */
+    kCLOCK_Sai2     = (5U << 8U) | CCM_CCGR5_CG10_SHIFT, /*!< CCGR5, CG10  */
+    kCLOCK_Sai3     = (5U << 8U) | CCM_CCGR5_CG11_SHIFT, /*!< CCGR5, CG11  */
+    kCLOCK_Lpuart1  = (5U << 8U) | CCM_CCGR5_CG12_SHIFT, /*!< CCGR5, CG12  */
+    kCLOCK_Lpuart7  = (5U << 8U) | CCM_CCGR5_CG13_SHIFT, /*!< CCGR5, CG13  */
+    kCLOCK_SnvsHp   = (5U << 8U) | CCM_CCGR5_CG14_SHIFT, /*!< CCGR5, CG14  */
+    kCLOCK_SnvsLp   = (5U << 8U) | CCM_CCGR5_CG15_SHIFT, /*!< CCGR5, CG15  */
 
     /* CCM CCGR6 */
-    kCLOCK_UsbOh3 = (6U << 8U) | CCM_CCGR6_CG0_SHIFT,   /*!< CCGR6, CG0   */
-    kCLOCK_Usdhc1 = (6U << 8U) | CCM_CCGR6_CG1_SHIFT,   /*!< CCGR6, CG1   */
-    kCLOCK_Usdhc2 = (6U << 8U) | CCM_CCGR6_CG2_SHIFT,   /*!< CCGR6, CG2   */
-    kCLOCK_Dcdc = (6U << 8U) | CCM_CCGR6_CG3_SHIFT,     /*!< CCGR6, CG3   */
-    kCLOCK_Ipmux4 = (6U << 8U) | CCM_CCGR6_CG4_SHIFT,   /*!< CCGR6, CG4   */
-    kCLOCK_FlexSpi = (6U << 8U) | CCM_CCGR6_CG5_SHIFT,  /*!< CCGR6, CG5   */
-    kCLOCK_Trng = (6U << 8U) | CCM_CCGR6_CG6_SHIFT,     /*!< CCGR6, CG6   */
-    kCLOCK_Lpuart8 = (6U << 8U) | CCM_CCGR6_CG7_SHIFT,  /*!< CCGR6, CG7   */
-    kCLOCK_Timer4 = (6U << 8U) | CCM_CCGR6_CG8_SHIFT,   /*!< CCGR6, CG8   */
-    kCLOCK_Aips_tz3 = (6U << 8U) | CCM_CCGR6_CG9_SHIFT, /*!< CCGR6, CG9   */
-    kCLOCK_SimPer = (6U << 8U) | CCM_CCGR6_CG10_SHIFT,  /*!< CCGR6, CG10  */
-    kCLOCK_Anadig = (6U << 8U) | CCM_CCGR6_CG11_SHIFT,  /*!< CCGR6, CG11  */
-    kCLOCK_Lpi2c4 = (6U << 8U) | CCM_CCGR6_CG12_SHIFT,  /*!< CCGR6, CG12  */
-    kCLOCK_Timer1 = (6U << 8U) | CCM_CCGR6_CG13_SHIFT,  /*!< CCGR6, CG13  */
-    kCLOCK_Timer2 = (6U << 8U) | CCM_CCGR6_CG14_SHIFT,  /*!< CCGR6, CG14  */
-    kCLOCK_Timer3 = (6U << 8U) | CCM_CCGR6_CG15_SHIFT,  /*!< CCGR6, CG15  */
+    kCLOCK_UsbOh3   = (6U << 8U) | CCM_CCGR6_CG0_SHIFT,  /*!< CCGR6, CG0   */
+    kCLOCK_Usdhc1   = (6U << 8U) | CCM_CCGR6_CG1_SHIFT,  /*!< CCGR6, CG1   */
+    kCLOCK_Usdhc2   = (6U << 8U) | CCM_CCGR6_CG2_SHIFT,  /*!< CCGR6, CG2   */
+    kCLOCK_Dcdc     = (6U << 8U) | CCM_CCGR6_CG3_SHIFT,  /*!< CCGR6, CG3   */
+    kCLOCK_Ipmux4   = (6U << 8U) | CCM_CCGR6_CG4_SHIFT,  /*!< CCGR6, CG4   */
+    kCLOCK_FlexSpi  = (6U << 8U) | CCM_CCGR6_CG5_SHIFT,  /*!< CCGR6, CG5   */
+    kCLOCK_Trng     = (6U << 8U) | CCM_CCGR6_CG6_SHIFT,  /*!< CCGR6, CG6   */
+    kCLOCK_Lpuart8  = (6U << 8U) | CCM_CCGR6_CG7_SHIFT,  /*!< CCGR6, CG7   */
+    kCLOCK_Timer4   = (6U << 8U) | CCM_CCGR6_CG8_SHIFT,  /*!< CCGR6, CG8   */
+    kCLOCK_Aips_tz3 = (6U << 8U) | CCM_CCGR6_CG9_SHIFT,  /*!< CCGR6, CG9   */
+    kCLOCK_SimPer   = (6U << 8U) | CCM_CCGR6_CG10_SHIFT, /*!< CCGR6, CG10  */
+    kCLOCK_Anadig   = (6U << 8U) | CCM_CCGR6_CG11_SHIFT, /*!< CCGR6, CG11  */
+    kCLOCK_Lpi2c4   = (6U << 8U) | CCM_CCGR6_CG12_SHIFT, /*!< CCGR6, CG12  */
+    kCLOCK_Timer1   = (6U << 8U) | CCM_CCGR6_CG13_SHIFT, /*!< CCGR6, CG13  */
+    kCLOCK_Timer2   = (6U << 8U) | CCM_CCGR6_CG14_SHIFT, /*!< CCGR6, CG14  */
+    kCLOCK_Timer3   = (6U << 8U) | CCM_CCGR6_CG15_SHIFT, /*!< CCGR6, CG15  */
 
 } clock_ip_name_t;
 
 /*! @brief OSC 24M sorce select */
 typedef enum _clock_osc
 {
-    kCLOCK_RcOsc = 0U,   /*!< On chip OSC. */
+    kCLOCK_RcOsc   = 0U, /*!< On chip OSC. */
     kCLOCK_XtalOsc = 1U, /*!< 24M Xtal OSC */
 } clock_osc_t;
 
 /*! @brief Clock gate value */
 typedef enum _clock_gate_value
 {
-    kCLOCK_ClockNotNeeded = 0U,     /*!< Clock is off during all modes. */
-    kCLOCK_ClockNeededRun = 1U,     /*!< Clock is on in run mode, but off in WAIT and STOP modes */
+    kCLOCK_ClockNotNeeded     = 0U, /*!< Clock is off during all modes. */
+    kCLOCK_ClockNeededRun     = 1U, /*!< Clock is on in run mode, but off in WAIT and STOP modes */
     kCLOCK_ClockNeededRunWait = 3U, /*!< Clock is on during all modes, except STOP mode */
 } clock_gate_value_t;
 
 /*! @brief System clock mode */
 typedef enum _clock_mode_t
 {
-    kCLOCK_ModeRun = 0U,  /*!< Remain in run mode. */
+    kCLOCK_ModeRun  = 0U, /*!< Remain in run mode. */
     kCLOCK_ModeWait = 1U, /*!< Transfer to wait mode. */
     kCLOCK_ModeStop = 2U, /*!< Transfer to stop mode. */
 } clock_mode_t;
@@ -600,7 +602,7 @@ typedef enum _clock_mux
                                  CCM_CCSR_PLL3_SW_CLK_SEL_MASK,
                                  CCM_NO_BUSY_WAIT), /*!< pll3_sw_clk mux name */
 
-    kCLOCK_PeriphMux = CCM_TUPLE(CBCDR_OFFSET,
+    kCLOCK_PeriphMux  = CCM_TUPLE(CBCDR_OFFSET,
                                  CCM_CBCDR_PERIPH_CLK_SEL_SHIFT,
                                  CCM_CBCDR_PERIPH_CLK_SEL_MASK,
                                  CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_SHIFT), /*!< periph mux name */
@@ -608,41 +610,53 @@ typedef enum _clock_mux
                                   CCM_CBCDR_SEMC_ALT_CLK_SEL_SHIFT,
                                   CCM_CBCDR_SEMC_ALT_CLK_SEL_MASK,
                                   CCM_NO_BUSY_WAIT), /*!< semc mux name */
-    kCLOCK_SemcMux = CCM_TUPLE(
-        CBCDR_OFFSET, CCM_CBCDR_SEMC_CLK_SEL_SHIFT, CCM_CBCDR_SEMC_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< semc mux name */
+    kCLOCK_SemcMux    = CCM_TUPLE(CBCDR_OFFSET,
+                               CCM_CBCDR_SEMC_CLK_SEL_SHIFT,
+                               CCM_CBCDR_SEMC_CLK_SEL_MASK,
+                               CCM_NO_BUSY_WAIT), /*!< semc mux name */
 
-    kCLOCK_PrePeriphMux = CCM_TUPLE(CBCMR_OFFSET,
+    kCLOCK_PrePeriphMux  = CCM_TUPLE(CBCMR_OFFSET,
                                     CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT,
                                     CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK,
                                     CCM_NO_BUSY_WAIT), /*!< pre-periph mux name */
-    kCLOCK_TraceMux = CCM_TUPLE(
-        CBCMR_OFFSET, CCM_CBCMR_TRACE_CLK_SEL_SHIFT, CCM_CBCMR_TRACE_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< trace mux name */
+    kCLOCK_TraceMux      = CCM_TUPLE(CBCMR_OFFSET,
+                                CCM_CBCMR_TRACE_CLK_SEL_SHIFT,
+                                CCM_CBCMR_TRACE_CLK_SEL_MASK,
+                                CCM_NO_BUSY_WAIT), /*!< trace mux name */
     kCLOCK_PeriphClk2Mux = CCM_TUPLE(CBCMR_OFFSET,
                                      CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT,
                                      CCM_CBCMR_PERIPH_CLK2_SEL_MASK,
                                      CCM_NO_BUSY_WAIT), /*!< periph clock2 mux name */
-    kCLOCK_LpspiMux = CCM_TUPLE(
-        CBCMR_OFFSET, CCM_CBCMR_LPSPI_CLK_SEL_SHIFT, CCM_CBCMR_LPSPI_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< lpspi mux name */
+    kCLOCK_LpspiMux      = CCM_TUPLE(CBCMR_OFFSET,
+                                CCM_CBCMR_LPSPI_CLK_SEL_SHIFT,
+                                CCM_CBCMR_LPSPI_CLK_SEL_MASK,
+                                CCM_NO_BUSY_WAIT), /*!< lpspi mux name */
 
     kCLOCK_FlexspiMux = CCM_TUPLE(CSCMR1_OFFSET,
                                   CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT,
                                   CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK,
                                   CCM_NO_BUSY_WAIT), /*!< flexspi mux name */
-    kCLOCK_Usdhc2Mux = CCM_TUPLE(CSCMR1_OFFSET,
+    kCLOCK_Usdhc2Mux  = CCM_TUPLE(CSCMR1_OFFSET,
                                  CCM_CSCMR1_USDHC2_CLK_SEL_SHIFT,
                                  CCM_CSCMR1_USDHC2_CLK_SEL_MASK,
                                  CCM_NO_BUSY_WAIT), /*!< usdhc2 mux name */
-    kCLOCK_Usdhc1Mux = CCM_TUPLE(CSCMR1_OFFSET,
+    kCLOCK_Usdhc1Mux  = CCM_TUPLE(CSCMR1_OFFSET,
                                  CCM_CSCMR1_USDHC1_CLK_SEL_SHIFT,
                                  CCM_CSCMR1_USDHC1_CLK_SEL_MASK,
                                  CCM_NO_BUSY_WAIT), /*!< usdhc1 mux name */
-    kCLOCK_Sai3Mux = CCM_TUPLE(
-        CSCMR1_OFFSET, CCM_CSCMR1_SAI3_CLK_SEL_SHIFT, CCM_CSCMR1_SAI3_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< sai3 mux name */
-    kCLOCK_Sai2Mux = CCM_TUPLE(
-        CSCMR1_OFFSET, CCM_CSCMR1_SAI2_CLK_SEL_SHIFT, CCM_CSCMR1_SAI2_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< sai2 mux name */
-    kCLOCK_Sai1Mux = CCM_TUPLE(
-        CSCMR1_OFFSET, CCM_CSCMR1_SAI1_CLK_SEL_SHIFT, CCM_CSCMR1_SAI1_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< sai1 mux name */
-    kCLOCK_PerclkMux = CCM_TUPLE(CSCMR1_OFFSET,
+    kCLOCK_Sai3Mux    = CCM_TUPLE(CSCMR1_OFFSET,
+                               CCM_CSCMR1_SAI3_CLK_SEL_SHIFT,
+                               CCM_CSCMR1_SAI3_CLK_SEL_MASK,
+                               CCM_NO_BUSY_WAIT), /*!< sai3 mux name */
+    kCLOCK_Sai2Mux    = CCM_TUPLE(CSCMR1_OFFSET,
+                               CCM_CSCMR1_SAI2_CLK_SEL_SHIFT,
+                               CCM_CSCMR1_SAI2_CLK_SEL_MASK,
+                               CCM_NO_BUSY_WAIT), /*!< sai2 mux name */
+    kCLOCK_Sai1Mux    = CCM_TUPLE(CSCMR1_OFFSET,
+                               CCM_CSCMR1_SAI1_CLK_SEL_SHIFT,
+                               CCM_CSCMR1_SAI1_CLK_SEL_MASK,
+                               CCM_NO_BUSY_WAIT), /*!< sai1 mux name */
+    kCLOCK_PerclkMux  = CCM_TUPLE(CSCMR1_OFFSET,
                                  CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT,
                                  CCM_CSCMR1_PERCLK_CLK_SEL_MASK,
                                  CCM_NO_BUSY_WAIT), /*!< perclk mux name */
@@ -651,28 +665,38 @@ typedef enum _clock_mux
                                   CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT,
                                   CCM_CSCMR2_FLEXIO2_CLK_SEL_MASK,
                                   CCM_NO_BUSY_WAIT), /*!< flexio2 mux name */
-    kCLOCK_CanMux = CCM_TUPLE(
-        CSCMR2_OFFSET, CCM_CSCMR2_CAN_CLK_SEL_SHIFT, CCM_CSCMR2_CAN_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< can mux name */
-
-    kCLOCK_UartMux = CCM_TUPLE(
-        CSCDR1_OFFSET, CCM_CSCDR1_UART_CLK_SEL_SHIFT, CCM_CSCDR1_UART_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< uart mux name */
-
-    kCLOCK_SpdifMux = CCM_TUPLE(
-        CDCDR_OFFSET, CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT, CCM_CDCDR_SPDIF0_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< spdif mux name */
+    kCLOCK_CanMux     = CCM_TUPLE(CSCMR2_OFFSET,
+                              CCM_CSCMR2_CAN_CLK_SEL_SHIFT,
+                              CCM_CSCMR2_CAN_CLK_SEL_MASK,
+                              CCM_NO_BUSY_WAIT), /*!< can mux name */
+
+    kCLOCK_UartMux = CCM_TUPLE(CSCDR1_OFFSET,
+                               CCM_CSCDR1_UART_CLK_SEL_SHIFT,
+                               CCM_CSCDR1_UART_CLK_SEL_MASK,
+                               CCM_NO_BUSY_WAIT), /*!< uart mux name */
+
+    kCLOCK_SpdifMux   = CCM_TUPLE(CDCDR_OFFSET,
+                                CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT,
+                                CCM_CDCDR_SPDIF0_CLK_SEL_MASK,
+                                CCM_NO_BUSY_WAIT), /*!< spdif mux name */
     kCLOCK_Flexio1Mux = CCM_TUPLE(CDCDR_OFFSET,
                                   CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT,
                                   CCM_CDCDR_FLEXIO1_CLK_SEL_MASK,
                                   CCM_NO_BUSY_WAIT), /*!< flexio1 mux name */
 
-    kCLOCK_Lpi2cMux = CCM_TUPLE(
-        CSCDR2_OFFSET, CCM_CSCDR2_LPI2C_CLK_SEL_SHIFT, CCM_CSCDR2_LPI2C_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< lpi2c mux name */
+    kCLOCK_Lpi2cMux    = CCM_TUPLE(CSCDR2_OFFSET,
+                                CCM_CSCDR2_LPI2C_CLK_SEL_SHIFT,
+                                CCM_CSCDR2_LPI2C_CLK_SEL_MASK,
+                                CCM_NO_BUSY_WAIT), /*!< lpi2c mux name */
     kCLOCK_LcdifPreMux = CCM_TUPLE(CSCDR2_OFFSET,
                                    CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT,
                                    CCM_CSCDR2_LCDIF_PRE_CLK_SEL_MASK,
                                    CCM_NO_BUSY_WAIT), /*!< lcdif pre mux name */
 
-    kCLOCK_CsiMux = CCM_TUPLE(
-        CSCDR3_OFFSET, CCM_CSCDR3_CSI_CLK_SEL_SHIFT, CCM_CSCDR3_CSI_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< csi mux name */
+    kCLOCK_CsiMux = CCM_TUPLE(CSCDR3_OFFSET,
+                              CCM_CSCDR3_CSI_CLK_SEL_SHIFT,
+                              CCM_CSCDR3_CSI_CLK_SEL_MASK,
+                              CCM_NO_BUSY_WAIT), /*!< csi mux name */
 } clock_mux_t;
 
 /*!
@@ -685,77 +709,101 @@ typedef enum _clock_mux
  */
 typedef enum _clock_div
 {
-    kCLOCK_ArmDiv = CCM_TUPLE(
-        CACRR_OFFSET, CCM_CACRR_ARM_PODF_SHIFT, CCM_CACRR_ARM_PODF_MASK, CCM_CDHIPR_ARM_PODF_BUSY_SHIFT), /*!< core div name */
+    kCLOCK_ArmDiv = CCM_TUPLE(CACRR_OFFSET,
+                              CCM_CACRR_ARM_PODF_SHIFT,
+                              CCM_CACRR_ARM_PODF_MASK,
+                              CCM_CDHIPR_ARM_PODF_BUSY_SHIFT), /*!< core div name */
 
     kCLOCK_PeriphClk2Div = CCM_TUPLE(CBCDR_OFFSET,
                                      CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT,
                                      CCM_CBCDR_PERIPH_CLK2_PODF_MASK,
                                      CCM_NO_BUSY_WAIT), /*!< periph clock2 div name */
-    kCLOCK_SemcDiv = CCM_TUPLE(CBCDR_OFFSET,
+    kCLOCK_SemcDiv       = CCM_TUPLE(CBCDR_OFFSET,
                                CCM_CBCDR_SEMC_PODF_SHIFT,
                                CCM_CBCDR_SEMC_PODF_MASK,
                                CCM_CDHIPR_SEMC_PODF_BUSY_SHIFT), /*!< semc div name */
-    kCLOCK_AhbDiv = CCM_TUPLE(
-        CBCDR_OFFSET, CCM_CBCDR_AHB_PODF_SHIFT, CCM_CBCDR_AHB_PODF_MASK, CCM_CDHIPR_AHB_PODF_BUSY_SHIFT), /*!< ahb div name */
-    kCLOCK_IpgDiv =
-        CCM_TUPLE(CBCDR_OFFSET, CCM_CBCDR_IPG_PODF_SHIFT, CCM_CBCDR_IPG_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< ipg div name */
+    kCLOCK_AhbDiv        = CCM_TUPLE(CBCDR_OFFSET,
+                              CCM_CBCDR_AHB_PODF_SHIFT,
+                              CCM_CBCDR_AHB_PODF_MASK,
+                              CCM_CDHIPR_AHB_PODF_BUSY_SHIFT), /*!< ahb div name */
+    kCLOCK_IpgDiv        = CCM_TUPLE(
+        CBCDR_OFFSET, CCM_CBCDR_IPG_PODF_SHIFT, CCM_CBCDR_IPG_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< ipg div name */
 
     kCLOCK_LpspiDiv = CCM_TUPLE(
         CBCMR_OFFSET, CCM_CBCMR_LPSPI_PODF_SHIFT, CCM_CBCMR_LPSPI_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< lpspi div name */
     kCLOCK_LcdifDiv = CCM_TUPLE(
         CBCMR_OFFSET, CCM_CBCMR_LCDIF_PODF_SHIFT, CCM_CBCMR_LCDIF_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< lcdif div name */
 
-    kCLOCK_FlexspiDiv = CCM_TUPLE(
-        CSCMR1_OFFSET, CCM_CSCMR1_FLEXSPI_PODF_SHIFT, CCM_CSCMR1_FLEXSPI_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< flexspi div name */
-    kCLOCK_PerclkDiv = CCM_TUPLE(
-        CSCMR1_OFFSET, CCM_CSCMR1_PERCLK_PODF_SHIFT, CCM_CSCMR1_PERCLK_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< perclk div name */
-
-    kCLOCK_CanDiv = CCM_TUPLE(
-        CSCMR2_OFFSET, CCM_CSCMR2_CAN_CLK_PODF_SHIFT, CCM_CSCMR2_CAN_CLK_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< can div name */
-
-    kCLOCK_TraceDiv = CCM_TUPLE(
-        CSCDR1_OFFSET, CCM_CSCDR1_TRACE_PODF_SHIFT, CCM_CSCDR1_TRACE_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< trace div name */
-    kCLOCK_Usdhc2Div = CCM_TUPLE(
-        CSCDR1_OFFSET, CCM_CSCDR1_USDHC2_PODF_SHIFT, CCM_CSCDR1_USDHC2_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< usdhc2 div name */
-    kCLOCK_Usdhc1Div = CCM_TUPLE(
-        CSCDR1_OFFSET, CCM_CSCDR1_USDHC1_PODF_SHIFT, CCM_CSCDR1_USDHC1_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< usdhc1 div name */
-    kCLOCK_UartDiv = CCM_TUPLE(
-        CSCDR1_OFFSET, CCM_CSCDR1_UART_CLK_PODF_SHIFT, CCM_CSCDR1_UART_CLK_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< uart div name */
-
-    kCLOCK_Flexio2Div = CCM_TUPLE(CS1CDR_OFFSET,
+    kCLOCK_FlexspiDiv = CCM_TUPLE(CSCMR1_OFFSET,
+                                  CCM_CSCMR1_FLEXSPI_PODF_SHIFT,
+                                  CCM_CSCMR1_FLEXSPI_PODF_MASK,
+                                  CCM_NO_BUSY_WAIT), /*!< flexspi div name */
+    kCLOCK_PerclkDiv  = CCM_TUPLE(CSCMR1_OFFSET,
+                                 CCM_CSCMR1_PERCLK_PODF_SHIFT,
+                                 CCM_CSCMR1_PERCLK_PODF_MASK,
+                                 CCM_NO_BUSY_WAIT), /*!< perclk div name */
+
+    kCLOCK_CanDiv = CCM_TUPLE(CSCMR2_OFFSET,
+                              CCM_CSCMR2_CAN_CLK_PODF_SHIFT,
+                              CCM_CSCMR2_CAN_CLK_PODF_MASK,
+                              CCM_NO_BUSY_WAIT), /*!< can div name */
+
+    kCLOCK_TraceDiv  = CCM_TUPLE(CSCDR1_OFFSET,
+                                CCM_CSCDR1_TRACE_PODF_SHIFT,
+                                CCM_CSCDR1_TRACE_PODF_MASK,
+                                CCM_NO_BUSY_WAIT), /*!< trace div name */
+    kCLOCK_Usdhc2Div = CCM_TUPLE(CSCDR1_OFFSET,
+                                 CCM_CSCDR1_USDHC2_PODF_SHIFT,
+                                 CCM_CSCDR1_USDHC2_PODF_MASK,
+                                 CCM_NO_BUSY_WAIT), /*!< usdhc2 div name */
+    kCLOCK_Usdhc1Div = CCM_TUPLE(CSCDR1_OFFSET,
+                                 CCM_CSCDR1_USDHC1_PODF_SHIFT,
+                                 CCM_CSCDR1_USDHC1_PODF_MASK,
+                                 CCM_NO_BUSY_WAIT), /*!< usdhc1 div name */
+    kCLOCK_UartDiv   = CCM_TUPLE(CSCDR1_OFFSET,
+                               CCM_CSCDR1_UART_CLK_PODF_SHIFT,
+                               CCM_CSCDR1_UART_CLK_PODF_MASK,
+                               CCM_NO_BUSY_WAIT), /*!< uart div name */
+
+    kCLOCK_Flexio2Div    = CCM_TUPLE(CS1CDR_OFFSET,
                                   CCM_CS1CDR_FLEXIO2_CLK_PODF_SHIFT,
                                   CCM_CS1CDR_FLEXIO2_CLK_PODF_MASK,
                                   CCM_NO_BUSY_WAIT), /*!< flexio2 pre div name */
-    kCLOCK_Sai3PreDiv = CCM_TUPLE(CS1CDR_OFFSET,
+    kCLOCK_Sai3PreDiv    = CCM_TUPLE(CS1CDR_OFFSET,
                                   CCM_CS1CDR_SAI3_CLK_PRED_SHIFT,
                                   CCM_CS1CDR_SAI3_CLK_PRED_MASK,
                                   CCM_NO_BUSY_WAIT), /*!< sai3 pre div name */
-    kCLOCK_Sai3Div = CCM_TUPLE(
-        CS1CDR_OFFSET, CCM_CS1CDR_SAI3_CLK_PODF_SHIFT, CCM_CS1CDR_SAI3_CLK_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< sai3 div name */
+    kCLOCK_Sai3Div       = CCM_TUPLE(CS1CDR_OFFSET,
+                               CCM_CS1CDR_SAI3_CLK_PODF_SHIFT,
+                               CCM_CS1CDR_SAI3_CLK_PODF_MASK,
+                               CCM_NO_BUSY_WAIT), /*!< sai3 div name */
     kCLOCK_Flexio2PreDiv = CCM_TUPLE(CS1CDR_OFFSET,
                                      CCM_CS1CDR_FLEXIO2_CLK_PRED_SHIFT,
                                      CCM_CS1CDR_FLEXIO2_CLK_PRED_MASK,
                                      CCM_NO_BUSY_WAIT), /*!< sai3 pre div name */
-    kCLOCK_Sai1PreDiv = CCM_TUPLE(CS1CDR_OFFSET,
+    kCLOCK_Sai1PreDiv    = CCM_TUPLE(CS1CDR_OFFSET,
                                   CCM_CS1CDR_SAI1_CLK_PRED_SHIFT,
                                   CCM_CS1CDR_SAI1_CLK_PRED_MASK,
                                   CCM_NO_BUSY_WAIT), /*!< sai1 pre div name */
-    kCLOCK_Sai1Div = CCM_TUPLE(
-        CS1CDR_OFFSET, CCM_CS1CDR_SAI1_CLK_PODF_SHIFT, CCM_CS1CDR_SAI1_CLK_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< sai1 div name */
+    kCLOCK_Sai1Div       = CCM_TUPLE(CS1CDR_OFFSET,
+                               CCM_CS1CDR_SAI1_CLK_PODF_SHIFT,
+                               CCM_CS1CDR_SAI1_CLK_PODF_MASK,
+                               CCM_NO_BUSY_WAIT), /*!< sai1 div name */
 
     kCLOCK_Sai2PreDiv = CCM_TUPLE(CS2CDR_OFFSET,
                                   CCM_CS2CDR_SAI2_CLK_PRED_SHIFT,
                                   CCM_CS2CDR_SAI2_CLK_PRED_MASK,
                                   CCM_NO_BUSY_WAIT), /*!< sai2 pre div name */
-    kCLOCK_Sai2Div = CCM_TUPLE(
-        CS2CDR_OFFSET, CCM_CS2CDR_SAI2_CLK_PODF_SHIFT, CCM_CS2CDR_SAI2_CLK_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< sai2 div name */
+    kCLOCK_Sai2Div    = CCM_TUPLE(CS2CDR_OFFSET,
+                               CCM_CS2CDR_SAI2_CLK_PODF_SHIFT,
+                               CCM_CS2CDR_SAI2_CLK_PODF_MASK,
+                               CCM_NO_BUSY_WAIT), /*!< sai2 div name */
 
-    kCLOCK_Spdif0PreDiv = CCM_TUPLE(CDCDR_OFFSET,
+    kCLOCK_Spdif0PreDiv  = CCM_TUPLE(CDCDR_OFFSET,
                                     CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT,
                                     CCM_CDCDR_SPDIF0_CLK_PRED_MASK,
                                     CCM_NO_BUSY_WAIT), /*!< spdif pre div name */
-    kCLOCK_Spdif0Div = CCM_TUPLE(CDCDR_OFFSET,
+    kCLOCK_Spdif0Div     = CCM_TUPLE(CDCDR_OFFSET,
                                  CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT,
                                  CCM_CDCDR_SPDIF0_CLK_PODF_MASK,
                                  CCM_NO_BUSY_WAIT), /*!< spdif div name */
@@ -763,26 +811,28 @@ typedef enum _clock_div
                                      CCM_CDCDR_FLEXIO1_CLK_PRED_SHIFT,
                                      CCM_CDCDR_FLEXIO1_CLK_PRED_MASK,
                                      CCM_NO_BUSY_WAIT), /*!< flexio1 pre div name */
-    kCLOCK_Flexio1Div = CCM_TUPLE(CDCDR_OFFSET,
+    kCLOCK_Flexio1Div    = CCM_TUPLE(CDCDR_OFFSET,
                                   CCM_CDCDR_FLEXIO1_CLK_PODF_SHIFT,
                                   CCM_CDCDR_FLEXIO1_CLK_PODF_MASK,
                                   CCM_NO_BUSY_WAIT), /*!< flexio1 div name */
 
-    kCLOCK_Lpi2cDiv = CCM_TUPLE(CSCDR2_OFFSET,
+    kCLOCK_Lpi2cDiv    = CCM_TUPLE(CSCDR2_OFFSET,
                                 CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT,
                                 CCM_CSCDR2_LPI2C_CLK_PODF_MASK,
                                 CCM_NO_BUSY_WAIT), /*!< lpi2c div name */
-    kCLOCK_LcdifPreDiv = CCM_TUPLE(
-        CSCDR2_OFFSET, CCM_CSCDR2_LCDIF_PRED_SHIFT, CCM_CSCDR2_LCDIF_PRED_MASK, CCM_NO_BUSY_WAIT), /*!< lcdif pre div name */
+    kCLOCK_LcdifPreDiv = CCM_TUPLE(CSCDR2_OFFSET,
+                                   CCM_CSCDR2_LCDIF_PRED_SHIFT,
+                                   CCM_CSCDR2_LCDIF_PRED_MASK,
+                                   CCM_NO_BUSY_WAIT), /*!< lcdif pre div name */
 
-    kCLOCK_CsiDiv =
-        CCM_TUPLE(CSCDR3_OFFSET, CCM_CSCDR3_CSI_PODF_SHIFT, CCM_CSCDR3_CSI_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< csi div name */
+    kCLOCK_CsiDiv = CCM_TUPLE(
+        CSCDR3_OFFSET, CCM_CSCDR3_CSI_PODF_SHIFT, CCM_CSCDR3_CSI_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< csi div name */
 } clock_div_t;
 
 /*! @brief USB clock source definition. */
 typedef enum _clock_usb_src
 {
-    kCLOCK_Usb480M = 0,                     /*!< Use 480M.      */
+    kCLOCK_Usb480M      = 0,                /*!< Use 480M.      */
     kCLOCK_UsbSrcUnused = (int)0xFFFFFFFFU, /*!< Used when the function does not
                                             care the clock source. */
 } clock_usb_src_t;
@@ -797,7 +847,7 @@ typedef enum _clock_usb_phy_src
 enum _clock_pll_clk_src
 {
     kCLOCK_PllClkSrc24M = 0U, /*!< Pll clock source 24M */
-    kCLOCK_PllSrcClkPN = 1U,  /*!< Pll clock source CLK1_P and CLK1_N */
+    kCLOCK_PllSrcClkPN  = 1U, /*!< Pll clock source CLK1_P and CLK1_N */
 };
 
 /*! @brief PLL configuration for ARM */
@@ -871,9 +921,9 @@ typedef struct _clock_enet_pll_config
 /*! @brief PLL name */
 typedef enum _clock_pll
 {
-    kCLOCK_PllArm = CCM_ANALOG_TUPLE(PLL_ARM_OFFSET, CCM_ANALOG_PLL_ARM_ENABLE_SHIFT),       /*!< PLL ARM */
-    kCLOCK_PllSys = CCM_ANALOG_TUPLE(PLL_SYS_OFFSET, CCM_ANALOG_PLL_SYS_ENABLE_SHIFT),       /*!< PLL SYS */
-    kCLOCK_PllUsb1 = CCM_ANALOG_TUPLE(PLL_USB1_OFFSET, CCM_ANALOG_PLL_USB1_ENABLE_SHIFT),    /*!< PLL USB1 */
+    kCLOCK_PllArm   = CCM_ANALOG_TUPLE(PLL_ARM_OFFSET, CCM_ANALOG_PLL_ARM_ENABLE_SHIFT),     /*!< PLL ARM */
+    kCLOCK_PllSys   = CCM_ANALOG_TUPLE(PLL_SYS_OFFSET, CCM_ANALOG_PLL_SYS_ENABLE_SHIFT),     /*!< PLL SYS */
+    kCLOCK_PllUsb1  = CCM_ANALOG_TUPLE(PLL_USB1_OFFSET, CCM_ANALOG_PLL_USB1_ENABLE_SHIFT),   /*!< PLL USB1 */
     kCLOCK_PllAudio = CCM_ANALOG_TUPLE(PLL_AUDIO_OFFSET, CCM_ANALOG_PLL_AUDIO_ENABLE_SHIFT), /*!< PLL Audio */
     kCLOCK_PllVideo = CCM_ANALOG_TUPLE(PLL_VIDEO_OFFSET, CCM_ANALOG_PLL_VIDEO_ENABLE_SHIFT), /*!< PLL Video */
 
@@ -912,7 +962,7 @@ static inline void CLOCK_SetMux(clock_mux_t mux, uint32_t value)
 {
     uint32_t busyShift;
 
-    busyShift = CCM_TUPLE_BUSY_SHIFT(mux);
+    busyShift               = CCM_TUPLE_BUSY_SHIFT(mux);
     CCM_TUPLE_REG(CCM, mux) = (CCM_TUPLE_REG(CCM, mux) & (~CCM_TUPLE_MASK(mux))) |
                               (((uint32_t)((value) << CCM_TUPLE_SHIFT(mux))) & CCM_TUPLE_MASK(mux));
 
@@ -949,7 +999,7 @@ static inline void CLOCK_SetDiv(clock_div_t divider, uint32_t value)
 {
     uint32_t busyShift;
 
-    busyShift = CCM_TUPLE_BUSY_SHIFT(divider);
+    busyShift                   = CCM_TUPLE_BUSY_SHIFT(divider);
     CCM_TUPLE_REG(CCM, divider) = (CCM_TUPLE_REG(CCM, divider) & (~CCM_TUPLE_MASK(divider))) |
                                   (((uint32_t)((value) << CCM_TUPLE_SHIFT(divider))) & CCM_TUPLE_MASK(divider));
 
@@ -989,7 +1039,7 @@ static inline void CLOCK_ControlGate(clock_ip_name_t name, clock_gate_value_t va
 
     assert(index <= 6);
 
-    reg = ((volatile uint32_t *)&CCM->CCGR0) + index;
+    reg  = ((volatile uint32_t *)&CCM->CCGR0) + index;
     *reg = ((*reg) & ~(3U << shift)) | (((uint32_t)value) << shift);
 }
 
@@ -1489,6 +1539,16 @@ bool CLOCK_EnableUsbhs1PhyPllClock(clock_usb_phy_src_t src, uint32_t freq);
  */
 void CLOCK_DisableUsbhs1PhyPllClock(void);
 
+/*!
+ * @brief Use DWT to delay at least for some time.
+ *  Please note that, this API will calculate the microsecond period with the maximum
+ *  supported CPU frequency, so this API will only delay for at least the given microseconds, if precise
+ *  delay count was needed, please implement a new timer count to achieve this function.
+ *
+ * @param delay_us  Delay time in unit of microsecond.
+ */
+void SDK_DelayAtLeastUs(uint32_t delay_us);
+
 /* @} */
 
 #if defined(__cplusplus)
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_cmp.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_cmp.c
index 98039cd6f96..806703bac8e 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_cmp.c
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_cmp.c
@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
  * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
  *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include "fsl_cmp.h"
@@ -39,7 +13,6 @@
 #define FSL_COMPONENT_ID "platform.drivers.cmp"
 #endif
 
-
 /*******************************************************************************
  * Prototypes
  ******************************************************************************/
@@ -81,6 +54,19 @@ static uint32_t CMP_GetInstance(CMP_Type *base)
     return instance;
 }
 
+/*!
+ * brief Initializes the CMP.
+ *
+ * This function initializes the CMP module. The operations included are as follows.
+ * - Enabling the clock for CMP module.
+ * - Configuring the comparator.
+ * - Enabling the CMP module.
+ * Note that for some devices, multiple CMP instances share the same clock gate. In this case, to enable the clock for
+ * any instance enables all CMPs. See the appropriate MCU reference manual for the clock assignment of the CMP.
+ *
+ * param base   CMP peripheral base address.
+ * param config Pointer to the configuration structure.
+ */
 void CMP_Init(CMP_Type *base, const cmp_config_t *config)
 {
     assert(NULL != config);
@@ -95,43 +81,56 @@ void CMP_Init(CMP_Type *base, const cmp_config_t *config)
     /* Configure. */
     CMP_Enable(base, false); /* Disable the CMP module during configuring. */
     /* CMPx_CR1. */
-    tmp8 = base->CR1 & ~(CMP_CR1_PMODE_MASK | CMP_CR1_INV_MASK | CMP_CR1_COS_MASK | CMP_CR1_OPE_MASK);
-    if (config->enableHighSpeed)
+    tmp8 = (uint8_t)(base->CR1 & ~(CMP_CR1_PMODE_MASK | CMP_CR1_INV_MASK | CMP_CR1_COS_MASK | CMP_CR1_OPE_MASK));
+    if (true == config->enableHighSpeed)
     {
         tmp8 |= CMP_CR1_PMODE_MASK;
     }
-    if (config->enableInvertOutput)
+    if (true == config->enableInvertOutput)
     {
         tmp8 |= CMP_CR1_INV_MASK;
     }
-    if (config->useUnfilteredOutput)
+    if (true == config->useUnfilteredOutput)
     {
         tmp8 |= CMP_CR1_COS_MASK;
     }
-    if (config->enablePinOut)
+    if (true == config->enablePinOut)
     {
         tmp8 |= CMP_CR1_OPE_MASK;
     }
 #if defined(FSL_FEATURE_CMP_HAS_TRIGGER_MODE) && FSL_FEATURE_CMP_HAS_TRIGGER_MODE
-    if (config->enableTriggerMode)
+    if (true == config->enableTriggerMode)
     {
         tmp8 |= CMP_CR1_TRIGM_MASK;
     }
     else
     {
-        tmp8 &= ~CMP_CR1_TRIGM_MASK;
+        tmp8 &= ~(uint8_t)CMP_CR1_TRIGM_MASK;
     }
 #endif /* FSL_FEATURE_CMP_HAS_TRIGGER_MODE */
     base->CR1 = tmp8;
 
     /* CMPx_CR0. */
-    tmp8 = base->CR0 & ~CMP_CR0_HYSTCTR_MASK;
+    tmp8 = base->CR0 & ~(uint8_t)CMP_CR0_HYSTCTR_MASK;
     tmp8 |= CMP_CR0_HYSTCTR(config->hysteresisMode);
     base->CR0 = tmp8;
 
     CMP_Enable(base, config->enableCmp); /* Enable the CMP module after configured or not. */
 }
 
+/*!
+ * brief De-initializes the CMP module.
+ *
+ * This function de-initializes the CMP module. The operations included are as follows.
+ * - Disabling the CMP module.
+ * - Disabling the clock for CMP module.
+ *
+ * This function disables the clock for the CMP.
+ * Note that for some devices, multiple CMP instances share the same clock gate. In this case, before disabling the
+ * clock for the CMP, ensure that all the CMP instances are not used.
+ *
+ * param base CMP peripheral base address.
+ */
 void CMP_Deinit(CMP_Type *base)
 {
     /* Disable the CMP module. */
@@ -143,34 +142,74 @@ void CMP_Deinit(CMP_Type *base)
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }
 
+/*!
+ * brief Initializes the CMP user configuration structure.
+ *
+ * This function initializes the user configuration structure to these default values.
+ * code
+ *   config->enableCmp           = true;
+ *   config->hysteresisMode      = kCMP_HysteresisLevel0;
+ *   config->enableHighSpeed     = false;
+ *   config->enableInvertOutput  = false;
+ *   config->useUnfilteredOutput = false;
+ *   config->enablePinOut        = false;
+ *   config->enableTriggerMode   = false;
+ * endcode
+ * param config Pointer to the configuration structure.
+ */
 void CMP_GetDefaultConfig(cmp_config_t *config)
 {
     assert(NULL != config);
 
-    config->enableCmp = true; /* Enable the CMP module after initialization. */
-    config->hysteresisMode = kCMP_HysteresisLevel0;
-    config->enableHighSpeed = false;
-    config->enableInvertOutput = false;
+    /* Initializes the configure structure to zero. */
+    (void)memset(config, 0, sizeof(*config));
+
+    config->enableCmp           = true; /* Enable the CMP module after initialization. */
+    config->hysteresisMode      = kCMP_HysteresisLevel0;
+    config->enableHighSpeed     = false;
+    config->enableInvertOutput  = false;
     config->useUnfilteredOutput = false;
-    config->enablePinOut = false;
+    config->enablePinOut        = false;
 #if defined(FSL_FEATURE_CMP_HAS_TRIGGER_MODE) && FSL_FEATURE_CMP_HAS_TRIGGER_MODE
     config->enableTriggerMode = false;
 #endif /* FSL_FEATURE_CMP_HAS_TRIGGER_MODE */
 }
 
+/*!
+ * brief  Sets the input channels for the comparator.
+ *
+ * This function sets the input channels for the comparator.
+ * Note that two input channels cannot be set the same way in the application. When the user selects the same input
+ * from the analog mux to the positive and negative port, the comparator is disabled automatically.
+ *
+ * param  base            CMP peripheral base address.
+ * param  positiveChannel Positive side input channel number. Available range is 0-7.
+ * param  negativeChannel Negative side input channel number. Available range is 0-7.
+ */
 void CMP_SetInputChannels(CMP_Type *base, uint8_t positiveChannel, uint8_t negativeChannel)
 {
     uint8_t tmp8 = base->MUXCR;
 
-    tmp8 &= ~(CMP_MUXCR_PSEL_MASK | CMP_MUXCR_MSEL_MASK);
+    tmp8 &= ~(uint8_t)(CMP_MUXCR_PSEL_MASK | CMP_MUXCR_MSEL_MASK);
     tmp8 |= CMP_MUXCR_PSEL(positiveChannel) | CMP_MUXCR_MSEL(negativeChannel);
     base->MUXCR = tmp8;
 }
 
 #if defined(FSL_FEATURE_CMP_HAS_DMA) && FSL_FEATURE_CMP_HAS_DMA
+/*!
+ * brief Enables/disables the DMA request for rising/falling events.
+ *
+ * This function enables/disables the DMA request for rising/falling events. Either event triggers the generation of
+ * the DMA request from CMP if the DMA feature is enabled. Both events are ignored for generating the DMA request from
+ * the CMP
+ * if the DMA is disabled.
+ *
+ * param base CMP peripheral base address.
+ * param enable Enables or disables the feature.
+ */
 void CMP_EnableDMA(CMP_Type *base, bool enable)
 {
-    uint8_t tmp8 = base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK); /* To avoid change the w1c bits. */
+    uint8_t tmp8 = (uint8_t)(base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK)); /* To avoid change the w1c bits. */
 
     if (enable)
     {
@@ -178,12 +217,18 @@ void CMP_EnableDMA(CMP_Type *base, bool enable)
     }
     else
     {
-        tmp8 &= ~CMP_SCR_DMAEN_MASK;
+        tmp8 &= ~(uint8_t)CMP_SCR_DMAEN_MASK;
     }
     base->SCR = tmp8;
 }
 #endif /* FSL_FEATURE_CMP_HAS_DMA */
 
+/*!
+ * brief  Configures the filter.
+ *
+ * param  base   CMP peripheral base address.
+ * param  config Pointer to the configuration structure.
+ */
 void CMP_SetFilterConfig(CMP_Type *base, const cmp_filter_config_t *config)
 {
     assert(NULL != config);
@@ -202,13 +247,19 @@ void CMP_SetFilterConfig(CMP_Type *base, const cmp_filter_config_t *config)
     }
 #endif /* FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT */
     /* Set the filter count. */
-    tmp8 = base->CR0 & ~CMP_CR0_FILTER_CNT_MASK;
+    tmp8 = (uint8_t)(base->CR0 & ~CMP_CR0_FILTER_CNT_MASK);
     tmp8 |= CMP_CR0_FILTER_CNT(config->filterCount);
     base->CR0 = tmp8;
     /* Set the filter period. It is used as the divider to bus clock. */
     base->FPR = CMP_FPR_FILT_PER(config->filterPeriod);
 }
 
+/*!
+ * brief Configures the internal DAC.
+ *
+ * param base   CMP peripheral base address.
+ * param config Pointer to the configuration structure. "NULL" disables the feature.
+ */
 void CMP_SetDACConfig(CMP_Type *base, const cmp_dac_config_t *config)
 {
     uint8_t tmp8 = 0U;
@@ -230,64 +281,89 @@ void CMP_SetDACConfig(CMP_Type *base, const cmp_dac_config_t *config)
     base->DACCR = tmp8;
 }
 
+/*!
+ * brief Enables the interrupts.
+ *
+ * param base    CMP peripheral base address.
+ * param mask    Mask value for interrupts. See "_cmp_interrupt_enable".
+ */
 void CMP_EnableInterrupts(CMP_Type *base, uint32_t mask)
 {
-    uint8_t tmp8 = base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK); /* To avoid change the w1c bits. */
+    uint8_t tmp8 = (uint8_t)(base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK)); /* To avoid change the w1c bits. */
 
-    if (0U != (kCMP_OutputRisingInterruptEnable & mask))
+    if (0U != ((uint32_t)kCMP_OutputRisingInterruptEnable & mask))
     {
         tmp8 |= CMP_SCR_IER_MASK;
     }
-    if (0U != (kCMP_OutputFallingInterruptEnable & mask))
+    if (0U != ((uint32_t)kCMP_OutputFallingInterruptEnable & mask))
     {
         tmp8 |= CMP_SCR_IEF_MASK;
     }
     base->SCR = tmp8;
 }
 
+/*!
+ * brief Disables the interrupts.
+ *
+ * param base    CMP peripheral base address.
+ * param mask    Mask value for interrupts. See "_cmp_interrupt_enable".
+ */
 void CMP_DisableInterrupts(CMP_Type *base, uint32_t mask)
 {
-    uint8_t tmp8 = base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK); /* To avoid change the w1c bits. */
+    uint8_t tmp8 = (uint8_t)(base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK)); /* To avoid change the w1c bits. */
 
-    if (0U != (kCMP_OutputRisingInterruptEnable & mask))
+    if (0U != ((uint32_t)kCMP_OutputRisingInterruptEnable & mask))
     {
-        tmp8 &= ~CMP_SCR_IER_MASK;
+        tmp8 &= ~(uint8_t)CMP_SCR_IER_MASK;
     }
-    if (0U != (kCMP_OutputFallingInterruptEnable & mask))
+    if (0U != ((uint32_t)kCMP_OutputFallingInterruptEnable & mask))
     {
-        tmp8 &= ~CMP_SCR_IEF_MASK;
+        tmp8 &= ~(uint8_t)CMP_SCR_IEF_MASK;
     }
     base->SCR = tmp8;
 }
 
+/*!
+ * brief  Gets the status flags.
+ *
+ * param  base     CMP peripheral base address.
+ *
+ * return          Mask value for the asserted flags. See "_cmp_status_flags".
+ */
 uint32_t CMP_GetStatusFlags(CMP_Type *base)
 {
     uint32_t ret32 = 0U;
 
     if (0U != (CMP_SCR_CFR_MASK & base->SCR))
     {
-        ret32 |= kCMP_OutputRisingEventFlag;
+        ret32 |= (uint32_t)kCMP_OutputRisingEventFlag;
     }
     if (0U != (CMP_SCR_CFF_MASK & base->SCR))
     {
-        ret32 |= kCMP_OutputFallingEventFlag;
+        ret32 |= (uint32_t)kCMP_OutputFallingEventFlag;
     }
     if (0U != (CMP_SCR_COUT_MASK & base->SCR))
     {
-        ret32 |= kCMP_OutputAssertEventFlag;
+        ret32 |= (uint32_t)kCMP_OutputAssertEventFlag;
     }
     return ret32;
 }
 
+/*!
+ * brief Clears the status flags.
+ *
+ * param base     CMP peripheral base address.
+ * param mask     Mask value for the flags. See "_cmp_status_flags".
+ */
 void CMP_ClearStatusFlags(CMP_Type *base, uint32_t mask)
 {
-    uint8_t tmp8 = base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK); /* To avoid change the w1c bits. */
+    uint8_t tmp8 = (uint8_t)(base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK)); /* To avoid change the w1c bits. */
 
-    if (0U != (kCMP_OutputRisingEventFlag & mask))
+    if (0U != ((uint32_t)kCMP_OutputRisingEventFlag & mask))
     {
         tmp8 |= CMP_SCR_CFR_MASK;
     }
-    if (0U != (kCMP_OutputFallingEventFlag & mask))
+    if (0U != ((uint32_t)kCMP_OutputFallingEventFlag & mask))
     {
         tmp8 |= CMP_SCR_CFF_MASK;
     }
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_cmp.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_cmp.h
index e228413f0c5..c62c710842a 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_cmp.h
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_cmp.h
@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
+ * Copyright 2016-2018 NXP
  * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
  *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #ifndef _FSL_CMP_H_
@@ -42,23 +16,22 @@
  * @{
  */
 
-
 /*******************************************************************************
  * Definitions
  ******************************************************************************/
 
 /*! @name Driver version */
 /*@{*/
-/*! @brief CMP driver version 2.0.0. */
-#define FSL_CMP_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*! @brief CMP driver version 2.0.1. */
+#define FSL_CMP_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
 /*@}*/
 
 /*!
-* @brief Interrupt enable/disable mask.
-*/
+ * @brief Interrupt enable/disable mask.
+ */
 enum _cmp_interrupt_enable
 {
-    kCMP_OutputRisingInterruptEnable = CMP_SCR_IER_MASK,  /*!< Comparator interrupt enable rising. */
+    kCMP_OutputRisingInterruptEnable  = CMP_SCR_IER_MASK, /*!< Comparator interrupt enable rising. */
     kCMP_OutputFallingInterruptEnable = CMP_SCR_IEF_MASK, /*!< Comparator interrupt enable falling. */
 };
 
@@ -67,9 +40,9 @@ enum _cmp_interrupt_enable
  */
 enum _cmp_status_flags
 {
-    kCMP_OutputRisingEventFlag = CMP_SCR_CFR_MASK,  /*!< Rising-edge on the comparison output has occurred. */
-    kCMP_OutputFallingEventFlag = CMP_SCR_CFF_MASK, /*!< Falling-edge on the comparison output has occurred. */
-    kCMP_OutputAssertEventFlag = CMP_SCR_COUT_MASK, /*!< Return the current value of the analog comparator output. */
+    kCMP_OutputRisingEventFlag  = CMP_SCR_CFR_MASK,  /*!< Rising-edge on the comparison output has occurred. */
+    kCMP_OutputFallingEventFlag = CMP_SCR_CFF_MASK,  /*!< Falling-edge on the comparison output has occurred. */
+    kCMP_OutputAssertEventFlag  = CMP_SCR_COUT_MASK, /*!< Return the current value of the analog comparator output. */
 };
 
 /*!
@@ -126,7 +99,7 @@ typedef struct _cmp_filter_config
 typedef struct _cmp_dac_config
 {
     cmp_reference_voltage_source_t referenceVoltageSource; /*!< Supply voltage reference source. */
-    uint8_t DACValue;                                      /*!< Value for the DAC Output Voltage. Available range is 0-63.*/
+    uint8_t DACValue; /*!< Value for the DAC Output Voltage. Available range is 0-63.*/
 } cmp_dac_config_t;
 
 #if defined(__cplusplus)
@@ -186,25 +159,25 @@ static inline void CMP_Enable(CMP_Type *base, bool enable)
     }
     else
     {
-        base->CR1 &= ~CMP_CR1_EN_MASK;
+        base->CR1 &= ~(uint8_t)CMP_CR1_EN_MASK;
     }
 }
 
 /*!
-* @brief Initializes the CMP user configuration structure.
-*
-* This function initializes the user configuration structure to these default values.
-* @code
-*   config->enableCmp           = true;
-*   config->hysteresisMode      = kCMP_HysteresisLevel0;
-*   config->enableHighSpeed     = false;
-*   config->enableInvertOutput  = false;
-*   config->useUnfilteredOutput = false;
-*   config->enablePinOut        = false;
-*   config->enableTriggerMode   = false;
-* @endcode
-* @param config Pointer to the configuration structure.
-*/
+ * @brief Initializes the CMP user configuration structure.
+ *
+ * This function initializes the user configuration structure to these default values.
+ * @code
+ *   config->enableCmp           = true;
+ *   config->hysteresisMode      = kCMP_HysteresisLevel0;
+ *   config->enableHighSpeed     = false;
+ *   config->enableInvertOutput  = false;
+ *   config->useUnfilteredOutput = false;
+ *   config->enablePinOut        = false;
+ *   config->enableTriggerMode   = false;
+ * @endcode
+ * @param config Pointer to the configuration structure.
+ */
 void CMP_GetDefaultConfig(cmp_config_t *config);
 
 /*!
@@ -232,7 +205,8 @@ void CMP_SetInputChannels(CMP_Type *base, uint8_t positiveChannel, uint8_t negat
  * @brief Enables/disables the DMA request for rising/falling events.
  *
  * This function enables/disables the DMA request for rising/falling events. Either event triggers the generation of
- * the DMA request from CMP if the DMA feature is enabled. Both events are ignored for generating the DMA request from the CMP
+ * the DMA request from CMP if the DMA feature is enabled. Both events are ignored for generating the DMA request from
+ * the CMP
  * if the DMA is disabled.
  *
  * @param base CMP peripheral base address.
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_common.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_common.c
index 903faf52b63..deca9c626e8 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_common.c
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_common.c
@@ -1,45 +1,19 @@
 /*
-* The Clear BSD License
-* Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
- * Copyright 2016 NXP
-* All rights reserved.
-*
-* 
-* Redistribution and use in source and binary forms, with or without modification,
-* are permitted (subject to the limitations in the disclaimer below) provided
-*  that the following conditions are met:
-*
-* o Redistributions of source code must retain the above copyright notice, this list
-*   of conditions and the following disclaimer.
-*
-* o Redistributions in binary form must reproduce the above copyright notice, this
-*   list of conditions and the following disclaimer in the documentation and/or
-*   other materials provided with the distribution.
-*
-* o Neither the name of the copyright holder nor the names of its
-*   contributors may be used to endorse or promote products derived from this
-*   software without specific prior written permission.
-*
-* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
-* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
+ * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2018 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
 
 #include "fsl_common.h"
-#define SDK_MEM_MAGIC_NUMBER   12345U
+#define SDK_MEM_MAGIC_NUMBER 12345U
 
 typedef struct _mem_align_control_block
 {
-    uint16_t    identifier;     /*!< Identifier for the memory control block. */
-    uint16_t    offset;         /*!< offset from aligned adress to real address */
+    uint16_t identifier; /*!< Identifier for the memory control block. */
+    uint16_t offset;     /*!< offset from aligned address to real address */
 } mem_align_cb_t;
 
 /* Component ID definition, used by tools. */
@@ -47,13 +21,12 @@ typedef struct _mem_align_control_block
 #define FSL_COMPONENT_ID "platform.drivers.common"
 #endif
 
-
 #ifndef __GIC_PRIO_BITS
 #if defined(ENABLE_RAM_VECTOR_TABLE)
 uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler)
 {
 /* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */
-#if defined(__CC_ARM)
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
     extern uint32_t Image$$VECTOR_ROM$$Base[];
     extern uint32_t Image$$VECTOR_RAM$$Base[];
     extern uint32_t Image$$RW_m_data$$Base[];
@@ -70,7 +43,7 @@ uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler)
     extern uint32_t __VECTOR_RAM[];
     extern uint32_t __RAM_VECTOR_TABLE_SIZE_BYTES[];
     uint32_t __RAM_VECTOR_TABLE_SIZE = (uint32_t)(__RAM_VECTOR_TABLE_SIZE_BYTES);
-#endif /* defined(__CC_ARM) */
+#endif /* defined(__CC_ARM) || defined(__ARMCC_VERSION) */
     uint32_t n;
     uint32_t ret;
     uint32_t irqMaskValue;
@@ -104,30 +77,22 @@ uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler)
 #endif /* ENABLE_RAM_VECTOR_TABLE. */
 #endif /* __GIC_PRIO_BITS. */
 
-#ifndef QN908XC_SERIES
 #if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0))
+#if !(defined(FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) && FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS)
 
 void EnableDeepSleepIRQ(IRQn_Type interrupt)
 {
     uint32_t intNumber = (uint32_t)interrupt;
 
-#if (defined(FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) && (FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS == 1))
+    uint32_t index = 0;
+
+    while (intNumber >= 32u)
     {
-        SYSCON->STARTERP1 = 1u << intNumber;
+        index++;
+        intNumber -= 32u;
     }
-#else
-    {
-        uint32_t index = 0;
-
-        while (intNumber >= 32u)
-        {
-            index++;
-            intNumber -= 32u;
-        }
 
-        SYSCON->STARTERSET[index] = 1u << intNumber;
-    }
-#endif                    /* FSL_FEATURE_STARTER_DISCONTINUOUS */
+    SYSCON->STARTERSET[index] = 1u << intNumber;
     EnableIRQ(interrupt); /* also enable interrupt at NVIC */
 }
 
@@ -136,28 +101,19 @@ void DisableDeepSleepIRQ(IRQn_Type interrupt)
     uint32_t intNumber = (uint32_t)interrupt;
 
     DisableIRQ(interrupt); /* also disable interrupt at NVIC */
-#if (defined(FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) && (FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS == 1))
+    uint32_t index = 0;
+
+    while (intNumber >= 32u)
     {
-        SYSCON->STARTERP1 &= ~(1u << intNumber);
+        index++;
+        intNumber -= 32u;
     }
-#else
-    {
-        uint32_t index = 0;
-
-        while (intNumber >= 32u)
-        {
-            index++;
-            intNumber -= 32u;
-        }
 
-        SYSCON->STARTERCLR[index] = 1u << intNumber;
-    }
-#endif /* FSL_FEATURE_STARTER_DISCONTINUOUS */
+    SYSCON->STARTERCLR[index] = 1u << intNumber;
 }
+#endif /* FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS */
 #endif /* FSL_FEATURE_SOC_SYSCON_COUNT */
 
-#endif /* QN908XC_SERIES */
-
 void *SDK_Malloc(size_t size, size_t alignbytes)
 {
     mem_align_cb_t *p_cb = NULL;
@@ -171,16 +127,16 @@ void *SDK_Malloc(size_t size, size_t alignbytes)
 
     p_align_addr = (void *)SDK_SIZEALIGN((uint32_t)p_addr + sizeof(mem_align_cb_t), alignbytes);
 
-    p_cb = (mem_align_cb_t *)((uint32_t)p_align_addr - 4);
+    p_cb             = (mem_align_cb_t *)((uint32_t)p_align_addr - 4U);
     p_cb->identifier = SDK_MEM_MAGIC_NUMBER;
-    p_cb->offset = (uint32_t)p_align_addr - (uint32_t)p_addr;
+    p_cb->offset     = (uint32_t)p_align_addr - (uint32_t)p_addr;
 
     return (void *)p_align_addr;
 }
 
 void SDK_Free(void *ptr)
 {
-    mem_align_cb_t *p_cb = (mem_align_cb_t *)((uint32_t)ptr - 4);
+    mem_align_cb_t *p_cb = (mem_align_cb_t *)((uint32_t)ptr - 4U);
 
     if (p_cb->identifier != SDK_MEM_MAGIC_NUMBER)
     {
@@ -189,4 +145,3 @@ void SDK_Free(void *ptr)
 
     free((void *)((uint32_t)ptr - p_cb->offset));
 }
-
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_common.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_common.h
index b0a3d37ce6f..450dbe582a0 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_common.h
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_common.h
@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
+ * Copyright 2016-2018 NXP
  * All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #ifndef _FSL_COMMON_H_
@@ -64,21 +38,21 @@
 
 /*! @name Driver version */
 /*@{*/
-/*! @brief common driver version 2.0.0. */
-#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*! @brief common driver version 2.0.1. */
+#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 1, 0))
 /*@}*/
 
 /* Debug console type definition. */
 #define DEBUG_CONSOLE_DEVICE_TYPE_NONE          0U      /*!< No debug console.             */
-#define DEBUG_CONSOLE_DEVICE_TYPE_UART          1U      /*!< Debug console base on UART.   */
-#define DEBUG_CONSOLE_DEVICE_TYPE_LPUART        2U      /*!< Debug console base on LPUART. */
-#define DEBUG_CONSOLE_DEVICE_TYPE_LPSCI         3U      /*!< Debug console base on LPSCI.  */
-#define DEBUG_CONSOLE_DEVICE_TYPE_USBCDC        4U      /*!< Debug console base on USBCDC. */
-#define DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM      5U      /*!< Debug console base on USBCDC. */
-#define DEBUG_CONSOLE_DEVICE_TYPE_IUART         6U      /*!< Debug console base on i.MX UART. */
-#define DEBUG_CONSOLE_DEVICE_TYPE_VUSART        7U      /*!< Debug console base on LPC_USART. */
-#define DEBUG_CONSOLE_DEVICE_TYPE_MINI_USART    8U      /*!< Debug console base on LPC_USART. */
-#define DEBUG_CONSOLE_DEVICE_TYPE_SWO           9U      /*!< Debug console base on SWO. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_UART          1U      /*!< Debug console based on UART.   */
+#define DEBUG_CONSOLE_DEVICE_TYPE_LPUART        2U      /*!< Debug console based on LPUART. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_LPSCI         3U      /*!< Debug console based on LPSCI.  */
+#define DEBUG_CONSOLE_DEVICE_TYPE_USBCDC        4U      /*!< Debug console based on USBCDC. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM      5U      /*!< Debug console based on FLEXCOMM. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_IUART         6U      /*!< Debug console based on i.MX UART. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_VUSART        7U      /*!< Debug console based on LPC_VUSART. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_MINI_USART    8U      /*!< Debug console based on LPC_USART. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_SWO           9U      /*!< Debug console based on SWO. */
 
 /*! @brief Status group numbers. */
 enum _status_groups
@@ -142,15 +116,43 @@ enum _status_groups
     kStatusGroup_ESAI = 69,                   /*!< Group number for ESAI status codes. */
     kStatusGroup_FLEXSPI = 70,                /*!< Group number for FLEXSPI status codes. */
     kStatusGroup_MMDC = 71,                   /*!< Group number for MMDC status codes. */
-    kStatusGroup_MICFIL = 72,                 /*!< Group number for MIC status codes. */
+    kStatusGroup_PDM = 72,                    /*!< Group number for MIC status codes. */
     kStatusGroup_SDMA = 73,                   /*!< Group number for SDMA status codes. */
     kStatusGroup_ICS = 74,                    /*!< Group number for ICS status codes. */
     kStatusGroup_SPDIF = 75,                  /*!< Group number for SPDIF status codes. */
     kStatusGroup_LPC_MINISPI = 76,            /*!< Group number for LPC_MINISPI status codes. */
+    kStatusGroup_HASHCRYPT = 77,              /*!< Group number for Hashcrypt status codes */
+    kStatusGroup_LPC_SPI_SSP = 78,            /*!< Group number for LPC_SPI_SSP status codes. */
+    kStatusGroup_I3C = 79,                    /*!< Group number for I3C status codes */
+    kStatusGroup_LPC_I2C_1 = 97,              /*!< Group number for LPC_I2C_1 status codes. */
     kStatusGroup_NOTIFIER = 98,               /*!< Group number for NOTIFIER status codes. */
     kStatusGroup_DebugConsole = 99,           /*!< Group number for debug console status codes. */
-    kStatusGroup_SEMC = 100,                   /*!< Group number for SEMC status codes. */
+    kStatusGroup_SEMC = 100,                  /*!< Group number for SEMC status codes. */
     kStatusGroup_ApplicationRangeStart = 101, /*!< Starting number for application groups. */
+    kStatusGroup_IAP = 102,                   /*!< Group number for IAP status codes */
+
+    kStatusGroup_HAL_GPIO = 121,              /*!< Group number for HAL GPIO status codes. */
+    kStatusGroup_HAL_UART = 122,              /*!< Group number for HAL UART status codes. */
+    kStatusGroup_HAL_TIMER = 123,             /*!< Group number for HAL TIMER status codes. */
+    kStatusGroup_HAL_SPI = 124,               /*!< Group number for HAL SPI status codes. */
+    kStatusGroup_HAL_I2C = 125,               /*!< Group number for HAL I2C status codes. */
+    kStatusGroup_HAL_FLASH = 126,             /*!< Group number for HAL FLASH status codes. */
+    kStatusGroup_HAL_PWM = 127,               /*!< Group number for HAL PWM status codes. */
+    kStatusGroup_HAL_RNG = 128,               /*!< Group number for HAL RNG status codes. */
+    kStatusGroup_TIMERMANAGER = 135,          /*!< Group number for TiMER MANAGER status codes. */
+    kStatusGroup_SERIALMANAGER = 136,         /*!< Group number for SERIAL MANAGER status codes. */
+    kStatusGroup_LED = 137,                   /*!< Group number for LED status codes. */
+    kStatusGroup_BUTTON = 138,                /*!< Group number for BUTTON status codes. */
+    kStatusGroup_EXTERN_EEPROM = 139,         /*!< Group number for EXTERN EEPROM status codes. */
+    kStatusGroup_SHELL = 140,                 /*!< Group number for SHELL status codes. */
+    kStatusGroup_MEM_MANAGER = 141,           /*!< Group number for MEM MANAGER status codes. */
+    kStatusGroup_LIST = 142,                  /*!< Group number for List status codes. */
+    kStatusGroup_OSA = 143,                   /*!< Group number for OSA status codes. */
+    kStatusGroup_COMMON_TASK = 144,           /*!< Group number for Common task status codes. */
+    kStatusGroup_MSG = 145,                   /*!< Group number for messaging status codes. */
+    kStatusGroup_SDK_OCOTP = 146,             /*!< Group number for OCOTP status codes. */
+    kStatusGroup_SDK_FLEXSPINOR = 147,        /*!< Group number for FLEXSPINOR status codes.*/
+    kStatusGroup_CODEC = 148,                 /*!< Group number for codec status codes. */
 };
 
 /*! @brief Generic status return codes. */
@@ -168,20 +170,6 @@ enum _generic_status
 /*! @brief Type used for all status and error return values. */
 typedef int32_t status_t;
 
-/*
- * The fsl_clock.h is included here because it needs MAKE_VERSION/MAKE_STATUS/status_t
- * defined in previous of this file.
- */
-#include "fsl_clock.h"
-
-/*
- * Chip level peripheral reset API, for MCUs that implement peripheral reset control external to a peripheral
- */
-#if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) || \
-     (defined(FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT) && (FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT > 0)))
-#include "fsl_reset.h"
-#endif
-
 /*
  * Macro guard for whether to use default weak IRQ implementation in drivers
  */
@@ -192,11 +180,11 @@ typedef int32_t status_t;
 /*! @name Min/max macros */
 /* @{ */
 #if !defined(MIN)
-#define MIN(a, b) ((a) < (b) ? (a) : (b))
+#define MIN(a, b) (((a) < (b)) ? (a) : (b))
 #endif
 
 #if !defined(MAX)
-#define MAX(a, b) ((a) > (b) ? (a) : (b))
+#define MAX(a, b) (((a) > (b)) ? (a) : (b))
 #endif
 /* @} */
 
@@ -295,7 +283,7 @@ _Pragma("diag_suppress=Pm120")
  */
 /* @{ */
 #if (defined(__ICCARM__))
-#if defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE)
+#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE))
 #define AT_NONCACHEABLE_SECTION(var) var @"NonCacheable"
 #define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable"
 #define AT_NONCACHEABLE_SECTION_INIT(var) var @"NonCacheable.init"
@@ -307,7 +295,7 @@ _Pragma("diag_suppress=Pm120")
 #define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var
 #endif
 #elif(defined(__CC_ARM) || defined(__ARMCC_VERSION))
-#if defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE)
+#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE))
 #define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable"), zero_init)) var
 #define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \
     __attribute__((section("NonCacheable"), zero_init)) __attribute__((aligned(alignbytes))) var
@@ -324,7 +312,7 @@ _Pragma("diag_suppress=Pm120")
 /* For GCC, when the non-cacheable section is required, please define "__STARTUP_INITIALIZE_NONCACHEDATA"
  * in your projects to make sure the non-cacheable section variables will be initialized in system startup.
  */
-#if defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE)
+#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE))
 #define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var
 #define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \
     __attribute__((section("NonCacheable.init"))) var __attribute__((aligned(alignbytes)))
@@ -347,6 +335,61 @@ _Pragma("diag_suppress=Pm120")
 /* @} */
 
 /*! @name Time sensitive region */
+/* @{ */
+#if defined(FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE) && FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE
+#if (defined(__ICCARM__))
+#define AT_QUICKACCESS_SECTION_CODE(func) __ramfunc func
+#define AT_QUICKACCESS_SECTION_DATA(func) func @"DataQuickAccess"
+#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION))
+#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"))) func
+#define AT_QUICKACCESS_SECTION_DATA(func) __attribute__((section("DataQuickAccess"))) func
+#elif(defined(__GNUC__))
+#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"))) func
+#define AT_QUICKACCESS_SECTION_DATA(func) __attribute__((section("DataQuickAccess"))) func
+#else
+#error Toolchain not supported.
+#endif /* defined(__ICCARM__) */
+#else
+#if (defined(__ICCARM__))
+#define AT_QUICKACCESS_SECTION_CODE(func) func
+#define AT_QUICKACCESS_SECTION_DATA(func) func
+#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION))
+#define AT_QUICKACCESS_SECTION_CODE(func) func
+#define AT_QUICKACCESS_SECTION_DATA(func) func
+#elif(defined(__GNUC__))
+#define AT_QUICKACCESS_SECTION_CODE(func) func
+#define AT_QUICKACCESS_SECTION_DATA(func) func
+#else
+#error Toolchain not supported.
+#endif
+#endif /* __FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE */
+/* @} */
+
+/*! @name Ram Function */
+#if (defined(__ICCARM__))
+#define RAMFUNCTION_SECTION_CODE(func) func @"RamFunction"
+#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION))
+#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func
+#elif(defined(__GNUC__))
+#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func
+#else
+#error Toolchain not supported.
+#endif /* defined(__ICCARM__) */
+/* @} */
+
+/*
+ * The fsl_clock.h is included here because it needs MAKE_VERSION/MAKE_STATUS/status_t
+ * defined in previous of this file.
+ */
+#include "fsl_clock.h"
+
+/*
+ * Chip level peripheral reset API, for MCUs that implement peripheral reset control external to a peripheral
+ */
+#if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) || \
+     (defined(FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT) && (FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT > 0)))
+#include "fsl_reset.h"
+#endif
 
 /*******************************************************************************
  * API
@@ -443,6 +486,9 @@ _Pragma("diag_suppress=Pm120")
      */
     static inline uint32_t DisableGlobalIRQ(void)
     {
+#if defined (__XCC__)
+        return 0;
+#else
 #if defined(CPSR_I_Msk)
         uint32_t cpsr = __get_CPSR() & CPSR_I_Msk;
 
@@ -455,6 +501,7 @@ _Pragma("diag_suppress=Pm120")
     __disable_irq();
 
     return regPrimask;
+#endif
 #endif
     }
 
@@ -470,10 +517,13 @@ _Pragma("diag_suppress=Pm120")
      */
     static inline void EnableGlobalIRQ(uint32_t primask)
     {
+#if defined (__XCC__)
+#else
 #if defined(CPSR_I_Msk)
         __set_CPSR((__get_CPSR() & ~CPSR_I_Msk) | primask);
 #else
     __set_PRIMASK(primask);
+#endif
 #endif
     }
 
@@ -498,7 +548,7 @@ _Pragma("diag_suppress=Pm120")
      * those clocks (significantly increasing power consumption in the reduced power mode),
      * making these wake-ups possible.
      *
-     * @note This function also enables the interrupt in the NVIC (EnableIRQ() is called internally).
+     * @note This function also enables the interrupt in the NVIC (EnableIRQ() is called internaly).
      *
      * @param interrupt The IRQ number.
      */
@@ -513,7 +563,7 @@ _Pragma("diag_suppress=Pm120")
      * those clocks (significantly increasing power consumption in the reduced power mode),
      * making these wake-ups possible.
      *
-     * @note This function also disables the interrupt in the NVIC (DisableIRQ() is called internally).
+     * @note This function also disables the interrupt in the NVIC (DisableIRQ() is called internaly).
      *
      * @param interrupt The IRQ number.
      */
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_csi.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_csi.c
index df993d29dc4..ffa5f082c33 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_csi.c
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_csi.c
@@ -1,38 +1,15 @@
 /*
- * The Clear BSD License
- * Copyright (c) 2017, NXP Semiconductors, Inc.
+ * Copyright  2017-2018 NXP
  * All rights reserved.
  *
- * 
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include "fsl_csi.h"
+#if CSI_DRIVER_FRAG_MODE
+#include "fsl_cache.h"
+#endif
 
 /*******************************************************************************
  * Definitions
@@ -43,13 +20,16 @@
 #define FSL_COMPONENT_ID "platform.drivers.csi"
 #endif
 
-
 /* Two frame buffer loaded to CSI register at most. */
 #define CSI_MAX_ACTIVE_FRAME_NUM 2
 
+/* CSI driver only support RGB565 and YUV422 in fragment mode, 2 bytes per pixel. */
+#define CSI_FRAG_INPUT_BYTES_PER_PIXEL 2
+
 /*******************************************************************************
  * Prototypes
  ******************************************************************************/
+
 /*!
  * @brief Get the instance from the base address
  *
@@ -59,6 +39,7 @@
  */
 static uint32_t CSI_GetInstance(CSI_Type *base);
 
+#if !CSI_DRIVER_FRAG_MODE
 /*!
  * @brief Get the delta value of two index in queue.
  *
@@ -105,6 +86,12 @@ static void CSI_TransferLoadBufferToDevice(CSI_Type *base, csi_handle_t *handle)
 /* Typedef for interrupt handler. */
 typedef void (*csi_isr_t)(CSI_Type *base, csi_handle_t *handle);
 
+#else
+
+/* Typedef for interrupt handler to work in fragment mode. */
+typedef void (*csi_isr_t)(CSI_Type *base, csi_frag_handle_t *handle);
+#endif /* CSI_DRIVER_FRAG_MODE */
+
 /*******************************************************************************
  * Variables
  ******************************************************************************/
@@ -117,7 +104,11 @@ static const clock_ip_name_t s_csiClocks[] = CSI_CLOCKS;
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
 /* Array for the CSI driver handle. */
+#if !CSI_DRIVER_FRAG_MODE
 static csi_handle_t *s_csiHandle[ARRAY_SIZE(s_csiBases)];
+#else
+static csi_frag_handle_t *s_csiHandle[ARRAY_SIZE(s_csiBases)];
+#endif
 
 /* Array of CSI IRQ number. */
 static const IRQn_Type s_csiIRQ[] = CSI_IRQS;
@@ -146,6 +137,7 @@ static uint32_t CSI_GetInstance(CSI_Type *base)
     return instance;
 }
 
+#if !CSI_DRIVER_FRAG_MODE
 static uint32_t CSI_TransferGetQueueDelta(uint32_t startIdx, uint32_t endIdx)
 {
     if (endIdx >= startIdx)
@@ -154,7 +146,7 @@ static uint32_t CSI_TransferGetQueueDelta(uint32_t startIdx, uint32_t endIdx)
     }
     else
     {
-        return startIdx + CSI_DRIVER_ACTUAL_QUEUE_SIZE - endIdx;
+        return endIdx + CSI_DRIVER_ACTUAL_QUEUE_SIZE - startIdx;
     }
 }
 
@@ -195,7 +187,19 @@ static void CSI_TransferLoadBufferToDevice(CSI_Type *base, csi_handle_t *handle)
     /* There are two CSI buffers, so could use XOR to get the next index. */
     handle->nextBufferIdx ^= 1U;
 }
+#endif /* CSI_DRIVER_FRAG_MODE */
 
+/*!
+ * brief Initialize the CSI.
+ *
+ * This function enables the CSI peripheral clock, and resets the CSI registers.
+ *
+ * param base CSI peripheral base address.
+ * param config Pointer to the configuration structure.
+ *
+ * retval kStatus_Success Initialize successfully.
+ * retval kStatus_InvalidArgument Initialize failed because of invalid argument.
+ */
 status_t CSI_Init(CSI_Type *base, const csi_config_t *config)
 {
     assert(config);
@@ -288,6 +292,13 @@ status_t CSI_Init(CSI_Type *base, const csi_config_t *config)
     return kStatus_Success;
 }
 
+/*!
+ * brief De-initialize the CSI.
+ *
+ * This function disables the CSI peripheral clock.
+ *
+ * param base CSI peripheral base address.
+ */
 void CSI_Deinit(CSI_Type *base)
 {
     /* Disable transfer first. */
@@ -298,6 +309,13 @@ void CSI_Deinit(CSI_Type *base)
 #endif
 }
 
+/*!
+ * brief Reset the CSI.
+ *
+ * This function resets the CSI peripheral registers to default status.
+ *
+ * param base CSI peripheral base address.
+ */
 void CSI_Reset(CSI_Type *base)
 {
     uint32_t csisr;
@@ -321,7 +339,7 @@ void CSI_Reset(CSI_Type *base)
     CSI_ReflashFifoDma(base, kCSI_AllFifo);
 
     /* Clear the status. */
-    csisr = base->CSISR;
+    csisr       = base->CSISR;
     base->CSISR = csisr;
 
     /* Set the control registers to default value. */
@@ -337,10 +355,12 @@ void CSI_Reset(CSI_Type *base)
     base->CSIIMAG_PARA = 0U;
 }
 
-void CSI_GetDefaultConfig(csi_config_t *config)
-{
-    assert(config);
-
+/*!
+ * brief Get the default configuration for to initialize the CSI.
+ *
+ * The default configuration value is:
+ *
+ * code
     config->width = 320U;
     config->height = 240U;
     config->polarityFlags = kCSI_HsyncActiveHigh | kCSI_DataLatchOnRisingEdge;
@@ -349,8 +369,34 @@ void CSI_GetDefaultConfig(csi_config_t *config)
     config->workMode = kCSI_GatedClockMode;
     config->dataBus = kCSI_DataBus8Bit;
     config->useExtVsync = true;
+   endcode
+ *
+ * param config Pointer to the CSI configuration.
+ */
+void CSI_GetDefaultConfig(csi_config_t *config)
+{
+    assert(config);
+
+    /* Initializes the configure structure to zero. */
+    memset(config, 0, sizeof(*config));
+
+    config->width           = 320U;
+    config->height          = 240U;
+    config->polarityFlags   = kCSI_HsyncActiveHigh | kCSI_DataLatchOnRisingEdge;
+    config->bytesPerPixel   = 2U;
+    config->linePitch_Bytes = 320U * 2U;
+    config->workMode        = kCSI_GatedClockMode;
+    config->dataBus         = kCSI_DataBus8Bit;
+    config->useExtVsync     = true;
 }
 
+/*!
+ * brief Set the RX frame buffer address.
+ *
+ * param base CSI peripheral base address.
+ * param index Buffer index.
+ * param addr Frame buffer address to set.
+ */
 void CSI_SetRxBufferAddr(CSI_Type *base, uint8_t index, uint32_t addr)
 {
     if (index)
@@ -363,13 +409,21 @@ void CSI_SetRxBufferAddr(CSI_Type *base, uint8_t index, uint32_t addr)
     }
 }
 
+/*!
+ * brief Clear the CSI FIFO.
+ *
+ * This function clears the CSI FIFO.
+ *
+ * param base CSI peripheral base address.
+ * param fifo The FIFO to clear.
+ */
 void CSI_ClearFifo(CSI_Type *base, csi_fifo_t fifo)
 {
     uint32_t cr1;
     uint32_t mask = 0U;
 
     /* The FIFO could only be cleared when CSICR1[FCC] = 0, so first clear the FCC. */
-    cr1 = base->CSICR1;
+    cr1          = base->CSICR1;
     base->CSICR1 = (cr1 & ~CSI_CSICR1_FCC_MASK);
 
     if ((uint32_t)fifo & (uint32_t)kCSI_RxFifo)
@@ -393,6 +447,19 @@ void CSI_ClearFifo(CSI_Type *base, csi_fifo_t fifo)
     base->CSICR1 = cr1;
 }
 
+/*!
+ * brief Reflash the CSI FIFO DMA.
+ *
+ * This function reflashes the CSI FIFO DMA.
+ *
+ * For RXFIFO, there are two frame buffers. When the CSI module started, it saves
+ * the frames to frame buffer 0 then frame buffer 1, the two buffers will be
+ * written by turns. After reflash DMA using this function, the CSI is reset to
+ * save frame to buffer 0.
+ *
+ * param base CSI peripheral base address.
+ * param fifo The FIFO DMA to reflash.
+ */
 void CSI_ReflashFifoDma(CSI_Type *base, csi_fifo_t fifo)
 {
     uint32_t cr3 = 0U;
@@ -415,6 +482,13 @@ void CSI_ReflashFifoDma(CSI_Type *base, csi_fifo_t fifo)
     }
 }
 
+/*!
+ * brief Enable or disable the CSI FIFO DMA request.
+ *
+ * param base CSI peripheral base address.
+ * param fifo The FIFO DMA reques to enable or disable.
+ * param enable True to enable, false to disable.
+ */
 void CSI_EnableFifoDmaRequest(CSI_Type *base, csi_fifo_t fifo, bool enable)
 {
     uint32_t cr3 = 0U;
@@ -439,6 +513,12 @@ void CSI_EnableFifoDmaRequest(CSI_Type *base, csi_fifo_t fifo, bool enable)
     }
 }
 
+/*!
+ * brief Enables CSI interrupt requests.
+ *
+ * param base CSI peripheral base address.
+ * param mask The interrupts to enable, pass in as OR'ed value of ref _csi_interrupt_enable.
+ */
 void CSI_EnableInterrupts(CSI_Type *base, uint32_t mask)
 {
     base->CSICR1 |= (mask & CSI_CSICR1_INT_EN_MASK);
@@ -446,6 +526,12 @@ void CSI_EnableInterrupts(CSI_Type *base, uint32_t mask)
     base->CSICR18 |= ((mask & CSI_CSICR18_INT_EN_MASK) >> 6U);
 }
 
+/*!
+ * brief Disable CSI interrupt requests.
+ *
+ * param base CSI peripheral base address.
+ * param mask The interrupts to disable, pass in as OR'ed value of ref _csi_interrupt_enable.
+ */
 void CSI_DisableInterrupts(CSI_Type *base, uint32_t mask)
 {
     base->CSICR1 &= ~(mask & CSI_CSICR1_INT_EN_MASK);
@@ -453,6 +539,20 @@ void CSI_DisableInterrupts(CSI_Type *base, uint32_t mask)
     base->CSICR18 &= ~((mask & CSI_CSICR18_INT_EN_MASK) >> 6U);
 }
 
+#if !CSI_DRIVER_FRAG_MODE
+/*!
+ * brief Initializes the CSI handle.
+ *
+ * This function initializes CSI handle, it should be called before any other
+ * CSI transactional functions.
+ *
+ * param base CSI peripheral base address.
+ * param handle Pointer to the handle structure.
+ * param callback Callback function for CSI transfer.
+ * param userData Callback function parameter.
+ *
+ * retval kStatus_Success Handle created successfully.
+ */
 status_t CSI_TransferCreateHandle(CSI_Type *base,
                                   csi_handle_t *handle,
                                   csi_transfer_callback_t callback,
@@ -481,6 +581,20 @@ status_t CSI_TransferCreateHandle(CSI_Type *base,
     return kStatus_Success;
 }
 
+/*!
+ * brief Start the transfer using transactional functions.
+ *
+ * When the empty frame buffers have been submit to CSI driver using function
+ * ref CSI_TransferSubmitEmptyBuffer, user could call this function to start
+ * the transfer. The incoming frame will be saved to the empty frame buffer,
+ * and user could be optionally notified through callback function.
+ *
+ * param base CSI peripheral base address.
+ * param handle Pointer to the handle structure.
+ *
+ * retval kStatus_Success Started successfully.
+ * retval kStatus_CSI_NoEmptyBuffer Could not start because no empty frame buffer in queue.
+ */
 status_t CSI_TransferStart(CSI_Type *base, csi_handle_t *handle)
 {
     assert(handle);
@@ -494,11 +608,16 @@ status_t CSI_TransferStart(CSI_Type *base, csi_handle_t *handle)
         return kStatus_CSI_NoEmptyBuffer;
     }
 
-    handle->nextBufferIdx = 0U;
+    handle->nextBufferIdx   = 0U;
     handle->activeBufferNum = 0U;
 
-    /* Write to memory from second completed frame. */
-    base->CSICR18 = (base->CSICR18 & ~CSI_CSICR18_MASK_OPTION_MASK) | CSI_CSICR18_MASK_OPTION(2);
+    /*
+     * Write to memory from first completed frame.
+     * DMA base addr switch at the edge of the first data of each frame, thus
+     * if one frame is broken, it could be reset at the next frame.
+     */
+    base->CSICR18 = (base->CSICR18 & ~CSI_CSICR18_MASK_OPTION_MASK) | CSI_CSICR18_MASK_OPTION(0) |
+                    CSI_CSICR18_BASEADDR_SWITCH_SEL_MASK | CSI_CSICR18_BASEADDR_SWITCH_EN_MASK;
 
     /* Load the frame buffer to CSI register, there are at least two empty buffers. */
     CSI_TransferLoadBufferToDevice(base, handle);
@@ -517,6 +636,18 @@ status_t CSI_TransferStart(CSI_Type *base, csi_handle_t *handle)
     return kStatus_Success;
 }
 
+/*!
+ * brief Stop the transfer using transactional functions.
+ *
+ * The driver does not clean the full frame buffers in queue. In other words, after
+ * calling this function, user still could get the full frame buffers in queue
+ * using function ref CSI_TransferGetFullBuffer.
+ *
+ * param base CSI peripheral base address.
+ * param handle Pointer to the handle structure.
+ *
+ * retval kStatus_Success Stoped successfully.
+ */
 status_t CSI_TransferStop(CSI_Type *base, csi_handle_t *handle)
 {
     assert(handle);
@@ -534,6 +665,20 @@ status_t CSI_TransferStop(CSI_Type *base, csi_handle_t *handle)
     return kStatus_Success;
 }
 
+/*!
+ * brief Submit empty frame buffer to queue.
+ *
+ * This function could be called before ref CSI_TransferStart or after ref
+ * CSI_TransferStart. If there is no room in queue to store the empty frame
+ * buffer, this function returns error.
+ *
+ * param base CSI peripheral base address.
+ * param handle Pointer to the handle structure.
+ * param frameBuffer Empty frame buffer to submit.
+ *
+ * retval kStatus_Success Started successfully.
+ * retval kStatus_CSI_QueueFull Could not submit because there is no room in queue.
+ */
 status_t CSI_TransferSubmitEmptyBuffer(CSI_Type *base, csi_handle_t *handle, uint32_t frameBuffer)
 {
     uint32_t csicr1;
@@ -550,7 +695,16 @@ status_t CSI_TransferSubmitEmptyBuffer(CSI_Type *base, csi_handle_t *handle, uin
 
     /* Save the empty frame buffer address to queue. */
     handle->frameBufferQueue[handle->queueUserWriteIdx] = frameBuffer;
-    handle->queueUserWriteIdx = CSI_TransferIncreaseQueueIdx(handle->queueUserWriteIdx);
+    handle->queueUserWriteIdx                           = CSI_TransferIncreaseQueueIdx(handle->queueUserWriteIdx);
+
+    /*
+     * If transfer is ongoing and an active slot is available, Load the buffer
+     * now to prevent buffer starvation during next TransferHandleIRQ event.
+     */
+    if (handle->transferOnGoing && handle->activeBufferNum < CSI_MAX_ACTIVE_FRAME_NUM)
+    {
+        CSI_TransferLoadBufferToDevice(base, handle);
+    }
 
     base->CSICR1 = csicr1;
 
@@ -563,7 +717,7 @@ status_t CSI_TransferSubmitEmptyBuffer(CSI_Type *base, csi_handle_t *handle, uin
         if ((!handle->transferOnGoing) && (CSI_TransferGetEmptyBufferCount(base, handle) >= 2U))
         {
             handle->transferOnGoing = true;
-            handle->nextBufferIdx = 0U;
+            handle->nextBufferIdx   = 0U;
 
             /* Load the frame buffers to CSI module. */
             CSI_TransferLoadBufferToDevice(base, handle);
@@ -576,6 +730,21 @@ status_t CSI_TransferSubmitEmptyBuffer(CSI_Type *base, csi_handle_t *handle, uin
     return kStatus_Success;
 }
 
+/*!
+ * brief Get one full frame buffer from queue.
+ *
+ * After the transfer started using function ref CSI_TransferStart, the incoming
+ * frames will be saved to the empty frame buffers in queue. This function gets
+ * the full-filled frame buffer from the queue. If there is no full frame buffer
+ * in queue, this function returns error.
+ *
+ * param base CSI peripheral base address.
+ * param handle Pointer to the handle structure.
+ * param frameBuffer Full frame buffer.
+ *
+ * retval kStatus_Success Started successfully.
+ * retval kStatus_CSI_NoFullBuffer There is no full frame buffer in queue.
+ */
 status_t CSI_TransferGetFullBuffer(CSI_Type *base, csi_handle_t *handle, uint32_t *frameBuffer)
 {
     uint32_t csicr1;
@@ -600,6 +769,15 @@ status_t CSI_TransferGetFullBuffer(CSI_Type *base, csi_handle_t *handle, uint32_
     return kStatus_Success;
 }
 
+/*!
+ * brief CSI IRQ handle function.
+ *
+ * This function handles the CSI IRQ request to work with CSI driver transactional
+ * APIs.
+ *
+ * param base CSI peripheral base address.
+ * param handle CSI handle pointer.
+ */
 void CSI_TransferHandleIRQ(CSI_Type *base, csi_handle_t *handle)
 {
     uint32_t queueDrvWriteIdx;
@@ -627,8 +805,8 @@ void CSI_TransferHandleIRQ(CSI_Type *base, csi_handle_t *handle)
 
             if (2U == handle->activeBufferNum)
             {
-                queueDrvWriteIdx = CSI_TransferIncreaseQueueIdx(queueDrvWriteIdx);
-                base->CSIDMASA_FB2 = handle->frameBufferQueue[queueDrvWriteIdx];
+                queueDrvWriteIdx      = CSI_TransferIncreaseQueueIdx(queueDrvWriteIdx);
+                base->CSIDMASA_FB2    = handle->frameBufferQueue[queueDrvWriteIdx];
                 handle->nextBufferIdx = 0U;
             }
             else
@@ -669,6 +847,455 @@ void CSI_TransferHandleIRQ(CSI_Type *base, csi_handle_t *handle)
     }
 }
 
+#else /* CSI_DRIVER_FRAG_MODE */
+
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+__asm void CSI_ExtractYFromYUYV(void *datBase, const void *dmaBase, size_t count)
+{
+    /* clang-format off */
+    push    {r4-r7, lr}
+10
+    LDMIA    R1!, {r3-r6}
+    bfi      r7, r3, #0, #8  /* Y0 */
+    bfi      ip, r5, #0, #8  /* Y4 */
+    lsr      r3, r3, #16
+    lsr      r5, r5, #16
+    bfi      r7, r3, #8, #8  /* Y1 */
+    bfi      ip, r5, #8, #8  /* Y5 */
+    bfi      r7, r4, #16, #8 /* Y2 */
+    bfi      ip, r6, #16, #8 /* Y6 */
+    lsr      r4, r4, #16
+    lsr      r6, r6, #16
+    bfi      r7, r4, #24, #8 /* Y3 */
+    bfi      ip, r6, #24, #8 /* Y7 */
+    STMIA    r0!, {r7, ip}
+    subs     r2, #8
+    bne      %b10
+    pop      {r4-r7, pc}
+    /* clang-format on */
+}
+
+__asm void CSI_ExtractYFromUYVY(void *datBase, const void *dmaBase, size_t count)
+{
+    /* clang-format off */
+    push    {r4-r7, lr}
+10
+    LDMIA    R1!, {r3-r6}
+    lsr      r3, r3, #8
+    lsr      r5, r5, #8
+    bfi      r7, r3, #0, #8  /* Y0 */
+    bfi      ip, r5, #0, #8  /* Y4 */
+    lsr      r3, r3, #16
+    lsr      r5, r5, #16
+    bfi      r7, r3, #8, #8  /* Y1 */
+    bfi      ip, r5, #8, #8  /* Y5 */
+    lsr      r4, r4, #8
+    lsr      r6, r6, #8
+    bfi      r7, r4, #16, #8 /* Y2 */
+    bfi      ip, r6, #16, #8 /* Y6 */
+    lsr      r4, r4, #16
+    lsr      r6, r6, #16
+    bfi      r7, r4, #24, #8 /* Y3 */
+    bfi      ip, r6, #24, #8 /* Y7 */
+    STMIA    r0!, {r7, ip}
+    subs     r2, #8
+    bne      %b10
+    pop      {r4-r7, pc}
+    /* clang-format on */
+}
+
+#elif (defined(__GNUC__) || defined(__ICCARM__))
+#if defined(__ICCARM__)
+#pragma diag_suppress = Pe940
+#endif
+__attribute__((naked)) void CSI_ExtractYFromYUYV(void *datBase, const void *dmaBase, size_t count)
+{
+    /* clang-format off */
+    __asm volatile(
+        "    push    {r1-r7, r12, lr}  \n"
+        "loop0:                        \n"
+        "    ldmia   r1!, {r3-r6}      \n"
+        "    bfi     r7, r3, #0, #8    \n" /* Y0 */
+        "    bfi     r12, r5, #0, #8   \n" /* Y4 */
+        "    lsr     r3, r3, #16       \n"
+        "    lsr     r5, r5, #16       \n"
+        "    bfi     r7, r3, #8, #8    \n" /* Y1 */
+        "    bfi     r12, r5, #8, #8   \n" /* Y5 */
+        "    bfi     r7, r4, #16, #8   \n" /* Y2 */
+        "    bfi     r12, r6, #16, #8  \n" /* Y6 */
+        "    lsr     r4, r4, #16       \n"
+        "    lsr     r6, r6, #16       \n"
+        "    bfi     r7, r4, #24, #8   \n" /* Y3 */
+        "    bfi     r12, r6, #24, #8  \n" /* Y7 */
+        "    stmia   r0!, {r7, r12}    \n"
+        "    subs    r2, #8            \n"
+        "    bne     loop0             \n"
+        "    pop     {r1-r7, r12, pc}  \n");
+    /* clang-format on */
+}
+
+__attribute__((naked)) void CSI_ExtractYFromUYVY(void *datBase, const void *dmaBase, size_t count)
+{
+    /* clang-format off */
+    __asm volatile(
+        "    push    {r1-r7, r12, lr}  \n"
+        "loop1:                        \n"
+        "    ldmia   r1!, {r3-r6}      \n"
+        "    lsr     r3, r3, #8        \n"
+        "    lsr     r5, r5, #8        \n"
+        "    bfi     r7, r3, #0, #8    \n" /* Y0 */
+        "    bfi     r12, r5, #0, #8   \n" /* Y4 */
+        "    lsr     r3, r3, #16       \n"
+        "    lsr     r5, r5, #16       \n"
+        "    bfi     r7, r3, #8, #8    \n" /* Y1 */
+        "    bfi     r12, r5, #8, #8   \n" /* Y5 */
+        "    lsr     r4, r4, #8        \n"
+        "    lsr     r6, r6, #8        \n"
+        "    bfi     r7, r4, #16, #8   \n" /* Y2 */
+        "    bfi     r12, r6, #16, #8  \n" /* Y6 */
+        "    lsr     r4, r4, #16       \n"
+        "    lsr     r6, r6, #16       \n"
+        "    bfi     r7, r4, #24, #8   \n" /* Y3 */
+        "    bfi     r12, r6, #24, #8  \n" /* Y7 */
+        "    stmia   r0!, {r7, r12}    \n"
+        "    subs    r2, #8            \n"
+        "    bne     loop1             \n"
+        "    pop     {r1-r7, r12, pc}  \n");
+    /* clang-format on */
+}
+#if defined(__ICCARM__)
+#pragma diag_default = Pe940
+#endif
+#else
+#error Toolchain not supported.
+#endif
+
+static void CSI_MemCopy(void *pDest, const void *pSrc, size_t cnt)
+{
+    memcpy(pDest, pSrc, cnt);
+}
+
+/*!
+ * brief Initialize the CSI to work in fragment mode.
+ *
+ * This function enables the CSI peripheral clock, and resets the CSI registers.
+ *
+ * param base CSI peripheral base address.
+ */
+void CSI_FragModeInit(CSI_Type *base)
+{
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    uint32_t instance = CSI_GetInstance(base);
+    CLOCK_EnableClock(s_csiClocks[instance]);
+#endif
+
+    CSI_Reset(base);
+}
+
+/*!
+ * brief De-initialize the CSI.
+ *
+ * This function disables the CSI peripheral clock.
+ *
+ * param base CSI peripheral base address.
+ */
+void CSI_FragModeDeinit(CSI_Type *base)
+{
+    CSI_Deinit(base);
+}
+
+/*!
+ * brief Create handle for CSI work in fragment mode.
+ *
+ * param base CSI peripheral base address.
+ * param handle Pointer to the transactional handle.
+ * param config Pointer to the configuration structure.
+ * param callback Callback function for CSI transfer.
+ * param userData Callback function parameter.
+ *
+ * retval kStatus_Success Initialize successfully.
+ * retval kStatus_InvalidArgument Initialize failed because of invalid argument.
+ */
+status_t CSI_FragModeCreateHandle(CSI_Type *base,
+                                  csi_frag_handle_t *handle,
+                                  const csi_frag_config_t *config,
+                                  csi_frag_transfer_callback_t callback,
+                                  void *userData)
+{
+    assert(config);
+    uint32_t reg;
+    uint32_t instance;
+    uint32_t imgWidth_Bytes;
+
+    imgWidth_Bytes = config->width * CSI_FRAG_INPUT_BYTES_PER_PIXEL;
+
+    /* The image buffer line width should be multiple of 8-bytes. */
+    if ((imgWidth_Bytes & 0x07) != 0)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* Camera frame height must be dividable by DMA buffer line. */
+    if (config->height % config->dmaBufferLine != 0)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    memset(handle, 0, sizeof(*handle));
+    handle->callback            = callback;
+    handle->userData            = userData;
+    handle->height              = config->height;
+    handle->width               = config->width;
+    handle->maxLinePerFrag      = config->dmaBufferLine;
+    handle->dmaBytePerLine      = config->width * CSI_FRAG_INPUT_BYTES_PER_PIXEL;
+    handle->isDmaBufferCachable = config->isDmaBufferCachable;
+
+    /* Get instance from peripheral base address. */
+    instance = CSI_GetInstance(base);
+    /* Save the handle in global variables to support the double weak mechanism. */
+    s_csiHandle[instance] = handle;
+
+    s_csiIsr = CSI_FragModeTransferHandleIRQ;
+
+    EnableIRQ(s_csiIRQ[instance]);
+
+    /* Configure CSICR1. CSICR1 has been reset to the default value, so could write it directly. */
+    reg = ((uint32_t)config->workMode) | config->polarityFlags | CSI_CSICR1_FCC_MASK;
+
+    if (config->useExtVsync)
+    {
+        reg |= CSI_CSICR1_EXT_VSYNC_MASK;
+    }
+
+    base->CSICR1 = reg;
+
+    /* No stride. */
+    base->CSIFBUF_PARA = 0;
+
+    /* Enable auto ECC. */
+    base->CSICR3 |= CSI_CSICR3_ECC_AUTO_EN_MASK;
+
+    /*
+     * For better performance.
+     * The DMA burst size could be set to 16 * 8 byte, 8 * 8 byte, or 4 * 8 byte,
+     * choose the best burst size based on bytes per line.
+     */
+    if (!(imgWidth_Bytes % (8 * 16)))
+    {
+        base->CSICR2 = CSI_CSICR2_DMA_BURST_TYPE_RFF(3U);
+        base->CSICR3 = (CSI->CSICR3 & ~CSI_CSICR3_RxFF_LEVEL_MASK) | ((2U << CSI_CSICR3_RxFF_LEVEL_SHIFT));
+    }
+    else if (!(imgWidth_Bytes % (8 * 8)))
+    {
+        base->CSICR2 = CSI_CSICR2_DMA_BURST_TYPE_RFF(2U);
+        base->CSICR3 = (CSI->CSICR3 & ~CSI_CSICR3_RxFF_LEVEL_MASK) | ((1U << CSI_CSICR3_RxFF_LEVEL_SHIFT));
+    }
+    else
+    {
+        base->CSICR2 = CSI_CSICR2_DMA_BURST_TYPE_RFF(1U);
+        base->CSICR3 = (CSI->CSICR3 & ~CSI_CSICR3_RxFF_LEVEL_MASK) | ((0U << CSI_CSICR3_RxFF_LEVEL_SHIFT));
+    }
+
+    base->CSIDMASA_FB1 = config->dmaBufferAddr0;
+    base->CSIDMASA_FB2 = config->dmaBufferAddr1;
+
+    if (handle->isDmaBufferCachable)
+    {
+        DCACHE_CleanInvalidateByRange(config->dmaBufferAddr0,
+                                      config->dmaBufferLine * config->width * CSI_FRAG_INPUT_BYTES_PER_PIXEL);
+        DCACHE_CleanInvalidateByRange(config->dmaBufferAddr1,
+                                      config->dmaBufferLine * config->width * CSI_FRAG_INPUT_BYTES_PER_PIXEL);
+    }
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Start to capture a image.
+ *
+ * param base CSI peripheral base address.
+ * param handle Pointer to the transactional handle.
+ * param config Pointer to the capture configuration.
+ *
+ * retval kStatus_Success Initialize successfully.
+ * retval kStatus_InvalidArgument Initialize failed because of invalid argument.
+ */
+status_t CSI_FragModeTransferCaptureImage(CSI_Type *base,
+                                          csi_frag_handle_t *handle,
+                                          const csi_frag_capture_config_t *config)
+{
+    assert(config);
+
+    uint16_t windowWidth;
+
+    /*
+     * If no special window setting, capture full frame.
+     * If capture window, then capture 1 one each fragment.
+     */
+    if (config->window != NULL)
+    {
+        handle->windowULX   = config->window->windowULX;
+        handle->windowULY   = config->window->windowULY;
+        handle->windowLRX   = config->window->windowLRX;
+        handle->windowLRY   = config->window->windowLRY;
+        handle->linePerFrag = 1;
+    }
+    else
+    {
+        handle->windowULX   = 0;
+        handle->windowULY   = 0;
+        handle->windowLRX   = handle->width - 1;
+        handle->windowLRY   = handle->height - 1;
+        handle->linePerFrag = handle->maxLinePerFrag;
+    }
+
+    windowWidth = handle->windowLRX - handle->windowULX + 1;
+
+    if (config->outputGrayScale)
+    {
+        /* When output format is gray, the window width must be multiple value of 8. */
+        if (windowWidth % 8 != 0)
+        {
+            return kStatus_InvalidArgument;
+        }
+
+        handle->datBytePerLine = windowWidth;
+        if (handle->inputFormat == kCSI_FragInputYUYV)
+        {
+            handle->copyFunc = CSI_ExtractYFromYUYV;
+        }
+        else
+        {
+            handle->copyFunc = CSI_ExtractYFromUYVY;
+        }
+    }
+    else
+    {
+        handle->datBytePerLine = windowWidth * CSI_FRAG_INPUT_BYTES_PER_PIXEL;
+        handle->copyFunc       = CSI_MemCopy;
+    }
+
+    handle->dmaCurLine      = 0;
+    handle->outputBuffer    = (uint32_t)config->buffer;
+    handle->datCurWriteAddr = (uint32_t)config->buffer;
+
+    /* Image parameter. */
+    base->CSIIMAG_PARA =
+        ((uint32_t)(handle->width * CSI_FRAG_INPUT_BYTES_PER_PIXEL) << CSI_CSIIMAG_PARA_IMAGE_WIDTH_SHIFT) |
+        ((uint32_t)(handle->linePerFrag) << CSI_CSIIMAG_PARA_IMAGE_HEIGHT_SHIFT);
+
+    /*
+     * Write to memory from first completed frame.
+     * DMA base addr switch at dma transfer done.
+     */
+    base->CSICR18 = (base->CSICR18 & ~CSI_CSICR18_MASK_OPTION_MASK) | CSI_CSICR18_MASK_OPTION(0);
+
+    CSI_EnableInterrupts(base, kCSI_StartOfFrameInterruptEnable | kCSI_RxBuffer1DmaDoneInterruptEnable |
+                                   kCSI_RxBuffer0DmaDoneInterruptEnable);
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Abort image capture.
+ *
+ * Abort image capture initialized by ref CSI_FragModeTransferCaptureImage.
+ *
+ * param base CSI peripheral base address.
+ * param handle Pointer to the transactional handle.
+ */
+void CSI_FragModeTransferAbortCaptureImage(CSI_Type *base, csi_frag_handle_t *handle)
+{
+    CSI_Stop(base);
+    CSI_DisableInterrupts(base, kCSI_StartOfFrameInterruptEnable | kCSI_RxBuffer1DmaDoneInterruptEnable |
+                                    kCSI_RxBuffer0DmaDoneInterruptEnable);
+}
+
+/*!
+ * brief CSI IRQ handle function.
+ *
+ * This function handles the CSI IRQ request to work with CSI driver fragment mode
+ * APIs.
+ *
+ * param base CSI peripheral base address.
+ * param handle CSI handle pointer.
+ */
+void CSI_FragModeTransferHandleIRQ(CSI_Type *base, csi_frag_handle_t *handle)
+{
+    uint32_t csisr = base->CSISR;
+    uint32_t dmaBufAddr;
+    uint16_t line;
+
+    /* Clear the error flags. */
+    base->CSISR = csisr;
+
+    /* Start of frame, clear the FIFO and start receiving. */
+    if (csisr & kCSI_StartOfFrameFlag)
+    {
+        /* Reflash the DMA and enable RX DMA request. */
+        base->CSICR3 |= (CSI_CSICR3_DMA_REFLASH_RFF_MASK | CSI_CSICR3_DMA_REQ_EN_RFF_MASK);
+        CSI_Start(base);
+        handle->dmaCurLine      = 0;
+        handle->datCurWriteAddr = handle->outputBuffer;
+    }
+    else if ((csisr & (CSI_CSISR_DMA_TSF_DONE_FB2_MASK | CSI_CSISR_DMA_TSF_DONE_FB1_MASK)) != 0)
+    {
+        if ((csisr & CSI_CSISR_DMA_TSF_DONE_FB1_MASK) == CSI_CSISR_DMA_TSF_DONE_FB1_MASK)
+        {
+            dmaBufAddr = base->CSIDMASA_FB1;
+        }
+        else
+        {
+            dmaBufAddr = base->CSIDMASA_FB2;
+        }
+
+        if (handle->isDmaBufferCachable)
+        {
+            DCACHE_InvalidateByRange(dmaBufAddr, handle->dmaBytePerLine * handle->linePerFrag);
+        }
+
+        /* Copy from DMA buffer to user data buffer. */
+        dmaBufAddr += (handle->windowULX * CSI_FRAG_INPUT_BYTES_PER_PIXEL);
+
+        for (line = 0; line < handle->linePerFrag; line++)
+        {
+            if (handle->dmaCurLine + line > handle->windowLRY)
+            {
+                /* out of window range */
+                break;
+            }
+            else if (handle->dmaCurLine + line >= handle->windowULY)
+            {
+                handle->copyFunc((void *)(handle->datCurWriteAddr), (void const *)dmaBufAddr, handle->datBytePerLine);
+                handle->datCurWriteAddr += handle->datBytePerLine;
+                dmaBufAddr += handle->dmaBytePerLine;
+            }
+            else
+            {
+            }
+        }
+
+        handle->dmaCurLine += handle->linePerFrag;
+
+        if (handle->dmaCurLine >= handle->height)
+        {
+            CSI_Stop(base);
+            CSI_DisableInterrupts(base, kCSI_StartOfFrameInterruptEnable | kCSI_RxBuffer1DmaDoneInterruptEnable |
+                                            kCSI_RxBuffer0DmaDoneInterruptEnable);
+
+            /* Image captured. Stop the CSI. */
+            if (handle->callback)
+            {
+                handle->callback(base, handle, kStatus_CSI_FrameDone, handle->userData);
+            }
+        }
+    }
+    else
+    {
+    }
+}
+#endif /* CSI_DRIVER_FRAG_MODE */
+
 #if defined(CSI)
 void CSI_DriverIRQHandler(void)
 {
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_csi.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_csi.h
index 96230c83186..408b0b1ce4f 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_csi.h
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_csi.h
@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
- * Copyright (c) 2017, NXP Semiconductors, Inc.
+ * Copyright  2017-2019 NXP
  * All rights reserved.
  *
- * 
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
  *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #ifndef _FSL_CSI_H_
@@ -48,7 +22,7 @@
 
 /*! @name Driver version */
 /*@{*/
-#define FSL_CSI_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+#define FSL_CSI_DRIVER_VERSION (MAKE_VERSION(2, 0, 3))
 /*@}*/
 
 /*! @brief Size of the frame buffer queue used in CSI transactional function. */
@@ -56,6 +30,11 @@
 #define CSI_DRIVER_QUEUE_SIZE 4U
 #endif
 
+/*! @brief Enable fragment capture function or not. */
+#ifndef CSI_DRIVER_FRAG_MODE
+#define CSI_DRIVER_FRAG_MODE 0U
+#endif
+
 /*
  * There is one empty room in queue, used to distinguish whether the queue
  * is full or empty. When header equals tail, the queue is empty; when header
@@ -84,7 +63,9 @@
 #error CSI_CSICR3_INT_EN_MASK could not cover all interrupt bits in CSICR3.
 #endif
 
-#if ((~CSI_CSICR18_INT_EN_MASK) & ((CSI_CSICR18_FIELD0_DONE_IE_MASK | CSI_CSICR18_DMA_FIELD1_DONE_IE_MASK | CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_MASK) << 6U))
+#if ((~CSI_CSICR18_INT_EN_MASK) & ((CSI_CSICR18_FIELD0_DONE_IE_MASK | CSI_CSICR18_DMA_FIELD1_DONE_IE_MASK | \
+                                    CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_MASK)                              \
+                                   << 6U))
 #error CSI_CSICR18_INT_EN_MASK could not cover all interrupt bits in CSICR18.
 #endif
 
@@ -92,7 +73,7 @@
 enum _csi_status
 {
     kStatus_CSI_NoEmptyBuffer = MAKE_STATUS(kStatusGroup_CSI, 0), /*!< No empty frame buffer in queue to load to CSI. */
-    kStatus_CSI_NoFullBuffer = MAKE_STATUS(kStatusGroup_CSI, 1),  /*!< No full frame buffer in queue to read out. */
+    kStatus_CSI_NoFullBuffer  = MAKE_STATUS(kStatusGroup_CSI, 1), /*!< No full frame buffer in queue to read out. */
     kStatus_CSI_QueueFull = MAKE_STATUS(kStatusGroup_CSI, 2), /*!< Queue is full, no room to save new empty buffer. */
     kStatus_CSI_FrameDone = MAKE_STATUS(kStatusGroup_CSI, 3), /*!< New frame received and saved to queue. */
 };
@@ -104,9 +85,9 @@ enum _csi_status
  */
 typedef enum _csi_work_mode
 {
-    kCSI_GatedClockMode = CSI_CSICR1_GCLK_MODE(1U),       /*!< HSYNC, VSYNC, and PIXCLK signals are used. */
-    kCSI_NonGatedClockMode = 0U,                          /*!< VSYNC, and PIXCLK signals are used. */
-    kCSI_CCIR656ProgressiveMode = CSI_CSICR1_CCIR_EN(1U), /*!< CCIR656 progressive mode. */
+    kCSI_GatedClockMode         = CSI_CSICR1_GCLK_MODE(1U), /*!< HSYNC, VSYNC, and PIXCLK signals are used. */
+    kCSI_NonGatedClockMode      = 0U,                       /*!< VSYNC, and PIXCLK signals are used. */
+    kCSI_CCIR656ProgressiveMode = CSI_CSICR1_CCIR_EN(1U),   /*!< CCIR656 progressive mode. */
 } csi_work_mode_t;
 
 /*!
@@ -122,12 +103,12 @@ typedef enum _csi_data_bus
 /*! @brief CSI signal polarity. */
 enum _csi_polarity_flags
 {
-    kCSI_HsyncActiveLow = 0U,                           /*!< HSYNC is active low. */
-    kCSI_HsyncActiveHigh = CSI_CSICR1_HSYNC_POL_MASK,   /*!< HSYNC is active high. */
-    kCSI_DataLatchOnRisingEdge = CSI_CSICR1_REDGE_MASK, /*!< Pixel data latched at rising edge of pixel clock. */
-    kCSI_DataLatchOnFallingEdge = 0U,                   /*!< Pixel data latched at falling edge of pixel clock. */
-    kCSI_VsyncActiveHigh = 0U,                       /*!< VSYNC is active high. */
-    kCSI_VsyncActiveLow = CSI_CSICR1_SOF_POL_MASK,   /*!< VSYNC is active low. */
+    kCSI_HsyncActiveLow         = 0U,                        /*!< HSYNC is active low. */
+    kCSI_HsyncActiveHigh        = CSI_CSICR1_HSYNC_POL_MASK, /*!< HSYNC is active high. */
+    kCSI_DataLatchOnRisingEdge  = CSI_CSICR1_REDGE_MASK,     /*!< Pixel data latched at rising edge of pixel clock. */
+    kCSI_DataLatchOnFallingEdge = 0U,                        /*!< Pixel data latched at falling edge of pixel clock. */
+    kCSI_VsyncActiveHigh        = 0U,                        /*!< VSYNC is active high. */
+    kCSI_VsyncActiveLow         = CSI_CSICR1_SOF_POL_MASK,   /*!< VSYNC is active low. */
 };
 
 /*! @brief Configuration to initialize the CSI module. */
@@ -151,33 +132,34 @@ typedef struct _csi_config
 /*! @brief The CSI FIFO, used for FIFO operation. */
 typedef enum _csi_fifo
 {
-    kCSI_RxFifo = (1U << 0U),   /*!< RXFIFO. */
-    kCSI_StatFifo = (1U << 1U), /*!< STAT FIFO. */
-    kCSI_AllFifo = 0x01 | 0x02, /*!< Both RXFIFO and STAT FIFO. */
+    kCSI_RxFifo   = (1U << 0U),  /*!< RXFIFO. */
+    kCSI_StatFifo = (1U << 1U),  /*!< STAT FIFO. */
+    kCSI_AllFifo  = 0x01 | 0x02, /*!< Both RXFIFO and STAT FIFO. */
 } csi_fifo_t;
 
 /*! @brief CSI feature interrupt source. */
 enum _csi_interrupt_enable
 {
-    kCSI_EndOfFrameInterruptEnable = CSI_CSICR1_EOF_INT_EN_MASK,       /*!< End of frame interrupt enable. */
-    kCSI_ChangeOfFieldInterruptEnable = CSI_CSICR1_COF_INT_EN_MASK,    /*!< Change of field interrupt enable. */
+    kCSI_EndOfFrameInterruptEnable      = CSI_CSICR1_EOF_INT_EN_MASK,  /*!< End of frame interrupt enable. */
+    kCSI_ChangeOfFieldInterruptEnable   = CSI_CSICR1_COF_INT_EN_MASK,  /*!< Change of field interrupt enable. */
     kCSI_StatFifoOverrunInterruptEnable = CSI_CSICR1_SF_OR_INTEN_MASK, /*!< STAT FIFO overrun interrupt enable. */
-    kCSI_RxFifoOverrunInterruptEnable = CSI_CSICR1_RF_OR_INTEN_MASK,   /*!< RXFIFO overrun interrupt enable. */
+    kCSI_RxFifoOverrunInterruptEnable   = CSI_CSICR1_RF_OR_INTEN_MASK, /*!< RXFIFO overrun interrupt enable. */
     kCSI_StatFifoDmaDoneInterruptEnable =
         CSI_CSICR1_SFF_DMA_DONE_INTEN_MASK,                          /*!< STAT FIFO DMA done interrupt enable. */
     kCSI_StatFifoFullInterruptEnable = CSI_CSICR1_STATFF_INTEN_MASK, /*!< STAT FIFO full interrupt enable. */
     kCSI_RxBuffer1DmaDoneInterruptEnable =
         CSI_CSICR1_FB2_DMA_DONE_INTEN_MASK, /*!< RX frame buffer 1 DMA transfer done. */
     kCSI_RxBuffer0DmaDoneInterruptEnable =
-        CSI_CSICR1_FB1_DMA_DONE_INTEN_MASK,                       /*!< RX frame buffer 0 DMA transfer done. */
-    kCSI_RxFifoFullInterruptEnable = CSI_CSICR1_RXFF_INTEN_MASK,  /*!< RXFIFO full interrupt enable. */
-    kCSI_StartOfFrameInterruptEnable = CSI_CSICR1_SOF_INTEN_MASK, /*!< Start of frame (SOF) interrupt enable. */
+        CSI_CSICR1_FB1_DMA_DONE_INTEN_MASK,                        /*!< RX frame buffer 0 DMA transfer done. */
+    kCSI_RxFifoFullInterruptEnable   = CSI_CSICR1_RXFF_INTEN_MASK, /*!< RXFIFO full interrupt enable. */
+    kCSI_StartOfFrameInterruptEnable = CSI_CSICR1_SOF_INTEN_MASK,  /*!< Start of frame (SOF) interrupt enable. */
 
-    kCSI_EccErrorInterruptEnable = CSI_CSICR3_ECC_INT_EN_MASK,      /*!< ECC error detection interrupt enable. */
+    kCSI_EccErrorInterruptEnable    = CSI_CSICR3_ECC_INT_EN_MASK,   /*!< ECC error detection interrupt enable. */
     kCSI_AhbResErrorInterruptEnable = CSI_CSICR3_HRESP_ERR_EN_MASK, /*!< AHB response Error interrupt enable. */
 
-    kCSI_BaseAddrChangeErrorInterruptEnable = CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_MASK << 6U, /*!< The DMA output buffer base address
-                                                                               changes before DMA completed. */
+    kCSI_BaseAddrChangeErrorInterruptEnable = CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_MASK
+                                              << 6U,                            /*!< The DMA output buffer base address
+                                                                changes before DMA completed. */
     kCSI_Field0DoneInterruptEnable = CSI_CSICR18_FIELD0_DONE_IE_MASK << 6U,     /*!< Field 0 done interrupt enable. */
     kCSI_Field1DoneInterruptEnable = CSI_CSICR18_DMA_FIELD1_DONE_IE_MASK << 6U, /*!< Field 1 done interrupt enable. */
 };
@@ -202,23 +184,23 @@ enum _csi_interrupt_enable
  */
 enum _csi_flags
 {
-    kCSI_RxFifoDataReadyFlag = CSI_CSISR_DRDY_MASK,      /*!< RXFIFO data ready. */
-    kCSI_EccErrorFlag = CSI_CSISR_ECC_INT_MASK,          /*!< ECC error detected. */
-    kCSI_AhbResErrorFlag = CSI_CSISR_HRESP_ERR_INT_MASK, /*!< Hresponse (AHB bus response) Error. */
-    kCSI_ChangeOfFieldFlag = CSI_CSISR_COF_INT_MASK,     /*!< Change of field. */
-    kCSI_Field0PresentFlag = CSI_CSISR_F1_INT_MASK,      /*!< Field 0 present in CCIR mode. */
-    kCSI_Field1PresentFlag = CSI_CSISR_F2_INT_MASK,      /*!< Field 1 present in CCIR mode. */
-    kCSI_StartOfFrameFlag = CSI_CSISR_SOF_INT_MASK,      /*!< Start of frame (SOF) detected. */
-    kCSI_EndOfFrameFlag = CSI_CSISR_EOF_INT_MASK,        /*!< End of frame (EOF) detected. */
-    kCSI_RxFifoFullFlag = CSI_CSISR_RxFF_INT_MASK,       /*!< RXFIFO full (Number of data reaches trigger level). */
-    kCSI_RxBuffer1DmaDoneFlag = CSI_CSISR_DMA_TSF_DONE_FB2_MASK,          /*!< RX frame buffer 1 DMA transfer done. */
-    kCSI_RxBuffer0DmaDoneFlag = CSI_CSISR_DMA_TSF_DONE_FB1_MASK,          /*!< RX frame buffer 0 DMA transfer done. */
-    kCSI_StatFifoFullFlag = CSI_CSISR_STATFF_INT_MASK,                    /*!< STAT FIFO full (Reach trigger level). */
-    kCSI_StatFifoDmaDoneFlag = CSI_CSISR_DMA_TSF_DONE_SFF_MASK,           /*!< STAT FIFO DMA transfer done. */
-    kCSI_StatFifoOverrunFlag = CSI_CSISR_SF_OR_INT_MASK,                  /*!< STAT FIFO overrun. */
-    kCSI_RxFifoOverrunFlag = CSI_CSISR_RF_OR_INT_MASK,                    /*!< RXFIFO overrun. */
-    kCSI_Field0DoneFlag = CSI_CSISR_DMA_FIELD0_DONE_MASK,                 /*!< Field 0 transfer done. */
-    kCSI_Field1DoneFlag = CSI_CSISR_DMA_FIELD1_DONE_MASK,                 /*!< Field 1 transfer done. */
+    kCSI_RxFifoDataReadyFlag     = CSI_CSISR_DRDY_MASK,          /*!< RXFIFO data ready. */
+    kCSI_EccErrorFlag            = CSI_CSISR_ECC_INT_MASK,       /*!< ECC error detected. */
+    kCSI_AhbResErrorFlag         = CSI_CSISR_HRESP_ERR_INT_MASK, /*!< Hresponse (AHB bus response) Error. */
+    kCSI_ChangeOfFieldFlag       = CSI_CSISR_COF_INT_MASK,       /*!< Change of field. */
+    kCSI_Field0PresentFlag       = CSI_CSISR_F1_INT_MASK,        /*!< Field 0 present in CCIR mode. */
+    kCSI_Field1PresentFlag       = CSI_CSISR_F2_INT_MASK,        /*!< Field 1 present in CCIR mode. */
+    kCSI_StartOfFrameFlag        = CSI_CSISR_SOF_INT_MASK,       /*!< Start of frame (SOF) detected. */
+    kCSI_EndOfFrameFlag          = CSI_CSISR_EOF_INT_MASK,       /*!< End of frame (EOF) detected. */
+    kCSI_RxFifoFullFlag          = CSI_CSISR_RxFF_INT_MASK, /*!< RXFIFO full (Number of data reaches trigger level). */
+    kCSI_RxBuffer1DmaDoneFlag    = CSI_CSISR_DMA_TSF_DONE_FB2_MASK,       /*!< RX frame buffer 1 DMA transfer done. */
+    kCSI_RxBuffer0DmaDoneFlag    = CSI_CSISR_DMA_TSF_DONE_FB1_MASK,       /*!< RX frame buffer 0 DMA transfer done. */
+    kCSI_StatFifoFullFlag        = CSI_CSISR_STATFF_INT_MASK,             /*!< STAT FIFO full (Reach trigger level). */
+    kCSI_StatFifoDmaDoneFlag     = CSI_CSISR_DMA_TSF_DONE_SFF_MASK,       /*!< STAT FIFO DMA transfer done. */
+    kCSI_StatFifoOverrunFlag     = CSI_CSISR_SF_OR_INT_MASK,              /*!< STAT FIFO overrun. */
+    kCSI_RxFifoOverrunFlag       = CSI_CSISR_RF_OR_INT_MASK,              /*!< RXFIFO overrun. */
+    kCSI_Field0DoneFlag          = CSI_CSISR_DMA_FIELD0_DONE_MASK,        /*!< Field 0 transfer done. */
+    kCSI_Field1DoneFlag          = CSI_CSISR_DMA_FIELD1_DONE_MASK,        /*!< Field 1 transfer done. */
     kCSI_BaseAddrChangeErrorFlag = CSI_CSISR_BASEADDR_CHHANGE_ERROR_MASK, /*!< The DMA output buffer base address
                                                                                changes before DMA completed. */
 };
@@ -258,6 +240,99 @@ struct _csi_handle
     void *userData;                   /*!< CSI callback function parameter.*/
 };
 
+#if CSI_DRIVER_FRAG_MODE
+
+/*! @brief Input pixel format when CSI works in fragment mode. */
+typedef enum _csi_frag_input_pixel_format
+{
+    kCSI_FragInputRGB565 = 0, /*!< Input pixel format is RGB565. */
+    kCSI_FragInputYUYV,       /*!< Input pixel format is YUV422 (Y-U-Y-V). */
+    kCSI_FragInputUYVY,       /*!< Input pixel format is YUV422 (U-Y-V-Y). */
+} csi_frag_input_pixel_format_t;
+
+/*! @brief Configuration for CSI module to work in fragment mode. */
+typedef struct _csi_frag_config
+{
+    uint16_t width;           /*!< Pixels of the input frame. */
+    uint16_t height;          /*!< Lines of the input frame.  */
+    uint32_t polarityFlags;   /*!< Timing signal polarity flags, OR'ed value of @ref _csi_polarity_flags. */
+    csi_work_mode_t workMode; /*!< CSI work mode. */
+    csi_data_bus_t dataBus;   /*!< Data bus width. */
+    bool useExtVsync;         /*!< In CCIR656 progressive mode, set true to use external VSYNC signal, set false
+                                to use internal VSYNC signal decoded from SOF. */
+    csi_frag_input_pixel_format_t inputFormat; /*!< Input pixel format. */
+
+    uint32_t dmaBufferAddr0;  /*!< Buffer 0 used for CSI DMA, must be double word aligned. */
+    uint32_t dmaBufferAddr1;  /*!< Buffer 1 used for CSI DMA, must be double word aligned. */
+    uint16_t dmaBufferLine;   /*!< Lines of each DMA buffer. The size of DMA buffer 0 and
+                                   buffer 1 must be the same. Camera frame height must be
+                                   dividable by this value. */
+    bool isDmaBufferCachable; /*!< Is DMA buffer cachable or not. */
+} csi_frag_config_t;
+
+/* Forward declaration of the handle typedef. */
+typedef struct _csi_frag_handle csi_frag_handle_t;
+
+/*!
+ * @brief CSI fragment transfer callback function.
+ *
+ * When a new frame is received and saved to the frame buffer queue, the callback
+ * is called and the pass the status @ref kStatus_CSI_FrameDone to upper layer.
+ */
+typedef void (*csi_frag_transfer_callback_t)(CSI_Type *base,
+                                             csi_frag_handle_t *handle,
+                                             status_t status,
+                                             void *userData);
+
+/*!
+ * @brief Function to copy data from CSI DMA buffer to user buffer.
+ */
+typedef void (*csi_frag_copy_func_t)(void *pDest, const void *pSrc, size_t cnt);
+
+/*! @brief Handle for CSI module to work in fragment mode. */
+struct _csi_frag_handle
+{
+    uint16_t width;                            /*!< Pixels of the input frame. */
+    uint16_t height;                           /*!< Lines of the input frame.  */
+    uint16_t maxLinePerFrag;                   /*!< Max line saved per fragment. */
+    uint16_t linePerFrag;                      /*!< Actual line saved per fragment. */
+    uint16_t dmaBytePerLine;                   /*!< How many bytes DMA transfered each line. */
+    uint16_t datBytePerLine;                   /*!< How many bytes copied to user buffer each line. */
+    uint16_t dmaCurLine;                       /*!< Current line index in whole frame. */
+    uint16_t windowULX;                        /*!< X of windows upper left corner. */
+    uint16_t windowULY;                        /*!< Y of windows upper left corner. */
+    uint16_t windowLRX;                        /*!< X of windows lower right corner. */
+    uint16_t windowLRY;                        /*!< Y of windows lower right corner. */
+    uint32_t outputBuffer;                     /*!< Address of buffer to save the captured image. */
+    uint32_t datCurWriteAddr;                  /*!< Current write address to the user buffer. */
+    csi_frag_input_pixel_format_t inputFormat; /*!< Input pixel format. */
+
+    csi_frag_transfer_callback_t callback; /*!< Callback function. */
+    void *userData;                        /*!< CSI callback function parameter.*/
+    csi_frag_copy_func_t copyFunc;         /*!< Function to copy data from CSI DMA buffer to user buffer. */
+    bool isDmaBufferCachable;              /*!< Is DMA buffer cachable or not. */
+};
+
+/*! @brief Handle for CSI module to work in fragment mode. */
+typedef struct _csi_frag_window
+{
+    uint16_t windowULX; /*!< X of windows upper left corner. */
+    uint16_t windowULY; /*!< Y of windows upper left corner. */
+    uint16_t windowLRX; /*!< X of windows lower right corner. */
+    uint16_t windowLRY; /*!< Y of windows lower right corner. */
+} csi_frag_window_t;
+
+/*! @brief Handle for CSI module to work in fragment mode. */
+typedef struct _csi_frag_capture_config
+{
+    bool outputGrayScale;      /*!< Output gray scale image or not, could only enable when input format is YUV. */
+    uint32_t buffer;           /*!< Buffer to save the captured image. */
+    csi_frag_window_t *window; /*!< Capture window. Capture full frame if set this to NULL. When output format is gray,
+                                    the window width must be multiple value of 8. */
+} csi_frag_capture_config_t;
+
+#endif /* CSI_DRIVER_FRAG_MODE */
+
 /*******************************************************************************
  * API
  ******************************************************************************/
@@ -455,6 +530,7 @@ static inline void CSI_ClearStatusFlags(CSI_Type *base, uint32_t statusMask)
 }
 /* @} */
 
+#if !CSI_DRIVER_FRAG_MODE
 /*!
  * @name Transactional
  * @{
@@ -553,6 +629,88 @@ status_t CSI_TransferGetFullBuffer(CSI_Type *base, csi_handle_t *handle, uint32_
 void CSI_TransferHandleIRQ(CSI_Type *base, csi_handle_t *handle);
 /* @} */
 
+#else
+
+/*!
+ * @name Fragment mode
+ * @{
+ */
+
+/*!
+ * @brief Initialize the CSI to work in fragment mode.
+ *
+ * This function enables the CSI peripheral clock, and resets the CSI registers.
+ *
+ * @param base CSI peripheral base address.
+ */
+void CSI_FragModeInit(CSI_Type *base);
+
+/*!
+ * @brief De-initialize the CSI.
+ *
+ * This function disables the CSI peripheral clock.
+ *
+ * @param base CSI peripheral base address.
+ */
+void CSI_FragModeDeinit(CSI_Type *base);
+
+/*!
+ * @brief Create handle for CSI work in fragment mode.
+ *
+ * @param base CSI peripheral base address.
+ * @param handle Pointer to the transactional handle.
+ * @param config Pointer to the configuration structure.
+ * @param callback Callback function for CSI transfer.
+ * @param userData Callback function parameter.
+ *
+ * @retval kStatus_Success Initialize successfully.
+ * @retval kStatus_InvalidArgument Initialize failed because of invalid argument.
+ */
+status_t CSI_FragModeCreateHandle(CSI_Type *base,
+                                  csi_frag_handle_t *handle,
+                                  const csi_frag_config_t *config,
+                                  csi_frag_transfer_callback_t callback,
+                                  void *userData);
+
+/*!
+ * @brief Start to capture a image.
+ *
+ * @param base CSI peripheral base address.
+ * @param handle Pointer to the transactional handle.
+ * @param config Pointer to the capture configuration.
+ *
+ * @retval kStatus_Success Initialize successfully.
+ * @retval kStatus_InvalidArgument Initialize failed because of invalid argument.
+ */
+status_t CSI_FragModeTransferCaptureImage(CSI_Type *base,
+                                          csi_frag_handle_t *handle,
+                                          const csi_frag_capture_config_t *config);
+
+/*!
+ * @brief Abort image capture.
+ *
+ * Abort image capture initialized by @ref CSI_FragModeTransferCaptureImage.
+ *
+ * @param base CSI peripheral base address.
+ * @param handle Pointer to the transactional handle.
+ */
+void CSI_FragModeTransferAbortCaptureImage(CSI_Type *base, csi_frag_handle_t *handle);
+
+/*!
+ * @brief CSI IRQ handle function.
+ *
+ * This function handles the CSI IRQ request to work with CSI driver fragment mode
+ * APIs.
+ *
+ * @param base CSI peripheral base address.
+ * @param handle CSI handle pointer.
+ */
+void CSI_FragModeTransferHandleIRQ(CSI_Type *base, csi_frag_handle_t *handle);
+
+/* @} */
+
+#endif /* CSI_DRIVER_FRAG_MODE */
+
 #if defined(__cplusplus)
 }
 #endif
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_dcdc.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_dcdc.c
index 5e0e3a97b41..248628763c3 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_dcdc.c
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_dcdc.c
@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
- * Copyright (c) 2017, NXP
+ * Copyright 2017, NXP
  * All rights reserved.
  *
- * 
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
  *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include "fsl_dcdc.h"
@@ -39,7 +13,6 @@
 #define FSL_COMPONENT_ID "platform.drivers.dcdc_1"
 #endif
 
-
 /*******************************************************************************
  * Prototypes
  ******************************************************************************/
@@ -82,6 +55,11 @@ static uint32_t DCDC_GetInstance(DCDC_Type *base)
     return instance;
 }
 
+/*!
+ * brief Enable the access to DCDC registers.
+ *
+ * param base DCDC peripheral base address.
+ */
 void DCDC_Init(DCDC_Type *base)
 {
 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
@@ -90,6 +68,11 @@ void DCDC_Init(DCDC_Type *base)
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }
 
+/*!
+ * brief Disable the access to DCDC registers.
+ *
+ * param base DCDC peripheral base address.
+ */
 void DCDC_Deinit(DCDC_Type *base)
 {
 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
@@ -98,14 +81,19 @@ void DCDC_Deinit(DCDC_Type *base)
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }
 
+/*!
+ * brief Configure the DCDC clock source.
+ *
+ * param base DCDC peripheral base address.
+ * param clockSource Clock source for DCDC. See to "dcdc_clock_source_t".
+ */
 void DCDC_SetClockSource(DCDC_Type *base, dcdc_clock_source_t clockSource)
 {
     uint32_t tmp32;
 
     /* Configure the DCDC_REG0 register. */
-    tmp32 = base->REG0 &
-            ~(DCDC_REG0_XTAL_24M_OK_MASK | DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK | DCDC_REG0_SEL_CLK_MASK |
-              DCDC_REG0_PWD_OSC_INT_MASK);
+    tmp32 = base->REG0 & ~(DCDC_REG0_XTAL_24M_OK_MASK | DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK |
+                           DCDC_REG0_SEL_CLK_MASK | DCDC_REG0_PWD_OSC_INT_MASK);
     switch (clockSource)
     {
         case kDCDC_ClockInternalOsc:
@@ -125,20 +113,47 @@ void DCDC_SetClockSource(DCDC_Type *base, dcdc_clock_source_t clockSource)
     base->REG0 = tmp32;
 }
 
+/*!
+ * brief Get the default setting for detection configuration.
+ *
+ * The default configuration are set according to responding registers' setting when powered on.
+ * They are:
+ * code
+ *   config->enableXtalokDetection = false;
+ *   config->powerDownOverVoltageDetection = true;
+ *   config->powerDownLowVlotageDetection = false;
+ *   config->powerDownOverCurrentDetection = true;
+ *   config->powerDownPeakCurrentDetection = true;
+ *   config->powerDownZeroCrossDetection = true;
+ *   config->OverCurrentThreshold = kDCDC_OverCurrentThresholdAlt0;
+ *   config->PeakCurrentThreshold = kDCDC_PeakCurrentThresholdAlt0;
+ * endcode
+ *
+ * param config Pointer to configuration structure. See to "dcdc_detection_config_t"
+ */
 void DCDC_GetDefaultDetectionConfig(dcdc_detection_config_t *config)
 {
     assert(NULL != config);
 
-    config->enableXtalokDetection = false;
+    /* Initializes the configure structure to zero. */
+    memset(config, 0, sizeof(*config));
+
+    config->enableXtalokDetection         = false;
     config->powerDownOverVoltageDetection = true;
-    config->powerDownLowVlotageDetection = false;
+    config->powerDownLowVlotageDetection  = false;
     config->powerDownOverCurrentDetection = true;
     config->powerDownPeakCurrentDetection = true;
-    config->powerDownZeroCrossDetection = true;
-    config->OverCurrentThreshold = kDCDC_OverCurrentThresholdAlt0;
-    config->PeakCurrentThreshold = kDCDC_PeakCurrentThresholdAlt0;
+    config->powerDownZeroCrossDetection   = true;
+    config->OverCurrentThreshold          = kDCDC_OverCurrentThresholdAlt0;
+    config->PeakCurrentThreshold          = kDCDC_PeakCurrentThresholdAlt0;
 }
 
+/*!
+ * breif Configure the DCDC detection.
+ *
+ * param base DCDC peripheral base address.
+ * param config Pointer to configuration structure. See to "dcdc_detection_config_t"
+ */
 void DCDC_SetDetectionConfig(DCDC_Type *base, const dcdc_detection_config_t *config)
 {
     assert(NULL != config);
@@ -179,25 +194,47 @@ void DCDC_SetDetectionConfig(DCDC_Type *base, const dcdc_detection_config_t *con
     base->REG0 = tmp32;
 }
 
+/*!
+ * brief Get the default setting for low power configuration.
+ *
+ * The default configuration are set according to responding registers' setting when powered on.
+ * They are:
+ * code
+ *   config->enableOverloadDetection = true;
+ *   config->enableAdjustHystereticValue = false;
+ *   config->countChargingTimePeriod = kDCDC_CountChargingTimePeriod8Cycle;
+ *   config->countChargingTimeThreshold = kDCDC_CountChargingTimeThreshold32;
+ * endcode
+ *
+ * param config Pointer to configuration structure. See to "dcdc_low_power_config_t"
+ */
 void DCDC_GetDefaultLowPowerConfig(dcdc_low_power_config_t *config)
 {
     assert(NULL != config);
 
-    config->enableOverloadDetection = true;
+    /* Initializes the configure structure to zero. */
+    memset(config, 0, sizeof(*config));
+
+    config->enableOverloadDetection     = true;
     config->enableAdjustHystereticValue = false;
-    config->countChargingTimePeriod = kDCDC_CountChargingTimePeriod8Cycle;
-    config->countChargingTimeThreshold = kDCDC_CountChargingTimeThreshold32;
+    config->countChargingTimePeriod     = kDCDC_CountChargingTimePeriod8Cycle;
+    config->countChargingTimeThreshold  = kDCDC_CountChargingTimeThreshold32;
 }
 
+/*!
+ * brief Configure the DCDC low power.
+ *
+ * param base DCDC peripheral base address.
+ * param config Pointer to configuration structure. See to "dcdc_low_power_config_t".
+ */
 void DCDC_SetLowPowerConfig(DCDC_Type *base, const dcdc_low_power_config_t *config)
 {
     assert(NULL != config);
 
     uint32_t tmp32;
     /* Configure the DCDC_REG0 register. */
-    tmp32 = base->REG0 &
-            ~(DCDC_REG0_EN_LP_OVERLOAD_SNS_MASK | DCDC_REG0_LP_HIGH_HYS_MASK | DCDC_REG0_LP_OVERLOAD_FREQ_SEL_MASK |
-              DCDC_REG0_LP_OVERLOAD_THRSH_MASK);
+    tmp32 = base->REG0 & ~(DCDC_REG0_EN_LP_OVERLOAD_SNS_MASK | DCDC_REG0_LP_HIGH_HYS_MASK |
+                           DCDC_REG0_LP_OVERLOAD_FREQ_SEL_MASK | DCDC_REG0_LP_OVERLOAD_THRSH_MASK);
     tmp32 |= DCDC_REG0_LP_OVERLOAD_FREQ_SEL(config->countChargingTimePeriod) |
              DCDC_REG0_LP_OVERLOAD_THRSH(config->countChargingTimeThreshold);
     if (config->enableOverloadDetection)
@@ -211,6 +248,12 @@ void DCDC_SetLowPowerConfig(DCDC_Type *base, const dcdc_low_power_config_t *conf
     base->REG0 = tmp32;
 }
 
+/*!
+ * brief Get DCDC status flags.
+ *
+ * param base peripheral base address.
+ * return Mask of asserted status flags. See to "_dcdc_status_flags_t".
+ */
 uint32_t DCDC_GetstatusFlags(DCDC_Type *base)
 {
     uint32_t tmp32 = 0U;
@@ -223,6 +266,12 @@ uint32_t DCDC_GetstatusFlags(DCDC_Type *base)
     return tmp32;
 }
 
+/*!
+ * brief Reset current alert signal. Alert signal is generate by peak current detection.
+ *
+ * param base DCDC peripheral base address.
+ * param enable Switcher to reset signal. True means reset signal. False means don't reset signal.
+ */
 void DCDC_ResetCurrentAlertSignal(DCDC_Type *base, bool enable)
 {
     if (enable)
@@ -235,20 +284,47 @@ void DCDC_ResetCurrentAlertSignal(DCDC_Type *base, bool enable)
     }
 }
 
+/*!
+ * brief Get the default setting for loop control configuration.
+ *
+ * The default configuration are set according to responding registers' setting when powered on.
+ * They are:
+ * code
+ *   config->enableCommonHysteresis = false;
+ *   config->enableCommonThresholdDetection = false;
+ *   config->enableInvertHysteresisSign = false;
+ *   config->enableRCThresholdDetection = false;
+ *   config->enableRCScaleCircuit = 0U;
+ *   config->complementFeedForwardStep = 0U;
+ *   config->controlParameterMagnitude = 2U;
+ *   config->integralProportionalRatio = 2U;
+ * endcode
+ *
+ * param config Pointer to configuration structure. See to "dcdc_loop_control_config_t"
+ */
 void DCDC_GetDefaultLoopControlConfig(dcdc_loop_control_config_t *config)
 {
     assert(NULL != config);
 
-    config->enableCommonHysteresis = false;
+    /* Initializes the configure structure to zero. */
+    memset(config, 0, sizeof(*config));
+
+    config->enableCommonHysteresis         = false;
     config->enableCommonThresholdDetection = false;
-    config->enableInvertHysteresisSign = false;
-    config->enableRCThresholdDetection = false;
-    config->enableRCScaleCircuit = 0U;
-    config->complementFeedForwardStep = 0U;
-    config->controlParameterMagnitude = 2U;
-    config->integralProportionalRatio = 2U;
+    config->enableInvertHysteresisSign     = false;
+    config->enableRCThresholdDetection     = false;
+    config->enableRCScaleCircuit           = 0U;
+    config->complementFeedForwardStep      = 0U;
+    config->controlParameterMagnitude      = 2U;
+    config->integralProportionalRatio      = 2U;
 }
 
+/*!
+ * brief Configure the DCDC loop control.
+ *
+ * param base DCDC peripheral base address.
+ * param config Pointer to configuration structure. See to "dcdc_loop_control_config_t".
+ */
 void DCDC_SetLoopControlConfig(DCDC_Type *base, const dcdc_loop_control_config_t *config)
 {
     assert(NULL != config);
@@ -268,10 +344,9 @@ void DCDC_SetLoopControlConfig(DCDC_Type *base, const dcdc_loop_control_config_t
     base->REG1 = tmp32;
 
     /* configure the DCDC_REG2 register. */
-    tmp32 = base->REG2 &
-            ~(DCDC_REG2_LOOPCTRL_HYST_SIGN_MASK | DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_MASK |
-              DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK | DCDC_REG2_LOOPCTRL_DC_FF_MASK | DCDC_REG2_LOOPCTRL_DC_R_MASK |
-              DCDC_REG2_LOOPCTRL_DC_C_MASK);
+    tmp32 = base->REG2 & ~(DCDC_REG2_LOOPCTRL_HYST_SIGN_MASK | DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_MASK |
+                           DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK | DCDC_REG2_LOOPCTRL_DC_FF_MASK |
+                           DCDC_REG2_LOOPCTRL_DC_R_MASK | DCDC_REG2_LOOPCTRL_DC_C_MASK);
     tmp32 |= DCDC_REG2_LOOPCTRL_DC_FF(config->complementFeedForwardStep) |
              DCDC_REG2_LOOPCTRL_DC_R(config->controlParameterMagnitude) |
              DCDC_REG2_LOOPCTRL_DC_C(config->integralProportionalRatio) |
@@ -287,6 +362,12 @@ void DCDC_SetLoopControlConfig(DCDC_Type *base, const dcdc_loop_control_config_t
     base->REG2 = tmp32;
 }
 
+/*!
+ * brief Configure for the min power.
+ *
+ * param base DCDC peripheral base address.
+ * param config Pointer to configuration structure. See to "dcdc_min_power_config_t".
+ */
 void DCDC_SetMinPowerConfig(DCDC_Type *base, const dcdc_min_power_config_t *config)
 {
     assert(NULL != config);
@@ -301,6 +382,18 @@ void DCDC_SetMinPowerConfig(DCDC_Type *base, const dcdc_min_power_config_t *conf
     base->REG3 = tmp32;
 }
 
+/*!
+ * brief Adjust the target voltage of VDD_SOC in run mode and low power mode.
+ *
+ * This function is to adjust the target voltage of DCDC output. Change them and finally wait until the output is
+ * stabled.
+ * Set the target value of run mode the same as low power mode before entering power save mode, because DCDC will switch
+ * back to run mode if it detects the current loading is larger than about 50 mA(typical value).
+ *
+ * param base DCDC peripheral base address.
+ * param VDDRun Target value in run mode. 25 mV each step from 0x00 to 0x1F. 00 is for 0.8V, 0x1F is for 1.575V.
+ * param VDDStandby Target value in low power mode. 25 mV each step from 0x00 to 0x4. 00 is for 0.9V, 0x4 is for 1.0V.
+ */
 void DCDC_AdjustTargetVoltage(DCDC_Type *base, uint32_t VDDRun, uint32_t VDDStandby)
 {
     uint32_t tmp32;
@@ -321,6 +414,12 @@ void DCDC_AdjustTargetVoltage(DCDC_Type *base, uint32_t VDDRun, uint32_t VDDStan
     }
 }
 
+/*!
+ * brief Configure the DCDC internal regulator.
+ *
+ * param base DCDC peripheral base address.
+ * param config Pointer to configuration structure. See to "dcdc_internal_regulator_config_t".
+ */
 void DCDC_SetInternalRegulatorConfig(DCDC_Type *base, const dcdc_internal_regulator_config_t *config)
 {
     assert(NULL != config);
@@ -337,6 +436,16 @@ void DCDC_SetInternalRegulatorConfig(DCDC_Type *base, const dcdc_internal_regula
     base->REG1 = tmp32;
 }
 
+/*!
+ * brief Boot DCDC into DCM(discontinous conduction mode).
+ *
+ *  pwd_zcd=0x0;
+ *  pwd_cmp_offset=0x0;
+ *  dcdc_loopctrl_en_rcscale=0x3 or 0x5;
+ *  DCM_set_ctrl=1'b1;
+ *
+ * param base DCDC peripheral base address.
+ */
 void DCDC_BootIntoDCM(DCDC_Type *base)
 {
     base->REG0 &= ~(DCDC_REG0_PWD_ZCD_MASK | DCDC_REG0_PWD_CMP_OFFSET_MASK);
@@ -344,6 +453,15 @@ void DCDC_BootIntoDCM(DCDC_Type *base)
                  DCDC_REG2_DCM_SET_CTRL_MASK;
 }
 
+/*!
+ * brief Boot DCDC into CCM(continous conduction mode).
+ *
+ *  pwd_zcd=0x1;
+ *  pwd_cmp_offset=0x0;
+ *  dcdc_loopctrl_en_rcscale=0x3;
+ *
+ * param base DCDC peripheral base address.
+ */
 void DCDC_BootIntoCCM(DCDC_Type *base)
 {
     base->REG0 = (~DCDC_REG0_PWD_CMP_OFFSET_MASK & base->REG0) | DCDC_REG0_PWD_ZCD_MASK;
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_dcdc.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_dcdc.h
index 647d3a85894..62636f4186b 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_dcdc.h
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_dcdc.h
@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
- * Copyright (c) 2017, NXP
+ * Copyright 2017, NXP
  * All rights reserved.
  *
- * 
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
  *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #ifndef __FSL_DCDC_H__
@@ -48,27 +22,27 @@
 /*! @brief DCDC driver version. */
 #define FSL_DCDC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */
                                                         /*!
-                                                        * @brief DCDC status flags.
-                                                        */
+                                                         * @brief DCDC status flags.
+                                                         */
 enum _dcdc_status_flags_t
 {
     kDCDC_LockedOKStatus = (1U << 0U), /*!< Indicate DCDC status. 1'b1: DCDC already settled 1'b0: DCDC is settling. */
 };
 
 /*!
-* @brief The current bias of low power comparator.
-*/
+ * @brief The current bias of low power comparator.
+ */
 typedef enum _dcdc_comparator_current_bias
 {
-    kDCDC_ComparatorCurrentBias50nA = 0U,  /*!< The current bias of low power comparator is 50nA. */
+    kDCDC_ComparatorCurrentBias50nA  = 0U, /*!< The current bias of low power comparator is 50nA. */
     kDCDC_ComparatorCurrentBias100nA = 1U, /*!< The current bias of low power comparator is 100nA. */
     kDCDC_ComparatorCurrentBias200nA = 2U, /*!< The current bias of low power comparator is 200nA. */
     kDCDC_ComparatorCurrentBias400nA = 3U, /*!< The current bias of low power comparator is 400nA. */
 } dcdc_comparator_current_bias_t;
 
 /*!
-* @brief The threshold of over current detection.
-*/
+ * @brief The threshold of over current detection.
+ */
 typedef enum _dcdc_over_current_threshold
 {
     kDCDC_OverCurrentThresholdAlt0 = 0U, /*!< 1A in the run mode, 0.25A in the power save mode. */
@@ -78,8 +52,8 @@ typedef enum _dcdc_over_current_threshold
 } dcdc_over_current_threshold_t;
 
 /*!
-* @brief The threshold if peak current detection.
-*/
+ * @brief The threshold if peak current detection.
+ */
 typedef enum _dcdc_peak_current_threshold
 {
     kDCDC_PeakCurrentThresholdAlt0 = 0U, /*!< 150mA peak current threshold. */
@@ -91,23 +65,23 @@ typedef enum _dcdc_peak_current_threshold
 } dcdc_peak_current_threshold_t;
 
 /*!
-* @brief The period of counting the charging times in power save mode.
-*/
+ * @brief The period of counting the charging times in power save mode.
+ */
 typedef enum _dcdc_count_charging_time_period
 {
-    kDCDC_CountChargingTimePeriod8Cycle = 0U,  /*!< Eight 32k cycle. */
+    kDCDC_CountChargingTimePeriod8Cycle  = 0U, /*!< Eight 32k cycle. */
     kDCDC_CountChargingTimePeriod16Cycle = 1U, /*!< Sixteen 32k cycle. */
 } dcdc_count_charging_time_period_t;
 
 /*!
-* @brief The threshold of the counting number of charging times
-*/
+ * @brief The threshold of the counting number of charging times
+ */
 typedef enum _dcdc_count_charging_time_threshold
 {
     kDCDC_CountChargingTimeThreshold32 = 0U, /*!< 0x0: 32. */
     kDCDC_CountChargingTimeThreshold64 = 1U, /*!< 0x1: 64. */
     kDCDC_CountChargingTimeThreshold16 = 2U, /*!< 0x2: 16. */
-    kDCDC_CountChargingTimeThreshold8 = 3U,  /*!< 0x3: 8. */
+    kDCDC_CountChargingTimeThreshold8  = 3U, /*!< 0x3: 8. */
 } dcdc_count_charging_time_threshold_t;
 
 /*!
@@ -115,14 +89,14 @@ typedef enum _dcdc_count_charging_time_threshold
  */
 typedef enum _dcdc_clock_source
 {
-    kDCDC_ClockAutoSwitch = 0U,  /*!< Automatic clock switch from internal oscillator to external clock. */
+    kDCDC_ClockAutoSwitch  = 0U, /*!< Automatic clock switch from internal oscillator to external clock. */
     kDCDC_ClockInternalOsc = 1U, /*!< Use internal oscillator. */
     kDCDC_ClockExternalOsc = 2U, /*!< Use external 24M crystal oscillator. */
 } dcdc_clock_source_t;
 
 /*!
-* @brief Configuration for DCDC detection.
-*/
+ * @brief Configuration for DCDC detection.
+ */
 typedef struct _dcdc_detection_config
 {
     bool enableXtalokDetection;         /*!< Enable xtalok detection circuit. */
@@ -137,8 +111,8 @@ typedef struct _dcdc_detection_config
 } dcdc_detection_config_t;
 
 /*!
-* @brief Configuration for the loop control.
-*/
+ * @brief Configuration for the loop control.
+ */
 typedef struct _dcdc_loop_control_config
 {
     bool enableCommonHysteresis;         /*!< Enable hysteresis in switching converter common mode analog comparators.
@@ -160,8 +134,8 @@ typedef struct _dcdc_loop_control_config
                                            optimize efficiency and loop response. */
 } dcdc_loop_control_config_t;
 /*!
-* @brief Configuration for DCDC low power.
-*/
+ * @brief Configuration for DCDC low power.
+ */
 typedef struct _dcdc_low_power_config
 {
     bool enableOverloadDetection; /*!< Enable the overload detection in power save mode, if current is larger than the
@@ -176,8 +150,8 @@ typedef struct _dcdc_low_power_config
 } dcdc_low_power_config_t;
 
 /*!
-* @brief Configuration for DCDC internal regulator.
-*/
+ * @brief Configuration for DCDC internal regulator.
+ */
 typedef struct _dcdc_internal_regulator_config
 {
     bool enableLoadResistor; /*!< control the load resistor of the internal regulator of DCDC, the load resistor is
@@ -206,17 +180,17 @@ extern "C" {
  */
 
 /*!
-* @brief Enable the access to DCDC registers.
-*
-* @param base DCDC peripheral base address.
-*/
+ * @brief Enable the access to DCDC registers.
+ *
+ * @param base DCDC peripheral base address.
+ */
 void DCDC_Init(DCDC_Type *base);
 
 /*!
-* @brief Disable the access to DCDC registers.
-*
-* @param base DCDC peripheral base address.
-*/
+ * @brief Disable the access to DCDC registers.
+ *
+ * @param base DCDC peripheral base address.
+ */
 void DCDC_Deinit(DCDC_Type *base);
 
 /* @} */
@@ -227,11 +201,11 @@ void DCDC_Deinit(DCDC_Type *base);
  */
 
 /*!
-* @brief Get DCDC status flags.
-*
-* @param base peripheral base address.
-* @return Mask of asserted status flags. See to "_dcdc_status_flags_t".
-*/
+ * @brief Get DCDC status flags.
+ *
+ * @param base peripheral base address.
+ * @return Mask of asserted status flags. See to "_dcdc_status_flags_t".
+ */
 uint32_t DCDC_GetstatusFlags(DCDC_Type *base);
 
 /* @} */
@@ -262,79 +236,79 @@ static inline void DCDC_EnableOutputRangeComparator(DCDC_Type *base, bool enable
 }
 
 /*!
-* @brief Configure the DCDC clock source.
-*
-* @param base DCDC peripheral base address.
-* @param clockSource Clock source for DCDC. See to "dcdc_clock_source_t".
-*/
+ * @brief Configure the DCDC clock source.
+ *
+ * @param base DCDC peripheral base address.
+ * @param clockSource Clock source for DCDC. See to "dcdc_clock_source_t".
+ */
 void DCDC_SetClockSource(DCDC_Type *base, dcdc_clock_source_t clockSource);
 
 /*!
-* @brief Get the default setting for detection configuration.
-*
-* The default configuration are set according to responding registers' setting when powered on.
-* They are:
-* @code
-*   config->enableXtalokDetection = false;
-*   config->powerDownOverVoltageDetection = true;
-*   config->powerDownLowVlotageDetection = false;
-*   config->powerDownOverCurrentDetection = true;
-*   config->powerDownPeakCurrentDetection = true;
-*   config->powerDownZeroCrossDetection = true;
-*   config->OverCurrentThreshold = kDCDC_OverCurrentThresholdAlt0;
-*   config->PeakCurrentThreshold = kDCDC_PeakCurrentThresholdAlt0;
-* @endcode
-*
-* @param config Pointer to configuration structure. See to "dcdc_detection_config_t"
-*/
+ * @brief Get the default setting for detection configuration.
+ *
+ * The default configuration are set according to responding registers' setting when powered on.
+ * They are:
+ * @code
+ *   config->enableXtalokDetection = false;
+ *   config->powerDownOverVoltageDetection = true;
+ *   config->powerDownLowVlotageDetection = false;
+ *   config->powerDownOverCurrentDetection = true;
+ *   config->powerDownPeakCurrentDetection = true;
+ *   config->powerDownZeroCrossDetection = true;
+ *   config->OverCurrentThreshold = kDCDC_OverCurrentThresholdAlt0;
+ *   config->PeakCurrentThreshold = kDCDC_PeakCurrentThresholdAlt0;
+ * @endcode
+ *
+ * @param config Pointer to configuration structure. See to "dcdc_detection_config_t"
+ */
 void DCDC_GetDefaultDetectionConfig(dcdc_detection_config_t *config);
 
 /*!
-* @breif Configure the DCDC detection.
-*
-* @param base DCDC peripheral base address.
-* @param config Pointer to configuration structure. See to "dcdc_detection_config_t"
-*/
+ * @breif Configure the DCDC detection.
+ *
+ * @param base DCDC peripheral base address.
+ * @param config Pointer to configuration structure. See to "dcdc_detection_config_t"
+ */
 void DCDC_SetDetectionConfig(DCDC_Type *base, const dcdc_detection_config_t *config);
 
 /*!
-* @brief Get the default setting for low power configuration.
-*
-* The default configuration are set according to responding registers' setting when powered on.
-* They are:
-* @code
-*   config->enableOverloadDetection = true;
-*   config->enableAdjustHystereticValue = false;
-*   config->countChargingTimePeriod = kDCDC_CountChargingTimePeriod8Cycle;
-*   config->countChargingTimeThreshold = kDCDC_CountChargingTimeThreshold32;
-* @endcode
-*
-* @param config Pointer to configuration structure. See to "dcdc_low_power_config_t"
-*/
+ * @brief Get the default setting for low power configuration.
+ *
+ * The default configuration are set according to responding registers' setting when powered on.
+ * They are:
+ * @code
+ *   config->enableOverloadDetection = true;
+ *   config->enableAdjustHystereticValue = false;
+ *   config->countChargingTimePeriod = kDCDC_CountChargingTimePeriod8Cycle;
+ *   config->countChargingTimeThreshold = kDCDC_CountChargingTimeThreshold32;
+ * @endcode
+ *
+ * @param config Pointer to configuration structure. See to "dcdc_low_power_config_t"
+ */
 void DCDC_GetDefaultLowPowerConfig(dcdc_low_power_config_t *config);
 
 /*!
-* @brief Configure the DCDC low power.
-*
-* @param base DCDC peripheral base address.
-* @param config Pointer to configuration structure. See to "dcdc_low_power_config_t".
-*/
+ * @brief Configure the DCDC low power.
+ *
+ * @param base DCDC peripheral base address.
+ * @param config Pointer to configuration structure. See to "dcdc_low_power_config_t".
+ */
 void DCDC_SetLowPowerConfig(DCDC_Type *base, const dcdc_low_power_config_t *config);
 
 /*!
-* @brief Reset current alert signal. Alert signal is generate by peak current detection.
-*
-* @param base DCDC peripheral base address.
-* @param enable Switcher to reset signal. True means reset signal. False means don't reset signal.
-*/
+ * @brief Reset current alert signal. Alert signal is generate by peak current detection.
+ *
+ * @param base DCDC peripheral base address.
+ * @param enable Switcher to reset signal. True means reset signal. False means don't reset signal.
+ */
 void DCDC_ResetCurrentAlertSignal(DCDC_Type *base, bool enable);
 
 /*!
-* @brief Set the bangap trim value to trim bandgap voltage.
-*
-* @param base DCDC peripheral base address.
-* @param TrimValue The bangap trim value. Available range is 0U-31U.
-*/
+ * @brief Set the bangap trim value to trim bandgap voltage.
+ *
+ * @param base DCDC peripheral base address.
+ * @param TrimValue The bangap trim value. Available range is 0U-31U.
+ */
 static inline void DCDC_SetBandgapVoltageTrimValue(DCDC_Type *base, uint32_t trimValue)
 {
     base->REG1 &= ~DCDC_REG1_VBG_TRIM_MASK;
@@ -342,31 +316,31 @@ static inline void DCDC_SetBandgapVoltageTrimValue(DCDC_Type *base, uint32_t tri
 }
 
 /*!
-* @brief Get the default setting for loop control configuration.
-*
-* The default configuration are set according to responding registers' setting when powered on.
-* They are:
-* @code
-*   config->enableCommonHysteresis = false;
-*   config->enableCommonThresholdDetection = false;
-*   config->enableInvertHysteresisSign = false;
-*   config->enableRCThresholdDetection = false;
-*   config->enableRCScaleCircuit = 0U;
-*   config->complementFeedForwardStep = 0U;
-*   config->controlParameterMagnitude = 2U;
-*   config->integralProportionalRatio = 2U;
-* @endcode
-*
-* @param config Pointer to configuration structure. See to "dcdc_loop_control_config_t"
-*/
+ * @brief Get the default setting for loop control configuration.
+ *
+ * The default configuration are set according to responding registers' setting when powered on.
+ * They are:
+ * @code
+ *   config->enableCommonHysteresis = false;
+ *   config->enableCommonThresholdDetection = false;
+ *   config->enableInvertHysteresisSign = false;
+ *   config->enableRCThresholdDetection = false;
+ *   config->enableRCScaleCircuit = 0U;
+ *   config->complementFeedForwardStep = 0U;
+ *   config->controlParameterMagnitude = 2U;
+ *   config->integralProportionalRatio = 2U;
+ * @endcode
+ *
+ * @param config Pointer to configuration structure. See to "dcdc_loop_control_config_t"
+ */
 void DCDC_GetDefaultLoopControlConfig(dcdc_loop_control_config_t *config);
 
 /*!
-* @brief Configure the DCDC loop control.
-*
-* @param base DCDC peripheral base address.
-* @param config Pointer to configuration structure. See to "dcdc_loop_control_config_t".
-*/
+ * @brief Configure the DCDC loop control.
+ *
+ * @param base DCDC peripheral base address.
+ * @param config Pointer to configuration structure. See to "dcdc_loop_control_config_t".
+ */
 void DCDC_SetLoopControlConfig(DCDC_Type *base, const dcdc_loop_control_config_t *config);
 
 /*!
@@ -378,11 +352,11 @@ void DCDC_SetLoopControlConfig(DCDC_Type *base, const dcdc_loop_control_config_t
 void DCDC_SetMinPowerConfig(DCDC_Type *base, const dcdc_min_power_config_t *config);
 
 /*!
-* @brief Set the current bias of low power comparator.
-*
-* @param base DCDC peripheral base address.
-* @param biasVaule The current bias of low power comparator. Refer to "dcdc_comparator_current_bias_t".
-*/
+ * @brief Set the current bias of low power comparator.
+ *
+ * @param base DCDC peripheral base address.
+ * @param biasVaule The current bias of low power comparator. Refer to "dcdc_comparator_current_bias_t".
+ */
 static inline void DCDC_SetLPComparatorBiasValue(DCDC_Type *base, dcdc_comparator_current_bias_t biasVaule)
 {
     base->REG1 &= ~DCDC_REG1_LP_CMP_ISRC_SEL_MASK;
@@ -395,33 +369,33 @@ static inline void DCDC_LockTargetVoltage(DCDC_Type *base)
 }
 
 /*!
-* @brief Adjust the target voltage of VDD_SOC in run mode and low power mode.
-*
-* This function is to adjust the target voltage of DCDC output. Change them and finally wait until the output is
-* stabled.
-* Set the target value of run mode the same as low power mode before entering power save mode, because DCDC will switch
-* back to run mode if it detects the current loading is larger than about 50 mA(typical value).
-*
-* @param base DCDC peripheral base address.
-* @param VDDRun Target value in run mode. 25 mV each step from 0x00 to 0x1F. 00 is for 0.8V, 0x1F is for 1.575V.
-* @param VDDStandby Target value in low power mode. 25 mV each step from 0x00 to 0x4. 00 is for 0.9V, 0x4 is for 1.0V.
-*/
+ * @brief Adjust the target voltage of VDD_SOC in run mode and low power mode.
+ *
+ * This function is to adjust the target voltage of DCDC output. Change them and finally wait until the output is
+ * stabled.
+ * Set the target value of run mode the same as low power mode before entering power save mode, because DCDC will switch
+ * back to run mode if it detects the current loading is larger than about 50 mA(typical value).
+ *
+ * @param base DCDC peripheral base address.
+ * @param VDDRun Target value in run mode. 25 mV each step from 0x00 to 0x1F. 00 is for 0.8V, 0x1F is for 1.575V.
+ * @param VDDStandby Target value in low power mode. 25 mV each step from 0x00 to 0x4. 00 is for 0.9V, 0x4 is for 1.0V.
+ */
 void DCDC_AdjustTargetVoltage(DCDC_Type *base, uint32_t VDDRun, uint32_t VDDStandby);
 
 /*!
-* @brief Configure the DCDC internal regulator.
-*
-* @param base DCDC peripheral base address.
-* @param config Pointer to configuration structure. See to "dcdc_internal_regulator_config_t".
-*/
+ * @brief Configure the DCDC internal regulator.
+ *
+ * @param base DCDC peripheral base address.
+ * @param config Pointer to configuration structure. See to "dcdc_internal_regulator_config_t".
+ */
 void DCDC_SetInternalRegulatorConfig(DCDC_Type *base, const dcdc_internal_regulator_config_t *config);
 
 /*!
-* @brief Ajust delay to reduce ground noise.
-*
-* @param base DCDC peripheral base address.
-* @param enable Enable the feature or not.
-*/
+ * @brief Ajust delay to reduce ground noise.
+ *
+ * @param base DCDC peripheral base address.
+ * @param enable Enable the feature or not.
+ */
 static inline void DCDC_EnableAdjustDelay(DCDC_Type *base, bool enable)
 {
     if (enable)
@@ -435,12 +409,12 @@ static inline void DCDC_EnableAdjustDelay(DCDC_Type *base, bool enable)
 }
 
 /*!
-* @brief Enable/Disable to improve the transition from heavy load to light load. It is valid while zero
-*        cross detection is enabled. If ouput exceeds the threshold, DCDC would return CCM from DCM.
-*
-* @param base DCDC peripheral base address.
-* @param enable Enable the feature or not.
-*/
+ * @brief Enable/Disable to improve the transition from heavy load to light load. It is valid while zero
+ *        cross detection is enabled. If ouput exceeds the threshold, DCDC would return CCM from DCM.
+ *
+ * @param base DCDC peripheral base address.
+ * @param enable Enable the feature or not.
+ */
 static inline void DCDC_EnableImproveTransition(DCDC_Type *base, bool enable)
 {
     if (enable)
@@ -461,26 +435,26 @@ static inline void DCDC_EnableImproveTransition(DCDC_Type *base, bool enable)
  */
 
 /*!
-* @brief Boot DCDC into DCM(discontinous conduction mode).
-*
-*  pwd_zcd=0x0;
-*  pwd_cmp_offset=0x0;
-*  dcdc_loopctrl_en_rcscale=0x3 or 0x5;
-*  DCM_set_ctrl=1'b1;
-*
-* @param base DCDC peripheral base address.
-*/
+ * @brief Boot DCDC into DCM(discontinous conduction mode).
+ *
+ *  pwd_zcd=0x0;
+ *  pwd_cmp_offset=0x0;
+ *  dcdc_loopctrl_en_rcscale=0x3 or 0x5;
+ *  DCM_set_ctrl=1'b1;
+ *
+ * @param base DCDC peripheral base address.
+ */
 void DCDC_BootIntoDCM(DCDC_Type *base);
 
 /*!
-* @brief Boot DCDC into CCM(continous conduction mode).
-*
-*  pwd_zcd=0x1;
-*  pwd_cmp_offset=0x0;
-*  dcdc_loopctrl_en_rcscale=0x3;
-*
-* @param base DCDC peripheral base address.
-*/
+ * @brief Boot DCDC into CCM(continous conduction mode).
+ *
+ *  pwd_zcd=0x1;
+ *  pwd_cmp_offset=0x0;
+ *  dcdc_loopctrl_en_rcscale=0x3;
+ *
+ * @param base DCDC peripheral base address.
+ */
 void DCDC_BootIntoCCM(DCDC_Type *base);
 
 #if defined(__cplusplus)
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_dcp.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_dcp.c
index fdc13fa0fc6..b5d2dee619a 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_dcp.c
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_dcp.c
@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
- * Copyright 2017 NXP
+ * Copyright 2017-2019 NXP
  * All rights reserved.
  *
- * 
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
  *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include "fsl_dcp.h"
@@ -43,7 +17,6 @@
 #define FSL_COMPONENT_ID "platform.drivers.dcp"
 #endif
 
-
 /*! Compile time sizeof() check */
 #define BUILD_ASSURE(condition, msg) extern int msg[1 - 2 * (!(condition))] __attribute__((unused))
 
@@ -79,20 +52,20 @@ typedef struct _dcp_hash_ctx_internal
 /*!< SHA-1/SHA-2 digest length in bytes  */
 enum _dcp_hash_digest_len
 {
-    kDCP_OutLenSha1 = 20u,
+    kDCP_OutLenSha1   = 20u,
     kDCP_OutLenSha256 = 32u,
-    kDCP_OutLenCrc32 = 4u,
+    kDCP_OutLenCrc32  = 4u,
 };
 
 enum _dcp_work_packet_bit_definitions
 {
-    kDCP_CONTROL0_DECR_SEMAPHOR = 1u << 1, /* DECR_SEMAPHOR */
-    kDCP_CONTROL0_ENABLE_HASH = 1u << 6,   /* ENABLE_HASH */
-    kDCP_CONTROL0_HASH_INIT = 1u << 12,    /* HASH_INIT */
-    kDCP_CONTROL0_HASH_TERM = 1u << 13,    /* HASH_TERM */
+    kDCP_CONTROL0_DECR_SEMAPHOR      = 1u << 1,  /* DECR_SEMAPHOR */
+    kDCP_CONTROL0_ENABLE_HASH        = 1u << 6,  /* ENABLE_HASH */
+    kDCP_CONTROL0_HASH_INIT          = 1u << 12, /* HASH_INIT */
+    kDCP_CONTROL0_HASH_TERM          = 1u << 13, /* HASH_TERM */
     kDCP_CONTROL1_HASH_SELECT_SHA256 = 2u << 16,
-    kDCP_CONTROL1_HASH_SELECT_SHA1 = 0u << 16,
-    kDCP_CONTROL1_HASH_SELECT_CRC32 = 1u << 16,
+    kDCP_CONTROL1_HASH_SELECT_SHA1   = 0u << 16,
+    kDCP_CONTROL1_HASH_SELECT_CRC32  = 1u << 16,
 };
 
 /*! 64-byte block represented as byte array of 16 32-bit words */
@@ -133,7 +106,7 @@ static status_t dcp_get_channel_status(DCP_Type *base, dcp_channel_t channel)
 {
     uint32_t statReg = 0;
     uint32_t semaReg = 0;
-    status_t status = kStatus_Fail;
+    status_t status  = kStatus_Fail;
 
     switch (channel)
     {
@@ -172,7 +145,11 @@ static status_t dcp_get_channel_status(DCP_Type *base, dcp_channel_t channel)
 static void dcp_clear_status(DCP_Type *base)
 {
     volatile uint32_t *dcpStatClrPtr = &base->STAT + 2u;
-    *dcpStatClrPtr = 0xFFu;
+    *dcpStatClrPtr                   = 0xFFu;
+
+    while(base->STAT & 0xffu)
+    {
+    }
 }
 
 static void dcp_clear_channel_status(DCP_Type *base, uint32_t mask)
@@ -181,22 +158,22 @@ static void dcp_clear_channel_status(DCP_Type *base, uint32_t mask)
 
     if (mask & kDCP_Channel0)
     {
-        chStatClrPtr = &base->CH0STAT + 2u;
+        chStatClrPtr  = &base->CH0STAT + 2u;
         *chStatClrPtr = 0xFFu;
     }
     if (mask & kDCP_Channel1)
     {
-        chStatClrPtr = &base->CH1STAT + 2u;
+        chStatClrPtr  = &base->CH1STAT + 2u;
         *chStatClrPtr = 0xFFu;
     }
     if (mask & kDCP_Channel2)
     {
-        chStatClrPtr = &base->CH2STAT + 2u;
+        chStatClrPtr  = &base->CH2STAT + 2u;
         *chStatClrPtr = 0xFFu;
     }
     if (mask & kDCP_Channel3)
     {
-        chStatClrPtr = &base->CH3STAT + 2u;
+        chStatClrPtr  = &base->CH3STAT + 2u;
         *chStatClrPtr = 0xFFu;
     }
 }
@@ -205,7 +182,7 @@ static status_t dcp_aes_set_sram_based_key(DCP_Type *base, dcp_handle_t *handle,
 {
     base->KEY = DCP_KEY_INDEX(handle->keySlot) | DCP_KEY_SUBWORD(0);
     /* move the key by 32-bit words */
-    int i = 0;
+    int i          = 0;
     size_t keySize = 16u;
     while (keySize)
     {
@@ -216,6 +193,11 @@ static status_t dcp_aes_set_sram_based_key(DCP_Type *base, dcp_handle_t *handle,
     return kStatus_Success;
 }
 
+/* Disable optimizations for GCC to prevent instruction reordering */
+#if defined(__GNUC__)
+#pragma GCC push_options
+#pragma GCC optimize ("O0")
+#endif
 static status_t dcp_schedule_work(DCP_Type *base, dcp_handle_t *handle, dcp_work_packet_t *dcpPacket)
 {
     status_t status;
@@ -263,7 +245,11 @@ static status_t dcp_schedule_work(DCP_Type *base, dcp_handle_t *handle, dcp_work
                 /* set out packet to DCP CMDPTR */
                 *cmdptr = (uint32_t)dcpPacket;
 
-                /* set the channel semaphore */
+                /* Make sure that all data memory accesses are completed before starting of the job */
+                __DSB();
+                __ISB();
+
+                /* set the channel semaphore to start the job */
                 *chsema = 1u;
             }
 
@@ -285,7 +271,28 @@ static status_t dcp_schedule_work(DCP_Type *base, dcp_handle_t *handle, dcp_work
 
     return status;
 }
+#if defined(__GNUC__)
+#pragma GCC pop_options
+#endif
 
+/*!
+ * brief Set AES key to dcp_handle_t struct and optionally to DCP.
+ *
+ * Sets the AES key for encryption/decryption with the dcp_handle_t structure.
+ * The dcp_handle_t input argument specifies keySlot.
+ * If the keySlot is kDCP_OtpKey, the function will check the OTP_KEY_READY bit and will return it's ready to use
+ * status.
+ * For other keySlot selections, the function will copy and hold the key in dcp_handle_t struct.
+ * If the keySlot is one of the four DCP SRAM-based keys (one of kDCP_KeySlot0, kDCP_KeySlot1, kDCP_KeySlot2,
+ * kDCP_KeySlot3),
+ * this function will also load the supplied key to the specified keySlot in DCP.
+ *
+ * param   base DCP peripheral base address.
+ * param   handle Handle used for the request.
+ * param   key 0-mod-4 aligned pointer to AES key.
+ * param   keySize AES key size in bytes. Shall equal 16.
+ * return  status from set key operation
+ */
 status_t DCP_AES_SetKey(DCP_Type *base, dcp_handle_t *handle, const uint8_t *key, size_t keySize)
 {
     status_t status = kStatus_Fail;
@@ -336,6 +343,19 @@ status_t DCP_AES_SetKey(DCP_Type *base, dcp_handle_t *handle, const uint8_t *key
     return status;
 }
 
+/*!
+ * brief Encrypts AES on one or multiple 128-bit block(s).
+ *
+ * Encrypts AES.
+ * The source plaintext and destination ciphertext can overlap in system memory.
+ *
+ * param base DCP peripheral base address
+ * param handle Handle used for this request.
+ * param plaintext Input plain text to encrypt
+ * param[out] ciphertext Output cipher text
+ * param size Size of input and output data in bytes. Must be multiple of 16 bytes.
+ * return Status from encrypt operation
+ */
 status_t DCP_AES_EncryptEcb(
     DCP_Type *base, dcp_handle_t *handle, const uint8_t *plaintext, uint8_t *ciphertext, size_t size)
 {
@@ -355,6 +375,20 @@ status_t DCP_AES_EncryptEcb(
     return DCP_WaitForChannelComplete(base, handle);
 }
 
+/*!
+ * brief Encrypts AES using the ECB block mode.
+ *
+ * Puts AES ECB encrypt work packet to DCP channel.
+ *
+ * param base DCP peripheral base address
+ * param handle Handle used for this request.
+ * param[out] dcpPacket Memory for the DCP work packet.
+ * param plaintext Input plain text to encrypt.
+ * param[out] ciphertext Output cipher text
+ * param size Size of input and output data in bytes. Must be multiple of 16 bytes.
+ * return kStatus_Success The work packet has been scheduled at DCP channel.
+ * return kStatus_DCP_Again The DCP channel is busy processing previous request.
+ */
 status_t DCP_AES_EncryptEcbNonBlocking(DCP_Type *base,
                                        dcp_handle_t *handle,
                                        dcp_work_packet_t *dcpPacket,
@@ -368,10 +402,11 @@ status_t DCP_AES_EncryptEcbNonBlocking(DCP_Type *base,
         return kStatus_InvalidArgument;
     }
 
-    dcpPacket->control0 = 0x122u; /* CIPHER_ENCRYPT | ENABLE_CIPHER | DECR_SEMAPHORE */
-    dcpPacket->sourceBufferAddress = (uint32_t)plaintext;
+    dcpPacket->control0 =
+        0x122u | (handle->swapConfig & 0xFC0000u); /* CIPHER_ENCRYPT | ENABLE_CIPHER | DECR_SEMAPHORE */
+    dcpPacket->sourceBufferAddress      = (uint32_t)plaintext;
     dcpPacket->destinationBufferAddress = (uint32_t)ciphertext;
-    dcpPacket->bufferSize = (uint32_t)size;
+    dcpPacket->bufferSize               = (uint32_t)size;
 
     if (handle->keySlot == kDCP_OtpKey)
     {
@@ -397,6 +432,19 @@ status_t DCP_AES_EncryptEcbNonBlocking(DCP_Type *base,
     return dcp_schedule_work(base, handle, dcpPacket);
 }
 
+/*!
+ * brief Decrypts AES on one or multiple 128-bit block(s).
+ *
+ * Decrypts AES.
+ * The source ciphertext and destination plaintext can overlap in system memory.
+ *
+ * param base DCP peripheral base address
+ * param handle Handle used for this request.
+ * param ciphertext Input plain text to encrypt
+ * param[out] plaintext Output cipher text
+ * param size Size of input and output data in bytes. Must be multiple of 16 bytes.
+ * return Status from decrypt operation
+ */
 status_t DCP_AES_DecryptEcb(
     DCP_Type *base, dcp_handle_t *handle, const uint8_t *ciphertext, uint8_t *plaintext, size_t size)
 {
@@ -416,6 +464,20 @@ status_t DCP_AES_DecryptEcb(
     return DCP_WaitForChannelComplete(base, handle);
 }
 
+/*!
+ * brief Decrypts AES using ECB block mode.
+ *
+ * Puts AES ECB decrypt dcpPacket to DCP input job ring.
+ *
+ * param base DCP peripheral base address
+ * param handle Handle used for this request.
+ * param[out] dcpPacket Memory for the DCP work packet.
+ * param ciphertext Input cipher text to decrypt
+ * param[out] plaintext Output plain text
+ * param size Size of input and output data in bytes. Must be multiple of 16 bytes.
+ * return kStatus_Success The work packet has been scheduled at DCP channel.
+ * return kStatus_DCP_Again The DCP channel is busy processing previous request.
+ */
 status_t DCP_AES_DecryptEcbNonBlocking(DCP_Type *base,
                                        dcp_handle_t *handle,
                                        dcp_work_packet_t *dcpPacket,
@@ -429,10 +491,10 @@ status_t DCP_AES_DecryptEcbNonBlocking(DCP_Type *base,
         return kStatus_InvalidArgument;
     }
 
-    dcpPacket->control0 = 0x22u; /* ENABLE_CIPHER | DECR_SEMAPHORE */
-    dcpPacket->sourceBufferAddress = (uint32_t)ciphertext;
+    dcpPacket->control0                 = 0x22u | (handle->swapConfig & 0xFC0000u); /* ENABLE_CIPHER | DECR_SEMAPHORE */
+    dcpPacket->sourceBufferAddress      = (uint32_t)ciphertext;
     dcpPacket->destinationBufferAddress = (uint32_t)plaintext;
-    dcpPacket->bufferSize = (uint32_t)size;
+    dcpPacket->bufferSize               = (uint32_t)size;
 
     if (handle->keySlot == kDCP_OtpKey)
     {
@@ -458,6 +520,20 @@ status_t DCP_AES_DecryptEcbNonBlocking(DCP_Type *base,
     return dcp_schedule_work(base, handle, dcpPacket);
 }
 
+/*!
+ * brief Encrypts AES using CBC block mode.
+ *
+ * Encrypts AES using CBC block mode.
+ * The source plaintext and destination ciphertext can overlap in system memory.
+ *
+ * param base DCP peripheral base address
+ * param handle Handle used for this request.
+ * param plaintext Input plain text to encrypt
+ * param[out] ciphertext Output cipher text
+ * param size Size of input and output data in bytes. Must be multiple of 16 bytes.
+ * param iv Input initial vector to combine with the first input block.
+ * return Status from encrypt operation
+ */
 status_t DCP_AES_EncryptCbc(DCP_Type *base,
                             dcp_handle_t *handle,
                             const uint8_t *plaintext,
@@ -481,6 +557,21 @@ status_t DCP_AES_EncryptCbc(DCP_Type *base,
     return DCP_WaitForChannelComplete(base, handle);
 }
 
+/*!
+ * brief Encrypts AES using CBC block mode.
+ *
+ * Puts AES CBC encrypt dcpPacket to DCP input job ring.
+ *
+ * param base DCP peripheral base address
+ * param handle Handle used for this request. Specifies jobRing.
+ * param[out] dcpPacket Memory for the DCP work packet.
+ * param plaintext Input plain text to encrypt
+ * param[out] ciphertext Output cipher text
+ * param size Size of input and output data in bytes. Must be multiple of 16 bytes.
+ * param iv Input initial vector to combine with the first input block.
+ * return kStatus_Success The work packet has been scheduled at DCP channel.
+ * return kStatus_DCP_Again The DCP channel is busy processing previous request.
+ */
 status_t DCP_AES_EncryptCbcNonBlocking(DCP_Type *base,
                                        dcp_handle_t *handle,
                                        dcp_work_packet_t *dcpPacket,
@@ -495,11 +586,12 @@ status_t DCP_AES_EncryptCbcNonBlocking(DCP_Type *base,
         return kStatus_InvalidArgument;
     }
 
-    dcpPacket->control0 = 0x322u; /* CIPHER_INIT | CIPHER_ENCRYPT | ENABLE_CIPHER | DECR_SEMAPHORE */
-    dcpPacket->control1 = 0x10u;  /* CBC */
-    dcpPacket->sourceBufferAddress = (uint32_t)plaintext;
+    dcpPacket->control0 =
+        0x322u | (handle->swapConfig & 0xFC0000u); /* CIPHER_INIT | CIPHER_ENCRYPT | ENABLE_CIPHER | DECR_SEMAPHORE */
+    dcpPacket->control1                 = 0x10u;   /* CBC */
+    dcpPacket->sourceBufferAddress      = (uint32_t)plaintext;
     dcpPacket->destinationBufferAddress = (uint32_t)ciphertext;
-    dcpPacket->bufferSize = (uint32_t)size;
+    dcpPacket->bufferSize               = (uint32_t)size;
 
     if (handle->keySlot == kDCP_OtpKey)
     {
@@ -530,6 +622,20 @@ status_t DCP_AES_EncryptCbcNonBlocking(DCP_Type *base,
     return dcp_schedule_work(base, handle, dcpPacket);
 }
 
+/*!
+ * brief Decrypts AES using CBC block mode.
+ *
+ * Decrypts AES using CBC block mode.
+ * The source ciphertext and destination plaintext can overlap in system memory.
+ *
+ * param base DCP peripheral base address
+ * param handle Handle used for this request.
+ * param ciphertext Input cipher text to decrypt
+ * param[out] plaintext Output plain text
+ * param size Size of input and output data in bytes. Must be multiple of 16 bytes.
+ * param iv Input initial vector to combine with the first input block.
+ * return Status from decrypt operation
+ */
 status_t DCP_AES_DecryptCbc(DCP_Type *base,
                             dcp_handle_t *handle,
                             const uint8_t *ciphertext,
@@ -553,6 +659,21 @@ status_t DCP_AES_DecryptCbc(DCP_Type *base,
     return DCP_WaitForChannelComplete(base, handle);
 }
 
+/*!
+ * brief Decrypts AES using CBC block mode.
+ *
+ * Puts AES CBC decrypt dcpPacket to DCP input job ring.
+ *
+ * param base DCP peripheral base address
+ * param handle Handle used for this request. Specifies jobRing.
+ * param[out] dcpPacket Memory for the DCP work packet.
+ * param ciphertext Input cipher text to decrypt
+ * param[out] plaintext Output plain text
+ * param size Size of input and output data in bytes. Must be multiple of 16 bytes.
+ * param iv Input initial vector to combine with the first input block.
+ * return kStatus_Success The work packet has been scheduled at DCP channel.
+ * return kStatus_DCP_Again The DCP channel is busy processing previous request.
+ */
 status_t DCP_AES_DecryptCbcNonBlocking(DCP_Type *base,
                                        dcp_handle_t *handle,
                                        dcp_work_packet_t *dcpPacket,
@@ -567,11 +688,11 @@ status_t DCP_AES_DecryptCbcNonBlocking(DCP_Type *base,
         return kStatus_InvalidArgument;
     }
 
-    dcpPacket->control0 = 0x222u; /* CIPHER_INIT | ENABLE_CIPHER | DECR_SEMAPHORE */
-    dcpPacket->control1 = 0x10u;  /* CBC */
-    dcpPacket->sourceBufferAddress = (uint32_t)ciphertext;
+    dcpPacket->control0 = 0x222u | (handle->swapConfig & 0xFC0000u); /* CIPHER_INIT | ENABLE_CIPHER | DECR_SEMAPHORE */
+    dcpPacket->control1 = 0x10u;                                     /* CBC */
+    dcpPacket->sourceBufferAddress      = (uint32_t)ciphertext;
     dcpPacket->destinationBufferAddress = (uint32_t)plaintext;
-    dcpPacket->bufferSize = (uint32_t)size;
+    dcpPacket->bufferSize               = (uint32_t)size;
 
     if (handle->keySlot == kDCP_OtpKey)
     {
@@ -602,12 +723,29 @@ status_t DCP_AES_DecryptCbcNonBlocking(DCP_Type *base,
     return dcp_schedule_work(base, handle, dcpPacket);
 }
 
+/*!
+ * brief Gets the default configuration structure.
+ *
+ * This function initializes the DCP configuration structure to a default value. The default
+ * values are as follows.
+ *   dcpConfig->gatherResidualWrites = true;
+ *   dcpConfig->enableContextCaching = true;
+ *   dcpConfig->enableContextSwitching = true;
+ *   dcpConfig->enableChannnel = kDCP_chEnableAll;
+ *   dcpConfig->enableChannelInterrupt = kDCP_chIntDisable;
+ *
+ * param[out] config Pointer to configuration structure.
+ */
 void DCP_GetDefaultConfig(dcp_config_t *config)
 {
     /* ENABLE_CONTEXT_CACHING is disabled by default as the DCP Hash driver uses
      * dcp_hash_save_running_hash() and dcp_hash_restore_running_hash() to support
      * Hash context switch (different messages interleaved) on the same channel.
      */
+
+    /* Initializes the configure structure to zero. */
+    memset(config, 0, sizeof(*config));
+
     dcp_config_t userConfig = {
         true, false, true, kDCP_chEnableAll, kDCP_chIntDisable,
     };
@@ -615,6 +753,14 @@ void DCP_GetDefaultConfig(dcp_config_t *config)
     *config = userConfig;
 }
 
+/*!
+ * brief   Enables clock to and enables DCP
+ *
+ * Enable DCP clock and configure DCP.
+ *
+ * param base DCP base address
+ * param config Pointer to configuration structure.
+ */
 void DCP_Init(DCP_Type *base, const dcp_config_t *config)
 {
 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
@@ -639,6 +785,13 @@ void DCP_Init(DCP_Type *base, const dcp_config_t *config)
     base->CONTEXT = (uint32_t)&s_dcpContextSwitchingBuffer;
 }
 
+/*!
+ * brief   Disable DCP clock
+ *
+ * Reset DCP and Disable DCP clock.
+ *
+ * param base DCP base address
+ */
 void DCP_Deinit(DCP_Type *base)
 {
     base->CTRL = 0xF0800000u; /* reset value */
@@ -649,6 +802,16 @@ void DCP_Deinit(DCP_Type *base)
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }
 
+/*!
+ * brief Poll and wait on DCP channel.
+ *
+ * Polls the specified DCP channel until current it completes activity.
+ *
+ * param   base DCP peripheral base address.
+ * param   handle Specifies DCP channel.
+ * return  kStatus_Success When data processing completes without error.
+ * return  kStatus_Fail When error occurs.
+ */
 status_t DCP_WaitForChannelComplete(DCP_Type *base, dcp_handle_t *handle)
 {
     /* wait if our channel is still active */
@@ -663,6 +826,7 @@ status_t DCP_WaitForChannelComplete(DCP_Type *base, dcp_handle_t *handle)
         return kStatus_Fail;
     }
 
+    dcp_clear_status(base);
     return kStatus_Success;
 }
 
@@ -745,7 +909,7 @@ static status_t dcp_hash_engine_init(DCP_Type *base, dcp_hash_ctx_internal_t *ct
     if ((kDCP_Sha256 == ctxInternal->algo) || (kDCP_Sha1 == ctxInternal->algo) || (kDCP_Crc32 == ctxInternal->algo))
     {
         ctxInternal->ctrl0 = kDCP_CONTROL0_HASH_INIT;
-        status = kStatus_Success;
+        status             = kStatus_Success;
     }
 
     return status;
@@ -754,7 +918,8 @@ static status_t dcp_hash_engine_init(DCP_Type *base, dcp_hash_ctx_internal_t *ct
 static status_t dcp_hash_update_non_blocking(
     DCP_Type *base, dcp_hash_ctx_internal_t *ctxInternal, dcp_work_packet_t *dcpPacket, const uint8_t *msg, size_t size)
 {
-    dcpPacket->control0 = ctxInternal->ctrl0 | kDCP_CONTROL0_ENABLE_HASH | kDCP_CONTROL0_DECR_SEMAPHOR;
+    dcpPacket->control0 = ctxInternal->ctrl0 | (ctxInternal->handle->swapConfig & 0xFC0000u) |
+                          kDCP_CONTROL0_ENABLE_HASH | kDCP_CONTROL0_DECR_SEMAPHOR;
     if (ctxInternal->algo == kDCP_Sha256)
     {
         dcpPacket->control1 = kDCP_CONTROL1_HASH_SELECT_SHA256;
@@ -771,10 +936,10 @@ static status_t dcp_hash_update_non_blocking(
     {
         return kStatus_Fail;
     }
-    dcpPacket->sourceBufferAddress = (uint32_t)msg;
+    dcpPacket->sourceBufferAddress      = (uint32_t)msg;
     dcpPacket->destinationBufferAddress = 0;
-    dcpPacket->bufferSize = size;
-    dcpPacket->payloadPointer = (uint32_t)ctxInternal->runningHash;
+    dcpPacket->bufferSize               = size;
+    dcpPacket->payloadPointer           = (uint32_t)ctxInternal->runningHash;
 
     return dcp_schedule_work(base, ctxInternal->handle, dcpPacket);
 }
@@ -932,6 +1097,17 @@ static void dcp_hash_restore_running_hash(dcp_hash_ctx_internal_t *ctxInternal)
     }
 }
 
+/*!
+ * brief Initialize HASH context
+ *
+ * This function initializes the HASH.
+ *
+ * param base DCP peripheral base address
+ * param handle Specifies the DCP channel used for hashing.
+ * param[out] ctx Output hash context
+ * param algo Underlaying algorithm to use for hash computation.
+ * return Status of initialization
+ */
 status_t DCP_HASH_Init(DCP_Type *base, dcp_handle_t *handle, dcp_hash_ctx_t *ctx, dcp_hash_algo_t algo)
 {
     status_t status;
@@ -948,19 +1124,34 @@ status_t DCP_HASH_Init(DCP_Type *base, dcp_handle_t *handle, dcp_hash_ctx_t *ctx
     }
 
     /* set algorithm in context struct for later use */
-    ctxInternal = (dcp_hash_ctx_internal_t *)ctx;
-    ctxInternal->algo = algo;
+    ctxInternal        = (dcp_hash_ctx_internal_t *)ctx;
+    ctxInternal->algo  = algo;
     ctxInternal->blksz = 0u;
     for (i = 0; i < sizeof(ctxInternal->blk.w) / sizeof(ctxInternal->blk.w[0]); i++)
     {
         ctxInternal->blk.w[0] = 0u;
     }
-    ctxInternal->state = kDCP_StateHashInit;
+    ctxInternal->state           = kDCP_StateHashInit;
     ctxInternal->fullMessageSize = 0;
-    ctxInternal->handle = handle;
+    ctxInternal->handle          = handle;
     return status;
 }
 
+/*!
+ * brief Add data to current HASH
+ *
+ * Add data to current HASH. This can be called repeatedly with an arbitrary amount of data to be
+ * hashed. The functions blocks. If it returns kStatus_Success, the running hash
+ * has been updated (DCP has processed the input data), so the memory at ref input pointer
+ * can be released back to system. The DCP context buffer is updated with the running hash
+ * and with all necessary information to support possible context switch.
+ *
+ * param base DCP peripheral base address
+ * param[in,out] ctx HASH context
+ * param input Input data
+ * param inputSize Size of input data in bytes
+ * return Status of the hash update operation
+ */
 status_t DCP_HASH_Update(DCP_Type *base, dcp_hash_ctx_t *ctx, const uint8_t *input, size_t inputSize)
 {
     bool isUpdateState;
@@ -974,7 +1165,7 @@ status_t DCP_HASH_Update(DCP_Type *base, dcp_hash_ctx_t *ctx, const uint8_t *inp
     }
 
     ctxInternal = (dcp_hash_ctx_internal_t *)ctx;
-    status = dcp_hash_check_context(ctxInternal, input);
+    status      = dcp_hash_check_context(ctxInternal, input);
     if (kStatus_Success != status)
     {
         return status;
@@ -1014,6 +1205,17 @@ status_t DCP_HASH_Update(DCP_Type *base, dcp_hash_ctx_t *ctx, const uint8_t *inp
     return status;
 }
 
+/*!
+ * brief Finalize hashing
+ *
+ * Outputs the final hash (computed by DCP_HASH_Update()) and erases the context.
+ *
+ * param[in,out] ctx Input hash context
+ * param[out] output Output hash data
+ * param[in,out] outputSize Optional parameter (can be passed as NULL). On function entry, it specifies the size of
+ * output[] buffer. On function return, it stores the number of updated output bytes.
+ * return Status of the hash finish operation
+ */
 status_t DCP_HASH_Finish(DCP_Type *base, dcp_hash_ctx_t *ctx, uint8_t *output, size_t *outputSize)
 {
     size_t algOutSize = 0;
@@ -1021,7 +1223,7 @@ status_t DCP_HASH_Finish(DCP_Type *base, dcp_hash_ctx_t *ctx, uint8_t *output, s
     dcp_hash_ctx_internal_t *ctxInternal;
 
     ctxInternal = (dcp_hash_ctx_internal_t *)ctx;
-    status = dcp_hash_check_context(ctxInternal, output);
+    status      = dcp_hash_check_context(ctxInternal, output);
     if (kStatus_Success != status)
     {
         return status;
@@ -1100,6 +1302,20 @@ status_t DCP_HASH_Finish(DCP_Type *base, dcp_hash_ctx_t *ctx, uint8_t *output, s
     return status;
 }
 
+/*!
+ * brief Create HASH on given data
+ *
+ * Perform the full SHA or CRC32 in one function call. The function is blocking.
+ *
+ * param base DCP peripheral base address
+ * param handle Handle used for the request.
+ * param algo Underlaying algorithm to use for hash computation.
+ * param input Input data
+ * param inputSize Size of input data in bytes
+ * param[out] output Output hash data
+ * param[out] outputSize Output parameter storing the size of the output hash in bytes
+ * return Status of the one call hash operation.
+ */
 status_t DCP_HASH(DCP_Type *base,
                   dcp_handle_t *handle,
                   dcp_hash_algo_t algo,
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_dcp.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_dcp.h
index 15694703a63..ce6625597c6 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_dcp.h
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_dcp.h
@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
- * Copyright 2017 NXP
+ * Copyright 2017-2019 NXP
  * All rights reserved.
  *
- * 
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #ifndef _FSL_DCP_H_
@@ -53,15 +27,21 @@ enum _dcp_status
  */
 /*! @name Driver version */
 /*@{*/
-/*! @brief DCP driver version. Version 2.0.0.
+/*! @brief DCP driver version. Version 2.1.1.
  *
- * Current version: 2.0.0
+ * Current version: 2.1.1
  *
  * Change log:
+ * - Version 2.1.1
+ *   - Add DCP status clearing when channel operation is complete
+ *
+ * - 2.1.0
+ *   - Add byte/word swap feature for key, input and output data
+ *
  * - Version 2.0.0
  *   - Initial version
  */
-#define FSL_DCP_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+#define FSL_DCP_DRIVER_VERSION (MAKE_VERSION(2, 1, 1))
 /*@}*/
 
 /*! @brief DCP channel enable.
@@ -69,11 +49,11 @@ enum _dcp_status
  */
 typedef enum _dcp_ch_enable
 {
-    kDCP_chDisable = 0U,    /*!< DCP channel disable */
-    kDCP_ch0Enable = 1U,    /*!< DCP channel 0 enable */
-    kDCP_ch1Enable = 2U,    /*!< DCP channel 1 enable */
-    kDCP_ch2Enable = 4U,    /*!< DCP channel 2 enable */
-    kDCP_ch3Enable = 8U,    /*!< DCP channel 3 enable */
+    kDCP_chDisable   = 0U,  /*!< DCP channel disable */
+    kDCP_ch0Enable   = 1U,  /*!< DCP channel 0 enable */
+    kDCP_ch1Enable   = 2U,  /*!< DCP channel 1 enable */
+    kDCP_ch2Enable   = 4U,  /*!< DCP channel 2 enable */
+    kDCP_ch3Enable   = 8U,  /*!< DCP channel 3 enable */
     kDCP_chEnableAll = 15U, /*!< DCP channel enable all */
 } _dcp_ch_enable_t;
 
@@ -105,15 +85,29 @@ typedef enum _dcp_channel
  */
 typedef enum _dcp_key_slot
 {
-    kDCP_KeySlot0 = 0U,     /*!< DCP key slot 0. */
-    kDCP_KeySlot1 = 1U,     /*!< DCP key slot 1. */
-    kDCP_KeySlot2 = 2U,     /*!< DCP key slot 2.*/
-    kDCP_KeySlot3 = 3U,     /*!< DCP key slot 3. */
-    kDCP_OtpKey = 4U,       /*!< DCP OTP key. */
+    kDCP_KeySlot0     = 0U, /*!< DCP key slot 0. */
+    kDCP_KeySlot1     = 1U, /*!< DCP key slot 1. */
+    kDCP_KeySlot2     = 2U, /*!< DCP key slot 2.*/
+    kDCP_KeySlot3     = 3U, /*!< DCP key slot 3. */
+    kDCP_OtpKey       = 4U, /*!< DCP OTP key. */
     kDCP_OtpUniqueKey = 5U, /*!< DCP unique OTP key. */
-    kDCP_PayloadKey = 6U,   /*!< DCP payload key. */
+    kDCP_PayloadKey   = 6U, /*!< DCP payload key. */
 } dcp_key_slot_t;
 
+/*! @brief DCP key, input & output swap options
+ *
+ */
+typedef enum _dcp_swap
+{
+    kDCP_NoSwap         = 0x0U,
+    kDCP_KeyByteSwap    = 0x40000U,
+    kDCP_KeyWordSwap    = 0x80000U,
+    kDCP_InputByteSwap  = 0x100000U,
+    kDCP_InputWordSwap  = 0x200000U,
+    kDCP_OutputByteSwap = 0x400000U,
+    kDCP_OutputWordSwap = 0x800000U,
+} dcp_swap_t;
+
 /*! @brief DCP's work packet. */
 typedef struct _dcp_work_packet
 {
@@ -132,6 +126,7 @@ typedef struct _dcp_handle
 {
     dcp_channel_t channel;  /*!< Specify DCP channel. */
     dcp_key_slot_t keySlot; /*!< For operations with key (such as AES encryption/decryption), specify DCP key slot. */
+    uint32_t swapConfig;    /*!< For configuration of key, input, output byte/word swap options */
     uint32_t keyWord[4];
     uint32_t iv[4];
 } dcp_handle_t;
@@ -382,19 +377,19 @@ status_t DCP_AES_DecryptCbc(DCP_Type *base,
  * @{
  */
 /*!
-* @brief Encrypts AES using the ECB block mode.
-*
-* Puts AES ECB encrypt work packet to DCP channel.
-*
-* @param base DCP peripheral base address
-* @param handle Handle used for this request.
-* @param[out] dcpPacket Memory for the DCP work packet.
-* @param plaintext Input plain text to encrypt.
-* @param[out] ciphertext Output cipher text
-* @param size Size of input and output data in bytes. Must be multiple of 16 bytes.
-* @return kStatus_Success The work packet has been scheduled at DCP channel.
-* @return kStatus_DCP_Again The DCP channel is busy processing previous request.
-*/
+ * @brief Encrypts AES using the ECB block mode.
+ *
+ * Puts AES ECB encrypt work packet to DCP channel.
+ *
+ * @param base DCP peripheral base address
+ * @param handle Handle used for this request.
+ * @param[out] dcpPacket Memory for the DCP work packet.
+ * @param plaintext Input plain text to encrypt.
+ * @param[out] ciphertext Output cipher text
+ * @param size Size of input and output data in bytes. Must be multiple of 16 bytes.
+ * @return kStatus_Success The work packet has been scheduled at DCP channel.
+ * @return kStatus_DCP_Again The DCP channel is busy processing previous request.
+ */
 status_t DCP_AES_EncryptEcbNonBlocking(DCP_Type *base,
                                        dcp_handle_t *handle,
                                        dcp_work_packet_t *dcpPacket,
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_dmamux.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_dmamux.c
index 155531de5a4..8bfbe6c3676 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_dmamux.c
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_dmamux.c
@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
  * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
  *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include "fsl_dmamux.h"
@@ -43,7 +17,6 @@
 #define FSL_COMPONENT_ID "platform.drivers.dmamux"
 #endif
 
-
 /*******************************************************************************
  * Prototypes
  ******************************************************************************/
@@ -88,6 +61,14 @@ static uint32_t DMAMUX_GetInstance(DMAMUX_Type *base)
     return instance;
 }
 
+/*!
+ * brief Initializes the DMAMUX peripheral.
+ *
+ * This function ungates the DMAMUX clock.
+ *
+ * param base DMAMUX peripheral base address.
+ *
+ */
 void DMAMUX_Init(DMAMUX_Type *base)
 {
 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
@@ -95,6 +76,13 @@ void DMAMUX_Init(DMAMUX_Type *base)
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }
 
+/*!
+ * brief Deinitializes the DMAMUX peripheral.
+ *
+ * This function gates the DMAMUX clock.
+ *
+ * param base DMAMUX peripheral base address.
+ */
 void DMAMUX_Deinit(DMAMUX_Type *base)
 {
 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_dmamux.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_dmamux.h
index 17f32ee2e8d..096bb851bf8 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_dmamux.h
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_dmamux.h
@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
  * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #ifndef _FSL_DMAMUX_H_
@@ -42,15 +16,14 @@
  * @{
  */
 
-
 /*******************************************************************************
  * Definitions
  ******************************************************************************/
 
 /*! @name Driver version */
 /*@{*/
-/*! @brief DMAMUX driver version 2.0.2. */
-#define FSL_DMAMUX_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
+/*! @brief DMAMUX driver version 2.0.3. */
+#define FSL_DMAMUX_DRIVER_VERSION (MAKE_VERSION(2, 0, 3))
 /*@}*/
 
 /*******************************************************************************
@@ -101,7 +74,7 @@ void DMAMUX_Deinit(DMAMUX_Type *base);
  */
 static inline void DMAMUX_EnableChannel(DMAMUX_Type *base, uint32_t channel)
 {
-    assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
+    assert(channel < (uint32_t)FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
 
     base->CHCFG[channel] |= DMAMUX_CHCFG_ENBL_MASK;
 }
@@ -117,9 +90,9 @@ static inline void DMAMUX_EnableChannel(DMAMUX_Type *base, uint32_t channel)
  */
 static inline void DMAMUX_DisableChannel(DMAMUX_Type *base, uint32_t channel)
 {
-    assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
+    assert(channel < (uint32_t)FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
 
-    base->CHCFG[channel] &= ~DMAMUX_CHCFG_ENBL_MASK;
+    base->CHCFG[channel] &= ~(uint8_t)DMAMUX_CHCFG_ENBL_MASK;
 }
 
 /*!
@@ -131,9 +104,9 @@ static inline void DMAMUX_DisableChannel(DMAMUX_Type *base, uint32_t channel)
  */
 static inline void DMAMUX_SetSource(DMAMUX_Type *base, uint32_t channel, uint32_t source)
 {
-    assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
+    assert(channel < (uint32_t)FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
 
-    base->CHCFG[channel] = ((base->CHCFG[channel] & ~DMAMUX_CHCFG_SOURCE_MASK) | DMAMUX_CHCFG_SOURCE(source));
+    base->CHCFG[channel] = (uint8_t)((base->CHCFG[channel] & ~DMAMUX_CHCFG_SOURCE_MASK) | DMAMUX_CHCFG_SOURCE(source));
 }
 
 #if defined(FSL_FEATURE_DMAMUX_HAS_TRIG) && FSL_FEATURE_DMAMUX_HAS_TRIG > 0U
@@ -147,7 +120,7 @@ static inline void DMAMUX_SetSource(DMAMUX_Type *base, uint32_t channel, uint32_
  */
 static inline void DMAMUX_EnablePeriodTrigger(DMAMUX_Type *base, uint32_t channel)
 {
-    assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
+    assert(channel < (uint32_t)FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
 
     base->CHCFG[channel] |= DMAMUX_CHCFG_TRIG_MASK;
 }
@@ -162,9 +135,9 @@ static inline void DMAMUX_EnablePeriodTrigger(DMAMUX_Type *base, uint32_t channe
  */
 static inline void DMAMUX_DisablePeriodTrigger(DMAMUX_Type *base, uint32_t channel)
 {
-    assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
+    assert(channel < (uint32_t)FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
 
-    base->CHCFG[channel] &= ~DMAMUX_CHCFG_TRIG_MASK;
+    base->CHCFG[channel] &= ~(uint8_t)DMAMUX_CHCFG_TRIG_MASK;
 }
 #endif /* FSL_FEATURE_DMAMUX_HAS_TRIG */
 
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_edma.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_edma.c
index 96b0f800229..b0456f1d0a6 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_edma.c
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_edma.c
@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
+ * Copyright 2016-2018 NXP
  * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
  *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include "fsl_edma.h"
@@ -43,7 +17,6 @@
 #define FSL_COMPONENT_ID "platform.drivers.edma"
 #endif
 
-
 #define EDMA_TRANSFER_ENABLED_MASK 0x80U
 
 /*******************************************************************************
@@ -97,28 +70,45 @@ static uint32_t EDMA_GetInstance(DMA_Type *base)
     return instance;
 }
 
+/*!
+ * brief Push content of TCD structure into hardware TCD register.
+ *
+ * param base EDMA peripheral base address.
+ * param channel EDMA channel number.
+ * param tcd Point to TCD structure.
+ */
 void EDMA_InstallTCD(DMA_Type *base, uint32_t channel, edma_tcd_t *tcd)
 {
-    assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
+    assert(channel < (uint32_t)FSL_FEATURE_EDMA_MODULE_CHANNEL);
     assert(tcd != NULL);
-    assert(((uint32_t)tcd & 0x1FU) == 0);
+    assert(((uint32_t)tcd & 0x1FU) == 0U);
 
     /* Push tcd into hardware TCD register */
-    base->TCD[channel].SADDR = tcd->SADDR;
-    base->TCD[channel].SOFF = tcd->SOFF;
-    base->TCD[channel].ATTR = tcd->ATTR;
-    base->TCD[channel].NBYTES_MLNO = tcd->NBYTES;
-    base->TCD[channel].SLAST = tcd->SLAST;
-    base->TCD[channel].DADDR = tcd->DADDR;
-    base->TCD[channel].DOFF = tcd->DOFF;
+    base->TCD[channel].SADDR         = tcd->SADDR;
+    base->TCD[channel].SOFF          = tcd->SOFF;
+    base->TCD[channel].ATTR          = tcd->ATTR;
+    base->TCD[channel].NBYTES_MLNO   = tcd->NBYTES;
+    base->TCD[channel].SLAST         = tcd->SLAST;
+    base->TCD[channel].DADDR         = tcd->DADDR;
+    base->TCD[channel].DOFF          = tcd->DOFF;
     base->TCD[channel].CITER_ELINKNO = tcd->CITER;
-    base->TCD[channel].DLAST_SGA = tcd->DLAST_SGA;
+    base->TCD[channel].DLAST_SGA     = tcd->DLAST_SGA;
     /* Clear DONE bit first, otherwise ESG cannot be set */
-    base->TCD[channel].CSR = 0;
-    base->TCD[channel].CSR = tcd->CSR;
+    base->TCD[channel].CSR           = 0;
+    base->TCD[channel].CSR           = tcd->CSR;
     base->TCD[channel].BITER_ELINKNO = tcd->BITER;
 }
 
+/*!
+ * brief Initializes the eDMA peripheral.
+ *
+ * This function ungates the eDMA clock and configures the eDMA peripheral according
+ * to the configuration structure.
+ *
+ * param base eDMA peripheral base address.
+ * param config A pointer to the configuration structure, see "edma_config_t".
+ * note This function enables the minor loop map feature.
+ */
 void EDMA_Init(DMA_Type *base, const edma_config_t *config)
 {
     assert(config != NULL);
@@ -126,54 +116,129 @@ void EDMA_Init(DMA_Type *base, const edma_config_t *config)
     uint32_t tmpreg;
 
 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
-    /* Ungate EDMA periphral clock */
+    /* Ungate EDMA peripheral clock */
     CLOCK_EnableClock(s_edmaClockName[EDMA_GetInstance(base)]);
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+    /* clear all the enabled request, status to make sure EDMA status is in normal condition */
+    base->ERQ = 0U;
+    base->INT = 0xFFFFFFFFU;
+    base->ERR = 0xFFFFFFFFU;
     /* Configure EDMA peripheral according to the configuration structure. */
     tmpreg = base->CR;
     tmpreg &= ~(DMA_CR_ERCA_MASK | DMA_CR_HOE_MASK | DMA_CR_CLM_MASK | DMA_CR_EDBG_MASK);
     tmpreg |= (DMA_CR_ERCA(config->enableRoundRobinArbitration) | DMA_CR_HOE(config->enableHaltOnError) |
-               DMA_CR_CLM(config->enableContinuousLinkMode) | DMA_CR_EDBG(config->enableDebugMode) | DMA_CR_EMLM(true));
+               DMA_CR_CLM(config->enableContinuousLinkMode) | DMA_CR_EDBG(config->enableDebugMode) | DMA_CR_EMLM(1U));
     base->CR = tmpreg;
 }
 
+/*!
+ * brief Deinitializes the eDMA peripheral.
+ *
+ * This function gates the eDMA clock.
+ *
+ * param base eDMA peripheral base address.
+ */
 void EDMA_Deinit(DMA_Type *base)
 {
 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
-    /* Gate EDMA periphral clock */
+    /* Gate EDMA peripheral clock */
     CLOCK_DisableClock(s_edmaClockName[EDMA_GetInstance(base)]);
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }
 
+/*!
+ * brief Gets the eDMA default configuration structure.
+ *
+ * This function sets the configuration structure to default values.
+ * The default configuration is set to the following values.
+ * code
+ *   config.enableContinuousLinkMode = false;
+ *   config.enableHaltOnError = true;
+ *   config.enableRoundRobinArbitration = false;
+ *   config.enableDebugMode = false;
+ * endcode
+ *
+ * param config A pointer to the eDMA configuration structure.
+ */
 void EDMA_GetDefaultConfig(edma_config_t *config)
 {
     assert(config != NULL);
 
+    /* Initializes the configure structure to zero. */
+    (void)memset(config, 0, sizeof(*config));
+
     config->enableRoundRobinArbitration = false;
-    config->enableHaltOnError = true;
-    config->enableContinuousLinkMode = false;
-    config->enableDebugMode = false;
+    config->enableHaltOnError           = true;
+    config->enableContinuousLinkMode    = false;
+    config->enableDebugMode             = false;
 }
 
+/*!
+ * brief Sets all TCD registers to default values.
+ *
+ * This function sets TCD registers for this channel to default values.
+ *
+ * param base eDMA peripheral base address.
+ * param channel eDMA channel number.
+ * note This function must not be called while the channel transfer is ongoing
+ *       or it causes unpredictable results.
+ * note This function enables the auto stop request feature.
+ */
 void EDMA_ResetChannel(DMA_Type *base, uint32_t channel)
 {
-    assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
+    assert(channel < (uint32_t)FSL_FEATURE_EDMA_MODULE_CHANNEL);
 
-    EDMA_TcdReset((edma_tcd_t *)&base->TCD[channel]);
+    EDMA_TcdReset((edma_tcd_t *)(uint32_t)&base->TCD[channel]);
 }
 
+/*!
+ * brief Configures the eDMA transfer attribute.
+ *
+ * This function configures the transfer attribute, including source address, destination address,
+ * transfer size, address offset, and so on. It also configures the scatter gather feature if the
+ * user supplies the TCD address.
+ * Example:
+ * code
+ *  edma_transfer_t config;
+ *  edma_tcd_t tcd;
+ *  config.srcAddr = ..;
+ *  config.destAddr = ..;
+ *  ...
+ *  EDMA_SetTransferConfig(DMA0, channel, &config, &stcd);
+ * endcode
+ *
+ * param base eDMA peripheral base address.
+ * param channel eDMA channel number.
+ * param config Pointer to eDMA transfer configuration structure.
+ * param nextTcd Point to TCD structure. It can be NULL if users
+ *                do not want to enable scatter/gather feature.
+ * note If nextTcd is not NULL, it means scatter gather feature is enabled
+ *       and DREQ bit is cleared in the previous transfer configuration, which
+ *       is set in the eDMA_ResetChannel.
+ */
 void EDMA_SetTransferConfig(DMA_Type *base, uint32_t channel, const edma_transfer_config_t *config, edma_tcd_t *nextTcd)
 {
-    assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
+    assert(channel < (uint32_t)FSL_FEATURE_EDMA_MODULE_CHANNEL);
     assert(config != NULL);
-    assert(((uint32_t)nextTcd & 0x1FU) == 0);
+    assert(((uint32_t)nextTcd & 0x1FU) == 0U);
 
-    EDMA_TcdSetTransferConfig((edma_tcd_t *)&base->TCD[channel], config, nextTcd);
+    EDMA_TcdSetTransferConfig((edma_tcd_t *)(uint32_t)&base->TCD[channel], config, nextTcd);
 }
 
+/*!
+ * brief Configures the eDMA minor offset feature.
+ *
+ * The minor offset means that the signed-extended value is added to the source address or destination
+ * address after each minor loop.
+ *
+ * param base eDMA peripheral base address.
+ * param channel eDMA channel number.
+ * param config A pointer to the minor offset configuration structure.
+ */
 void EDMA_SetMinorOffsetConfig(DMA_Type *base, uint32_t channel, const edma_minor_offset_config_t *config)
 {
-    assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
+    assert(channel < (uint32_t)FSL_FEATURE_EDMA_MODULE_CHANNEL);
     assert(config != NULL);
 
     uint32_t tmpreg;
@@ -186,103 +251,220 @@ void EDMA_SetMinorOffsetConfig(DMA_Type *base, uint32_t channel, const edma_mino
     base->TCD[channel].NBYTES_MLOFFYES = tmpreg;
 }
 
+/*!
+ * brief Configures the eDMA channel preemption feature.
+ *
+ * This function configures the channel preemption attribute and the priority of the channel.
+ *
+ * param base eDMA peripheral base address.
+ * param channel eDMA channel number
+ * param config A pointer to the channel preemption configuration structure.
+ */
+void EDMA_SetChannelPreemptionConfig(DMA_Type *base, uint32_t channel, const edma_channel_Preemption_config_t *config)
+{
+    assert(channel < (uint32_t)FSL_FEATURE_EDMA_MODULE_CHANNEL);
+    assert(config != NULL);
+
+    bool tmpEnablePreemptAbility    = config->enablePreemptAbility;
+    bool tmpEnableChannelPreemption = config->enableChannelPreemption;
+    uint8_t tmpChannelPriority      = config->channelPriority;
+    volatile uint8_t *tmpReg        = &base->DCHPRI3;
+
+    tmpReg[DMA_DCHPRI_INDEX(channel)] =
+        (DMA_DCHPRI0_DPA((true == tmpEnablePreemptAbility ? 0U : 1U)) |
+         DMA_DCHPRI0_ECP((true == tmpEnableChannelPreemption ? 1U : 0U)) | DMA_DCHPRI0_CHPRI(tmpChannelPriority));
+}
+
+/*!
+ * brief Sets the channel link for the eDMA transfer.
+ *
+ * This function configures either the minor link or the major link mode. The minor link means that the channel link is
+ * triggered every time CITER decreases by 1. The major link means that the channel link is triggered when the CITER is
+ * exhausted.
+ *
+ * param base eDMA peripheral base address.
+ * param channel eDMA channel number.
+ * param type A channel link type, which can be one of the following:
+ *   arg kEDMA_LinkNone
+ *   arg kEDMA_MinorLink
+ *   arg kEDMA_MajorLink
+ * param linkedChannel The linked channel number.
+ * note Users should ensure that DONE flag is cleared before calling this interface, or the configuration is invalid.
+ */
 void EDMA_SetChannelLink(DMA_Type *base, uint32_t channel, edma_channel_link_type_t type, uint32_t linkedChannel)
 {
-    assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
-    assert(linkedChannel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
+    assert(channel < (uint32_t)FSL_FEATURE_EDMA_MODULE_CHANNEL);
+    assert(linkedChannel < (uint32_t)FSL_FEATURE_EDMA_MODULE_CHANNEL);
 
-    EDMA_TcdSetChannelLink((edma_tcd_t *)&base->TCD[channel], type, linkedChannel);
+    EDMA_TcdSetChannelLink((edma_tcd_t *)(uint32_t)&base->TCD[channel], type, linkedChannel);
 }
 
+/*!
+ * brief Sets the bandwidth for the eDMA transfer.
+ *
+ * Because the eDMA processes the minor loop, it continuously generates read/write sequences
+ * until the minor count is exhausted. The bandwidth forces the eDMA to stall after the completion of
+ * each read/write access to control the bus request bandwidth seen by the crossbar switch.
+ *
+ * param base eDMA peripheral base address.
+ * param channel eDMA channel number.
+ * param bandWidth A bandwidth setting, which can be one of the following:
+ *     arg kEDMABandwidthStallNone
+ *     arg kEDMABandwidthStall4Cycle
+ *     arg kEDMABandwidthStall8Cycle
+ */
 void EDMA_SetBandWidth(DMA_Type *base, uint32_t channel, edma_bandwidth_t bandWidth)
 {
-    assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
+    assert(channel < (uint32_t)FSL_FEATURE_EDMA_MODULE_CHANNEL);
 
-    base->TCD[channel].CSR = (base->TCD[channel].CSR & (~DMA_CSR_BWC_MASK)) | DMA_CSR_BWC(bandWidth);
+    base->TCD[channel].CSR = (uint16_t)((base->TCD[channel].CSR & (~DMA_CSR_BWC_MASK)) | DMA_CSR_BWC(bandWidth));
 }
 
+/*!
+ * brief Sets the source modulo and the destination modulo for the eDMA transfer.
+ *
+ * This function defines a specific address range specified to be the value after (SADDR + SOFF)/(DADDR + DOFF)
+ * calculation is performed or the original register value. It provides the ability to implement a circular data
+ * queue easily.
+ *
+ * param base eDMA peripheral base address.
+ * param channel eDMA channel number.
+ * param srcModulo A source modulo value.
+ * param destModulo A destination modulo value.
+ */
 void EDMA_SetModulo(DMA_Type *base, uint32_t channel, edma_modulo_t srcModulo, edma_modulo_t destModulo)
 {
-    assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
+    assert(channel < (uint32_t)FSL_FEATURE_EDMA_MODULE_CHANNEL);
 
-    uint32_t tmpreg;
+    uint16_t tmpreg;
 
-    tmpreg = base->TCD[channel].ATTR & (~(DMA_ATTR_SMOD_MASK | DMA_ATTR_DMOD_MASK));
+    tmpreg                  = base->TCD[channel].ATTR & (~(uint16_t)(DMA_ATTR_SMOD_MASK | DMA_ATTR_DMOD_MASK));
     base->TCD[channel].ATTR = tmpreg | DMA_ATTR_DMOD(destModulo) | DMA_ATTR_SMOD(srcModulo);
 }
 
+/*!
+ * brief Enables the interrupt source for the eDMA transfer.
+ *
+ * param base eDMA peripheral base address.
+ * param channel eDMA channel number.
+ * param mask The mask of interrupt source to be set. Users need to use
+ *             the defined edma_interrupt_enable_t type.
+ */
 void EDMA_EnableChannelInterrupts(DMA_Type *base, uint32_t channel, uint32_t mask)
 {
-    assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
+    assert(channel < (uint32_t)FSL_FEATURE_EDMA_MODULE_CHANNEL);
 
     /* Enable error interrupt */
-    if (mask & kEDMA_ErrorInterruptEnable)
+    if (0U != (mask & (uint32_t)kEDMA_ErrorInterruptEnable))
     {
-        base->EEI |= (0x1U << channel);
+        base->EEI |= ((uint32_t)0x1U << channel);
     }
 
     /* Enable Major interrupt */
-    if (mask & kEDMA_MajorInterruptEnable)
+    if (0U != (mask & (uint32_t)kEDMA_MajorInterruptEnable))
     {
         base->TCD[channel].CSR |= DMA_CSR_INTMAJOR_MASK;
     }
 
     /* Enable Half major interrupt */
-    if (mask & kEDMA_HalfInterruptEnable)
+    if (0U != (mask & (uint32_t)kEDMA_HalfInterruptEnable))
     {
         base->TCD[channel].CSR |= DMA_CSR_INTHALF_MASK;
     }
 }
 
+/*!
+ * brief Disables the interrupt source for the eDMA transfer.
+ *
+ * param base eDMA peripheral base address.
+ * param channel eDMA channel number.
+ * param mask The mask of the interrupt source to be set. Use
+ *             the defined edma_interrupt_enable_t type.
+ */
 void EDMA_DisableChannelInterrupts(DMA_Type *base, uint32_t channel, uint32_t mask)
 {
-    assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
+    assert(channel < (uint32_t)FSL_FEATURE_EDMA_MODULE_CHANNEL);
 
     /* Disable error interrupt */
-    if (mask & kEDMA_ErrorInterruptEnable)
+    if (0U != (mask & (uint32_t)kEDMA_ErrorInterruptEnable))
     {
-        base->EEI &= ~(0x1U << channel);
+        base->EEI &= (uint32_t)(~(0x1U << channel));
     }
 
     /* Disable Major interrupt */
-    if (mask & kEDMA_MajorInterruptEnable)
+    if (0U != (mask & (uint32_t)kEDMA_MajorInterruptEnable))
     {
-        base->TCD[channel].CSR &= ~DMA_CSR_INTMAJOR_MASK;
+        base->TCD[channel].CSR &= ~(uint16_t)DMA_CSR_INTMAJOR_MASK;
     }
 
     /* Disable Half major interrupt */
-    if (mask & kEDMA_HalfInterruptEnable)
+    if (0U != (mask & (uint32_t)kEDMA_HalfInterruptEnable))
     {
-        base->TCD[channel].CSR &= ~DMA_CSR_INTHALF_MASK;
+        base->TCD[channel].CSR &= ~(uint16_t)DMA_CSR_INTHALF_MASK;
     }
 }
 
+/*!
+ * brief Sets all fields to default values for the TCD structure.
+ *
+ * This function sets all fields for this TCD structure to default value.
+ *
+ * param tcd Pointer to the TCD structure.
+ * note This function enables the auto stop request feature.
+ */
 void EDMA_TcdReset(edma_tcd_t *tcd)
 {
     assert(tcd != NULL);
-    assert(((uint32_t)tcd & 0x1FU) == 0);
+    assert(((uint32_t)tcd & 0x1FU) == 0U);
 
     /* Reset channel TCD */
-    tcd->SADDR = 0U;
-    tcd->SOFF = 0U;
-    tcd->ATTR = 0U;
-    tcd->NBYTES = 0U;
-    tcd->SLAST = 0U;
-    tcd->DADDR = 0U;
-    tcd->DOFF = 0U;
-    tcd->CITER = 0U;
+    tcd->SADDR     = 0U;
+    tcd->SOFF      = 0U;
+    tcd->ATTR      = 0U;
+    tcd->NBYTES    = 0U;
+    tcd->SLAST     = 0U;
+    tcd->DADDR     = 0U;
+    tcd->DOFF      = 0U;
+    tcd->CITER     = 0U;
     tcd->DLAST_SGA = 0U;
     /* Enable auto disable request feature */
-    tcd->CSR = DMA_CSR_DREQ(true);
+    tcd->CSR   = DMA_CSR_DREQ(true);
     tcd->BITER = 0U;
 }
 
+/*!
+ * brief Configures the eDMA TCD transfer attribute.
+ *
+ * The TCD is a transfer control descriptor. The content of the TCD is the same as the hardware TCD registers.
+ * The STCD is used in the scatter-gather mode.
+ * This function configures the TCD transfer attribute, including source address, destination address,
+ * transfer size, address offset, and so on. It also configures the scatter gather feature if the
+ * user supplies the next TCD address.
+ * Example:
+ * code
+ *   edma_transfer_t config = {
+ *   ...
+ *   }
+ *   edma_tcd_t tcd __aligned(32);
+ *   edma_tcd_t nextTcd __aligned(32);
+ *   EDMA_TcdSetTransferConfig(&tcd, &config, &nextTcd);
+ * endcode
+ *
+ * param tcd Pointer to the TCD structure.
+ * param config Pointer to eDMA transfer configuration structure.
+ * param nextTcd Pointer to the next TCD structure. It can be NULL if users
+ *                do not want to enable scatter/gather feature.
+ * note TCD address should be 32 bytes aligned or it causes an eDMA error.
+ * note If the nextTcd is not NULL, the scatter gather feature is enabled
+ *       and DREQ bit is cleared in the previous transfer configuration, which
+ *       is set in the EDMA_TcdReset.
+ */
 void EDMA_TcdSetTransferConfig(edma_tcd_t *tcd, const edma_transfer_config_t *config, edma_tcd_t *nextTcd)
 {
     assert(tcd != NULL);
-    assert(((uint32_t)tcd & 0x1FU) == 0);
+    assert(((uint32_t)tcd & 0x1FU) == 0U);
     assert(config != NULL);
-    assert(((uint32_t)nextTcd & 0x1FU) == 0);
+    assert(((uint32_t)nextTcd & 0x1FU) == 0U);
 
     /* source address */
     tcd->SADDR = config->srcAddr;
@@ -291,15 +473,15 @@ void EDMA_TcdSetTransferConfig(edma_tcd_t *tcd, const edma_transfer_config_t *co
     /* Source data and destination data transfer size */
     tcd->ATTR = DMA_ATTR_SSIZE(config->srcTransferSize) | DMA_ATTR_DSIZE(config->destTransferSize);
     /* Source address signed offset */
-    tcd->SOFF = config->srcOffset;
+    tcd->SOFF = (uint16_t)config->srcOffset;
     /* Destination address signed offset */
-    tcd->DOFF = config->destOffset;
+    tcd->DOFF = (uint16_t)config->destOffset;
     /* Minor byte transfer count */
     tcd->NBYTES = config->minorLoopBytes;
     /* Current major iteration count */
-    tcd->CITER = config->majorLoopCounts;
+    tcd->CITER = (uint16_t)config->majorLoopCounts;
     /* Starting major iteration count */
-    tcd->BITER = config->majorLoopCounts;
+    tcd->BITER = (uint16_t)config->majorLoopCounts;
     /* Enable scatter/gather processing */
     if (nextTcd != NULL)
     {
@@ -313,14 +495,23 @@ void EDMA_TcdSetTransferConfig(edma_tcd_t *tcd, const edma_transfer_config_t *co
             previous transfer is not the last transfer, and channel request should
             be enabled at the next transfer(the next TCD).
         */
-        tcd->CSR = (tcd->CSR | DMA_CSR_ESG_MASK) & ~DMA_CSR_DREQ_MASK;
+        tcd->CSR = (tcd->CSR | (uint16_t)DMA_CSR_ESG_MASK) & ~(uint16_t)DMA_CSR_DREQ_MASK;
     }
 }
 
+/*!
+ * brief Configures the eDMA TCD minor offset feature.
+ *
+ * A minor offset is a signed-extended value added to the source address or a destination
+ * address after each minor loop.
+ *
+ * param tcd A point to the TCD structure.
+ * param config A pointer to the minor offset configuration structure.
+ */
 void EDMA_TcdSetMinorOffsetConfig(edma_tcd_t *tcd, const edma_minor_offset_config_t *config)
 {
     assert(tcd != NULL);
-    assert(((uint32_t)tcd & 0x1FU) == 0);
+    assert(((uint32_t)tcd & 0x1FU) == 0U);
 
     uint32_t tmpreg;
 
@@ -332,152 +523,229 @@ void EDMA_TcdSetMinorOffsetConfig(edma_tcd_t *tcd, const edma_minor_offset_confi
     tcd->NBYTES = tmpreg;
 }
 
+/*!
+ * brief Sets the channel link for the eDMA TCD.
+ *
+ * This function configures either a minor link or a major link. The minor link means the channel link is
+ * triggered every time CITER decreases by 1. The major link means that the channel link  is triggered when the CITER is
+ * exhausted.
+ *
+ * note Users should ensure that DONE flag is cleared before calling this interface, or the configuration is invalid.
+ * param tcd Point to the TCD structure.
+ * param type Channel link type, it can be one of:
+ *   arg kEDMA_LinkNone
+ *   arg kEDMA_MinorLink
+ *   arg kEDMA_MajorLink
+ * param linkedChannel The linked channel number.
+ */
 void EDMA_TcdSetChannelLink(edma_tcd_t *tcd, edma_channel_link_type_t type, uint32_t linkedChannel)
 {
     assert(tcd != NULL);
-    assert(((uint32_t)tcd & 0x1FU) == 0);
-    assert(linkedChannel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
+    assert(((uint32_t)tcd & 0x1FU) == 0U);
+    assert(linkedChannel < (uint32_t)FSL_FEATURE_EDMA_MODULE_CHANNEL);
 
     if (type == kEDMA_MinorLink) /* Minor link config */
     {
-        uint32_t tmpreg;
+        uint16_t tmpreg;
 
         /* Enable minor link */
         tcd->CITER |= DMA_CITER_ELINKYES_ELINK_MASK;
         tcd->BITER |= DMA_BITER_ELINKYES_ELINK_MASK;
-        /* Set likned channel */
-        tmpreg = tcd->CITER & (~DMA_CITER_ELINKYES_LINKCH_MASK);
+        /* Set linked channel */
+        tmpreg = tcd->CITER & (~(uint16_t)DMA_CITER_ELINKYES_LINKCH_MASK);
         tmpreg |= DMA_CITER_ELINKYES_LINKCH(linkedChannel);
         tcd->CITER = tmpreg;
-        tmpreg = tcd->BITER & (~DMA_BITER_ELINKYES_LINKCH_MASK);
+        tmpreg     = tcd->BITER & (~(uint16_t)DMA_BITER_ELINKYES_LINKCH_MASK);
         tmpreg |= DMA_BITER_ELINKYES_LINKCH(linkedChannel);
         tcd->BITER = tmpreg;
     }
     else if (type == kEDMA_MajorLink) /* Major link config */
     {
-        uint32_t tmpreg;
+        uint16_t tmpreg;
 
         /* Enable major link */
         tcd->CSR |= DMA_CSR_MAJORELINK_MASK;
         /* Set major linked channel */
-        tmpreg = tcd->CSR & (~DMA_CSR_MAJORLINKCH_MASK);
+        tmpreg   = tcd->CSR & (~(uint16_t)DMA_CSR_MAJORLINKCH_MASK);
         tcd->CSR = tmpreg | DMA_CSR_MAJORLINKCH(linkedChannel);
     }
     else /* Link none */
     {
-        tcd->CITER &= ~DMA_CITER_ELINKYES_ELINK_MASK;
-        tcd->BITER &= ~DMA_BITER_ELINKYES_ELINK_MASK;
-        tcd->CSR &= ~DMA_CSR_MAJORELINK_MASK;
+        tcd->CITER &= ~(uint16_t)DMA_CITER_ELINKYES_ELINK_MASK;
+        tcd->BITER &= ~(uint16_t)DMA_BITER_ELINKYES_ELINK_MASK;
+        tcd->CSR &= ~(uint16_t)DMA_CSR_MAJORELINK_MASK;
     }
 }
 
+/*!
+ * brief Sets the source modulo and the destination modulo for the eDMA TCD.
+ *
+ * This function defines a specific address range specified to be the value after (SADDR + SOFF)/(DADDR + DOFF)
+ * calculation is performed or the original register value. It provides the ability to implement a circular data
+ * queue easily.
+ *
+ * param tcd A pointer to the TCD structure.
+ * param srcModulo A source modulo value.
+ * param destModulo A destination modulo value.
+ */
 void EDMA_TcdSetModulo(edma_tcd_t *tcd, edma_modulo_t srcModulo, edma_modulo_t destModulo)
 {
     assert(tcd != NULL);
-    assert(((uint32_t)tcd & 0x1FU) == 0);
+    assert(((uint32_t)tcd & 0x1FU) == 0U);
 
-    uint32_t tmpreg;
+    uint16_t tmpreg;
 
-    tmpreg = tcd->ATTR & (~(DMA_ATTR_SMOD_MASK | DMA_ATTR_DMOD_MASK));
+    tmpreg    = tcd->ATTR & (~(uint16_t)(DMA_ATTR_SMOD_MASK | DMA_ATTR_DMOD_MASK));
     tcd->ATTR = tmpreg | DMA_ATTR_DMOD(destModulo) | DMA_ATTR_SMOD(srcModulo);
 }
 
+/*!
+ * brief Enables the interrupt source for the eDMA TCD.
+ *
+ * param tcd Point to the TCD structure.
+ * param mask The mask of interrupt source to be set. Users need to use
+ *             the defined edma_interrupt_enable_t type.
+ */
 void EDMA_TcdEnableInterrupts(edma_tcd_t *tcd, uint32_t mask)
 {
     assert(tcd != NULL);
 
     /* Enable Major interrupt */
-    if (mask & kEDMA_MajorInterruptEnable)
+    if (0U != (mask & (uint32_t)kEDMA_MajorInterruptEnable))
     {
         tcd->CSR |= DMA_CSR_INTMAJOR_MASK;
     }
 
     /* Enable Half major interrupt */
-    if (mask & kEDMA_HalfInterruptEnable)
+    if (0U != (mask & (uint32_t)kEDMA_HalfInterruptEnable))
     {
         tcd->CSR |= DMA_CSR_INTHALF_MASK;
     }
 }
 
+/*!
+ * brief Disables the interrupt source for the eDMA TCD.
+ *
+ * param tcd Point to the TCD structure.
+ * param mask The mask of interrupt source to be set. Users need to use
+ *             the defined edma_interrupt_enable_t type.
+ */
 void EDMA_TcdDisableInterrupts(edma_tcd_t *tcd, uint32_t mask)
 {
     assert(tcd != NULL);
 
     /* Disable Major interrupt */
-    if (mask & kEDMA_MajorInterruptEnable)
+    if (0U != (mask & (uint32_t)kEDMA_MajorInterruptEnable))
     {
-        tcd->CSR &= ~DMA_CSR_INTMAJOR_MASK;
+        tcd->CSR &= ~(uint16_t)DMA_CSR_INTMAJOR_MASK;
     }
 
     /* Disable Half major interrupt */
-    if (mask & kEDMA_HalfInterruptEnable)
+    if (0U != (mask & (uint32_t)kEDMA_HalfInterruptEnable))
     {
-        tcd->CSR &= ~DMA_CSR_INTHALF_MASK;
+        tcd->CSR &= ~(uint16_t)DMA_CSR_INTHALF_MASK;
     }
 }
 
+/*!
+ * brief Gets the remaining major loop count from the eDMA current channel TCD.
+ *
+ * This function checks the TCD (Task Control Descriptor) status for a specified
+ * eDMA channel and returns the number of major loop count that has not finished.
+ *
+ * param base eDMA peripheral base address.
+ * param channel eDMA channel number.
+ * return Major loop count which has not been transferred yet for the current TCD.
+ * note 1. This function can only be used to get unfinished major loop count of transfer without
+ *          the next TCD, or it might be inaccuracy.
+ *       2. The unfinished/remaining transfer bytes cannot be obtained directly from registers while
+ *          the channel is running.
+ *          Because to calculate the remaining bytes, the initial NBYTES configured in DMA_TCDn_NBYTES_MLNO
+ *          register is needed while the eDMA IP does not support getting it while a channel is active.
+ *          In another word, the NBYTES value reading is always the actual (decrementing) NBYTES value the dma_engine
+ *          is working with while a channel is running.
+ *          Consequently, to get the remaining transfer bytes, a software-saved initial value of NBYTES (for example
+ *          copied before enabling the channel) is needed. The formula to calculate it is shown below:
+ *          RemainingBytes = RemainingMajorLoopCount * NBYTES(initially configured)
+ */
 uint32_t EDMA_GetRemainingMajorLoopCount(DMA_Type *base, uint32_t channel)
 {
-    assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
+    assert(channel < (uint32_t)FSL_FEATURE_EDMA_MODULE_CHANNEL);
 
     uint32_t remainingCount = 0;
 
-    if (DMA_CSR_DONE_MASK & base->TCD[channel].CSR)
+    if (0U != (DMA_CSR_DONE_MASK & base->TCD[channel].CSR))
     {
         remainingCount = 0;
     }
     else
     {
         /* Calculate the unfinished bytes */
-        if (base->TCD[channel].CITER_ELINKNO & DMA_CITER_ELINKNO_ELINK_MASK)
+        if (0U != (base->TCD[channel].CITER_ELINKNO & DMA_CITER_ELINKNO_ELINK_MASK))
         {
-            remainingCount =
-                (base->TCD[channel].CITER_ELINKYES & DMA_CITER_ELINKYES_CITER_MASK) >> DMA_CITER_ELINKYES_CITER_SHIFT;
+            remainingCount = (((uint32_t)base->TCD[channel].CITER_ELINKYES & DMA_CITER_ELINKYES_CITER_MASK) >>
+                              DMA_CITER_ELINKYES_CITER_SHIFT);
         }
         else
         {
-            remainingCount =
-                (base->TCD[channel].CITER_ELINKNO & DMA_CITER_ELINKNO_CITER_MASK) >> DMA_CITER_ELINKNO_CITER_SHIFT;
+            remainingCount = (((uint32_t)base->TCD[channel].CITER_ELINKNO & DMA_CITER_ELINKNO_CITER_MASK) >>
+                              DMA_CITER_ELINKNO_CITER_SHIFT);
         }
     }
 
     return remainingCount;
 }
 
+/*!
+ * brief Gets the eDMA channel status flags.
+ *
+ * param base eDMA peripheral base address.
+ * param channel eDMA channel number.
+ * return The mask of channel status flags. Users need to use the
+ *         _edma_channel_status_flags type to decode the return variables.
+ */
 uint32_t EDMA_GetChannelStatusFlags(DMA_Type *base, uint32_t channel)
 {
-    assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
+    assert(channel < (uint32_t)FSL_FEATURE_EDMA_MODULE_CHANNEL);
 
     uint32_t retval = 0;
 
     /* Get DONE bit flag */
-    retval |= ((base->TCD[channel].CSR & DMA_CSR_DONE_MASK) >> DMA_CSR_DONE_SHIFT);
+    retval |= (((uint32_t)base->TCD[channel].CSR & DMA_CSR_DONE_MASK) >> DMA_CSR_DONE_SHIFT);
     /* Get ERROR bit flag */
-    retval |= (((base->ERR >> channel) & 0x1U) << 1U);
+    retval |= ((((uint32_t)base->ERR >> channel) & 0x1U) << 1U);
     /* Get INT bit flag */
-    retval |= (((base->INT >> channel) & 0x1U) << 2U);
+    retval |= ((((uint32_t)base->INT >> channel) & 0x1U) << 2U);
 
     return retval;
 }
 
+/*!
+ * brief Clears the eDMA channel status flags.
+ *
+ * param base eDMA peripheral base address.
+ * param channel eDMA channel number.
+ * param mask The mask of channel status to be cleared. Users need to use
+ *             the defined _edma_channel_status_flags type.
+ */
 void EDMA_ClearChannelStatusFlags(DMA_Type *base, uint32_t channel, uint32_t mask)
 {
-    assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
+    assert(channel < (uint32_t)FSL_FEATURE_EDMA_MODULE_CHANNEL);
 
     /* Clear DONE bit flag */
-    if (mask & kEDMA_DoneFlag)
+    if (0U != (mask & (uint32_t)kEDMA_DoneFlag))
     {
-        base->CDNE = channel;
+        base->CDNE = (uint8_t)channel;
     }
     /* Clear ERROR bit flag */
-    if (mask & kEDMA_ErrorFlag)
+    if (0U != (mask & (uint32_t)kEDMA_ErrorFlag))
     {
-        base->CERR = channel;
+        base->CERR = (uint8_t)channel;
     }
     /* Clear INT bit flag */
-    if (mask & kEDMA_InterruptFlag)
+    if (0U != (mask & (uint32_t)kEDMA_InterruptFlag))
     {
-        base->CINT = channel;
+        base->CINT = (uint8_t)channel;
     }
 }
 
@@ -486,7 +754,7 @@ static uint8_t Get_StartInstance(void)
     static uint8_t StartInstanceNum;
 
 #if defined(DMA0)
-    StartInstanceNum = EDMA_GetInstance(DMA0);
+    StartInstanceNum = (uint8_t)EDMA_GetInstance(DMA0);
 #elif defined(DMA1)
     StartInstanceNum = EDMA_GetInstance(DMA1);
 #elif defined(DMA2)
@@ -498,10 +766,21 @@ static uint8_t Get_StartInstance(void)
     return StartInstanceNum;
 }
 
+/*!
+ * brief Creates the eDMA handle.
+ *
+ * This function is called if using the transactional API for eDMA. This function
+ * initializes the internal state of the eDMA handle.
+ *
+ * param handle eDMA handle pointer. The eDMA handle stores callback function and
+ *               parameters.
+ * param base eDMA peripheral base address.
+ * param channel eDMA channel number.
+ */
 void EDMA_CreateHandle(edma_handle_t *handle, DMA_Type *base, uint32_t channel)
 {
     assert(handle != NULL);
-    assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
+    assert(channel < (uint32_t)FSL_FEATURE_EDMA_MODULE_CHANNEL);
 
     uint32_t edmaInstance;
     uint32_t channelIndex;
@@ -509,52 +788,74 @@ void EDMA_CreateHandle(edma_handle_t *handle, DMA_Type *base, uint32_t channel)
     edma_tcd_t *tcdRegs;
 
     /* Zero the handle */
-    memset(handle, 0, sizeof(*handle));
+    (void)memset(handle, 0, sizeof(*handle));
 
-    handle->base = base;
-    handle->channel = channel;
+    handle->base    = base;
+    handle->channel = (uint8_t)channel;
     /* Get the DMA instance number */
-    edmaInstance = EDMA_GetInstance(base);
-    StartInstance = Get_StartInstance();
-    channelIndex = ((edmaInstance - StartInstance) * FSL_FEATURE_EDMA_MODULE_CHANNEL) + channel;
+    edmaInstance               = EDMA_GetInstance(base);
+    StartInstance              = Get_StartInstance();
+    channelIndex               = ((edmaInstance - StartInstance) * (uint32_t)FSL_FEATURE_EDMA_MODULE_CHANNEL) + channel;
     s_EDMAHandle[channelIndex] = handle;
 
     /* Enable NVIC interrupt */
-    EnableIRQ(s_edmaIRQNumber[edmaInstance][channel]);
+    (void)EnableIRQ(s_edmaIRQNumber[edmaInstance][channel]);
 
     /*
        Reset TCD registers to zero. Unlike the EDMA_TcdReset(DREQ will be set),
        CSR will be 0. Because in order to suit EDMA busy check mechanism in
        EDMA_SubmitTransfer, CSR must be set 0.
     */
-    tcdRegs = (edma_tcd_t *)&handle->base->TCD[handle->channel];
-    tcdRegs->SADDR = 0;
-    tcdRegs->SOFF = 0;
-    tcdRegs->ATTR = 0;
-    tcdRegs->NBYTES = 0;
-    tcdRegs->SLAST = 0;
-    tcdRegs->DADDR = 0;
-    tcdRegs->DOFF = 0;
-    tcdRegs->CITER = 0;
+    tcdRegs            = (edma_tcd_t *)(uint32_t)&handle->base->TCD[handle->channel];
+    tcdRegs->SADDR     = 0;
+    tcdRegs->SOFF      = 0;
+    tcdRegs->ATTR      = 0;
+    tcdRegs->NBYTES    = 0;
+    tcdRegs->SLAST     = 0;
+    tcdRegs->DADDR     = 0;
+    tcdRegs->DOFF      = 0;
+    tcdRegs->CITER     = 0;
     tcdRegs->DLAST_SGA = 0;
-    tcdRegs->CSR = 0;
-    tcdRegs->BITER = 0;
+    tcdRegs->CSR       = 0;
+    tcdRegs->BITER     = 0;
 }
 
+/*!
+ * brief Installs the TCDs memory pool into the eDMA handle.
+ *
+ * This function is called after the EDMA_CreateHandle to use scatter/gather feature. This function shall only be used
+ * while users need to use scatter gather mode. Scatter gather mode enables EDMA to load a new transfer control block
+ * (tcd) in hardware, and automatically reconfigure that DMA channel for a new transfer.
+ * Users need to prepare tcd memory and also configure tcds using interface EDMA_SubmitTransfer.
+ *
+ * param handle eDMA handle pointer.
+ * param tcdPool A memory pool to store TCDs. It must be 32 bytes aligned.
+ * param tcdSize The number of TCD slots.
+ */
 void EDMA_InstallTCDMemory(edma_handle_t *handle, edma_tcd_t *tcdPool, uint32_t tcdSize)
 {
     assert(handle != NULL);
-    assert(((uint32_t)tcdPool & 0x1FU) == 0);
+    assert(((uint32_t)tcdPool & 0x1FU) == 0U);
 
-    /* Initialize tcd queue attibute. */
-    handle->header = 0;
-    handle->tail = 0;
+    /* Initialize tcd queue attribute. */
+    handle->header  = 0;
+    handle->tail    = 0;
     handle->tcdUsed = 0;
-    handle->tcdSize = tcdSize;
-    handle->flags = 0;
+    handle->tcdSize = (int8_t)tcdSize;
+    handle->flags   = 0;
     handle->tcdPool = tcdPool;
 }
 
+/*!
+ * brief Installs a callback function for the eDMA transfer.
+ *
+ * This callback is called in the eDMA IRQ handler. Use the callback to do something after
+ * the current major loop transfer completes. This function will be called every time one tcd finished transfer.
+ *
+ * param handle eDMA handle pointer.
+ * param callback eDMA callback function pointer.
+ * param userData A parameter for the callback function.
+ */
 void EDMA_SetCallback(edma_handle_t *handle, edma_callback callback, void *userData)
 {
     assert(handle != NULL);
@@ -563,6 +864,23 @@ void EDMA_SetCallback(edma_handle_t *handle, edma_callback callback, void *userD
     handle->userData = userData;
 }
 
+/*!
+ * brief Prepares the eDMA transfer structure.
+ *
+ * This function prepares the transfer configuration structure according to the user input.
+ *
+ * param config The user configuration structure of type edma_transfer_t.
+ * param srcAddr eDMA transfer source address.
+ * param srcWidth eDMA transfer source address width(bytes).
+ * param destAddr eDMA transfer destination address.
+ * param destWidth eDMA transfer destination address width(bytes).
+ * param bytesEachRequest eDMA transfer bytes per channel request.
+ * param transferBytes eDMA transfer bytes to be transferred.
+ * param type eDMA transfer type.
+ * note The data address and the data width must be consistent. For example, if the SRC
+ *       is 4 bytes, the source address must be 4 bytes aligned, or it results in
+ *       source address error (SAE).
+ */
 void EDMA_PrepareTransfer(edma_transfer_config_t *config,
                           void *srcAddr,
                           uint32_t srcWidth,
@@ -575,13 +893,18 @@ void EDMA_PrepareTransfer(edma_transfer_config_t *config,
     assert(config != NULL);
     assert(srcAddr != NULL);
     assert(destAddr != NULL);
-    assert((srcWidth == 1U) || (srcWidth == 2U) || (srcWidth == 4U) || (srcWidth == 16U) || (srcWidth == 32U));
-    assert((destWidth == 1U) || (destWidth == 2U) || (destWidth == 4U) || (destWidth == 16U) || (destWidth == 32U));
-    assert(transferBytes % bytesEachRequest == 0);
-
-    config->destAddr = (uint32_t)destAddr;
-    config->srcAddr = (uint32_t)srcAddr;
-    config->minorLoopBytes = bytesEachRequest;
+    assert((srcWidth == 1U) || (srcWidth == 2U) || (srcWidth == 4U) || (srcWidth == 8U) || (srcWidth == 16U) ||
+           (srcWidth == 32U));
+    assert((destWidth == 1U) || (destWidth == 2U) || (destWidth == 4U) || (destWidth == 8U) || (destWidth == 16U) ||
+           (destWidth == 32U));
+    assert((transferBytes % bytesEachRequest) == 0U);
+
+    /* Initializes the configure structure to zero. */
+    (void)memset(config, 0, sizeof(*config));
+
+    config->destAddr        = (uint32_t)(uint32_t *)destAddr;
+    config->srcAddr         = (uint32_t)(uint32_t *)srcAddr;
+    config->minorLoopBytes  = bytesEachRequest;
     config->majorLoopCounts = transferBytes / bytesEachRequest;
     switch (srcWidth)
     {
@@ -594,13 +917,22 @@ void EDMA_PrepareTransfer(edma_transfer_config_t *config,
         case 4U:
             config->srcTransferSize = kEDMA_TransferSize4Bytes;
             break;
+#if (defined(FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER) && FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER)
+        case 8U:
+            config->srcTransferSize = kEDMA_TransferSize8Bytes;
+            break;
+#endif
+#if (defined(FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER) && FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER)
         case 16U:
             config->srcTransferSize = kEDMA_TransferSize16Bytes;
             break;
+#endif
         case 32U:
             config->srcTransferSize = kEDMA_TransferSize32Bytes;
             break;
         default:
+            /* All the cases have been listed above, the default clause should not be reached. */
+            assert(false);
             break;
     }
     switch (destWidth)
@@ -614,40 +946,65 @@ void EDMA_PrepareTransfer(edma_transfer_config_t *config,
         case 4U:
             config->destTransferSize = kEDMA_TransferSize4Bytes;
             break;
+#if (defined(FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER) && FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER)
+        case 8U:
+            config->destTransferSize = kEDMA_TransferSize8Bytes;
+            break;
+#endif
+#if (defined(FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER) && FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER)
         case 16U:
             config->destTransferSize = kEDMA_TransferSize16Bytes;
             break;
+#endif
         case 32U:
             config->destTransferSize = kEDMA_TransferSize32Bytes;
             break;
         default:
+            /* All the cases have been listed above, the default clause should not be reached. */
+            assert(false);
             break;
     }
     switch (type)
     {
         case kEDMA_MemoryToMemory:
-            config->destOffset = destWidth;
-            config->srcOffset = srcWidth;
+            config->destOffset = (int16_t)destWidth;
+            config->srcOffset  = (int16_t)srcWidth;
             break;
         case kEDMA_MemoryToPeripheral:
-            config->destOffset = 0U;
-            config->srcOffset = srcWidth;
+            config->destOffset = 0;
+            config->srcOffset  = (int16_t)srcWidth;
             break;
         case kEDMA_PeripheralToMemory:
-            config->destOffset = destWidth;
-            config->srcOffset = 0U;
+            config->destOffset = (int16_t)destWidth;
+            config->srcOffset  = 0;
             break;
         default:
+            /* All the cases have been listed above, the default clause should not be reached. */
+            assert(false);
             break;
     }
 }
 
+/*!
+ * brief Submits the eDMA transfer request.
+ *
+ * This function submits the eDMA transfer request according to the transfer configuration structure.
+ * In scatter gather mode, call this function will add a configured tcd to the circular list of tcd pool.
+ * The tcd pools is setup by call function EDMA_InstallTCDMemory before.
+ *
+ * param handle eDMA handle pointer.
+ * param config Pointer to eDMA transfer configuration structure.
+ * retval kStatus_EDMA_Success It means submit transfer request succeed.
+ * retval kStatus_EDMA_QueueFull It means TCD queue is full. Submit transfer request is not allowed.
+ * retval kStatus_EDMA_Busy It means the given channel is busy, need to submit request later.
+ */
 status_t EDMA_SubmitTransfer(edma_handle_t *handle, const edma_transfer_config_t *config)
 {
     assert(handle != NULL);
     assert(config != NULL);
+    uint32_t tmpCSR = 0;
 
-    edma_tcd_t *tcdRegs = (edma_tcd_t *)&handle->base->TCD[handle->channel];
+    edma_tcd_t *tcdRegs = (edma_tcd_t *)(uint32_t)&handle->base->TCD[handle->channel];
 
     if (handle->tcdPool == NULL)
     {
@@ -656,7 +1013,8 @@ status_t EDMA_SubmitTransfer(edma_handle_t *handle, const edma_transfer_config_t
             if it is the last transfer, DREQ will be set. If not, ESG will be set. So in order to suit
             this check mechanism, EDMA_CreatHandle will clear CSR register.
         */
-        if ((tcdRegs->CSR != 0) && ((tcdRegs->CSR & DMA_CSR_DONE_MASK) == 0))
+        tmpCSR = tcdRegs->CSR;
+        if ((tmpCSR != 0U) && ((tmpCSR & DMA_CSR_DONE_MASK) == 0U))
         {
             return kStatus_EDMA_Busy;
         }
@@ -674,14 +1032,18 @@ status_t EDMA_SubmitTransfer(edma_handle_t *handle, const edma_transfer_config_t
     else /* Use the TCD queue. */
     {
         uint32_t primask;
-        uint32_t csr;
+        uint16_t csr;
         int8_t currentTcd;
         int8_t previousTcd;
         int8_t nextTcd;
+        int8_t tmpTcdUsed;
+        int8_t tmpTcdSize;
 
         /* Check if tcd pool is full. */
-        primask = DisableGlobalIRQ();
-        if (handle->tcdUsed >= handle->tcdSize)
+        primask    = DisableGlobalIRQ();
+        tmpTcdUsed = handle->tcdUsed;
+        tmpTcdSize = handle->tcdSize;
+        if (tmpTcdUsed >= tmpTcdSize)
         {
             EnableGlobalIRQ(primask);
 
@@ -690,16 +1052,16 @@ status_t EDMA_SubmitTransfer(edma_handle_t *handle, const edma_transfer_config_t
         currentTcd = handle->tail;
         handle->tcdUsed++;
         /* Calculate index of next TCD */
-        nextTcd = currentTcd + 1U;
+        nextTcd = currentTcd + 1;
         if (nextTcd == handle->tcdSize)
         {
-            nextTcd = 0U;
+            nextTcd = 0;
         }
         /* Advance queue tail index */
         handle->tail = nextTcd;
         EnableGlobalIRQ(primask);
         /* Calculate index of previous TCD */
-        previousTcd = currentTcd ? currentTcd - 1U : handle->tcdSize - 1U;
+        previousTcd = currentTcd != 0 ? currentTcd - 1 : (handle->tcdSize - 1);
         /* Configure current TCD block. */
         EDMA_TcdReset(&handle->tcdPool[currentTcd]);
         EDMA_TcdSetTransferConfig(&handle->tcdPool[currentTcd], config, NULL);
@@ -711,10 +1073,10 @@ status_t EDMA_SubmitTransfer(edma_handle_t *handle, const edma_transfer_config_t
         if (currentTcd != previousTcd)
         {
             /* Enable scatter/gather feature in the previous TCD block. */
-            csr = (handle->tcdPool[previousTcd].CSR | DMA_CSR_ESG_MASK) & ~DMA_CSR_DREQ_MASK;
+            csr = (uint16_t)((handle->tcdPool[previousTcd].CSR | DMA_CSR_ESG_MASK) & ~DMA_CSR_DREQ_MASK);
             handle->tcdPool[previousTcd].CSR = csr;
             /*
-                Check if the TCD blcok in the registers is the previous one (points to current TCD block). It
+                Check if the TCD block in the registers is the previous one (points to current TCD block). It
                 is used to check if the previous TCD linked has been loaded in TCD register. If so, it need to
                 link the TCD register in case link the current TCD with the dead chain when TCD loading occurs
                 before link the previous TCD block.
@@ -734,12 +1096,12 @@ status_t EDMA_SubmitTransfer(edma_handle_t *handle, const edma_transfer_config_t
                     and the DLAST_SGA is not the next TCD address(it means the dynamic TCD link succeed and
                     the current TCD block has been loaded into TCD registers), it means transfer finished
                     and TCD link operation fail, so must install TCD content into TCD registers and enable
-                    transfer again. And if ESG is set, it means transfer has notfinished, so TCD dynamic
+                    transfer again. And if ESG is set, it means transfer has not finished, so TCD dynamic
                     link succeed.
                 */
-                if (tcdRegs->CSR & DMA_CSR_ESG_MASK)
+                if (0U != (tcdRegs->CSR & DMA_CSR_ESG_MASK))
                 {
-                    tcdRegs->CSR &= ~DMA_CSR_DREQ_MASK;
+                    tcdRegs->CSR &= ~(uint16_t)DMA_CSR_DREQ_MASK;
                     return kStatus_Success;
                 }
                 /*
@@ -756,7 +1118,7 @@ status_t EDMA_SubmitTransfer(edma_handle_t *handle, const edma_transfer_config_t
                     So shall configure TCD registers.
                 */
             }
-            else if (tcdRegs->DLAST_SGA != 0)
+            else if (tcdRegs->DLAST_SGA != 0U)
             {
                 /* The current TCD block has been linked successfully. */
                 return kStatus_Success;
@@ -772,7 +1134,7 @@ status_t EDMA_SubmitTransfer(edma_handle_t *handle, const edma_transfer_config_t
         /* There is no live chain, TCD block need to be installed in TCD registers. */
         EDMA_InstallTCD(handle->base, handle->channel, &handle->tcdPool[currentTcd]);
         /* Enable channel request again. */
-        if (handle->flags & EDMA_TRANSFER_ENABLED_MASK)
+        if (0U != (handle->flags & EDMA_TRANSFER_ENABLED_MASK))
         {
             handle->base->SERQ = DMA_SERQ_SERQ(handle->channel);
         }
@@ -781,9 +1143,18 @@ status_t EDMA_SubmitTransfer(edma_handle_t *handle, const edma_transfer_config_t
     }
 }
 
+/*!
+ * brief eDMA starts transfer.
+ *
+ * This function enables the channel request. Users can call this function after submitting the transfer request
+ * or before submitting the transfer request.
+ *
+ * param handle eDMA handle pointer.
+ */
 void EDMA_StartTransfer(edma_handle_t *handle)
 {
     assert(handle != NULL);
+    uint32_t tmpCSR = 0;
 
     if (handle->tcdPool == NULL)
     {
@@ -792,7 +1163,7 @@ void EDMA_StartTransfer(edma_handle_t *handle)
     else /* Use the TCD queue. */
     {
         uint32_t primask;
-        edma_tcd_t *tcdRegs = (edma_tcd_t *)&handle->base->TCD[handle->channel];
+        edma_tcd_t *tcdRegs = (edma_tcd_t *)(uint32_t)&handle->base->TCD[handle->channel];
 
         handle->flags |= EDMA_TRANSFER_ENABLED_MASK;
 
@@ -801,10 +1172,11 @@ void EDMA_StartTransfer(edma_handle_t *handle)
         {
             primask = DisableGlobalIRQ();
             /* Check if channel request is actually disable. */
-            if ((handle->base->ERQ & (1U << handle->channel)) == 0U)
+            if ((handle->base->ERQ & ((uint32_t)1U << handle->channel)) == 0U)
             {
                 /* Check if transfer is paused. */
-                if ((!(tcdRegs->CSR & DMA_CSR_DONE_MASK)) || (tcdRegs->CSR & DMA_CSR_ESG_MASK))
+                tmpCSR = tcdRegs->CSR;
+                if ((0U == (tmpCSR & DMA_CSR_DONE_MASK)) || (0U != (tmpCSR & DMA_CSR_ESG_MASK)))
                 {
                     /*
                         Re-enable channel request must be as soon as possible, so must put it into
@@ -818,14 +1190,30 @@ void EDMA_StartTransfer(edma_handle_t *handle)
     }
 }
 
+/*!
+ * brief eDMA stops transfer.
+ *
+ * This function disables the channel request to pause the transfer. Users can call EDMA_StartTransfer()
+ * again to resume the transfer.
+ *
+ * param handle eDMA handle pointer.
+ */
 void EDMA_StopTransfer(edma_handle_t *handle)
 {
     assert(handle != NULL);
 
-    handle->flags &= (~EDMA_TRANSFER_ENABLED_MASK);
+    handle->flags &= (~(uint8_t)EDMA_TRANSFER_ENABLED_MASK);
     handle->base->CERQ = DMA_CERQ_CERQ(handle->channel);
 }
 
+/*!
+ * brief eDMA aborts transfer.
+ *
+ * This function disables the channel request and clear transfer status bits.
+ * Users can submit another transfer after calling this API.
+ *
+ * param handle DMA handle pointer.
+ */
 void EDMA_AbortTransfer(edma_handle_t *handle)
 {
     handle->base->CERQ = DMA_CERQ_CERQ(handle->channel);
@@ -841,21 +1229,57 @@ void EDMA_AbortTransfer(edma_handle_t *handle)
     /* Handle the tcd */
     if (handle->tcdPool != NULL)
     {
-        handle->header = 0;
-        handle->tail = 0;
+        handle->header  = 0;
+        handle->tail    = 0;
         handle->tcdUsed = 0;
     }
 }
 
+/*!
+ * brief eDMA IRQ handler for the current major loop transfer completion.
+ *
+ * This function clears the channel major interrupt flag and calls
+ * the callback function if it is not NULL.
+ *
+ * Note:
+ * For the case using TCD queue, when the major iteration count is exhausted, additional operations are performed.
+ * These include the final address adjustments and reloading of the BITER field into the CITER.
+ * Assertion of an optional interrupt request also occurs at this time, as does a possible fetch of a new TCD from
+ * memory using the scatter/gather address pointer included in the descriptor (if scatter/gather is enabled).
+ *
+ * For instance, when the time interrupt of TCD[0] happens, the TCD[1] has already been loaded into the eDMA engine.
+ * As sga and sga_index are calculated based on the DLAST_SGA bitfield lies in the TCD_CSR register, the sga_index
+ * in this case should be 2 (DLAST_SGA of TCD[1] stores the address of TCD[2]). Thus, the "tcdUsed" updated should be
+ * (tcdUsed - 2U) which indicates the number of TCDs can be loaded in the memory pool (because TCD[0] and TCD[1] have
+ * been loaded into the eDMA engine at this point already.).
+ *
+ * For the last two continuous ISRs in a scatter/gather process, they  both load the last TCD (The last ISR does not
+ * load a new TCD) from the memory pool to the eDMA engine when major loop completes.
+ * Therefore, ensure that the header and tcdUsed updated are identical for them.
+ * tcdUsed are both 0 in this case as no TCD to be loaded.
+ *
+ * See the "eDMA basic data flow" in the eDMA Functional description section of the Reference Manual for
+ * further details.
+ *
+ * param handle eDMA handle pointer.
+ */
 void EDMA_HandleIRQ(edma_handle_t *handle)
 {
     assert(handle != NULL);
 
+    bool transfer_done;
+
     /* Clear EDMA interrupt flag */
     handle->base->CINT = handle->channel;
-    if ((handle->tcdPool == NULL) && (handle->callback != NULL))
+    /* Check if transfer is already finished. */
+    transfer_done = ((handle->base->TCD[handle->channel].CSR & DMA_CSR_DONE_MASK) != 0U);
+
+    if (handle->tcdPool == NULL)
     {
-        (handle->callback)(handle, handle->userData, true, 0);
+        if (handle->callback != NULL)
+        {
+            (handle->callback)(handle, handle->userData, transfer_done, 0);
+        }
     }
     else /* Use the TCD queue. Please refer to the API descriptions in the eDMA header file for detailed information. */
     {
@@ -863,29 +1287,29 @@ void EDMA_HandleIRQ(edma_handle_t *handle)
         uint32_t sga_index;
         int32_t tcds_done;
         uint8_t new_header;
-        bool transfer_done;
 
-        /* Check if transfer is already finished. */
-        transfer_done = ((handle->base->TCD[handle->channel].CSR & DMA_CSR_DONE_MASK) != 0);
-        /* Get the offset of the next transfer TCD blcoks to be loaded into the eDMA engine. */
+        /* Get the offset of the next transfer TCD blocks to be loaded into the eDMA engine. */
         sga -= (uint32_t)handle->tcdPool;
-        /* Get the index of the next transfer TCD blcoks to be loaded into the eDMA engine. */
+        /* Get the index of the next transfer TCD blocks to be loaded into the eDMA engine. */
         sga_index = sga / sizeof(edma_tcd_t);
         /* Adjust header positions. */
         if (transfer_done)
         {
             /* New header shall point to the next TCD to be loaded (current one is already finished) */
-            new_header = sga_index;
+            new_header = (uint8_t)sga_index;
         }
         else
         {
             /* New header shall point to this descriptor currently loaded (not finished yet) */
-            new_header = sga_index ? sga_index - 1U : handle->tcdSize - 1U;
+            new_header = sga_index != 0U ? (uint8_t)sga_index - 1U : (uint8_t)handle->tcdSize - 1U;
         }
         /* Calculate the number of finished TCDs */
-        if (new_header == handle->header)
+        if (new_header == (uint8_t)handle->header)
         {
-            if (handle->tcdUsed == handle->tcdSize)
+            int8_t tmpTcdUsed = handle->tcdUsed;
+            int8_t tmpTcdSize = handle->tcdSize;
+
+            if (tmpTcdUsed == tmpTcdSize)
             {
                 tcds_done = handle->tcdUsed;
             }
@@ -897,26 +1321,41 @@ void EDMA_HandleIRQ(edma_handle_t *handle)
         }
         else
         {
-            tcds_done = new_header - handle->header;
+            tcds_done = (uint32_t)new_header - (uint32_t)handle->header;
             if (tcds_done < 0)
             {
                 tcds_done += handle->tcdSize;
             }
         }
         /* Advance header which points to the TCD to be loaded into the eDMA engine from memory. */
-        handle->header = new_header;
+        handle->header = (int8_t)new_header;
         /* Release TCD blocks. tcdUsed is the TCD number which can be used/loaded in the memory pool. */
-        handle->tcdUsed -= tcds_done;
+        handle->tcdUsed -= (int8_t)tcds_done;
         /* Invoke callback function. */
-        if (handle->callback)
+        if (NULL != handle->callback)
         {
             (handle->callback)(handle, handle->userData, transfer_done, tcds_done);
         }
+
+        /* clear the DONE bit here is meaningful for below cases:
+         *1.A new TCD has been loaded to EDMA already:
+         * need to clear the DONE bit in the IRQ handler to avoid TCD in EDMA been overwritten
+         * if peripheral request isn't coming before next transfer request.
+         *2.A new TCD has not been loaded to EDMA:
+         * for the case that transfer request occur in the privious edma callback, this is a case that doesn't
+         * need scatter gather, so keep DONE bit during the next transfer request will re-install the TCD.
+         */
+        if (transfer_done)
+        {
+            handle->base->CDNE = handle->channel;
+        }
     }
 }
 
+#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SHARED_OFFSET) && \
+    (FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SHARED_OFFSET == 4)
 /* 8 channels (Shared): kl28 */
-#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL == 8U
+#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && (FSL_FEATURE_EDMA_MODULE_CHANNEL == 8U)
 
 #if defined(DMA0)
 void DMA0_04_DriverIRQHandler(void)
@@ -929,8 +1368,8 @@ void DMA0_04_DriverIRQHandler(void)
     {
         EDMA_HandleIRQ(s_EDMAHandle[4]);
     }
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-      exception return operation might vector to incorrect interrupt */
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
 #endif
@@ -946,8 +1385,8 @@ void DMA0_15_DriverIRQHandler(void)
     {
         EDMA_HandleIRQ(s_EDMAHandle[5]);
     }
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-      exception return operation might vector to incorrect interrupt */
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
 #endif
@@ -963,8 +1402,8 @@ void DMA0_26_DriverIRQHandler(void)
     {
         EDMA_HandleIRQ(s_EDMAHandle[6]);
     }
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-      exception return operation might vector to incorrect interrupt */
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
 #endif
@@ -980,8 +1419,8 @@ void DMA0_37_DriverIRQHandler(void)
     {
         EDMA_HandleIRQ(s_EDMAHandle[7]);
     }
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-      exception return operation might vector to incorrect interrupt */
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
 #endif
@@ -1001,8 +1440,8 @@ void DMA1_04_DriverIRQHandler(void)
     {
         EDMA_HandleIRQ(s_EDMAHandle[12]);
     }
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-      exception return operation might vector to incorrect interrupt */
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
 #endif
@@ -1018,8 +1457,8 @@ void DMA1_15_DriverIRQHandler(void)
     {
         EDMA_HandleIRQ(s_EDMAHandle[13]);
     }
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-      exception return operation might vector to incorrect interrupt */
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
 #endif
@@ -1035,8 +1474,8 @@ void DMA1_26_DriverIRQHandler(void)
     {
         EDMA_HandleIRQ(s_EDMAHandle[14]);
     }
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-      exception return operation might vector to incorrect interrupt */
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
 #endif
@@ -1052,8 +1491,8 @@ void DMA1_37_DriverIRQHandler(void)
     {
         EDMA_HandleIRQ(s_EDMAHandle[15]);
     }
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-      exception return operation might vector to incorrect interrupt */
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
 #endif
@@ -1070,8 +1509,8 @@ void DMA1_04_DriverIRQHandler(void)
     {
         EDMA_HandleIRQ(s_EDMAHandle[4]);
     }
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-      exception return operation might vector to incorrect interrupt */
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
 #endif
@@ -1087,8 +1526,8 @@ void DMA1_15_DriverIRQHandler(void)
     {
         EDMA_HandleIRQ(s_EDMAHandle[5]);
     }
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-      exception return operation might vector to incorrect interrupt */
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
 #endif
@@ -1104,8 +1543,8 @@ void DMA1_26_DriverIRQHandler(void)
     {
         EDMA_HandleIRQ(s_EDMAHandle[6]);
     }
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-      exception return operation might vector to incorrect interrupt */
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
 #endif
@@ -1121,8 +1560,8 @@ void DMA1_37_DriverIRQHandler(void)
     {
         EDMA_HandleIRQ(s_EDMAHandle[7]);
     }
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-      exception return operation might vector to incorrect interrupt */
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
 #endif
@@ -1130,9 +1569,12 @@ void DMA1_37_DriverIRQHandler(void)
 #endif
 #endif
 #endif /* 8 channels (Shared) */
+#endif /* FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SHARED_OFFSET */
 
+#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SHARED_OFFSET) && \
+    (FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SHARED_OFFSET == 8)
 /* 16 channels (Shared): K32H844P */
-#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL == 16U
+#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && (FSL_FEATURE_EDMA_MODULE_CHANNEL == 16U)
 
 void DMA0_08_DriverIRQHandler(void)
 {
@@ -1144,8 +1586,8 @@ void DMA0_08_DriverIRQHandler(void)
     {
         EDMA_HandleIRQ(s_EDMAHandle[8]);
     }
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-      exception return operation might vector to incorrect interrupt */
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
 #endif
@@ -1161,8 +1603,8 @@ void DMA0_19_DriverIRQHandler(void)
     {
         EDMA_HandleIRQ(s_EDMAHandle[9]);
     }
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-      exception return operation might vector to incorrect interrupt */
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
 #endif
@@ -1178,8 +1620,8 @@ void DMA0_210_DriverIRQHandler(void)
     {
         EDMA_HandleIRQ(s_EDMAHandle[10]);
     }
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-      exception return operation might vector to incorrect interrupt */
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
 #endif
@@ -1195,8 +1637,8 @@ void DMA0_311_DriverIRQHandler(void)
     {
         EDMA_HandleIRQ(s_EDMAHandle[11]);
     }
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-      exception return operation might vector to incorrect interrupt */
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
 #endif
@@ -1212,8 +1654,8 @@ void DMA0_412_DriverIRQHandler(void)
     {
         EDMA_HandleIRQ(s_EDMAHandle[12]);
     }
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-      exception return operation might vector to incorrect interrupt */
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
 #endif
@@ -1229,8 +1671,8 @@ void DMA0_513_DriverIRQHandler(void)
     {
         EDMA_HandleIRQ(s_EDMAHandle[13]);
     }
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-      exception return operation might vector to incorrect interrupt */
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
 #endif
@@ -1246,8 +1688,8 @@ void DMA0_614_DriverIRQHandler(void)
     {
         EDMA_HandleIRQ(s_EDMAHandle[14]);
     }
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-      exception return operation might vector to incorrect interrupt */
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
 #endif
@@ -1263,8 +1705,8 @@ void DMA0_715_DriverIRQHandler(void)
     {
         EDMA_HandleIRQ(s_EDMAHandle[15]);
     }
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-      exception return operation might vector to incorrect interrupt */
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
 #endif
@@ -1281,8 +1723,8 @@ void DMA1_08_DriverIRQHandler(void)
     {
         EDMA_HandleIRQ(s_EDMAHandle[24]);
     }
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-      exception return operation might vector to incorrect interrupt */
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
 #endif
@@ -1298,8 +1740,8 @@ void DMA1_19_DriverIRQHandler(void)
     {
         EDMA_HandleIRQ(s_EDMAHandle[25]);
     }
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-      exception return operation might vector to incorrect interrupt */
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
 #endif
@@ -1315,8 +1757,8 @@ void DMA1_210_DriverIRQHandler(void)
     {
         EDMA_HandleIRQ(s_EDMAHandle[26]);
     }
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-      exception return operation might vector to incorrect interrupt */
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
 #endif
@@ -1332,8 +1774,8 @@ void DMA1_311_DriverIRQHandler(void)
     {
         EDMA_HandleIRQ(s_EDMAHandle[27]);
     }
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-      exception return operation might vector to incorrect interrupt */
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
 #endif
@@ -1349,8 +1791,8 @@ void DMA1_412_DriverIRQHandler(void)
     {
         EDMA_HandleIRQ(s_EDMAHandle[28]);
     }
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-      exception return operation might vector to incorrect interrupt */
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
 #endif
@@ -1366,8 +1808,8 @@ void DMA1_513_DriverIRQHandler(void)
     {
         EDMA_HandleIRQ(s_EDMAHandle[29]);
     }
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-      exception return operation might vector to incorrect interrupt */
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
 #endif
@@ -1383,8 +1825,8 @@ void DMA1_614_DriverIRQHandler(void)
     {
         EDMA_HandleIRQ(s_EDMAHandle[30]);
     }
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-      exception return operation might vector to incorrect interrupt */
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
 #endif
@@ -1400,15 +1842,18 @@ void DMA1_715_DriverIRQHandler(void)
     {
         EDMA_HandleIRQ(s_EDMAHandle[31]);
     }
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-      exception return operation might vector to incorrect interrupt */
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
 #endif
 }
 #endif
 #endif /* 16 channels (Shared) */
+#endif /* FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SHARED_OFFSET */
 
+#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SHARED_OFFSET) && \
+    (FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SHARED_OFFSET == 16)
 /* 32 channels (Shared): k80 */
 #if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL == 32U
 
@@ -1422,8 +1867,8 @@ void DMA0_DMA16_DriverIRQHandler(void)
     {
         EDMA_HandleIRQ(s_EDMAHandle[16]);
     }
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-      exception return operation might vector to incorrect interrupt */
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
 #endif
@@ -1439,8 +1884,8 @@ void DMA1_DMA17_DriverIRQHandler(void)
     {
         EDMA_HandleIRQ(s_EDMAHandle[17]);
     }
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-      exception return operation might vector to incorrect interrupt */
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
 #endif
@@ -1456,8 +1901,8 @@ void DMA2_DMA18_DriverIRQHandler(void)
     {
         EDMA_HandleIRQ(s_EDMAHandle[18]);
     }
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-      exception return operation might vector to incorrect interrupt */
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
 #endif
@@ -1473,8 +1918,8 @@ void DMA3_DMA19_DriverIRQHandler(void)
     {
         EDMA_HandleIRQ(s_EDMAHandle[19]);
     }
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-      exception return operation might vector to incorrect interrupt */
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
 #endif
@@ -1490,8 +1935,8 @@ void DMA4_DMA20_DriverIRQHandler(void)
     {
         EDMA_HandleIRQ(s_EDMAHandle[20]);
     }
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-      exception return operation might vector to incorrect interrupt */
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
 #endif
@@ -1507,8 +1952,8 @@ void DMA5_DMA21_DriverIRQHandler(void)
     {
         EDMA_HandleIRQ(s_EDMAHandle[21]);
     }
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-      exception return operation might vector to incorrect interrupt */
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
 #endif
@@ -1524,8 +1969,8 @@ void DMA6_DMA22_DriverIRQHandler(void)
     {
         EDMA_HandleIRQ(s_EDMAHandle[22]);
     }
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-      exception return operation might vector to incorrect interrupt */
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
 #endif
@@ -1541,8 +1986,8 @@ void DMA7_DMA23_DriverIRQHandler(void)
     {
         EDMA_HandleIRQ(s_EDMAHandle[23]);
     }
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-      exception return operation might vector to incorrect interrupt */
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
 #endif
@@ -1558,8 +2003,8 @@ void DMA8_DMA24_DriverIRQHandler(void)
     {
         EDMA_HandleIRQ(s_EDMAHandle[24]);
     }
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-      exception return operation might vector to incorrect interrupt */
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
 #endif
@@ -1575,8 +2020,8 @@ void DMA9_DMA25_DriverIRQHandler(void)
     {
         EDMA_HandleIRQ(s_EDMAHandle[25]);
     }
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-      exception return operation might vector to incorrect interrupt */
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
 #endif
@@ -1592,8 +2037,8 @@ void DMA10_DMA26_DriverIRQHandler(void)
     {
         EDMA_HandleIRQ(s_EDMAHandle[26]);
     }
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-      exception return operation might vector to incorrect interrupt */
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
 #endif
@@ -1609,8 +2054,8 @@ void DMA11_DMA27_DriverIRQHandler(void)
     {
         EDMA_HandleIRQ(s_EDMAHandle[27]);
     }
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-      exception return operation might vector to incorrect interrupt */
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
 #endif
@@ -1626,8 +2071,8 @@ void DMA12_DMA28_DriverIRQHandler(void)
     {
         EDMA_HandleIRQ(s_EDMAHandle[28]);
     }
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-      exception return operation might vector to incorrect interrupt */
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
 #endif
@@ -1643,8 +2088,8 @@ void DMA13_DMA29_DriverIRQHandler(void)
     {
         EDMA_HandleIRQ(s_EDMAHandle[29]);
     }
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-      exception return operation might vector to incorrect interrupt */
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
 #endif
@@ -1660,8 +2105,8 @@ void DMA14_DMA30_DriverIRQHandler(void)
     {
         EDMA_HandleIRQ(s_EDMAHandle[30]);
     }
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-      exception return operation might vector to incorrect interrupt */
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
 #endif
@@ -1677,16 +2122,19 @@ void DMA15_DMA31_DriverIRQHandler(void)
     {
         EDMA_HandleIRQ(s_EDMAHandle[31]);
     }
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-      exception return operation might vector to incorrect interrupt */
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
 #endif
 }
 #endif /* 32 channels (Shared) */
+#endif /* FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SHARED_OFFSET */
 
+#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SHARED_OFFSET) && \
+    (FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SHARED_OFFSET == 4)
 /* 32 channels (Shared): MCIMX7U5_M4 */
-#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL == 32U
+#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && (FSL_FEATURE_EDMA_MODULE_CHANNEL == 32U)
 
 void DMA0_0_4_DriverIRQHandler(void)
 {
@@ -1698,8 +2146,8 @@ void DMA0_0_4_DriverIRQHandler(void)
     {
         EDMA_HandleIRQ(s_EDMAHandle[4]);
     }
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-      exception return operation might vector to incorrect interrupt */
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
 #endif
@@ -1715,8 +2163,8 @@ void DMA0_1_5_DriverIRQHandler(void)
     {
         EDMA_HandleIRQ(s_EDMAHandle[5]);
     }
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-      exception return operation might vector to incorrect interrupt */
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
 #endif
@@ -1732,8 +2180,8 @@ void DMA0_2_6_DriverIRQHandler(void)
     {
         EDMA_HandleIRQ(s_EDMAHandle[6]);
     }
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-      exception return operation might vector to incorrect interrupt */
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
 #endif
@@ -1749,8 +2197,8 @@ void DMA0_3_7_DriverIRQHandler(void)
     {
         EDMA_HandleIRQ(s_EDMAHandle[7]);
     }
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-      exception return operation might vector to incorrect interrupt */
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
 #endif
@@ -1766,8 +2214,8 @@ void DMA0_8_12_DriverIRQHandler(void)
     {
         EDMA_HandleIRQ(s_EDMAHandle[12]);
     }
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-      exception return operation might vector to incorrect interrupt */
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
 #endif
@@ -1783,8 +2231,8 @@ void DMA0_9_13_DriverIRQHandler(void)
     {
         EDMA_HandleIRQ(s_EDMAHandle[13]);
     }
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-      exception return operation might vector to incorrect interrupt */
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
 #endif
@@ -1800,8 +2248,8 @@ void DMA0_10_14_DriverIRQHandler(void)
     {
         EDMA_HandleIRQ(s_EDMAHandle[14]);
     }
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-      exception return operation might vector to incorrect interrupt */
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
 #endif
@@ -1817,8 +2265,8 @@ void DMA0_11_15_DriverIRQHandler(void)
     {
         EDMA_HandleIRQ(s_EDMAHandle[15]);
     }
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-      exception return operation might vector to incorrect interrupt */
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
 #endif
@@ -1834,8 +2282,8 @@ void DMA0_16_20_DriverIRQHandler(void)
     {
         EDMA_HandleIRQ(s_EDMAHandle[20]);
     }
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-      exception return operation might vector to incorrect interrupt */
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
 #endif
@@ -1851,8 +2299,8 @@ void DMA0_17_21_DriverIRQHandler(void)
     {
         EDMA_HandleIRQ(s_EDMAHandle[21]);
     }
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-      exception return operation might vector to incorrect interrupt */
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
 #endif
@@ -1868,8 +2316,8 @@ void DMA0_18_22_DriverIRQHandler(void)
     {
         EDMA_HandleIRQ(s_EDMAHandle[22]);
     }
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-      exception return operation might vector to incorrect interrupt */
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
 #endif
@@ -1885,8 +2333,8 @@ void DMA0_19_23_DriverIRQHandler(void)
     {
         EDMA_HandleIRQ(s_EDMAHandle[23]);
     }
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-      exception return operation might vector to incorrect interrupt */
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
 #endif
@@ -1902,8 +2350,8 @@ void DMA0_24_28_DriverIRQHandler(void)
     {
         EDMA_HandleIRQ(s_EDMAHandle[28]);
     }
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-      exception return operation might vector to incorrect interrupt */
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
 #endif
@@ -1919,8 +2367,8 @@ void DMA0_25_29_DriverIRQHandler(void)
     {
         EDMA_HandleIRQ(s_EDMAHandle[29]);
     }
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-      exception return operation might vector to incorrect interrupt */
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
 #endif
@@ -1936,8 +2384,8 @@ void DMA0_26_30_DriverIRQHandler(void)
     {
         EDMA_HandleIRQ(s_EDMAHandle[30]);
     }
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-      exception return operation might vector to incorrect interrupt */
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
 #endif
@@ -1953,22 +2401,25 @@ void DMA0_27_31_DriverIRQHandler(void)
     {
         EDMA_HandleIRQ(s_EDMAHandle[31]);
     }
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-      exception return operation might vector to incorrect interrupt */
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
 #endif
 }
 #endif /* 32 channels (Shared): MCIMX7U5 */
+#endif /* FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SHARED_OFFSET */
 
+#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SHARED_OFFSET) && \
+    (FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SHARED_OFFSET == 0)
 /* 4 channels (No Shared): kv10  */
-#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL > 0
+#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && (FSL_FEATURE_EDMA_MODULE_CHANNEL > 0)
 
 void DMA0_DriverIRQHandler(void)
 {
     EDMA_HandleIRQ(s_EDMAHandle[0]);
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-      exception return operation might vector to incorrect interrupt */
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
 #endif
@@ -1977,8 +2428,8 @@ void DMA0_DriverIRQHandler(void)
 void DMA1_DriverIRQHandler(void)
 {
     EDMA_HandleIRQ(s_EDMAHandle[1]);
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-      exception return operation might vector to incorrect interrupt */
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
 #endif
@@ -1987,8 +2438,8 @@ void DMA1_DriverIRQHandler(void)
 void DMA2_DriverIRQHandler(void)
 {
     EDMA_HandleIRQ(s_EDMAHandle[2]);
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-      exception return operation might vector to incorrect interrupt */
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
 #endif
@@ -1997,21 +2448,21 @@ void DMA2_DriverIRQHandler(void)
 void DMA3_DriverIRQHandler(void)
 {
     EDMA_HandleIRQ(s_EDMAHandle[3]);
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-      exception return operation might vector to incorrect interrupt */
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
 #endif
 }
 
 /* 8 channels (No Shared) */
-#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL > 4U
+#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && (FSL_FEATURE_EDMA_MODULE_CHANNEL > 4U)
 
 void DMA4_DriverIRQHandler(void)
 {
     EDMA_HandleIRQ(s_EDMAHandle[4]);
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-      exception return operation might vector to incorrect interrupt */
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
 #endif
@@ -2020,8 +2471,8 @@ void DMA4_DriverIRQHandler(void)
 void DMA5_DriverIRQHandler(void)
 {
     EDMA_HandleIRQ(s_EDMAHandle[5]);
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-      exception return operation might vector to incorrect interrupt */
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
 #endif
@@ -2030,8 +2481,8 @@ void DMA5_DriverIRQHandler(void)
 void DMA6_DriverIRQHandler(void)
 {
     EDMA_HandleIRQ(s_EDMAHandle[6]);
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-      exception return operation might vector to incorrect interrupt */
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
 #endif
@@ -2040,8 +2491,8 @@ void DMA6_DriverIRQHandler(void)
 void DMA7_DriverIRQHandler(void)
 {
     EDMA_HandleIRQ(s_EDMAHandle[7]);
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-      exception return operation might vector to incorrect interrupt */
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
 #endif
@@ -2049,13 +2500,13 @@ void DMA7_DriverIRQHandler(void)
 #endif /* FSL_FEATURE_EDMA_MODULE_CHANNEL == 8 */
 
 /* 16 channels (No Shared) */
-#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL > 8U
+#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && (FSL_FEATURE_EDMA_MODULE_CHANNEL > 8U)
 
 void DMA8_DriverIRQHandler(void)
 {
     EDMA_HandleIRQ(s_EDMAHandle[8]);
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-      exception return operation might vector to incorrect interrupt */
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
 #endif
@@ -2064,8 +2515,8 @@ void DMA8_DriverIRQHandler(void)
 void DMA9_DriverIRQHandler(void)
 {
     EDMA_HandleIRQ(s_EDMAHandle[9]);
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-      exception return operation might vector to incorrect interrupt */
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
 #endif
@@ -2074,8 +2525,8 @@ void DMA9_DriverIRQHandler(void)
 void DMA10_DriverIRQHandler(void)
 {
     EDMA_HandleIRQ(s_EDMAHandle[10]);
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-      exception return operation might vector to incorrect interrupt */
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
 #endif
@@ -2084,8 +2535,8 @@ void DMA10_DriverIRQHandler(void)
 void DMA11_DriverIRQHandler(void)
 {
     EDMA_HandleIRQ(s_EDMAHandle[11]);
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-      exception return operation might vector to incorrect interrupt */
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
 #endif
@@ -2094,8 +2545,8 @@ void DMA11_DriverIRQHandler(void)
 void DMA12_DriverIRQHandler(void)
 {
     EDMA_HandleIRQ(s_EDMAHandle[12]);
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-      exception return operation might vector to incorrect interrupt */
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
 #endif
@@ -2104,8 +2555,8 @@ void DMA12_DriverIRQHandler(void)
 void DMA13_DriverIRQHandler(void)
 {
     EDMA_HandleIRQ(s_EDMAHandle[13]);
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-      exception return operation might vector to incorrect interrupt */
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
 #endif
@@ -2114,8 +2565,8 @@ void DMA13_DriverIRQHandler(void)
 void DMA14_DriverIRQHandler(void)
 {
     EDMA_HandleIRQ(s_EDMAHandle[14]);
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-      exception return operation might vector to incorrect interrupt */
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
 #endif
@@ -2124,8 +2575,8 @@ void DMA14_DriverIRQHandler(void)
 void DMA15_DriverIRQHandler(void)
 {
     EDMA_HandleIRQ(s_EDMAHandle[15]);
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-      exception return operation might vector to incorrect interrupt */
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
 #endif
@@ -2133,13 +2584,13 @@ void DMA15_DriverIRQHandler(void)
 #endif /* FSL_FEATURE_EDMA_MODULE_CHANNEL == 16 */
 
 /* 32 channels (No Shared) */
-#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL > 16U
+#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && (FSL_FEATURE_EDMA_MODULE_CHANNEL > 16U)
 
 void DMA16_DriverIRQHandler(void)
 {
     EDMA_HandleIRQ(s_EDMAHandle[16]);
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-      exception return operation might vector to incorrect interrupt */
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
 #endif
@@ -2148,8 +2599,8 @@ void DMA16_DriverIRQHandler(void)
 void DMA17_DriverIRQHandler(void)
 {
     EDMA_HandleIRQ(s_EDMAHandle[17]);
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-      exception return operation might vector to incorrect interrupt */
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
 #endif
@@ -2158,8 +2609,8 @@ void DMA17_DriverIRQHandler(void)
 void DMA18_DriverIRQHandler(void)
 {
     EDMA_HandleIRQ(s_EDMAHandle[18]);
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-      exception return operation might vector to incorrect interrupt */
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
 #endif
@@ -2168,8 +2619,8 @@ void DMA18_DriverIRQHandler(void)
 void DMA19_DriverIRQHandler(void)
 {
     EDMA_HandleIRQ(s_EDMAHandle[19]);
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-      exception return operation might vector to incorrect interrupt */
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
 #endif
@@ -2178,8 +2629,8 @@ void DMA19_DriverIRQHandler(void)
 void DMA20_DriverIRQHandler(void)
 {
     EDMA_HandleIRQ(s_EDMAHandle[20]);
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-      exception return operation might vector to incorrect interrupt */
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
 #endif
@@ -2188,8 +2639,8 @@ void DMA20_DriverIRQHandler(void)
 void DMA21_DriverIRQHandler(void)
 {
     EDMA_HandleIRQ(s_EDMAHandle[21]);
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-      exception return operation might vector to incorrect interrupt */
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
 #endif
@@ -2198,8 +2649,8 @@ void DMA21_DriverIRQHandler(void)
 void DMA22_DriverIRQHandler(void)
 {
     EDMA_HandleIRQ(s_EDMAHandle[22]);
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-      exception return operation might vector to incorrect interrupt */
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
 #endif
@@ -2208,8 +2659,8 @@ void DMA22_DriverIRQHandler(void)
 void DMA23_DriverIRQHandler(void)
 {
     EDMA_HandleIRQ(s_EDMAHandle[23]);
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-      exception return operation might vector to incorrect interrupt */
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
 #endif
@@ -2218,8 +2669,8 @@ void DMA23_DriverIRQHandler(void)
 void DMA24_DriverIRQHandler(void)
 {
     EDMA_HandleIRQ(s_EDMAHandle[24]);
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-      exception return operation might vector to incorrect interrupt */
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
 #endif
@@ -2228,8 +2679,8 @@ void DMA24_DriverIRQHandler(void)
 void DMA25_DriverIRQHandler(void)
 {
     EDMA_HandleIRQ(s_EDMAHandle[25]);
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-      exception return operation might vector to incorrect interrupt */
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
 #endif
@@ -2238,8 +2689,8 @@ void DMA25_DriverIRQHandler(void)
 void DMA26_DriverIRQHandler(void)
 {
     EDMA_HandleIRQ(s_EDMAHandle[26]);
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-      exception return operation might vector to incorrect interrupt */
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
 #endif
@@ -2248,8 +2699,8 @@ void DMA26_DriverIRQHandler(void)
 void DMA27_DriverIRQHandler(void)
 {
     EDMA_HandleIRQ(s_EDMAHandle[27]);
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-      exception return operation might vector to incorrect interrupt */
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
 #endif
@@ -2258,8 +2709,8 @@ void DMA27_DriverIRQHandler(void)
 void DMA28_DriverIRQHandler(void)
 {
     EDMA_HandleIRQ(s_EDMAHandle[28]);
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-      exception return operation might vector to incorrect interrupt */
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
 #endif
@@ -2268,8 +2719,8 @@ void DMA28_DriverIRQHandler(void)
 void DMA29_DriverIRQHandler(void)
 {
     EDMA_HandleIRQ(s_EDMAHandle[29]);
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-      exception return operation might vector to incorrect interrupt */
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
 #endif
@@ -2278,8 +2729,8 @@ void DMA29_DriverIRQHandler(void)
 void DMA30_DriverIRQHandler(void)
 {
     EDMA_HandleIRQ(s_EDMAHandle[30]);
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-      exception return operation might vector to incorrect interrupt */
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
 #endif
@@ -2288,8 +2739,8 @@ void DMA30_DriverIRQHandler(void)
 void DMA31_DriverIRQHandler(void)
 {
     EDMA_HandleIRQ(s_EDMAHandle[31]);
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-      exception return operation might vector to incorrect interrupt */
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
 #endif
@@ -2297,3 +2748,4 @@ void DMA31_DriverIRQHandler(void)
 #endif /* FSL_FEATURE_EDMA_MODULE_CHANNEL == 32 */
 
 #endif /* 4/8/16/32 channels (No Shared)  */
+#endif /* FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SHARED_OFFSET */
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_edma.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_edma.h
index 03bc8db16dd..6fe8de688d5 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_edma.h
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_edma.h
@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
+ * Copyright 2016-2018 NXP
  * All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #ifndef _FSL_EDMA_H_
@@ -49,22 +23,19 @@
 /*! @name Driver version */
 /*@{*/
 /*! @brief eDMA driver version */
-#define FSL_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 1, 2)) /*!< Version 2.1.2. */
+#define FSL_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 1, 7)) /*!< Version 2.1.7. */
 /*@}*/
 
 /*! @brief Compute the offset unit from DCHPRI3 */
-#define DMA_DCHPRI_INDEX(channel) (((channel) & ~0x03U) | (3 - ((channel)&0x03U)))
-
-/*! @brief Get the pointer of DCHPRIn */
-#define DMA_DCHPRIn(base, channel) ((volatile uint8_t *)&((base)->DCHPRI3))[DMA_DCHPRI_INDEX(channel)]
+#define DMA_DCHPRI_INDEX(channel) (((channel) & ~0x03U) | (3U - ((channel)&0x03U)))
 
 /*! @brief eDMA transfer configuration */
 typedef enum _edma_transfer_size
 {
-    kEDMA_TransferSize1Bytes = 0x0U,  /*!< Source/Destination data transfer size is 1 byte every time */
-    kEDMA_TransferSize2Bytes = 0x1U,  /*!< Source/Destination data transfer size is 2 bytes every time */
-    kEDMA_TransferSize4Bytes = 0x2U,  /*!< Source/Destination data transfer size is 4 bytes every time */
-    kEDMA_TransferSize8Bytes = 0x3U,  /*!< Source/Destination data transfer size is 8 bytes every time */
+    kEDMA_TransferSize1Bytes  = 0x0U, /*!< Source/Destination data transfer size is 1 byte every time */
+    kEDMA_TransferSize2Bytes  = 0x1U, /*!< Source/Destination data transfer size is 2 bytes every time */
+    kEDMA_TransferSize4Bytes  = 0x2U, /*!< Source/Destination data transfer size is 4 bytes every time */
+    kEDMA_TransferSize8Bytes  = 0x3U, /*!< Source/Destination data transfer size is 8 bytes every time */
     kEDMA_TransferSize16Bytes = 0x4U, /*!< Source/Destination data transfer size is 16 bytes every time */
     kEDMA_TransferSize32Bytes = 0x5U, /*!< Source/Destination data transfer size is 32 bytes every time */
 } edma_transfer_size_t;
@@ -109,7 +80,7 @@ typedef enum _edma_modulo
 /*! @brief Bandwidth control */
 typedef enum _edma_bandwidth
 {
-    kEDMA_BandwidthStallNone = 0x0U,   /*!< No eDMA engine stalls. */
+    kEDMA_BandwidthStallNone   = 0x0U, /*!< No eDMA engine stalls. */
     kEDMA_BandwidthStall4Cycle = 0x2U, /*!< eDMA engine stalls for 4 cycles after each read/write. */
     kEDMA_BandwidthStall8Cycle = 0x3U, /*!< eDMA engine stalls for 8 cycles after each read/write. */
 } edma_bandwidth_t;
@@ -125,29 +96,29 @@ typedef enum _edma_channel_link_type
 /*!@brief eDMA channel status flags. */
 enum _edma_channel_status_flags
 {
-    kEDMA_DoneFlag = 0x1U,      /*!< DONE flag, set while transfer finished, CITER value exhausted*/
-    kEDMA_ErrorFlag = 0x2U,     /*!< eDMA error flag, an error occurred in a transfer */
+    kEDMA_DoneFlag      = 0x1U, /*!< DONE flag, set while transfer finished, CITER value exhausted*/
+    kEDMA_ErrorFlag     = 0x2U, /*!< eDMA error flag, an error occurred in a transfer */
     kEDMA_InterruptFlag = 0x4U, /*!< eDMA interrupt flag, set while an interrupt occurred of this channel */
 };
 
 /*! @brief eDMA channel error status flags. */
 enum _edma_error_status_flags
 {
-    kEDMA_DestinationBusErrorFlag = DMA_ES_DBE_MASK,    /*!< Bus error on destination address */
-    kEDMA_SourceBusErrorFlag = DMA_ES_SBE_MASK,         /*!< Bus error on the source address */
-    kEDMA_ScatterGatherErrorFlag = DMA_ES_SGE_MASK,     /*!< Error on the Scatter/Gather address, not 32byte aligned. */
-    kEDMA_NbytesErrorFlag = DMA_ES_NCE_MASK,            /*!< NBYTES/CITER configuration error */
+    kEDMA_DestinationBusErrorFlag    = DMA_ES_DBE_MASK, /*!< Bus error on destination address */
+    kEDMA_SourceBusErrorFlag         = DMA_ES_SBE_MASK, /*!< Bus error on the source address */
+    kEDMA_ScatterGatherErrorFlag     = DMA_ES_SGE_MASK, /*!< Error on the Scatter/Gather address, not 32byte aligned. */
+    kEDMA_NbytesErrorFlag            = DMA_ES_NCE_MASK, /*!< NBYTES/CITER configuration error */
     kEDMA_DestinationOffsetErrorFlag = DMA_ES_DOE_MASK, /*!< Destination offset not aligned with destination size */
     kEDMA_DestinationAddressErrorFlag = DMA_ES_DAE_MASK, /*!< Destination address not aligned with destination size */
-    kEDMA_SourceOffsetErrorFlag = DMA_ES_SOE_MASK,       /*!< Source offset not aligned with source size */
-    kEDMA_SourceAddressErrorFlag = DMA_ES_SAE_MASK,      /*!< Source address not aligned with source size*/
-    kEDMA_ErrorChannelFlag = DMA_ES_ERRCHN_MASK,         /*!< Error channel number of the cancelled channel number */
-    kEDMA_ChannelPriorityErrorFlag = DMA_ES_CPE_MASK,    /*!< Channel priority is not unique. */
-    kEDMA_TransferCanceledFlag = DMA_ES_ECX_MASK,        /*!< Transfer cancelled */
-#if defined(FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT) && FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT > 1
+    kEDMA_SourceOffsetErrorFlag       = DMA_ES_SOE_MASK, /*!< Source offset not aligned with source size */
+    kEDMA_SourceAddressErrorFlag      = DMA_ES_SAE_MASK, /*!< Source address not aligned with source size*/
+    kEDMA_ErrorChannelFlag            = DMA_ES_ERRCHN_MASK, /*!< Error channel number of the cancelled channel number */
+    kEDMA_ChannelPriorityErrorFlag    = DMA_ES_CPE_MASK,    /*!< Channel priority is not unique. */
+    kEDMA_TransferCanceledFlag        = DMA_ES_ECX_MASK,    /*!< Transfer cancelled */
+#if defined(FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT) && (FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT > 1)
     kEDMA_GroupPriorityErrorFlag = DMA_ES_GPE_MASK, /*!< Group priority is not unique. */
 #endif
-    kEDMA_ValidFlag = DMA_ES_VLD_MASK, /*!< No error occurred, this bit is 0. Otherwise, it is 1. */
+    kEDMA_ValidFlag = (int)DMA_ES_VLD_MASK, /*!< No error occurred, this bit is 0. Otherwise, it is 1. */
 };
 
 /*! @brief eDMA interrupt source */
@@ -155,7 +126,7 @@ typedef enum _edma_interrupt_enable
 {
     kEDMA_ErrorInterruptEnable = 0x1U,                  /*!< Enable interrupt while channel error occurs. */
     kEDMA_MajorInterruptEnable = DMA_CSR_INTMAJOR_MASK, /*!< Enable interrupt while major count exhausted. */
-    kEDMA_HalfInterruptEnable = DMA_CSR_INTHALF_MASK,   /*!< Enable interrupt while major count to half value. */
+    kEDMA_HalfInterruptEnable  = DMA_CSR_INTHALF_MASK,  /*!< Enable interrupt while major count to half value. */
 } edma_interrupt_enable_t;
 
 /*! @brief eDMA transfer type */
@@ -170,7 +141,7 @@ typedef enum _edma_transfer_type
 enum _edma_transfer_status
 {
     kStatus_EDMA_QueueFull = MAKE_STATUS(kStatusGroup_EDMA, 0), /*!< TCD queue is full. */
-    kStatus_EDMA_Busy = MAKE_STATUS(kStatusGroup_EDMA, 1),      /*!< Channel is busy and can't handle the
+    kStatus_EDMA_Busy      = MAKE_STATUS(kStatusGroup_EDMA, 1), /*!< Channel is busy and can't handle the
                                                                      transfer request. */
 };
 
@@ -239,7 +210,7 @@ typedef struct _edma_tcd
     __IO uint32_t DADDR;     /*!< DADDR register, used for destination address */
     __IO uint16_t DOFF;      /*!< DOFF register, used for destination offset */
     __IO uint16_t CITER;     /*!< CITER register, current minor loop numbers, for unfinished minor loop.*/
-    __IO uint32_t DLAST_SGA; /*!< DLASTSGA register, next stcd address used in scatter-gather mode */
+    __IO uint32_t DLAST_SGA; /*!< DLASTSGA register, next tcd address used in scatter-gather mode */
     __IO uint16_t CSR;       /*!< CSR register, for TCD control status */
     __IO uint16_t BITER;     /*!< BITER register, begin minor loop count. */
 } edma_tcd_t;
@@ -255,10 +226,10 @@ struct _edma_handle;
  * all transfer finished, users can get the finished tcd numbers using interface EDMA_GetUnusedTCDNumber.
  *
  * @param handle EDMA handle pointer, users shall not touch the values inside.
- * @param userData The callback user paramter pointer. Users can use this paramter to involve things users need to
+ * @param userData The callback user parameter pointer. Users can use this parameter to involve things users need to
  *                 change in EDMA callback function.
  * @param transferDone If the current loaded transfer done. In normal mode it means if all transfer done. In scatter
- *                     gather mode, this paramter shows is the current transfer block in EDMA regsiter is done. As the
+ *                     gather mode, this parameter shows is the current transfer block in EDMA register is done. As the
  *                     load of core is different, it will be different if the new tcd loaded into EDMA registers while
  *                     this callback called. If true, it always means new tcd still not loaded into registers, while
  *                     false means new tcd already loaded into registers.
@@ -411,17 +382,7 @@ void EDMA_SetMinorOffsetConfig(DMA_Type *base, uint32_t channel, const edma_mino
  * @param channel eDMA channel number
  * @param config A pointer to the channel preemption configuration structure.
  */
-static inline void EDMA_SetChannelPreemptionConfig(DMA_Type *base,
-                                                   uint32_t channel,
-                                                   const edma_channel_Preemption_config_t *config)
-{
-    assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
-    assert(config != NULL);
-
-    DMA_DCHPRIn(base, channel) =
-        (DMA_DCHPRI0_DPA(!config->enablePreemptAbility) | DMA_DCHPRI0_ECP(config->enableChannelPreemption) |
-         DMA_DCHPRI0_CHPRI(config->channelPriority));
-}
+void EDMA_SetChannelPreemptionConfig(DMA_Type *base, uint32_t channel, const edma_channel_Preemption_config_t *config);
 
 /*!
  * @brief Sets the channel link for the eDMA transfer.
@@ -481,9 +442,9 @@ void EDMA_SetModulo(DMA_Type *base, uint32_t channel, edma_modulo_t srcModulo, e
  */
 static inline void EDMA_EnableAsyncRequest(DMA_Type *base, uint32_t channel, bool enable)
 {
-    assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
+    assert(channel < (uint32_t)FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
 
-    base->EARS = (base->EARS & (~(1U << channel))) | ((uint32_t)enable << channel);
+    base->EARS = (base->EARS & (uint32_t)(~(1U << channel))) | ((true == enable ? 1U : 0U) << channel);
 }
 #endif /* FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT */
 
@@ -498,9 +459,10 @@ static inline void EDMA_EnableAsyncRequest(DMA_Type *base, uint32_t channel, boo
  */
 static inline void EDMA_EnableAutoStopRequest(DMA_Type *base, uint32_t channel, bool enable)
 {
-    assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
+    assert(channel < (uint32_t)FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
 
-    base->TCD[channel].CSR = (base->TCD[channel].CSR & (~DMA_CSR_DREQ_MASK)) | DMA_CSR_DREQ(enable);
+    base->TCD[channel].CSR =
+        (uint16_t)((base->TCD[channel].CSR & (~DMA_CSR_DREQ_MASK)) | DMA_CSR_DREQ((true == enable ? 1U : 0U)));
 }
 
 /*!
@@ -611,9 +573,9 @@ void EDMA_TcdSetChannelLink(edma_tcd_t *tcd, edma_channel_link_type_t type, uint
 static inline void EDMA_TcdSetBandWidth(edma_tcd_t *tcd, edma_bandwidth_t bandWidth)
 {
     assert(tcd != NULL);
-    assert(((uint32_t)tcd & 0x1FU) == 0);
+    assert(((uint32_t)tcd & 0x1FU) == 0U);
 
-    tcd->CSR = (tcd->CSR & (~DMA_CSR_BWC_MASK)) | DMA_CSR_BWC(bandWidth);
+    tcd->CSR = (uint16_t)((tcd->CSR & (~DMA_CSR_BWC_MASK)) | DMA_CSR_BWC(bandWidth));
 }
 
 /*!
@@ -640,9 +602,9 @@ void EDMA_TcdSetModulo(edma_tcd_t *tcd, edma_modulo_t srcModulo, edma_modulo_t d
 static inline void EDMA_TcdEnableAutoStopRequest(edma_tcd_t *tcd, bool enable)
 {
     assert(tcd != NULL);
-    assert(((uint32_t)tcd & 0x1FU) == 0);
+    assert(((uint32_t)tcd & 0x1FU) == 0U);
 
-    tcd->CSR = (tcd->CSR & (~DMA_CSR_DREQ_MASK)) | DMA_CSR_DREQ(enable);
+    tcd->CSR = (uint16_t)((tcd->CSR & (~DMA_CSR_DREQ_MASK)) | DMA_CSR_DREQ((true == enable ? 1U : 0U)));
 }
 
 /*!
@@ -679,7 +641,7 @@ void EDMA_TcdDisableInterrupts(edma_tcd_t *tcd, uint32_t mask);
  */
 static inline void EDMA_EnableChannelRequest(DMA_Type *base, uint32_t channel)
 {
-    assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
+    assert(channel < (uint32_t)FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
 
     base->SERQ = DMA_SERQ_SERQ(channel);
 }
@@ -694,7 +656,7 @@ static inline void EDMA_EnableChannelRequest(DMA_Type *base, uint32_t channel)
  */
 static inline void EDMA_DisableChannelRequest(DMA_Type *base, uint32_t channel)
 {
-    assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
+    assert(channel < (uint32_t)FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
 
     base->CERQ = DMA_CERQ_CERQ(channel);
 }
@@ -709,7 +671,7 @@ static inline void EDMA_DisableChannelRequest(DMA_Type *base, uint32_t channel)
  */
 static inline void EDMA_TriggerChannelStart(DMA_Type *base, uint32_t channel)
 {
-    assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
+    assert(channel < (uint32_t)FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
 
     base->SSRT = DMA_SSRT_SSRT(channel);
 }
@@ -748,7 +710,7 @@ uint32_t EDMA_GetRemainingMajorLoopCount(DMA_Type *base, uint32_t channel);
  *
  * @param base eDMA peripheral base address.
  * @return The mask of error status flags. Users need to use the
-*         _edma_error_status_flags type to decode the return variables.
+ *         _edma_error_status_flags type to decode the return variables.
  */
 static inline uint32_t EDMA_GetErrorStatusFlags(DMA_Type *base)
 {
@@ -799,7 +761,7 @@ void EDMA_CreateHandle(edma_handle_t *handle, DMA_Type *base, uint32_t channel);
  * This function is called after the EDMA_CreateHandle to use scatter/gather feature. This function shall only be used
  * while users need to use scatter gather mode. Scatter gather mode enables EDMA to load a new transfer control block
  * (tcd) in hardware, and automatically reconfigure that DMA channel for a new transfer.
- * Users need to preapre tcd memory and also configure tcds using interface EDMA_SubmitTransfer.
+ * Users need to prepare tcd memory and also configure tcds using interface EDMA_SubmitTransfer.
  *
  * @param handle eDMA handle pointer.
  * @param tcdPool A memory pool to store TCDs. It must be 32 bytes aligned.
@@ -900,7 +862,9 @@ void EDMA_AbortTransfer(edma_handle_t *handle);
  */
 static inline uint32_t EDMA_GetUnusedTCDNumber(edma_handle_t *handle)
 {
-    return (handle->tcdSize - handle->tcdUsed);
+    int8_t tmpTcdSize = handle->tcdSize;
+    int8_t tmpTcdUsed = handle->tcdUsed;
+    return ((uint32_t)tmpTcdSize - (uint32_t)tmpTcdUsed);
 }
 
 /*!
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_elcdif.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_elcdif.c
index 51aabe3b885..5a2aa820f17 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_elcdif.c
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_elcdif.c
@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
- * Copyright (c) 2017, NXP Semiconductors, Inc.
+ * Copyright  2017 NXP
  * All rights reserved.
  *
- * 
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
  *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include "fsl_elcdif.h"
@@ -39,7 +13,6 @@
 #define FSL_COMPONENT_ID "platform.drivers.elcdif"
 #endif
 
-
 /*******************************************************************************
  * Prototypes
  ******************************************************************************/
@@ -117,6 +90,15 @@ static uint32_t ELCDIF_GetInstance(LCDIF_Type *base)
     return instance;
 }
 
+/*!
+ * brief Initializes the eLCDIF to work in RGB mode (DOTCLK mode).
+ *
+ * This function ungates the eLCDIF clock and configures the eLCDIF peripheral according
+ * to the configuration structure.
+ *
+ * param base eLCDIF peripheral base address.
+ * param config Pointer to the configuration structure.
+ */
 void ELCDIF_RgbModeInit(LCDIF_Type *base, const elcdif_rgb_mode_config_t *config)
 {
     assert(config);
@@ -160,14 +142,16 @@ void ELCDIF_RgbModeInit(LCDIF_Type *base, const elcdif_rgb_mode_config_t *config
     base->VDCTRL4 = LCDIF_VDCTRL4_SYNC_SIGNALS_ON_MASK |
                     ((uint32_t)config->panelWidth << LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_SHIFT);
 
-    base->CUR_BUF = config->bufferAddr;
+    base->CUR_BUF  = config->bufferAddr;
     base->NEXT_BUF = config->bufferAddr;
 }
 
-void ELCDIF_RgbModeGetDefaultConfig(elcdif_rgb_mode_config_t *config)
-{
-    assert(config);
-
+/*!
+ * brief Gets the eLCDIF default configuration structure for RGB (DOTCLK) mode.
+ *
+ * This function sets the configuration structure to default values.
+ * The default configuration is set to the following values.
+ * code
     config->panelWidth = 480U;
     config->panelHeight = 272U;
     config->hsw = 41;
@@ -176,13 +160,61 @@ void ELCDIF_RgbModeGetDefaultConfig(elcdif_rgb_mode_config_t *config)
     config->vsw = 10;
     config->vfp = 4;
     config->vbp = 2;
-    config->polarityFlags = kELCDIF_VsyncActiveLow | kELCDIF_HsyncActiveLow | kELCDIF_DataEnableActiveLow |
+    config->polarityFlags = kELCDIF_VsyncActiveLow |
+                            kELCDIF_HsyncActiveLow |
+                            kELCDIF_DataEnableActiveLow |
                             kELCDIF_DriveDataOnFallingClkEdge;
     config->bufferAddr = 0U;
     config->pixelFormat = kELCDIF_PixelFormatRGB888;
     config->dataBus = kELCDIF_DataBus24Bit;
+    code
+ *
+ * param config Pointer to the eLCDIF configuration structure.
+ */
+void ELCDIF_RgbModeGetDefaultConfig(elcdif_rgb_mode_config_t *config)
+{
+    assert(config);
+
+    /* Initializes the configure structure to zero. */
+    memset(config, 0, sizeof(*config));
+
+    config->panelWidth    = 480U;
+    config->panelHeight   = 272U;
+    config->hsw           = 41;
+    config->hfp           = 4;
+    config->hbp           = 8;
+    config->vsw           = 10;
+    config->vfp           = 4;
+    config->vbp           = 2;
+    config->polarityFlags = kELCDIF_VsyncActiveLow | kELCDIF_HsyncActiveLow | kELCDIF_DataEnableActiveLow |
+                            kELCDIF_DriveDataOnFallingClkEdge;
+    config->bufferAddr  = 0U;
+    config->pixelFormat = kELCDIF_PixelFormatRGB888;
+    config->dataBus     = kELCDIF_DataBus24Bit;
 }
 
+/*!
+ * brief Set the pixel format in RGB (DOTCLK) mode.
+ *
+ * param base eLCDIF peripheral base address.
+ * param pixelFormat The pixel format.
+ */
+void ELCDIF_RgbModeSetPixelFormat(LCDIF_Type *base, elcdif_pixel_format_t pixelFormat)
+{
+    assert(pixelFormat < ARRAY_SIZE(s_pixelFormatReg));
+
+    base->CTRL = (base->CTRL & ~(LCDIF_CTRL_WORD_LENGTH_MASK | LCDIF_CTRL_DATA_FORMAT_24_BIT_MASK |
+                                 LCDIF_CTRL_DATA_FORMAT_18_BIT_MASK | LCDIF_CTRL_DATA_FORMAT_16_BIT_MASK)) |
+                 s_pixelFormatReg[(uint32_t)pixelFormat].regCtrl;
+
+    base->CTRL1 = s_pixelFormatReg[(uint32_t)pixelFormat].regCtrl1;
+}
+
+/*!
+ * brief Deinitializes the eLCDIF peripheral.
+ *
+ * param base eLCDIF peripheral base address.
+ */
 void ELCDIF_Deinit(LCDIF_Type *base)
 {
     ELCDIF_Reset(base);
@@ -197,6 +229,11 @@ void ELCDIF_Deinit(LCDIF_Type *base)
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }
 
+/*!
+ * brief Stop display in RGB (DOTCLK) mode and wait until finished.
+ *
+ * param base eLCDIF peripheral base address.
+ */
 void ELCDIF_RgbModeStop(LCDIF_Type *base)
 {
     base->CTRL_CLR = LCDIF_CTRL_DOTCLK_MODE_MASK;
@@ -207,6 +244,11 @@ void ELCDIF_RgbModeStop(LCDIF_Type *base)
     }
 }
 
+/*!
+ * brief Reset the eLCDIF peripheral.
+ *
+ * param base eLCDIF peripheral base address.
+ */
 void ELCDIF_Reset(LCDIF_Type *base)
 {
     volatile uint32_t i = 0x100;
@@ -237,15 +279,27 @@ void ELCDIF_Reset(LCDIF_Type *base)
 }
 
 #if !(defined(FSL_FEATURE_LCDIF_HAS_NO_AS) && FSL_FEATURE_LCDIF_HAS_NO_AS)
+/*!
+ * brief Set the configuration for alpha surface buffer.
+ *
+ * param base eLCDIF peripheral base address.
+ * param config Pointer to the configuration structure.
+ */
 void ELCDIF_SetAlphaSurfaceBufferConfig(LCDIF_Type *base, const elcdif_as_buffer_config_t *config)
 {
     assert(config);
 
-    base->AS_CTRL = (base->AS_CTRL & ~LCDIF_AS_CTRL_FORMAT_MASK) | LCDIF_AS_CTRL_FORMAT(config->pixelFormat);
-    base->AS_BUF = config->bufferAddr;
+    base->AS_CTRL     = (base->AS_CTRL & ~LCDIF_AS_CTRL_FORMAT_MASK) | LCDIF_AS_CTRL_FORMAT(config->pixelFormat);
+    base->AS_BUF      = config->bufferAddr;
     base->AS_NEXT_BUF = config->bufferAddr;
 }
 
+/*!
+ * brief Set the alpha surface blending configuration.
+ *
+ * param base eLCDIF peripheral base address.
+ * param config Pointer to the configuration structure.
+ */
 void ELCDIF_SetAlphaSurfaceBlendConfig(LCDIF_Type *base, const elcdif_as_blend_config_t *config)
 {
     assert(config);
@@ -267,6 +321,20 @@ void ELCDIF_SetAlphaSurfaceBlendConfig(LCDIF_Type *base, const elcdif_as_blend_c
 #endif /* FSL_FEATURE_LCDIF_HAS_NO_AS */
 
 #if (defined(FSL_FEATURE_LCDIF_HAS_LUT) && FSL_FEATURE_LCDIF_HAS_LUT)
+/*!
+ * brief Load the LUT value.
+ *
+ * This function loads the LUT value to the specific LUT memory, user can
+ * specify the start entry index.
+ *
+ * param base eLCDIF peripheral base address.
+ * param lut Which LUT to load.
+ * param startIndex The start index of the LUT entry to update.
+ * param lutData The LUT data to load.
+ * param count Count of p lutData.
+ * retval kStatus_Success Initialization success.
+ * retval kStatus_InvalidArgument Wrong argument.
+ */
 status_t ELCDIF_UpdateLut(
     LCDIF_Type *base, elcdif_lut_t lut, uint16_t startIndex, const uint32_t *lutData, uint16_t count)
 {
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_elcdif.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_elcdif.h
index 2183c84f7d7..68e5019faee 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_elcdif.h
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_elcdif.h
@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
- * Copyright (c) 2017, NXP Semiconductors, Inc.
+ * Copyright  2017 NXP
  * All rights reserved.
  *
- * 
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
  *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #ifndef _FSL_ELCDIF_H_
@@ -49,7 +23,7 @@
 /*! @name Driver version */
 /*@{*/
 /*! @brief eLCDIF driver version */
-#define FSL_ELCDIF_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */
+#define FSL_ELCDIF_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) /*!< Version 2.0.1. */
 /*@}*/
 
 /* All IRQ flags in CTRL1 register. */
@@ -88,14 +62,14 @@
  */
 enum _elcdif_polarity_flags
 {
-    kELCDIF_VsyncActiveLow = 0U,                                  /*!< VSYNC active low. */
-    kELCDIF_VsyncActiveHigh = LCDIF_VDCTRL0_VSYNC_POL_MASK,       /*!< VSYNC active high. */
-    kELCDIF_HsyncActiveLow = 0U,                                  /*!< HSYNC active low. */
-    kELCDIF_HsyncActiveHigh = LCDIF_VDCTRL0_HSYNC_POL_MASK,       /*!< HSYNC active high. */
-    kELCDIF_DataEnableActiveLow = 0U,                             /*!< Data enable line active low. */
-    kELCDIF_DataEnableActiveHigh = LCDIF_VDCTRL0_ENABLE_POL_MASK, /*!< Data enable line active high. */
-    kELCDIF_DriveDataOnFallingClkEdge = 0U,                       /*!< Drive data on falling clock edge, capture data
-                                                                       on rising clock edge. */
+    kELCDIF_VsyncActiveLow            = 0U,                            /*!< VSYNC active low. */
+    kELCDIF_VsyncActiveHigh           = LCDIF_VDCTRL0_VSYNC_POL_MASK,  /*!< VSYNC active high. */
+    kELCDIF_HsyncActiveLow            = 0U,                            /*!< HSYNC active low. */
+    kELCDIF_HsyncActiveHigh           = LCDIF_VDCTRL0_HSYNC_POL_MASK,  /*!< HSYNC active high. */
+    kELCDIF_DataEnableActiveLow       = 0U,                            /*!< Data enable line active low. */
+    kELCDIF_DataEnableActiveHigh      = LCDIF_VDCTRL0_ENABLE_POL_MASK, /*!< Data enable line active high. */
+    kELCDIF_DriveDataOnFallingClkEdge = 0U, /*!< Drive data on falling clock edge, capture data
+                                                 on rising clock edge. */
     kELCDIF_DriveDataOnRisingClkEdge = LCDIF_VDCTRL0_DOTCLK_POL_MASK, /*!< Drive data on falling
                                                                         clock edge, capture data
                                                                         on rising clock edge. */
@@ -106,8 +80,8 @@ enum _elcdif_polarity_flags
  */
 enum _elcdif_interrupt_enable
 {
-    kELCDIF_BusMasterErrorInterruptEnable = LCDIF_CTRL1_BM_ERROR_IRQ_EN_MASK,   /*!< Bus master error interrupt. */
-    kELCDIF_TxFifoOverflowInterruptEnable = LCDIF_CTRL1_OVERFLOW_IRQ_EN_MASK,   /*!< TXFIFO overflow interrupt. */
+    kELCDIF_BusMasterErrorInterruptEnable  = LCDIF_CTRL1_BM_ERROR_IRQ_EN_MASK,  /*!< Bus master error interrupt. */
+    kELCDIF_TxFifoOverflowInterruptEnable  = LCDIF_CTRL1_OVERFLOW_IRQ_EN_MASK,  /*!< TXFIFO overflow interrupt. */
     kELCDIF_TxFifoUnderflowInterruptEnable = LCDIF_CTRL1_UNDERFLOW_IRQ_EN_MASK, /*!< TXFIFO underflow interrupt. */
     kELCDIF_CurFrameDoneInterruptEnable =
         LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_MASK, /*!< Interrupt when hardware enters vertical blanking state. */
@@ -124,8 +98,8 @@ enum _elcdif_interrupt_enable
  */
 enum _elcdif_interrupt_flags
 {
-    kELCDIF_BusMasterError = LCDIF_CTRL1_BM_ERROR_IRQ_MASK,   /*!< Bus master error interrupt. */
-    kELCDIF_TxFifoOverflow = LCDIF_CTRL1_OVERFLOW_IRQ_MASK,   /*!< TXFIFO overflow interrupt. */
+    kELCDIF_BusMasterError  = LCDIF_CTRL1_BM_ERROR_IRQ_MASK,  /*!< Bus master error interrupt. */
+    kELCDIF_TxFifoOverflow  = LCDIF_CTRL1_OVERFLOW_IRQ_MASK,  /*!< TXFIFO overflow interrupt. */
     kELCDIF_TxFifoUnderflow = LCDIF_CTRL1_UNDERFLOW_IRQ_MASK, /*!< TXFIFO underflow interrupt. */
     kELCDIF_CurFrameDone =
         LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_MASK,             /*!< Interrupt when hardware enters vertical blanking state. */
@@ -140,9 +114,9 @@ enum _elcdif_interrupt_flags
  */
 enum _elcdif_status_flags
 {
-    kELCDIF_LFifoFull = LCDIF_STAT_LFIFO_FULL_MASK,     /*!< LFIFO full. */
-    kELCDIF_LFifoEmpty = LCDIF_STAT_LFIFO_EMPTY_MASK,   /*!< LFIFO empty. */
-    kELCDIF_TxFifoFull = LCDIF_STAT_TXFIFO_FULL_MASK,   /*!< TXFIFO full. */
+    kELCDIF_LFifoFull   = LCDIF_STAT_LFIFO_FULL_MASK,   /*!< LFIFO full. */
+    kELCDIF_LFifoEmpty  = LCDIF_STAT_LFIFO_EMPTY_MASK,  /*!< LFIFO empty. */
+    kELCDIF_TxFifoFull  = LCDIF_STAT_TXFIFO_FULL_MASK,  /*!< TXFIFO full. */
     kELCDIF_TxFifoEmpty = LCDIF_STAT_TXFIFO_EMPTY_MASK, /*!< TXFIFO empty. */
 #if defined(LCDIF_STAT_BUSY_MASK)
     kELCDIF_LcdControllerBusy = LCDIF_STAT_BUSY_MASK, /*!< The external LCD controller busy signal. */
@@ -161,18 +135,18 @@ enum _elcdif_status_flags
  */
 typedef enum _elcdif_pixel_format
 {
-    kELCDIF_PixelFormatRAW8 = 0,     /*!< RAW 8 bit, four data use 32 bits. */
+    kELCDIF_PixelFormatRAW8   = 0,   /*!< RAW 8 bit, four data use 32 bits. */
     kELCDIF_PixelFormatRGB565 = 1,   /*!< RGB565, two pixel use 32 bits. */
     kELCDIF_PixelFormatRGB666 = 2,   /*!< RGB666 unpacked, one pixel uses 32 bits, high byte unused,
                                           upper 2 bits of other bytes unused. */
     kELCDIF_PixelFormatXRGB8888 = 3, /*!< XRGB8888 unpacked, one pixel uses 32 bits, high byte unused. */
-    kELCDIF_PixelFormatRGB888 = 4,   /*!< RGB888 packed, one pixel uses 24 bits. */
+    kELCDIF_PixelFormatRGB888   = 4, /*!< RGB888 packed, one pixel uses 24 bits. */
 } elcdif_pixel_format_t;
 
 /*! @brief The LCD data bus type.  */
 typedef enum _elcdif_lcd_data_bus
 {
-    kELCDIF_DataBus8Bit = LCDIF_CTRL_LCD_DATABUS_WIDTH(1),  /*!< 8-bit data bus. */
+    kELCDIF_DataBus8Bit  = LCDIF_CTRL_LCD_DATABUS_WIDTH(1), /*!< 8-bit data bus. */
     kELCDIF_DataBus16Bit = LCDIF_CTRL_LCD_DATABUS_WIDTH(0), /*!< 16-bit data bus, support RGB565. */
     kELCDIF_DataBus18Bit = LCDIF_CTRL_LCD_DATABUS_WIDTH(2), /*!< 18-bit data bus, support RGB666. */
     kELCDIF_DataBus24Bit = LCDIF_CTRL_LCD_DATABUS_WIDTH(3), /*!< 24-bit data bus, support RGB888. */
@@ -219,12 +193,12 @@ typedef struct _elcdif_rgb_mode_config
 typedef enum _elcdif_as_pixel_format
 {
     kELCDIF_AsPixelFormatARGB8888 = 0x0, /*!< 32-bit pixels with alpha. */
-    kELCDIF_AsPixelFormatRGB888 = 0x4,   /*!< 32-bit pixels without alpha (unpacked 24-bit format) */
+    kELCDIF_AsPixelFormatRGB888   = 0x4, /*!< 32-bit pixels without alpha (unpacked 24-bit format) */
     kELCDIF_AsPixelFormatARGB1555 = 0x8, /*!< 16-bit pixels with alpha. */
     kELCDIF_AsPixelFormatARGB4444 = 0x9, /*!< 16-bit pixels with alpha. */
-    kELCDIF_AsPixelFormatRGB555 = 0xC,   /*!< 16-bit pixels without alpha. */
-    kELCDIF_AsPixelFormatRGB444 = 0xD,   /*!< 16-bit pixels without alpha. */
-    kELCDIF_AsPixelFormatRGB565 = 0xE,   /*!< 16-bit pixels without alpha. */
+    kELCDIF_AsPixelFormatRGB555   = 0xC, /*!< 16-bit pixels without alpha. */
+    kELCDIF_AsPixelFormatRGB444   = 0xD, /*!< 16-bit pixels without alpha. */
+    kELCDIF_AsPixelFormatRGB565   = 0xE, /*!< 16-bit pixels without alpha. */
 } elcdif_as_pixel_format_t;
 
 /*!
@@ -261,18 +235,18 @@ typedef enum _elcdif_alpha_mode
  */
 typedef enum _elcdif_rop_mode
 {
-    kELCDIF_RopMaskAs = 0x0,     /*!< AS AND PS. */
-    kELCDIF_RopMaskNotAs = 0x1,  /*!< nAS AND PS. */
-    kELCDIF_RopMaskAsNot = 0x2,  /*!< AS AND nPS. */
-    kELCDIF_RopMergeAs = 0x3,    /*!< AS OR PS. */
+    kELCDIF_RopMaskAs     = 0x0, /*!< AS AND PS. */
+    kELCDIF_RopMaskNotAs  = 0x1, /*!< nAS AND PS. */
+    kELCDIF_RopMaskAsNot  = 0x2, /*!< AS AND nPS. */
+    kELCDIF_RopMergeAs    = 0x3, /*!< AS OR PS. */
     kELCDIF_RopMergeNotAs = 0x4, /*!< nAS OR PS. */
     kELCDIF_RopMergeAsNot = 0x5, /*!< AS OR nPS. */
-    kELCDIF_RopNotCopyAs = 0x6,  /*!< nAS. */
-    kELCDIF_RopNot = 0x7,        /*!< nPS. */
-    kELCDIF_RopNotMaskAs = 0x8,  /*!< AS NAND PS. */
+    kELCDIF_RopNotCopyAs  = 0x6, /*!< nAS. */
+    kELCDIF_RopNot        = 0x7, /*!< nPS. */
+    kELCDIF_RopNotMaskAs  = 0x8, /*!< AS NAND PS. */
     kELCDIF_RopNotMergeAs = 0x9, /*!< AS NOR PS. */
-    kELCDIF_RopXorAs = 0xA,      /*!< AS XOR PS. */
-    kELCDIF_RopNotXorAs = 0xB    /*!< AS XNOR PS. */
+    kELCDIF_RopXorAs      = 0xA, /*!< AS XOR PS. */
+    kELCDIF_RopNotXorAs   = 0xB  /*!< AS XNOR PS. */
 } elcdif_rop_mode_t;
 
 /*!
@@ -367,6 +341,14 @@ void ELCDIF_Deinit(LCDIF_Type *base);
  * @{
  */
 
+/*!
+ * @brief Set the pixel format in RGB (DOTCLK) mode.
+ *
+ * @param base eLCDIF peripheral base address.
+ * @param pixelFormat The pixel format.
+ */
+void ELCDIF_RgbModeSetPixelFormat(LCDIF_Type *base, elcdif_pixel_format_t pixelFormat);
+
 /*!
  * @brief Start to display in RGB (DOTCLK) mode.
  *
@@ -513,7 +495,7 @@ static inline uint32_t ELCDIF_GetStatus(LCDIF_Type *base)
 #if defined(LCDIF_STAT_DVI_CURRENT_FIELD_MASK)
                          | LCDIF_STAT_DVI_CURRENT_FIELD_MASK
 #endif
-                         );
+                        );
 }
 
 /*!
@@ -644,7 +626,7 @@ static inline void ELCDIF_SetNextAlphaSurfaceBufferAddr(LCDIF_Type *base, uint32
  */
 static inline void ELCDIF_SetOverlayColorKey(LCDIF_Type *base, uint32_t colorKeyLow, uint32_t colorKeyHigh)
 {
-    base->AS_CLRKEYLOW = colorKeyLow;
+    base->AS_CLRKEYLOW  = colorKeyLow;
     base->AS_CLRKEYHIGH = colorKeyHigh;
 }
 
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_enc.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_enc.c
index 76db836d06b..0c906277590 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_enc.c
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_enc.c
@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
  * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
  *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include "fsl_enc.h"
@@ -88,6 +62,17 @@ static uint32_t ENC_GetInstance(ENC_Type *base)
     return instance;
 }
 
+/*!
+ * brief Initialization for the ENC module.
+ *
+ * This function is to make the initialization for the ENC module. It should be called firstly before any operation to
+ * the ENC with the operations like:
+ *  - Enable the clock for ENC module.
+ *  - Configure the ENC's working attributes.
+ *
+ * param base   ENC peripheral base address.
+ * param config Pointer to configuration structure. See to "enc_config_t".
+ */
 void ENC_Init(ENC_Type *base, const enc_config_t *config)
 {
     assert(NULL != config);
@@ -177,6 +162,15 @@ void ENC_Init(ENC_Type *base, const enc_config_t *config)
     base->LINIT = (uint16_t)(config->positionInitialValue);        /* Lower 16 bits. */
 }
 
+/*!
+ * brief De-initialization for the ENC module.
+ *
+ * This function is to make the de-initialization for the ENC module. It could be called when ENC is no longer used with
+ * the operations like:
+ *  - Disable the clock for ENC module.
+ *
+ * param base ENC peripheral base address.
+ */
 void ENC_Deinit(ENC_Type *base)
 {
 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
@@ -185,28 +179,63 @@ void ENC_Deinit(ENC_Type *base)
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }
 
+/*!
+ * brief Get an available pre-defined settings for ENC's configuration.
+ *
+ * This function initializes the ENC configuration structure with an available settings, the default value are:
+ * code
+ *   config->enableReverseDirection                = false;
+ *   config->decoderWorkMode                       = kENC_DecoderWorkAsNormalMode;
+ *   config->HOMETriggerMode                       = kENC_HOMETriggerDisabled;
+ *   config->INDEXTriggerMode                      = kENC_INDEXTriggerDisabled;
+ *   config->enableTRIGGERClearPositionCounter     = false;
+ *   config->enableTRIGGERClearHoldPositionCounter = false;
+ *   config->enableWatchdog                        = false;
+ *   config->watchdogTimeoutValue                  = 0U;
+ *   config->filterCount                           = 0U;
+ *   config->filterSamplePeriod                    = 0U;
+ *   config->positionMatchMode                     = kENC_POSMATCHOnPositionCounterEqualToComapreValue;
+ *   config->positionCompareValue                  = 0xFFFFFFFFU;
+ *   config->revolutionCountCondition              = kENC_RevolutionCountOnINDEXPulse;
+ *   config->enableModuloCountMode                 = false;
+ *   config->positionModulusValue                  = 0U;
+ *   config->positionInitialValue                  = 0U;
+ * endcode
+ * param config Pointer to a variable of configuration structure. See to "enc_config_t".
+ */
 void ENC_GetDefaultConfig(enc_config_t *config)
 {
     assert(NULL != config);
 
-    config->enableReverseDirection = false;
-    config->decoderWorkMode = kENC_DecoderWorkAsNormalMode;
-    config->HOMETriggerMode = kENC_HOMETriggerDisabled;
-    config->INDEXTriggerMode = kENC_INDEXTriggerDisabled;
-    config->enableTRIGGERClearPositionCounter = false;
+    /* Initializes the configure structure to zero. */
+    memset(config, 0, sizeof(*config));
+
+    config->enableReverseDirection                = false;
+    config->decoderWorkMode                       = kENC_DecoderWorkAsNormalMode;
+    config->HOMETriggerMode                       = kENC_HOMETriggerDisabled;
+    config->INDEXTriggerMode                      = kENC_INDEXTriggerDisabled;
+    config->enableTRIGGERClearPositionCounter     = false;
     config->enableTRIGGERClearHoldPositionCounter = false;
-    config->enableWatchdog = false;
-    config->watchdogTimeoutValue = 0U;
-    config->filterCount = 0U;
-    config->filterSamplePeriod = 0U;
-    config->positionMatchMode = kENC_POSMATCHOnPositionCounterEqualToComapreValue;
-    config->positionCompareValue = 0xFFFFFFFFU;
-    config->revolutionCountCondition = kENC_RevolutionCountOnINDEXPulse;
-    config->enableModuloCountMode = false;
-    config->positionModulusValue = 0U;
-    config->positionInitialValue = 0U;
+    config->enableWatchdog                        = false;
+    config->watchdogTimeoutValue                  = 0U;
+    config->filterCount                           = 0U;
+    config->filterSamplePeriod                    = 0U;
+    config->positionMatchMode                     = kENC_POSMATCHOnPositionCounterEqualToComapreValue;
+    config->positionCompareValue                  = 0xFFFFFFFFU;
+    config->revolutionCountCondition              = kENC_RevolutionCountOnINDEXPulse;
+    config->enableModuloCountMode                 = false;
+    config->positionModulusValue                  = 0U;
+    config->positionInitialValue                  = 0U;
 }
 
+/*!
+ * brief Load the initial position value to position counter.
+ *
+ * This function is to transfer the initial position value (UINIT and LINIT) contents to position counter (UPOS and
+ * LPOS), so that to provide the consistent operation the position counter registers.
+ *
+ * param base ENC peripheral base address.
+ */
 void ENC_DoSoftwareLoadInitialPositionValue(ENC_Type *base)
 {
     uint16_t tmp16 = base->CTRL & (uint16_t)(~ENC_CTRL_W1C_FLAGS);
@@ -215,6 +244,16 @@ void ENC_DoSoftwareLoadInitialPositionValue(ENC_Type *base)
     base->CTRL = tmp16;
 }
 
+/*!
+ * brief Enable and configure the self test function.
+ *
+ * This function is to enable and configuration the self test function. It controls and sets the frequency of a
+ * quadrature signal generator. It provides a quadrature test signal to the inputs of the quadrature decoder module.
+ * It is a factory test feature; however, it may be useful to customers' software development and testing.
+ *
+ * param base   ENC peripheral base address.
+ * param config Pointer to configuration structure. See to "enc_self_test_config_t". Pass "NULL" to disable.
+ */
 void ENC_SetSelfTestConfig(ENC_Type *base, const enc_self_test_config_t *config)
 {
     uint16_t tmp16 = 0U;
@@ -233,6 +272,12 @@ void ENC_SetSelfTestConfig(ENC_Type *base, const enc_self_test_config_t *config)
     base->TST = tmp16;
 }
 
+/*!
+ * brief Enable watchdog for ENC module.
+ *
+ * param base ENC peripheral base address
+ * param enable Enables or disables the watchdog
+ */
 void ENC_EnableWatchdog(ENC_Type *base, bool enable)
 {
     uint16_t tmp16 = base->CTRL & (uint16_t)(~(ENC_CTRL_W1C_FLAGS | ENC_CTRL_WDE_MASK));
@@ -244,6 +289,13 @@ void ENC_EnableWatchdog(ENC_Type *base, bool enable)
     base->CTRL = tmp16;
 }
 
+/*!
+ * brief  Get the status flags.
+ *
+ * param  base ENC peripheral base address.
+ *
+ * return      Mask value of status flags. For available mask, see to "_enc_status_flags".
+ */
 uint32_t ENC_GetStatusFlags(ENC_Type *base)
 {
     uint32_t ret32 = 0U;
@@ -287,6 +339,12 @@ uint32_t ENC_GetStatusFlags(ENC_Type *base)
     return ret32;
 }
 
+/*!
+ * brief Clear the status flags.
+ *
+ * param base ENC peripheral base address.
+ * param mask Mask value of status flags to be cleared. For available mask, see to "_enc_status_flags".
+ */
 void ENC_ClearStatusFlags(ENC_Type *base, uint32_t mask)
 {
     uint32_t tmp16 = 0U;
@@ -333,6 +391,12 @@ void ENC_ClearStatusFlags(ENC_Type *base, uint32_t mask)
     }
 }
 
+/*!
+ * brief Enable the interrupts.
+ *
+ * param base ENC peripheral base address.
+ * param mask Mask value of interrupts to be enabled. For available mask, see to "_enc_interrupt_enable".
+ */
 void ENC_EnableInterrupts(ENC_Type *base, uint32_t mask)
 {
     uint32_t tmp16 = 0U;
@@ -378,6 +442,12 @@ void ENC_EnableInterrupts(ENC_Type *base, uint32_t mask)
     }
 }
 
+/*!
+ * brief Disable the interrupts.
+ *
+ * param base ENC peripheral base address.
+ * param mask Mask value of interrupts to be disabled. For available mask, see to "_enc_interrupt_enable".
+ */
 void ENC_DisableInterrupts(ENC_Type *base, uint32_t mask)
 {
     uint16_t tmp16 = 0U;
@@ -423,6 +493,13 @@ void ENC_DisableInterrupts(ENC_Type *base, uint32_t mask)
     }
 }
 
+/*!
+ * brief  Get the enabled interrupts' flags.
+ *
+ * param  base ENC peripheral base address.
+ *
+ * return      Mask value of enabled interrupts.
+ */
 uint32_t ENC_GetEnabledInterrupts(ENC_Type *base)
 {
     uint32_t ret32 = 0U;
@@ -460,12 +537,25 @@ uint32_t ENC_GetEnabledInterrupts(ENC_Type *base)
     return ret32;
 }
 
+/*!
+ * brief Set initial position value for ENC module.
+ *
+ * param base ENC peripheral base address
+ * param value Positive initial value
+ */
 void ENC_SetInitialPositionValue(ENC_Type *base, uint32_t value)
 {
     base->UINIT = (uint16_t)(value >> 16U); /* Set upper 16 bits. */
     base->LINIT = (uint16_t)(value);        /* Set lower 16 bits. */
 }
 
+/*!
+ * brief  Get the current position counter's value.
+ *
+ * param  base ENC peripheral base address.
+ *
+ * return     Current position counter's value.
+ */
 uint32_t ENC_GetPositionValue(ENC_Type *base)
 {
     uint32_t ret32;
@@ -477,6 +567,17 @@ uint32_t ENC_GetPositionValue(ENC_Type *base)
     return ret32;
 }
 
+/*!
+ * brief  Get the hold position counter's value.
+ *
+ * When any of the counter registers is read, the contents of each counter register is written to the corresponding hold
+ * register. Taking a snapshot of the counters' values provides a consistent view of a system position and a velocity to
+ * be attained.
+ *
+ * param  base ENC peripheral base address.
+ *
+ * return      Hold position counter's value.
+ */
 uint32_t ENC_GetHoldPositionValue(ENC_Type *base)
 {
     uint32_t ret32;
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_enc.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_enc.h
index 64c4f402da2..badd234cf24 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_enc.h
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_enc.h
@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
  * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #ifndef _FSL_ENC_H_
@@ -51,13 +25,13 @@
  */
 enum _enc_interrupt_enable
 {
-    kENC_HOMETransitionInterruptEnable = (1U << 0U),  /*!< HOME interrupt enable. */
-    kENC_INDEXPulseInterruptEnable = (1U << 1U),      /*!< INDEX pulse interrupt enable. */
+    kENC_HOMETransitionInterruptEnable  = (1U << 0U), /*!< HOME interrupt enable. */
+    kENC_INDEXPulseInterruptEnable      = (1U << 1U), /*!< INDEX pulse interrupt enable. */
     kENC_WatchdogTimeoutInterruptEnable = (1U << 2U), /*!< Watchdog timeout interrupt enable. */
-    kENC_PositionCompareInerruptEnable = (1U << 3U),  /*!< Position compare interrupt enable. */
+    kENC_PositionCompareInerruptEnable  = (1U << 3U), /*!< Position compare interrupt enable. */
     kENC_SimultBothPhaseChangeInterruptEnable =
         (1U << 4U),                                     /*!< Simultaneous PHASEA and PHASEB change interrupt enable. */
-    kENC_PositionRollOverInterruptEnable = (1U << 5U),  /*!< Roll-over interrupt enable. */
+    kENC_PositionRollOverInterruptEnable  = (1U << 5U), /*!< Roll-over interrupt enable. */
     kENC_PositionRollUnderInterruptEnable = (1U << 6U), /*!< Roll-under interrupt enable. */
 };
 
@@ -68,14 +42,14 @@ enum _enc_interrupt_enable
  */
 enum _enc_status_flags
 {
-    kENC_HOMETransitionFlag = (1U << 0U),        /*!< HOME signal transition interrupt request. */
-    kENC_INDEXPulseFlag = (1U << 1U),            /*!< INDEX Pulse Interrupt Request. */
-    kENC_WatchdogTimeoutFlag = (1U << 2U),       /*!< Watchdog timeout interrupt request. */
-    kENC_PositionCompareFlag = (1U << 3U),       /*!< Position compare interrupt request. */
+    kENC_HOMETransitionFlag        = (1U << 0U), /*!< HOME signal transition interrupt request. */
+    kENC_INDEXPulseFlag            = (1U << 1U), /*!< INDEX Pulse Interrupt Request. */
+    kENC_WatchdogTimeoutFlag       = (1U << 2U), /*!< Watchdog timeout interrupt request. */
+    kENC_PositionCompareFlag       = (1U << 3U), /*!< Position compare interrupt request. */
     kENC_SimultBothPhaseChangeFlag = (1U << 4U), /*!< Simultaneous PHASEA and PHASEB change interrupt request. */
-    kENC_PositionRollOverFlag = (1U << 5U),      /*!< Roll-over interrupt request. */
-    kENC_PositionRollUnderFlag = (1U << 6U),     /*!< Roll-under interrupt request. */
-    kENC_LastCountDirectionFlag = (1U << 7U),    /*!< Last count was in the up direction, or the down direction. */
+    kENC_PositionRollOverFlag      = (1U << 5U), /*!< Roll-over interrupt request. */
+    kENC_PositionRollUnderFlag     = (1U << 6U), /*!< Roll-under interrupt request. */
+    kENC_LastCountDirectionFlag    = (1U << 7U), /*!< Last count was in the up direction, or the down direction. */
 };
 
 /*!
@@ -85,14 +59,14 @@ enum _enc_status_flags
  */
 enum _enc_signal_status_flags
 {
-    kENC_RawHOMEStatusFlag = ENC_IMR_HOME_MASK,       /*!< Raw HOME input. */
-    kENC_RawINDEXStatusFlag = ENC_IMR_INDEX_MASK,     /*!< Raw INDEX input. */
-    kENC_RawPHBStatusFlag = ENC_IMR_PHB_MASK,         /*!< Raw PHASEB input. */
-    kENC_RawPHAEXStatusFlag = ENC_IMR_PHA_MASK,       /*!< Raw PHASEA input. */
-    kENC_FilteredHOMEStatusFlag = ENC_IMR_FHOM_MASK,  /*!< The filtered version of HOME input. */
-    kENC_FilteredINDEXStatusFlag = ENC_IMR_FIND_MASK, /*!< The filtered version of INDEX input. */
-    kENC_FilteredPHBStatusFlag = ENC_IMR_FPHB_MASK,   /*!< The filtered version of PHASEB input. */
-    kENC_FilteredPHAStatusFlag = ENC_IMR_FPHA_MASK,   /*!< The filtered version of PHASEA input. */
+    kENC_RawHOMEStatusFlag       = ENC_IMR_HOME_MASK,  /*!< Raw HOME input. */
+    kENC_RawINDEXStatusFlag      = ENC_IMR_INDEX_MASK, /*!< Raw INDEX input. */
+    kENC_RawPHBStatusFlag        = ENC_IMR_PHB_MASK,   /*!< Raw PHASEB input. */
+    kENC_RawPHAEXStatusFlag      = ENC_IMR_PHA_MASK,   /*!< Raw PHASEA input. */
+    kENC_FilteredHOMEStatusFlag  = ENC_IMR_FHOM_MASK,  /*!< The filtered version of HOME input. */
+    kENC_FilteredINDEXStatusFlag = ENC_IMR_FIND_MASK,  /*!< The filtered version of INDEX input. */
+    kENC_FilteredPHBStatusFlag   = ENC_IMR_FPHB_MASK,  /*!< The filtered version of PHASEB input. */
+    kENC_FilteredPHAStatusFlag   = ENC_IMR_FPHA_MASK,  /*!< The filtered version of PHASEA input. */
 };
 
 /*!
@@ -177,7 +151,7 @@ typedef struct _enc_config
     enc_index_trigger_mode_t INDEXTriggerMode; /*!< Enable INDEX to initialize position counters. */
     bool enableTRIGGERClearPositionCounter;    /*!< Clear POSD, REV, UPOS and LPOS on rising edge of TRIGGER, or not. */
     bool enableTRIGGERClearHoldPositionCounter; /*!< Enable update of hold registers on rising edge of TRIGGER, or not.
-                                                   */
+                                                 */
 
     /* Watchdog. */
     bool enableWatchdog;           /*!< Enable the watchdog to detect if the target is moving or not. */
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_enet.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_enet.c
index 5161963c557..46a470b28d6 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_enet.c
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_enet.c
@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
+ * Copyright 2016-2019 NXP
  * All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include "fsl_enet.h"
@@ -136,8 +110,8 @@ typedef void (*enet_isr_ring_t)(ENET_Type *base, enet_handle_t *handle, uint32_t
 typedef void (*enet_isr_t)(ENET_Type *base, enet_handle_t *handle);
 
 /*******************************************************************************
-* Prototypes
-******************************************************************************/
+ * Prototypes
+ ******************************************************************************/
 
 /*!
  * @brief Get the ENET instance from peripheral base address.
@@ -181,7 +155,9 @@ static void ENET_SetHandler(ENET_Type *base,
  * @param config The ENET configuration structure.
  * @param bufferConfig The ENET buffer configuration.
  */
-static void ENET_SetTxBufferDescriptors(enet_handle_t *handle, const enet_config_t *config, const enet_buffer_config_t *bufferConfig);
+static void ENET_SetTxBufferDescriptors(enet_handle_t *handle,
+                                        const enet_config_t *config,
+                                        const enet_buffer_config_t *bufferConfig);
 
 /*!
  * @brief Set ENET MAC receive buffer descriptors.
@@ -190,7 +166,9 @@ static void ENET_SetTxBufferDescriptors(enet_handle_t *handle, const enet_config
  * @param config The ENET configuration structure.
  * @param bufferConfig The ENET buffer configuration.
  */
-static void ENET_SetRxBufferDescriptors(enet_handle_t *handle, const enet_config_t *config, const enet_buffer_config_t *bufferConfig);
+static void ENET_SetRxBufferDescriptors(enet_handle_t *handle,
+                                        const enet_config_t *config,
+                                        const enet_buffer_config_t *bufferConfig);
 
 /*!
  * @brief Updates the ENET read buffer descriptors.
@@ -338,6 +316,20 @@ uint32_t ENET_GetInstance(ENET_Type *base)
     return instance;
 }
 
+/*!
+ * brief Gets the ENET default configuration structure.
+ *
+ * The purpose of this API is to get the default ENET MAC controller
+ * configure structure for ENET_Init(). User may use the initialized
+ * structure unchanged in ENET_Init(), or modify some fields of the
+ * structure before calling ENET_Init().
+ * Example:
+   code
+   enet_config_t config;
+   ENET_GetDefaultConfig(&config);
+   endcode
+ * param config The ENET mac controller configuration structure pointer.
+ */
 void ENET_GetDefaultConfig(enet_config_t *config)
 {
     /* Checks input parameter. */
@@ -346,7 +338,7 @@ void ENET_GetDefaultConfig(enet_config_t *config)
     /* Initializes the MAC configure structure to zero. */
     memset(config, 0, sizeof(enet_config_t));
 
-    /* Sets MII mode, full duplex, 100Mbps for MAC and PHY data interface. */
+/* Sets MII mode, full duplex, 100Mbps for MAC and PHY data interface. */
 #if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB
     config->miiMode = kENET_RgmiiMode;
 #else
@@ -361,6 +353,33 @@ void ENET_GetDefaultConfig(enet_config_t *config)
     config->rxMaxFrameLen = ENET_FRAME_MAX_FRAMELEN;
 }
 
+/*!
+ * brief Initializes the ENET module.
+ *
+ * This function ungates the module clock and initializes it with the ENET configuration.
+ *
+ * param base    ENET peripheral base address.
+ * param handle  ENET handler pointer.
+ * param config  ENET mac configuration structure pointer.
+ *        The "enet_config_t" type mac configuration return from ENET_GetDefaultConfig
+ *        can be used directly. It is also possible to verify the Mac configuration using other methods.
+ * param bufferConfig  ENET buffer configuration structure pointer.
+ *        The buffer configuration should be prepared for ENET Initialization.
+ *        It is the start address of "ringNum" enet_buffer_config structures.
+ *        To support added multi-ring features in some soc and compatible with the previous
+ *        enet driver version. For single ring supported, this bufferConfig is a buffer
+ *        configure structure pointer, for multi-ring supported and used case, this bufferConfig
+ *        pointer should be a buffer configure structure array pointer.
+ * param macAddr  ENET mac address of Ethernet device. This MAC address should be
+ *        provided.
+ * param srcClock_Hz The internal module clock source for MII clock.
+ *
+ * note ENET has two buffer descriptors legacy buffer descriptors and
+ * enhanced IEEE 1588 buffer descriptors. The legacy descriptor is used by default. To
+ * use the IEEE 1588 feature, use the enhanced IEEE 1588 buffer descriptor
+ * by defining "ENET_ENHANCEDBUFFERDESCRIPTOR_MODE" and calling ENET_Ptp1588Configure()
+ * to configure the 1588 feature and related buffers after calling ENET_Init().
+ */
 void ENET_Init(ENET_Type *base,
                enet_handle_t *handle,
                const enet_config_t *config,
@@ -397,6 +416,13 @@ void ENET_Init(ENET_Type *base,
     ENET_SetHandler(base, handle, config, bufferConfig);
 }
 
+/*!
+ * brief Deinitializes the ENET module.
+
+ * This function gates the module clock, clears ENET interrupts, and disables the ENET module.
+ *
+ * param base  ENET peripheral base address.
+ */
 void ENET_Deinit(ENET_Type *base)
 {
     /* Disable interrupt. */
@@ -405,13 +431,21 @@ void ENET_Deinit(ENET_Type *base)
     /* Disable ENET. */
     base->ECR &= ~ENET_ECR_ETHEREN_MASK;
 
-
 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* Disables the clock source. */
     CLOCK_DisableClock(s_enetClock[ENET_GetInstance(base)]);
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }
 
+/*!
+ * brief Sets the callback function.
+ * This API is provided for the application callback required case when ENET
+ * interrupt is enabled. This API should be called after calling ENET_Init.
+ *
+ * param handle ENET handler pointer. Should be provided by application.
+ * param callback The ENET callback function.
+ * param userData The callback function parameter.
+ */
 void ENET_SetCallback(enet_handle_t *handle, enet_callback_t callback, void *userData)
 {
     assert(handle);
@@ -607,7 +641,7 @@ static void ENET_SetMacController(ENET_Type *base,
         base->RSFL = 0;
     }
 
-    /* Initializes the ring 0. */
+/* Initializes the ring 0. */
 #if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET
     base->TDSR = MEMORY_ConvertMemoryMapAddress((uint32_t)bufferConfig->txBdStartAddrAlign, kMEMORY_Local2DMA);
     base->RDSR = MEMORY_ConvertMemoryMapAddress((uint32_t)bufferConfig->rxBdStartAddrAlign, kMEMORY_Local2DMA);
@@ -711,7 +745,9 @@ static void ENET_SetMacController(ENET_Type *base,
     base->ECR = ecr;
 }
 
-static void ENET_SetTxBufferDescriptors(enet_handle_t *handle, const enet_config_t *config, const enet_buffer_config_t *bufferConfig)
+static void ENET_SetTxBufferDescriptors(enet_handle_t *handle,
+                                        const enet_config_t *config,
+                                        const enet_buffer_config_t *bufferConfig)
 {
     assert(config);
     assert(bufferConfig);
@@ -765,7 +801,9 @@ static void ENET_SetTxBufferDescriptors(enet_handle_t *handle, const enet_config
     }
 }
 
-static void ENET_SetRxBufferDescriptors(enet_handle_t *handle, const enet_config_t *config, const enet_buffer_config_t *bufferConfig)
+static void ENET_SetRxBufferDescriptors(enet_handle_t *handle,
+                                        const enet_config_t *config,
+                                        const enet_buffer_config_t *bufferConfig)
 {
     assert(config);
     assert(bufferConfig);
@@ -849,6 +887,9 @@ static void ENET_ActiveSend(ENET_Type *base, uint32_t ringId)
 {
     assert(ringId < FSL_FEATURE_ENET_QUEUE);
 
+    /* Ensure previous data update is completed with Data Synchronization Barrier before activing Tx BD. */
+    __DSB();
+
     switch (ringId)
     {
         case kENET_Ring0:
@@ -868,6 +909,15 @@ static void ENET_ActiveSend(ENET_Type *base, uint32_t ringId)
     }
 }
 
+/*!
+ * brief Sets the ENET MII speed and duplex.
+ *
+ * This API is provided to dynamically change the speed and dulpex for MAC.
+ *
+ * param base  ENET peripheral base address.
+ * param speed The speed of the RMII mode.
+ * param duplex The duplex of the RMII mode.
+ */
 void ENET_SetMII(ENET_Type *base, enet_mii_speed_t speed, enet_mii_duplex_t duplex)
 {
     uint32_t rcr = base->RCR;
@@ -914,6 +964,13 @@ void ENET_SetMII(ENET_Type *base, enet_mii_speed_t speed, enet_mii_duplex_t dupl
     base->TCR = tcr;
 }
 
+/*!
+ * brief Sets the ENET module Mac address.
+ *
+ * param base  ENET peripheral base address.
+ * param macAddr The six-byte Mac address pointer.
+ *        The pointer is allocated by application and input into the API.
+ */
 void ENET_SetMacAddr(ENET_Type *base, uint8_t *macAddr)
 {
     uint32_t address;
@@ -927,6 +984,13 @@ void ENET_SetMacAddr(ENET_Type *base, uint8_t *macAddr)
     base->PAUR = address << ENET_PAUR_PADDR2_SHIFT;
 }
 
+/*!
+ * brief Gets the ENET module Mac address.
+ *
+ * param base  ENET peripheral base address.
+ * param macAddr The six-byte Mac address pointer.
+ *        The pointer is allocated by application and input into the API.
+ */
 void ENET_GetMacAddr(ENET_Type *base, uint8_t *macAddr)
 {
     assert(macAddr);
@@ -946,6 +1010,15 @@ void ENET_GetMacAddr(ENET_Type *base, uint8_t *macAddr)
     macAddr[5] = 0xFFU & address;
 }
 
+/*!
+ * brief Sets the ENET SMI(serial management interface)- MII management interface.
+ *
+ * param base  ENET peripheral base address.
+ * param srcClock_Hz This is the ENET module clock frequency. Normally it's the system clock. See clock distribution.
+ * param isPreambleDisabled The preamble disable flag.
+ *        - true   Enables the preamble.
+ *        - false  Disables the preamble.
+ */
 void ENET_SetSMI(ENET_Type *base, uint32_t srcClock_Hz, bool isPreambleDisabled)
 {
     assert(srcClock_Hz);
@@ -959,10 +1032,22 @@ void ENET_SetSMI(ENET_Type *base, uint32_t srcClock_Hz, bool isPreambleDisabled)
     /* Calculate the hold time on the MDIO output. */
     clkCycle = (10 + ENET_NANOSECOND_ONE_SECOND / srcClock_Hz - 1) / (ENET_NANOSECOND_ONE_SECOND / srcClock_Hz) - 1;
     /* Build the configuration for MDC/MDIO control. */
-    mscr = ENET_MSCR_MII_SPEED(speed) | ENET_MSCR_HOLDTIME(clkCycle) | (isPreambleDisabled ? ENET_MSCR_DIS_PRE_MASK : 0);
+    mscr =
+        ENET_MSCR_MII_SPEED(speed) | ENET_MSCR_HOLDTIME(clkCycle) | (isPreambleDisabled ? ENET_MSCR_DIS_PRE_MASK : 0);
     base->MSCR = mscr;
 }
 
+/*!
+ * brief Starts an SMI write command.
+ *
+ * Used for standard IEEE802.3 MDIO Clause 22 format.
+ *
+ * param base  ENET peripheral base address.
+ * param phyAddr The PHY address.
+ * param phyReg The PHY register. Range from 0 ~ 31.
+ * param operation The write operation.
+ * param data The data written to PHY.
+ */
 void ENET_StartSMIWrite(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, enet_mii_write_t operation, uint32_t data)
 {
     uint32_t mmfr = 0;
@@ -973,6 +1058,16 @@ void ENET_StartSMIWrite(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, enet
     base->MMFR = mmfr;
 }
 
+/*!
+ * brief Starts an SMI (Serial Management Interface) read command.
+ *
+ * Used for standard IEEE802.3 MDIO Clause 22 format.
+ *
+ * param base  ENET peripheral base address.
+ * param phyAddr The PHY address.
+ * param phyReg The PHY register. Range from 0 ~ 31.
+ * param operation The read operation.
+ */
 void ENET_StartSMIRead(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, enet_mii_read_t operation)
 {
     uint32_t mmfr = 0;
@@ -983,6 +1078,16 @@ void ENET_StartSMIRead(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, enet_
 }
 
 #if defined(FSL_FEATURE_ENET_HAS_EXTEND_MDIO) && FSL_FEATURE_ENET_HAS_EXTEND_MDIO
+/*!
+ * brief Starts the extended IEEE802.3 Clause 45 MDIO format SMI write command.
+ *
+ * param base  ENET peripheral base address.
+ * param phyAddr The PHY address.
+ * param phyReg The PHY register. For MDIO IEEE802.3 Clause 45,
+ *        the phyReg is a 21-bits combination of the devaddr (5 bits device address)
+ *        and the regAddr (16 bits phy register): phyReg = (devaddr << 16) | regAddr.
+ * param data The data written to PHY.
+ */
 void ENET_StartExtC45SMIWrite(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t data)
 {
     uint32_t mmfr = 0;
@@ -1002,6 +1107,15 @@ void ENET_StartExtC45SMIWrite(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg
     base->MMFR = mmfr;
 }
 
+/*!
+ * brief Starts the extended IEEE802.3 Clause 45 MDIO format SMI read command.
+ *
+ * param base  ENET peripheral base address.
+ * param phyAddr The PHY address.
+ * param phyReg The PHY register. For MDIO IEEE802.3 Clause 45,
+ *        the phyReg is a 21-bits combination of the devaddr (5 bits device address)
+ *        and the regAddr (16 bits phy register): phyReg = (devaddr << 16) | regAddr.
+ */
 void ENET_StartExtC45SMIRead(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg)
 {
     uint32_t mmfr = 0;
@@ -1022,6 +1136,26 @@ void ENET_StartExtC45SMIRead(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg)
 }
 #endif /* FSL_FEATURE_ENET_HAS_EXTEND_MDIO */
 
+/*!
+ * brief Gets the error statistics of a received frame for ENET single ring.
+ *
+ * This API must be called after the ENET_GetRxFrameSize and before the ENET_ReadFrame().
+ * If the ENET_GetRxFrameSize returns kStatus_ENET_RxFrameError,
+ * the ENET_GetRxErrBeforeReadFrame can be used to get the exact error statistics.
+ * This is an example.
+ * code
+ *       status = ENET_GetRxFrameSize(&g_handle, &length);
+ *       if (status == kStatus_ENET_RxFrameError)
+ *       {
+ *           // Get the error information of the received frame.
+ *           ENET_GetRxErrBeforeReadFrame(&g_handle, &eErrStatic);
+ *           // update the receive buffer.
+ *           ENET_ReadFrame(EXAMPLE_ENET, &g_handle, NULL, 0);
+ *       }
+ * endcode
+ * param handle The ENET handler structure pointer. This is the same handler pointer used in the ENET_Init.
+ * param eErrorStatic The error statistics structure pointer.
+ */
 void ENET_GetRxErrBeforeReadFrame(enet_handle_t *handle, enet_data_error_stats_t *eErrorStatic)
 {
     assert(handle);
@@ -1097,6 +1231,22 @@ void ENET_GetRxErrBeforeReadFrame(enet_handle_t *handle, enet_data_error_stats_t
     } while (curBuffDescrip != handle->rxBdCurrent[0]);
 }
 
+/*!
+ * brief Gets the size of the read frame for single ring.
+ *
+ * This function gets a received frame size from the ENET buffer descriptors.
+ * note The FCS of the frame is automatically removed by MAC and the size is the length without the FCS.
+ * After calling ENET_GetRxFrameSize, ENET_ReadFrame() should be called to update the
+ * receive buffers If the result is not "kStatus_ENET_RxFrameEmpty".
+ *
+ * param handle The ENET handler structure. This is the same handler pointer used in the ENET_Init.
+ * param length The length of the valid frame received.
+ * retval kStatus_ENET_RxFrameEmpty No frame received. Should not call ENET_ReadFrame to read frame.
+ * retval kStatus_ENET_RxFrameError Data error happens. ENET_ReadFrame should be called with NULL data
+ *         and NULL length to update the receive buffers.
+ * retval kStatus_Success Receive a frame Successfully then the ENET_ReadFrame
+ *         should be called with the right data buffer and the captured data length input.
+ */
 status_t ENET_GetRxFrameSize(enet_handle_t *handle, uint32_t *length)
 {
     assert(handle);
@@ -1155,6 +1305,43 @@ status_t ENET_GetRxFrameSize(enet_handle_t *handle, uint32_t *length)
     return kStatus_ENET_RxFrameEmpty;
 }
 
+/*!
+ * brief Reads a frame from the ENET device for single ring.
+ * This function reads a frame (both the data and the length) from the ENET buffer descriptors.
+ * The ENET_GetRxFrameSize should be used to get the size of the prepared data buffer.
+ * This is an example:
+ * code
+ *       uint32_t length;
+ *       enet_handle_t g_handle;
+ *       //Get the received frame size firstly.
+ *       status = ENET_GetRxFrameSize(&g_handle, &length);
+ *       if (length != 0)
+ *       {
+ *           //Allocate memory here with the size of "length"
+ *           uint8_t *data = memory allocate interface;
+ *           if (!data)
+ *           {
+ *               ENET_ReadFrame(ENET, &g_handle, NULL, 0);
+ *               //Add the console warning log.
+ *           }
+ *           else
+ *           {
+ *              status = ENET_ReadFrame(ENET, &g_handle, data, length);
+ *              //Call stack input API to deliver the data to stack
+ *           }
+ *       }
+ *       else if (status == kStatus_ENET_RxFrameError)
+ *       {
+ *          //Update the received buffer when a error frame is received.
+ *           ENET_ReadFrame(ENET, &g_handle, NULL, 0);
+ *       }
+ * endcode
+ * param base  ENET peripheral base address.
+ * param handle The ENET handler structure. This is the same handler pointer used in the ENET_Init.
+ * param data The data buffer provided by user to store the frame which memory size should be at least "length".
+ * param length The size of the data buffer which is still the length of the received frame.
+ * return The execute status, successful or failure.
+ */
 status_t ENET_ReadFrame(ENET_Type *base, enet_handle_t *handle, uint8_t *data, uint32_t length)
 {
     assert(handle);
@@ -1190,9 +1377,9 @@ status_t ENET_ReadFrame(ENET_Type *base, enet_handle_t *handle, uint8_t *data, u
     }
     else
     {
-        /* A frame on one buffer or several receive buffers are both considered. */
+/* A frame on one buffer or several receive buffers are both considered. */
 #if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET
-        address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local);
+        address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer, kMEMORY_DMA2Local);
 #else
         address = (uint32_t)curBuffDescrip->buffer;
 #endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */
@@ -1258,9 +1445,9 @@ status_t ENET_ReadFrame(ENET_Type *base, enet_handle_t *handle, uint8_t *data, u
 
             /* Get the current buffer descriptor. */
             curBuffDescrip = handle->rxBdCurrent[0];
-            /* Add the cache invalidate maintain. */
+/* Add the cache invalidate maintain. */
 #if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET
-            address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local);
+            address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer, kMEMORY_DMA2Local);
 #else
             address = (uint32_t)curBuffDescrip->buffer;
 #endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */
@@ -1293,6 +1480,9 @@ static void ENET_UpdateReadBuffers(ENET_Type *base, enet_handle_t *handle, uint3
         handle->rxBdCurrent[ringId]++;
     }
 
+    /* Ensure previous data update is completed with Data Synchronization Barrier before activing Rx BD. */
+    __DSB();
+
     /* Actives the receive buffer descriptor. */
     switch (ringId)
     {
@@ -1313,6 +1503,22 @@ static void ENET_UpdateReadBuffers(ENET_Type *base, enet_handle_t *handle, uint3
     }
 }
 
+/*!
+ * brief Transmits an ENET frame for single ring.
+ * note The CRC is automatically appended to the data. Input the data
+ * to send without the CRC.
+ *
+ *
+ * param base  ENET peripheral base address.
+ * param handle The ENET handler pointer. This is the same handler pointer used in the ENET_Init.
+ * param data The data buffer provided by user to be send.
+ * param length The length of the data to be send.
+ * retval kStatus_Success  Send frame succeed.
+ * retval kStatus_ENET_TxFrameBusy  Transmit buffer descriptor is busy under transmission.
+ *         The transmit busy happens when the data send rate is over the MAC capacity.
+ *         The waiting mechanism is recommended to be added after each call return with
+ *         kStatus_ENET_TxFrameBusy.
+ */
 status_t ENET_SendFrame(ENET_Type *base, enet_handle_t *handle, const uint8_t *data, uint32_t length)
 {
     assert(handle);
@@ -1343,9 +1549,9 @@ status_t ENET_SendFrame(ENET_Type *base, enet_handle_t *handle, const uint8_t *d
     /* One transmit buffer is enough for one frame. */
     if (handle->txBuffSizeAlign[0] >= length)
     {
-        /* Copy data to the buffer for uDMA transfer. */
+/* Copy data to the buffer for uDMA transfer. */
 #if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET
-        address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local);
+        address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer, kMEMORY_DMA2Local);
 #else
         address = (uint32_t)curBuffDescrip->buffer;
 #endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */
@@ -1412,7 +1618,7 @@ status_t ENET_SendFrame(ENET_Type *base, enet_handle_t *handle, const uint8_t *d
             /* update the size left to be transmit. */
             sizeleft = length - len;
 #if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET
-            address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local);
+            address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer, kMEMORY_DMA2Local);
 #else
             address = (uint32_t)curBuffDescrip->buffer;
 #endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */
@@ -1435,7 +1641,6 @@ status_t ENET_SendFrame(ENET_Type *base, enet_handle_t *handle, const uint8_t *d
             }
             else
             {
-
                 memcpy((void *)address, data + len, sizeleft);
 #if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL
                 /* Add the cache clean maintain. */
@@ -1460,6 +1665,17 @@ status_t ENET_SendFrame(ENET_Type *base, enet_handle_t *handle, const uint8_t *d
 }
 
 #if FSL_FEATURE_ENET_QUEUE > 1
+/*!
+ * brief Gets the error statistics of received frame for extended multi-ring.
+ *
+ * This API must be called after the ENET_GetRxFrameSizeMultiRing and before the ENET_ReadFrameMultiRing().
+ * If the ENET_GetRxFrameSizeMultiRing returns kStatus_ENET_RxFrameError,
+ * the ENET_GetRxErrBeforeReadFrameMultiRing can be used to get the exact error statistics.
+ *
+ * param handle The ENET handler structure pointer. This is the same handler pointer used in the ENET_Init.
+ * param eErrorStatic The error statistics structure pointer.
+ * param ringId The ring index, range from 0 ~ FSL_FEATURE_ENET_QUEUE - 1.
+ */
 void ENET_GetRxErrBeforeReadFrameMultiRing(enet_handle_t *handle,
                                            enet_data_error_stats_t *eErrorStatic,
                                            uint32_t ringId)
@@ -1537,6 +1753,24 @@ void ENET_GetRxErrBeforeReadFrameMultiRing(enet_handle_t *handle,
     } while (curBuffDescrip != handle->rxBdCurrent[ringId]);
 }
 
+/*!
+ * brief Gets the size of the read frame for extended mutli-ring.
+ *
+ * This function gets a received frame size from the ENET buffer descriptors.
+ * note The FCS of the frame is automatically removed by MAC and the size is the length without the FCS.
+ * After calling ENET_GetRxFrameSizeMultiRing, ENET_ReadFrameMultiRing() should be called to update the
+ * receive buffers If the result is not "kStatus_ENET_RxFrameEmpty". The usage is
+ * the same to the single ring, refer to ENET_GetRxFrameSize.
+ *
+ * param handle The ENET handler structure. This is the same handler pointer used in the ENET_Init.
+ * param length The length of the valid frame received.
+ * param ringId The ring index or ring number;
+ * retval kStatus_ENET_RxFrameEmpty No frame received. Should not call ENET_ReadFrameMultiRing to read frame.
+ * retval kStatus_ENET_RxFrameError Data error happens. ENET_ReadFrameMultiRing should be called with NULL data
+ *         and NULL length to update the receive buffers.
+ * retval kStatus_Success Receive a frame Successfully then the ENET_ReadFrame
+ *         should be called with the right data buffer and the captured data length input.
+ */
 status_t ENET_GetRxFrameSizeMultiRing(enet_handle_t *handle, uint32_t *length, uint32_t ringId)
 {
     assert(handle);
@@ -1593,6 +1827,20 @@ status_t ENET_GetRxFrameSizeMultiRing(enet_handle_t *handle, uint32_t *length, u
     return kStatus_ENET_RxFrameEmpty;
 }
 
+/*!
+ * brief Reads a frame from the ENET device for multi-ring.
+ *
+ * This function reads a frame (both the data and the length) from the ENET buffer descriptors.
+ * The ENET_GetRxFrameSizeMultiRing should be used to get the size of the prepared data buffer.
+ * This usage is the same as the single ring, refer to ENET_ReadFrame.
+
+ * param base  ENET peripheral base address.
+ * param handle The ENET handler structure. This is the same handler pointer used in the ENET_Init.
+ * param data The data buffer provided by user to store the frame which memory size should be at least "length".
+ * param length The size of the data buffer which is still the length of the received frame.
+ * param ringId The ring index or ring number;
+ * return The execute status, successful or failure.
+ */
 status_t ENET_ReadFrameMultiRing(
     ENET_Type *base, enet_handle_t *handle, uint8_t *data, uint32_t length, uint32_t ringId)
 {
@@ -1629,9 +1877,9 @@ status_t ENET_ReadFrameMultiRing(
     }
     else
     {
-        /* A frame on one buffer or several receive buffers are both considered. */
+/* A frame on one buffer or several receive buffers are both considered. */
 #if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET
-        address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local);
+        address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer, kMEMORY_DMA2Local);
 #else
         address = (uint32_t)curBuffDescrip->buffer;
 #endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */
@@ -1690,7 +1938,6 @@ status_t ENET_ReadFrameMultiRing(
                 memcpy(data + offset, (void *)address, handle->rxBuffSizeAlign[ringId]);
                 offset += handle->rxBuffSizeAlign[ringId];
 
-
                 /* Updates the receive buffer descriptors. */
                 ENET_UpdateReadBuffers(base, handle, ringId);
             }
@@ -1699,7 +1946,7 @@ status_t ENET_ReadFrameMultiRing(
 
             curBuffDescrip = handle->rxBdCurrent[ringId];
 #if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET
-            address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local);
+            address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer, kMEMORY_DMA2Local);
 #else
             address = (uint32_t)curBuffDescrip->buffer;
 #endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */
@@ -1713,7 +1960,27 @@ status_t ENET_ReadFrameMultiRing(
     return kStatus_ENET_RxFrameFail;
 }
 
-
+/*!
+ * brief Transmits an ENET frame for extended multi-ring.
+ * note The CRC is automatically appended to the data. Input the data
+ * to send without the CRC.
+ *
+ * In this API, multiple-ring are mainly used for extended avb frames are supported.
+ * The transmit scheme for avb frames is the credit-based scheme, the AVB class A, AVB class B
+ * and the non-AVB frame are transmitted in ring 1, ring 2 and ring 0 independently.
+ * So application should care about the transmit ring index when use multiple-ring transmission.
+ *
+ * param base  ENET peripheral base address.
+ * param handle The ENET handler pointer. This is the same handler pointer used in the ENET_Init.
+ * param data The data buffer provided by user to be send.
+ * param length The length of the data to be send.
+ * param ringId The ring index for transmission.
+ * retval kStatus_Success  Send frame succeed.
+ * retval kStatus_ENET_TxFrameBusy  Transmit buffer descriptor is busy under transmission.
+ *         The transmit busy happens when the data send rate is over the MAC capacity.
+ *         The waiting mechanism is recommended to be added after each call return with
+ *         kStatus_ENET_TxFrameBusy.
+ */
 status_t ENET_SendFrameMultiRing(
     ENET_Type *base, enet_handle_t *handle, uint8_t *data, uint32_t length, uint32_t ringId)
 {
@@ -1746,9 +2013,9 @@ status_t ENET_SendFrameMultiRing(
     /* One transmit buffer is enough for one frame. */
     if (handle->txBuffSizeAlign[ringId] >= length)
     {
-        /* Copy data to the buffer for uDMA transfer. */
+/* Copy data to the buffer for uDMA transfer. */
 #if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET
-        address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local);
+        address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer, kMEMORY_DMA2Local);
 #else
         address = (uint32_t)curBuffDescrip->buffer;
 #endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */
@@ -1819,14 +2086,14 @@ status_t ENET_SendFrameMultiRing(
             /* update the size left to be transmit. */
             sizeleft = length - len;
 #if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET
-            address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local);
+            address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer, kMEMORY_DMA2Local);
 #else
             address = (uint32_t)curBuffDescrip->buffer;
 #endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */
             if (sizeleft > handle->txBuffSizeAlign[ringId])
             {
                 /* Data copy. */
-                memcpy((void*)address, data + len, handle->txBuffSizeAlign[ringId]);
+                memcpy((void *)address, data + len, handle->txBuffSizeAlign[ringId]);
 #if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL
                 /* Add the cache clean maintain. */
                 DCACHE_CleanByRange(address, handle->txBuffSizeAlign[ringId]);
@@ -1843,7 +2110,6 @@ status_t ENET_SendFrameMultiRing(
             }
             else
             {
-
                 memcpy((void *)address, data + len, sizeleft);
 #if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL
                 /* Add the cache clean maintain. */
@@ -1868,6 +2134,12 @@ status_t ENET_SendFrameMultiRing(
 }
 #endif /*  FSL_FEATURE_ENET_QUEUE > 1 */
 
+/*!
+ * brief Adds the ENET device to a multicast group.
+ *
+ * param base    ENET peripheral base address.
+ * param address The six-byte multicast group address which is provided by application.
+ */
 void ENET_AddMulticastGroup(ENET_Type *base, uint8_t *address)
 {
     assert(address);
@@ -1907,6 +2179,12 @@ void ENET_AddMulticastGroup(ENET_Type *base, uint8_t *address)
     }
 }
 
+/*!
+ * brief Moves the ENET device from a multicast group.
+ *
+ * param base  ENET peripheral base address.
+ * param address The six-byte multicast group address which is provided by application.
+ */
 void ENET_LeaveMulticastGroup(ENET_Type *base, uint8_t *address)
 {
     assert(address);
@@ -1947,6 +2225,19 @@ void ENET_LeaveMulticastGroup(ENET_Type *base, uint8_t *address)
 }
 
 #ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE
+/*!
+ * brief Gets the ENET transmit frame statistics after the data send for single ring.
+ *
+ * This interface gets the error statistics of the transmit frame.
+ * Because the error information is reported by the uDMA after the data delivery, this interface
+ * should be called after the data transmit API. It is recommended to call this function on
+ * transmit interrupt handler. After calling the ENET_SendFrame, the
+ * transmit interrupt notifies the transmit completion.
+ *
+ * param handle The PTP handler pointer. This is the same handler pointer used in the ENET_Init.
+ * param eErrorStatic The error statistics structure pointer.
+ * return The execute status.
+ */
 status_t ENET_GetTxErrAfterSendFrame(enet_handle_t *handle, enet_data_error_stats_t *eErrorStatic)
 {
     assert(handle);
@@ -2013,7 +2304,21 @@ status_t ENET_GetTxErrAfterSendFrame(enet_handle_t *handle, enet_data_error_stat
 }
 
 #if FSL_FEATURE_ENET_QUEUE > 1
-status_t ENET_GetTxErrAfterSendFrameMultiRing(enet_handle_t *handle, enet_data_error_stats_t *eErrorStatic,
+/*!
+ * brief Gets the ENET transmit frame statistics after the data send for extended multi-ring.
+ *
+ * This interface gets the error statistics of the transmit frame.
+ * Because the error information is reported by the uDMA after the data delivery, this interface
+ * should be called after the data transmit API and shall be called by transmit interrupt handler.
+ * After calling the ENET_SendFrame, the transmit interrupt notifies the transmit completion.
+ *
+ * param handle The PTP handler pointer. This is the same handler pointer used in the ENET_Init.
+ * param eErrorStatic The error statistics structure pointer.
+ * param ringId The ring index.
+ * return The execute status.
+ */
+status_t ENET_GetTxErrAfterSendFrameMultiRing(enet_handle_t *handle,
+                                              enet_data_error_stats_t *eErrorStatic,
                                                                              uint32_t ringId)
 {
     assert(handle);
@@ -2177,6 +2482,22 @@ static bool ENET_Ptp1588ParseFrame(const uint8_t *data, enet_ptp_time_data_t *pt
     return isPtpMsg;
 }
 
+/*!
+ * brief Configures the ENET PTP IEEE 1588 feature with the basic configuration.
+ * The function sets the clock for PTP 1588 timer and enables
+ * time stamp interrupts and transmit interrupts for PTP 1588 features.
+ * This API should be called when the 1588 feature is enabled
+ * or the ENET_ENHANCEDBUFFERDESCRIPTOR_MODE is defined.
+ * ENET_Init should be called before calling this API.
+ *
+ * note The PTP 1588 time-stamp second increase though time-stamp interrupt handler
+ *  and the transmit time-stamp store is done through transmit interrupt handler.
+ *  As a result, the TS interrupt and TX interrupt are enabled when you call this API.
+ *
+ * param base    ENET peripheral base address.
+ * param handle  ENET handler pointer.
+ * param ptpConfig The ENET PTP1588 configuration.
+ */
 void ENET_Ptp1588Configure(ENET_Type *base, enet_handle_t *handle, enet_ptp_config_t *ptpConfig)
 {
     assert(handle);
@@ -2222,6 +2543,14 @@ void ENET_Ptp1588Configure(ENET_Type *base, enet_handle_t *handle, enet_ptp_conf
     EnableIRQ(s_enetTxIrqId[instance]);
 }
 
+/*!
+ * brief Starts the ENET PTP 1588 Timer.
+ * This function is used to initialize the PTP timer. After the PTP starts,
+ * the PTP timer starts running.
+ *
+ * param base  ENET peripheral base address.
+ * param ptpClkSrc The clock source of the PTP timer.
+ */
 void ENET_Ptp1588StartTimer(ENET_Type *base, uint32_t ptpClkSrc)
 {
     /* Restart PTP 1588 timer, master clock. */
@@ -2234,6 +2563,13 @@ void ENET_Ptp1588StartTimer(ENET_Type *base, uint32_t ptpClkSrc)
     base->ATCR = ENET_ATCR_PEREN_MASK | ENET_ATCR_PINPER_MASK | ENET_ATCR_EN_MASK;
 }
 
+/*!
+ * brief Gets the current ENET time from the PTP 1588 timer.
+ *
+ * param base  ENET peripheral base address.
+ * param handle The ENET state pointer. This is the same state pointer used in the ENET_Init.
+ * param ptpTime The PTP timer structure.
+ */
 void ENET_Ptp1588GetTimer(ENET_Type *base, enet_handle_t *handle, enet_ptp_time_t *ptpTime)
 {
     assert(handle);
@@ -2259,10 +2595,23 @@ void ENET_Ptp1588GetTimer(ENET_Type *base, enet_handle_t *handle, enet_ptp_time_
     /* Get the captured time. */
     ptpTime->nanosecond = base->ATVR;
 
+    /* Get PTP timer wrap event. */
+    if (base->EIR & kENET_TsTimerInterrupt)
+    {
+        ptpTime->second++;
+    }
+
     /* Enables the interrupt. */
     EnableGlobalIRQ(primask);
 }
 
+/*!
+ * brief Sets the ENET PTP 1588 timer to the assigned time.
+ *
+ * param base  ENET peripheral base address.
+ * param handle The ENET state pointer. This is the same state pointer used in the ENET_Init.
+ * param ptpTime The timer to be set to the PTP timer.
+ */
 void ENET_Ptp1588SetTimer(ENET_Type *base, enet_handle_t *handle, enet_ptp_time_t *ptpTime)
 {
     assert(handle);
@@ -2281,6 +2630,17 @@ void ENET_Ptp1588SetTimer(ENET_Type *base, enet_handle_t *handle, enet_ptp_time_
     EnableGlobalIRQ(primask);
 }
 
+/*!
+ * brief Adjusts the ENET PTP 1588 timer.
+ *
+ * param base  ENET peripheral base address.
+ * param corrIncrease The correction increment value. This value is added every time the correction
+ *       timer expires. A value less than the PTP timer frequency(1/ptpClkSrc) slows down the timer,
+ *        a value greater than the 1/ptpClkSrc speeds up the timer.
+ * param corrPeriod The PTP timer correction counter wrap-around value. This defines after how
+ *       many timer clock the correction counter should be reset and trigger a correction
+ *       increment on the timer. A value of 0 disables the correction counter and no correction occurs.
+ */
 void ENET_Ptp1588AdjustTimer(ENET_Type *base, uint32_t corrIncrease, uint32_t corrPeriod)
 {
     /* Set correction for PTP timer increment. */
@@ -2307,9 +2667,10 @@ static status_t ENET_Ptp1588UpdateTimeRing(enet_ptp_time_data_ring_t *ptpTsDataR
         usedBuffer = ptpTsDataRing->size - (ptpTsDataRing->front - ptpTsDataRing->end);
     }
 
-    if (usedBuffer == ptpTsDataRing->size)
+    if (usedBuffer == (ptpTsDataRing->size - 1))
     {
-        return kStatus_ENET_PtpTsRingFull;
+        /* Ptp timestamp ring full, drop one in the front. */
+        ptpTsDataRing->front = (ptpTsDataRing->front + 1) % ptpTsDataRing->size;
     }
 
     /* Copy the new data into the buffer. */
@@ -2330,6 +2691,7 @@ static status_t ENET_Ptp1588SearchTimeRing(enet_ptp_time_data_ring_t *ptpTsDataR
     uint32_t index;
     uint32_t size;
     uint16_t usedBuffer = 0;
+    bool isRingBufferFull = false;
 
     /* Check the PTP 1588 timestamp ring. */
     if (ptpTsDataRing->front == ptpTsDataRing->end)
@@ -2337,6 +2699,21 @@ static status_t ENET_Ptp1588SearchTimeRing(enet_ptp_time_data_ring_t *ptpTsDataR
         return kStatus_ENET_PtpTsRingEmpty;
     }
 
+    /* Check if buffers is full. */
+    if (ptpTsDataRing->end >= ptpTsDataRing->front)
+    {
+        usedBuffer = ptpTsDataRing->end - ptpTsDataRing->front;
+    }
+    else
+    {
+        usedBuffer = ptpTsDataRing->size - (ptpTsDataRing->front - ptpTsDataRing->end);
+    }
+
+    if (usedBuffer == (ptpTsDataRing->size-1))
+    {
+        isRingBufferFull = true;
+    }
+
     /* Search the element in the ring buffer */
     index = ptpTsDataRing->front;
     size = ptpTsDataRing->size;
@@ -2357,29 +2734,37 @@ static status_t ENET_Ptp1588SearchTimeRing(enet_ptp_time_data_ring_t *ptpTsDataR
 
     if (index == ptpTsDataRing->end)
     {
-        /* Check if buffers is full. */
-        if (ptpTsDataRing->end >= ptpTsDataRing->front)
+        if (isRingBufferFull == true)
+        {
+            /* PTP timestamp buffer ring full, data in index ptpTsDataRing->end is valid. */
+            if (((ptpTsDataRing->ptpTsData + index)->sequenceId != ptpTimedata->sequenceId) ||
+            (memcmp(((void *)&(ptpTsDataRing->ptpTsData + index)->sourcePortId[0]),
+                     (void *)&ptpTimedata->sourcePortId[0], kENET_PtpSrcPortIdLen)) ||
+            ((ptpTsDataRing->ptpTsData + index)->version != ptpTimedata->version)  ||
+            ((ptpTsDataRing->ptpTsData + index)->messageType != ptpTimedata->messageType))
         {
-            usedBuffer = ptpTsDataRing->end - ptpTsDataRing->front;
+                return kStatus_ENET_PtpTsRingFull;
+            }
         }
         else
         {
-            usedBuffer = ptpTsDataRing->size - (ptpTsDataRing->front - ptpTsDataRing->end);
-        }
-
-        if (usedBuffer == ptpTsDataRing->size)
-        { /* Drop one in the front. */
-            ptpTsDataRing->front = (ptpTsDataRing->front + 1) % size;
+            return kStatus_ENET_PtpTsRingFull;
         }
-        return kStatus_ENET_PtpTsRingFull;
     }
 
     /* Get the right timestamp of the required ptp messag. */
     ptpTimedata->timeStamp.second = (ptpTsDataRing->ptpTsData + index)->timeStamp.second;
     ptpTimedata->timeStamp.nanosecond = (ptpTsDataRing->ptpTsData + index)->timeStamp.nanosecond;
 
-    /* Increase the index. */
-    ptpTsDataRing->front = (ptpTsDataRing->front + 1) % size;
+    if( isRingBufferFull == true)
+    {
+        /* If ring buffer full, move front pointer to next pointer behind end pointer, then next
+        read will still read whole ring. */
+        ptpTsDataRing->end = index;
+    }
+
+    /* Drop previous ptp stamp. */
+    ptpTsDataRing->front = (index + 1) % size;
 
     return kStatus_Success;
 }
@@ -2389,31 +2774,20 @@ static status_t ENET_StoreRxFrameTime(ENET_Type *base, enet_handle_t *handle, en
     assert(handle);
     assert(ptpTimeData);
 
-    bool ptpTimerWrap = false;
     enet_ptp_time_t ptpTimer;
-    uint32_t primask;
-
-    /* Disables the interrupt. */
-    primask = DisableGlobalIRQ();
 
     /* Get current PTP timer nanosecond value. */
     ENET_Ptp1588GetTimer(base, handle, &ptpTimer);
 
-    /* Get PTP timer wrap event. */
-    ptpTimerWrap = base->EIR & kENET_TsTimerInterrupt;
-
     /* Get transmit time stamp second. */
-    if ((ptpTimer.nanosecond > ptpTimeData->timeStamp.nanosecond) ||
-        ((ptpTimer.nanosecond < ptpTimeData->timeStamp.nanosecond) && ptpTimerWrap))
+    if (ptpTimer.nanosecond >= ptpTimeData->timeStamp.nanosecond)
     {
-        ptpTimeData->timeStamp.second = handle->msTimerSecond;
+        ptpTimeData->timeStamp.second = ptpTimer.second;
     }
     else
     {
-        ptpTimeData->timeStamp.second = handle->msTimerSecond - 1;
+        ptpTimeData->timeStamp.second = ptpTimer.second - 1;
     }
-    /* Enable the interrupt. */
-    EnableGlobalIRQ(primask);
 
     /* Store the timestamp to the receive time stamp ring. */
     /* Check if the buffers ring is full. */
@@ -2424,12 +2798,43 @@ static status_t ENET_StoreTxFrameTime(ENET_Type *base, enet_handle_t *handle, ui
 {
     assert(handle);
 
-    uint32_t primask;
-    bool ptpTimerWrap;
     bool isPtpEventMessage = false;
     enet_ptp_time_data_t ptpTimeData;
-    volatile enet_tx_bd_struct_t *curBuffDescrip = handle->txBdDirtyTime[ringId];
+    volatile enet_tx_bd_struct_t *curBuffDescrip;
+    volatile enet_tx_bd_struct_t *endBuffDescrip;
     uint32_t address;
+    bool isReadLastBd = false;
+    bool readLastBd = false;
+
+    /* Treat the txBdCurrent[ringId] as the tx bd write buffer pointer,
+    txBdDirtyTime[ringId] as the tx bd read buffer pointer. Considering
+    that the tx frame time read is driven by tx frame send, so the read
+    pointer txBdDirtyTime[ringId] should always behind write pointer
+    txBdDirtyTime[ringId]. Then if the read pointer equals write pointer,
+    we could treat the tx bd buffer is full. We could read out all
+    available bds. */
+    if(handle->txBdDirtyTime[ringId] == handle->txBdCurrent[ringId])
+    {
+        isReadLastBd = true;
+        if(handle->txBdDirtyTime[ringId] == handle->txBdBase[ringId])
+        {
+           endBuffDescrip =  handle->txBdDirtyTime[ringId] + 3;
+        }
+        else
+        {
+           endBuffDescrip = handle->txBdDirtyTime[ringId] - 1;
+        }
+    }
+    else
+    {
+        endBuffDescrip = handle->txBdCurrent[ringId];
+    }
+
+    /* Read tx bd buffer until read pointer txBdDirtyTime[ringId] equals to the end pointer of
+    tx bd buffer. */
+    while((handle->txBdDirtyTime[ringId] != endBuffDescrip)  || (readLastBd == true))
+    {
+         curBuffDescrip = handle->txBdDirtyTime[ringId];
 
     /* Get the control status data, If the buffer descriptor has not been processed break out. */
     if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_TX_READY_MASK)
@@ -2438,17 +2843,15 @@ static status_t ENET_StoreTxFrameTime(ENET_Type *base, enet_handle_t *handle, ui
     }
 
     /* Parse the PTP message. */
-#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET
-    address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local);
-#else
+    #if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET
+        address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer, kMEMORY_DMA2Local);
+    #else
     address = (uint32_t)curBuffDescrip->buffer;
-#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */
+    #endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */
     isPtpEventMessage = ENET_Ptp1588ParseFrame((uint8_t *)address, &ptpTimeData, false);
     if (isPtpEventMessage)
     {
          /* Only store tx timestamp for ptp event message. */
-        do
-        {
             /* Increase current buffer descriptor to the next one. */
             if (handle->txBdDirtyTime[ringId]->control & ENET_BUFFDESCRIPTOR_TX_WRAP_MASK)
             {
@@ -2462,46 +2865,21 @@ static status_t ENET_StoreTxFrameTime(ENET_Type *base, enet_handle_t *handle, ui
             /* Do time stamp check on the last buffer descriptor of the frame. */
             if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_TX_LAST_MASK)
             {
-                /* Disables the interrupt. */
-                primask = DisableGlobalIRQ();
-
                 /* Get current PTP timer nanosecond value. */
                 ENET_Ptp1588GetTimer(base, handle, &ptpTimeData.timeStamp);
 
-                /* Get PTP timer wrap event. */
-                ptpTimerWrap = base->EIR & kENET_TsTimerInterrupt;
-
                 /* Get transmit time stamp second. */
-                if ((ptpTimeData.timeStamp.nanosecond > curBuffDescrip->timestamp) ||
-                    ((ptpTimeData.timeStamp.nanosecond < curBuffDescrip->timestamp) && ptpTimerWrap))
+                if (ptpTimeData.timeStamp.nanosecond < curBuffDescrip->timestamp)
                 {
-                    ptpTimeData.timeStamp.second = handle->msTimerSecond;
-                }
-                else
-                {
-                    ptpTimeData.timeStamp.second = handle->msTimerSecond - 1;
+                    ptpTimeData.timeStamp.second--;
                 }
 
                 /* Save transmit time stamp nanosecond. */
                 ptpTimeData.timeStamp.nanosecond = curBuffDescrip->timestamp;
 
-                /* Enable the interrupt. */
-                EnableGlobalIRQ(primask);
-
                 /* Store the timestamp to the transmit timestamp ring. */
-                return ENET_Ptp1588UpdateTimeRing(&handle->txPtpTsDataRing, &ptpTimeData);
+                ENET_Ptp1588UpdateTimeRing(&handle->txPtpTsDataRing, &ptpTimeData);
             }
-
-            /* Get the current transmit buffer descriptor. */
-            curBuffDescrip = handle->txBdDirtyTime[ringId];
-
-            /* Get the control status data, If the buffer descriptor has not been processed break out. */
-            if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_TX_READY_MASK)
-            {
-                return kStatus_ENET_TxFrameBusy;
-            }
-        } while (handle->txBdDirtyTime[ringId] != handle->txBdCurrent[ringId]);
-        return kStatus_ENET_TxFrameFail;
     }
     else
     {
@@ -2515,9 +2893,35 @@ static status_t ENET_StoreTxFrameTime(ENET_Type *base, enet_handle_t *handle, ui
             handle->txBdDirtyTime[ringId]++;
         }
     }
+
+        if(readLastBd == true)
+        {
+            break;
+        }
+
+        /* If if read pointer equals write pointer, the end pointer is set at the pointer before
+        current write pointer and the buffer in the end pointer is available, so read last bd at
+        the end pointer. */
+        if((isReadLastBd == true) && (handle->txBdDirtyTime[ringId] == endBuffDescrip))
+        {
+            readLastBd = true;
+        }
+    }
     return kStatus_Success;
 }
 
+/*!
+ * brief Gets the time stamp of the transmit frame.
+ *
+ * This function is used for PTP stack to get the timestamp captured by the ENET driver.
+ *
+ * param handle The ENET handler pointer.This is the same state pointer used in
+ *        ENET_Init.
+ * param ptpTimeData The special PTP timestamp data for search the receive timestamp.
+ * retval kStatus_Success Get 1588 timestamp success.
+ * retval kStatus_ENET_PtpTsRingEmpty 1588 timestamp ring empty.
+ * retval kStatus_ENET_PtpTsRingFull 1588 timestamp ring full.
+ */
 status_t ENET_GetTxFrameTime(enet_handle_t *handle, enet_ptp_time_data_t *ptpTimeData)
 {
     assert(handle);
@@ -2526,6 +2930,18 @@ status_t ENET_GetTxFrameTime(enet_handle_t *handle, enet_ptp_time_data_t *ptpTim
     return ENET_Ptp1588SearchTimeRing(&handle->txPtpTsDataRing, ptpTimeData);
 }
 
+/*!
+ * brief Gets the time stamp of the received frame.
+ *
+ * This function is used for PTP stack to get the timestamp captured by the ENET driver.
+ *
+ * param handle The ENET handler pointer.This is the same state pointer used in
+ *        ENET_Init.
+ * param ptpTimeData The special PTP timestamp data for search the receive timestamp.
+ * retval kStatus_Success Get 1588 timestamp success.
+ * retval kStatus_ENET_PtpTsRingEmpty 1588 timestamp ring empty.
+ * retval kStatus_ENET_PtpTsRingFull 1588 timestamp ring full.
+ */
 status_t ENET_GetRxFrameTime(enet_handle_t *handle, enet_ptp_time_data_t *ptpTimeData)
 {
     assert(handle);
@@ -2535,6 +2951,21 @@ status_t ENET_GetRxFrameTime(enet_handle_t *handle, enet_ptp_time_data_t *ptpTim
 }
 
 #if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB
+/*!
+ * brief Sets the ENET AVB feature.
+ *
+ * ENET AVB feature configuration, set the Receive classification match and transmit
+ * bandwidth. This API is called when the AVB feature is required.
+ *
+ * Note: The AVB frames transmission scheme is credit-based tx scheme and it's only supported
+ * with the Enhanced buffer descriptors. so the AVB configuration should only done with
+ * Enhanced buffer descriptor. so when the AVB feature is required, please make sure the
+ * the "ENET_ENHANCEDBUFFERDESCRIPTOR_MODE" is defined.
+ *
+ * param base ENET peripheral base address.
+ * param handle ENET handler pointer.
+ * param config The ENET AVB feature configuration structure.
+ */
 void ENET_AVBConfigure(ENET_Type *base, enet_handle_t *handle, const enet_avb_config_t *config)
 {
     assert(config);
@@ -2560,8 +2991,20 @@ void ENET_AVBConfigure(ENET_Type *base, enet_handle_t *handle, const enet_avb_co
 #endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */
 
 #if FSL_FEATURE_ENET_QUEUE > 1
+/*!
+ * brief The transmit IRQ handler.
+ *
+ * param base  ENET peripheral base address.
+ * param handle The ENET handler pointer.
+ */
 void ENET_TransmitIRQHandler(ENET_Type *base, enet_handle_t *handle, uint32_t ringId)
 #else
+/*!
+ * brief The transmit IRQ handler.
+ *
+ * param base  ENET peripheral base address.
+ * param handle The ENET handler pointer.
+ */
 void ENET_TransmitIRQHandler(ENET_Type *base, enet_handle_t *handle)
 #endif /* FSL_FEATURE_ENET_QUEUE > 1 */
 {
@@ -2613,8 +3056,20 @@ void ENET_TransmitIRQHandler(ENET_Type *base, enet_handle_t *handle)
 }
 
 #if FSL_FEATURE_ENET_QUEUE > 1
+/*!
+ * brief The receive IRQ handler.
+ *
+ * param base  ENET peripheral base address.
+ * param handle The ENET handler pointer.
+ */
 void ENET_ReceiveIRQHandler(ENET_Type *base, enet_handle_t *handle, uint32_t ringId)
 #else
+/*!
+ * brief The receive IRQ handler.
+ *
+ * param base  ENET peripheral base address.
+ * param handle The ENET handler pointer.
+ */
 void ENET_ReceiveIRQHandler(ENET_Type *base, enet_handle_t *handle)
 #endif /* FSL_FEATURE_ENET_QUEUE > 1 */
 {
@@ -2653,6 +3108,12 @@ void ENET_ReceiveIRQHandler(ENET_Type *base, enet_handle_t *handle)
     }
 }
 
+/*!
+ * brief Some special IRQ handler including the error, mii, wakeup irq handler.
+ *
+ * param base  ENET peripheral base address.
+ * param handle The ENET handler pointer.
+ */
 void ENET_ErrorIRQHandler(ENET_Type *base, enet_handle_t *handle)
 {
     assert(handle);
@@ -2692,7 +3153,7 @@ void ENET_ErrorIRQHandler(ENET_Type *base, enet_handle_t *handle)
 #endif /* FSL_FEATURE_ENET_QUEUE > 1 */
         }
     }
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
       exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
@@ -2700,6 +3161,12 @@ void ENET_ErrorIRQHandler(ENET_Type *base, enet_handle_t *handle)
 }
 
 #ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE
+/*!
+ * brief The IEEE 1588 PTP time stamp interrupt handler.
+ *
+ * param base  ENET peripheral base address.
+ * param handle The ENET state pointer. This is the same state pointer used in the ENET_Init.
+ */
 void ENET_Ptp1588TimerIRQHandler(ENET_Type *base, enet_handle_t *handle)
 {
     assert(handle);
@@ -2737,7 +3204,7 @@ void ENET_Ptp1588TimerIRQHandler(ENET_Type *base, enet_handle_t *handle)
 #endif /* FSL_FEATURE_ENET_QUEUE > 1 */
         }
     }
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
       exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
@@ -2745,6 +3212,13 @@ void ENET_Ptp1588TimerIRQHandler(ENET_Type *base, enet_handle_t *handle)
 }
 #endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */
 
+/*!
+ * brief the common IRQ handler for the tx/rx/error etc irq handler.
+ *
+ * This is used for the combined tx/rx/error interrupt for single/mutli-ring (frame 0).
+ *
+ * param base  ENET peripheral base address.
+ */
 void ENET_CommonFrame0IRQHandler(ENET_Type *base)
 {
     uint32_t event = base->EIR;
@@ -2776,7 +3250,7 @@ void ENET_CommonFrame0IRQHandler(ENET_Type *base)
     {
         s_enetErrIsr(base, s_ENETHandle[instance]);
     }
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
       exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
@@ -2784,6 +3258,13 @@ void ENET_CommonFrame0IRQHandler(ENET_Type *base)
 }
 
 #if FSL_FEATURE_ENET_QUEUE > 1
+/*!
+ * brief the common IRQ handler for the tx/rx irq handler.
+ *
+ * This is used for the combined tx/rx interrupt for multi-ring (frame 1).
+ *
+ * param base  ENET peripheral base address.
+ */
 void ENET_CommonFrame1IRQHandler(ENET_Type *base)
 {
     uint32_t event = base->EIR;
@@ -2798,13 +3279,20 @@ void ENET_CommonFrame1IRQHandler(ENET_Type *base)
     {
         s_enetRxIsr(base, s_ENETHandle[instance], 1);
     }
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
       exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
 #endif
 }
 
+/*!
+ * brief the common IRQ handler for the tx/rx irq handler.
+ *
+ * This is used for the combined tx/rx interrupt for multi-ring (frame 2).
+ *
+ * param base  ENET peripheral base address.
+ */
 void ENET_CommonFrame2IRQHandler(ENET_Type *base)
 {
     uint32_t event = base->EIR;
@@ -2819,7 +3307,7 @@ void ENET_CommonFrame2IRQHandler(ENET_Type *base)
     {
         s_enetRxIsr(base, s_ENETHandle[instance], 2);
     }
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
       exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
@@ -2831,7 +3319,7 @@ void ENET_CommonFrame2IRQHandler(ENET_Type *base)
 void ENET_Transmit_IRQHandler(void)
 {
     s_enetTxIsr(ENET, s_ENETHandle[0]);
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
       exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
@@ -2841,7 +3329,7 @@ void ENET_Transmit_IRQHandler(void)
 void ENET_Receive_IRQHandler(void)
 {
     s_enetRxIsr(ENET, s_ENETHandle[0]);
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
       exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
@@ -2851,7 +3339,7 @@ void ENET_Receive_IRQHandler(void)
 void ENET_Error_IRQHandler(void)
 {
     s_enetErrIsr(ENET, s_ENETHandle[0]);
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
       exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
@@ -2861,7 +3349,7 @@ void ENET_Error_IRQHandler(void)
 void ENET_1588_Timer_IRQHandler(void)
 {
     s_enetTsIsr(ENET, s_ENETHandle[0]);
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
       exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
@@ -2876,7 +3364,7 @@ void ENET_DriverIRQHandler(void)
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
 #endif
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
       exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
@@ -2885,12 +3373,11 @@ void ENET_DriverIRQHandler(void)
 
 #endif
 
-
 #if defined(ENET1)
 void ENET1_DriverIRQHandler(void)
 {
     ENET_CommonFrame0IRQHandler(ENET1);
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
       exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
@@ -2902,7 +3389,7 @@ void ENET1_DriverIRQHandler(void)
 void ENET2_DriverIRQHandler(void)
 {
     ENET_CommonFrame0IRQHandler(ENET2);
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
       exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
@@ -2910,12 +3397,11 @@ void ENET2_DriverIRQHandler(void)
 }
 #endif
 
-
 #if defined(CONNECTIVITY__ENET0)
 void CONNECTIVITY_ENET0_FRAME0_EVENT_INT_DriverIRQHandler(void)
 {
     ENET_CommonFrame0IRQHandler(CONNECTIVITY__ENET0);
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
       exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
@@ -2925,7 +3411,7 @@ void CONNECTIVITY_ENET0_FRAME0_EVENT_INT_DriverIRQHandler(void)
 void CONNECTIVITY_ENET0_FRAME1_INT_DriverIRQHandler(void)
 {
     ENET_CommonFrame1IRQHandler(CONNECTIVITY__ENET0);
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
       exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
@@ -2934,7 +3420,7 @@ void CONNECTIVITY_ENET0_FRAME1_INT_DriverIRQHandler(void)
 void CONNECTIVITY_ENET0_FRAME2_INT_DriverIRQHandler(void)
 {
     ENET_CommonFrame2IRQHandler(CONNECTIVITY__ENET0);
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
       exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
@@ -2946,7 +3432,7 @@ void CONNECTIVITY_ENET0_FRAME2_INT_DriverIRQHandler(void)
 void CONNECTIVITY_ENET1_FRAME0_EVENT_INT_DriverIRQHandler(void)
 {
     ENET_CommonFrame0IRQHandler(CONNECTIVITY__ENET1);
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
       exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
@@ -2956,7 +3442,7 @@ void CONNECTIVITY_ENET1_FRAME0_EVENT_INT_DriverIRQHandler(void)
 void CONNECTIVITY_ENET1_FRAME1_INT_DriverIRQHandler(void)
 {
     ENET_CommonFrame1IRQHandler(CONNECTIVITY__ENET1);
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
       exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
@@ -2965,7 +3451,7 @@ void CONNECTIVITY_ENET1_FRAME1_INT_DriverIRQHandler(void)
 void CONNECTIVITY_ENET1_FRAME2_INT_DriverIRQHandler(void)
 {
     ENET_CommonFrame2IRQHandler(CONNECTIVITY__ENET1);
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
       exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_enet.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_enet.h
index b0c9adafe40..167361dbae7 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_enet.h
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_enet.h
@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
+ * Copyright 2016-2019 NXP
  * All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- * that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 #ifndef _FSL_ENET_H_
 #define _FSL_ENET_H_
@@ -50,7 +24,7 @@
 /*! @name Driver version */
 /*@{*/
 /*! @brief Defines the driver version. */
-#define FSL_ENET_DRIVER_VERSION (MAKE_VERSION(2, 2, 3)) /*!< Version 2.2.3. */
+#define FSL_ENET_DRIVER_VERSION (MAKE_VERSION(2, 2, 4)) /*!< Version 2.2.4. */
 /*@}*/
 
 /*! @name ENET DESCRIPTOR QUEUE */
@@ -445,7 +419,7 @@ typedef struct _enet_tx_bd_struct
 #endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */
 } enet_tx_bd_struct_t;
 
-/*! @brief Defines the ENET data error statistic structure. */
+/*! @brief Defines the ENET data error statistics structure. */
 typedef struct _enet_data_error_stats
 {
     uint32_t statsRxLenGreaterErr; /*!< Receive length greater than RCR[MAX_FL]. */
@@ -619,9 +593,8 @@ typedef struct _enet_config
     uint8_t txFifoWatermark;          /*!< For store and forward disable case, the data required in TX FIFO
                                       before a frame transmit start. */
 #if defined(FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE) && FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE
-    enet_intcoalesce_config_t
-        *intCoalesceCfg; /* If the interrupt coalsecence is not required in the ring n(0,1,2), please set
-                   to NULL. */
+    enet_intcoalesce_config_t *intCoalesceCfg; /* If the interrupt coalsecence is not required in the ring n(0,1,2),
+                                         please set to NULL. */
 #endif                   /* FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE */
     uint8_t ringNum;     /*!< Number of used rings. default with 1 -- single ring. */
 } enet_config_t;
@@ -1169,21 +1142,21 @@ status_t ENET_GetTxErrAfterSendFrame(enet_handle_t *handle, enet_data_error_stat
 #endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */
 
 /*!
-* @brief Gets the size of the read frame for single ring.
-*
-* This function gets a received frame size from the ENET buffer descriptors.
-* @note The FCS of the frame is automatically removed by MAC and the size is the length without the FCS.
-* After calling ENET_GetRxFrameSize, ENET_ReadFrame() should be called to update the
-* receive buffers If the result is not "kStatus_ENET_RxFrameEmpty".
-*
-* @param handle The ENET handler structure. This is the same handler pointer used in the ENET_Init.
-* @param length The length of the valid frame received.
-* @retval kStatus_ENET_RxFrameEmpty No frame received. Should not call ENET_ReadFrame to read frame.
-* @retval kStatus_ENET_RxFrameError Data error happens. ENET_ReadFrame should be called with NULL data
-*         and NULL length to update the receive buffers.
-* @retval kStatus_Success Receive a frame Successfully then the ENET_ReadFrame
-*         should be called with the right data buffer and the captured data length input.
-*/
+ * @brief Gets the size of the read frame for single ring.
+ *
+ * This function gets a received frame size from the ENET buffer descriptors.
+ * @note The FCS of the frame is automatically removed by MAC and the size is the length without the FCS.
+ * After calling ENET_GetRxFrameSize, ENET_ReadFrame() should be called to update the
+ * receive buffers If the result is not "kStatus_ENET_RxFrameEmpty".
+ *
+ * @param handle The ENET handler structure. This is the same handler pointer used in the ENET_Init.
+ * @param length The length of the valid frame received.
+ * @retval kStatus_ENET_RxFrameEmpty No frame received. Should not call ENET_ReadFrame to read frame.
+ * @retval kStatus_ENET_RxFrameError Data error happens. ENET_ReadFrame should be called with NULL data
+ *         and NULL length to update the receive buffers.
+ * @retval kStatus_Success Receive a frame Successfully then the ENET_ReadFrame
+ *         should be called with the right data buffer and the captured data length input.
+ */
 status_t ENET_GetRxFrameSize(enet_handle_t *handle, uint32_t *length);
 
 /*!
@@ -1303,23 +1276,23 @@ status_t ENET_GetTxErrAfterSendFrameMultiRing(enet_handle_t *handle,
 #endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */
 
 /*!
-* @brief Gets the size of the read frame for extended mutli-ring.
-*
-* This function gets a received frame size from the ENET buffer descriptors.
-* @note The FCS of the frame is automatically removed by MAC and the size is the length without the FCS.
-* After calling ENET_GetRxFrameSizeMultiRing, ENET_ReadFrameMultiRing() should be called to update the
-* receive buffers If the result is not "kStatus_ENET_RxFrameEmpty". The usage is
-* the same to the single ring, refer to ENET_GetRxFrameSize.
-*
-* @param handle The ENET handler structure. This is the same handler pointer used in the ENET_Init.
-* @param length The length of the valid frame received.
-* @param ringId The ring index or ring number;
-* @retval kStatus_ENET_RxFrameEmpty No frame received. Should not call ENET_ReadFrameMultiRing to read frame.
-* @retval kStatus_ENET_RxFrameError Data error happens. ENET_ReadFrameMultiRing should be called with NULL data
-*         and NULL length to update the receive buffers.
-* @retval kStatus_Success Receive a frame Successfully then the ENET_ReadFrame
-*         should be called with the right data buffer and the captured data length input.
-*/
+ * @brief Gets the size of the read frame for extended mutli-ring.
+ *
+ * This function gets a received frame size from the ENET buffer descriptors.
+ * @note The FCS of the frame is automatically removed by MAC and the size is the length without the FCS.
+ * After calling ENET_GetRxFrameSizeMultiRing, ENET_ReadFrameMultiRing() should be called to update the
+ * receive buffers If the result is not "kStatus_ENET_RxFrameEmpty". The usage is
+ * the same to the single ring, refer to ENET_GetRxFrameSize.
+ *
+ * @param handle The ENET handler structure. This is the same handler pointer used in the ENET_Init.
+ * @param length The length of the valid frame received.
+ * @param ringId The ring index or ring number;
+ * @retval kStatus_ENET_RxFrameEmpty No frame received. Should not call ENET_ReadFrameMultiRing to read frame.
+ * @retval kStatus_ENET_RxFrameError Data error happens. ENET_ReadFrameMultiRing should be called with NULL data
+ *         and NULL length to update the receive buffers.
+ * @retval kStatus_Success Receive a frame Successfully then the ENET_ReadFrame
+ *         should be called with the right data buffer and the captured data length input.
+ */
 status_t ENET_GetRxFrameSizeMultiRing(enet_handle_t *handle, uint32_t *length, uint32_t ringId);
 
 /*!
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_ewm.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_ewm.c
index bbc49d62e75..15182e15fa3 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_ewm.c
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_ewm.c
@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
  * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
  *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include "fsl_ewm.h"
@@ -39,11 +13,29 @@
 #define FSL_COMPONENT_ID "platform.drivers.ewm"
 #endif
 
-
 /*******************************************************************************
  * Code
  ******************************************************************************/
 
+/*!
+ * brief Initializes the EWM peripheral.
+ *
+ * This function is used to initialize the EWM. After calling, the EWM
+ * runs immediately according to the configuration.
+ * Note that, except for the interrupt enable control bit, other control bits and registers are write once after a
+ * CPU reset. Modifying them more than once generates a bus transfer error.
+ *
+ * This is an example.
+ * code
+ *   ewm_config_t config;
+ *   EWM_GetDefaultConfig(&config);
+ *   config.compareHighValue = 0xAAU;
+ *   EWM_Init(ewm_base,&config);
+ * endcode
+ *
+ * param base EWM peripheral base address
+ * param config The configuration of the EWM
+ */
 void EWM_Init(EWM_Type *base, const ewm_config_t *config)
 {
     assert(config);
@@ -51,7 +43,7 @@ void EWM_Init(EWM_Type *base, const ewm_config_t *config)
     uint32_t value = 0U;
 
 #if !((defined(FSL_FEATURE_SOC_PCC_COUNT) && FSL_FEATURE_SOC_PCC_COUNT) && \
-    (defined(FSL_FEATURE_PCC_SUPPORT_EWM_CLOCK_REMOVE) && FSL_FEATURE_PCC_SUPPORT_EWM_CLOCK_REMOVE))
+      (defined(FSL_FEATURE_PCC_SUPPORT_EWM_CLOCK_REMOVE) && FSL_FEATURE_PCC_SUPPORT_EWM_CLOCK_REMOVE))
 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     CLOCK_EnableClock(kCLOCK_Ewm0);
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
@@ -71,42 +63,78 @@ void EWM_Init(EWM_Type *base, const ewm_config_t *config)
     base->CTRL = value;
 }
 
+/*!
+ * brief Deinitializes the EWM peripheral.
+ *
+ * This function is used to shut down the EWM.
+ *
+ * param base EWM peripheral base address
+ */
 void EWM_Deinit(EWM_Type *base)
 {
     EWM_DisableInterrupts(base, kEWM_InterruptEnable);
 #if !((defined(FSL_FEATURE_SOC_PCC_COUNT) && FSL_FEATURE_SOC_PCC_COUNT) && \
-    (defined(FSL_FEATURE_PCC_SUPPORT_EWM_CLOCK_REMOVE) && FSL_FEATURE_PCC_SUPPORT_EWM_CLOCK_REMOVE))
+      (defined(FSL_FEATURE_PCC_SUPPORT_EWM_CLOCK_REMOVE) && FSL_FEATURE_PCC_SUPPORT_EWM_CLOCK_REMOVE))
 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     CLOCK_DisableClock(kCLOCK_Ewm0);
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 #endif /* FSL_FEATURE_PCC_SUPPORT_EWM_CLOCK_REMOVE */
 }
 
+/*!
+ * brief Initializes the EWM configuration structure.
+ *
+ * This function initializes the EWM configuration structure to default values. The default
+ * values are as follows.
+ * code
+ *   ewmConfig->enableEwm = true;
+ *   ewmConfig->enableEwmInput = false;
+ *   ewmConfig->setInputAssertLogic = false;
+ *   ewmConfig->enableInterrupt = false;
+ *   ewmConfig->ewm_lpo_clock_source_t = kEWM_LpoClockSource0;
+ *   ewmConfig->prescaler = 0;
+ *   ewmConfig->compareLowValue = 0;
+ *   ewmConfig->compareHighValue = 0xFEU;
+ * endcode
+ *
+ * param config Pointer to the EWM configuration structure.
+ * see ewm_config_t
+ */
 void EWM_GetDefaultConfig(ewm_config_t *config)
 {
     assert(config);
 
-    config->enableEwm = true;
-    config->enableEwmInput = false;
+    /* Initializes the configure structure to zero. */
+    memset(config, 0, sizeof(*config));
+
+    config->enableEwm           = true;
+    config->enableEwmInput      = false;
     config->setInputAssertLogic = false;
-    config->enableInterrupt = false;
+    config->enableInterrupt     = false;
 #if defined(FSL_FEATURE_EWM_HAS_CLOCK_SELECT) && FSL_FEATURE_EWM_HAS_CLOCK_SELECT
     config->clockSource = kEWM_LpoClockSource0;
 #endif /* FSL_FEATURE_EWM_HAS_CLOCK_SELECT*/
 #if defined(FSL_FEATURE_EWM_HAS_PRESCALER) && FSL_FEATURE_EWM_HAS_PRESCALER
     config->prescaler = 0U;
 #endif /* FSL_FEATURE_EWM_HAS_PRESCALER */
-    config->compareLowValue = 0U;
+    config->compareLowValue  = 0U;
     config->compareHighValue = 0xFEU;
 }
 
+/*!
+ * brief Services the EWM.
+ *
+ * This function resets the EWM counter to zero.
+ *
+ * param base EWM peripheral base address
+ */
 void EWM_Refresh(EWM_Type *base)
 {
     uint32_t primaskValue = 0U;
 
     /* Disable the global interrupt to protect refresh sequence */
     primaskValue = DisableGlobalIRQ();
-    base->SERV = (uint8_t)0xB4U;
-    base->SERV = (uint8_t)0x2CU;
+    base->SERV   = (uint8_t)0xB4U;
+    base->SERV   = (uint8_t)0x2CU;
     EnableGlobalIRQ(primaskValue);
 }
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_ewm.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_ewm.h
index 55ab66af951..3b5fd3a7de4 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_ewm.h
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_ewm.h
@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
  * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 #ifndef _FSL_EWM_H_
 #define _FSL_EWM_H_
@@ -41,7 +15,6 @@
  * @{
  */
 
-
 /*******************************************************************************
  * Definitions
  *******************************************************************************/
@@ -64,10 +37,10 @@ typedef enum _ewm_lpo_clock_source
 #endif /* FSL_FEATURE_EWM_HAS_CLOCK_SELECT */
 
 /*!
-* @brief Data structure for EWM configuration.
-*
-* This structure is used to configure the EWM.
-*/
+ * @brief Data structure for EWM configuration.
+ *
+ * This structure is used to configure the EWM.
+ */
 typedef struct _ewm_config
 {
     bool enableEwm;           /*!< Enable EWM module */
@@ -135,7 +108,7 @@ extern "C" {
  *
  * @param base EWM peripheral base address
  * @param config The configuration of the EWM
-*/
+ */
 void EWM_Init(EWM_Type *base, const ewm_config_t *config);
 
 /*!
@@ -144,7 +117,7 @@ void EWM_Init(EWM_Type *base, const ewm_config_t *config);
  * This function is used to shut down the EWM.
  *
  * @param base EWM peripheral base address
-*/
+ */
 void EWM_Deinit(EWM_Type *base);
 
 /*!
@@ -231,7 +204,7 @@ static inline uint32_t EWM_GetStatusFlags(EWM_Type *base)
  * This function resets the EWM counter to zero.
  *
  * @param base EWM peripheral base address
-*/
+ */
 void EWM_Refresh(EWM_Type *base);
 
 /*@}*/
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexcan.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexcan.c
index 132dbfb7025..47cea9785d3 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexcan.c
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexcan.c
@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
+ * Copyright 2016-2019 NXP
  * All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- * that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include "fsl_flexcan.h"
@@ -43,26 +17,69 @@
 #define FSL_COMPONENT_ID "platform.drivers.flexcan"
 #endif
 
+#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032)
+#define RXINTERMISSION (CAN_DBG1_CFSM(0x2f))
+#define TXINTERMISSION (CAN_DBG1_CFSM(0x14))
+#define BUSIDLE (CAN_DBG1_CFSM(0x02))
+#define CBN_VALUE3 (CAN_DBG1_CBN(0x03))
+#define DELAY_BUSIDLE (200)
+#endif
+
+#define IDEAL_SP_LOW (750U)
+#define IDEAL_SP_MID (800U)
+#define IDEAL_SP_HIGH (875U)
+#define IDEAL_SP_FACTOR (1000U)
+
+#define MAX_PROPSEG (CAN_CTRL1_PROPSEG_MASK >> CAN_CTRL1_PROPSEG_SHIFT)
+#define MAX_PSEG1 (CAN_CTRL1_PSEG1_MASK >> CAN_CTRL1_PSEG1_SHIFT)
+#define MAX_PSEG2 (CAN_CTRL1_PSEG2_MASK >> CAN_CTRL1_PSEG2_SHIFT)
+#define MAX_RJW (CAN_CTRL1_RJW_MASK >> CAN_CTRL1_RJW_SHIFT)
+#define MAX_PRESDIV (CAN_CTRL1_PRESDIV_MASK >> CAN_CTRL1_PRESDIV_SHIFT)
+#define CTRL1_MAX_TIME_QUANTA (1U + MAX_PROPSEG + 1U + MAX_PSEG1 + 1U + MAX_PSEG2 + 1U)
+#define CTRL1_MIN_TIME_QUANTA (8U)
+
+#define MAX_EPROPSEG (CAN_CBT_EPROPSEG_MASK >> CAN_CBT_EPROPSEG_SHIFT)
+#define MAX_EPSEG1 (CAN_CBT_EPSEG1_MASK >> CAN_CBT_EPSEG1_SHIFT)
+#define MAX_EPSEG2 (CAN_CBT_EPSEG2_MASK >> CAN_CBT_EPSEG2_SHIFT)
+#define MAX_ERJW (CAN_CBT_ERJW_MASK >> CAN_CBT_ERJW_SHIFT)
+#define MAX_EPRESDIV (CAN_CBT_EPRESDIV_MASK >> CAN_CBT_EPRESDIV_SHIFT)
+#define CBT_MAX_TIME_QUANTA (1U + MAX_EPROPSEG + 1U + MAX_EPSEG1 + 1U + MAX_EPSEG2 + 1U)
+#define CBT_MIN_TIME_QUANTA (8U)
+
+#define FDCBT_MAX_TIME_QUANTA (1U + MAX_FPROPSEG + 0U + MAX_FPSEG1 + 1U + MAX_FPSEG2 + 1U)
+#define FDCBT_MIN_TIME_QUANTA (5U)
+#define MAX_FPROPSEG (CAN_FDCBT_FPROPSEG_MASK >> CAN_FDCBT_FPROPSEG_SHIFT)
+#define MAX_FPSEG1 (CAN_FDCBT_FPSEG1_MASK >> CAN_FDCBT_FPSEG1_SHIFT)
+#define MAX_FPSEG2 (CAN_FDCBT_FPSEG2_MASK >> CAN_FDCBT_FPSEG2_SHIFT)
+#define MAX_FRJW (CAN_FDCBT_FRJW_MASK >> CAN_FDCBT_FRJW_SHIFT)
+#define MAX_FPRESDIV (CAN_FDCBT_FPRESDIV_MASK >> CAN_FDCBT_FPRESDIV_SHIFT)
+
+#define MAX_CANFD_BAUDRATE (8000000U)
+#define MAX_CAN_BAUDRATE (1000000U)
+
+#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_9595) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_9595)
+#define CAN_ESR1_FLTCONF_BUSOFF CAN_ESR1_FLTCONF(2U)
+#endif
 
 /*! @brief FlexCAN Internal State. */
 enum _flexcan_state
 {
-    kFLEXCAN_StateIdle = 0x0,     /*!< MB/RxFIFO idle.*/
-    kFLEXCAN_StateRxData = 0x1,   /*!< MB receiving.*/
+    kFLEXCAN_StateIdle     = 0x0, /*!< MB/RxFIFO idle.*/
+    kFLEXCAN_StateRxData   = 0x1, /*!< MB receiving.*/
     kFLEXCAN_StateRxRemote = 0x2, /*!< MB receiving remote reply.*/
-    kFLEXCAN_StateTxData = 0x3,   /*!< MB transmitting.*/
+    kFLEXCAN_StateTxData   = 0x3, /*!< MB transmitting.*/
     kFLEXCAN_StateTxRemote = 0x4, /*!< MB transmitting remote request.*/
-    kFLEXCAN_StateRxFifo = 0x5,   /*!< RxFIFO receiving.*/
+    kFLEXCAN_StateRxFifo   = 0x5, /*!< RxFIFO receiving.*/
 };
 
 /*! @brief FlexCAN message buffer CODE for Rx buffers. */
 enum _flexcan_mb_code_rx
 {
     kFLEXCAN_RxMbInactive = 0x0, /*!< MB is not active.*/
-    kFLEXCAN_RxMbFull = 0x2,     /*!< MB is full.*/
-    kFLEXCAN_RxMbEmpty = 0x4,    /*!< MB is active and empty.*/
-    kFLEXCAN_RxMbOverrun = 0x6,  /*!< MB is overwritten into a full buffer.*/
-    kFLEXCAN_RxMbBusy = 0x8,     /*!< FlexCAN is updating the contents of the MB.*/
+    kFLEXCAN_RxMbFull     = 0x2, /*!< MB is full.*/
+    kFLEXCAN_RxMbEmpty    = 0x4, /*!< MB is active and empty.*/
+    kFLEXCAN_RxMbOverrun  = 0x6, /*!< MB is overwritten into a full buffer.*/
+    kFLEXCAN_RxMbBusy     = 0x8, /*!< FlexCAN is updating the contents of the MB.*/
                                  /*!  The CPU must not access the MB.*/
     kFLEXCAN_RxMbRanswer = 0xA,  /*!< A frame was configured to recognize a Remote Request Frame */
                                  /*!  and transmit a Response Frame in return.*/
@@ -72,8 +89,8 @@ enum _flexcan_mb_code_rx
 /*! @brief FlexCAN message buffer CODE FOR Tx buffers. */
 enum _flexcan_mb_code_tx
 {
-    kFLEXCAN_TxMbInactive = 0x8,     /*!< MB is not active.*/
-    kFLEXCAN_TxMbAbort = 0x9,        /*!< MB is aborted.*/
+    kFLEXCAN_TxMbInactive     = 0x8, /*!< MB is not active.*/
+    kFLEXCAN_TxMbAbort        = 0x9, /*!< MB is aborted.*/
     kFLEXCAN_TxMbDataOrRemote = 0xC, /*!< MB is a TX Data Frame(when MB RTR = 0) or */
                                      /*!< MB is a TX Remote Request Frame (when MB RTR = 1).*/
     kFLEXCAN_TxMbTanswer = 0xE,      /*!< MB is a TX Response Request Frame from */
@@ -118,7 +135,8 @@ static void FLEXCAN_ExitFreezeMode(CAN_Type *base);
 static bool FLEXCAN_IsMbOccupied(CAN_Type *base, uint8_t mbIdx);
 #endif
 
-#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641)
+#if ((defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) || \
+     (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829))
 /*!
  * @brief Get the first valid Message buffer ID of give FlexCAN instance.
  *
@@ -148,7 +166,7 @@ static bool FLEXCAN_IsMbIntEnabled(CAN_Type *base, uint8_t mbIdx);
  * after calling this API.
  *
  * @param base FlexCAN peripheral base address.
-*/
+ */
 static void FLEXCAN_Reset(CAN_Type *base);
 
 /*!
@@ -165,6 +183,15 @@ static void FLEXCAN_SetBaudRate(CAN_Type *base,
                                 uint32_t sourceClock_Hz,
                                 uint32_t baudRate_Bps,
                                 flexcan_timing_config_t timingConfig);
+/*!
+ * @brief Calculates the segment values for a single bit time for classical CAN
+ *
+ * @param baudRate The data speed in bps
+ * @param tqNum Number of time quantas per bit
+ * @param pconfig Pointer to the FlexCAN timing configuration structure.
+ *
+ */
+static void FLEXCAN_GetSegments(uint32_t baudRate, uint32_t tqNum, flexcan_timing_config_t *pconfig);
 
 #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
 /*!
@@ -177,7 +204,10 @@ static void FLEXCAN_SetBaudRate(CAN_Type *base,
  * @param baudRateFD_Bps FD frame Baud Rate in Bps.
  * @param timingConfig FlexCAN timingConfig.
  */
-static void FLEXCAN_SetFDBaudRate(CAN_Type *base, uint32_t sourceClock_Hz, uint32_t baudRateFD_Bps, flexcan_timing_config_t timingConfig);
+static void FLEXCAN_SetFDBaudRate(CAN_Type *base,
+                                  uint32_t sourceClock_Hz,
+                                  uint32_t baudRateFD_Bps,
+                                  flexcan_timing_config_t timingConfig);
 
 /*!
  * @brief Get Mailbox offset number by dword.
@@ -193,6 +223,26 @@ static void FLEXCAN_SetFDBaudRate(CAN_Type *base, uint32_t sourceClock_Hz, uint3
  * @param mbIdx Mailbox index.
  */
 static uint32_t FLEXCAN_GetFDMailboxOffset(CAN_Type *base, uint8_t mbIdx);
+
+/*!
+ * @brief Calculates the segment values for a single bit time for CANFD bus control baud Rate
+ *
+ * @param baudRate The canfd bus control speed in bps
+ * @param tqNum Number of time quanta per bit
+ * @param pconfig Pointer to the FlexCAN timing configuration structure.
+ *
+ */
+static void FLEXCAN_FDGetSegments(uint32_t baudRateFD, uint32_t tqNum, flexcan_timing_config_t *pconfig);
+/*!
+ * @brief Calculates the segment values for a single bit time for CANFD bus data baud Rate
+ *
+ * @param baudRate The canfd bus data speed in bps
+ * @param tqNum Number of time quanta per bit
+ * @param pconfig Pointer to the FlexCAN timing configuration structure.
+ *
+ */
+static void FLEXCAN_FDGetSegmentswithBRS(uint32_t baudRateFDbrs, uint32_t tqNum, flexcan_timing_config_t *pconfig);
+
 #endif
 
 /*******************************************************************************
@@ -205,10 +255,10 @@ static CAN_Type *const s_flexcanBases[] = CAN_BASE_PTRS;
 /* Array of FlexCAN IRQ number. */
 static const IRQn_Type s_flexcanRxWarningIRQ[] = CAN_Rx_Warning_IRQS;
 static const IRQn_Type s_flexcanTxWarningIRQ[] = CAN_Tx_Warning_IRQS;
-static const IRQn_Type s_flexcanWakeUpIRQ[] = CAN_Wake_Up_IRQS;
-static const IRQn_Type s_flexcanErrorIRQ[] = CAN_Error_IRQS;
-static const IRQn_Type s_flexcanBusOffIRQ[] = CAN_Bus_Off_IRQS;
-static const IRQn_Type s_flexcanMbIRQ[] = CAN_ORed_Message_buffer_IRQS;
+static const IRQn_Type s_flexcanWakeUpIRQ[]    = CAN_Wake_Up_IRQS;
+static const IRQn_Type s_flexcanErrorIRQ[]     = CAN_Error_IRQS;
+static const IRQn_Type s_flexcanBusOffIRQ[]    = CAN_Bus_Off_IRQS;
+static const IRQn_Type s_flexcanMbIRQ[]        = CAN_ORed_Message_buffer_IRQS;
 
 /* Array of FlexCAN handle. */
 static flexcan_handle_t *s_flexcanHandle[ARRAY_SIZE(s_flexcanBases)];
@@ -229,6 +279,12 @@ static flexcan_isr_t s_flexcanIsr;
  * Code
  ******************************************************************************/
 
+/*!
+ * brief Get the FlexCAN instance from peripheral base address.
+ *
+ * param base FlexCAN peripheral base address.
+ * return FlexCAN instance.
+ */
 uint32_t FLEXCAN_GetInstance(CAN_Type *base)
 {
     uint32_t instance;
@@ -247,17 +303,93 @@ uint32_t FLEXCAN_GetInstance(CAN_Type *base)
     return instance;
 }
 
+#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_9595) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_9595)
+static void FLEXCAN_EnterFreezeMode(CAN_Type *base)
+{
+    uint32_t u32TimeoutCount = 0U;
+    uint32_t u32TempMCR      = 0U;
+    uint32_t u32TempIMASK1   = 0U;
+#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0)
+    uint32_t u32TempIMASK2 = 0U;
+#endif
+
+    /* Step1: set FRZ enable in MCR. */
+    base->MCR |= CAN_MCR_FRZ_MASK;
+
+    /* Step2: to check if MDIS bit set in MCR. if yes, clear it. */
+    if (0U != (base->MCR & CAN_MCR_MDIS_MASK))
+    {
+        base->MCR &= ~CAN_MCR_MDIS_MASK;
+    }
+
+    /* Step3: polling LPMACK. */
+    u32TimeoutCount = (uint32_t)FLEXCAN_WAIT_TIMEOUT;
+    while ((0U == (base->MCR & CAN_MCR_LPMACK_MASK)) && (u32TimeoutCount > 0U))
+    {
+        u32TimeoutCount--;
+    }
+
+    /* Step4: to check FLTCONF in ESR1 register */
+    if (0U == (base->ESR1 & CAN_ESR1_FLTCONF_BUSOFF))
+    {
+        /* Step5B: Set Halt bits. */
+        base->MCR |= CAN_MCR_HALT_MASK;
+
+        /* Step6B: Poll the MCR register until the Freeze Acknowledge (FRZACK) bit is set, timeout need more than 178
+         * CAN bit length, so 20 multiply timeout is enough. */
+        u32TimeoutCount = (uint32_t)FLEXCAN_WAIT_TIMEOUT * 20U;
+        while ((0U == (base->MCR & CAN_MCR_FRZACK_MASK)) && (u32TimeoutCount > 0U))
+        {
+            u32TimeoutCount--;
+        }
+    }
+    else
+    {
+        /* backup MCR and IMASK register. Errata document not descript it, but we need backup for step 8A and 9A. */
+        u32TempMCR    = base->MCR;
+        u32TempIMASK1 = base->IMASK1;
+#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0)
+        u32TempIMASK2 = base->IMASK2;
+#endif
+
+        /* Step5A: Set the Soft Reset bit ((SOFTRST) in the MCR.*/
+        base->MCR |= CAN_MCR_SOFTRST_MASK;
+
+        /* Step6A: Poll the MCR register until the Soft Reset (SOFTRST) bit is cleared. */
+        u32TimeoutCount = (uint32_t)FLEXCAN_WAIT_TIMEOUT;
+        while ((CAN_MCR_SOFTRST_MASK == (base->MCR & CAN_MCR_SOFTRST_MASK)) && (u32TimeoutCount > 0U))
+        {
+            u32TimeoutCount--;
+        }
+
+        /* Step7A: Poll the MCR register until the Freeze Acknowledge (FRZACK) bit is set. */
+        u32TimeoutCount = (uint32_t)FLEXCAN_WAIT_TIMEOUT;
+        while ((0U == (base->MCR & CAN_MCR_FRZACK_MASK)) && (u32TimeoutCount > 0U))
+        {
+            u32TimeoutCount--;
+        }
+
+        /* Step8A: reconfig MCR. */
+        base->MCR = u32TempMCR;
+
+        /* Step9A: reconfig IMASK. */
+        base->IMASK1 = u32TempIMASK1;
+#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0)
+        base->IMASK2 = u32TempIMASK2;
+#endif
+    }
+}
+#else
 static void FLEXCAN_EnterFreezeMode(CAN_Type *base)
 {
     /* Set Freeze, Halt bits. */
     base->MCR |= CAN_MCR_FRZ_MASK;
     base->MCR |= CAN_MCR_HALT_MASK;
-
-    /* Wait until the FlexCAN Module enter freeze mode. */
-    while (!(base->MCR & CAN_MCR_FRZACK_MASK))
+    while (0U == (base->MCR & CAN_MCR_FRZACK_MASK))
     {
     }
 }
+#endif
 
 static void FLEXCAN_ExitFreezeMode(CAN_Type *base)
 {
@@ -266,7 +398,7 @@ static void FLEXCAN_ExitFreezeMode(CAN_Type *base)
     base->MCR &= ~CAN_MCR_FRZ_MASK;
 
     /* Wait until the FlexCAN Module exit freeze mode. */
-    while (base->MCR & CAN_MCR_FRZACK_MASK)
+    while (0U != (base->MCR & CAN_MCR_FRZACK_MASK))
     {
     }
 }
@@ -280,12 +412,13 @@ static bool FLEXCAN_IsMbOccupied(CAN_Type *base, uint8_t mbIdx)
     if (base->MCR & CAN_MCR_RFEN_MASK)
     {
         /* Get RFFN value. */
-        lastOccupiedMb = ((base->CTRL2 & CAN_CTRL2_RFFN_MASK) >> CAN_CTRL2_RFFN_SHIFT);
+        lastOccupiedMb = (uint8_t)((base->CTRL2 & CAN_CTRL2_RFFN_MASK) >> CAN_CTRL2_RFFN_SHIFT);
         /* Calculate the number of last Message Buffer occupied by Rx FIFO. */
-        lastOccupiedMb = ((lastOccupiedMb + 1) * 2) + 5;
+        lastOccupiedMb = ((lastOccupiedMb + 1U) * 2U) + 5U;
 
-#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641)
-        if (mbIdx <= (lastOccupiedMb + 1))
+#if ((defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) || \
+     (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829))
+        if (mbIdx <= (lastOccupiedMb + 1U))
 #else
         if (mbIdx <= lastOccupiedMb)
 #endif
@@ -299,8 +432,9 @@ static bool FLEXCAN_IsMbOccupied(CAN_Type *base, uint8_t mbIdx)
     }
     else
     {
-#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641)
-        if (0 == mbIdx)
+#if ((defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) || \
+     (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829))
+        if (0U == mbIdx)
         {
             return true;
         }
@@ -315,7 +449,8 @@ static bool FLEXCAN_IsMbOccupied(CAN_Type *base, uint8_t mbIdx)
 }
 #endif
 
-#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641)
+#if ((defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) || \
+     (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829))
 static uint32_t FLEXCAN_GetFirstValidMb(CAN_Type *base)
 {
     uint32_t firstValidMbNum;
@@ -323,7 +458,7 @@ static uint32_t FLEXCAN_GetFirstValidMb(CAN_Type *base)
     if (base->MCR & CAN_MCR_RFEN_MASK)
     {
         firstValidMbNum = ((base->CTRL2 & CAN_CTRL2_RFFN_MASK) >> CAN_CTRL2_RFFN_SHIFT);
-        firstValidMbNum = ((firstValidMbNum + 1) * 2) + 6;
+        firstValidMbNum = ((firstValidMbNum + 1U) * 2U) + 6U;
     }
     else
     {
@@ -337,13 +472,13 @@ static uint32_t FLEXCAN_GetFirstValidMb(CAN_Type *base)
 static bool FLEXCAN_IsMbIntEnabled(CAN_Type *base, uint8_t mbIdx)
 {
     /* Assertion. */
-    assert(mbIdx < FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base));
+    assert(mbIdx < (uint8_t)FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base));
 
 #if (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0)
-    if (mbIdx < 32)
+    if (mbIdx < 32U)
     {
 #endif
-        if (base->IMASK1 & ((uint32_t)(1 << mbIdx)))
+        if (0U != (base->IMASK1 & (((uint32_t)1U << mbIdx))))
         {
             return true;
         }
@@ -355,7 +490,7 @@ static bool FLEXCAN_IsMbIntEnabled(CAN_Type *base, uint8_t mbIdx)
     }
     else
     {
-        if (base->IMASK2 & ((uint32_t)(1 << (mbIdx - 32))))
+        if (base->IMASK2 & (1U << (mbIdx - 32U)))
         {
             return true;
         }
@@ -372,28 +507,31 @@ static void FLEXCAN_Reset(CAN_Type *base)
     /* The module must should be first exit from low power
      * mode, and then soft reset can be applied.
      */
-    assert(!(base->MCR & CAN_MCR_MDIS_MASK));
+    assert(0U == (base->MCR & CAN_MCR_MDIS_MASK));
 
     uint8_t i;
 
-#if (FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT != 0)
-    /* De-assert DOZE Enable Bit. */
-    base->MCR &= ~CAN_MCR_DOZE_MASK;
+#if (defined(FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT) && FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT)
+    if (0 != (FSL_FEATURE_FLEXCAN_INSTANCE_HAS_DOZE_MODE_SUPPORTn(base)))
+    {
+        /* De-assert DOZE Enable Bit. */
+        base->MCR &= ~CAN_MCR_DOZE_MASK;
+    }
 #endif
 
     /* Wait until FlexCAN exit from any Low Power Mode. */
-    while (base->MCR & CAN_MCR_LPMACK_MASK)
+    while (0U != (base->MCR & CAN_MCR_LPMACK_MASK))
     {
     }
 
     /* Assert Soft Reset Signal. */
     base->MCR |= CAN_MCR_SOFTRST_MASK;
     /* Wait until FlexCAN reset completes. */
-    while (base->MCR & CAN_MCR_SOFTRST_MASK)
+    while (0U != (base->MCR & CAN_MCR_SOFTRST_MASK))
     {
     }
 
-/* Reset MCR rigister. */
+/* Reset MCR register. */
 #if (defined(FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER) && FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER)
     base->MCR |= CAN_MCR_WRNEN_MASK | CAN_MCR_WAKSRC_MASK |
                  CAN_MCR_MAXMB(FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base) - 1);
@@ -401,12 +539,24 @@ static void FLEXCAN_Reset(CAN_Type *base)
     base->MCR |= CAN_MCR_WRNEN_MASK | CAN_MCR_MAXMB(FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base) - 1);
 #endif
 
-    /* Reset CTRL1 and CTRL2 rigister. */
+/* Reset CTRL1 and CTRL2 register. */
+#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
+    /* SMP bit cannot be asserted when CAN FD is enabled */
+    if (0 != FSL_FEATURE_FLEXCAN_INSTANCE_HAS_FLEXIBLE_DATA_RATEn(base))
+    {
+        base->CTRL1 = 0x0;
+    }
+    else
+    {
+        base->CTRL1 = CAN_CTRL1_SMP_MASK;
+    }
+#else
     base->CTRL1 = CAN_CTRL1_SMP_MASK;
+#endif
     base->CTRL2 = CAN_CTRL2_TASD(0x16) | CAN_CTRL2_RRS_MASK | CAN_CTRL2_EACEN_MASK;
 
     /* Clean all individual Rx Mask of Message Buffers. */
-    for (i = 0; i < FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base); i++)
+    for (i = 0; i < (uint32_t)FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base); i++)
     {
         base->RXIMR[i] = 0x3FFFFFFF;
     }
@@ -421,7 +571,7 @@ static void FLEXCAN_Reset(CAN_Type *base)
     base->RXFGMASK = 0x3FFFFFFF;
 
     /* Clean all Message Buffer CS fields. */
-    for (i = 0; i < FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base); i++)
+    for (i = 0; i < (uint32_t)FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base); i++)
     {
         base->MB[i].CS = 0x0;
     }
@@ -435,31 +585,32 @@ static void FLEXCAN_SetBaudRate(CAN_Type *base,
     /* FlexCAN timing setting formula:
      * quantum = 1 + (PSEG1 + 1) + (PSEG2 + 1) + (PROPSEG + 1);
      */
-    uint32_t quantum = 1 + (timingConfig.phaseSeg1 + 1) + (timingConfig.phaseSeg2 + 1) + (timingConfig.propSeg + 1);
-    uint32_t priDiv = baudRate_Bps * quantum;
+    uint32_t quantum = (1U + ((uint32_t)timingConfig.phaseSeg1 + 1U) + ((uint32_t)timingConfig.phaseSeg2 + 1U) +
+                        ((uint32_t)timingConfig.propSeg + 1U));
+    uint32_t priDiv  = baudRate_Bps * quantum;
 
     /* Assertion: Desired baud rate is too high. */
     assert(baudRate_Bps <= 1000000U);
     /* Assertion: Source clock should greater than baud rate * quantum. */
     assert(priDiv <= sourceClock_Hz);
 
-    if (0 == priDiv)
+    if (0U == priDiv)
     {
         priDiv = 1;
     }
 
-    priDiv = (sourceClock_Hz / priDiv) - 1;
+    priDiv = (sourceClock_Hz / priDiv) - 1U;
 
     /* Desired baud rate is too low. */
-    if (priDiv > 0xFF)
+    if (priDiv > 0xFFU)
     {
         priDiv = 0xFF;
     }
 
-    timingConfig.preDivider = priDiv;
+    timingConfig.preDivider = (uint16_t)priDiv;
 
     /* Update actual timing characteristic. */
-    FLEXCAN_SetTimingConfig(base, &timingConfig);
+    FLEXCAN_SetTimingConfig(base, (const flexcan_timing_config_t *)(uint32_t)&timingConfig);
 }
 
 #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
@@ -471,34 +622,58 @@ static void FLEXCAN_SetFDBaudRate(CAN_Type *base,
     /* FlexCAN FD timing setting formula:
      * quantum = 1 + (FPSEG1 + 1) + (FPSEG2 + 1) + FPROPSEG;
      */
-    uint32_t quantum = 1 + (timingConfig.fphaseSeg1 + 1) + (timingConfig.fphaseSeg2 + 1) + timingConfig.fpropSeg;
-    uint32_t priDiv = baudRateFD_Bps * quantum;
+    uint32_t quantum = (1U + ((uint32_t)timingConfig.fphaseSeg1 + 1U) + ((uint32_t)timingConfig.fphaseSeg2 + 1U) +
+                        (uint32_t)timingConfig.fpropSeg);
+    uint32_t priDiv  = baudRateFD_Bps * quantum;
 
     /* Assertion: Desired baud rate is too high. */
     assert(baudRateFD_Bps <= 8000000U);
     /* Assertion: Source clock should greater than baud rate * FLEXCAN_TIME_QUANTA_NUM. */
     assert(priDiv <= sourceClock_Hz);
 
-    if (0 == priDiv)
+    if (0U == priDiv)
     {
         priDiv = 1;
     }
 
-    priDiv = (sourceClock_Hz / priDiv) - 1;
+    priDiv = (sourceClock_Hz / priDiv) - 1U;
 
     /* Desired baud rate is too low. */
-    if (priDiv > 0xFF)
+    if (priDiv > 0xFFU)
     {
         priDiv = 0xFF;
     }
 
-    timingConfig.fpreDivider = priDiv;
+    timingConfig.fpreDivider = (uint16_t)priDiv;
 
     /* Update actual timing characteristic. */
-    FLEXCAN_SetFDTimingConfig(base, &timingConfig);
+    FLEXCAN_SetFDTimingConfig(base, (const flexcan_timing_config_t *)(uint32_t)&timingConfig);
 }
 #endif
 
+/*!
+ * brief Initializes a FlexCAN instance.
+ *
+ * This function initializes the FlexCAN module with user-defined settings.
+ * This example shows how to set up the flexcan_config_t parameters and how
+ * to call the FLEXCAN_Init function by passing in these parameters.
+ *  code
+ *   flexcan_config_t flexcanConfig;
+ *   flexcanConfig.clkSrc            = kFLEXCAN_ClkSrcOsc;
+ *   flexcanConfig.baudRate          = 1000000U;
+ *   flexcanConfig.maxMbNum          = 16;
+ *   flexcanConfig.enableLoopBack    = false;
+ *   flexcanConfig.enableSelfWakeup  = false;
+ *   flexcanConfig.enableIndividMask = false;
+ *   flexcanConfig.enableDoze        = false;
+ *   flexcanConfig.timingConfig      = timingConfig;
+ *   FLEXCAN_Init(CAN0, &flexcanConfig, 8000000UL);
+ *   endcode
+ *
+ * param base FlexCAN peripheral base address.
+ * param config Pointer to the user-defined configuration structure.
+ * param sourceClock_Hz FlexCAN Protocol Engine clock source frequency in Hz.
+ */
 void FLEXCAN_Init(CAN_Type *base, const flexcan_config_t *config, uint32_t sourceClock_Hz)
 {
     uint32_t mcrTemp;
@@ -507,8 +682,9 @@ void FLEXCAN_Init(CAN_Type *base, const flexcan_config_t *config, uint32_t sourc
 #endif
 
     /* Assertion. */
-    assert(config);
-    assert((config->maxMbNum > 0) && (config->maxMbNum <= FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base)));
+    assert(NULL != config);
+    assert((config->maxMbNum > 0U) &&
+           (config->maxMbNum <= (uint8_t)FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base)));
 
 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     instance = FLEXCAN_GetInstance(base);
@@ -527,11 +703,25 @@ void FLEXCAN_Init(CAN_Type *base, const flexcan_config_t *config, uint32_t sourc
     /* Protocol-Engine clock source selection, This bit must be set
      * when FlexCAN Module in Disable Mode.
      */
-    base->CTRL1 = (kFLEXCAN_ClkSrcOsc == config->clkSrc) ? base->CTRL1 & ~CAN_CTRL1_CLKSRC_MASK :
-                                                           base->CTRL1 | CAN_CTRL1_CLKSRC_MASK;
+    base->CTRL1 = (kFLEXCAN_ClkSrcOsc == config->clkSrc) ? (base->CTRL1 & ~CAN_CTRL1_CLKSRC_MASK) :
+                                                           (base->CTRL1 | CAN_CTRL1_CLKSRC_MASK);
+#else
+#if defined(CAN_CTRL1_CLKSRC_MASK)
+    if (!FSL_FEATURE_FLEXCAN_INSTANCE_SUPPORT_ENGINE_CLK_SEL_REMOVEn(base))
+    {
+        /* Disable FlexCAN Module. */
+        FLEXCAN_Enable(base, false);
+
+        /* Protocol-Engine clock source selection, This bit must be set
+         * when FlexCAN Module in Disable Mode.
+         */
+        base->CTRL1 = (kFLEXCAN_ClkSrcOsc == config->clkSrc) ? (base->CTRL1 & ~CAN_CTRL1_CLKSRC_MASK) :
+                                                               (base->CTRL1 | CAN_CTRL1_CLKSRC_MASK);
+    }
+#endif
 #endif /* FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE */
 
-    /* Enable FlexCAN Module for configuartion. */
+    /* Enable FlexCAN Module for configuration. */
     FLEXCAN_Enable(base, true);
 
     /* Reset to known status. */
@@ -541,32 +731,130 @@ void FLEXCAN_Init(CAN_Type *base, const flexcan_config_t *config, uint32_t sourc
     mcrTemp = base->MCR;
 
     /* Set the maximum number of Message Buffers */
-    mcrTemp = (mcrTemp & ~CAN_MCR_MAXMB_MASK) | CAN_MCR_MAXMB(config->maxMbNum - 1);
+    mcrTemp = (mcrTemp & ~CAN_MCR_MAXMB_MASK) | CAN_MCR_MAXMB((uint32_t)config->maxMbNum - 1U);
 
     /* Enable Loop Back Mode? */
-    base->CTRL1 = (config->enableLoopBack) ? base->CTRL1 | CAN_CTRL1_LPB_MASK : base->CTRL1 & ~CAN_CTRL1_LPB_MASK;
+    base->CTRL1 =
+        (true == config->enableLoopBack) ? (base->CTRL1 | CAN_CTRL1_LPB_MASK) : (base->CTRL1 & ~CAN_CTRL1_LPB_MASK);
+
+    /* Enable Timer Sync? */
+    base->CTRL1 =
+        (true == config->enableTimerSync) ? (base->CTRL1 | CAN_CTRL1_TSYN_MASK) : (base->CTRL1 & ~CAN_CTRL1_TSYN_MASK);
 
-    /* Enable Self Wake Up Mode? */
-    mcrTemp = (config->enableSelfWakeup) ? mcrTemp | CAN_MCR_SLFWAK_MASK : mcrTemp & ~CAN_MCR_SLFWAK_MASK;
+    /* Enable Self Wake Up Mode and configure the wake up source. */
+    mcrTemp = (true == config->enableSelfWakeup) ? (mcrTemp | CAN_MCR_SLFWAK_MASK) : (mcrTemp & ~CAN_MCR_SLFWAK_MASK);
+    mcrTemp = (kFLEXCAN_WakeupSrcFiltered == config->wakeupSrc) ? (mcrTemp | CAN_MCR_WAKSRC_MASK) :
+                                                                  (mcrTemp & ~CAN_MCR_WAKSRC_MASK);
 
     /* Enable Individual Rx Masking? */
-    mcrTemp = (config->enableIndividMask) ? mcrTemp | CAN_MCR_IRMQ_MASK : mcrTemp & ~CAN_MCR_IRMQ_MASK;
+    mcrTemp = (true == config->enableIndividMask) ? (mcrTemp | CAN_MCR_IRMQ_MASK) : (mcrTemp & ~CAN_MCR_IRMQ_MASK);
 
 #if (defined(FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT) && FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT)
-    /* Enable Doze Mode? */
-    mcrTemp = (config->enableDoze) ? mcrTemp | CAN_MCR_DOZE_MASK : mcrTemp & ~CAN_MCR_DOZE_MASK;
+    if (0 != FSL_FEATURE_FLEXCAN_INSTANCE_HAS_DOZE_MODE_SUPPORTn(base))
+    {
+        /* Enable Doze Mode? */
+        mcrTemp = (true == config->enableDoze) ? (mcrTemp | CAN_MCR_DOZE_MASK) : (mcrTemp & ~CAN_MCR_DOZE_MASK);
+    }
 #endif
 
-    /* Save MCR Configuation. */
+    /* Save MCR Configuration. */
     base->MCR = mcrTemp;
 
     /* Baud Rate Configuration.*/
     FLEXCAN_SetBaudRate(base, sourceClock_Hz, config->baudRate, config->timingConfig);
+}
+
 #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
+/*!
+ * brief Initializes a FlexCAN instance.
+ *
+ * This function initializes the FlexCAN module with user-defined settings.
+ * This example shows how to set up the flexcan_config_t parameters and how
+ * to call the FLEXCAN_FDInit function by passing in these parameters.
+ *  code
+ *   flexcan_config_t flexcanConfig;
+ *   flexcanConfig.clkSrc            = kFLEXCAN_ClkSrcOsc;
+ *   flexcanConfig.baudRate          = 1000000U;
+ *   flexcanConfig.baudRateFD        = 2000000U;
+ *   flexcanConfig.maxMbNum          = 16;
+ *   flexcanConfig.enableLoopBack    = false;
+ *   flexcanConfig.enableSelfWakeup  = false;
+ *   flexcanConfig.enableIndividMask = false;
+ *   flexcanConfig.enableDoze        = false;
+ *   flexcanConfig.timingConfig      = timingConfig;
+ *   FLEXCAN_FDInit(CAN0, &flexcanConfig, 8000000UL, kFLEXCAN_16BperMB, false);
+ *   endcode
+ *
+ * param base FlexCAN peripheral base address.
+ * param config Pointer to the user-defined configuration structure.
+ * param sourceClock_Hz FlexCAN Protocol Engine clock source frequency in Hz.
+ * param dataSize FlexCAN FD frame payload size.
+ * param brs If bitrate switch is enabled in FD mode.
+ */
+void FLEXCAN_FDInit(
+    CAN_Type *base, const flexcan_config_t *config, uint32_t sourceClock_Hz, flexcan_mb_size_t dataSize, bool brs)
+{
+    uint32_t fdctrl = 0U;
+    assert((uint32_t)dataSize <= 3U);
+
+    /* Initialization of classical CAN. */
+    FLEXCAN_Init(base, config, sourceClock_Hz);
+
+    /* Extra bitrate setting for CANFD. */
     FLEXCAN_SetFDBaudRate(base, sourceClock_Hz, config->baudRateFD, config->timingConfig);
+
+    /* read FDCTRL register. */
+    fdctrl = base->FDCTRL;
+
+    /* Enable FD operation and set bitrate switch. */
+    if (brs)
+    {
+        fdctrl &= CAN_FDCTRL_FDRATE_MASK;
+    }
+    else
+    {
+        fdctrl &= ~CAN_FDCTRL_FDRATE_MASK;
+    }
+
+    if ((true == brs) && (false == config->enableLoopBack))
+    {
+        /* Before use "|=" operation for multi-bits field, CPU should Clean previous Setting. */
+        fdctrl = (fdctrl & ~CAN_FDCTRL_TDCOFF_MASK) | CAN_FDCTRL_TDCOFF(0x2U);
+    }
+
+    /* Before use "|=" operation for multi-bits field, CPU should clean previous Setting. */
+    fdctrl = (fdctrl & ~CAN_FDCTRL_MBDSR0_MASK) | CAN_FDCTRL_MBDSR0(dataSize);
+#if defined(CAN_FDCTRL_MBDSR1_MASK)
+    fdctrl = (fdctrl & ~CAN_FDCTRL_MBDSR1_MASK) | CAN_FDCTRL_MBDSR1(dataSize);
 #endif
+#if defined(CAN_FDCTRL_MBDSR2_MASK)
+    fdctrl = (fdctrl & ~CAN_FDCTRL_MBDSR2_MASK) | CAN_FDCTRL_MBDSR2(dataSize);
+#endif
+#if defined(CAN_FDCTRL_MBDSR3_MASK)
+    fdctrl = (fdctrl & ~CAN_FDCTRL_MBDSR3_MASK) | CAN_FDCTRL_MBDSR3(dataSize);
+#endif
+
+    /* Enter Freeze Mode. */
+    FLEXCAN_EnterFreezeMode(base);
+
+    base->MCR |= CAN_MCR_FDEN_MASK;
+
+    /* update the FDCTL register. */
+    base->FDCTRL = fdctrl;
+
+    /* Exit Freeze Mode. */
+    FLEXCAN_ExitFreezeMode(base);
 }
+#endif
 
+/*!
+ * brief De-initializes a FlexCAN instance.
+ *
+ * This function disables the FlexCAN module clock and sets all register values
+ * to the reset value.
+ *
+ * param base FlexCAN peripheral base address.
+ */
 void FLEXCAN_Deinit(CAN_Type *base)
 {
 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
@@ -589,85 +877,104 @@ void FLEXCAN_Deinit(CAN_Type *base)
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }
 
+/*!
+ * brief Gets the default configuration structure.
+ *
+ * This function initializes the FlexCAN configuration structure to default values. The default
+ * values are as follows.
+ *   flexcanConfig->clkSrc            = kFLEXCAN_ClkSrcOsc;
+ *   flexcanConfig->baudRate          = 1000000U;
+ *   flexcanConfig->baudRateFD        = 2000000U;
+ *   flexcanConfig->maxMbNum          = 16;
+ *   flexcanConfig->enableLoopBack    = false;
+ *   flexcanConfig->enableSelfWakeup  = false;
+ *   flexcanConfig->enableIndividMask = false;
+ *   flexcanConfig->enableDoze        = false;
+ *   flexcanConfig.timingConfig       = timingConfig;
+ *
+ * param config Pointer to the FlexCAN configuration structure.
+ */
 void FLEXCAN_GetDefaultConfig(flexcan_config_t *config)
 {
     /* Assertion. */
-    assert(config);
+    assert(NULL != config);
+
+    /* Initializes the configure structure to zero. */
+    (void)memset(config, 0, sizeof(*config));
 
     /* Initialize FlexCAN Module config struct with default value. */
-#if (!defined(FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE)) || !FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE
-    config->clkSrc = kFLEXCAN_ClkSrcOsc;
-#endif /* FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE */
+    config->clkSrc   = kFLEXCAN_ClkSrcOsc;
     config->baudRate = 1000000U;
 #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
-    config->baudRateFD = 1000000U;
+    config->baudRateFD = 2000000U;
 #endif
-    config->maxMbNum = 16;
-    config->enableLoopBack = false;
-    config->enableSelfWakeup = false;
+    config->maxMbNum          = 16;
+    config->enableLoopBack    = false;
+    config->enableTimerSync   = true;
+    config->enableSelfWakeup  = false;
+    config->wakeupSrc         = kFLEXCAN_WakeupSrcUnfiltered;
     config->enableIndividMask = false;
 #if (defined(FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT) && FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT)
     config->enableDoze = false;
 #endif
     /* Default protocol timing configuration, time quantum is 10. */
-    config->timingConfig.phaseSeg1 = 3;
-    config->timingConfig.phaseSeg2 = 2;
-    config->timingConfig.propSeg = 1;
+    config->timingConfig.phaseSeg1  = 3;
+    config->timingConfig.phaseSeg2  = 2;
+    config->timingConfig.propSeg    = 1;
     config->timingConfig.rJumpwidth = 1;
 #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
-    config->timingConfig.fphaseSeg1 = 3;
-    config->timingConfig.fphaseSeg2 = 3;
-    config->timingConfig.fpropSeg = 1;
+    config->timingConfig.fphaseSeg1  = 3;
+    config->timingConfig.fphaseSeg2  = 3;
+    config->timingConfig.fpropSeg    = 1;
     config->timingConfig.frJumpwidth = 1;
 #endif
 }
 
-#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
-void FLEXCAN_FDEnable(CAN_Type *base, flexcan_mb_size_t dataSize, bool brs)
-{
-    if (brs)
-    {
-        base->FDCTRL &= CAN_FDCTRL_FDRATE_MASK;
-    }
-    else
-    {
-        base->FDCTRL &= ~CAN_FDCTRL_FDRATE_MASK;
-    }
-    /* Enter Freeze Mode. */
-    FLEXCAN_EnterFreezeMode(base);
-    base->MCR |= CAN_MCR_FDEN_MASK;
-    base->FDCTRL |= CAN_FDCTRL_MBDSR0(dataSize);
-#if defined(CAN_FDCTRL_MBDSR1_MASK)
-    base->FDCTRL |= CAN_FDCTRL_MBDSR1(dataSize);
-#endif
-#if defined(CAN_FDCTRL_MBDSR2_MASK)
-    base->FDCTRL |= CAN_FDCTRL_MBDSR2(dataSize);
-#endif
-#if defined(CAN_FDCTRL_MBDSR3_MASK)
-    base->FDCTRL |= CAN_FDCTRL_MBDSR3(dataSize);
-#endif
-    /* Exit Freeze Mode. */
-    FLEXCAN_ExitFreezeMode(base);
-}
-#endif
-
+/*!
+ * brief Sets the FlexCAN protocol timing characteristic.
+ *
+ * This function gives user settings to CAN bus timing characteristic.
+ * The function is for an experienced user. For less experienced users, call
+ * the FLEXCAN_Init() and fill the baud rate field with a desired value.
+ * This provides the default timing characteristics to the module.
+ *
+ * Note that calling FLEXCAN_SetTimingConfig() overrides the baud rate set
+ * in FLEXCAN_Init().
+ *
+ * param base FlexCAN peripheral base address.
+ * param config Pointer to the timing configuration structure.
+ */
 void FLEXCAN_SetTimingConfig(CAN_Type *base, const flexcan_timing_config_t *config)
 {
     /* Assertion. */
-    assert(config);
+    assert(NULL != config);
 
     /* Enter Freeze Mode. */
     FLEXCAN_EnterFreezeMode(base);
 
 #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
-    /* Cleaning previous Timing Setting. */
-    base->CBT &= ~(CAN_CBT_EPRESDIV_MASK | CAN_CBT_ERJW_MASK | CAN_CBT_EPSEG1_MASK | CAN_CBT_EPSEG2_MASK |
-                   CAN_CBT_EPROPSEG_MASK);
+    if (0 != FSL_FEATURE_FLEXCAN_INSTANCE_HAS_FLEXIBLE_DATA_RATEn(base))
+    {
+        /* Cleaning previous Timing Setting. */
+        base->CBT &= ~(CAN_CBT_EPRESDIV_MASK | CAN_CBT_ERJW_MASK | CAN_CBT_EPSEG1_MASK | CAN_CBT_EPSEG2_MASK |
+                       CAN_CBT_EPROPSEG_MASK);
 
-    /* Updating Timing Setting according to configuration structure. */
-    base->CBT |=
-        (CAN_CBT_EPRESDIV(config->preDivider) | CAN_CBT_ERJW(config->rJumpwidth) | CAN_CBT_EPSEG1(config->phaseSeg1) |
-         CAN_CBT_EPSEG2(config->phaseSeg2) | CAN_CBT_EPROPSEG(config->propSeg));
+        /* Updating Timing Setting according to configuration structure. */
+        base->CBT |=
+            (CAN_CBT_EPRESDIV(config->preDivider) | CAN_CBT_ERJW(config->rJumpwidth) |
+             CAN_CBT_EPSEG1(config->phaseSeg1) | CAN_CBT_EPSEG2(config->phaseSeg2) | CAN_CBT_EPROPSEG(config->propSeg));
+    }
+    else
+    {
+        /* Cleaning previous Timing Setting. */
+        base->CTRL1 &= ~(CAN_CTRL1_PRESDIV_MASK | CAN_CTRL1_RJW_MASK | CAN_CTRL1_PSEG1_MASK | CAN_CTRL1_PSEG2_MASK |
+                         CAN_CTRL1_PROPSEG_MASK);
+
+        /* Updating Timing Setting according to configuration structure. */
+        base->CTRL1 |= (CAN_CTRL1_PRESDIV(config->preDivider) | CAN_CTRL1_RJW(config->rJumpwidth) |
+                        CAN_CTRL1_PSEG1(config->phaseSeg1) | CAN_CTRL1_PSEG2(config->phaseSeg2) |
+                        CAN_CTRL1_PROPSEG(config->propSeg));
+    }
 #else
     /* Cleaning previous Timing Setting. */
     base->CTRL1 &= ~(CAN_CTRL1_PRESDIV_MASK | CAN_CTRL1_RJW_MASK | CAN_CTRL1_PSEG1_MASK | CAN_CTRL1_PSEG2_MASK |
@@ -684,10 +991,24 @@ void FLEXCAN_SetTimingConfig(CAN_Type *base, const flexcan_timing_config_t *conf
 }
 
 #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
+/*!
+ * brief Sets the FlexCAN FD protocol timing characteristic.
+ *
+ * This function gives user settings to CAN bus timing characteristic.
+ * The function is for an experienced user. For less experienced users, call
+ * the FLEXCAN_Init() and fill the baud rate field with a desired value.
+ * This provides the default timing characteristics to the module.
+ *
+ * Note that calling FLEXCAN_SetFDTimingConfig() overrides the baud rate set
+ * in FLEXCAN_Init().
+ *
+ * param base FlexCAN peripheral base address.
+ * param config Pointer to the timing configuration structure.
+ */
 void FLEXCAN_SetFDTimingConfig(CAN_Type *base, const flexcan_timing_config_t *config)
 {
     /* Assertion. */
-    assert(config);
+    assert(NULL != config);
 
     /* Enter Freeze Mode. */
     FLEXCAN_EnterFreezeMode(base);
@@ -707,6 +1028,15 @@ void FLEXCAN_SetFDTimingConfig(CAN_Type *base, const flexcan_timing_config_t *co
 }
 #endif
 
+/*!
+ * brief Sets the FlexCAN receive message buffer global mask.
+ *
+ * This function sets the global mask for the FlexCAN message buffer in a matching process.
+ * The configuration is only effective when the Rx individual mask is disabled in the FLEXCAN_Init().
+ *
+ * param base FlexCAN peripheral base address.
+ * param mask Rx Message Buffer Global Mask value.
+ */
 void FLEXCAN_SetRxMbGlobalMask(CAN_Type *base, uint32_t mask)
 {
     /* Enter Freeze Mode. */
@@ -721,6 +1051,14 @@ void FLEXCAN_SetRxMbGlobalMask(CAN_Type *base, uint32_t mask)
     FLEXCAN_ExitFreezeMode(base);
 }
 
+/*!
+ * brief Sets the FlexCAN receive FIFO global mask.
+ *
+ * This function sets the global mask for FlexCAN FIFO in a matching process.
+ *
+ * param base FlexCAN peripheral base address.
+ * param mask Rx Fifo Global Mask value.
+ */
 void FLEXCAN_SetRxFifoGlobalMask(CAN_Type *base, uint32_t mask)
 {
     /* Enter Freeze Mode. */
@@ -733,6 +1071,20 @@ void FLEXCAN_SetRxFifoGlobalMask(CAN_Type *base, uint32_t mask)
     FLEXCAN_ExitFreezeMode(base);
 }
 
+/*!
+ * brief Sets the FlexCAN receive individual mask.
+ *
+ * This function sets the individual mask for the FlexCAN matching process.
+ * The configuration is only effective when the Rx individual mask is enabled in the FLEXCAN_Init().
+ * If the Rx FIFO is disabled, the individual mask is applied to the corresponding Message Buffer.
+ * If the Rx FIFO is enabled, the individual mask for Rx FIFO occupied Message Buffer is applied to
+ * the Rx Filter with the same index. Note that only the first 32
+ * individual masks can be used as the Rx FIFO filter mask.
+ *
+ * param base FlexCAN peripheral base address.
+ * param maskIdx The Index of individual Mask.
+ * param mask Rx Individual Mask value.
+ */
 void FLEXCAN_SetRxIndividualMask(CAN_Type *base, uint8_t maskIdx, uint32_t mask)
 {
     assert(maskIdx <= (base->MCR & CAN_MCR_MAXMB_MASK));
@@ -747,6 +1099,18 @@ void FLEXCAN_SetRxIndividualMask(CAN_Type *base, uint8_t maskIdx, uint32_t mask)
     FLEXCAN_ExitFreezeMode(base);
 }
 
+/*!
+ * brief Configures a FlexCAN transmit message buffer.
+ *
+ * This function aborts the previous transmission, cleans the Message Buffer, and
+ * configures it as a Transmit Message Buffer.
+ *
+ * param base FlexCAN peripheral base address.
+ * param mbIdx The Message Buffer index.
+ * param enable Enable/disable Tx Message Buffer.
+ *               - true: Enable Tx Message Buffer.
+ *               - false: Disable Tx Message Buffer.
+ */
 void FLEXCAN_SetTxMbConfig(CAN_Type *base, uint8_t mbIdx, bool enable)
 {
     /* Assertion. */
@@ -764,53 +1128,335 @@ void FLEXCAN_SetTxMbConfig(CAN_Type *base, uint8_t mbIdx, bool enable)
     }
 
     /* Clean Message Buffer content. */
-    base->MB[mbIdx].ID = 0x0;
+    base->MB[mbIdx].ID    = 0x0;
     base->MB[mbIdx].WORD0 = 0x0;
     base->MB[mbIdx].WORD1 = 0x0;
 }
 
+/*!
+ * @brief Calculates the segment values for a single bit time for classical CAN
+ *
+ * @param baudRate The data speed in bps
+ * @param tqNum Number of time quantas per bit
+ * @param pconfig Pointer to the FlexCAN timing configuration structure.
+ *
+ */
+static void FLEXCAN_GetSegments(uint32_t baudRate, uint32_t tqNum, flexcan_timing_config_t *pconfig)
+{
+    uint32_t ideal_sp;
+    uint32_t p1;
+
+    /* get ideal sample point. */
+    if (baudRate >= 1000000)
+        ideal_sp = IDEAL_SP_LOW;
+    else if (baudRate >= 800000)
+        ideal_sp = IDEAL_SP_MID;
+    else
+        ideal_sp = IDEAL_SP_HIGH;
+
+    /* distribute time quanta. */
+    p1                 = tqNum * (uint32_t)ideal_sp;
+    pconfig->propSeg   = 0;
+    pconfig->phaseSeg1 = p1 / IDEAL_SP_FACTOR - 2U;
+    if (pconfig->phaseSeg1 > (MAX_PSEG1 + MAX_PROPSEG))
+    {
+        pconfig->phaseSeg1 = MAX_PSEG1;
+        pconfig->propSeg   = MAX_PROPSEG;
+    }
+    else if (pconfig->phaseSeg1 > MAX_PSEG1)
+    {
+        pconfig->propSeg   = pconfig->phaseSeg1 - MAX_PSEG1;
+        pconfig->phaseSeg1 = MAX_PSEG1;
+    }
+    pconfig->phaseSeg2 = tqNum - (1U + pconfig->phaseSeg1 + 1U + pconfig->propSeg + 1U + 1U);
+    assert(pconfig->phaseSeg2 <= MAX_PSEG2);
+
+    /* subtract one TQ for sync seg. */
+    /* sjw is 20% of total TQ, rounded to nearest int. */
+    pconfig->rJumpwidth = (tqNum + (5 - 1)) / 5 - 1U;
+    if (pconfig->rJumpwidth > MAX_RJW)
+    {
+        pconfig->rJumpwidth = MAX_RJW;
+    }
+}
+
+/*!
+ * @brief Calculates the improved timing values by specific baudrates for classical CAN
+ *
+ * @param baudRate  The classical CAN speed in bps defined by user
+ * @param sourceClock_Hz The Source clock data speed in bps. Zero to disable baudrate switching
+ * @param pconfig Pointer to the FlexCAN timing configuration structure.
+ *
+ * @return TRUE if timing configuration found, FALSE if failed to find configuration
+ */
+bool FLEXCAN_CalculateImprovedTimingValues(uint32_t baudRate, uint32_t sourceClock_Hz, flexcan_timing_config_t *pconfig)
+{
+    uint32_t clk;   /* the clock is tqNumb x baudRateFD. */
+    uint32_t clk2;  /* the clock2 is clk2 / Pre-scaler Division Factor. */
+    uint32_t tqNum; /* Numbers of TQ. */
+
+    /* observe baud rate maximums. */
+    assert(baudRate <= MAX_CAN_BAUDRATE);
+
+    /*  Auto Improved Protocal timing for CBT. */
+    for (tqNum = CTRL1_MAX_TIME_QUANTA; tqNum >= CTRL1_MIN_TIME_QUANTA; tqNum--)
+    {
+        clk = baudRate * tqNum;
+        if (clk > sourceClock_Hz)
+        {
+            continue; /* tqNum too large, clk has been exceed sourceClock_Hz. */
+        }
+
+        for (pconfig->preDivider = 0x00; pconfig->preDivider <= MAX_PRESDIV; (pconfig->preDivider)++)
+        {
+            /* Consider some proessor not contain FPU, the parameter need to be exact division. */
+            if ((clk / (pconfig->preDivider + 1U) * (pconfig->preDivider + 1U)) != clk)
+            {
+                continue; /* clk need to be exact division by preDivider + 1. */
+            }
+            clk2 = clk / (pconfig->preDivider + 1U);
+            if (((sourceClock_Hz / clk2) * clk2) != sourceClock_Hz)
+            {
+                continue; /* sourceClock_Hz need to be exact division by preDivider. */
+            }
+            FLEXCAN_GetSegments(baudRate, tqNum, pconfig);
+            return true;
+        }
+    }
+    /* failed to find solution. */
+    return false;
+}
+
 #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
 static uint32_t FLEXCAN_GetFDMailboxOffset(CAN_Type *base, uint8_t mbIdx)
 {
     uint32_t dataSize;
     uint32_t offset = 0;
-    dataSize = (base->FDCTRL & CAN_FDCTRL_MBDSR0_MASK) >> CAN_FDCTRL_MBDSR0_SHIFT;
+    dataSize        = (base->FDCTRL & CAN_FDCTRL_MBDSR0_MASK) >> CAN_FDCTRL_MBDSR0_SHIFT;
     switch (dataSize)
     {
-        case kFLEXCAN_8BperMB:
-            offset = (mbIdx / 32) * 512 + mbIdx % 32 * 16;
+        case (uint32_t)kFLEXCAN_8BperMB:
+            offset = (((uint32_t)mbIdx / 32U) * 512U + ((uint32_t)mbIdx % 32U) * 16U);
             break;
-        case kFLEXCAN_16BperMB:
-            offset = (mbIdx / 21) * 512 + mbIdx % 21 * 24;
+        case (uint32_t)kFLEXCAN_16BperMB:
+            offset = (((uint32_t)mbIdx / 21U) * 512U + ((uint32_t)mbIdx % 21U) * 24U);
             break;
-        case kFLEXCAN_32BperMB:
-            offset = (mbIdx / 12) * 512 + mbIdx % 12 * 40;
+        case (uint32_t)kFLEXCAN_32BperMB:
+            offset = (((uint32_t)mbIdx / 12U) * 512U + ((uint32_t)mbIdx % 12U) * 40U);
             break;
-        case kFLEXCAN_64BperMB:
-            offset = (mbIdx / 7) * 512 + mbIdx % 7 * 72;
+        case (uint32_t)kFLEXCAN_64BperMB:
+            offset = (((uint32_t)mbIdx / 7U) * 512U + ((uint32_t)mbIdx % 7U) * 72U);
             break;
         default:
+            /* All the cases have been listed above, the default clause should not be reached. */
+            assert(false);
             break;
     }
     /* To get the dword aligned offset, need to divide by 4. */
-    offset = offset / 4;
+    offset = offset / 4U;
     return offset;
 }
+
+/*!
+ * @brief Calculates the segment values for a single bit time for CANFD bus control baud Rate
+ *
+ * @param baudRate The canfd bus control speed in bps
+ * @param tqNum Number of time quanta per bit
+ * @param pconfig Pointer to the FlexCAN timing configuration structure.
+ *
+ */
+static void FLEXCAN_FDGetSegments(uint32_t baudRate, uint32_t tqNum, flexcan_timing_config_t *pconfig)
+{
+    uint32_t ideal_sp;
+    uint32_t p1;
+
+    /* get ideal sample point. */
+    if (baudRate >= 1000000)
+        ideal_sp = IDEAL_SP_LOW;
+    else if (baudRate >= 800000)
+        ideal_sp = IDEAL_SP_MID;
+    else
+        ideal_sp = IDEAL_SP_HIGH;
+
+    /* distribute time quanta. */
+    p1                 = tqNum * (uint32_t)ideal_sp;
+    pconfig->propSeg   = 0;
+    pconfig->phaseSeg1 = p1 / IDEAL_SP_FACTOR - 2U;
+    if (pconfig->phaseSeg1 > (MAX_EPSEG1 + MAX_EPROPSEG))
+    {
+        pconfig->phaseSeg1 = MAX_EPSEG1;
+        pconfig->propSeg   = MAX_EPROPSEG;
+    }
+    else if (pconfig->phaseSeg1 > MAX_EPSEG1)
+    {
+        pconfig->propSeg   = pconfig->phaseSeg1 - MAX_EPSEG1;
+        pconfig->phaseSeg1 = MAX_EPSEG1;
+    }
+
+    pconfig->phaseSeg2 = tqNum - (1U + pconfig->phaseSeg1 + 1U + pconfig->propSeg + 1U + 1U);
+    assert(pconfig->phaseSeg2 <= MAX_EPSEG2);
+
+    /* subtract one TQ for sync seg. */
+    /* sjw is 20% of total TQ, rounded to nearest int. */
+    pconfig->rJumpwidth = (tqNum + (5 - 1)) / 5 - 1U;
+    /* the max tqNum for CBT will reach to 129, ERJW would not larger than 26. */
+    /* Consider and max ERJW is 31, so rJumpwidth will always smaller than MAX_ERJW. */
+    assert(pconfig->rJumpwidth <= MAX_ERJW);
+}
+
+/*!
+ * @brief Calculates the segment values for a single bit time for CANFD bus data baud Rate
+ *
+ * @param baudRate The canfd bus data speed in bps
+ * @param tqNum Number of time quanta per bit
+ * @param pconfig Pointer to the FlexCAN timing configuration structure.
+ *
+ */
+static void FLEXCAN_FDGetSegmentswithBRS(uint32_t baudRateFD, uint32_t tqNum, flexcan_timing_config_t *pconfig)
+{
+    uint32_t ideal_sp;
+    uint32_t p1;
+
+    /* get ideal sample point. */
+    if (baudRateFD >= 1000000)
+        ideal_sp = IDEAL_SP_LOW;
+    else if (baudRateFD >= 800000)
+        ideal_sp = IDEAL_SP_MID;
+    else
+        ideal_sp = IDEAL_SP_HIGH;
+
+    /* distribute time quanta. */
+    p1                  = tqNum * (uint32_t)ideal_sp;
+    pconfig->fpropSeg   = 0;
+    pconfig->fphaseSeg1 = p1 / IDEAL_SP_FACTOR - 1U;
+    if (pconfig->fphaseSeg1 > (MAX_FPSEG1 + MAX_FPROPSEG))
+    {
+        pconfig->fphaseSeg1 = MAX_FPSEG1;
+        pconfig->fpropSeg   = MAX_FPROPSEG;
+    }
+    else if (pconfig->fphaseSeg1 > MAX_FPSEG1)
+    {
+        pconfig->fpropSeg   = pconfig->fphaseSeg1 - MAX_FPSEG1;
+        pconfig->fphaseSeg1 = MAX_FPSEG1;
+    }
+
+    pconfig->fphaseSeg2 = tqNum - (1U + pconfig->fphaseSeg1 + 1U + pconfig->fpropSeg + 0U + 1U);
+
+    assert(pconfig->fphaseSeg2 <= MAX_FPSEG2);
+
+    /* subtract one TQ for sync seg. */
+    /* sjw is 20% of total TQ, rounded to nearest int. */
+    pconfig->frJumpwidth = (tqNum + (5 - 1)) / 5 - 1U;
+
+    if (pconfig->frJumpwidth > MAX_FRJW)
+    {
+        pconfig->frJumpwidth = MAX_FRJW;
+    }
+}
+
+/*!
+ * @brief Calculates the improved timing values by specific baudrates for CANFD
+ *
+ * @param baudRate  The CANFD bus control speed in bps defined by user
+ * @param baudRateFD  The CANFD bus data speed in bps defined by user
+ * @param sourceClock_Hz The Source clock data speed in bps. Zero to disable baudrate switching
+ * @param pconfig Pointer to the FlexCAN timing configuration structure.
+ *
+ * @return TRUE if timing configuration found, FALSE if failed to find configuration
+ */
+bool FLEXCAN_FDCalculateImprovedTimingValues(uint32_t baudRate,
+                                             uint32_t baudRateFD,
+                                             uint32_t sourceClock_Hz,
+                                             flexcan_timing_config_t *pconfig)
+{
+    uint32_t clk, clkbrs;
+    uint32_t clk2, clkbrs2;
+    uint32_t tqNum, tqNumbrs; /* Numbers of TQ. */
+
+    /* observe baud rate maximums */
+    assert(baudRate <= MAX_CAN_BAUDRATE);
+    assert(baudRateFD <= MAX_CANFD_BAUDRATE);
+
+    /*  Auto Improved Protocal timing for CBT. */
+    for (tqNum = CBT_MAX_TIME_QUANTA; tqNum >= CBT_MIN_TIME_QUANTA; tqNum--)
+    {
+        clk = baudRate * tqNum;
+        if (clk > sourceClock_Hz)
+        {
+            continue; /* tqNum too large, clk x tqNum has been exceed sourceClock_Hz. */
+        }
+
+        for (pconfig->preDivider = 0x00; pconfig->preDivider <= MAX_EPRESDIV; (pconfig->preDivider)++)
+        {
+            /* Consider some proessor not contain FPU, the parameter need to be exact division. */
+            if ((clk / (pconfig->preDivider + 1U) * (pconfig->preDivider + 1U)) != clk)
+            {
+                continue; /* clk need to be exact division by preDivider + 1. */
+            }
+            clk2 = clk / (pconfig->preDivider + 1U);
+
+            if ((sourceClock_Hz / clk2 * clk2) != sourceClock_Hz)
+            {
+                continue; /* sourceClock_Hz need to be exact division by clk2. */
+            }
+            FLEXCAN_FDGetSegments(baudRate, tqNum, pconfig);
+            /* After calculate for CBT, continue to calculate FBCBT field timing configuration. */
+            for (tqNumbrs = FDCBT_MAX_TIME_QUANTA; tqNumbrs >= FDCBT_MIN_TIME_QUANTA; tqNumbrs--)
+            {
+                clkbrs = baudRateFD * tqNumbrs;
+                if (clkbrs > sourceClock_Hz)
+                {
+                    continue; /* tqNumbrs too large, clkbrs x tqNumbrs has been exceed sourceClock_Hz. */
+                }
+                for (pconfig->fpreDivider = 0x00; pconfig->fpreDivider <= MAX_FPRESDIV; (pconfig->fpreDivider)++)
+                {
+                    /* Consider some proessor not contain FPU, the parameter need to be exact division. */
+                    if ((clkbrs / (pconfig->fpreDivider + 1U) * (pconfig->fpreDivider + 1U)) != clkbrs)
+                    {
+                        continue; /* clk need to be exact division by preDivider + 1. */
+                    }
+                    clkbrs2 = clkbrs / (pconfig->fpreDivider + 1U);
+                    if ((sourceClock_Hz / clkbrs2 * clkbrs2) != sourceClock_Hz)
+                    {
+                        continue; /* sourceClock_Hz need to be exact division by preDivider. */
+                    }
+                    FLEXCAN_FDGetSegmentswithBRS(baudRateFD, tqNumbrs, pconfig);
+                    return true;
+                }
+            }
+        }
+    }
+    /* failed to find solution. */
+    return false;
+}
 #endif
 
 #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
+/*!
+ * brief Configures a FlexCAN transmit message buffer.
+ *
+ * This function aborts the previous transmission, cleans the Message Buffer, and
+ * configures it as a Transmit Message Buffer.
+ *
+ * param base FlexCAN peripheral base address.
+ * param mbIdx The Message Buffer index.
+ * param enable Enable/disable Tx Message Buffer.
+ *               - true: Enable Tx Message Buffer.
+ *               - false: Disable Tx Message Buffer.
+ */
 void FLEXCAN_SetFDTxMbConfig(CAN_Type *base, uint8_t mbIdx, bool enable)
 {
     /* Assertion. */
     assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK));
     assert(!FLEXCAN_IsMbOccupied(base, mbIdx));
-    uint8_t cnt = 0;
+    uint8_t cnt           = 0;
     uint8_t payload_dword = 1;
     uint32_t dataSize;
-    dataSize = (base->FDCTRL & CAN_FDCTRL_MBDSR0_MASK) >> CAN_FDCTRL_MBDSR0_SHIFT;
+    dataSize                  = (base->FDCTRL & CAN_FDCTRL_MBDSR0_MASK) >> CAN_FDCTRL_MBDSR0_SHIFT;
     volatile uint32_t *mbAddr = &(base->MB[0].CS);
-    uint32_t offset = FLEXCAN_GetFDMailboxOffset(base, mbIdx);
-#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641)
+    uint32_t offset           = FLEXCAN_GetFDMailboxOffset(base, mbIdx);
+#if ((defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) || \
+     (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829))
     uint32_t availoffset = FLEXCAN_GetFDMailboxOffset(base, FLEXCAN_GetFirstValidMb(base));
 #endif
 
@@ -827,31 +1473,45 @@ void FLEXCAN_SetFDTxMbConfig(CAN_Type *base, uint8_t mbIdx, bool enable)
 
     /* Calculate the DWORD number, dataSize 0/1/2/3 corresponds to 8/16/32/64
        Bytes payload. */
-    for (cnt = 0; cnt < dataSize + 1; cnt++)
+    for (cnt = 0; cnt < (dataSize + 1U); cnt++)
     {
-        payload_dword *= 2;
+        payload_dword *= 2U;
     }
 
     /* Clean ID. */
-    mbAddr[offset + 1] = 0x0;
+    mbAddr[offset + 1U] = 0x0U;
     /* Clean Message Buffer content, DWORD by DWORD. */
     for (cnt = 0; cnt < payload_dword; cnt++)
     {
-        mbAddr[offset + 2 + cnt] = 0x0;
+        mbAddr[offset + 2U + cnt] = 0x0U;
     }
 
-#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641)
+#if ((defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) || \
+     (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829))
     mbAddr[availoffset] = CAN_CS_CODE(kFLEXCAN_TxMbInactive);
 #endif
 }
 #endif
 
+/*!
+ * brief Configures a FlexCAN Receive Message Buffer.
+ *
+ * This function cleans a FlexCAN build-in Message Buffer and configures it
+ * as a Receive Message Buffer.
+ *
+ * param base FlexCAN peripheral base address.
+ * param mbIdx The Message Buffer index.
+ * param config Pointer to the FlexCAN Message Buffer configuration structure.
+ * param enable Enable/disable Rx Message Buffer.
+ *               - true: Enable Rx Message Buffer.
+ *               - false: Disable Rx Message Buffer.
+ */
 void FLEXCAN_SetRxMbConfig(CAN_Type *base, uint8_t mbIdx, const flexcan_rx_mb_config_t *config, bool enable)
 {
     /* Assertion. */
     assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK));
-    assert(((config) || (false == enable)));
-    assert(!FLEXCAN_IsMbOccupied(base, mbIdx));
+    assert(((NULL != config) || (false == enable)));
+    assert(false == FLEXCAN_IsMbOccupied(base, mbIdx));
 
     uint32_t cs_temp = 0;
 
@@ -859,7 +1519,7 @@ void FLEXCAN_SetRxMbConfig(CAN_Type *base, uint8_t mbIdx, const flexcan_rx_mb_co
     base->MB[mbIdx].CS = 0;
 
     /* Clean Message Buffer content. */
-    base->MB[mbIdx].ID = 0x0;
+    base->MB[mbIdx].ID    = 0x0;
     base->MB[mbIdx].WORD0 = 0x0;
     base->MB[mbIdx].WORD1 = 0x0;
 
@@ -887,31 +1547,45 @@ void FLEXCAN_SetRxMbConfig(CAN_Type *base, uint8_t mbIdx, const flexcan_rx_mb_co
 }
 
 #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
+/*!
+ * brief Configures a FlexCAN Receive Message Buffer.
+ *
+ * This function cleans a FlexCAN build-in Message Buffer and configures it
+ * as a Receive Message Buffer.
+ *
+ * param base FlexCAN peripheral base address.
+ * param mbIdx The Message Buffer index.
+ * param config Pointer to the FlexCAN Message Buffer configuration structure.
+ * param enable Enable/disable Rx Message Buffer.
+ *               - true: Enable Rx Message Buffer.
+ *               - false: Disable Rx Message Buffer.
+ */
 void FLEXCAN_SetFDRxMbConfig(CAN_Type *base, uint8_t mbIdx, const flexcan_rx_mb_config_t *config, bool enable)
 {
     /* Assertion. */
     assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK));
-    assert(((config) || (false == enable)));
-    assert(!FLEXCAN_IsMbOccupied(base, mbIdx));
+    assert(((NULL != config) || (false == enable)));
+    assert(false == FLEXCAN_IsMbOccupied(base, mbIdx));
 
-    uint32_t cs_temp = 0;
-    uint8_t cnt = 0;
+    uint32_t cs_temp          = 0;
+    uint8_t cnt               = 0;
     volatile uint32_t *mbAddr = &(base->MB[0].CS);
-    uint32_t offset = FLEXCAN_GetFDMailboxOffset(base, mbIdx);
+    uint32_t offset           = FLEXCAN_GetFDMailboxOffset(base, mbIdx);
+    uint8_t payload_dword     = 1;
+    uint32_t dataSize         = (base->FDCTRL & CAN_FDCTRL_MBDSR0_MASK) >> CAN_FDCTRL_MBDSR0_SHIFT;
 
-    /* Inactivate all mailboxes first, clean ID and Message Buffer content. */
-    for (cnt = 0; cnt < FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base); cnt++)
+    /* Calculate the DWORD number, dataSize 0/1/2/3 corresponds to 8/16/32/64
+       Bytes payload. */
+    payload_dword = (2U << dataSize);
+    for (cnt = 0; cnt < payload_dword; cnt++)
     {
-       base->MB[cnt].CS = 0;
-       base->MB[cnt].ID = 0;
-       base->MB[cnt].WORD0 = 0;
-       base->MB[cnt].WORD1 = 0;
+        mbAddr[offset + 2U + cnt] = 0x0;
     }
 
     if (enable)
     {
         /* Setup Message Buffer ID. */
-        mbAddr[offset + 1] = config->id;
+        mbAddr[offset + 1U] = config->id;
 
         /* Setup Message Buffer format. */
         if (kFLEXCAN_FrameFormatExtend == config->format)
@@ -919,6 +1593,12 @@ void FLEXCAN_SetFDRxMbConfig(CAN_Type *base, uint8_t mbIdx, const flexcan_rx_mb_
             cs_temp |= CAN_CS_IDE_MASK;
         }
 
+        /* Setup Message Buffer type. */
+        if (kFLEXCAN_FrameTypeRemote == config->type)
+        {
+            cs_temp |= CAN_CS_RTR_MASK;
+        }
+
         /* Activate Rx Message Buffer. */
         cs_temp |= CAN_CS_CODE(kFLEXCAN_RxMbEmpty);
         mbAddr[offset] = cs_temp;
@@ -926,34 +1606,46 @@ void FLEXCAN_SetFDRxMbConfig(CAN_Type *base, uint8_t mbIdx, const flexcan_rx_mb_
 }
 #endif
 
+/*!
+ * brief Configures the FlexCAN Rx FIFO.
+ *
+ * This function configures the Rx FIFO with given Rx FIFO configuration.
+ *
+ * param base FlexCAN peripheral base address.
+ * param config Pointer to the FlexCAN Rx FIFO configuration structure.
+ * param enable Enable/disable Rx FIFO.
+ *               - true: Enable Rx FIFO.
+ *               - false: Disable Rx FIFO.
+ */
 void FLEXCAN_SetRxFifoConfig(CAN_Type *base, const flexcan_rx_fifo_config_t *config, bool enable)
 {
     /* Assertion. */
-    assert((config) || (false == enable));
+    assert((NULL != config) || (false == enable));
 
     volatile uint32_t *idFilterRegion = (volatile uint32_t *)(&base->MB[6].CS);
-    uint8_t setup_mb, i, rffn = 0;
+    uint8_t i, rffn = 0;
+    uint32_t setup_mb = 0;
 
     /* Enter Freeze Mode. */
     FLEXCAN_EnterFreezeMode(base);
 
     if (enable)
     {
-        assert(config->idFilterNum <= 128);
+        assert(config->idFilterNum <= 128U);
 
         /* Get the setup_mb value. */
-        setup_mb = (base->MCR & CAN_MCR_MAXMB_MASK) >> CAN_MCR_MAXMB_SHIFT;
-        setup_mb = (setup_mb < FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base)) ?
+        setup_mb = (uint8_t)((base->MCR & CAN_MCR_MAXMB_MASK) >> CAN_MCR_MAXMB_SHIFT);
+        setup_mb = (setup_mb < (uint32_t)FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base)) ?
                        setup_mb :
-                       FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base);
+                       (uint32_t)FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base);
 
         /* Determine RFFN value. */
-        for (i = 0; i <= 0xF; i++)
+        for (i = 0; i <= 0xFU; i++)
         {
-            if ((8 * (i + 1)) >= config->idFilterNum)
+            if ((8U * (i + 1U)) >= config->idFilterNum)
             {
                 rffn = i;
-                assert(((setup_mb - 8) - (2 * rffn)) > 0);
+                assert(((setup_mb - 8U) - (2U * rffn)) > 0U);
 
                 base->CTRL2 = (base->CTRL2 & ~CAN_CTRL2_RFFN_MASK) | CAN_CTRL2_RFFN(rffn);
                 break;
@@ -962,11 +1654,11 @@ void FLEXCAN_SetRxFifoConfig(CAN_Type *base, const flexcan_rx_fifo_config_t *con
     }
     else
     {
-        rffn = (base->CTRL2 & CAN_CTRL2_RFFN_MASK) >> CAN_CTRL2_RFFN_SHIFT;
+        rffn = (uint8_t)((base->CTRL2 & CAN_CTRL2_RFFN_MASK) >> CAN_CTRL2_RFFN_SHIFT);
     }
 
     /* Clean ID filter table occuyied Message Buffer Region. */
-    rffn = (rffn + 1) * 8;
+    rffn = (uint8_t)((rffn + 1U) * 8U);
     for (i = 0; i < rffn; i++)
     {
         idFilterRegion[i] = 0x0;
@@ -1003,12 +1695,14 @@ void FLEXCAN_SetRxFifoConfig(CAN_Type *base, const flexcan_rx_fifo_config_t *con
                 base->MCR = (base->MCR & ~CAN_MCR_IDAM_MASK) | CAN_MCR_IDAM(0x3);
                 break;
             default:
+                /* All the cases have been listed above, the default clause should not be reached. */
+                assert(false);
                 break;
         }
 
         /* Setting Message Reception Priority. */
-        base->CTRL2 = (config->priority == kFLEXCAN_RxFifoPrioHigh) ? base->CTRL2 & ~CAN_CTRL2_MRP_MASK :
-                                                                      base->CTRL2 | CAN_CTRL2_MRP_MASK;
+        base->CTRL2 = (config->priority == kFLEXCAN_RxFifoPrioHigh) ? (base->CTRL2 & ~CAN_CTRL2_MRP_MASK) :
+                                                                      (base->CTRL2 | CAN_CTRL2_MRP_MASK);
 
         /* Enable Rx Message FIFO. */
         base->MCR |= CAN_MCR_RFEN_MASK;
@@ -1032,6 +1726,14 @@ void FLEXCAN_SetRxFifoConfig(CAN_Type *base, const flexcan_rx_fifo_config_t *con
 }
 
 #if (defined(FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA) && FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA)
+/*!
+ * brief Enables or disables the FlexCAN Rx FIFO DMA request.
+ *
+ * This function enables or disables the DMA feature of FlexCAN build-in Rx FIFO.
+ *
+ * param base FlexCAN peripheral base address.
+ * param enable true to enable, false to disable.
+ */
 void FLEXCAN_EnableRxFifoDMA(CAN_Type *base, bool enable)
 {
     if (enable)
@@ -1059,16 +1761,102 @@ void FLEXCAN_EnableRxFifoDMA(CAN_Type *base, bool enable)
 }
 #endif /* FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA */
 
+#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032)
+/*!
+ * FlexCAN: A frame with wrong ID or payload is transmitted into
+ * the CAN bus when the Message Buffer under transmission is
+ * either aborted or deactivated while the CAN bus is in the Bus Idle state
+ *
+ * This function to do workaround for ERR006032
+ *
+ * param base FlexCAN peripheral base address.
+ * param mbIdx The FlexCAN Message Buffer index.
+ */
+static void FLEXCAN_ERRATA_6032(CAN_Type *base, volatile uint32_t *mbCSAddr)
+{
+    uint32_t dbg_temp      = 0U;
+    uint32_t u32TempCS     = 0U;
+    uint32_t u32Timeout    = DELAY_BUSIDLE;
+    uint32_t u32TempIMASK1 = base->IMASK1;
+/*after backup all interruption, disable ALL interruption*/
+#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0)
+    uint32_t u32TempIMASK2 = base->IMASK2;
+    base->IMASK2           = 0;
+#endif
+    base->IMASK1 = 0;
+    dbg_temp     = (uint32_t)(base->DBG1);
+    switch (dbg_temp & CAN_DBG1_CFSM_MASK)
+    {
+        case RXINTERMISSION:
+            if (CBN_VALUE3 == (dbg_temp & CAN_DBG1_CBN_MASK))
+            {
+                /*wait until CFSM is different from RXINTERMISSION */
+                while (RXINTERMISSION == (base->DBG1 & CAN_DBG1_CFSM_MASK))
+                {
+                    __NOP();
+                }
+            }
+            break;
+        case TXINTERMISSION:
+            if (CBN_VALUE3 == (dbg_temp & CAN_DBG1_CBN_MASK))
+            {
+                /*wait until CFSM is different from TXINTERMISSION*/
+                while (TXINTERMISSION == (base->DBG1 & CAN_DBG1_CFSM_MASK))
+                {
+                    __NOP();
+                }
+            }
+            break;
+        default:
+            break;
+    }
+    /*Anyway, BUSIDLE need to delay*/
+    if (BUSIDLE == (base->DBG1 & CAN_DBG1_CFSM_MASK))
+    {
+        while (u32Timeout-- > 0)
+        {
+            __NOP();
+        }
+
+        /*Write 0x0 into Code field of CS word.*/
+        u32TempCS = (uint32_t)(*mbCSAddr);
+        u32TempCS &= ~CAN_CS_CODE_MASK;
+        *mbCSAddr = u32TempCS;
+    }
+    /*restore interruption*/
+    base->IMASK1 = u32TempIMASK1;
+#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0)
+    base->IMASK2 = u32TempIMASK2;
+#endif
+}
+#endif
+
+/*!
+ * brief Writes a FlexCAN Message to the Transmit Message Buffer.
+ *
+ * This function writes a CAN Message to the specified Transmit Message Buffer
+ * and changes the Message Buffer state to start CAN Message transmit. After
+ * that the function returns immediately.
+ *
+ * param base FlexCAN peripheral base address.
+ * param mbIdx The FlexCAN Message Buffer index.
+ * param txFrame Pointer to CAN message frame to be sent.
+ * retval kStatus_Success - Write Tx Message Buffer Successfully.
+ * retval kStatus_Fail    - Tx Message Buffer is currently in use.
+ */
 status_t FLEXCAN_WriteTxMb(CAN_Type *base, uint8_t mbIdx, const flexcan_frame_t *txFrame)
 {
     /* Assertion. */
     assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK));
-    assert(txFrame);
-    assert(txFrame->length <= 8);
-    assert(!FLEXCAN_IsMbOccupied(base, mbIdx));
+    assert(NULL != txFrame);
+    assert(txFrame->length <= 8U);
+    assert(false == FLEXCAN_IsMbOccupied(base, mbIdx));
 
     uint32_t cs_temp = 0;
 
+#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032)
+    FLEXCAN_ERRATA_6032(base, &(base->MB[mbIdx].CS));
+#endif
     /* Check if Message Buffer is available. */
     if (CAN_CS_CODE(kFLEXCAN_TxMbDataOrRemote) != (base->MB[mbIdx].CS & CAN_CS_CODE_MASK))
     {
@@ -1079,13 +1867,13 @@ status_t FLEXCAN_WriteTxMb(CAN_Type *base, uint8_t mbIdx, const flexcan_frame_t
         base->MB[mbIdx].ID = txFrame->id;
 
         /* Fill Message Format field. */
-        if (kFLEXCAN_FrameFormatExtend == txFrame->format)
+        if ((uint32_t)kFLEXCAN_FrameFormatExtend == txFrame->format)
         {
             cs_temp |= CAN_CS_SRR_MASK | CAN_CS_IDE_MASK;
         }
 
         /* Fill Message Type field. */
-        if (kFLEXCAN_FrameTypeRemote == txFrame->type)
+        if ((uint32_t)kFLEXCAN_FrameTypeRemote == txFrame->type)
         {
             cs_temp |= CAN_CS_RTR_MASK;
         }
@@ -1099,7 +1887,8 @@ status_t FLEXCAN_WriteTxMb(CAN_Type *base, uint8_t mbIdx, const flexcan_frame_t
         /* Activate Tx Message Buffer. */
         base->MB[mbIdx].CS = cs_temp;
 
-#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641)
+#if ((defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) || \
+     (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829))
         base->MB[FLEXCAN_GetFirstValidMb(base)].CS = CAN_CS_CODE(kFLEXCAN_TxMbInactive);
         base->MB[FLEXCAN_GetFirstValidMb(base)].CS = CAN_CS_CODE(kFLEXCAN_TxMbInactive);
 #endif
@@ -1114,56 +1903,81 @@ status_t FLEXCAN_WriteTxMb(CAN_Type *base, uint8_t mbIdx, const flexcan_frame_t
 }
 
 #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
+/*!
+ * brief Writes a FlexCAN FD Message to the Transmit Message Buffer.
+ *
+ * This function writes a CAN FD Message to the specified Transmit Message Buffer
+ * and changes the Message Buffer state to start CAN FD Message transmit. After
+ * that the function returns immediately.
+ *
+ * param base FlexCAN peripheral base address.
+ * param mbIdx The FlexCAN FD Message Buffer index.
+ * param txFrame Pointer to CAN FD message frame to be sent.
+ * retval kStatus_Success - Write Tx Message Buffer Successfully.
+ * retval kStatus_Fail    - Tx Message Buffer is currently in use.
+ */
 status_t FLEXCAN_WriteFDTxMb(CAN_Type *base, uint8_t mbIdx, const flexcan_fd_frame_t *txFrame)
 {
     /* Assertion. */
     assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK));
-    assert(txFrame);
-    assert(!FLEXCAN_IsMbOccupied(base, mbIdx));
+    assert(NULL != txFrame);
+    assert(false == FLEXCAN_IsMbOccupied(base, mbIdx));
 
-    uint32_t cs_temp = 0;
-    uint8_t cnt = 0;
-    uint32_t can_cs = 0;
+    uint32_t cs_temp      = 0;
+    uint8_t cnt           = 0;
+    uint32_t can_cs       = 0;
     uint8_t payload_dword = 1;
-    uint32_t dataSize;
-    dataSize = (base->FDCTRL & CAN_FDCTRL_MBDSR0_MASK) >> CAN_FDCTRL_MBDSR0_SHIFT;
-#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641)
+    uint32_t dataSize     = (base->FDCTRL & CAN_FDCTRL_MBDSR0_MASK) >> CAN_FDCTRL_MBDSR0_SHIFT;
+#if ((defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) || \
+     (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829))
     uint32_t availoffset = FLEXCAN_GetFDMailboxOffset(base, FLEXCAN_GetFirstValidMb(base));
 #endif
     volatile uint32_t *mbAddr = &(base->MB[0].CS);
-    uint32_t offset = FLEXCAN_GetFDMailboxOffset(base, mbIdx);
+    uint32_t offset           = FLEXCAN_GetFDMailboxOffset(base, mbIdx);
+
+#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032)
+    FLEXCAN_ERRATA_6032(base, &(mbAddr[offset]));
+#endif
 
-    can_cs = mbAddr[0];
+    can_cs = mbAddr[offset];
     /* Check if Message Buffer is available. */
     if (CAN_CS_CODE(kFLEXCAN_TxMbDataOrRemote) != (can_cs & CAN_CS_CODE_MASK))
     {
         /* Inactive Tx Message Buffer and Fill Message ID field. */
-        mbAddr[offset] = (can_cs & ~CAN_CS_CODE_MASK) | CAN_CS_CODE(kFLEXCAN_TxMbInactive);
-        mbAddr[offset + 1] = txFrame->id;
+        mbAddr[offset]      = (can_cs & ~CAN_CS_CODE_MASK) | CAN_CS_CODE(kFLEXCAN_TxMbInactive);
+        mbAddr[offset + 1U] = txFrame->id;
 
         /* Fill Message Format field. */
-        if (kFLEXCAN_FrameFormatExtend == txFrame->format)
+        if ((uint32_t)kFLEXCAN_FrameFormatExtend == txFrame->format)
         {
             cs_temp |= CAN_CS_SRR_MASK | CAN_CS_IDE_MASK;
         }
 
-        cs_temp |= CAN_CS_CODE(kFLEXCAN_TxMbDataOrRemote) | CAN_CS_DLC(txFrame->length) | CAN_CS_EDL(1);
+        /* Fill Message Type field. */
+        if ((uint32_t)kFLEXCAN_FrameTypeRemote == txFrame->type)
+        {
+            cs_temp |= CAN_CS_RTR_MASK;
+        }
+
+        cs_temp |= CAN_CS_CODE(kFLEXCAN_TxMbDataOrRemote) | CAN_CS_DLC(txFrame->length) | CAN_CS_EDL(1) |
+                   CAN_CS_BRS(txFrame->brs);
 
         /* Calculate the DWORD number, dataSize 0/1/2/3 corresponds to 8/16/32/64
            Bytes payload. */
-        for (cnt = 0; cnt < dataSize + 1; cnt++)
+        for (cnt = 0; cnt < (dataSize + 1U); cnt++)
         {
-            payload_dword *= 2;
+            payload_dword *= 2U;
         }
 
         /* Load Message Payload and Activate Tx Message Buffer. */
         for (cnt = 0; cnt < payload_dword; cnt++)
         {
-            mbAddr[offset + 2 + cnt] = txFrame->dataWord[cnt];
+            mbAddr[offset + 2U + cnt] = txFrame->dataWord[cnt];
         }
         mbAddr[offset] = cs_temp;
 
-#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641)
+#if ((defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) || \
+     (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829))
         mbAddr[availoffset] = CAN_CS_CODE(kFLEXCAN_TxMbInactive);
         mbAddr[availoffset] = CAN_CS_CODE(kFLEXCAN_TxMbInactive);
 #endif
@@ -1178,15 +1992,30 @@ status_t FLEXCAN_WriteFDTxMb(CAN_Type *base, uint8_t mbIdx, const flexcan_fd_fra
 }
 #endif
 
+/*!
+ * brief Reads a FlexCAN Message from Receive Message Buffer.
+ *
+ * This function reads a CAN message from a specified Receive Message Buffer.
+ * The function fills a receive CAN message frame structure with
+ * just received data and activates the Message Buffer again.
+ * The function returns immediately.
+ *
+ * param base FlexCAN peripheral base address.
+ * param mbIdx The FlexCAN Message Buffer index.
+ * param rxFrame Pointer to CAN message frame structure for reception.
+ * retval kStatus_Success            - Rx Message Buffer is full and has been read successfully.
+ * retval kStatus_FLEXCAN_RxOverflow - Rx Message Buffer is already overflowed and has been read successfully.
+ * retval kStatus_Fail               - Rx Message Buffer is empty.
+ */
 status_t FLEXCAN_ReadRxMb(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *rxFrame)
 {
     /* Assertion. */
     assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK));
-    assert(rxFrame);
-    assert(!FLEXCAN_IsMbOccupied(base, mbIdx));
+    assert(NULL != rxFrame);
+    assert(false == FLEXCAN_IsMbOccupied(base, mbIdx));
 
     uint32_t cs_temp;
-    uint8_t rx_code;
+    uint32_t rx_code;
 
     /* Read CS field of Rx Message Buffer to lock Message Buffer. */
     cs_temp = base->MB[mbIdx].CS;
@@ -1194,19 +2023,24 @@ status_t FLEXCAN_ReadRxMb(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *rxFram
     rx_code = (cs_temp & CAN_CS_CODE_MASK) >> CAN_CS_CODE_SHIFT;
 
     /* Check to see if Rx Message Buffer is full. */
-    if ((kFLEXCAN_RxMbFull == rx_code) || (kFLEXCAN_RxMbOverrun == rx_code))
+    if (((uint32_t)kFLEXCAN_RxMbFull == rx_code) || ((uint32_t)kFLEXCAN_RxMbOverrun == rx_code))
     {
         /* Store Message ID. */
         rxFrame->id = base->MB[mbIdx].ID & (CAN_ID_EXT_MASK | CAN_ID_STD_MASK);
 
         /* Get the message ID and format. */
-        rxFrame->format = (cs_temp & CAN_CS_IDE_MASK) ? kFLEXCAN_FrameFormatExtend : kFLEXCAN_FrameFormatStandard;
+        rxFrame->format = (cs_temp & CAN_CS_IDE_MASK) != 0U ? (uint32_t)kFLEXCAN_FrameFormatExtend :
+                                                              (uint32_t)kFLEXCAN_FrameFormatStandard;
 
         /* Get the message type. */
-        rxFrame->type = (cs_temp & CAN_CS_RTR_MASK) ? kFLEXCAN_FrameTypeRemote : kFLEXCAN_FrameTypeData;
+        rxFrame->type =
+            (cs_temp & CAN_CS_RTR_MASK) != 0U ? (uint32_t)kFLEXCAN_FrameTypeRemote : (uint32_t)kFLEXCAN_FrameTypeData;
 
         /* Get the message length. */
-        rxFrame->length = (cs_temp & CAN_CS_DLC_MASK) >> CAN_CS_DLC_SHIFT;
+        rxFrame->length = (uint8_t)((cs_temp & CAN_CS_DLC_MASK) >> CAN_CS_DLC_SHIFT);
+
+        /* Get the time stamp. */
+        rxFrame->timestamp = (uint16_t)((cs_temp & CAN_CS_TIME_STAMP_MASK) >> CAN_CS_TIME_STAMP_SHIFT);
 
         /* Store Message Payload. */
         rxFrame->dataWord0 = base->MB[mbIdx].WORD0;
@@ -1215,7 +2049,7 @@ status_t FLEXCAN_ReadRxMb(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *rxFram
         /* Read free-running timer to unlock Rx Message Buffer. */
         (void)base->TIMER;
 
-        if (kFLEXCAN_RxMbFull == rx_code)
+        if ((uint32_t)kFLEXCAN_RxMbFull == rx_code)
         {
             return kStatus_Success;
         }
@@ -1234,62 +2068,82 @@ status_t FLEXCAN_ReadRxMb(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *rxFram
 }
 
 #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
+/*!
+ * brief Reads a FlexCAN FD Message from Receive Message Buffer.
+ *
+ * This function reads a CAN FD message from a specified Receive Message Buffer.
+ * The function fills a receive CAN FD message frame structure with
+ * just received data and activates the Message Buffer again.
+ * The function returns immediately.
+ *
+ * param base FlexCAN peripheral base address.
+ * param mbIdx The FlexCAN FD Message Buffer index.
+ * param rxFrame Pointer to CAN FD message frame structure for reception.
+ * retval kStatus_Success            - Rx Message Buffer is full and has been read successfully.
+ * retval kStatus_FLEXCAN_RxOverflow - Rx Message Buffer is already overflowed and has been read successfully.
+ * retval kStatus_Fail               - Rx Message Buffer is empty.
+ */
 status_t FLEXCAN_ReadFDRxMb(CAN_Type *base, uint8_t mbIdx, flexcan_fd_frame_t *rxFrame)
 {
     /* Assertion. */
     assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK));
-    assert(rxFrame);
+    assert(NULL != rxFrame);
     assert(!FLEXCAN_IsMbOccupied(base, mbIdx));
 
     uint32_t cs_temp;
     uint8_t rx_code;
-    uint8_t cnt = 0;
+    uint8_t cnt     = 0;
     uint32_t can_id = 0;
     uint32_t dataSize;
-    dataSize = (base->FDCTRL & CAN_FDCTRL_MBDSR0_MASK) >> CAN_FDCTRL_MBDSR0_SHIFT;
-    uint8_t payload_dword = 1;
+    dataSize                  = (base->FDCTRL & CAN_FDCTRL_MBDSR0_MASK) >> CAN_FDCTRL_MBDSR0_SHIFT;
+    uint8_t payload_dword     = 1;
     volatile uint32_t *mbAddr = &(base->MB[0].CS);
-    uint32_t offset = FLEXCAN_GetFDMailboxOffset(base, mbIdx);
+    uint32_t offset           = FLEXCAN_GetFDMailboxOffset(base, mbIdx);
 
     /* Read CS field of Rx Message Buffer to lock Message Buffer. */
     cs_temp = mbAddr[offset];
-    can_id = mbAddr[offset + 1];
+    can_id  = mbAddr[offset + 1U];
 
     /* Get Rx Message Buffer Code field. */
-    rx_code = (cs_temp & CAN_CS_CODE_MASK) >> CAN_CS_CODE_SHIFT;
+    rx_code = (uint8_t)((cs_temp & CAN_CS_CODE_MASK) >> CAN_CS_CODE_SHIFT);
 
     /* Check to see if Rx Message Buffer is full. */
-    if ((kFLEXCAN_RxMbFull == rx_code) || (kFLEXCAN_RxMbOverrun == rx_code))
+    if (((uint8_t)kFLEXCAN_RxMbFull == rx_code) || ((uint8_t)kFLEXCAN_RxMbOverrun == rx_code))
     {
         /* Store Message ID. */
         rxFrame->id = can_id & (CAN_ID_EXT_MASK | CAN_ID_STD_MASK);
 
         /* Get the message ID and format. */
-        rxFrame->format = (cs_temp & CAN_CS_IDE_MASK) ? kFLEXCAN_FrameFormatExtend : kFLEXCAN_FrameFormatStandard;
+        rxFrame->format = (cs_temp & CAN_CS_IDE_MASK) != 0U ? (uint32_t)kFLEXCAN_FrameFormatExtend :
+                                                              (uint32_t)kFLEXCAN_FrameFormatStandard;
 
         /* Get the message type. */
-        rxFrame->type = (cs_temp & CAN_CS_RTR_MASK) ? kFLEXCAN_FrameTypeRemote : kFLEXCAN_FrameTypeData;
+        rxFrame->type =
+            (cs_temp & CAN_CS_RTR_MASK) != 0U ? (uint32_t)kFLEXCAN_FrameTypeRemote : (uint32_t)kFLEXCAN_FrameTypeData;
 
         /* Get the message length. */
-        rxFrame->length = (cs_temp & CAN_CS_DLC_MASK) >> CAN_CS_DLC_SHIFT;
+        rxFrame->length = (uint8_t)((cs_temp & CAN_CS_DLC_MASK) >> CAN_CS_DLC_SHIFT);
+
+        /* Get the time stamp. */
+        rxFrame->timestamp = (uint16_t)((cs_temp & CAN_CS_TIME_STAMP_MASK) >> CAN_CS_TIME_STAMP_SHIFT);
 
         /* Calculate the DWORD number, dataSize 0/1/2/3 corresponds to 8/16/32/64
            Bytes payload. */
-        for (cnt = 0; cnt < dataSize + 1; cnt++)
+        for (cnt = 0; cnt < (dataSize + 1U); cnt++)
         {
-            payload_dword *= 2;
+            payload_dword *= 2U;
         }
 
         /* Store Message Payload. */
         for (cnt = 0; cnt < payload_dword; cnt++)
         {
-            rxFrame->dataWord[cnt] = mbAddr[offset + 2 + cnt];
+            rxFrame->dataWord[cnt] = mbAddr[offset + 2U + cnt];
         }
 
         /* Read free-running timer to unlock Rx Message Buffer. */
         (void)base->TIMER;
 
-        if (kFLEXCAN_RxMbFull == rx_code)
+        if ((uint32_t)kFLEXCAN_RxMbFull == rx_code)
         {
             return kStatus_Success;
         }
@@ -1308,15 +2162,25 @@ status_t FLEXCAN_ReadFDRxMb(CAN_Type *base, uint8_t mbIdx, flexcan_fd_frame_t *r
 }
 #endif
 
+/*!
+ * brief Reads a FlexCAN Message from Rx FIFO.
+ *
+ * This function reads a CAN message from the FlexCAN build-in Rx FIFO.
+ *
+ * param base FlexCAN peripheral base address.
+ * param rxFrame Pointer to CAN message frame structure for reception.
+ * retval kStatus_Success - Read Message from Rx FIFO successfully.
+ * retval kStatus_Fail    - Rx FIFO is not enabled.
+ */
 status_t FLEXCAN_ReadRxFifo(CAN_Type *base, flexcan_frame_t *rxFrame)
 {
     /* Assertion. */
-    assert(rxFrame);
+    assert(NULL != rxFrame);
 
     uint32_t cs_temp;
 
     /* Check if Rx FIFO is Enabled. */
-    if (base->MCR & CAN_MCR_RFEN_MASK)
+    if (0U != (base->MCR & CAN_MCR_RFEN_MASK))
     {
         /* Read CS field of Rx Message Buffer to lock Message Buffer. */
         cs_temp = base->MB[0].CS;
@@ -1326,13 +2190,18 @@ status_t FLEXCAN_ReadRxFifo(CAN_Type *base, flexcan_frame_t *rxFrame)
         rxFrame->id = base->MB[0].ID & (CAN_ID_EXT_MASK | CAN_ID_STD_MASK);
 
         /* Get the message ID and format. */
-        rxFrame->format = (cs_temp & CAN_CS_IDE_MASK) ? kFLEXCAN_FrameFormatExtend : kFLEXCAN_FrameFormatStandard;
+        rxFrame->format = (cs_temp & CAN_CS_IDE_MASK) != 0U ? (uint32_t)kFLEXCAN_FrameFormatExtend :
+                                                              (uint32_t)kFLEXCAN_FrameFormatStandard;
 
         /* Get the message type. */
-        rxFrame->type = (cs_temp & CAN_CS_RTR_MASK) ? kFLEXCAN_FrameTypeRemote : kFLEXCAN_FrameTypeData;
+        rxFrame->type =
+            (cs_temp & CAN_CS_RTR_MASK) != 0U ? (uint32_t)kFLEXCAN_FrameTypeRemote : (uint32_t)kFLEXCAN_FrameTypeData;
 
         /* Get the message length. */
-        rxFrame->length = (cs_temp & CAN_CS_DLC_MASK) >> CAN_CS_DLC_SHIFT;
+        rxFrame->length = (uint8_t)((cs_temp & CAN_CS_DLC_MASK) >> CAN_CS_DLC_SHIFT);
+
+        /* Get the time stamp. */
+        rxFrame->timestamp = (uint16_t)((cs_temp & CAN_CS_TIME_STAMP_MASK) >> CAN_CS_TIME_STAMP_SHIFT);
 
         /* Store Message Payload. */
         rxFrame->dataWord0 = base->MB[0].WORD0;
@@ -1352,26 +2221,41 @@ status_t FLEXCAN_ReadRxFifo(CAN_Type *base, flexcan_frame_t *rxFrame)
     }
 }
 
+/*!
+ * brief Performs a polling send transaction on the CAN bus.
+ *
+ * Note that a transfer handle does not need to be created  before calling this API.
+ *
+ * param base FlexCAN peripheral base pointer.
+ * param mbIdx The FlexCAN Message Buffer index.
+ * param txFrame Pointer to CAN message frame to be sent.
+ * retval kStatus_Success - Write Tx Message Buffer Successfully.
+ * retval kStatus_Fail    - Tx Message Buffer is currently in use.
+ */
 status_t FLEXCAN_TransferSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *txFrame)
 {
     /* Write Tx Message Buffer to initiate a data sending. */
-    if (kStatus_Success == FLEXCAN_WriteTxMb(base, mbIdx, txFrame))
+    if (kStatus_Success == FLEXCAN_WriteTxMb(base, mbIdx, (const flexcan_frame_t *)(uint32_t)txFrame))
     {
-        /* Wait until CAN Message send out. */
+/* Wait until CAN Message send out. */
 #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0)
-        while (!FLEXCAN_GetMbStatusFlags(base, (uint64_t)1 << mbIdx))
+        uint64_t u64flag = 1;
+        while (0U == FLEXCAN_GetMbStatusFlags(base, u64flag << mbIdx))
 #else
-        while (!FLEXCAN_GetMbStatusFlags(base, 1 << mbIdx))
+        uint32_t u32flag = 1;
+        while (0U == FLEXCAN_GetMbStatusFlags(base, u32flag << mbIdx))
 #endif
         {
         }
 
-        /* Clean Tx Message Buffer Flag. */
+/* Clean Tx Message Buffer Flag. */
 #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0)
-        FLEXCAN_ClearMbStatusFlags(base, (uint64_t)1 << mbIdx);
+        FLEXCAN_ClearMbStatusFlags(base, u64flag << mbIdx);
 #else
-        FLEXCAN_ClearMbStatusFlags(base, 1 << mbIdx);
+        FLEXCAN_ClearMbStatusFlags(base, u32flag << mbIdx);
 #endif
+        /*After TX MB tranfered success, update the Timestamp from MB[mbIdx].CS register*/
+        txFrame->timestamp = (uint16_t)((base->MB[mbIdx].CS & CAN_CS_TIME_STAMP_MASK) >> CAN_CS_TIME_STAMP_SHIFT);
 
         return kStatus_Success;
     }
@@ -1381,22 +2265,36 @@ status_t FLEXCAN_TransferSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_fra
     }
 }
 
+/*!
+ * brief Performs a polling receive transaction on the CAN bus.
+ *
+ * Note that a transfer handle does not need to be created  before calling this API.
+ *
+ * param base FlexCAN peripheral base pointer.
+ * param mbIdx The FlexCAN Message Buffer index.
+ * param rxFrame Pointer to CAN message frame structure for reception.
+ * retval kStatus_Success            - Rx Message Buffer is full and has been read successfully.
+ * retval kStatus_FLEXCAN_RxOverflow - Rx Message Buffer is already overflowed and has been read successfully.
+ * retval kStatus_Fail               - Rx Message Buffer is empty.
+ */
 status_t FLEXCAN_TransferReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *rxFrame)
 {
-    /* Wait until Rx Message Buffer non-empty. */
+/* Wait until Rx Message Buffer non-empty. */
 #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0)
-    while (!FLEXCAN_GetMbStatusFlags(base, (uint64_t)1 << mbIdx))
+    uint64_t u64flag = 1;
+    while (0U == FLEXCAN_GetMbStatusFlags(base, u64flag << mbIdx))
 #else
-    while (!FLEXCAN_GetMbStatusFlags(base, 1 << mbIdx))
+    uint32_t u32flag = 1;
+    while (0U == FLEXCAN_GetMbStatusFlags(base, u32flag << mbIdx))
 #endif
     {
     }
 
-    /* Clean Rx Message Buffer Flag. */
+/* Clean Rx Message Buffer Flag. */
 #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0)
-    FLEXCAN_ClearMbStatusFlags(base, (uint64_t)1 << mbIdx);
+    FLEXCAN_ClearMbStatusFlags(base, u64flag << mbIdx);
 #else
-    FLEXCAN_ClearMbStatusFlags(base, 1 << mbIdx);
+    FLEXCAN_ClearMbStatusFlags(base, u32flag << mbIdx);
 #endif
 
     /* Read Received CAN Message. */
@@ -1404,26 +2302,43 @@ status_t FLEXCAN_TransferReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_
 }
 
 #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
+/*!
+ * brief Performs a polling send transaction on the CAN bus.
+ *
+ * Note that a transfer handle does not need to be created before calling this API.
+ *
+ * param base FlexCAN peripheral base pointer.
+ * param mbIdx The FlexCAN FD Message Buffer index.
+ * param txFrame Pointer to CAN FD message frame to be sent.
+ * retval kStatus_Success - Write Tx Message Buffer Successfully.
+ * retval kStatus_Fail    - Tx Message Buffer is currently in use.
+ */
 status_t FLEXCAN_TransferFDSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_fd_frame_t *txFrame)
 {
     /* Write Tx Message Buffer to initiate a data sending. */
-    if (kStatus_Success == FLEXCAN_WriteFDTxMb(base, mbIdx, txFrame))
+    if (kStatus_Success == FLEXCAN_WriteFDTxMb(base, mbIdx, (const flexcan_fd_frame_t *)(uint32_t)txFrame))
     {
-        /* Wait until CAN Message send out. */
+/* Wait until CAN Message send out. */
 #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0)
-        while (!FLEXCAN_GetMbStatusFlags(base, (uint64_t)1 << mbIdx))
+        uint64_t u64flag = 1;
+        while (0U == FLEXCAN_GetMbStatusFlags(base, u64flag << mbIdx))
 #else
-        while (!FLEXCAN_GetMbStatusFlags(base, 1 << mbIdx))
+        uint32_t u32flag = 1;
+        while (0U == FLEXCAN_GetMbStatusFlags(base, u32flag << mbIdx))
 #endif
         {
         }
 
-        /* Clean Tx Message Buffer Flag. */
+/* Clean Tx Message Buffer Flag. */
 #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0)
-        FLEXCAN_ClearMbStatusFlags(base, (uint64_t)1 << mbIdx);
+        FLEXCAN_ClearMbStatusFlags(base, u64flag << mbIdx);
 #else
-        FLEXCAN_ClearMbStatusFlags(base, 1 << mbIdx);
+        FLEXCAN_ClearMbStatusFlags(base, u32flag << mbIdx);
 #endif
+        /*After TX MB tranfered success, update the Timestamp from base->MB[offset for CANFD].CS register*/
+        volatile uint32_t *mbAddr = &(base->MB[0].CS);
+        uint32_t offset           = FLEXCAN_GetFDMailboxOffset(base, mbIdx);
+        txFrame->timestamp        = (uint16_t)((mbAddr[offset] & CAN_CS_TIME_STAMP_MASK) >> CAN_CS_TIME_STAMP_SHIFT);
 
         return kStatus_Success;
     }
@@ -1433,22 +2348,36 @@ status_t FLEXCAN_TransferFDSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_f
     }
 }
 
+/*!
+ * brief Performs a polling receive transaction on the CAN bus.
+ *
+ * Note that a transfer handle does not need to be created before calling this API.
+ *
+ * param base FlexCAN peripheral base pointer.
+ * param mbIdx The FlexCAN FD Message Buffer index.
+ * param rxFrame Pointer to CAN FD message frame structure for reception.
+ * retval kStatus_Success            - Rx Message Buffer is full and has been read successfully.
+ * retval kStatus_FLEXCAN_RxOverflow - Rx Message Buffer is already overflowed and has been read successfully.
+ * retval kStatus_Fail               - Rx Message Buffer is empty.
+ */
 status_t FLEXCAN_TransferFDReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_fd_frame_t *rxFrame)
 {
-    /* Wait until Rx Message Buffer non-empty. */
+/* Wait until Rx Message Buffer non-empty. */
 #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0)
-    while (!FLEXCAN_GetMbStatusFlags(base, (uint64_t)1 << mbIdx))
+    uint64_t u64flag = 1;
+    while (0U == FLEXCAN_GetMbStatusFlags(base, u64flag << mbIdx))
 #else
-    while (!FLEXCAN_GetMbStatusFlags(base, 1 << mbIdx))
+    uint32_t u32flag = 1;
+    while (0U == FLEXCAN_GetMbStatusFlags(base, u32flag << mbIdx))
 #endif
     {
     }
 
-    /* Clean Rx Message Buffer Flag. */
+/* Clean Rx Message Buffer Flag. */
 #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0)
-    FLEXCAN_ClearMbStatusFlags(base, (uint64_t)1 << mbIdx);
+    FLEXCAN_ClearMbStatusFlags(base, u64flag << mbIdx);
 #else
-    FLEXCAN_ClearMbStatusFlags(base, 1 << mbIdx);
+    FLEXCAN_ClearMbStatusFlags(base, u32flag << mbIdx);
 #endif
 
     /* Read Received CAN Message. */
@@ -1456,12 +2385,22 @@ status_t FLEXCAN_TransferFDReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexca
 }
 #endif
 
+/*!
+ * brief Performs a polling receive transaction from Rx FIFO on the CAN bus.
+ *
+ * Note that a transfer handle does not need to be created  before calling this API.
+ *
+ * param base FlexCAN peripheral base pointer.
+ * param rxFrame Pointer to CAN message frame structure for reception.
+ * retval kStatus_Success - Read Message from Rx FIFO successfully.
+ * retval kStatus_Fail    - Rx FIFO is not enabled.
+ */
 status_t FLEXCAN_TransferReceiveFifoBlocking(CAN_Type *base, flexcan_frame_t *rxFrame)
 {
     status_t rxFifoStatus;
 
     /* Wait until Rx FIFO non-empty. */
-    while (!FLEXCAN_GetMbStatusFlags(base, kFLEXCAN_RxFifoFrameAvlFlag))
+    while (0U == FLEXCAN_GetMbStatusFlags(base, (uint32_t)kFLEXCAN_RxFifoFrameAvlFlag))
     {
     }
 
@@ -1469,25 +2408,37 @@ status_t FLEXCAN_TransferReceiveFifoBlocking(CAN_Type *base, flexcan_frame_t *rx
     rxFifoStatus = FLEXCAN_ReadRxFifo(base, rxFrame);
 
     /* Clean Rx Fifo available flag. */
-    FLEXCAN_ClearMbStatusFlags(base, kFLEXCAN_RxFifoFrameAvlFlag);
+    FLEXCAN_ClearMbStatusFlags(base, (uint32_t)kFLEXCAN_RxFifoFrameAvlFlag);
 
     return rxFifoStatus;
 }
 
+/*!
+ * brief Initializes the FlexCAN handle.
+ *
+ * This function initializes the FlexCAN handle, which can be used for other FlexCAN
+ * transactional APIs. Usually, for a specified FlexCAN instance,
+ * call this API once to get the initialized handle.
+ *
+ * param base FlexCAN peripheral base address.
+ * param handle FlexCAN handle pointer.
+ * param callback The callback function.
+ * param userData The parameter of the callback function.
+ */
 void FLEXCAN_TransferCreateHandle(CAN_Type *base,
                                   flexcan_handle_t *handle,
                                   flexcan_transfer_callback_t callback,
                                   void *userData)
 {
-    assert(handle);
+    assert(NULL != handle);
 
     uint8_t instance;
 
     /* Clean FlexCAN transfer handle. */
-    memset(handle, 0, sizeof(*handle));
+    (void)memset(handle, 0, sizeof(*handle));
 
     /* Get instance from peripheral base address. */
-    instance = FLEXCAN_GetInstance(base);
+    instance = (uint8_t)FLEXCAN_GetInstance(base);
 
     /* Save the context in global variables to support the double weak mechanism. */
     s_flexcanHandle[instance] = handle;
@@ -1504,64 +2455,81 @@ void FLEXCAN_TransferCreateHandle(CAN_Type *base,
      */
     if (handle->callback != NULL)
     {
-        FLEXCAN_EnableInterrupts(base, kFLEXCAN_BusOffInterruptEnable | kFLEXCAN_ErrorInterruptEnable |
-                                           kFLEXCAN_RxWarningInterruptEnable | kFLEXCAN_TxWarningInterruptEnable |
-                                           kFLEXCAN_WakeUpInterruptEnable);
+        FLEXCAN_EnableInterrupts(
+            base, (uint32_t)kFLEXCAN_BusOffInterruptEnable | (uint32_t)kFLEXCAN_ErrorInterruptEnable |
+                      (uint32_t)kFLEXCAN_RxWarningInterruptEnable | (uint32_t)kFLEXCAN_TxWarningInterruptEnable |
+                      (uint32_t)kFLEXCAN_WakeUpInterruptEnable);
     }
     else
     {
-        FLEXCAN_DisableInterrupts(base, kFLEXCAN_BusOffInterruptEnable | kFLEXCAN_ErrorInterruptEnable |
-                                            kFLEXCAN_RxWarningInterruptEnable | kFLEXCAN_TxWarningInterruptEnable |
-                                            kFLEXCAN_WakeUpInterruptEnable);
+        FLEXCAN_DisableInterrupts(
+            base, (uint32_t)kFLEXCAN_BusOffInterruptEnable | (uint32_t)kFLEXCAN_ErrorInterruptEnable |
+                      (uint32_t)kFLEXCAN_RxWarningInterruptEnable | (uint32_t)kFLEXCAN_TxWarningInterruptEnable |
+                      (uint32_t)kFLEXCAN_WakeUpInterruptEnable);
     }
 
     /* Enable interrupts in NVIC. */
-    EnableIRQ((IRQn_Type)(s_flexcanRxWarningIRQ[instance]));
-    EnableIRQ((IRQn_Type)(s_flexcanTxWarningIRQ[instance]));
-    EnableIRQ((IRQn_Type)(s_flexcanWakeUpIRQ[instance]));
-    EnableIRQ((IRQn_Type)(s_flexcanErrorIRQ[instance]));
-    EnableIRQ((IRQn_Type)(s_flexcanBusOffIRQ[instance]));
-    EnableIRQ((IRQn_Type)(s_flexcanMbIRQ[instance]));
+    (void)EnableIRQ((IRQn_Type)(s_flexcanRxWarningIRQ[instance]));
+    (void)EnableIRQ((IRQn_Type)(s_flexcanTxWarningIRQ[instance]));
+    (void)EnableIRQ((IRQn_Type)(s_flexcanWakeUpIRQ[instance]));
+    (void)EnableIRQ((IRQn_Type)(s_flexcanErrorIRQ[instance]));
+    (void)EnableIRQ((IRQn_Type)(s_flexcanBusOffIRQ[instance]));
+    (void)EnableIRQ((IRQn_Type)(s_flexcanMbIRQ[instance]));
 }
 
+/*!
+ * brief Sends a message using IRQ.
+ *
+ * This function sends a message using IRQ. This is a non-blocking function, which returns
+ * right away. When messages have been sent out, the send callback function is called.
+ *
+ * param base FlexCAN peripheral base address.
+ * param handle FlexCAN handle pointer.
+ * param xfer FlexCAN Message Buffer transfer structure. See the #flexcan_mb_transfer_t.
+ * retval kStatus_Success        Start Tx Message Buffer sending process successfully.
+ * retval kStatus_Fail           Write Tx Message Buffer failed.
+ * retval kStatus_FLEXCAN_TxBusy Tx Message Buffer is in use.
+ */
 status_t FLEXCAN_TransferSendNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *xfer)
 {
     /* Assertion. */
-    assert(handle);
-    assert(xfer);
+    assert(NULL != handle);
+    assert(NULL != xfer);
     assert(xfer->mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK));
-    assert(!FLEXCAN_IsMbOccupied(base, xfer->mbIdx));
+    assert(false == FLEXCAN_IsMbOccupied(base, xfer->mbIdx));
 
     /* Check if Message Buffer is idle. */
-    if (kFLEXCAN_StateIdle == handle->mbState[xfer->mbIdx])
+    if ((uint8_t)kFLEXCAN_StateIdle == handle->mbState[xfer->mbIdx])
     {
         /* Distinguish transmit type. */
-        if (kFLEXCAN_FrameTypeRemote == xfer->frame->type)
+        if ((uint32_t)kFLEXCAN_FrameTypeRemote == xfer->frame->type)
         {
-            handle->mbState[xfer->mbIdx] = kFLEXCAN_StateTxRemote;
-
-            /* Register user Frame buffer to receive remote Frame. */
-            handle->mbFrameBuf[xfer->mbIdx] = xfer->frame;
+            handle->mbState[xfer->mbIdx] = (uint8_t)kFLEXCAN_StateTxRemote;
         }
         else
         {
-            handle->mbState[xfer->mbIdx] = kFLEXCAN_StateTxData;
+            handle->mbState[xfer->mbIdx] = (uint8_t)kFLEXCAN_StateTxData;
         }
 
-        if (kStatus_Success == FLEXCAN_WriteTxMb(base, xfer->mbIdx, xfer->frame))
+        /* Register user Frame buffer to the handle. */
+        handle->mbFrameBuf[xfer->mbIdx] = xfer->frame;
+
+        if (kStatus_Success == FLEXCAN_WriteTxMb(base, xfer->mbIdx, (const flexcan_frame_t *)(uint32_t)xfer->frame))
         {
-            /* Enable Message Buffer Interrupt. */
+/* Enable Message Buffer Interrupt. */
 #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0)
-            FLEXCAN_EnableMbInterrupts(base, (uint64_t)1 << xfer->mbIdx);
+            uint64_t u64mask = 1;
+            FLEXCAN_EnableMbInterrupts(base, u64mask << xfer->mbIdx);
 #else
-            FLEXCAN_EnableMbInterrupts(base, 1 << xfer->mbIdx);
+            uint32_t u32mask = 1;
+            FLEXCAN_EnableMbInterrupts(base, u32mask << xfer->mbIdx);
 #endif
 
             return kStatus_Success;
         }
         else
         {
-            handle->mbState[xfer->mbIdx] = kFLEXCAN_StateIdle;
+            handle->mbState[xfer->mbIdx] = (uint8_t)kFLEXCAN_StateIdle;
             return kStatus_Fail;
         }
     }
@@ -1571,27 +2539,41 @@ status_t FLEXCAN_TransferSendNonBlocking(CAN_Type *base, flexcan_handle_t *handl
     }
 }
 
+/*!
+ * brief Receives a message using IRQ.
+ *
+ * This function receives a message using IRQ. This is non-blocking function, which returns
+ * right away. When the message has been received, the receive callback function is called.
+ *
+ * param base FlexCAN peripheral base address.
+ * param handle FlexCAN handle pointer.
+ * param xfer FlexCAN Message Buffer transfer structure. See the #flexcan_mb_transfer_t.
+ * retval kStatus_Success        - Start Rx Message Buffer receiving process successfully.
+ * retval kStatus_FLEXCAN_RxBusy - Rx Message Buffer is in use.
+ */
 status_t FLEXCAN_TransferReceiveNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *xfer)
 {
     /* Assertion. */
-    assert(handle);
-    assert(xfer);
+    assert(NULL != handle);
+    assert(NULL != xfer);
     assert(xfer->mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK));
-    assert(!FLEXCAN_IsMbOccupied(base, xfer->mbIdx));
+    assert(false == FLEXCAN_IsMbOccupied(base, xfer->mbIdx));
 
     /* Check if Message Buffer is idle. */
-    if (kFLEXCAN_StateIdle == handle->mbState[xfer->mbIdx])
+    if ((uint8_t)kFLEXCAN_StateIdle == handle->mbState[xfer->mbIdx])
     {
-        handle->mbState[xfer->mbIdx] = kFLEXCAN_StateRxData;
+        handle->mbState[xfer->mbIdx] = (uint8_t)kFLEXCAN_StateRxData;
 
         /* Register Message Buffer. */
         handle->mbFrameBuf[xfer->mbIdx] = xfer->frame;
 
-        /* Enable Message Buffer Interrupt. */
+/* Enable Message Buffer Interrupt. */
 #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0)
-        FLEXCAN_EnableMbInterrupts(base, (uint64_t)1 << xfer->mbIdx);
+        uint64_t u64mask = 1;
+        FLEXCAN_EnableMbInterrupts(base, u64mask << xfer->mbIdx);
 #else
-        FLEXCAN_EnableMbInterrupts(base, 1 << xfer->mbIdx);
+        uint32_t u32mask = 1;
+        FLEXCAN_EnableMbInterrupts(base, u32mask << xfer->mbIdx);
 #endif
 
         return kStatus_Success;
@@ -1603,44 +2585,60 @@ status_t FLEXCAN_TransferReceiveNonBlocking(CAN_Type *base, flexcan_handle_t *ha
 }
 
 #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
+/*!
+ * brief Sends a message using IRQ.
+ *
+ * This function sends a message using IRQ. This is a non-blocking function, which returns
+ * right away. When messages have been sent out, the send callback function is called.
+ *
+ * param base FlexCAN peripheral base address.
+ * param handle FlexCAN handle pointer.
+ * param xfer FlexCAN FD Message Buffer transfer structure. See the #flexcan_mb_transfer_t.
+ * retval kStatus_Success        Start Tx Message Buffer sending process successfully.
+ * retval kStatus_Fail           Write Tx Message Buffer failed.
+ * retval kStatus_FLEXCAN_TxBusy Tx Message Buffer is in use.
+ */
 status_t FLEXCAN_TransferFDSendNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *xfer)
 {
     /* Assertion. */
-    assert(handle);
-    assert(xfer);
+    assert(NULL != handle);
+    assert(NULL != xfer);
     assert(xfer->mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK));
-    assert(!FLEXCAN_IsMbOccupied(base, xfer->mbIdx));
+    assert(false == FLEXCAN_IsMbOccupied(base, xfer->mbIdx));
 
     /* Check if Message Buffer is idle. */
-    if (kFLEXCAN_StateIdle == handle->mbState[xfer->mbIdx])
+    if ((uint8_t)kFLEXCAN_StateIdle == handle->mbState[xfer->mbIdx])
     {
         /* Distinguish transmit type. */
-        if (kFLEXCAN_FrameTypeRemote == xfer->frame->type)
+        if ((uint32_t)kFLEXCAN_FrameTypeRemote == xfer->framefd->type)
         {
-            handle->mbState[xfer->mbIdx] = kFLEXCAN_StateTxRemote;
-
-            /* Register user Frame buffer to receive remote Frame. */
-            handle->mbFDFrameBuf[xfer->mbIdx] = xfer->framefd;
+            handle->mbState[xfer->mbIdx] = (uint8_t)kFLEXCAN_StateTxRemote;
         }
         else
         {
-            handle->mbState[xfer->mbIdx] = kFLEXCAN_StateTxData;
+            handle->mbState[xfer->mbIdx] = (uint8_t)kFLEXCAN_StateTxData;
         }
 
-        if (kStatus_Success == FLEXCAN_WriteFDTxMb(base, xfer->mbIdx, xfer->framefd))
+        /* Register user Frame buffer to the handle. */
+        handle->mbFDFrameBuf[xfer->mbIdx] = xfer->framefd;
+
+        if (kStatus_Success ==
+            FLEXCAN_WriteFDTxMb(base, xfer->mbIdx, (const flexcan_fd_frame_t *)(uint32_t)xfer->framefd))
         {
-            /* Enable Message Buffer Interrupt. */
+/* Enable Message Buffer Interrupt. */
 #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0)
-            FLEXCAN_EnableMbInterrupts(base, (uint64_t)1 << xfer->mbIdx);
+            uint64_t u64mask = 1;
+            FLEXCAN_EnableMbInterrupts(base, u64mask << xfer->mbIdx);
 #else
-            FLEXCAN_EnableMbInterrupts(base, 1 << xfer->mbIdx);
+            uint32_t u32mask = 1;
+            FLEXCAN_EnableMbInterrupts(base, u32mask << xfer->mbIdx);
 #endif
 
             return kStatus_Success;
         }
         else
         {
-            handle->mbState[xfer->mbIdx] = kFLEXCAN_StateIdle;
+            handle->mbState[xfer->mbIdx] = (uint8_t)kFLEXCAN_StateIdle;
             return kStatus_Fail;
         }
     }
@@ -1650,27 +2648,41 @@ status_t FLEXCAN_TransferFDSendNonBlocking(CAN_Type *base, flexcan_handle_t *han
     }
 }
 
+/*!
+ * brief Receives a message using IRQ.
+ *
+ * This function receives a message using IRQ. This is non-blocking function, which returns
+ * right away. When the message has been received, the receive callback function is called.
+ *
+ * param base FlexCAN peripheral base address.
+ * param handle FlexCAN handle pointer.
+ * param xfer FlexCAN FD Message Buffer transfer structure. See the #flexcan_mb_transfer_t.
+ * retval kStatus_Success        - Start Rx Message Buffer receiving process successfully.
+ * retval kStatus_FLEXCAN_RxBusy - Rx Message Buffer is in use.
+ */
 status_t FLEXCAN_TransferFDReceiveNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *xfer)
 {
     /* Assertion. */
-    assert(handle);
-    assert(xfer);
+    assert(NULL != handle);
+    assert(NULL != xfer);
     assert(xfer->mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK));
-    assert(!FLEXCAN_IsMbOccupied(base, xfer->mbIdx));
+    assert(false == FLEXCAN_IsMbOccupied(base, xfer->mbIdx));
 
     /* Check if Message Buffer is idle. */
-    if (kFLEXCAN_StateIdle == handle->mbState[xfer->mbIdx])
+    if ((uint8_t)kFLEXCAN_StateIdle == handle->mbState[xfer->mbIdx])
     {
-        handle->mbState[xfer->mbIdx] = kFLEXCAN_StateRxData;
+        handle->mbState[xfer->mbIdx] = (uint8_t)kFLEXCAN_StateRxData;
 
         /* Register Message Buffer. */
         handle->mbFDFrameBuf[xfer->mbIdx] = xfer->framefd;
 
-        /* Enable Message Buffer Interrupt. */
+/* Enable Message Buffer Interrupt. */
 #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0)
-        FLEXCAN_EnableMbInterrupts(base, (uint64_t)1 << xfer->mbIdx);
+        uint64_t u64mask = 1;
+        FLEXCAN_EnableMbInterrupts(base, u64mask << xfer->mbIdx);
 #else
-        FLEXCAN_EnableMbInterrupts(base, 1 << xfer->mbIdx);
+        uint32_t u32mask = 1;
+        FLEXCAN_EnableMbInterrupts(base, u32mask << xfer->mbIdx);
 #endif
 
         return kStatus_Success;
@@ -1682,23 +2694,35 @@ status_t FLEXCAN_TransferFDReceiveNonBlocking(CAN_Type *base, flexcan_handle_t *
 }
 #endif
 
+/*!
+ * brief Receives a message from Rx FIFO using IRQ.
+ *
+ * This function receives a message using IRQ. This is a non-blocking function, which returns
+ * right away. When all messages have been received, the receive callback function is called.
+ *
+ * param base FlexCAN peripheral base address.
+ * param handle FlexCAN handle pointer.
+ * param xfer FlexCAN Rx FIFO transfer structure. See the ref flexcan_fifo_transfer_t.
+ * retval kStatus_Success            - Start Rx FIFO receiving process successfully.
+ * retval kStatus_FLEXCAN_RxFifoBusy - Rx FIFO is currently in use.
+ */
 status_t FLEXCAN_TransferReceiveFifoNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_fifo_transfer_t *xfer)
 {
     /* Assertion. */
-    assert(handle);
-    assert(xfer);
+    assert(NULL != handle);
+    assert(NULL != xfer);
 
     /* Check if Message Buffer is idle. */
-    if (kFLEXCAN_StateIdle == handle->rxFifoState)
+    if ((uint8_t)kFLEXCAN_StateIdle == handle->rxFifoState)
     {
-        handle->rxFifoState = kFLEXCAN_StateRxFifo;
+        handle->rxFifoState = (uint8_t)kFLEXCAN_StateRxFifo;
 
         /* Register Message Buffer. */
         handle->rxFifoFrameBuf = xfer->frame;
 
         /* Enable Message Buffer Interrupt. */
-        FLEXCAN_EnableMbInterrupts(
-            base, kFLEXCAN_RxFifoOverflowFlag | kFLEXCAN_RxFifoWarningFlag | kFLEXCAN_RxFifoFrameAvlFlag);
+        FLEXCAN_EnableMbInterrupts(base, (uint32_t)kFLEXCAN_RxFifoOverflowFlag | (uint32_t)kFLEXCAN_RxFifoWarningFlag |
+                                             (uint32_t)kFLEXCAN_RxFifoFrameAvlFlag);
 
         return kStatus_Success;
     }
@@ -1708,171 +2732,255 @@ status_t FLEXCAN_TransferReceiveFifoNonBlocking(CAN_Type *base, flexcan_handle_t
     }
 }
 
+/*!
+ * brief Aborts the interrupt driven message send process.
+ *
+ * This function aborts the interrupt driven message send process.
+ *
+ * param base FlexCAN peripheral base address.
+ * param handle FlexCAN handle pointer.
+ * param mbIdx The FlexCAN Message Buffer index.
+ */
 void FLEXCAN_TransferAbortSend(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx)
 {
     /* Assertion. */
-    assert(handle);
+    assert(NULL != handle);
     assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK));
-    assert(!FLEXCAN_IsMbOccupied(base, mbIdx));
+    assert(NULL != handle->mbFrameBuf[mbIdx]);
+    assert(false == FLEXCAN_IsMbOccupied(base, mbIdx));
 
-    /* Disable Message Buffer Interrupt. */
+/* Disable Message Buffer Interrupt. */
 #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0)
-    FLEXCAN_DisableMbInterrupts(base, (uint64_t)1 << mbIdx);
+    uint64_t u64mask = 1;
+    FLEXCAN_DisableMbInterrupts(base, u64mask << mbIdx);
 #else
-    FLEXCAN_DisableMbInterrupts(base, 1 << mbIdx);
+    uint32_t u32mask = 1;
+    FLEXCAN_DisableMbInterrupts(base, u32mask << mbIdx);
 #endif
 
+    /*Update the TX frame 's time stamp by MB[mbIdx].cs*/
+    handle->mbFrameBuf[mbIdx]->timestamp =
+        (uint16_t)((base->MB[mbIdx].CS & CAN_CS_TIME_STAMP_MASK) >> CAN_CS_TIME_STAMP_SHIFT);
+
     /* Un-register handle. */
-    handle->mbFrameBuf[mbIdx] = 0x0;
+    handle->mbFrameBuf[mbIdx] = NULL;
 
     /* Clean Message Buffer. */
     FLEXCAN_SetTxMbConfig(base, mbIdx, true);
 
-    handle->mbState[mbIdx] = kFLEXCAN_StateIdle;
+    handle->mbState[mbIdx] = (uint8_t)kFLEXCAN_StateIdle;
 }
 
 #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
+/*!
+ * brief Aborts the interrupt driven message send process.
+ *
+ * This function aborts the interrupt driven message send process.
+ *
+ * param base FlexCAN peripheral base address.
+ * param handle FlexCAN handle pointer.
+ * param mbIdx The FlexCAN FD Message Buffer index.
+ */
 void FLEXCAN_TransferFDAbortSend(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx)
 {
     /* Assertion. */
-    assert(handle);
+    assert(NULL != handle);
     assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK));
-    assert(!FLEXCAN_IsMbOccupied(base, mbIdx));
+    assert(NULL != handle->mbFDFrameBuf[mbIdx]);
+    assert(false == FLEXCAN_IsMbOccupied(base, mbIdx));
 
-    /* Disable Message Buffer Interrupt. */
+/* Disable Message Buffer Interrupt. */
 #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0)
-    FLEXCAN_DisableMbInterrupts(base, (uint64_t)1 << mbIdx);
+    uint64_t u64mask = 1;
+    FLEXCAN_DisableMbInterrupts(base, u64mask << mbIdx);
 #else
-    FLEXCAN_DisableMbInterrupts(base, 1 << mbIdx);
+    uint32_t u32mask = 1;
+    FLEXCAN_DisableMbInterrupts(base, u32mask << mbIdx);
 #endif
 
+    /*Update the TX frame 's time stamp by base->MB[offset for CANFD].CS*/
+    volatile uint32_t *mbAddr = &(base->MB[0].CS);
+    uint32_t offset           = FLEXCAN_GetFDMailboxOffset(base, mbIdx);
+    handle->mbFDFrameBuf[mbIdx]->timestamp =
+        (uint16_t)((mbAddr[offset] & CAN_CS_TIME_STAMP_MASK) >> CAN_CS_TIME_STAMP_SHIFT);
+
     /* Un-register handle. */
-    handle->mbFDFrameBuf[mbIdx] = 0x0;
+    handle->mbFDFrameBuf[mbIdx] = NULL;
 
     /* Clean Message Buffer. */
     FLEXCAN_SetFDTxMbConfig(base, mbIdx, true);
 
-    handle->mbState[mbIdx] = kFLEXCAN_StateIdle;
+    handle->mbState[mbIdx] = (uint8_t)kFLEXCAN_StateIdle;
 }
 
+/*!
+ * brief Aborts the interrupt driven message receive process.
+ *
+ * This function aborts the interrupt driven message receive process.
+ *
+ * param base FlexCAN peripheral base address.
+ * param handle FlexCAN handle pointer.
+ * param mbIdx The FlexCAN FD Message Buffer index.
+ */
 void FLEXCAN_TransferFDAbortReceive(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx)
 {
     /* Assertion. */
-    assert(handle);
+    assert(NULL != handle);
     assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK));
-    assert(!FLEXCAN_IsMbOccupied(base, mbIdx));
+    assert(false == FLEXCAN_IsMbOccupied(base, mbIdx));
 
-    /* Disable Message Buffer Interrupt. */
+/* Disable Message Buffer Interrupt. */
 #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0)
-    FLEXCAN_DisableMbInterrupts(base, (uint64_t)1 << mbIdx);
+    uint64_t u64mask = 1;
+    FLEXCAN_DisableMbInterrupts(base, u64mask << mbIdx);
 #else
-    FLEXCAN_DisableMbInterrupts(base, 1 << mbIdx);
+    uint32_t u32mask = 1;
+    FLEXCAN_DisableMbInterrupts(base, u32mask << mbIdx);
 #endif
 
     /* Un-register handle. */
-    handle->mbFDFrameBuf[mbIdx] = 0x0;
-    handle->mbState[mbIdx] = kFLEXCAN_StateIdle;
+    handle->mbFDFrameBuf[mbIdx] = NULL;
+    handle->mbState[mbIdx]      = (uint8_t)kFLEXCAN_StateIdle;
 }
 #endif
 
+/*!
+ * brief Aborts the interrupt driven message receive process.
+ *
+ * This function aborts the interrupt driven message receive process.
+ *
+ * param base FlexCAN peripheral base address.
+ * param handle FlexCAN handle pointer.
+ * param mbIdx The FlexCAN Message Buffer index.
+ */
 void FLEXCAN_TransferAbortReceive(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx)
 {
     /* Assertion. */
-    assert(handle);
+    assert(NULL != handle);
     assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK));
-    assert(!FLEXCAN_IsMbOccupied(base, mbIdx));
+    assert(false == FLEXCAN_IsMbOccupied(base, mbIdx));
 
-    /* Disable Message Buffer Interrupt. */
+/* Disable Message Buffer Interrupt. */
 #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0)
-    FLEXCAN_DisableMbInterrupts(base, (uint64_t)1 << mbIdx);
+    uint64_t u64mask = 1;
+    FLEXCAN_DisableMbInterrupts(base, (u64mask << mbIdx));
 #else
-    FLEXCAN_DisableMbInterrupts(base, 1 << mbIdx);
+    uint32_t u32mask = 1;
+    FLEXCAN_DisableMbInterrupts(base, (u32mask << mbIdx));
 #endif
 
     /* Un-register handle. */
-    handle->mbFrameBuf[mbIdx] = 0x0;
-    handle->mbState[mbIdx] = kFLEXCAN_StateIdle;
+    handle->mbFrameBuf[mbIdx] = NULL;
+    handle->mbState[mbIdx]    = (uint8_t)kFLEXCAN_StateIdle;
 }
 
+/*!
+ * brief Aborts the interrupt driven message receive from Rx FIFO process.
+ *
+ * This function aborts the interrupt driven message receive from Rx FIFO process.
+ *
+ * param base FlexCAN peripheral base address.
+ * param handle FlexCAN handle pointer.
+ */
 void FLEXCAN_TransferAbortReceiveFifo(CAN_Type *base, flexcan_handle_t *handle)
 {
     /* Assertion. */
-    assert(handle);
+    assert(NULL != handle);
 
     /* Check if Rx FIFO is enabled. */
-    if (base->MCR & CAN_MCR_RFEN_MASK)
+    if (0U != (base->MCR & CAN_MCR_RFEN_MASK))
     {
         /* Disable Rx Message FIFO Interrupts. */
-        FLEXCAN_DisableMbInterrupts(
-            base, kFLEXCAN_RxFifoOverflowFlag | kFLEXCAN_RxFifoWarningFlag | kFLEXCAN_RxFifoFrameAvlFlag);
+        FLEXCAN_DisableMbInterrupts(base, (uint32_t)kFLEXCAN_RxFifoOverflowFlag | (uint32_t)kFLEXCAN_RxFifoWarningFlag |
+                                              (uint32_t)kFLEXCAN_RxFifoFrameAvlFlag);
 
         /* Un-register handle. */
-        handle->rxFifoFrameBuf = 0x0;
+        handle->rxFifoFrameBuf = NULL;
     }
 
-    handle->rxFifoState = kFLEXCAN_StateIdle;
+    handle->rxFifoState = (uint8_t)kFLEXCAN_StateIdle;
 }
 
+/*!
+ * brief FlexCAN IRQ handle function.
+ *
+ * This function handles the FlexCAN Error, the Message Buffer, and the Rx FIFO IRQ request.
+ *
+ * param base FlexCAN peripheral base address.
+ * param handle FlexCAN handle pointer.
+ */
 void FLEXCAN_TransferHandleIRQ(CAN_Type *base, flexcan_handle_t *handle)
 {
     /* Assertion. */
-    assert(handle);
+    assert(NULL != handle);
 
     status_t status = kStatus_FLEXCAN_UnHandled;
-    uint32_t result;
-
+    uint32_t result = 0U;
     /* Store Current FlexCAN Module Error and Status. */
-    result = base->ESR1;
+    uint32_t EsrStatus = base->ESR1;
 
     do
     {
         /* Solve FlexCAN Error and Status Interrupt. */
-        if (result & (kFLEXCAN_TxWarningIntFlag | kFLEXCAN_RxWarningIntFlag | kFLEXCAN_BusOffIntFlag |
-                      kFLEXCAN_ErrorIntFlag | kFLEXCAN_WakeUpIntFlag))
+        if (0U != (EsrStatus & ((uint32_t)kFLEXCAN_TxWarningIntFlag | (uint32_t)kFLEXCAN_RxWarningIntFlag |
+                                (uint32_t)kFLEXCAN_BusOffIntFlag | (uint32_t)kFLEXCAN_ErrorIntFlag)))
         {
             status = kStatus_FLEXCAN_ErrorStatus;
 
             /* Clear FlexCAN Error and Status Interrupt. */
-            FLEXCAN_ClearStatusFlags(base, kFLEXCAN_TxWarningIntFlag | kFLEXCAN_RxWarningIntFlag |
-                                               kFLEXCAN_BusOffIntFlag | kFLEXCAN_ErrorIntFlag | kFLEXCAN_WakeUpIntFlag);
+            FLEXCAN_ClearStatusFlags(base, (uint32_t)kFLEXCAN_TxWarningIntFlag | (uint32_t)kFLEXCAN_RxWarningIntFlag |
+                                               (uint32_t)kFLEXCAN_BusOffIntFlag | (uint32_t)kFLEXCAN_ErrorIntFlag);
+        }
+        else if (0U != (EsrStatus & (uint32_t)kFLEXCAN_WakeUpIntFlag))
+        {
+            status = kStatus_FLEXCAN_WakeUp;
+            FLEXCAN_ClearStatusFlags(base, (uint32_t)kFLEXCAN_WakeUpIntFlag);
         }
         /* Solve FlexCAN Rx FIFO & Message Buffer Interrupt. */
         else
         {
             /* For this implementation, we solve the Message with lowest MB index first. */
-            for (result = 0; result < FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base); result++)
+            for (result = 0U; result < (uint32_t)FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base); result++)
             {
-                /* Get the lowest unhandled Message Buffer */
+/* Get the lowest unhandled Message Buffer */
 #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0)
-                if ((FLEXCAN_GetMbStatusFlags(base, (uint64_t)1 << result)) && (FLEXCAN_IsMbIntEnabled(base, result)))
+                uint64_t u64flag = 1;
+                if (0U != FLEXCAN_GetMbStatusFlags(base, (u64flag << result)))
+                {
+                    if (true == FLEXCAN_IsMbIntEnabled(base, result))
 #else
-                if ((FLEXCAN_GetMbStatusFlags(base, 1 << result)) && (FLEXCAN_IsMbIntEnabled(base, result)))
-#endif
+                uint32_t u32flag = 1;
+                if (0U != FLEXCAN_GetMbStatusFlags(base, (u32flag << result)))
                 {
-                    break;
+                    if (true == FLEXCAN_IsMbIntEnabled(base, (uint8_t)result))
+#endif
+                    {
+                        break;
+                    }
                 }
             }
 
             /* Does not find Message to deal with. */
-            if (result == FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base))
+            if (result == (uint32_t)FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base))
             {
                 break;
             }
 
             /* Solve Rx FIFO interrupt. */
-            if ((kFLEXCAN_StateIdle != handle->rxFifoState) && ((1 << result) <= kFLEXCAN_RxFifoOverflowFlag))
+            if (((uint8_t)kFLEXCAN_StateIdle != handle->rxFifoState) && (result <= (uint32_t)CAN_IFLAG1_BUF7I_SHIFT))
             {
-                switch (1 << result)
+                uint32_t u32mask = 1;
+                switch (u32mask << result)
                 {
-                    case kFLEXCAN_RxFifoOverflowFlag:
+                    case (int32_t)kFLEXCAN_RxFifoOverflowFlag:
                         status = kStatus_FLEXCAN_RxFifoOverflow;
                         break;
 
-                    case kFLEXCAN_RxFifoWarningFlag:
+                    case (int32_t)kFLEXCAN_RxFifoWarningFlag:
                         status = kStatus_FLEXCAN_RxFifoWarning;
                         break;
 
-                    case kFLEXCAN_RxFifoFrameAvlFlag:
+                    case (int32_t)kFLEXCAN_RxFifoFrameAvlFlag:
                         status = FLEXCAN_ReadRxFifo(base, handle->rxFifoFrameBuf);
                         if (kStatus_Success == status)
                         {
@@ -1891,10 +2999,18 @@ void FLEXCAN_TransferHandleIRQ(CAN_Type *base, flexcan_handle_t *handle)
                 /* Get current State of Message Buffer. */
                 switch (handle->mbState[result])
                 {
-                    /* Solve Rx Data Frame. */
-                    case kFLEXCAN_StateRxData:
+                    /* Solve Rx Data Frame or Rx Remote Frame. */
+                    case (uint8_t)kFLEXCAN_StateRxData:
+                    case (uint8_t)kFLEXCAN_StateRxRemote:
 #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
-                        status = FLEXCAN_ReadFDRxMb(base, result, handle->mbFDFrameBuf[result]);
+                        if (0U != (base->MCR & CAN_MCR_FDEN_MASK))
+                        {
+                            status = FLEXCAN_ReadFDRxMb(base, (uint8_t)result, handle->mbFDFrameBuf[result]);
+                        }
+                        else
+                        {
+                            status = FLEXCAN_ReadRxMb(base, (uint8_t)result, handle->mbFrameBuf[result]);
+                        }
 #else
                         status = FLEXCAN_ReadRxMb(base, result, handle->mbFrameBuf[result]);
 #endif
@@ -1903,36 +3019,40 @@ void FLEXCAN_TransferHandleIRQ(CAN_Type *base, flexcan_handle_t *handle)
                             status = kStatus_FLEXCAN_RxIdle;
                         }
 #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
-                        FLEXCAN_TransferFDAbortReceive(base, handle, result);
-#else
-                        FLEXCAN_TransferAbortReceive(base, handle, result);
-#endif
-                        break;
-
-                    /* Solve Rx Remote Frame. */
-                    case kFLEXCAN_StateRxRemote:
-                        status = FLEXCAN_ReadRxMb(base, result, handle->mbFrameBuf[result]);
-                        if (kStatus_Success == status)
+                        if (0U != (base->MCR & CAN_MCR_FDEN_MASK))
                         {
-                            status = kStatus_FLEXCAN_RxIdle;
+                            FLEXCAN_TransferFDAbortReceive(base, handle, (uint8_t)result);
                         }
+                        else
+                        {
+                            FLEXCAN_TransferAbortReceive(base, handle, (uint8_t)result);
+                        }
+#else
                         FLEXCAN_TransferAbortReceive(base, handle, result);
+#endif
                         break;
 
                     /* Solve Tx Data Frame. */
-                    case kFLEXCAN_StateTxData:
+                    case (uint8_t)kFLEXCAN_StateTxData:
                         status = kStatus_FLEXCAN_TxIdle;
 #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
-                        FLEXCAN_TransferFDAbortSend(base, handle, result);
+                        if (0U != (base->MCR & CAN_MCR_FDEN_MASK))
+                        {
+                            FLEXCAN_TransferFDAbortSend(base, handle, (uint8_t)result);
+                        }
+                        else
+                        {
+                            FLEXCAN_TransferAbortSend(base, handle, (uint8_t)result);
+                        }
 #else
                         FLEXCAN_TransferAbortSend(base, handle, result);
 #endif
                         break;
 
                     /* Solve Tx Remote Frame. */
-                    case kFLEXCAN_StateTxRemote:
-                        handle->mbState[result] = kFLEXCAN_StateRxRemote;
-                        status = kStatus_FLEXCAN_TxSwitchToRx;
+                    case (uint8_t)kFLEXCAN_StateTxRemote:
+                        handle->mbState[result] = (uint8_t)kFLEXCAN_StateRxRemote;
+                        status                  = kStatus_FLEXCAN_TxSwitchToRx;
                         break;
 
                     default:
@@ -1941,11 +3061,13 @@ void FLEXCAN_TransferHandleIRQ(CAN_Type *base, flexcan_handle_t *handle)
                 }
             }
 
-            /* Clear resolved Message Buffer IRQ. */
+/* Clear resolved Message Buffer IRQ. */
 #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0)
-            FLEXCAN_ClearMbStatusFlags(base, (uint64_t)1 << result);
+            uint64_t u64flag = 1;
+            FLEXCAN_ClearMbStatusFlags(base, u64flag << result);
 #else
-            FLEXCAN_ClearMbStatusFlags(base, 1 << result);
+            uint32_t u32flag = 1;
+            FLEXCAN_ClearMbStatusFlags(base, u32flag << result);
 #endif
         }
 
@@ -1959,27 +3081,29 @@ void FLEXCAN_TransferHandleIRQ(CAN_Type *base, flexcan_handle_t *handle)
         status = kStatus_FLEXCAN_UnHandled;
 
         /* Store Current FlexCAN Module Error and Status. */
-        result = base->ESR1;
+        EsrStatus = base->ESR1;
     }
 #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0)
-    while ((0 != FLEXCAN_GetMbStatusFlags(base, 0xFFFFFFFFFFFFFFFFU)) ||
-           (0 != (result & (kFLEXCAN_TxWarningIntFlag | kFLEXCAN_RxWarningIntFlag | kFLEXCAN_BusOffIntFlag |
-                            kFLEXCAN_ErrorIntFlag | kFLEXCAN_WakeUpIntFlag))));
+    while ((0U != FLEXCAN_GetMbStatusFlags(base, 0xFFFFFFFFFFFFFFFFU)) ||
+           (0U != (EsrStatus & ((uint32_t)kFLEXCAN_TxWarningIntFlag | (uint32_t)kFLEXCAN_RxWarningIntFlag |
+                                (uint32_t)kFLEXCAN_BusOffIntFlag | (uint32_t)kFLEXCAN_ErrorIntFlag |
+                                (uint32_t)kFLEXCAN_WakeUpIntFlag))));
 #else
-    while ((0 != FLEXCAN_GetMbStatusFlags(base, 0xFFFFFFFFU)) ||
-           (0 != (result & (kFLEXCAN_TxWarningIntFlag | kFLEXCAN_RxWarningIntFlag | kFLEXCAN_BusOffIntFlag |
-                            kFLEXCAN_ErrorIntFlag | kFLEXCAN_WakeUpIntFlag))));
+    while ((0U != FLEXCAN_GetMbStatusFlags(base, 0xFFFFFFFFU)) ||
+           (0U != (EsrStatus & ((uint32_t)kFLEXCAN_TxWarningIntFlag | (uint32_t)kFLEXCAN_RxWarningIntFlag |
+                                (uint32_t)kFLEXCAN_BusOffIntFlag | (uint32_t)kFLEXCAN_ErrorIntFlag |
+                                (uint32_t)kFLEXCAN_WakeUpIntFlag))));
 #endif
 }
 
 #if defined(CAN0)
 void CAN0_DriverIRQHandler(void)
 {
-    assert(s_flexcanHandle[0]);
+    assert(NULL != s_flexcanHandle[0]);
 
     s_flexcanIsr(CAN0, s_flexcanHandle[0]);
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-      exception return operation might vector to incorrect interrupt */
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
 #endif
@@ -1989,11 +3113,11 @@ void CAN0_DriverIRQHandler(void)
 #if defined(CAN1)
 void CAN1_DriverIRQHandler(void)
 {
-    assert(s_flexcanHandle[1]);
+    assert(NULL != s_flexcanHandle[1]);
 
     s_flexcanIsr(CAN1, s_flexcanHandle[1]);
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-      exception return operation might vector to incorrect interrupt */
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
 #endif
@@ -2003,11 +3127,11 @@ void CAN1_DriverIRQHandler(void)
 #if defined(CAN2)
 void CAN2_DriverIRQHandler(void)
 {
-    assert(s_flexcanHandle[2]);
+    assert(NULL != s_flexcanHandle[2]);
 
     s_flexcanIsr(CAN2, s_flexcanHandle[2]);
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-      exception return operation might vector to incorrect interrupt */
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
 #endif
@@ -2017,11 +3141,11 @@ void CAN2_DriverIRQHandler(void)
 #if defined(CAN3)
 void CAN3_DriverIRQHandler(void)
 {
-    assert(s_flexcanHandle[3]);
+    assert(NULL != s_flexcanHandle[3]);
 
     s_flexcanIsr(CAN3, s_flexcanHandle[3]);
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-      exception return operation might vector to incorrect interrupt */
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
 #endif
@@ -2031,11 +3155,11 @@ void CAN3_DriverIRQHandler(void)
 #if defined(CAN4)
 void CAN4_DriverIRQHandler(void)
 {
-    assert(s_flexcanHandle[4]);
+    assert(NULL != s_flexcanHandle[4]);
 
     s_flexcanIsr(CAN4, s_flexcanHandle[4]);
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-      exception return operation might vector to incorrect interrupt */
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
 #endif
@@ -2048,8 +3172,8 @@ void DMA_FLEXCAN0_INT_DriverIRQHandler(void)
     assert(s_flexcanHandle[FLEXCAN_GetInstance(DMA__CAN0)]);
 
     s_flexcanIsr(DMA__CAN0, s_flexcanHandle[FLEXCAN_GetInstance(DMA__CAN0)]);
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-      exception return operation might vector to incorrect interrupt */
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
 #endif
@@ -2062,8 +3186,8 @@ void DMA_FLEXCAN1_INT_DriverIRQHandler(void)
     assert(s_flexcanHandle[FLEXCAN_GetInstance(DMA__CAN1)]);
 
     s_flexcanIsr(DMA__CAN1, s_flexcanHandle[FLEXCAN_GetInstance(DMA__CAN1)]);
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-      exception return operation might vector to incorrect interrupt */
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
 #endif
@@ -2076,8 +3200,8 @@ void DMA_FLEXCAN2_INT_DriverIRQHandler(void)
     assert(s_flexcanHandle[FLEXCAN_GetInstance(DMA__CAN2)]);
 
     s_flexcanIsr(DMA__CAN2, s_flexcanHandle[FLEXCAN_GetInstance(DMA__CAN2)]);
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-      exception return operation might vector to incorrect interrupt */
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
 #endif
@@ -2090,8 +3214,8 @@ void ADMA_FLEXCAN0_INT_DriverIRQHandler(void)
     assert(s_flexcanHandle[FLEXCAN_GetInstance(ADMA__CAN0)]);
 
     s_flexcanIsr(ADMA__CAN0, s_flexcanHandle[FLEXCAN_GetInstance(ADMA__CAN0)]);
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-      exception return operation might vector to incorrect interrupt */
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
 #endif
@@ -2104,8 +3228,8 @@ void ADMA_FLEXCAN1_INT_DriverIRQHandler(void)
     assert(s_flexcanHandle[FLEXCAN_GetInstance(ADMA__CAN1)]);
 
     s_flexcanIsr(ADMA__CAN1, s_flexcanHandle[FLEXCAN_GetInstance(ADMA__CAN1)]);
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-      exception return operation might vector to incorrect interrupt */
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
 #endif
@@ -2118,8 +3242,8 @@ void ADMA_FLEXCAN2_INT_DriverIRQHandler(void)
     assert(s_flexcanHandle[FLEXCAN_GetInstance(ADMA__CAN2)]);
 
     s_flexcanIsr(ADMA__CAN2, s_flexcanHandle[FLEXCAN_GetInstance(ADMA__CAN2)]);
-    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-      exception return operation might vector to incorrect interrupt */
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
     __DSB();
 #endif
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexcan.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexcan.h
index 78ec2c42935..9fe1b439969 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexcan.h
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexcan.h
@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
+ * Copyright 2016-2019 NXP
  * All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- * that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 #ifndef _FSL_FLEXCAN_H_
 #define _FSL_FLEXCAN_H_
@@ -47,10 +21,15 @@
 
 /*! @name Driver version */
 /*@{*/
-/*! @brief FlexCAN driver version 2.2.0. */
-#define FSL_FLEXCAN_DRIVER_VERSION (MAKE_VERSION(2, 2, 0))
+/*! @brief FlexCAN driver version 2.4.0. */
+#define FSL_FLEXCAN_DRIVER_VERSION (MAKE_VERSION(2, 4, 0))
 /*@}*/
 
+#if !(defined(FLEXCAN_WAIT_TIMEOUT) && FLEXCAN_WAIT_TIMEOUT)
+/* Define to 1000 means keep waiting 1000 times until the flag is assert/deassert.  */
+#define FLEXCAN_WAIT_TIMEOUT (1000U)
+#endif
+
 /*! @brief FlexCAN Frame ID helper macro. */
 #define FLEXCAN_ID_STD(id) \
     (((uint32_t)(((uint32_t)(id)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK) /*!< Standard Frame ID helper macro. */
@@ -125,10 +104,9 @@
 #define FLEXCAN_RX_FIFO_STD_FILTER_TYPE_C_MID_LOW(id) \
     FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_MID_LOW(          \
         id) /*!< Standard Rx FIFO Filter helper macro Type C mid-lower part helper macro. */
-#define FLEXCAN_RX_FIFO_STD_FILTER_TYPE_C_LOW(id)                                               \
-    FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_LOW(                                                        \
-        id) /*!< Standard Rx FIFO Filter helper macro Type C lower part helper macro. \ \ \ \ \ \
-               */
+#define FLEXCAN_RX_FIFO_STD_FILTER_TYPE_C_LOW(id) \
+    FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_LOW(          \
+        id) /*!< Standard Rx FIFO Filter helper macro Type C lower part helper macro.  */
 #define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_A(id, rtr, ide) \
     FLEXCAN_RX_FIFO_EXT_MASK_TYPE_A(id, rtr, ide) /*!< Extend Rx FIFO Filter helper macro Type A helper macro. */
 #define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_B_HIGH(id, rtr, ide) \
@@ -137,10 +115,9 @@
 #define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_B_LOW(id, rtr, ide) \
     FLEXCAN_RX_FIFO_EXT_MASK_TYPE_B_LOW(                    \
         id, rtr, ide) /*!< Extend Rx FIFO Filter helper macro Type B lower part helper macro. */
-#define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_C_HIGH(id)                                            \
-    FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_HIGH(                                                     \
-        id) /*!< Extend Rx FIFO Filter helper macro Type C upper part helper macro. \ \ \ \ \ \
-               */
+#define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_C_HIGH(id) \
+    FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_HIGH(          \
+        id) /*!< Extend Rx FIFO Filter helper macro Type C upper part helper macro.           */
 #define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_C_MID_HIGH(id) \
     FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_MID_HIGH(          \
         id) /*!< Extend Rx FIFO Filter helper macro Type C mid-upper part helper macro. */
@@ -153,43 +130,49 @@
 /*! @brief FlexCAN transfer status. */
 enum _flexcan_status
 {
-    kStatus_FLEXCAN_TxBusy = MAKE_STATUS(kStatusGroup_FLEXCAN, 0), /*!< Tx Message Buffer is Busy. */
-    kStatus_FLEXCAN_TxIdle = MAKE_STATUS(kStatusGroup_FLEXCAN, 1), /*!< Tx Message Buffer is Idle. */
+    kStatus_FLEXCAN_TxBusy       = MAKE_STATUS(kStatusGroup_FLEXCAN, 0), /*!< Tx Message Buffer is Busy. */
+    kStatus_FLEXCAN_TxIdle       = MAKE_STATUS(kStatusGroup_FLEXCAN, 1), /*!< Tx Message Buffer is Idle. */
     kStatus_FLEXCAN_TxSwitchToRx = MAKE_STATUS(
         kStatusGroup_FLEXCAN, 2), /*!< Remote Message is send out and Message buffer changed to Receive one. */
-    kStatus_FLEXCAN_RxBusy = MAKE_STATUS(kStatusGroup_FLEXCAN, 3),         /*!< Rx Message Buffer is Busy. */
-    kStatus_FLEXCAN_RxIdle = MAKE_STATUS(kStatusGroup_FLEXCAN, 4),         /*!< Rx Message Buffer is Idle. */
-    kStatus_FLEXCAN_RxOverflow = MAKE_STATUS(kStatusGroup_FLEXCAN, 5),     /*!< Rx Message Buffer is Overflowed. */
-    kStatus_FLEXCAN_RxFifoBusy = MAKE_STATUS(kStatusGroup_FLEXCAN, 6),     /*!< Rx Message FIFO is Busy. */
-    kStatus_FLEXCAN_RxFifoIdle = MAKE_STATUS(kStatusGroup_FLEXCAN, 7),     /*!< Rx Message FIFO is Idle. */
+    kStatus_FLEXCAN_RxBusy         = MAKE_STATUS(kStatusGroup_FLEXCAN, 3), /*!< Rx Message Buffer is Busy. */
+    kStatus_FLEXCAN_RxIdle         = MAKE_STATUS(kStatusGroup_FLEXCAN, 4), /*!< Rx Message Buffer is Idle. */
+    kStatus_FLEXCAN_RxOverflow     = MAKE_STATUS(kStatusGroup_FLEXCAN, 5), /*!< Rx Message Buffer is Overflowed. */
+    kStatus_FLEXCAN_RxFifoBusy     = MAKE_STATUS(kStatusGroup_FLEXCAN, 6), /*!< Rx Message FIFO is Busy. */
+    kStatus_FLEXCAN_RxFifoIdle     = MAKE_STATUS(kStatusGroup_FLEXCAN, 7), /*!< Rx Message FIFO is Idle. */
     kStatus_FLEXCAN_RxFifoOverflow = MAKE_STATUS(kStatusGroup_FLEXCAN, 8), /*!< Rx Message FIFO is overflowed. */
-    kStatus_FLEXCAN_RxFifoWarning = MAKE_STATUS(kStatusGroup_FLEXCAN, 9),  /*!< Rx Message FIFO is almost overflowed. */
-    kStatus_FLEXCAN_ErrorStatus = MAKE_STATUS(kStatusGroup_FLEXCAN, 10),   /*!< FlexCAN Module Error and Status. */
-    kStatus_FLEXCAN_UnHandled = MAKE_STATUS(kStatusGroup_FLEXCAN, 11),     /*!< UnHadled Interrupt asserted. */
+    kStatus_FLEXCAN_RxFifoWarning  = MAKE_STATUS(kStatusGroup_FLEXCAN, 9), /*!< Rx Message FIFO is almost overflowed. */
+    kStatus_FLEXCAN_ErrorStatus    = MAKE_STATUS(kStatusGroup_FLEXCAN, 10), /*!< FlexCAN Module Error and Status. */
+    kStatus_FLEXCAN_WakeUp         = MAKE_STATUS(kStatusGroup_FLEXCAN, 11), /*!< FlexCAN is waken up from STOP mode. */
+    kStatus_FLEXCAN_UnHandled      = MAKE_STATUS(kStatusGroup_FLEXCAN, 12), /*!< UnHadled Interrupt asserted. */
 };
 
 /*! @brief FlexCAN frame format. */
 typedef enum _flexcan_frame_format
 {
     kFLEXCAN_FrameFormatStandard = 0x0U, /*!< Standard frame format attribute. */
-    kFLEXCAN_FrameFormatExtend = 0x1U,   /*!< Extend frame format attribute. */
+    kFLEXCAN_FrameFormatExtend   = 0x1U, /*!< Extend frame format attribute. */
 } flexcan_frame_format_t;
 
 /*! @brief FlexCAN frame type. */
 typedef enum _flexcan_frame_type
 {
-    kFLEXCAN_FrameTypeData = 0x0U,   /*!< Data frame type attribute. */
+    kFLEXCAN_FrameTypeData   = 0x0U, /*!< Data frame type attribute. */
     kFLEXCAN_FrameTypeRemote = 0x1U, /*!< Remote frame type attribute. */
 } flexcan_frame_type_t;
 
-#if (!defined(FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE)) || !FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE
 /*! @brief FlexCAN clock source. */
 typedef enum _flexcan_clock_source
 {
-    kFLEXCAN_ClkSrcOsc = 0x0U,  /*!< FlexCAN Protocol Engine clock from Oscillator. */
+    kFLEXCAN_ClkSrcOsc  = 0x0U, /*!< FlexCAN Protocol Engine clock from Oscillator. */
     kFLEXCAN_ClkSrcPeri = 0x1U, /*!< FlexCAN Protocol Engine clock from Peripheral Clock. */
 } flexcan_clock_source_t;
-#endif /* FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE */
+
+/*! @brief FlexCAN wake up source. */
+typedef enum _flexcan_wake_up_source
+{
+    kFLEXCAN_WakeupSrcUnfiltered = 0x0U, /*!< FlexCAN uses unfiltered Rx input to detect edge. */
+    kFLEXCAN_WakeupSrcFiltered   = 0x1U, /*!< FlexCAN uses filtered Rx input to detect edge. */
+} flexcan_wake_up_source_t;
 
 /*! @brief FlexCAN Rx Fifo Filter type. */
 typedef enum _flexcan_rx_fifo_filter_type
@@ -208,7 +191,7 @@ typedef enum _flexcan_rx_fifo_filter_type
  */
 typedef enum _flexcan_mb_size
 {
-    kFLEXCAN_8BperMB = 0x0U,  /*!< Selects 8 bytes per Message Buffer. */
+    kFLEXCAN_8BperMB  = 0x0U, /*!< Selects 8 bytes per Message Buffer. */
     kFLEXCAN_16BperMB = 0x1U, /*!< Selects 16 bytes per Message Buffer. */
     kFLEXCAN_32BperMB = 0x2U, /*!< Selects 32 bytes per Message Buffer. */
     kFLEXCAN_64BperMB = 0x3U, /*!< Selects 64 bytes per Message Buffer. */
@@ -224,7 +207,7 @@ typedef enum _flexcan_mb_size
  */
 typedef enum _flexcan_rx_fifo_priority
 {
-    kFLEXCAN_RxFifoPrioLow = 0x0U,  /*!< Matching process start from Rx Message Buffer first*/
+    kFLEXCAN_RxFifoPrioLow  = 0x0U, /*!< Matching process start from Rx Message Buffer first*/
     kFLEXCAN_RxFifoPrioHigh = 0x1U, /*!< Matching process start from Rx FIFO first*/
 } flexcan_rx_fifo_priority_t;
 
@@ -236,11 +219,11 @@ typedef enum _flexcan_rx_fifo_priority
  */
 enum _flexcan_interrupt_enable
 {
-    kFLEXCAN_BusOffInterruptEnable = CAN_CTRL1_BOFFMSK_MASK,    /*!< Bus Off interrupt. */
-    kFLEXCAN_ErrorInterruptEnable = CAN_CTRL1_ERRMSK_MASK,      /*!< Error interrupt. */
+    kFLEXCAN_BusOffInterruptEnable    = CAN_CTRL1_BOFFMSK_MASK, /*!< Bus Off interrupt. */
+    kFLEXCAN_ErrorInterruptEnable     = CAN_CTRL1_ERRMSK_MASK,  /*!< Error interrupt. */
     kFLEXCAN_RxWarningInterruptEnable = CAN_CTRL1_RWRNMSK_MASK, /*!< Rx Warning interrupt. */
     kFLEXCAN_TxWarningInterruptEnable = CAN_CTRL1_TWRNMSK_MASK, /*!< Tx Warning interrupt. */
-    kFLEXCAN_WakeUpInterruptEnable = CAN_MCR_WAKMSK_MASK,       /*!< Wake Up interrupt. */
+    kFLEXCAN_WakeUpInterruptEnable    = CAN_MCR_WAKMSK_MASK,    /*!< Wake Up interrupt. */
 };
 
 /*!
@@ -254,28 +237,28 @@ enum _flexcan_interrupt_enable
 enum _flexcan_flags
 {
 #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
-    kFLEXCAN_FDErrorIntFlag = CAN_ESR1_ERRINT_FAST_MASK,    /*!< Error Overrun Status. */
+    kFLEXCAN_FDErrorIntFlag    = CAN_ESR1_ERRINT_FAST_MASK, /*!< Error Overrun Status. */
     kFLEXCAN_BusoffDoneIntFlag = CAN_ESR1_BOFFDONEINT_MASK, /*!< Error Overrun Status. */
 #endif
-    kFLEXCAN_SynchFlag = CAN_ESR1_SYNCH_MASK,              /*!< CAN Synchronization Status. */
-    kFLEXCAN_TxWarningIntFlag = CAN_ESR1_TWRNINT_MASK,     /*!< Tx Warning Interrupt Flag. */
-    kFLEXCAN_RxWarningIntFlag = CAN_ESR1_RWRNINT_MASK,     /*!< Rx Warning Interrupt Flag. */
-    kFLEXCAN_TxErrorWarningFlag = CAN_ESR1_TXWRN_MASK,     /*!< Tx Error Warning Status. */
-    kFLEXCAN_RxErrorWarningFlag = CAN_ESR1_RXWRN_MASK,     /*!< Rx Error Warning Status. */
-    kFLEXCAN_IdleFlag = CAN_ESR1_IDLE_MASK,                /*!< CAN IDLE Status Flag. */
+    kFLEXCAN_SynchFlag            = CAN_ESR1_SYNCH_MASK,   /*!< CAN Synchronization Status. */
+    kFLEXCAN_TxWarningIntFlag     = CAN_ESR1_TWRNINT_MASK, /*!< Tx Warning Interrupt Flag. */
+    kFLEXCAN_RxWarningIntFlag     = CAN_ESR1_RWRNINT_MASK, /*!< Rx Warning Interrupt Flag. */
+    kFLEXCAN_TxErrorWarningFlag   = CAN_ESR1_TXWRN_MASK,   /*!< Tx Error Warning Status. */
+    kFLEXCAN_RxErrorWarningFlag   = CAN_ESR1_RXWRN_MASK,   /*!< Rx Error Warning Status. */
+    kFLEXCAN_IdleFlag             = CAN_ESR1_IDLE_MASK,    /*!< CAN IDLE Status Flag. */
     kFLEXCAN_FaultConfinementFlag = CAN_ESR1_FLTCONF_MASK, /*!< Fault Confinement State Flag. */
-    kFLEXCAN_TransmittingFlag = CAN_ESR1_TX_MASK,          /*!< FlexCAN In Transmission Status. */
-    kFLEXCAN_ReceivingFlag = CAN_ESR1_RX_MASK,             /*!< FlexCAN In Reception Status. */
-    kFLEXCAN_BusOffIntFlag = CAN_ESR1_BOFFINT_MASK,        /*!< Bus Off Interrupt Flag. */
-    kFLEXCAN_ErrorIntFlag = CAN_ESR1_ERRINT_MASK,          /*!< Error Interrupt Flag. */
-    kFLEXCAN_WakeUpIntFlag = CAN_ESR1_WAKINT_MASK,         /*!< Wake-Up Interrupt Flag. */
-    kFLEXCAN_ErrorFlag =                                   /*!< All FlexCAN Error Status. */
+    kFLEXCAN_TransmittingFlag     = CAN_ESR1_TX_MASK,      /*!< FlexCAN In Transmission Status. */
+    kFLEXCAN_ReceivingFlag        = CAN_ESR1_RX_MASK,      /*!< FlexCAN In Reception Status. */
+    kFLEXCAN_BusOffIntFlag        = CAN_ESR1_BOFFINT_MASK, /*!< Bus Off Interrupt Flag. */
+    kFLEXCAN_ErrorIntFlag         = CAN_ESR1_ERRINT_MASK,  /*!< Error Interrupt Flag. */
+    kFLEXCAN_WakeUpIntFlag        = CAN_ESR1_WAKINT_MASK,  /*!< Wake-Up Interrupt Flag. */
+    kFLEXCAN_ErrorFlag            = (int)(                 /*!< All FlexCAN Error Status. */
 #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
-    CAN_ESR1_STFERR_FAST_MASK | CAN_ESR1_FRMERR_FAST_MASK | CAN_ESR1_CRCERR_FAST_MASK | CAN_ESR1_BIT0ERR_FAST_MASK |
-    CAN_ESR1_BIT1ERR_FAST_MASK | CAN_ESR1_ERROVR_MASK |
+                               CAN_ESR1_STFERR_FAST_MASK | CAN_ESR1_FRMERR_FAST_MASK | CAN_ESR1_CRCERR_FAST_MASK |
+                               CAN_ESR1_BIT0ERR_FAST_MASK | CAN_ESR1_BIT1ERR_FAST_MASK | CAN_ESR1_ERROVR_MASK |
 #endif
-    CAN_ESR1_BIT1ERR_MASK | CAN_ESR1_BIT0ERR_MASK | CAN_ESR1_ACKERR_MASK | CAN_ESR1_CRCERR_MASK | CAN_ESR1_FRMERR_MASK |
-    CAN_ESR1_STFERR_MASK,
+                               CAN_ESR1_BIT1ERR_MASK | CAN_ESR1_BIT0ERR_MASK | CAN_ESR1_ACKERR_MASK |
+                               CAN_ESR1_CRCERR_MASK | CAN_ESR1_FRMERR_MASK | CAN_ESR1_STFERR_MASK),
 };
 
 /*!
@@ -288,19 +271,19 @@ enum _flexcan_flags
 enum _flexcan_error_flags
 {
 #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
-    kFLEXCAN_FDStuffingError = CAN_ESR1_STFERR_FAST_MASK, /*!< Stuffing Error. */
-    kFLEXCAN_FDFormError = CAN_ESR1_FRMERR_FAST_MASK,     /*!< Form Error. */
-    kFLEXCAN_FDCrcError = CAN_ESR1_CRCERR_FAST_MASK,      /*!< Cyclic Redundancy Check Error. */
-    kFLEXCAN_FDBit0Error = CAN_ESR1_BIT0ERR_FAST_MASK,    /*!< Unable to send dominant bit. */
-    kFLEXCAN_FDBit1Error = CAN_ESR1_BIT1ERR_FAST_MASK,    /*!< Unable to send recessive bit. */
-    kFLEXCAN_OverrunError = CAN_ESR1_ERROVR_MASK,         /*!< Error Overrun Status. */
+    kFLEXCAN_FDStuffingError = CAN_ESR1_STFERR_FAST_MASK,       /*!< Stuffing Error. */
+    kFLEXCAN_FDFormError     = CAN_ESR1_FRMERR_FAST_MASK,       /*!< Form Error. */
+    kFLEXCAN_FDCrcError      = CAN_ESR1_CRCERR_FAST_MASK,       /*!< Cyclic Redundancy Check Error. */
+    kFLEXCAN_FDBit0Error     = CAN_ESR1_BIT0ERR_FAST_MASK,      /*!< Unable to send dominant bit. */
+    kFLEXCAN_FDBit1Error     = (int)CAN_ESR1_BIT1ERR_FAST_MASK, /*!< Unable to send recessive bit. */
+    kFLEXCAN_OverrunError    = CAN_ESR1_ERROVR_MASK,            /*!< Error Overrun Status. */
 #endif
-    kFLEXCAN_StuffingError = CAN_ESR1_STFERR_MASK, /*!< Stuffing Error. */
-    kFLEXCAN_FormError = CAN_ESR1_FRMERR_MASK,     /*!< Form Error. */
-    kFLEXCAN_CrcError = CAN_ESR1_CRCERR_MASK,      /*!< Cyclic Redundancy Check Error. */
-    kFLEXCAN_AckError = CAN_ESR1_ACKERR_MASK,      /*!< Received no ACK on transmission. */
-    kFLEXCAN_Bit0Error = CAN_ESR1_BIT0ERR_MASK,    /*!< Unable to send dominant bit. */
-    kFLEXCAN_Bit1Error = CAN_ESR1_BIT1ERR_MASK,    /*!< Unable to send recessive bit. */
+    kFLEXCAN_StuffingError = CAN_ESR1_STFERR_MASK,  /*!< Stuffing Error. */
+    kFLEXCAN_FormError     = CAN_ESR1_FRMERR_MASK,  /*!< Form Error. */
+    kFLEXCAN_CrcError      = CAN_ESR1_CRCERR_MASK,  /*!< Cyclic Redundancy Check Error. */
+    kFLEXCAN_AckError      = CAN_ESR1_ACKERR_MASK,  /*!< Received no ACK on transmission. */
+    kFLEXCAN_Bit0Error     = CAN_ESR1_BIT0ERR_MASK, /*!< Unable to send dominant bit. */
+    kFLEXCAN_Bit1Error     = CAN_ESR1_BIT1ERR_MASK, /*!< Unable to send recessive bit. */
 };
 
 /*!
@@ -314,7 +297,7 @@ enum _flexcan_error_flags
 enum _flexcan_rx_fifo_flags
 {
     kFLEXCAN_RxFifoOverflowFlag = CAN_IFLAG1_BUF7I_MASK, /*!< Rx FIFO overflow flag. */
-    kFLEXCAN_RxFifoWarningFlag = CAN_IFLAG1_BUF6I_MASK,  /*!< Rx FIFO almost full flag. */
+    kFLEXCAN_RxFifoWarningFlag  = CAN_IFLAG1_BUF6I_MASK, /*!< Rx FIFO almost full flag. */
     kFLEXCAN_RxFifoFrameAvlFlag = CAN_IFLAG1_BUF5I_MASK, /*!< Frames available in Rx FIFO flag. */
 };
 
@@ -388,6 +371,8 @@ typedef struct _flexcan_fd_frame
         {
             uint32_t dataWord[16]; /*!< CAN FD Frame payload, 16 double word maximum. */
         };
+        /* Note: the maximum databyte* below is actually 64, user can add them if needed,
+           or just use dataWord[*] instead. */
         struct
         {
             uint8_t dataByte3; /*!< CAN Frame payload byte3. */
@@ -427,13 +412,13 @@ typedef struct _flexcan_config
 #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
     uint32_t baudRateFD; /*!< FlexCAN FD baud rate in bps. */
 #endif
-#if (!defined(FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE)) || !FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE
-    flexcan_clock_source_t clkSrc; /*!< Clock source for FlexCAN Protocol Engine. */
-#endif                             /* FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE */
-    uint8_t maxMbNum;              /*!< The maximum number of Message Buffers used by user. */
-    bool enableLoopBack;           /*!< Enable or Disable Loop Back Self Test Mode. */
-    bool enableSelfWakeup;         /*!< Enable or Disable Self Wakeup Mode. */
-    bool enableIndividMask;        /*!< Enable or Disable Rx Individual Mask. */
+    flexcan_clock_source_t clkSrc;      /*!< Clock source for FlexCAN Protocol Engine. */
+    flexcan_wake_up_source_t wakeupSrc; /*!< Wake up source selection. */
+    uint8_t maxMbNum;                   /*!< The maximum number of Message Buffers used by user. */
+    bool enableLoopBack;                /*!< Enable or Disable Loop Back Self Test Mode. */
+    bool enableTimerSync;               /*!< Enable or Disable Timer Synchronization. */
+    bool enableSelfWakeup;              /*!< Enable or Disable Self Wakeup Mode. */
+    bool enableIndividMask;             /*!< Enable or Disable Rx Individual Mask. */
 #if (defined(FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT) && FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT)
     bool enableDoze; /*!< Enable or Disable Doze Mode. */
 #endif
@@ -533,6 +518,18 @@ extern "C" {
  * @return FlexCAN instance.
  */
 uint32_t FLEXCAN_GetInstance(CAN_Type *base);
+/*!
+ * @brief Calculates the improved timing values by specific baudrates for classical CAN
+ *
+ * @param baudRate  The classical CAN speed in bps defined by user
+ * @param sourceClock_Hz The Source clock data speed in bps. Zero to disable baudrate switching
+ * @param pconfig Pointer to the FlexCAN timing configuration structure.
+ *
+ * @return TRUE if timing configuration found, FALSE if failed to find configuration
+ */
+bool FLEXCAN_CalculateImprovedTimingValues(uint32_t baudRate,
+                                           uint32_t sourceClock_Hz,
+                                           flexcan_timing_config_t *pconfig);
 
 /*!
  * @brief Initializes a FlexCAN instance.
@@ -559,6 +556,51 @@ uint32_t FLEXCAN_GetInstance(CAN_Type *base);
  */
 void FLEXCAN_Init(CAN_Type *base, const flexcan_config_t *config, uint32_t sourceClock_Hz);
 
+#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
+/*!
+ * @brief Calculates the improved timing values by specific baudrates for CANFD
+ *
+ * @param baudRate  The CANFD bus control speed in bps defined by user
+ * @param baudRateFD  The CANFD bus data speed in bps defined by user
+ * @param sourceClock_Hz The Source clock data speed in bps. Zero to disable baudrate switching
+ * @param pconfig Pointer to the FlexCAN timing configuration structure.
+ *
+ * @return TRUE if timing configuration found, FALSE if failed to find configuration
+ */
+bool FLEXCAN_FDCalculateImprovedTimingValues(uint32_t baudRate,
+                                             uint32_t baudRateFD,
+                                             uint32_t sourceClock_Hz,
+                                             flexcan_timing_config_t *pconfig);
+/*!
+ * @brief Initializes a FlexCAN instance.
+ *
+ * This function initializes the FlexCAN module with user-defined settings.
+ * This example shows how to set up the flexcan_config_t parameters and how
+ * to call the FLEXCAN_FDInit function by passing in these parameters.
+ *  @code
+ *   flexcan_config_t flexcanConfig;
+ *   flexcanConfig.clkSrc            = kFLEXCAN_ClkSrcOsc;
+ *   flexcanConfig.baudRate          = 1000000U;
+ *   flexcanConfig.baudRateFD        = 2000000U;
+ *   flexcanConfig.maxMbNum          = 16;
+ *   flexcanConfig.enableLoopBack    = false;
+ *   flexcanConfig.enableSelfWakeup  = false;
+ *   flexcanConfig.enableIndividMask = false;
+ *   flexcanConfig.enableDoze        = false;
+ *   flexcanConfig.timingConfig      = timingConfig;
+ *   FLEXCAN_FDInit(CAN0, &flexcanConfig, 8000000UL, kFLEXCAN_16BperMB, false);
+ *   @endcode
+ *
+ * @param base FlexCAN peripheral base address.
+ * @param config Pointer to the user-defined configuration structure.
+ * @param sourceClock_Hz FlexCAN Protocol Engine clock source frequency in Hz.
+ * @param dataSize FlexCAN FD frame payload size.
+ * @param brs If bitrate switch is enabled in FD mode.
+ */
+void FLEXCAN_FDInit(
+    CAN_Type *base, const flexcan_config_t *config, uint32_t sourceClock_Hz, flexcan_mb_size_t dataSize, bool brs);
+#endif
+
 /*!
  * @brief De-initializes a FlexCAN instance.
  *
@@ -574,8 +616,9 @@ void FLEXCAN_Deinit(CAN_Type *base);
  *
  * This function initializes the FlexCAN configuration structure to default values. The default
  * values are as follows.
- *   flexcanConfig->clkSrc            = KFLEXCAN_ClkSrcOsc;
+ *   flexcanConfig->clkSrc            = kFLEXCAN_ClkSrcOsc;
  *   flexcanConfig->baudRate          = 1000000U;
+ *   flexcanConfig->baudRateFD        = 2000000U;
  *   flexcanConfig->maxMbNum          = 16;
  *   flexcanConfig->enableLoopBack    = false;
  *   flexcanConfig->enableSelfWakeup  = false;
@@ -587,19 +630,6 @@ void FLEXCAN_Deinit(CAN_Type *base);
  */
 void FLEXCAN_GetDefaultConfig(flexcan_config_t *config);
 
-#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
-/*!
- * @brief Sets the FlexCAN FD protocol characteristic.
- *
- * This function gives user settings to CAN FD characteristic.
- *
- * @param base FlexCAN peripheral base address.
- * @param dataSize Quantity of data bytes allocated for the message payload.
- * @param brs Enable/Disable the effect of bit rate switch during data phase of Tx messages.
- */
-void FLEXCAN_FDEnable(CAN_Type *base, flexcan_mb_size_t dataSize, bool brs);
-#endif
-
 /* @} */
 
 /*!
@@ -802,12 +832,12 @@ static inline void FLEXCAN_ClearStatusFlags(CAN_Type *base, uint32_t mask)
  */
 static inline void FLEXCAN_GetBusErrCount(CAN_Type *base, uint8_t *txErrBuf, uint8_t *rxErrBuf)
 {
-    if (txErrBuf)
+    if (NULL != txErrBuf)
     {
         *txErrBuf = (uint8_t)((base->ECR & CAN_ECR_TXERRCNT_MASK) >> CAN_ECR_TXERRCNT_SHIFT);
     }
 
-    if (rxErrBuf)
+    if (NULL != rxErrBuf)
     {
         *rxErrBuf = (uint8_t)((base->ECR & CAN_ECR_RXERRCNT_MASK) >> CAN_ECR_RXERRCNT_SHIFT);
     }
@@ -876,7 +906,7 @@ static inline void FLEXCAN_ClearMbStatusFlags(CAN_Type *base, uint32_t mask)
 static inline void FLEXCAN_EnableInterrupts(CAN_Type *base, uint32_t mask)
 {
     /* Solve Wake Up Interrupt. */
-    if (mask & kFLEXCAN_WakeUpInterruptEnable)
+    if ((uint32_t)kFLEXCAN_WakeUpInterruptEnable == (mask & (uint32_t)kFLEXCAN_WakeUpInterruptEnable))
     {
         base->MCR |= CAN_MCR_WAKMSK_MASK;
     }
@@ -897,7 +927,7 @@ static inline void FLEXCAN_EnableInterrupts(CAN_Type *base, uint32_t mask)
 static inline void FLEXCAN_DisableInterrupts(CAN_Type *base, uint32_t mask)
 {
     /* Solve Wake Up Interrupt. */
-    if (mask & kFLEXCAN_WakeUpInterruptEnable)
+    if ((uint32_t)kFLEXCAN_WakeUpInterruptEnable == (mask & (uint32_t)kFLEXCAN_WakeUpInterruptEnable))
     {
         base->MCR &= ~CAN_MCR_WAKMSK_MASK;
     }
@@ -1004,7 +1034,7 @@ static inline void FLEXCAN_Enable(CAN_Type *base, bool enable)
         base->MCR &= ~CAN_MCR_MDIS_MASK;
 
         /* Wait FlexCAN exit from low-power mode. */
-        while (base->MCR & CAN_MCR_LPMACK_MASK)
+        while (0U != (base->MCR & CAN_MCR_LPMACK_MASK))
         {
         }
     }
@@ -1013,7 +1043,7 @@ static inline void FLEXCAN_Enable(CAN_Type *base, bool enable)
         base->MCR |= CAN_MCR_MDIS_MASK;
 
         /* Wait FlexCAN enter low-power mode. */
-        while (!(base->MCR & CAN_MCR_LPMACK_MASK))
+        while (0U == (base->MCR & CAN_MCR_LPMACK_MASK))
         {
         }
     }
@@ -1171,6 +1201,17 @@ status_t FLEXCAN_TransferFDReceiveNonBlocking(CAN_Type *base, flexcan_handle_t *
  * @param mbIdx The FlexCAN FD Message Buffer index.
  */
 void FLEXCAN_TransferFDAbortSend(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx);
+
+/*!
+ * @brief Aborts the interrupt driven message receive process.
+ *
+ * This function aborts the interrupt driven message receive process.
+ *
+ * @param base FlexCAN peripheral base address.
+ * @param handle FlexCAN handle pointer.
+ * @param mbIdx The FlexCAN FD Message Buffer index.
+ */
+void FLEXCAN_TransferFDAbortReceive(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx);
 #endif
 
 /*!
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio.c
index e6c256c3eea..9cb5046e050 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio.c
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio.c
@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
  * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
  *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include "fsl_flexio.h"
@@ -43,7 +17,6 @@
 #define FSL_COMPONENT_ID "platform.drivers.flexio"
 #endif
 
-
 /*< @brief user configurable flexio handle count. */
 #define FLEXIO_HANDLE_COUNT 2
 
@@ -71,6 +44,11 @@ static flexio_isr_t s_flexioIsr[FLEXIO_HANDLE_COUNT];
  * Codes
  ******************************************************************************/
 
+/*!
+ * brief Get instance number for FLEXIO module.
+ *
+ * param base FLEXIO peripheral base address.
+ */
 uint32_t FLEXIO_GetInstance(FLEXIO_Type *base)
 {
     uint32_t instance;
@@ -89,6 +67,24 @@ uint32_t FLEXIO_GetInstance(FLEXIO_Type *base)
     return instance;
 }
 
+/*!
+ * brief Configures the FlexIO with a FlexIO configuration. The configuration structure
+ * can be filled by the user or be set with default values by FLEXIO_GetDefaultConfig().
+ *
+ * Example
+   code
+   flexio_config_t config = {
+   .enableFlexio = true,
+   .enableInDoze = false,
+   .enableInDebug = true,
+   .enableFastAccess = false
+   };
+   FLEXIO_Configure(base, &config);
+   endcode
+ *
+ * param base FlexIO peripheral base address
+ * param userConfig pointer to flexio_config_t structure
+*/
 void FLEXIO_Init(FLEXIO_Type *base, const flexio_config_t *userConfig)
 {
     uint32_t ctrlReg = 0;
@@ -111,6 +107,13 @@ void FLEXIO_Init(FLEXIO_Type *base, const flexio_config_t *userConfig)
     base->CTRL = ctrlReg;
 }
 
+/*!
+ * brief Gates the FlexIO clock. Call this API to stop the FlexIO clock.
+ *
+ * note After calling this API, call the FLEXO_Init to use the FlexIO module.
+ *
+ * param base FlexIO peripheral base address
+ */
 void FLEXIO_Deinit(FLEXIO_Type *base)
 {
     FLEXIO_Enable(base, false);
@@ -119,16 +122,36 @@ void FLEXIO_Deinit(FLEXIO_Type *base)
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }
 
+/*!
+ * brief Gets the default configuration to configure the FlexIO module. The configuration
+ * can used directly to call the FLEXIO_Configure().
+ *
+ * Example:
+   code
+   flexio_config_t config;
+   FLEXIO_GetDefaultConfig(&config);
+   endcode
+ *
+ * param userConfig pointer to flexio_config_t structure
+*/
 void FLEXIO_GetDefaultConfig(flexio_config_t *userConfig)
 {
     assert(userConfig);
 
-    userConfig->enableFlexio = true;
-    userConfig->enableInDoze = false;
-    userConfig->enableInDebug = true;
+    /* Initializes the configure structure to zero. */
+    memset(userConfig, 0, sizeof(*userConfig));
+
+    userConfig->enableFlexio     = true;
+    userConfig->enableInDoze     = false;
+    userConfig->enableInDebug    = true;
     userConfig->enableFastAccess = false;
 }
 
+/*!
+ * brief Resets the FlexIO module.
+ *
+ * param base FlexIO peripheral base address
+ */
 void FLEXIO_Reset(FLEXIO_Type *base)
 {
     /*do software reset, software reset operation affect all other FLEXIO registers except CTRL*/
@@ -136,6 +159,14 @@ void FLEXIO_Reset(FLEXIO_Type *base)
     base->CTRL = 0;
 }
 
+/*!
+ * brief Gets the shifter buffer address for the DMA transfer usage.
+ *
+ * param base FlexIO peripheral base address
+ * param type Shifter type of flexio_shifter_buffer_type_t
+ * param index Shifter index
+ * return Corresponding shifter buffer index
+ */
 uint32_t FLEXIO_GetShifterBufferAddress(FLEXIO_Type *base, flexio_shifter_buffer_type_t type, uint8_t index)
 {
     assert(index < FLEXIO_SHIFTBUF_COUNT);
@@ -184,6 +215,31 @@ uint32_t FLEXIO_GetShifterBufferAddress(FLEXIO_Type *base, flexio_shifter_buffer
     return address;
 }
 
+/*!
+ * brief Configures the shifter with the shifter configuration. The configuration structure
+ * covers both the SHIFTCTL and SHIFTCFG registers. To configure the shifter to the proper
+ * mode, select which timer controls the shifter to shift, whether to generate start bit/stop
+ *  bit, and the polarity of start bit and stop bit.
+ *
+ * Example
+   code
+   flexio_shifter_config_t config = {
+   .timerSelect = 0,
+   .timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive,
+   .pinConfig = kFLEXIO_PinConfigOpenDrainOrBidirection,
+   .pinPolarity = kFLEXIO_PinActiveLow,
+   .shifterMode = kFLEXIO_ShifterModeTransmit,
+   .inputSource = kFLEXIO_ShifterInputFromPin,
+   .shifterStop = kFLEXIO_ShifterStopBitHigh,
+   .shifterStart = kFLEXIO_ShifterStartBitLow
+   };
+   FLEXIO_SetShifterConfig(base, &config);
+   endcode
+ *
+ * param base FlexIO peripheral base address
+ * param index Shifter index
+ * param shifterConfig Pointer to flexio_shifter_config_t structure
+*/
 void FLEXIO_SetShifterConfig(FLEXIO_Type *base, uint8_t index, const flexio_shifter_config_t *shifterConfig)
 {
     base->SHIFTCFG[index] = FLEXIO_SHIFTCFG_INSRC(shifterConfig->inputSource)
@@ -199,6 +255,36 @@ void FLEXIO_SetShifterConfig(FLEXIO_Type *base, uint8_t index, const flexio_shif
         FLEXIO_SHIFTCTL_PINPOL(shifterConfig->pinPolarity) | FLEXIO_SHIFTCTL_SMOD(shifterConfig->shifterMode);
 }
 
+/*!
+ * brief Configures the timer with the timer configuration. The configuration structure
+ * covers both the TIMCTL and TIMCFG registers. To configure the timer to the proper
+ * mode, select trigger source for timer and the timer pin output and the timing for timer.
+ *
+ * Example
+   code
+   flexio_timer_config_t config = {
+   .triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(0),
+   .triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow,
+   .triggerSource = kFLEXIO_TimerTriggerSourceInternal,
+   .pinConfig = kFLEXIO_PinConfigOpenDrainOrBidirection,
+   .pinSelect = 0,
+   .pinPolarity = kFLEXIO_PinActiveHigh,
+   .timerMode = kFLEXIO_TimerModeDual8BitBaudBit,
+   .timerOutput = kFLEXIO_TimerOutputZeroNotAffectedByReset,
+   .timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput,
+   .timerReset = kFLEXIO_TimerResetOnTimerPinEqualToTimerOutput,
+   .timerDisable = kFLEXIO_TimerDisableOnTimerCompare,
+   .timerEnable = kFLEXIO_TimerEnableOnTriggerHigh,
+   .timerStop = kFLEXIO_TimerStopBitEnableOnTimerDisable,
+   .timerStart = kFLEXIO_TimerStartBitEnabled
+   };
+   FLEXIO_SetTimerConfig(base, &config);
+   endcode
+ *
+ * param base FlexIO peripheral base address
+ * param index Timer index
+ * param timerConfig Pointer to the flexio_timer_config_t structure
+*/
 void FLEXIO_SetTimerConfig(FLEXIO_Type *base, uint8_t index, const flexio_timer_config_t *timerConfig)
 {
     base->TIMCFG[index] =
@@ -216,6 +302,15 @@ void FLEXIO_SetTimerConfig(FLEXIO_Type *base, uint8_t index, const flexio_timer_
                           FLEXIO_TIMCTL_PINPOL(timerConfig->pinPolarity) | FLEXIO_TIMCTL_TIMOD(timerConfig->timerMode);
 }
 
+/*!
+ * brief Registers the handle and the interrupt handler for the FlexIO-simulated peripheral.
+ *
+ * param base Pointer to the FlexIO simulated peripheral type.
+ * param handle Pointer to the handler for FlexIO simulated peripheral.
+ * param isr FlexIO simulated peripheral interrupt handler.
+ * retval kStatus_Success Successfully create the handle.
+ * retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range.
+ */
 status_t FLEXIO_RegisterHandleIRQ(void *base, void *handle, flexio_isr_t isr)
 {
     assert(base);
@@ -230,9 +325,9 @@ status_t FLEXIO_RegisterHandleIRQ(void *base, void *handle, flexio_isr_t isr)
         if (s_flexioHandle[index] == NULL)
         {
             /* Register FLEXIO simulated driver base, handle and isr. */
-            s_flexioType[index] = base;
+            s_flexioType[index]   = base;
             s_flexioHandle[index] = handle;
-            s_flexioIsr[index] = isr;
+            s_flexioIsr[index]    = isr;
             break;
         }
     }
@@ -247,6 +342,13 @@ status_t FLEXIO_RegisterHandleIRQ(void *base, void *handle, flexio_isr_t isr)
     }
 }
 
+/*!
+ * brief Unregisters the handle and the interrupt handler for the FlexIO-simulated peripheral.
+ *
+ * param base Pointer to the FlexIO simulated peripheral type.
+ * retval kStatus_Success Successfully create the handle.
+ * retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range.
+ */
 status_t FLEXIO_UnregisterHandleIRQ(void *base)
 {
     assert(base);
@@ -259,9 +361,9 @@ status_t FLEXIO_UnregisterHandleIRQ(void *base)
         if (s_flexioType[index] == base)
         {
             /* Unregister FLEXIO simulated driver handle and isr. */
-            s_flexioType[index] = NULL;
+            s_flexioType[index]   = NULL;
             s_flexioHandle[index] = NULL;
-            s_flexioIsr[index] = NULL;
+            s_flexioIsr[index]    = NULL;
             break;
         }
     }
@@ -318,3 +420,8 @@ void FLEXIO2_DriverIRQHandler(void)
 {
     FLEXIO_CommonIRQHandler();
 }
+
+void FLEXIO3_DriverIRQHandler(void)
+{
+    FLEXIO_CommonIRQHandler();
+}
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio.h
index bebca939ec3..b54a1dc2f63 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio.h
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio.h
@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
  * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 #ifndef _FSL_FLEXIO_H_
 #define _FSL_FLEXIO_H_
@@ -60,7 +34,7 @@
 typedef enum _flexio_timer_trigger_polarity
 {
     kFLEXIO_TimerTriggerPolarityActiveHigh = 0x0U, /*!< Active high. */
-    kFLEXIO_TimerTriggerPolarityActiveLow = 0x1U,  /*!< Active low. */
+    kFLEXIO_TimerTriggerPolarityActiveLow  = 0x1U, /*!< Active low. */
 } flexio_timer_trigger_polarity_t;
 
 /*! @brief Define type of timer trigger source.*/
@@ -73,26 +47,26 @@ typedef enum _flexio_timer_trigger_source
 /*! @brief Define type of timer/shifter pin configuration.*/
 typedef enum _flexio_pin_config
 {
-    kFLEXIO_PinConfigOutputDisabled = 0x0U,         /*!< Pin output disabled. */
+    kFLEXIO_PinConfigOutputDisabled         = 0x0U, /*!< Pin output disabled. */
     kFLEXIO_PinConfigOpenDrainOrBidirection = 0x1U, /*!< Pin open drain or bidirectional output enable. */
-    kFLEXIO_PinConfigBidirectionOutputData = 0x2U,  /*!< Pin bidirectional output data. */
-    kFLEXIO_PinConfigOutput = 0x3U,                 /*!< Pin output. */
+    kFLEXIO_PinConfigBidirectionOutputData  = 0x2U, /*!< Pin bidirectional output data. */
+    kFLEXIO_PinConfigOutput                 = 0x3U, /*!< Pin output. */
 } flexio_pin_config_t;
 
 /*! @brief Definition of pin polarity.*/
 typedef enum _flexio_pin_polarity
 {
     kFLEXIO_PinActiveHigh = 0x0U, /*!< Active high. */
-    kFLEXIO_PinActiveLow = 0x1U,  /*!< Active low. */
+    kFLEXIO_PinActiveLow  = 0x1U, /*!< Active low. */
 } flexio_pin_polarity_t;
 
 /*! @brief Define type of timer work mode.*/
 typedef enum _flexio_timer_mode
 {
-    kFLEXIO_TimerModeDisabled = 0x0U,        /*!< Timer Disabled. */
+    kFLEXIO_TimerModeDisabled        = 0x0U, /*!< Timer Disabled. */
     kFLEXIO_TimerModeDual8BitBaudBit = 0x1U, /*!< Dual 8-bit counters baud/bit mode. */
-    kFLEXIO_TimerModeDual8BitPWM = 0x2U,     /*!< Dual 8-bit counters PWM mode. */
-    kFLEXIO_TimerModeSingle16Bit = 0x3U,     /*!< Single 16-bit counter mode. */
+    kFLEXIO_TimerModeDual8BitPWM     = 0x2U, /*!< Dual 8-bit counters PWM mode. */
+    kFLEXIO_TimerModeSingle16Bit     = 0x3U, /*!< Single 16-bit counter mode. */
 } flexio_timer_mode_t;
 
 /*! @brief Define type of timer initial output or timer reset condition.*/
@@ -102,7 +76,7 @@ typedef enum _flexio_timer_output
                                                        reset. */
     kFLEXIO_TimerOutputZeroNotAffectedByReset = 0x1U, /*!< Logic zero when enabled and is not affected by timer
                                                        reset. */
-    kFLEXIO_TimerOutputOneAffectedByReset = 0x2U,     /*!< Logic one when enabled and on timer reset. */
+    kFLEXIO_TimerOutputOneAffectedByReset  = 0x2U,    /*!< Logic one when enabled and on timer reset. */
     kFLEXIO_TimerOutputZeroAffectedByReset = 0x3U,    /*!< Logic zero when enabled and on timer reset. */
 } flexio_timer_output_t;
 
@@ -122,23 +96,23 @@ typedef enum _flexio_timer_decrement_source
 /*! @brief Define type of timer reset condition.*/
 typedef enum _flexio_timer_reset_condition
 {
-    kFLEXIO_TimerResetNever = 0x0U,                            /*!< Timer never reset. */
-    kFLEXIO_TimerResetOnTimerPinEqualToTimerOutput = 0x2U,     /*!< Timer reset on Timer Pin equal to Timer Output. */
+    kFLEXIO_TimerResetNever                            = 0x0U, /*!< Timer never reset. */
+    kFLEXIO_TimerResetOnTimerPinEqualToTimerOutput     = 0x2U, /*!< Timer reset on Timer Pin equal to Timer Output. */
     kFLEXIO_TimerResetOnTimerTriggerEqualToTimerOutput = 0x3U, /*!< Timer reset on Timer Trigger equal to
                                                                 Timer Output. */
-    kFLEXIO_TimerResetOnTimerPinRisingEdge = 0x4U,             /*!< Timer reset on Timer Pin rising edge. */
+    kFLEXIO_TimerResetOnTimerPinRisingEdge     = 0x4U,         /*!< Timer reset on Timer Pin rising edge. */
     kFLEXIO_TimerResetOnTimerTriggerRisingEdge = 0x6U,         /*!< Timer reset on Trigger rising edge. */
-    kFLEXIO_TimerResetOnTimerTriggerBothEdge = 0x7U,           /*!< Timer reset on Trigger rising or falling edge. */
+    kFLEXIO_TimerResetOnTimerTriggerBothEdge   = 0x7U,         /*!< Timer reset on Trigger rising or falling edge. */
 } flexio_timer_reset_condition_t;
 
 /*! @brief Define type of timer disable condition.*/
 typedef enum _flexio_timer_disable_condition
 {
-    kFLEXIO_TimerDisableNever = 0x0U,                    /*!< Timer never disabled. */
-    kFLEXIO_TimerDisableOnPreTimerDisable = 0x1U,        /*!< Timer disabled on Timer N-1 disable. */
-    kFLEXIO_TimerDisableOnTimerCompare = 0x2U,           /*!< Timer disabled on Timer compare. */
+    kFLEXIO_TimerDisableNever                    = 0x0U, /*!< Timer never disabled. */
+    kFLEXIO_TimerDisableOnPreTimerDisable        = 0x1U, /*!< Timer disabled on Timer N-1 disable. */
+    kFLEXIO_TimerDisableOnTimerCompare           = 0x2U, /*!< Timer disabled on Timer compare. */
     kFLEXIO_TimerDisableOnTimerCompareTriggerLow = 0x3U, /*!< Timer disabled on Timer compare and Trigger Low. */
-    kFLEXIO_TimerDisableOnPinBothEdge = 0x4U,            /*!< Timer disabled on Pin rising or falling edge. */
+    kFLEXIO_TimerDisableOnPinBothEdge            = 0x4U, /*!< Timer disabled on Pin rising or falling edge. */
     kFLEXIO_TimerDisableOnPinBothEdgeTriggerHigh = 0x5U, /*!< Timer disabled on Pin rising or falling edge provided
                                                           Trigger is high. */
     kFLEXIO_TimerDisableOnTriggerFallingEdge = 0x6U,     /*!< Timer disabled on Trigger falling edge. */
@@ -147,22 +121,22 @@ typedef enum _flexio_timer_disable_condition
 /*! @brief Define type of timer enable condition.*/
 typedef enum _flexio_timer_enable_condition
 {
-    kFLEXIO_TimerEnabledAlways = 0x0U,                    /*!< Timer always enabled. */
-    kFLEXIO_TimerEnableOnPrevTimerEnable = 0x1U,          /*!< Timer enabled on Timer N-1 enable. */
-    kFLEXIO_TimerEnableOnTriggerHigh = 0x2U,              /*!< Timer enabled on Trigger high. */
-    kFLEXIO_TimerEnableOnTriggerHighPinHigh = 0x3U,       /*!< Timer enabled on Trigger high and Pin high. */
-    kFLEXIO_TimerEnableOnPinRisingEdge = 0x4U,            /*!< Timer enabled on Pin rising edge. */
+    kFLEXIO_TimerEnabledAlways                    = 0x0U, /*!< Timer always enabled. */
+    kFLEXIO_TimerEnableOnPrevTimerEnable          = 0x1U, /*!< Timer enabled on Timer N-1 enable. */
+    kFLEXIO_TimerEnableOnTriggerHigh              = 0x2U, /*!< Timer enabled on Trigger high. */
+    kFLEXIO_TimerEnableOnTriggerHighPinHigh       = 0x3U, /*!< Timer enabled on Trigger high and Pin high. */
+    kFLEXIO_TimerEnableOnPinRisingEdge            = 0x4U, /*!< Timer enabled on Pin rising edge. */
     kFLEXIO_TimerEnableOnPinRisingEdgeTriggerHigh = 0x5U, /*!< Timer enabled on Pin rising edge and Trigger high. */
-    kFLEXIO_TimerEnableOnTriggerRisingEdge = 0x6U,        /*!< Timer enabled on Trigger rising edge. */
-    kFLEXIO_TimerEnableOnTriggerBothEdge = 0x7U,          /*!< Timer enabled on Trigger rising or falling edge. */
+    kFLEXIO_TimerEnableOnTriggerRisingEdge        = 0x6U, /*!< Timer enabled on Trigger rising edge. */
+    kFLEXIO_TimerEnableOnTriggerBothEdge          = 0x7U, /*!< Timer enabled on Trigger rising or falling edge. */
 } flexio_timer_enable_condition_t;
 
 /*! @brief Define type of timer stop bit generate condition.*/
 typedef enum _flexio_timer_stop_bit_condition
 {
-    kFLEXIO_TimerStopBitDisabled = 0x0U,                    /*!< Stop bit disabled. */
-    kFLEXIO_TimerStopBitEnableOnTimerCompare = 0x1U,        /*!< Stop bit is enabled on timer compare. */
-    kFLEXIO_TimerStopBitEnableOnTimerDisable = 0x2U,        /*!< Stop bit is enabled on timer disable. */
+    kFLEXIO_TimerStopBitDisabled                    = 0x0U, /*!< Stop bit disabled. */
+    kFLEXIO_TimerStopBitEnableOnTimerCompare        = 0x1U, /*!< Stop bit is enabled on timer compare. */
+    kFLEXIO_TimerStopBitEnableOnTimerDisable        = 0x2U, /*!< Stop bit is enabled on timer disable. */
     kFLEXIO_TimerStopBitEnableOnTimerCompareDisable = 0x3U, /*!< Stop bit is enabled on timer compare and timer
                                                              disable. */
 } flexio_timer_stop_bit_condition_t;
@@ -171,23 +145,23 @@ typedef enum _flexio_timer_stop_bit_condition
 typedef enum _flexio_timer_start_bit_condition
 {
     kFLEXIO_TimerStartBitDisabled = 0x0U, /*!< Start bit disabled. */
-    kFLEXIO_TimerStartBitEnabled = 0x1U,  /*!< Start bit enabled. */
+    kFLEXIO_TimerStartBitEnabled  = 0x1U, /*!< Start bit enabled. */
 } flexio_timer_start_bit_condition_t;
 
 /*! @brief Define type of timer polarity for shifter control. */
 typedef enum _flexio_shifter_timer_polarity
 {
-    kFLEXIO_ShifterTimerPolarityOnPositive = 0x0U, /* Shift on positive edge of shift clock. */
-    kFLEXIO_ShifterTimerPolarityOnNegitive = 0x1U, /* Shift on negative edge of shift clock. */
+    kFLEXIO_ShifterTimerPolarityOnPositive = 0x0U, /*!< Shift on positive edge of shift clock. */
+    kFLEXIO_ShifterTimerPolarityOnNegitive = 0x1U, /*!< Shift on negative edge of shift clock. */
 } flexio_shifter_timer_polarity_t;
 
 /*! @brief Define type of shifter working mode.*/
 typedef enum _flexio_shifter_mode
 {
-    kFLEXIO_ShifterDisabled = 0x0U,            /*!< Shifter is disabled. */
-    kFLEXIO_ShifterModeReceive = 0x1U,         /*!< Receive mode. */
-    kFLEXIO_ShifterModeTransmit = 0x2U,        /*!< Transmit mode. */
-    kFLEXIO_ShifterModeMatchStore = 0x4U,      /*!< Match store mode. */
+    kFLEXIO_ShifterDisabled            = 0x0U, /*!< Shifter is disabled. */
+    kFLEXIO_ShifterModeReceive         = 0x1U, /*!< Receive mode. */
+    kFLEXIO_ShifterModeTransmit        = 0x2U, /*!< Transmit mode. */
+    kFLEXIO_ShifterModeMatchStore      = 0x4U, /*!< Match store mode. */
     kFLEXIO_ShifterModeMatchContinuous = 0x5U, /*!< Match continuous mode. */
 #if FSL_FEATURE_FLEXIO_HAS_STATE_MODE
     kFLEXIO_ShifterModeState = 0x6U, /*!< SHIFTBUF contents are used for storing
@@ -202,7 +176,7 @@ typedef enum _flexio_shifter_mode
 /*! @brief Define type of shifter input source.*/
 typedef enum _flexio_shifter_input_source
 {
-    kFLEXIO_ShifterInputFromPin = 0x0U,               /*!< Shifter input from pin. */
+    kFLEXIO_ShifterInputFromPin               = 0x0U, /*!< Shifter input from pin. */
     kFLEXIO_ShifterInputFromNextShifterOutput = 0x1U, /*!< Shifter input from Shifter N+1. */
 } flexio_shifter_input_source_t;
 
@@ -210,8 +184,8 @@ typedef enum _flexio_shifter_input_source
 typedef enum _flexio_shifter_stop_bit
 {
     kFLEXIO_ShifterStopBitDisable = 0x0U, /*!< Disable shifter stop bit. */
-    kFLEXIO_ShifterStopBitLow = 0x2U,     /*!< Set shifter stop bit to logic low level. */
-    kFLEXIO_ShifterStopBitHigh = 0x3U,    /*!< Set shifter stop bit to logic high level. */
+    kFLEXIO_ShifterStopBitLow     = 0x2U, /*!< Set shifter stop bit to logic low level. */
+    kFLEXIO_ShifterStopBitHigh    = 0x3U, /*!< Set shifter stop bit to logic high level. */
 } flexio_shifter_stop_bit_t;
 
 /*! @brief Define type of START bit configuration.*/
@@ -221,16 +195,16 @@ typedef enum _flexio_shifter_start_bit
                                                              data on enable. */
     kFLEXIO_ShifterStartBitDisabledLoadDataOnShift = 0x1U,  /*!< Disable shifter start bit, transmitter loads
                                                              data on first shift. */
-    kFLEXIO_ShifterStartBitLow = 0x2U,                      /*!< Set shifter start bit to logic low level. */
+    kFLEXIO_ShifterStartBitLow  = 0x2U,                     /*!< Set shifter start bit to logic low level. */
     kFLEXIO_ShifterStartBitHigh = 0x3U,                     /*!< Set shifter start bit to logic high level. */
 } flexio_shifter_start_bit_t;
 
 /*! @brief Define FlexIO shifter buffer type*/
 typedef enum _flexio_shifter_buffer_type
 {
-    kFLEXIO_ShifterBuffer = 0x0U,               /*!< Shifter Buffer N Register. */
-    kFLEXIO_ShifterBufferBitSwapped = 0x1U,     /*!< Shifter Buffer N Bit Byte Swapped Register. */
-    kFLEXIO_ShifterBufferByteSwapped = 0x2U,    /*!< Shifter Buffer N Byte Swapped Register. */
+    kFLEXIO_ShifterBuffer               = 0x0U, /*!< Shifter Buffer N Register. */
+    kFLEXIO_ShifterBufferBitSwapped     = 0x1U, /*!< Shifter Buffer N Bit Byte Swapped Register. */
+    kFLEXIO_ShifterBufferByteSwapped    = 0x2U, /*!< Shifter Buffer N Byte Swapped Register. */
     kFLEXIO_ShifterBufferBitByteSwapped = 0x3U, /*!< Shifter Buffer N Bit Swapped Register. */
 #if defined(FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP) && FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP
     kFLEXIO_ShifterBufferNibbleByteSwapped = 0x4U, /*!< Shifter Buffer N Nibble Byte Swapped Register. */
@@ -368,7 +342,7 @@ void FLEXIO_Init(FLEXIO_Type *base, const flexio_config_t *userConfig);
  * @note After calling this API, call the FLEXO_Init to use the FlexIO module.
  *
  * @param base FlexIO peripheral base address
-*/
+ */
 void FLEXIO_Deinit(FLEXIO_Type *base);
 
 /*!
@@ -389,7 +363,7 @@ uint32_t FLEXIO_GetInstance(FLEXIO_Type *base);
  * @brief Resets the FlexIO module.
  *
  * @param base FlexIO peripheral base address
-*/
+ */
 void FLEXIO_Reset(FLEXIO_Type *base);
 
 /*!
@@ -397,7 +371,7 @@ void FLEXIO_Reset(FLEXIO_Type *base);
  *
  * @param base FlexIO peripheral base address
  * @param enable true to enable, false to disable.
-*/
+ */
 static inline void FLEXIO_Enable(FLEXIO_Type *base, bool enable)
 {
     if (enable)
@@ -416,7 +390,7 @@ static inline void FLEXIO_Enable(FLEXIO_Type *base, bool enable)
  *
  * @param base FlexIO peripheral base address
  * @return FlexIO pin input data
-*/
+ */
 static inline uint32_t FLEXIO_ReadPinInput(FLEXIO_Type *base)
 {
     return base->PIN;
@@ -429,7 +403,7 @@ static inline uint32_t FLEXIO_ReadPinInput(FLEXIO_Type *base)
  *
  * @param base FlexIO peripheral base address
  * @return current State pointer
-*/
+ */
 static inline uint8_t FLEXIO_GetShifterState(FLEXIO_Type *base)
 {
     return ((base->SHIFTSTATE) & FLEXIO_SHIFTSTATE_STATE_MASK);
@@ -508,7 +482,7 @@ void FLEXIO_SetTimerConfig(FLEXIO_Type *base, uint8_t index, const flexio_timer_
  * @param mask The shifter status mask which can be calculated by (1 << shifter index)
  * @note For multiple shifter status interrupt enable, for example, two shifter status enable, can calculate
  * the mask by using ((1 << shifter index0) | (1 << shifter index1))
-*/
+ */
 static inline void FLEXIO_EnableShifterStatusInterrupts(FLEXIO_Type *base, uint32_t mask)
 {
     base->SHIFTSIEN |= mask;
@@ -521,7 +495,7 @@ static inline void FLEXIO_EnableShifterStatusInterrupts(FLEXIO_Type *base, uint3
  * @param mask The shifter status mask which can be calculated by (1 << shifter index)
  * @note For multiple shifter status interrupt enable, for example, two shifter status enable, can calculate
  * the mask by using ((1 << shifter index0) | (1 << shifter index1))
-*/
+ */
 static inline void FLEXIO_DisableShifterStatusInterrupts(FLEXIO_Type *base, uint32_t mask)
 {
     base->SHIFTSIEN &= ~mask;
@@ -534,7 +508,7 @@ static inline void FLEXIO_DisableShifterStatusInterrupts(FLEXIO_Type *base, uint
  * @param mask The shifter error mask which can be calculated by (1 << shifter index)
  * @note For multiple shifter error interrupt enable, for example, two shifter error enable, can calculate
  * the mask by using ((1 << shifter index0) | (1 << shifter index1))
-*/
+ */
 static inline void FLEXIO_EnableShifterErrorInterrupts(FLEXIO_Type *base, uint32_t mask)
 {
     base->SHIFTEIEN |= mask;
@@ -547,7 +521,7 @@ static inline void FLEXIO_EnableShifterErrorInterrupts(FLEXIO_Type *base, uint32
  * @param mask The shifter error mask which can be calculated by (1 << shifter index)
  * @note For multiple shifter error interrupt enable, for example, two shifter error enable, can calculate
  * the mask by using ((1 << shifter index0) | (1 << shifter index1))
-*/
+ */
 static inline void FLEXIO_DisableShifterErrorInterrupts(FLEXIO_Type *base, uint32_t mask)
 {
     base->SHIFTEIEN &= ~mask;
@@ -560,7 +534,7 @@ static inline void FLEXIO_DisableShifterErrorInterrupts(FLEXIO_Type *base, uint3
  * @param mask The timer status mask which can be calculated by (1 << timer index)
  * @note For multiple timer status interrupt enable, for example, two timer status enable, can calculate
  * the mask by using ((1 << timer index0) | (1 << timer index1))
-*/
+ */
 static inline void FLEXIO_EnableTimerStatusInterrupts(FLEXIO_Type *base, uint32_t mask)
 {
     base->TIMIEN |= mask;
@@ -573,7 +547,7 @@ static inline void FLEXIO_EnableTimerStatusInterrupts(FLEXIO_Type *base, uint32_
  * @param mask The timer status mask which can be calculated by (1 << timer index)
  * @note For multiple timer status interrupt enable, for example, two timer status enable, can calculate
  * the mask by using ((1 << timer index0) | (1 << timer index1))
-*/
+ */
 static inline void FLEXIO_DisableTimerStatusInterrupts(FLEXIO_Type *base, uint32_t mask)
 {
     base->TIMIEN &= ~mask;
@@ -591,7 +565,7 @@ static inline void FLEXIO_DisableTimerStatusInterrupts(FLEXIO_Type *base, uint32
  *
  * @param base FlexIO peripheral base address
  * @return Shifter status flags
-*/
+ */
 static inline uint32_t FLEXIO_GetShifterStatusFlags(FLEXIO_Type *base)
 {
     return ((base->SHIFTSTAT) & FLEXIO_SHIFTSTAT_SSF_MASK);
@@ -604,7 +578,7 @@ static inline uint32_t FLEXIO_GetShifterStatusFlags(FLEXIO_Type *base)
  * @param mask The shifter status mask which can be calculated by (1 << shifter index)
  * @note For clearing multiple shifter status flags, for example, two shifter status flags, can calculate
  * the mask by using ((1 << shifter index0) | (1 << shifter index1))
-*/
+ */
 static inline void FLEXIO_ClearShifterStatusFlags(FLEXIO_Type *base, uint32_t mask)
 {
     base->SHIFTSTAT = mask;
@@ -615,7 +589,7 @@ static inline void FLEXIO_ClearShifterStatusFlags(FLEXIO_Type *base, uint32_t ma
  *
  * @param base FlexIO peripheral base address
  * @return Shifter error flags
-*/
+ */
 static inline uint32_t FLEXIO_GetShifterErrorFlags(FLEXIO_Type *base)
 {
     return ((base->SHIFTERR) & FLEXIO_SHIFTERR_SEF_MASK);
@@ -628,7 +602,7 @@ static inline uint32_t FLEXIO_GetShifterErrorFlags(FLEXIO_Type *base)
  * @param mask The shifter error mask which can be calculated by (1 << shifter index)
  * @note For clearing multiple shifter error flags, for example, two shifter error flags, can calculate
  * the mask by using ((1 << shifter index0) | (1 << shifter index1))
-*/
+ */
 static inline void FLEXIO_ClearShifterErrorFlags(FLEXIO_Type *base, uint32_t mask)
 {
     base->SHIFTERR = mask;
@@ -639,7 +613,7 @@ static inline void FLEXIO_ClearShifterErrorFlags(FLEXIO_Type *base, uint32_t mas
  *
  * @param base FlexIO peripheral base address
  * @return Timer status flags
-*/
+ */
 static inline uint32_t FLEXIO_GetTimerStatusFlags(FLEXIO_Type *base)
 {
     return ((base->TIMSTAT) & FLEXIO_TIMSTAT_TSF_MASK);
@@ -652,7 +626,7 @@ static inline uint32_t FLEXIO_GetTimerStatusFlags(FLEXIO_Type *base)
  * @param mask The timer status mask which can be calculated by (1 << timer index)
  * @note For clearing multiple timer status flags, for example, two timer status flags, can calculate
  * the mask by using ((1 << timer index0) | (1 << timer index1))
-*/
+ */
 static inline void FLEXIO_ClearTimerStatusFlags(FLEXIO_Type *base, uint32_t mask)
 {
     base->TIMSTAT = mask;
@@ -674,7 +648,7 @@ static inline void FLEXIO_ClearTimerStatusFlags(FLEXIO_Type *base, uint32_t mask
  * @param base FlexIO peripheral base address
  * @param mask The shifter status mask which can be calculated by (1 << shifter index)
  * @param enable True to enable, false to disable.
-*/
+ */
 static inline void FLEXIO_EnableShifterStatusDMA(FLEXIO_Type *base, uint32_t mask, bool enable)
 {
     if (enable)
@@ -694,7 +668,7 @@ static inline void FLEXIO_EnableShifterStatusDMA(FLEXIO_Type *base, uint32_t mas
  * @param type Shifter type of flexio_shifter_buffer_type_t
  * @param index Shifter index
  * @return Corresponding shifter buffer index
-*/
+ */
 uint32_t FLEXIO_GetShifterBufferAddress(FLEXIO_Type *base, flexio_shifter_buffer_type_t type, uint8_t index);
 
 /*!
@@ -705,7 +679,7 @@ uint32_t FLEXIO_GetShifterBufferAddress(FLEXIO_Type *base, flexio_shifter_buffer
  * @param isr FlexIO simulated peripheral interrupt handler.
  * @retval kStatus_Success Successfully create the handle.
  * @retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range.
-*/
+ */
 status_t FLEXIO_RegisterHandleIRQ(void *base, void *handle, flexio_isr_t isr);
 
 /*!
@@ -714,7 +688,7 @@ status_t FLEXIO_RegisterHandleIRQ(void *base, void *handle, flexio_isr_t isr);
  * @param base Pointer to the FlexIO simulated peripheral type.
  * @retval kStatus_Success Successfully create the handle.
  * @retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range.
-*/
+ */
 status_t FLEXIO_UnregisterHandleIRQ(void *base);
 /* @} */
 
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_camera.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_camera.c
new file mode 100644
index 00000000000..e699522c628
--- /dev/null
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_camera.c
@@ -0,0 +1,213 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_flexio_camera.h"
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.flexio_camera"
+#endif
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Codes
+ ******************************************************************************/
+
+static uint32_t FLEXIO_CAMERA_GetInstance(FLEXIO_CAMERA_Type *base)
+{
+    return FLEXIO_GetInstance(base->flexioBase);
+}
+
+/*!
+ * brief Gets the default configuration to configure the FlexIO Camera. The configuration
+ * can be used directly for calling the FLEXIO_CAMERA_Init().
+ * Example:
+   code
+   flexio_camera_config_t config;
+   FLEXIO_CAMERA_GetDefaultConfig(&userConfig);
+   endcode
+ * param config Pointer to the flexio_camera_config_t structure
+*/
+void FLEXIO_CAMERA_GetDefaultConfig(flexio_camera_config_t *config)
+{
+    assert(config);
+
+    /* Initializes the configure structure to zero. */
+    memset(config, 0, sizeof(*config));
+
+    config->enablecamera     = false;
+    config->enableInDoze     = false;
+    config->enableInDebug    = false;
+    config->enableFastAccess = false;
+}
+
+/*!
+ * brief Ungates the FlexIO clock, resets the FlexIO module, and configures the FlexIO Camera.
+ *
+ * param base Pointer to FLEXIO_CAMERA_Type structure
+ * param config Pointer to flexio_camera_config_t structure
+ */
+void FLEXIO_CAMERA_Init(FLEXIO_CAMERA_Type *base, const flexio_camera_config_t *config)
+{
+    assert(base && config);
+
+    volatile uint32_t i          = 0;
+    volatile uint32_t controlVal = 0;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Ungate flexio clock. */
+    CLOCK_EnableClock(s_flexioClocks[FLEXIO_CAMERA_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+    flexio_shifter_config_t shifterConfig;
+    flexio_timer_config_t timerConfig;
+
+    /* Clear the shifterConfig & timerConfig struct. */
+    memset(&shifterConfig, 0, sizeof(shifterConfig));
+    memset(&timerConfig, 0, sizeof(timerConfig));
+
+    /* Configure flexio camera */
+    controlVal = base->flexioBase->CTRL;
+    controlVal &=
+        ~(FLEXIO_CTRL_DOZEN_MASK | FLEXIO_CTRL_DBGE_MASK | FLEXIO_CTRL_FASTACC_MASK | FLEXIO_CTRL_FLEXEN_MASK);
+    controlVal |= (FLEXIO_CTRL_DBGE(config->enableInDebug) | FLEXIO_CTRL_FASTACC(config->enableFastAccess) |
+                   FLEXIO_CTRL_FLEXEN(config->enablecamera));
+    if (!config->enableInDoze)
+    {
+        controlVal |= FLEXIO_CTRL_DOZEN_MASK;
+    }
+    base->flexioBase->CTRL = controlVal;
+
+    /* FLEXIO_CAMERA shifter config */
+    shifterConfig.timerSelect   = base->timerIdx;
+    shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive;
+    shifterConfig.pinConfig     = kFLEXIO_PinConfigOutputDisabled;
+    shifterConfig.pinSelect     = base->datPinStartIdx;
+    shifterConfig.pinPolarity   = kFLEXIO_PinActiveHigh;
+    shifterConfig.shifterMode   = kFLEXIO_ShifterModeReceive;
+    shifterConfig.parallelWidth = FLEXIO_CAMERA_PARALLEL_DATA_WIDTH - 1U;
+    shifterConfig.inputSource   = kFLEXIO_ShifterInputFromNextShifterOutput;
+    shifterConfig.shifterStop   = kFLEXIO_ShifterStopBitDisable;
+    shifterConfig.shifterStart  = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable;
+    /* Configure the shifters as FIFO buffer. */
+    for (i = base->shifterStartIdx; i < (base->shifterStartIdx + base->shifterCount - 1U); i++)
+    {
+        FLEXIO_SetShifterConfig(base->flexioBase, i, &shifterConfig);
+    }
+    shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin;
+    FLEXIO_SetShifterConfig(base->flexioBase, i, &shifterConfig);
+
+    /* FLEXIO_CAMERA timer config, the PCLK's clk is source of timer to drive the shifter, the HREF is the selecting
+     * signal for available data. */
+    timerConfig.triggerSelect   = FLEXIO_TIMER_TRIGGER_SEL_PININPUT(base->hrefPinIdx);
+    timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveHigh;
+    timerConfig.triggerSource   = kFLEXIO_TimerTriggerSourceInternal;
+    timerConfig.pinConfig       = kFLEXIO_PinConfigOutputDisabled;
+    timerConfig.pinSelect       = base->pclkPinIdx;
+    timerConfig.pinPolarity     = kFLEXIO_PinActiveHigh;
+    timerConfig.timerMode       = kFLEXIO_TimerModeSingle16Bit;
+    timerConfig.timerOutput     = kFLEXIO_TimerOutputZeroNotAffectedByReset;
+    timerConfig.timerDecrement  = kFLEXIO_TimerDecSrcOnPinInputShiftPinInput;
+    timerConfig.timerReset      = kFLEXIO_TimerResetOnTimerTriggerRisingEdge;
+    timerConfig.timerDisable    = kFLEXIO_TimerDisableOnTriggerFallingEdge;
+    timerConfig.timerEnable     = kFLEXIO_TimerEnableOnTriggerRisingEdge;
+    timerConfig.timerStop       = kFLEXIO_TimerStopBitDisabled;
+    timerConfig.timerStart      = kFLEXIO_TimerStartBitDisabled;
+    timerConfig.timerCompare    = 8U * base->shifterCount - 1U;
+
+    FLEXIO_SetTimerConfig(base->flexioBase, base->timerIdx, &timerConfig);
+    /* Clear flags. */
+    FLEXIO_ClearShifterErrorFlags(base->flexioBase, ((1U << (base->shifterCount)) - 1U) << (base->shifterStartIdx));
+    FLEXIO_ClearTimerStatusFlags(base->flexioBase, 1U << (base->timerIdx));
+}
+
+/*!
+ * brief Resets the FLEXIO_CAMERA shifer and timer config.
+ *
+ * note After calling this API, call FLEXO_CAMERA_Init to use the FlexIO Camera module.
+ *
+ * param base Pointer to FLEXIO_CAMERA_Type structure
+ */
+void FLEXIO_CAMERA_Deinit(FLEXIO_CAMERA_Type *base)
+{
+    base->flexioBase->SHIFTCFG[base->shifterStartIdx] = 0;
+    base->flexioBase->SHIFTCTL[base->shifterStartIdx] = 0;
+    base->flexioBase->TIMCFG[base->timerIdx]          = 0;
+    base->flexioBase->TIMCMP[base->timerIdx]          = 0;
+    base->flexioBase->TIMCTL[base->timerIdx]          = 0;
+    /* Clear the shifter flag. */
+    base->flexioBase->SHIFTSTAT = (1U << base->shifterStartIdx);
+    /* Clear the timer flag. */
+    base->flexioBase->TIMSTAT = (1U << base->timerIdx);
+}
+
+/*!
+ * brief Gets the FlexIO Camera status flags.
+ *
+ * param base Pointer to FLEXIO_CAMERA_Type structure
+ * return FlexIO shifter status flags
+ *          arg FLEXIO_SHIFTSTAT_SSF_MASK
+ *          arg 0
+ */
+uint32_t FLEXIO_CAMERA_GetStatusFlags(FLEXIO_CAMERA_Type *base)
+{
+    uint32_t status = 0;
+    status          = ((FLEXIO_GetShifterStatusFlags(base->flexioBase) >> (base->shifterStartIdx)) &
+              ((1U << (base->shifterCount)) - 1U));
+    return status;
+}
+
+/*!
+ * brief Clears the receive buffer full flag manually.
+ *
+ * param base Pointer to the device.
+ * param mask status flag
+ *      The parameter can be any combination of the following values:
+ *          arg kFLEXIO_CAMERA_RxDataRegFullFlag
+ *          arg kFLEXIO_CAMERA_RxErrorFlag
+ */
+void FLEXIO_CAMERA_ClearStatusFlags(FLEXIO_CAMERA_Type *base, uint32_t mask)
+{
+    if (mask & kFLEXIO_CAMERA_RxDataRegFullFlag)
+    {
+        FLEXIO_ClearShifterStatusFlags(base->flexioBase, ((1U << (base->shifterCount)) - 1U)
+                                                             << (base->shifterStartIdx));
+    }
+    if (mask & kFLEXIO_CAMERA_RxErrorFlag)
+    { /* Clear error flags if they are asserted to make sure the buffer would be available. */
+        FLEXIO_ClearShifterErrorFlags(base->flexioBase, ((1U << (base->shifterCount)) - 1U) << (base->shifterStartIdx));
+    }
+}
+
+/*!
+ * brief Switches on the interrupt for receive buffer full event.
+ *
+ * param base Pointer to the device.
+ */
+void FLEXIO_CAMERA_EnableInterrupt(FLEXIO_CAMERA_Type *base)
+{
+    FLEXIO_EnableShifterStatusInterrupts(base->flexioBase, 1U << (base->shifterStartIdx));
+}
+
+/*!
+ * brief Switches off the interrupt for receive buffer full event.
+ *
+ * param base Pointer to the device.
+ *
+ */
+void FLEXIO_CAMERA_DisableInterrupt(FLEXIO_CAMERA_Type *base)
+{
+    FLEXIO_DisableShifterStatusInterrupts(base->flexioBase, 1U << (base->shifterStartIdx));
+}
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_camera.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_camera.h
new file mode 100644
index 00000000000..6d7fec25744
--- /dev/null
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_camera.h
@@ -0,0 +1,230 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_FLEXIO_CAMERA_H_
+#define _FSL_FLEXIO_CAMERA_H_
+
+#include "fsl_common.h"
+#include "fsl_flexio.h"
+/*!
+ * @addtogroup flexio_camera
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief FlexIO Camera driver version 2.1.2. */
+#define FSL_FLEXIO_CAMERA_DRIVER_VERSION (MAKE_VERSION(2, 1, 2))
+/*@}*/
+
+/*! @brief Define the Camera CPI interface is constantly 8-bit width. */
+#define FLEXIO_CAMERA_PARALLEL_DATA_WIDTH (8U)
+
+/*! @brief Error codes for the Camera driver. */
+enum _flexio_camera_status
+{
+    kStatus_FLEXIO_CAMERA_RxBusy = MAKE_STATUS(kStatusGroup_FLEXIO_CAMERA, 0), /*!< Receiver is busy. */
+    kStatus_FLEXIO_CAMERA_RxIdle = MAKE_STATUS(kStatusGroup_FLEXIO_CAMERA, 1), /*!< Camera receiver is idle. */
+};
+
+/*! @brief Define FlexIO Camera status mask. */
+enum _flexio_camera_status_flags
+{
+    kFLEXIO_CAMERA_RxDataRegFullFlag = 0x1U, /*!< Receive buffer full flag. */
+    kFLEXIO_CAMERA_RxErrorFlag       = 0x2U, /*!< Receive buffer error flag. */
+};
+
+/*!
+ * @brief Define structure of configuring the FlexIO Camera device.
+ */
+typedef struct _flexio_camera_type
+{
+    FLEXIO_Type *flexioBase; /*!< FlexIO module base address. */
+    uint32_t datPinStartIdx; /*!< First data pin (D0) index for flexio_camera.
+                                  Then the successive following FLEXIO_CAMERA_DATA_WIDTH-1 pins
+                                  are used as D1-D7.*/
+    uint32_t pclkPinIdx;     /*!< Pixel clock pin (PCLK) index for flexio_camera. */
+    uint32_t hrefPinIdx;     /*!< Horizontal sync pin (HREF) index for flexio_camera. */
+
+    uint32_t shifterStartIdx; /*!< First shifter index used for flexio_camera data FIFO. */
+    uint32_t shifterCount;    /*!< The count of shifters that are used as flexio_camera data FIFO. */
+    uint32_t timerIdx;        /*!< Timer index used for flexio_camera in FlexIO. */
+} FLEXIO_CAMERA_Type;
+
+/*! @brief Define FlexIO Camera user configuration structure. */
+typedef struct _flexio_camera_config
+{
+    bool enablecamera;     /*!< Enable/disable FlexIO Camera TX & RX. */
+    bool enableInDoze;     /*!< Enable/disable FlexIO operation in doze mode*/
+    bool enableInDebug;    /*!< Enable/disable FlexIO operation in debug mode*/
+    bool enableFastAccess; /*!< Enable/disable fast access to FlexIO registers,
+                            fast access requires the FlexIO clock to be at least
+                            twice the frequency of the bus clock. */
+} flexio_camera_config_t;
+
+/*! @brief Define FlexIO Camera transfer structure. */
+typedef struct _flexio_camera_transfer
+{
+    uint32_t dataAddress; /*!< Transfer buffer*/
+    uint32_t dataNum;     /*!< Transfer num*/
+} flexio_camera_transfer_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /*_cplusplus*/
+
+/*!
+ * @name Initialization and configuration
+ * @{
+ */
+
+/*!
+ * @brief Ungates the FlexIO clock, resets the FlexIO module, and configures the FlexIO Camera.
+ *
+ * @param base Pointer to FLEXIO_CAMERA_Type structure
+ * @param config Pointer to flexio_camera_config_t structure
+ */
+void FLEXIO_CAMERA_Init(FLEXIO_CAMERA_Type *base, const flexio_camera_config_t *config);
+
+/*!
+ * @brief Resets the FLEXIO_CAMERA shifer and timer config.
+ *
+ * @note After calling this API, call FLEXO_CAMERA_Init to use the FlexIO Camera module.
+ *
+ * @param base Pointer to FLEXIO_CAMERA_Type structure
+ */
+void FLEXIO_CAMERA_Deinit(FLEXIO_CAMERA_Type *base);
+
+/*!
+ * @brief Gets the default configuration to configure the FlexIO Camera. The configuration
+ * can be used directly for calling the FLEXIO_CAMERA_Init().
+ * Example:
+   @code
+   flexio_camera_config_t config;
+   FLEXIO_CAMERA_GetDefaultConfig(&userConfig);
+   @endcode
+ * @param config Pointer to the flexio_camera_config_t structure
+*/
+void FLEXIO_CAMERA_GetDefaultConfig(flexio_camera_config_t *config);
+
+/*!
+ * @brief Enables/disables the FlexIO Camera module operation.
+ *
+ * @param base Pointer to the FLEXIO_CAMERA_Type
+ * @param enable True to enable, false does not have any effect.
+ */
+static inline void FLEXIO_CAMERA_Enable(FLEXIO_CAMERA_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->flexioBase->CTRL |= FLEXIO_CTRL_FLEXEN_MASK;
+    }
+}
+
+/*! @} */
+
+/*!
+ * @name Status
+ * @{
+ */
+
+/*!
+ * @brief Gets the FlexIO Camera status flags.
+ *
+ * @param base Pointer to FLEXIO_CAMERA_Type structure
+ * @return FlexIO shifter status flags
+ *          @arg FLEXIO_SHIFTSTAT_SSF_MASK
+ *          @arg 0
+ */
+uint32_t FLEXIO_CAMERA_GetStatusFlags(FLEXIO_CAMERA_Type *base);
+
+/*!
+ * @brief Clears the receive buffer full flag manually.
+ *
+ * @param base Pointer to the device.
+ * @param mask status flag
+ *      The parameter can be any combination of the following values:
+ *          @arg kFLEXIO_CAMERA_RxDataRegFullFlag
+ *          @arg kFLEXIO_CAMERA_RxErrorFlag
+ */
+void FLEXIO_CAMERA_ClearStatusFlags(FLEXIO_CAMERA_Type *base, uint32_t mask);
+
+/* @} */
+
+/*!
+ * @name Interrupts
+ * @{
+ */
+
+/*!
+ * @brief Switches on the interrupt for receive buffer full event.
+ *
+ * @param base Pointer to the device.
+ */
+void FLEXIO_CAMERA_EnableInterrupt(FLEXIO_CAMERA_Type *base);
+
+/*!
+ * @brief Switches off the interrupt for receive buffer full event.
+ *
+ * @param base Pointer to the device.
+ *
+ */
+void FLEXIO_CAMERA_DisableInterrupt(FLEXIO_CAMERA_Type *base);
+
+/*! @} */
+
+/*!
+ * @name DMA support
+ * @{
+ */
+
+/*!
+ * @brief Enables/disables the FlexIO Camera receive DMA.
+ *
+ * @param base Pointer to FLEXIO_CAMERA_Type structure
+ * @param enable True to enable, false to disable.
+ *
+ *    The FlexIO Camera mode can't work without the DMA or eDMA support,
+ *    Usually, it needs at least two DMA or eDMA channels, one for transferring data from
+ *    Camera, such as 0V7670 to FlexIO buffer, another is for transferring data from FlexIO
+ *    buffer to LCD.
+ *
+ */
+static inline void FLEXIO_CAMERA_EnableRxDMA(FLEXIO_CAMERA_Type *base, bool enable)
+{
+    FLEXIO_EnableShifterStatusDMA(base->flexioBase, 1 << base->shifterStartIdx, enable);
+}
+
+/*!
+ * @brief Gets the data from the receive buffer.
+ *
+ * @param base Pointer to the device.
+ * @return data Pointer to the buffer that keeps the data with count of base->shifterCount .
+ */
+static inline uint32_t FLEXIO_CAMERA_GetRxBufferAddress(FLEXIO_CAMERA_Type *base)
+{
+    return FLEXIO_GetShifterBufferAddress(base->flexioBase, kFLEXIO_ShifterBuffer, base->shifterStartIdx);
+}
+
+/*! @} */
+
+#if defined(__cplusplus)
+}
+#endif /*_cplusplus*/
+
+/*@}*/
+
+#endif /*_FSL_FLEXIO_CAMERA_H_*/
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_camera_edma.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_camera_edma.c
new file mode 100644
index 00000000000..5fb650bb639
--- /dev/null
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_camera_edma.c
@@ -0,0 +1,248 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_flexio_camera_edma.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.flexio_camera_edma"
+#endif
+
+/*<! Structure definition for camera_edma_private_handle_t. The structure is private. */
+typedef struct _flexio_camera_edma_private_handle
+{
+    FLEXIO_CAMERA_Type *base;
+    flexio_camera_edma_handle_t *handle;
+} flexio_camera_edma_private_handle_t;
+
+/* CAMERA EDMA transfer handle. */
+enum _flexio_camera_edma_tansfer_states
+{
+    kFLEXIO_CAMERA_RxIdle, /* RX idle. */
+    kFLEXIO_CAMERA_RxBusy  /* RX busy. */
+};
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*< @brief user configurable flexio camera handle count. */
+#define FLEXIO_CAMERA_HANDLE_COUNT 1
+
+/*<! Private handle only used for internally. */
+static flexio_camera_edma_private_handle_t s_edmaPrivateHandle[FLEXIO_CAMERA_HANDLE_COUNT];
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*!
+ * @brief FLEXIO CAMERA EDMA receive finished callback function.
+ *
+ * This function is called when FLEXIO CAMERA EDMA receive finished. It disables the CAMERA
+ * RX EDMA request and sends @ref kStatus_FLEXIO_CAMERA_RxIdle to CAMERA callback.
+ *
+ * @param handle The EDMA handle.
+ * @param param Callback function parameter.
+ */
+static void FLEXIO_CAMERA_TransferReceiveEDMACallback(edma_handle_t *handle,
+                                                      void *param,
+                                                      bool transferDone,
+                                                      uint32_t tcds);
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+static void FLEXIO_CAMERA_TransferReceiveEDMACallback(edma_handle_t *handle,
+                                                      void *param,
+                                                      bool transferDone,
+                                                      uint32_t tcds)
+{
+    flexio_camera_edma_private_handle_t *cameraPrivateHandle = (flexio_camera_edma_private_handle_t *)param;
+
+    /* Avoid the warning for unused variables. */
+    handle = handle;
+    tcds   = tcds;
+
+    if (transferDone)
+    {
+        FLEXIO_CAMERA_TransferAbortReceiveEDMA(cameraPrivateHandle->base, cameraPrivateHandle->handle);
+
+        if (cameraPrivateHandle->handle->callback)
+        {
+            cameraPrivateHandle->handle->callback(cameraPrivateHandle->base, cameraPrivateHandle->handle,
+                                                  kStatus_FLEXIO_CAMERA_RxIdle, cameraPrivateHandle->handle->userData);
+        }
+    }
+}
+/*!
+ * brief Initializes the Camera handle, which is used in transactional functions.
+ *
+ * param base Pointer to the FLEXIO_CAMERA_Type.
+ * param handle Pointer to flexio_camera_edma_handle_t structure.
+ * param callback The callback function.
+ * param userData The parameter of the callback function.
+ * param rxEdmaHandle User requested DMA handle for RX DMA transfer.
+ * retval kStatus_Success Successfully create the handle.
+ * retval kStatus_OutOfRange The FlexIO Camera eDMA type/handle table out of range.
+ */
+status_t FLEXIO_CAMERA_TransferCreateHandleEDMA(FLEXIO_CAMERA_Type *base,
+                                                flexio_camera_edma_handle_t *handle,
+                                                flexio_camera_edma_transfer_callback_t callback,
+                                                void *userData,
+                                                edma_handle_t *rxEdmaHandle)
+{
+    assert(handle);
+
+    uint8_t index = 0;
+
+    /* Find the an empty handle pointer to store the handle. */
+    for (index = 0; index < FLEXIO_CAMERA_HANDLE_COUNT; index++)
+    {
+        if (s_edmaPrivateHandle[index].base == NULL)
+        {
+            s_edmaPrivateHandle[index].base   = base;
+            s_edmaPrivateHandle[index].handle = handle;
+            break;
+        }
+    }
+
+    if (index == FLEXIO_CAMERA_HANDLE_COUNT)
+    {
+        return kStatus_OutOfRange;
+    }
+
+    s_edmaPrivateHandle[index].base   = base;
+    s_edmaPrivateHandle[index].handle = handle;
+
+    memset(handle, 0, sizeof(*handle));
+
+    handle->rxState      = kFLEXIO_CAMERA_RxIdle;
+    handle->rxEdmaHandle = rxEdmaHandle;
+
+    handle->callback = callback;
+    handle->userData = userData;
+
+    /* Configure RX. */
+    if (rxEdmaHandle)
+    {
+        EDMA_SetCallback(handle->rxEdmaHandle, FLEXIO_CAMERA_TransferReceiveEDMACallback, &s_edmaPrivateHandle);
+    }
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Receives data using eDMA.
+ *
+ * This function receives data using eDMA. This is a non-blocking function, which returns
+ * right away. When all data is received, the receive callback function is called.
+ *
+ * param base Pointer to the FLEXIO_CAMERA_Type.
+ * param handle Pointer to the flexio_camera_edma_handle_t structure.
+ * param xfer Camera eDMA transfer structure, see #flexio_camera_transfer_t.
+ * retval kStatus_Success if succeeded, others failed.
+ * retval kStatus_CAMERA_RxBusy Previous transfer on going.
+ */
+status_t FLEXIO_CAMERA_TransferReceiveEDMA(FLEXIO_CAMERA_Type *base,
+                                           flexio_camera_edma_handle_t *handle,
+                                           flexio_camera_transfer_t *xfer)
+{
+    assert(handle->rxEdmaHandle);
+
+    edma_transfer_config_t xferConfig;
+    status_t status;
+
+    /* If previous RX not finished. */
+    if (kFLEXIO_CAMERA_RxBusy == handle->rxState)
+    {
+        status = kStatus_FLEXIO_CAMERA_RxBusy;
+    }
+    else
+    {
+        handle->rxState = kFLEXIO_CAMERA_RxBusy;
+
+        /* Prepare transfer. */
+        EDMA_PrepareTransfer(&xferConfig, (void *)FLEXIO_CAMERA_GetRxBufferAddress(base), 32, (void *)xfer->dataAddress,
+                             32, 32, xfer->dataNum, kEDMA_PeripheralToMemory);
+
+        /* Store the initially configured eDMA minor byte transfer count into the FLEXIO CAMERA handle */
+        handle->nbytes = 32;
+
+        /* Submit transfer. */
+        EDMA_SubmitTransfer(handle->rxEdmaHandle, &xferConfig);
+        EDMA_StartTransfer(handle->rxEdmaHandle);
+        /* Enable CAMERA RX EDMA. */
+        FLEXIO_CAMERA_EnableRxDMA(base, true);
+        status = kStatus_Success;
+    }
+
+    return status;
+}
+
+/*!
+ * brief Aborts the receive data which used the eDMA.
+ *
+ * This function aborts the receive data which used the eDMA.
+ *
+ * param base Pointer to the FLEXIO_CAMERA_Type.
+ * param handle Pointer to the flexio_camera_edma_handle_t structure.
+ */
+void FLEXIO_CAMERA_TransferAbortReceiveEDMA(FLEXIO_CAMERA_Type *base, flexio_camera_edma_handle_t *handle)
+{
+    assert(handle->rxEdmaHandle);
+
+    /* Disable CAMERA RX EDMA. */
+    FLEXIO_CAMERA_EnableRxDMA(base, false);
+
+    /* Stop transfer. */
+    EDMA_StopTransfer(handle->rxEdmaHandle);
+
+    handle->rxState = kFLEXIO_CAMERA_RxIdle;
+}
+
+/*!
+ * brief Gets the remaining bytes to be received.
+ *
+ * This function gets the number of bytes still not received.
+ *
+ * param base Pointer to the FLEXIO_CAMERA_Type.
+ * param handle Pointer to the flexio_camera_edma_handle_t structure.
+ * param count Number of bytes sent so far by the non-blocking transaction.
+ * retval kStatus_Success Succeed get the transfer count.
+ * retval kStatus_InvalidArgument The count parameter is invalid.
+ */
+status_t FLEXIO_CAMERA_TransferGetReceiveCountEDMA(FLEXIO_CAMERA_Type *base,
+                                                   flexio_camera_edma_handle_t *handle,
+                                                   size_t *count)
+{
+    assert(handle->rxEdmaHandle);
+
+    if (!count)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    if (kFLEXIO_CAMERA_RxBusy == handle->rxState)
+    {
+        *count = (handle->rxSize -
+                  (uint32_t)handle->nbytes *
+                      EDMA_GetRemainingMajorLoopCount(handle->rxEdmaHandle->base, handle->rxEdmaHandle->channel));
+    }
+    else
+    {
+        *count = handle->rxSize;
+    }
+
+    return kStatus_Success;
+}
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_camera_edma.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_camera_edma.h
new file mode 100644
index 00000000000..303eac4048f
--- /dev/null
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_camera_edma.h
@@ -0,0 +1,130 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _FSL_FLEXIO_CAMERA_EDMA_H_
+#define _FSL_FLEXIO_CAMERA_EDMA_H_
+
+#include "fsl_flexio_camera.h"
+#include "fsl_edma.h"
+
+/*!
+ * @addtogroup flexio_edma_camera
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief FlexIO Camera EDMA driver version 2.1.2. */
+#define FSL_FLEXIO_CAMERA_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 1, 2))
+/*@}*/
+
+/*! @brief Forward declaration of the handle typedef. */
+typedef struct _flexio_camera_edma_handle flexio_camera_edma_handle_t;
+
+/*! @brief Camera transfer callback function. */
+typedef void (*flexio_camera_edma_transfer_callback_t)(FLEXIO_CAMERA_Type *base,
+                                                       flexio_camera_edma_handle_t *handle,
+                                                       status_t status,
+                                                       void *userData);
+
+/*!
+ * @brief Camera eDMA handle
+ */
+struct _flexio_camera_edma_handle
+{
+    flexio_camera_edma_transfer_callback_t callback; /*!< Callback function. */
+    void *userData;                                  /*!< Camera callback function parameter.*/
+    size_t rxSize;                                   /*!< Total bytes to be received. */
+    edma_handle_t *rxEdmaHandle;                     /*!< The eDMA RX channel used. */
+    uint8_t nbytes;                                  /*!< eDMA minor byte transfer count initially configured. */
+    volatile uint8_t rxState;                        /*!< RX transfer state */
+};
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name eDMA transactional
+ * @{
+ */
+
+/*!
+ * @brief Initializes the Camera handle, which is used in transactional functions.
+ *
+ * @param base Pointer to the FLEXIO_CAMERA_Type.
+ * @param handle Pointer to flexio_camera_edma_handle_t structure.
+ * @param callback The callback function.
+ * @param userData The parameter of the callback function.
+ * @param rxEdmaHandle User requested DMA handle for RX DMA transfer.
+ * @retval kStatus_Success Successfully create the handle.
+ * @retval kStatus_OutOfRange The FlexIO Camera eDMA type/handle table out of range.
+ */
+status_t FLEXIO_CAMERA_TransferCreateHandleEDMA(FLEXIO_CAMERA_Type *base,
+                                                flexio_camera_edma_handle_t *handle,
+                                                flexio_camera_edma_transfer_callback_t callback,
+                                                void *userData,
+                                                edma_handle_t *rxEdmaHandle);
+
+/*!
+ * @brief Receives data using eDMA.
+ *
+ * This function receives data using eDMA. This is a non-blocking function, which returns
+ * right away. When all data is received, the receive callback function is called.
+ *
+ * @param base Pointer to the FLEXIO_CAMERA_Type.
+ * @param handle Pointer to the flexio_camera_edma_handle_t structure.
+ * @param xfer Camera eDMA transfer structure, see #flexio_camera_transfer_t.
+ * @retval kStatus_Success if succeeded, others failed.
+ * @retval kStatus_CAMERA_RxBusy Previous transfer on going.
+ */
+status_t FLEXIO_CAMERA_TransferReceiveEDMA(FLEXIO_CAMERA_Type *base,
+                                           flexio_camera_edma_handle_t *handle,
+                                           flexio_camera_transfer_t *xfer);
+
+/*!
+ * @brief Aborts the receive data which used the eDMA.
+ *
+ * This function aborts the receive data which used the eDMA.
+ *
+ * @param base Pointer to the FLEXIO_CAMERA_Type.
+ * @param handle Pointer to the flexio_camera_edma_handle_t structure.
+ */
+void FLEXIO_CAMERA_TransferAbortReceiveEDMA(FLEXIO_CAMERA_Type *base, flexio_camera_edma_handle_t *handle);
+
+/*!
+ * @brief Gets the remaining bytes to be received.
+ *
+ * This function gets the number of bytes still not received.
+ *
+ * @param base Pointer to the FLEXIO_CAMERA_Type.
+ * @param handle Pointer to the flexio_camera_edma_handle_t structure.
+ * @param count Number of bytes sent so far by the non-blocking transaction.
+ * @retval kStatus_Success Succeed get the transfer count.
+ * @retval kStatus_InvalidArgument The count parameter is invalid.
+ */
+status_t FLEXIO_CAMERA_TransferGetReceiveCountEDMA(FLEXIO_CAMERA_Type *base,
+                                                   flexio_camera_edma_handle_t *handle,
+                                                   size_t *count);
+
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* _FSL_CAMERA_EDMA_H_ */
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_i2c_master.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_i2c_master.c
index 3d3ca0d6577..a3a237a35c0 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_i2c_master.c
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_i2c_master.c
@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
+ * Copyright 2016-2019 NXP
  * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include "fsl_flexio_i2c_master.h"
@@ -43,16 +17,15 @@
 #define FSL_COMPONENT_ID "platform.drivers.flexio_i2c_master"
 #endif
 
-
 /*! @brief  FLEXIO I2C transfer state */
 enum _flexio_i2c_master_transfer_states
 {
-    kFLEXIO_I2C_Idle = 0x0U,             /*!< I2C bus idle */
-    kFLEXIO_I2C_CheckAddress = 0x1U,     /*!< 7-bit address check state */
-    kFLEXIO_I2C_SendCommand = 0x2U,      /*!< Send command byte phase */
-    kFLEXIO_I2C_SendData = 0x3U,         /*!< Send data transfer phase*/
+    kFLEXIO_I2C_Idle             = 0x0U, /*!< I2C bus idle */
+    kFLEXIO_I2C_CheckAddress     = 0x1U, /*!< 7-bit address check state */
+    kFLEXIO_I2C_SendCommand      = 0x2U, /*!< Send command byte phase */
+    kFLEXIO_I2C_SendData         = 0x3U, /*!< Send data transfer phase*/
     kFLEXIO_I2C_ReceiveDataBegin = 0x4U, /*!< Receive data begin transfer phase*/
-    kFLEXIO_I2C_ReceiveData = 0x5U,      /*!< Receive data transfer phase*/
+    kFLEXIO_I2C_ReceiveData      = 0x5U, /*!< Receive data transfer phase*/
 };
 
 /*******************************************************************************
@@ -112,14 +85,14 @@ static status_t FLEXIO_I2C_MasterTransferInitStateMachine(FLEXIO_I2C_Type *base,
     uint32_t byteCount;
 
     /* Init the handle member. */
-    handle->transfer.slaveAddress = xfer->slaveAddress;
-    handle->transfer.direction = xfer->direction;
-    handle->transfer.subaddress = xfer->subaddress;
+    handle->transfer.slaveAddress   = xfer->slaveAddress;
+    handle->transfer.direction      = xfer->direction;
+    handle->transfer.subaddress     = xfer->subaddress;
     handle->transfer.subaddressSize = xfer->subaddressSize;
-    handle->transfer.data = xfer->data;
-    handle->transfer.dataSize = xfer->dataSize;
-    handle->transfer.flags = xfer->flags;
-    handle->transferSize = xfer->dataSize;
+    handle->transfer.data           = xfer->data;
+    handle->transfer.dataSize       = xfer->dataSize;
+    handle->transfer.flags          = xfer->flags;
+    handle->transferSize            = xfer->dataSize;
 
     /* Initial state, i2c check address state. */
     handle->state = kFLEXIO_I2C_CheckAddress;
@@ -181,7 +154,7 @@ static status_t FLEXIO_I2C_MasterTransferRunStateMachine(FLEXIO_I2C_Type *base,
             (!(((handle->state == kFLEXIO_I2C_ReceiveData) || (handle->state == kFLEXIO_I2C_ReceiveDataBegin)) &&
                (handle->transfer.dataSize == 1U))))
         {
-            FLEXIO_I2C_MasterReadByte(base);
+            (void)FLEXIO_I2C_MasterReadByte(base);
 
             FLEXIO_I2C_MasterAbortStop(base);
 
@@ -207,7 +180,7 @@ static status_t FLEXIO_I2C_MasterTransferRunStateMachine(FLEXIO_I2C_Type *base,
 
     if ((statusFlags & kFLEXIO_I2C_RxFullFlag) && (handle->state != kFLEXIO_I2C_ReceiveData))
     {
-        FLEXIO_I2C_MasterReadByte(base);
+        (void)FLEXIO_I2C_MasterReadByte(base);
     }
 
     switch (handle->state)
@@ -237,17 +210,27 @@ static status_t FLEXIO_I2C_MasterTransferRunStateMachine(FLEXIO_I2C_Type *base,
                 {
                     if (handle->transfer.direction == kFLEXIO_I2C_Write)
                     {
-                        /* Next state, send data. */
-                        handle->state = kFLEXIO_I2C_SendData;
-
                         /* Send first byte of data. */
                         if (handle->transfer.dataSize > 0)
                         {
-                            FLEXIO_I2C_MasterWriteByte(base, *handle->transfer.data);
+                            /* Next state, send data. */
+                            handle->state = kFLEXIO_I2C_SendData;
 
+                            FLEXIO_I2C_MasterWriteByte(base, *handle->transfer.data);
                             handle->transfer.data++;
                             handle->transfer.dataSize--;
                         }
+                        else
+                        {
+                            FLEXIO_I2C_MasterStop(base);
+
+                            while (!(FLEXIO_I2C_MasterGetStatusFlags(base) & kFLEXIO_I2C_RxFullFlag))
+                            {
+                            }
+                            (void)FLEXIO_I2C_MasterReadByte(base);
+
+                            handle->state = kFLEXIO_I2C_Idle;
+                        }
                     }
                     else
                     {
@@ -280,7 +263,7 @@ static status_t FLEXIO_I2C_MasterTransferRunStateMachine(FLEXIO_I2C_Type *base,
                     while (!(FLEXIO_I2C_MasterGetStatusFlags(base) & kFLEXIO_I2C_RxFullFlag))
                     {
                     }
-                    FLEXIO_I2C_MasterReadByte(base);
+                    (void)FLEXIO_I2C_MasterReadByte(base);
 
                     handle->state = kFLEXIO_I2C_Idle;
                 }
@@ -370,6 +353,34 @@ static void FLEXIO_I2C_MasterTransferComplete(FLEXIO_I2C_Type *base,
     }
 }
 
+/*!
+ * brief Ungates the FlexIO clock, resets the FlexIO module, and configures the FlexIO I2C
+ * hardware configuration.
+ *
+ * Example
+   code
+   FLEXIO_I2C_Type base = {
+   .flexioBase = FLEXIO,
+   .SDAPinIndex = 0,
+   .SCLPinIndex = 1,
+   .shifterIndex = {0,1},
+   .timerIndex = {0,1}
+   };
+   flexio_i2c_master_config_t config = {
+   .enableInDoze = false,
+   .enableInDebug = true,
+   .enableFastAccess = false,
+   .baudRate_Bps = 100000
+   };
+   FLEXIO_I2C_MasterInit(base, &config, srcClock_Hz);
+   endcode
+ *
+ * param base Pointer to FLEXIO_I2C_Type structure.
+ * param masterConfig Pointer to flexio_i2c_master_config_t structure.
+ * param srcClock_Hz FlexIO source clock in Hz.
+ * retval kStatus_Success Initialization successful
+ * retval kStatus_InvalidArgument The source clock exceed upper range limitation
+*/
 status_t FLEXIO_I2C_MasterInit(FLEXIO_I2C_Type *base, flexio_i2c_master_config_t *masterConfig, uint32_t srcClock_Hz)
 {
     assert(base && masterConfig);
@@ -377,8 +388,8 @@ status_t FLEXIO_I2C_MasterInit(FLEXIO_I2C_Type *base, flexio_i2c_master_config_t
     flexio_shifter_config_t shifterConfig;
     flexio_timer_config_t timerConfig;
     uint32_t controlVal = 0;
-    uint16_t timerDiv = 0;
-    status_t result = kStatus_Success;
+    uint16_t timerDiv   = 0;
+    status_t result     = kStatus_Success;
 
     memset(&shifterConfig, 0, sizeof(shifterConfig));
     memset(&timerConfig, 0, sizeof(timerConfig));
@@ -390,46 +401,46 @@ status_t FLEXIO_I2C_MasterInit(FLEXIO_I2C_Type *base, flexio_i2c_master_config_t
 
     /* Do hardware configuration. */
     /* 1. Configure the shifter 0 for tx. */
-    shifterConfig.timerSelect = base->timerIndex[1];
+    shifterConfig.timerSelect   = base->timerIndex[1];
     shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive;
-    shifterConfig.pinConfig = kFLEXIO_PinConfigOpenDrainOrBidirection;
-    shifterConfig.pinSelect = base->SDAPinIndex;
-    shifterConfig.pinPolarity = kFLEXIO_PinActiveLow;
-    shifterConfig.shifterMode = kFLEXIO_ShifterModeTransmit;
-    shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin;
-    shifterConfig.shifterStop = kFLEXIO_ShifterStopBitHigh;
-    shifterConfig.shifterStart = kFLEXIO_ShifterStartBitLow;
+    shifterConfig.pinConfig     = kFLEXIO_PinConfigOpenDrainOrBidirection;
+    shifterConfig.pinSelect     = base->SDAPinIndex;
+    shifterConfig.pinPolarity   = kFLEXIO_PinActiveLow;
+    shifterConfig.shifterMode   = kFLEXIO_ShifterModeTransmit;
+    shifterConfig.inputSource   = kFLEXIO_ShifterInputFromPin;
+    shifterConfig.shifterStop   = kFLEXIO_ShifterStopBitHigh;
+    shifterConfig.shifterStart  = kFLEXIO_ShifterStartBitLow;
 
     FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[0], &shifterConfig);
 
     /* 2. Configure the shifter 1 for rx. */
-    shifterConfig.timerSelect = base->timerIndex[1];
+    shifterConfig.timerSelect   = base->timerIndex[1];
     shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnNegitive;
-    shifterConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled;
-    shifterConfig.pinSelect = base->SDAPinIndex;
-    shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh;
-    shifterConfig.shifterMode = kFLEXIO_ShifterModeReceive;
-    shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin;
-    shifterConfig.shifterStop = kFLEXIO_ShifterStopBitLow;
-    shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable;
+    shifterConfig.pinConfig     = kFLEXIO_PinConfigOutputDisabled;
+    shifterConfig.pinSelect     = base->SDAPinIndex;
+    shifterConfig.pinPolarity   = kFLEXIO_PinActiveHigh;
+    shifterConfig.shifterMode   = kFLEXIO_ShifterModeReceive;
+    shifterConfig.inputSource   = kFLEXIO_ShifterInputFromPin;
+    shifterConfig.shifterStop   = kFLEXIO_ShifterStopBitLow;
+    shifterConfig.shifterStart  = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable;
 
     FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[1], &shifterConfig);
 
     /*3. Configure the timer 0 for generating bit clock. */
-    timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->shifterIndex[0]);
+    timerConfig.triggerSelect   = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->shifterIndex[0]);
     timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow;
-    timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal;
-    timerConfig.pinConfig = kFLEXIO_PinConfigOpenDrainOrBidirection;
-    timerConfig.pinSelect = base->SCLPinIndex;
-    timerConfig.pinPolarity = kFLEXIO_PinActiveHigh;
-    timerConfig.timerMode = kFLEXIO_TimerModeDual8BitBaudBit;
-    timerConfig.timerOutput = kFLEXIO_TimerOutputZeroNotAffectedByReset;
-    timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput;
-    timerConfig.timerReset = kFLEXIO_TimerResetOnTimerPinEqualToTimerOutput;
-    timerConfig.timerDisable = kFLEXIO_TimerDisableOnTimerCompare;
-    timerConfig.timerEnable = kFLEXIO_TimerEnableOnTriggerHigh;
-    timerConfig.timerStop = kFLEXIO_TimerStopBitEnableOnTimerDisable;
-    timerConfig.timerStart = kFLEXIO_TimerStartBitEnabled;
+    timerConfig.triggerSource   = kFLEXIO_TimerTriggerSourceInternal;
+    timerConfig.pinConfig       = kFLEXIO_PinConfigOpenDrainOrBidirection;
+    timerConfig.pinSelect       = base->SCLPinIndex;
+    timerConfig.pinPolarity     = kFLEXIO_PinActiveHigh;
+    timerConfig.timerMode       = kFLEXIO_TimerModeDual8BitBaudBit;
+    timerConfig.timerOutput     = kFLEXIO_TimerOutputZeroNotAffectedByReset;
+    timerConfig.timerDecrement  = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput;
+    timerConfig.timerReset      = kFLEXIO_TimerResetOnTimerPinEqualToTimerOutput;
+    timerConfig.timerDisable    = kFLEXIO_TimerDisableOnTimerCompare;
+    timerConfig.timerEnable     = kFLEXIO_TimerEnableOnTriggerHigh;
+    timerConfig.timerStop       = kFLEXIO_TimerStopBitEnableOnTimerDisable;
+    timerConfig.timerStart      = kFLEXIO_TimerStartBitEnabled;
 
     /* Set TIMCMP[7:0] = (baud rate divider / 2) - 1. */
     timerDiv = (srcClock_Hz / masterConfig->baudRate_Bps) / 2 - 1;
@@ -445,20 +456,20 @@ status_t FLEXIO_I2C_MasterInit(FLEXIO_I2C_Type *base, flexio_i2c_master_config_t
     FLEXIO_SetTimerConfig(base->flexioBase, base->timerIndex[0], &timerConfig);
 
     /* 4. Configure the timer 1 for controlling shifters. */
-    timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->shifterIndex[0]);
+    timerConfig.triggerSelect   = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->shifterIndex[0]);
     timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow;
-    timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal;
-    timerConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled;
-    timerConfig.pinSelect = base->SCLPinIndex;
-    timerConfig.pinPolarity = kFLEXIO_PinActiveLow;
-    timerConfig.timerMode = kFLEXIO_TimerModeSingle16Bit;
-    timerConfig.timerOutput = kFLEXIO_TimerOutputOneNotAffectedByReset;
-    timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnPinInputShiftPinInput;
-    timerConfig.timerReset = kFLEXIO_TimerResetNever;
-    timerConfig.timerDisable = kFLEXIO_TimerDisableOnPreTimerDisable;
-    timerConfig.timerEnable = kFLEXIO_TimerEnableOnPrevTimerEnable;
-    timerConfig.timerStop = kFLEXIO_TimerStopBitEnableOnTimerCompare;
-    timerConfig.timerStart = kFLEXIO_TimerStartBitEnabled;
+    timerConfig.triggerSource   = kFLEXIO_TimerTriggerSourceInternal;
+    timerConfig.pinConfig       = kFLEXIO_PinConfigOutputDisabled;
+    timerConfig.pinSelect       = base->SCLPinIndex;
+    timerConfig.pinPolarity     = kFLEXIO_PinActiveLow;
+    timerConfig.timerMode       = kFLEXIO_TimerModeSingle16Bit;
+    timerConfig.timerOutput     = kFLEXIO_TimerOutputOneNotAffectedByReset;
+    timerConfig.timerDecrement  = kFLEXIO_TimerDecSrcOnPinInputShiftPinInput;
+    timerConfig.timerReset      = kFLEXIO_TimerResetNever;
+    timerConfig.timerDisable    = kFLEXIO_TimerDisableOnPreTimerDisable;
+    timerConfig.timerEnable     = kFLEXIO_TimerEnableOnPrevTimerEnable;
+    timerConfig.timerStop       = kFLEXIO_TimerStopBitEnableOnTimerCompare;
+    timerConfig.timerStart      = kFLEXIO_TimerStartBitEnabled;
 
     /* Set TIMCMP[15:0] = (number of bits x 2) - 1. */
     timerConfig.timerCompare = 8 * 2 - 1;
@@ -480,18 +491,24 @@ status_t FLEXIO_I2C_MasterInit(FLEXIO_I2C_Type *base, flexio_i2c_master_config_t
     return result;
 }
 
+/*!
+ * brief De-initializes the FlexIO I2C master peripheral. Calling this API Resets the FlexIO I2C master
+ * shifer and timer config, module can't work unless the FLEXIO_I2C_MasterInit is called.
+ *
+ * param base pointer to FLEXIO_I2C_Type structure.
+ */
 void FLEXIO_I2C_MasterDeinit(FLEXIO_I2C_Type *base)
 {
     base->flexioBase->SHIFTCFG[base->shifterIndex[0]] = 0;
     base->flexioBase->SHIFTCTL[base->shifterIndex[0]] = 0;
     base->flexioBase->SHIFTCFG[base->shifterIndex[1]] = 0;
     base->flexioBase->SHIFTCTL[base->shifterIndex[1]] = 0;
-    base->flexioBase->TIMCFG[base->timerIndex[0]] = 0;
-    base->flexioBase->TIMCMP[base->timerIndex[0]] = 0;
-    base->flexioBase->TIMCTL[base->timerIndex[0]] = 0;
-    base->flexioBase->TIMCFG[base->timerIndex[1]] = 0;
-    base->flexioBase->TIMCMP[base->timerIndex[1]] = 0;
-    base->flexioBase->TIMCTL[base->timerIndex[1]] = 0;
+    base->flexioBase->TIMCFG[base->timerIndex[0]]     = 0;
+    base->flexioBase->TIMCMP[base->timerIndex[0]]     = 0;
+    base->flexioBase->TIMCTL[base->timerIndex[0]]     = 0;
+    base->flexioBase->TIMCFG[base->timerIndex[1]]     = 0;
+    base->flexioBase->TIMCMP[base->timerIndex[1]]     = 0;
+    base->flexioBase->TIMCTL[base->timerIndex[1]]     = 0;
     /* Clear the shifter flag. */
     base->flexioBase->SHIFTSTAT = (1U << base->shifterIndex[0]);
     base->flexioBase->SHIFTSTAT = (1U << base->shifterIndex[1]);
@@ -500,19 +517,40 @@ void FLEXIO_I2C_MasterDeinit(FLEXIO_I2C_Type *base)
     base->flexioBase->TIMSTAT = (1U << base->timerIndex[1]);
 }
 
+/*!
+ * brief Gets the default configuration to configure the FlexIO module. The configuration
+ * can be used directly for calling the FLEXIO_I2C_MasterInit().
+ *
+ * Example:
+   code
+   flexio_i2c_master_config_t config;
+   FLEXIO_I2C_MasterGetDefaultConfig(&config);
+   endcode
+ * param masterConfig Pointer to flexio_i2c_master_config_t structure.
+*/
 void FLEXIO_I2C_MasterGetDefaultConfig(flexio_i2c_master_config_t *masterConfig)
 {
     assert(masterConfig);
 
-    masterConfig->enableMaster = true;
-    masterConfig->enableInDoze = false;
-    masterConfig->enableInDebug = true;
+    /* Initializes the configure structure to zero. */
+    memset(masterConfig, 0, sizeof(*masterConfig));
+
+    masterConfig->enableMaster     = true;
+    masterConfig->enableInDoze     = false;
+    masterConfig->enableInDebug    = true;
     masterConfig->enableFastAccess = false;
 
     /* Default baud rate at 100kbps. */
     masterConfig->baudRate_Bps = 100000U;
 }
 
+/*!
+ * brief Gets the FlexIO I2C master status flags.
+ *
+ * param base Pointer to FLEXIO_I2C_Type structure
+ * return Status flag, use status flag to AND #_flexio_i2c_master_status_flags can get the related status.
+ */
+
 uint32_t FLEXIO_I2C_MasterGetStatusFlags(FLEXIO_I2C_Type *base)
 {
     uint32_t status = 0;
@@ -529,6 +567,16 @@ uint32_t FLEXIO_I2C_MasterGetStatusFlags(FLEXIO_I2C_Type *base)
     return status;
 }
 
+/*!
+ * brief Clears the FlexIO I2C master status flags.
+ *
+ * param base Pointer to FLEXIO_I2C_Type structure.
+ * param mask Status flag.
+ *      The parameter can be any combination of the following values:
+ *          arg kFLEXIO_I2C_RxFullFlag
+ *          arg kFLEXIO_I2C_ReceiveNakFlag
+ */
+
 void FLEXIO_I2C_MasterClearStatusFlags(FLEXIO_I2C_Type *base, uint32_t mask)
 {
     if (mask & kFLEXIO_I2C_TxEmptyFlag)
@@ -547,6 +595,14 @@ void FLEXIO_I2C_MasterClearStatusFlags(FLEXIO_I2C_Type *base, uint32_t mask)
     }
 }
 
+/*!
+ * brief Enables the FlexIO i2c master interrupt requests.
+ *
+ * param base Pointer to FLEXIO_I2C_Type structure.
+ * param mask Interrupt source.
+ *     Currently only one interrupt request source:
+ *     arg kFLEXIO_I2C_TransferCompleteInterruptEnable
+ */
 void FLEXIO_I2C_MasterEnableInterrupts(FLEXIO_I2C_Type *base, uint32_t mask)
 {
     if (mask & kFLEXIO_I2C_TxEmptyInterruptEnable)
@@ -559,6 +615,12 @@ void FLEXIO_I2C_MasterEnableInterrupts(FLEXIO_I2C_Type *base, uint32_t mask)
     }
 }
 
+/*!
+ * brief Disables the FlexIO I2C master interrupt requests.
+ *
+ * param base Pointer to FLEXIO_I2C_Type structure.
+ * param mask Interrupt source.
+ */
 void FLEXIO_I2C_MasterDisableInterrupts(FLEXIO_I2C_Type *base, uint32_t mask)
 {
     if (mask & kFLEXIO_I2C_TxEmptyInterruptEnable)
@@ -571,10 +633,17 @@ void FLEXIO_I2C_MasterDisableInterrupts(FLEXIO_I2C_Type *base, uint32_t mask)
     }
 }
 
+/*!
+ * brief Sets the FlexIO I2C master transfer baudrate.
+ *
+ * param base Pointer to FLEXIO_I2C_Type structure
+ * param baudRate_Bps the baud rate value in HZ
+ * param srcClock_Hz source clock in HZ
+ */
 void FLEXIO_I2C_MasterSetBaudRate(FLEXIO_I2C_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz)
 {
-    uint16_t timerDiv = 0;
-    uint16_t timerCmp = 0;
+    uint16_t timerDiv       = 0;
+    uint16_t timerCmp       = 0;
     FLEXIO_Type *flexioBase = base->flexioBase;
 
     /* Set TIMCMP[7:0] = (baud rate divider / 2) - 1.*/
@@ -588,6 +657,17 @@ void FLEXIO_I2C_MasterSetBaudRate(FLEXIO_I2C_Type *base, uint32_t baudRate_Bps,
     flexioBase->TIMCMP[base->timerIndex[0]] = timerCmp;
 }
 
+/*!
+ * brief Sets the number of bytes to be transferred from a start signal to a stop signal.
+ *
+ * note Call this API before a transfer begins because the timer generates a number of clocks according
+ * to the number of bytes that need to be transferred.
+ *
+ * param base Pointer to FLEXIO_I2C_Type structure.
+ * param count Number of bytes need to be transferred from a start signal to a re-start/stop signal
+ * retval kStatus_Success Successfully configured the count.
+ * retval kStatus_InvalidArgument Input argument is invalid.
+ */
 status_t FLEXIO_I2C_MasterSetTransferCount(FLEXIO_I2C_Type *base, uint8_t count)
 {
     if (count > 14U)
@@ -595,15 +675,15 @@ status_t FLEXIO_I2C_MasterSetTransferCount(FLEXIO_I2C_Type *base, uint8_t count)
         return kStatus_InvalidArgument;
     }
 
-    uint16_t timerCmp = 0;
-    uint32_t timerConfig = 0;
+    uint16_t timerCmp       = 0;
+    uint32_t timerConfig    = 0;
     FLEXIO_Type *flexioBase = base->flexioBase;
 
     timerCmp = flexioBase->TIMCMP[base->timerIndex[0]];
     timerCmp &= 0x00FFU;
     timerCmp |= (count * 18 + 1U) << 8U;
     flexioBase->TIMCMP[base->timerIndex[0]] = timerCmp;
-    timerConfig = flexioBase->TIMCFG[base->timerIndex[0]];
+    timerConfig                             = flexioBase->TIMCFG[base->timerIndex[0]];
     timerConfig &= ~FLEXIO_TIMCFG_TIMDIS_MASK;
     timerConfig |= FLEXIO_TIMCFG_TIMDIS(kFLEXIO_TimerDisableOnTimerCompare);
     flexioBase->TIMCFG[base->timerIndex[0]] = timerConfig;
@@ -611,6 +691,21 @@ status_t FLEXIO_I2C_MasterSetTransferCount(FLEXIO_I2C_Type *base, uint8_t count)
     return kStatus_Success;
 }
 
+/*!
+ * brief Sends START + 7-bit address to the bus.
+ *
+ * note This API should be called when the transfer configuration is ready to send a START signal
+ * and 7-bit address to the bus. This is a non-blocking API, which returns directly after the address
+ * is put into the data register but the address transfer is not finished on the bus. Ensure that
+ * the kFLEXIO_I2C_RxFullFlag status is asserted before calling this API.
+ * param base Pointer to FLEXIO_I2C_Type structure.
+ * param address 7-bit address.
+ * param direction transfer direction.
+ *     This parameter is one of the values in flexio_i2c_direction_t:
+ *        arg kFLEXIO_I2C_Write: Transmit
+ *        arg kFLEXIO_I2C_Read:  Receive
+ */
+
 void FLEXIO_I2C_MasterStart(FLEXIO_I2C_Type *base, uint8_t address, flexio_i2c_direction_t direction)
 {
     uint32_t data;
@@ -620,12 +715,22 @@ void FLEXIO_I2C_MasterStart(FLEXIO_I2C_Type *base, uint8_t address, flexio_i2c_d
     FLEXIO_I2C_MasterWriteByte(base, data);
 }
 
+/*!
+ * brief Sends the repeated start signal on the bus.
+ *
+ * param base Pointer to FLEXIO_I2C_Type structure.
+ */
 void FLEXIO_I2C_MasterRepeatedStart(FLEXIO_I2C_Type *base)
 {
     /* Prepare for RESTART condition, no stop.*/
     FLEXIO_I2C_MasterWriteByte(base, 0xFFFFFFFFU);
 }
 
+/*!
+ * brief Sends the stop signal on the bus.
+ *
+ * param base Pointer to FLEXIO_I2C_Type structure.
+ */
 void FLEXIO_I2C_MasterStop(FLEXIO_I2C_Type *base)
 {
     /* Prepare normal stop. */
@@ -633,6 +738,11 @@ void FLEXIO_I2C_MasterStop(FLEXIO_I2C_Type *base)
     FLEXIO_I2C_MasterWriteByte(base, 0x0U);
 }
 
+/*!
+ * brief Sends the stop signal when transfer is still on-going.
+ *
+ * param base Pointer to FLEXIO_I2C_Type structure.
+ */
 void FLEXIO_I2C_MasterAbortStop(FLEXIO_I2C_Type *base)
 {
     uint32_t tmpConfig;
@@ -644,6 +754,12 @@ void FLEXIO_I2C_MasterAbortStop(FLEXIO_I2C_Type *base)
     base->flexioBase->TIMCFG[base->timerIndex[0]] = tmpConfig;
 }
 
+/*!
+ * brief Configures the sent ACK/NAK for the following byte.
+ *
+ * param base Pointer to FLEXIO_I2C_Type structure.
+ * param enable True to configure send ACK, false configure to send NAK.
+ */
 void FLEXIO_I2C_MasterEnableAck(FLEXIO_I2C_Type *base, bool enable)
 {
     uint32_t tmpConfig = 0;
@@ -661,6 +777,17 @@ void FLEXIO_I2C_MasterEnableAck(FLEXIO_I2C_Type *base, bool enable)
     base->flexioBase->SHIFTCFG[base->shifterIndex[0]] = tmpConfig;
 }
 
+/*!
+ * brief Sends a buffer of data in bytes.
+ *
+ * note This function blocks via polling until all bytes have been sent.
+ *
+ * param base Pointer to FLEXIO_I2C_Type structure.
+ * param txBuff The data bytes to send.
+ * param txSize The number of data bytes to send.
+ * retval kStatus_Success Successfully write data.
+ * retval kStatus_FLEXIO_I2C_Nak Receive NAK during writing data.
+ */
 status_t FLEXIO_I2C_MasterWriteBlocking(FLEXIO_I2C_Type *base, const uint8_t *txBuff, uint8_t txSize)
 {
     assert(txBuff);
@@ -686,6 +813,15 @@ status_t FLEXIO_I2C_MasterWriteBlocking(FLEXIO_I2C_Type *base, const uint8_t *tx
     return kStatus_Success;
 }
 
+/*!
+ * brief Receives a buffer of bytes.
+ *
+ * note This function blocks via polling until all bytes have been received.
+ *
+ * param base Pointer to FLEXIO_I2C_Type structure.
+ * param rxBuff The buffer to store the received bytes.
+ * param rxSize The number of data bytes to be received.
+ */
 void FLEXIO_I2C_MasterReadBlocking(FLEXIO_I2C_Type *base, uint8_t *rxBuff, uint8_t rxSize)
 {
     assert(rxBuff);
@@ -702,6 +838,16 @@ void FLEXIO_I2C_MasterReadBlocking(FLEXIO_I2C_Type *base, uint8_t *rxBuff, uint8
     }
 }
 
+/*!
+ * brief Performs a master polling transfer on the I2C bus.
+ *
+ * note The API does not return until the transfer succeeds or fails due
+ * to receiving NAK.
+ *
+ * param base pointer to FLEXIO_I2C_Type structure.
+ * param xfer pointer to flexio_i2c_master_transfer_t structure.
+ * return status of status_t.
+ */
 status_t FLEXIO_I2C_MasterTransferBlocking(FLEXIO_I2C_Type *base, flexio_i2c_master_transfer_t *xfer)
 {
     assert(xfer);
@@ -723,14 +869,29 @@ status_t FLEXIO_I2C_MasterTransferBlocking(FLEXIO_I2C_Type *base, flexio_i2c_mas
                  (kFLEXIO_I2C_TxEmptyFlag | kFLEXIO_I2C_RxFullFlag)))
         {
         }
-
+        FLEXIO_ClearTimerStatusFlags(base->flexioBase, ((1 << base->timerIndex[0]) | (1 << base->timerIndex[1])));
         result = FLEXIO_I2C_MasterTransferRunStateMachine(base, &tmpHandle, statusFlags);
 
     } while ((tmpHandle.state != kFLEXIO_I2C_Idle) && (result == kStatus_Success));
 
+    /* Timer disable on timer compare, wait until bit clock TSF set, which means timer disable and stop has been sent. */
+    while(0U == (FLEXIO_GetTimerStatusFlags(base->flexioBase) & (1 << base->timerIndex[0])))
+    {
+    }
+
     return result;
 }
 
+/*!
+ * brief Initializes the I2C handle which is used in transactional functions.
+ *
+ * param base Pointer to FLEXIO_I2C_Type structure.
+ * param handle Pointer to flexio_i2c_master_handle_t structure to store the transfer state.
+ * param callback Pointer to user callback function.
+ * param userData User param passed to the callback function.
+ * retval kStatus_Success Successfully create the handle.
+ * retval kStatus_OutOfRange The FlexIO type/handle/isr table out of range.
+ */
 status_t FLEXIO_I2C_MasterTransferCreateHandle(FLEXIO_I2C_Type *base,
                                                flexio_i2c_master_handle_t *handle,
                                                flexio_i2c_master_transfer_callback_t callback,
@@ -745,7 +906,7 @@ status_t FLEXIO_I2C_MasterTransferCreateHandle(FLEXIO_I2C_Type *base,
 
     /* Register callback and userData. */
     handle->completionCallback = callback;
-    handle->userData = userData;
+    handle->userData           = userData;
 
     /* Enable interrupt in NVIC. */
     EnableIRQ(flexio_irqs[FLEXIO_I2C_GetInstance(base)]);
@@ -754,6 +915,20 @@ status_t FLEXIO_I2C_MasterTransferCreateHandle(FLEXIO_I2C_Type *base,
     return FLEXIO_RegisterHandleIRQ(base, handle, FLEXIO_I2C_MasterTransferHandleIRQ);
 }
 
+/*!
+ * brief Performs a master interrupt non-blocking transfer on the I2C bus.
+ *
+ * note The API returns immediately after the transfer initiates.
+ * Call FLEXIO_I2C_MasterGetTransferCount to poll the transfer status to check whether
+ * the transfer is finished. If the return status is not kStatus_FLEXIO_I2C_Busy, the transfer
+ * is finished.
+ *
+ * param base Pointer to FLEXIO_I2C_Type structure
+ * param handle Pointer to flexio_i2c_master_handle_t structure which stores the transfer state
+ * param xfer pointer to flexio_i2c_master_transfer_t structure
+ * retval kStatus_Success Successfully start a transfer.
+ * retval kStatus_FLEXIO_I2C_Busy FlexIO I2C is not idle, is running another transfer.
+ */
 status_t FLEXIO_I2C_MasterTransferNonBlocking(FLEXIO_I2C_Type *base,
                                               flexio_i2c_master_handle_t *handle,
                                               flexio_i2c_master_transfer_t *xfer)
@@ -777,6 +952,15 @@ status_t FLEXIO_I2C_MasterTransferNonBlocking(FLEXIO_I2C_Type *base,
     }
 }
 
+/*!
+ * brief Aborts an interrupt non-blocking transfer early.
+ *
+ * note This API can be called at any time when an interrupt non-blocking transfer initiates
+ * to abort the transfer early.
+ *
+ * param base Pointer to FLEXIO_I2C_Type structure
+ * param handle Pointer to flexio_i2c_master_handle_t structure which stores the transfer state
+ */
 void FLEXIO_I2C_MasterTransferAbort(FLEXIO_I2C_Type *base, flexio_i2c_master_handle_t *handle)
 {
     assert(handle);
@@ -788,6 +972,15 @@ void FLEXIO_I2C_MasterTransferAbort(FLEXIO_I2C_Type *base, flexio_i2c_master_han
     handle->state = kFLEXIO_I2C_Idle;
 }
 
+/*!
+ * brief Gets the master transfer status during a interrupt non-blocking transfer.
+ *
+ * param base Pointer to FLEXIO_I2C_Type structure.
+ * param handle Pointer to flexio_i2c_master_handle_t structure which stores the transfer state.
+ * param count Number of bytes transferred so far by the non-blocking transaction.
+ * retval kStatus_InvalidArgument count is Invalid.
+ * retval kStatus_Success Successfully return the count.
+ */
 status_t FLEXIO_I2C_MasterTransferGetCount(FLEXIO_I2C_Type *base, flexio_i2c_master_handle_t *handle, size_t *count)
 {
     if (!count)
@@ -800,9 +993,15 @@ status_t FLEXIO_I2C_MasterTransferGetCount(FLEXIO_I2C_Type *base, flexio_i2c_mas
     return kStatus_Success;
 }
 
+/*!
+ * brief Master interrupt handler.
+ *
+ * param i2cType Pointer to FLEXIO_I2C_Type structure
+ * param i2cHandle Pointer to flexio_i2c_master_transfer_t structure
+ */
 void FLEXIO_I2C_MasterTransferHandleIRQ(void *i2cType, void *i2cHandle)
 {
-    FLEXIO_I2C_Type *base = (FLEXIO_I2C_Type *)i2cType;
+    FLEXIO_I2C_Type *base              = (FLEXIO_I2C_Type *)i2cType;
     flexio_i2c_master_handle_t *handle = (flexio_i2c_master_handle_t *)i2cHandle;
     uint32_t statusFlags;
     status_t result;
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_i2c_master.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_i2c_master.h
index 5e6ee2b9bfb..c55d476a80d 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_i2c_master.h
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_i2c_master.h
@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
+ * Copyright 2016-2019 NXP
  * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 #ifndef _FSL_FLEXIO_I2C_MASTER_H_
 #define _FSL_FLEXIO_I2C_MASTER_H_
@@ -48,8 +22,8 @@
 
 /*! @name Driver version */
 /*@{*/
-/*! @brief FlexIO I2C master driver version 2.1.5. */
-#define FSL_FLEXIO_I2C_MASTER_DRIVER_VERSION (MAKE_VERSION(2, 1, 5))
+/*! @brief FlexIO I2C master driver version 2.1.7. */
+#define FSL_FLEXIO_I2C_MASTER_DRIVER_VERSION (MAKE_VERSION(2, 1, 7))
 /*@}*/
 
 /*! @brief  FlexIO I2C transfer status*/
@@ -57,21 +31,21 @@ enum _flexio_i2c_status
 {
     kStatus_FLEXIO_I2C_Busy = MAKE_STATUS(kStatusGroup_FLEXIO_I2C, 0), /*!< I2C is busy doing transfer. */
     kStatus_FLEXIO_I2C_Idle = MAKE_STATUS(kStatusGroup_FLEXIO_I2C, 1), /*!< I2C is busy doing transfer. */
-    kStatus_FLEXIO_I2C_Nak = MAKE_STATUS(kStatusGroup_FLEXIO_I2C, 2),  /*!< NAK received during transfer. */
+    kStatus_FLEXIO_I2C_Nak  = MAKE_STATUS(kStatusGroup_FLEXIO_I2C, 2), /*!< NAK received during transfer. */
 };
 
 /*! @brief Define FlexIO I2C master interrupt mask. */
 enum _flexio_i2c_master_interrupt
 {
     kFLEXIO_I2C_TxEmptyInterruptEnable = 0x1U, /*!< Tx buffer empty interrupt enable. */
-    kFLEXIO_I2C_RxFullInterruptEnable = 0x2U,  /*!< Rx buffer full interrupt enable. */
+    kFLEXIO_I2C_RxFullInterruptEnable  = 0x2U, /*!< Rx buffer full interrupt enable. */
 };
 
 /*! @brief Define FlexIO I2C master status mask. */
 enum _flexio_i2c_master_status_flags
 {
-    kFLEXIO_I2C_TxEmptyFlag = 0x1U,    /*!< Tx shifter empty flag. */
-    kFLEXIO_I2C_RxFullFlag = 0x2U,     /*!< Rx shifter full/Transfer complete flag. */
+    kFLEXIO_I2C_TxEmptyFlag    = 0x1U, /*!< Tx shifter empty flag. */
+    kFLEXIO_I2C_RxFullFlag     = 0x2U, /*!< Rx shifter full/Transfer complete flag. */
     kFLEXIO_I2C_ReceiveNakFlag = 0x4U, /*!< Receive NAK flag. */
 };
 
@@ -79,7 +53,7 @@ enum _flexio_i2c_master_status_flags
 typedef enum _flexio_i2c_direction
 {
     kFLEXIO_I2C_Write = 0x0U, /*!< Master send to slave. */
-    kFLEXIO_I2C_Read = 0x1U,  /*!< Master receive from slave. */
+    kFLEXIO_I2C_Read  = 0x1U, /*!< Master receive from slave. */
 } flexio_i2c_direction_t;
 
 /*! @brief Define FlexIO I2C master access structure typedef. */
@@ -204,7 +178,7 @@ void FLEXIO_I2C_MasterGetDefaultConfig(flexio_i2c_master_config_t *masterConfig)
  *
  * @param base Pointer to FLEXIO_I2C_Type structure.
  * @param enable Pass true to enable module, false does not have any effect.
-*/
+ */
 static inline void FLEXIO_I2C_MasterEnable(FLEXIO_I2C_Type *base, bool enable)
 {
     if (enable)
@@ -225,7 +199,7 @@ static inline void FLEXIO_I2C_MasterEnable(FLEXIO_I2C_Type *base, bool enable)
  *
  * @param base Pointer to FLEXIO_I2C_Type structure
  * @return Status flag, use status flag to AND #_flexio_i2c_master_status_flags can get the related status.
-*/
+ */
 
 uint32_t FLEXIO_I2C_MasterGetStatusFlags(FLEXIO_I2C_Type *base);
 
@@ -237,7 +211,7 @@ uint32_t FLEXIO_I2C_MasterGetStatusFlags(FLEXIO_I2C_Type *base);
  *      The parameter can be any combination of the following values:
  *          @arg kFLEXIO_I2C_RxFullFlag
  *          @arg kFLEXIO_I2C_ReceiveNakFlag
-*/
+ */
 
 void FLEXIO_I2C_MasterClearStatusFlags(FLEXIO_I2C_Type *base, uint32_t mask);
 
@@ -338,7 +312,7 @@ void FLEXIO_I2C_MasterEnableAck(FLEXIO_I2C_Type *base, bool enable);
  * @param count Number of bytes need to be transferred from a start signal to a re-start/stop signal
  * @retval kStatus_Success Successfully configured the count.
  * @retval kStatus_InvalidArgument Input argument is invalid.
-*/
+ */
 status_t FLEXIO_I2C_MasterSetTransferCount(FLEXIO_I2C_Type *base, uint8_t count);
 
 /*!
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_i2s.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_i2s.c
index 5e7bc437736..acf2ea32a76 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_i2s.c
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_i2s.c
@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
+ * Copyright 2016-2018 NXP
  * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include "fsl_flexio_i2s.h"
@@ -39,10 +13,9 @@
 #define FSL_COMPONENT_ID "platform.drivers.flexio_i2s"
 #endif
 
-
 /*******************************************************************************
-* Definitations
-******************************************************************************/
+ * Definitations
+ ******************************************************************************/
 enum _sai_transfer_state
 {
     kFLEXIO_I2S_Busy = 0x0U, /*!< FLEXIO_I2S is busy */
@@ -87,11 +60,11 @@ static uint32_t FLEXIO_I2S_GetInstance(FLEXIO_I2S_Type *base)
 
 static void FLEXIO_I2S_WriteNonBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth, uint8_t *txData, size_t size)
 {
-    uint32_t i = 0;
-    uint8_t j = 0;
+    uint32_t i           = 0;
+    uint8_t j            = 0;
     uint8_t bytesPerWord = bitWidth / 8U;
-    uint32_t data = 0;
-    uint32_t temp = 0;
+    uint32_t data        = 0;
+    uint32_t temp        = 0;
 
     for (i = 0; i < size / bytesPerWord; i++)
     {
@@ -101,21 +74,21 @@ static void FLEXIO_I2S_WriteNonBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth,
             data |= (temp << (8U * j));
             txData++;
         }
-        base->flexioBase->SHIFTBUFBIS[base->txShifterIndex] = (data << (32U - bitWidth));
-        data = 0;
+        base->flexioBase->SHIFTBUFBIS[base->txShifterIndex] = data << (32U - bitWidth);
+        data                                                = 0;
     }
 }
 
 static void FLEXIO_I2S_ReadNonBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth, uint8_t *rxData, size_t size)
 {
-    uint32_t i = 0;
-    uint8_t j = 0;
+    uint32_t i           = 0;
+    uint8_t j            = 0;
     uint8_t bytesPerWord = bitWidth / 8U;
-    uint32_t data = 0;
+    uint32_t data        = 0;
 
     for (i = 0; i < size / bytesPerWord; i++)
     {
-        data = (base->flexioBase->SHIFTBUFBIS[base->rxShifterIndex] >> (32U - bitWidth));
+        data = (base->flexioBase->SHIFTBUFBIS[base->rxShifterIndex]);
         for (j = 0; j < bytesPerWord; j++)
         {
             *rxData = (data >> (8U * j)) & 0xFF;
@@ -124,27 +97,44 @@ static void FLEXIO_I2S_ReadNonBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth,
     }
 }
 
+/*!
+ * brief Initializes the FlexIO I2S.
+ *
+ * This API configures FlexIO pins and shifter to I2S and configures the FlexIO I2S with a configuration structure.
+ * The configuration structure can be filled by the user, or be set with default values by
+ * FLEXIO_I2S_GetDefaultConfig().
+ *
+ * note  This API should be called at the beginning of the application to use
+ * the FlexIO I2S driver. Otherwise, any access to the FlexIO I2S module can cause hard fault
+ * because the clock is not enabled.
+ *
+ * param base FlexIO I2S base pointer
+ * param config FlexIO I2S configure structure.
+ */
 void FLEXIO_I2S_Init(FLEXIO_I2S_Type *base, const flexio_i2s_config_t *config)
 {
     assert(base && config);
 
     flexio_shifter_config_t shifterConfig = {0};
-    flexio_timer_config_t timerConfig = {0};
+    flexio_timer_config_t timerConfig     = {0};
 
 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* Ungate flexio clock. */
     CLOCK_EnableClock(s_flexioClocks[FLEXIO_I2S_GetInstance(base)]);
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
+    /* reset Flexio */
+    FLEXIO_Reset(base->flexioBase);
+
     /* Set shifter for I2S Tx data */
-    shifterConfig.timerSelect = base->bclkTimerIndex;
-    shifterConfig.pinSelect = base->txPinIndex;
+    shifterConfig.timerSelect   = base->bclkTimerIndex;
+    shifterConfig.pinSelect     = base->txPinIndex;
     shifterConfig.timerPolarity = config->txTimerPolarity;
-    shifterConfig.pinConfig = kFLEXIO_PinConfigOutput;
-    shifterConfig.pinPolarity = config->txPinPolarity;
-    shifterConfig.shifterMode = kFLEXIO_ShifterModeTransmit;
-    shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin;
-    shifterConfig.shifterStop = kFLEXIO_ShifterStopBitDisable;
+    shifterConfig.pinConfig     = kFLEXIO_PinConfigOutput;
+    shifterConfig.pinPolarity   = config->txPinPolarity;
+    shifterConfig.shifterMode   = kFLEXIO_ShifterModeTransmit;
+    shifterConfig.inputSource   = kFLEXIO_ShifterInputFromPin;
+    shifterConfig.shifterStop   = kFLEXIO_ShifterStopBitDisable;
     if (config->masterSlave == kFLEXIO_I2S_Master)
     {
         shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnShift;
@@ -157,89 +147,89 @@ void FLEXIO_I2S_Init(FLEXIO_I2S_Type *base, const flexio_i2s_config_t *config)
     FLEXIO_SetShifterConfig(base->flexioBase, base->txShifterIndex, &shifterConfig);
 
     /* Set shifter for I2S Rx Data */
-    shifterConfig.timerSelect = base->bclkTimerIndex;
-    shifterConfig.pinSelect = base->rxPinIndex;
+    shifterConfig.timerSelect   = base->bclkTimerIndex;
+    shifterConfig.pinSelect     = base->rxPinIndex;
     shifterConfig.timerPolarity = config->rxTimerPolarity;
-    shifterConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled;
-    shifterConfig.pinPolarity = config->rxPinPolarity;
-    shifterConfig.shifterMode = kFLEXIO_ShifterModeReceive;
-    shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin;
-    shifterConfig.shifterStop = kFLEXIO_ShifterStopBitDisable;
-    shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable;
+    shifterConfig.pinConfig     = kFLEXIO_PinConfigOutputDisabled;
+    shifterConfig.pinPolarity   = config->rxPinPolarity;
+    shifterConfig.shifterMode   = kFLEXIO_ShifterModeReceive;
+    shifterConfig.inputSource   = kFLEXIO_ShifterInputFromPin;
+    shifterConfig.shifterStop   = kFLEXIO_ShifterStopBitDisable;
+    shifterConfig.shifterStart  = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable;
 
     FLEXIO_SetShifterConfig(base->flexioBase, base->rxShifterIndex, &shifterConfig);
 
     /* Set Timer to I2S frame sync */
     if (config->masterSlave == kFLEXIO_I2S_Master)
     {
-        timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_PININPUT(base->txPinIndex);
+        timerConfig.triggerSelect   = FLEXIO_TIMER_TRIGGER_SEL_PININPUT(base->txPinIndex);
         timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveHigh;
-        timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceExternal;
-        timerConfig.pinConfig = kFLEXIO_PinConfigOutput;
-        timerConfig.pinSelect = base->fsPinIndex;
-        timerConfig.pinPolarity = config->fsPinPolarity;
-        timerConfig.timerMode = kFLEXIO_TimerModeSingle16Bit;
-        timerConfig.timerOutput = kFLEXIO_TimerOutputOneNotAffectedByReset;
-        timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput;
-        timerConfig.timerReset = kFLEXIO_TimerResetNever;
-        timerConfig.timerDisable = kFLEXIO_TimerDisableNever;
-        timerConfig.timerEnable = kFLEXIO_TimerEnableOnPrevTimerEnable;
-        timerConfig.timerStart = kFLEXIO_TimerStartBitDisabled;
-        timerConfig.timerStop = kFLEXIO_TimerStopBitDisabled;
+        timerConfig.triggerSource   = kFLEXIO_TimerTriggerSourceExternal;
+        timerConfig.pinConfig       = kFLEXIO_PinConfigOutput;
+        timerConfig.pinSelect       = base->fsPinIndex;
+        timerConfig.pinPolarity     = config->fsPinPolarity;
+        timerConfig.timerMode       = kFLEXIO_TimerModeSingle16Bit;
+        timerConfig.timerOutput     = kFLEXIO_TimerOutputOneNotAffectedByReset;
+        timerConfig.timerDecrement  = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput;
+        timerConfig.timerReset      = kFLEXIO_TimerResetNever;
+        timerConfig.timerDisable    = kFLEXIO_TimerDisableNever;
+        timerConfig.timerEnable     = kFLEXIO_TimerEnableOnPrevTimerEnable;
+        timerConfig.timerStart      = kFLEXIO_TimerStartBitDisabled;
+        timerConfig.timerStop       = kFLEXIO_TimerStopBitDisabled;
     }
     else
     {
-        timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_PININPUT(base->bclkPinIndex);
+        timerConfig.triggerSelect   = FLEXIO_TIMER_TRIGGER_SEL_PININPUT(base->bclkPinIndex);
         timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveHigh;
-        timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal;
-        timerConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled;
-        timerConfig.pinSelect = base->fsPinIndex;
-        timerConfig.pinPolarity = config->fsPinPolarity;
-        timerConfig.timerMode = kFLEXIO_TimerModeSingle16Bit;
-        timerConfig.timerOutput = kFLEXIO_TimerOutputOneNotAffectedByReset;
-        timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnTriggerInputShiftTriggerInput;
-        timerConfig.timerReset = kFLEXIO_TimerResetNever;
-        timerConfig.timerDisable = kFLEXIO_TimerDisableOnTimerCompare;
-        timerConfig.timerEnable = kFLEXIO_TimerEnableOnPinRisingEdge;
-        timerConfig.timerStart = kFLEXIO_TimerStartBitDisabled;
-        timerConfig.timerStop = kFLEXIO_TimerStopBitDisabled;
+        timerConfig.triggerSource   = kFLEXIO_TimerTriggerSourceInternal;
+        timerConfig.pinConfig       = kFLEXIO_PinConfigOutputDisabled;
+        timerConfig.pinSelect       = base->fsPinIndex;
+        timerConfig.pinPolarity     = config->fsPinPolarity;
+        timerConfig.timerMode       = kFLEXIO_TimerModeSingle16Bit;
+        timerConfig.timerOutput     = kFLEXIO_TimerOutputOneNotAffectedByReset;
+        timerConfig.timerDecrement  = kFLEXIO_TimerDecSrcOnTriggerInputShiftTriggerInput;
+        timerConfig.timerReset      = kFLEXIO_TimerResetNever;
+        timerConfig.timerDisable    = kFLEXIO_TimerDisableOnTimerCompare;
+        timerConfig.timerEnable     = kFLEXIO_TimerEnableOnPinRisingEdge;
+        timerConfig.timerStart      = kFLEXIO_TimerStartBitDisabled;
+        timerConfig.timerStop       = kFLEXIO_TimerStopBitDisabled;
     }
     FLEXIO_SetTimerConfig(base->flexioBase, base->fsTimerIndex, &timerConfig);
 
     /* Set Timer to I2S bit clock */
     if (config->masterSlave == kFLEXIO_I2S_Master)
     {
-        timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->txShifterIndex);
+        timerConfig.triggerSelect   = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->txShifterIndex);
         timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow;
-        timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal;
-        timerConfig.pinSelect = base->bclkPinIndex;
-        timerConfig.pinConfig = kFLEXIO_PinConfigOutput;
-        timerConfig.pinPolarity = config->bclkPinPolarity;
-        timerConfig.timerMode = kFLEXIO_TimerModeDual8BitBaudBit;
-        timerConfig.timerOutput = kFLEXIO_TimerOutputOneNotAffectedByReset;
-        timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput;
-        timerConfig.timerReset = kFLEXIO_TimerResetNever;
-        timerConfig.timerDisable = kFLEXIO_TimerDisableNever;
-        timerConfig.timerEnable = kFLEXIO_TimerEnableOnTriggerHigh;
-        timerConfig.timerStart = kFLEXIO_TimerStartBitEnabled;
-        timerConfig.timerStop = kFLEXIO_TimerStopBitDisabled;
+        timerConfig.triggerSource   = kFLEXIO_TimerTriggerSourceInternal;
+        timerConfig.pinSelect       = base->bclkPinIndex;
+        timerConfig.pinConfig       = kFLEXIO_PinConfigOutput;
+        timerConfig.pinPolarity     = config->bclkPinPolarity;
+        timerConfig.timerMode       = kFLEXIO_TimerModeDual8BitBaudBit;
+        timerConfig.timerOutput     = kFLEXIO_TimerOutputOneNotAffectedByReset;
+        timerConfig.timerDecrement  = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput;
+        timerConfig.timerReset      = kFLEXIO_TimerResetNever;
+        timerConfig.timerDisable    = kFLEXIO_TimerDisableNever;
+        timerConfig.timerEnable     = kFLEXIO_TimerEnableOnTriggerHigh;
+        timerConfig.timerStart      = kFLEXIO_TimerStartBitEnabled;
+        timerConfig.timerStop       = kFLEXIO_TimerStopBitDisabled;
     }
     else
     {
-        timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_TIMn(base->fsTimerIndex);
+        timerConfig.triggerSelect   = FLEXIO_TIMER_TRIGGER_SEL_TIMn(base->fsTimerIndex);
         timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveHigh;
-        timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal;
-        timerConfig.pinSelect = base->bclkPinIndex;
-        timerConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled;
-        timerConfig.pinPolarity = config->bclkPinPolarity;
-        timerConfig.timerMode = kFLEXIO_TimerModeSingle16Bit;
-        timerConfig.timerOutput = kFLEXIO_TimerOutputOneNotAffectedByReset;
-        timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnPinInputShiftPinInput;
-        timerConfig.timerReset = kFLEXIO_TimerResetNever;
-        timerConfig.timerDisable = kFLEXIO_TimerDisableOnTimerCompareTriggerLow;
-        timerConfig.timerEnable = kFLEXIO_TimerEnableOnPinRisingEdgeTriggerHigh;
-        timerConfig.timerStart = kFLEXIO_TimerStartBitDisabled;
-        timerConfig.timerStop = kFLEXIO_TimerStopBitDisabled;
+        timerConfig.triggerSource   = kFLEXIO_TimerTriggerSourceInternal;
+        timerConfig.pinSelect       = base->bclkPinIndex;
+        timerConfig.pinConfig       = kFLEXIO_PinConfigOutputDisabled;
+        timerConfig.pinPolarity     = config->bclkPinPolarity;
+        timerConfig.timerMode       = kFLEXIO_TimerModeSingle16Bit;
+        timerConfig.timerOutput     = kFLEXIO_TimerOutputOneNotAffectedByReset;
+        timerConfig.timerDecrement  = kFLEXIO_TimerDecSrcOnPinInputShiftPinInput;
+        timerConfig.timerReset      = kFLEXIO_TimerResetNever;
+        timerConfig.timerDisable    = kFLEXIO_TimerDisableOnTimerCompareTriggerLow;
+        timerConfig.timerEnable     = kFLEXIO_TimerEnableOnPinRisingEdgeTriggerHigh;
+        timerConfig.timerStart      = kFLEXIO_TimerStartBitDisabled;
+        timerConfig.timerStop       = kFLEXIO_TimerStopBitDisabled;
     }
     FLEXIO_SetTimerConfig(base->flexioBase, base->bclkTimerIndex, &timerConfig);
 
@@ -254,32 +244,60 @@ void FLEXIO_I2S_Init(FLEXIO_I2S_Type *base, const flexio_i2s_config_t *config)
     }
 }
 
+/*!
+ * brief  Sets the FlexIO I2S configuration structure to default values.
+ *
+ * The purpose of this API is to get the configuration structure initialized for use in FLEXIO_I2S_Init().
+ * Users may use the initialized structure unchanged in FLEXIO_I2S_Init() or modify
+ * some fields of the structure before calling FLEXIO_I2S_Init().
+ *
+ * param config pointer to master configuration structure
+ */
 void FLEXIO_I2S_GetDefaultConfig(flexio_i2s_config_t *config)
 {
-    config->masterSlave = kFLEXIO_I2S_Master;
-    config->enableI2S = true;
-    config->txPinPolarity = kFLEXIO_PinActiveHigh;
-    config->rxPinPolarity = kFLEXIO_PinActiveHigh;
+    /* Initializes the configure structure to zero. */
+    memset(config, 0, sizeof(*config));
+
+    config->masterSlave     = kFLEXIO_I2S_Master;
+    config->enableI2S       = true;
+    config->txPinPolarity   = kFLEXIO_PinActiveHigh;
+    config->rxPinPolarity   = kFLEXIO_PinActiveHigh;
     config->bclkPinPolarity = kFLEXIO_PinActiveHigh;
-    config->fsPinPolarity = kFLEXIO_PinActiveLow;
+    config->fsPinPolarity   = kFLEXIO_PinActiveLow;
     config->txTimerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive;
     config->rxTimerPolarity = kFLEXIO_ShifterTimerPolarityOnNegitive;
 }
 
+/*!
+ * brief De-initializes the FlexIO I2S.
+ *
+ * Calling this API resets the FlexIO I2S shifter and timer config. After calling this API,
+ * call the FLEXO_I2S_Init to use the FlexIO I2S module.
+ *
+ * param base FlexIO I2S base pointer
+ */
 void FLEXIO_I2S_Deinit(FLEXIO_I2S_Type *base)
 {
     base->flexioBase->SHIFTCFG[base->txShifterIndex] = 0;
     base->flexioBase->SHIFTCTL[base->txShifterIndex] = 0;
     base->flexioBase->SHIFTCFG[base->rxShifterIndex] = 0;
     base->flexioBase->SHIFTCTL[base->rxShifterIndex] = 0;
-    base->flexioBase->TIMCFG[base->fsTimerIndex] = 0;
-    base->flexioBase->TIMCMP[base->fsTimerIndex] = 0;
-    base->flexioBase->TIMCTL[base->fsTimerIndex] = 0;
-    base->flexioBase->TIMCFG[base->bclkTimerIndex] = 0;
-    base->flexioBase->TIMCMP[base->bclkTimerIndex] = 0;
-    base->flexioBase->TIMCTL[base->bclkTimerIndex] = 0;
+    base->flexioBase->TIMCFG[base->fsTimerIndex]     = 0;
+    base->flexioBase->TIMCMP[base->fsTimerIndex]     = 0;
+    base->flexioBase->TIMCTL[base->fsTimerIndex]     = 0;
+    base->flexioBase->TIMCFG[base->bclkTimerIndex]   = 0;
+    base->flexioBase->TIMCMP[base->bclkTimerIndex]   = 0;
+    base->flexioBase->TIMCTL[base->bclkTimerIndex]   = 0;
 }
 
+/*!
+ * brief Enables the FlexIO I2S interrupt.
+ *
+ * This function enables the FlexIO UART interrupt.
+ *
+ * param base Pointer to FLEXIO_I2S_Type structure
+ * param mask interrupt source
+ */
 void FLEXIO_I2S_EnableInterrupts(FLEXIO_I2S_Type *base, uint32_t mask)
 {
     if (mask & kFLEXIO_I2S_TxDataRegEmptyInterruptEnable)
@@ -292,6 +310,12 @@ void FLEXIO_I2S_EnableInterrupts(FLEXIO_I2S_Type *base, uint32_t mask)
     }
 }
 
+/*!
+ * brief Gets the FlexIO I2S status flags.
+ *
+ * param base Pointer to FLEXIO_I2S_Type structure
+ * return Status flag, which are ORed by the enumerators in the _flexio_i2s_status_flags.
+ */
 uint32_t FLEXIO_I2S_GetStatusFlags(FLEXIO_I2S_Type *base)
 {
     uint32_t status = 0;
@@ -302,6 +326,14 @@ uint32_t FLEXIO_I2S_GetStatusFlags(FLEXIO_I2S_Type *base)
     return status;
 }
 
+/*!
+ * brief Disables the FlexIO I2S interrupt.
+ *
+ * This function enables the FlexIO UART interrupt.
+ *
+ * param base pointer to FLEXIO_I2S_Type structure
+ * param mask interrupt source
+ */
 void FLEXIO_I2S_DisableInterrupts(FLEXIO_I2S_Type *base, uint32_t mask)
 {
     if (mask & kFLEXIO_I2S_TxDataRegEmptyInterruptEnable)
@@ -314,9 +346,19 @@ void FLEXIO_I2S_DisableInterrupts(FLEXIO_I2S_Type *base, uint32_t mask)
     }
 }
 
+/*!
+ * brief Configures the FlexIO I2S audio format in master mode.
+ *
+ * Audio format can be changed in run-time of FlexIO I2S. This function configures the sample rate and audio data
+ * format to be transferred.
+ *
+ * param base Pointer to FLEXIO_I2S_Type structure
+ * param format Pointer to FlexIO I2S audio data format structure.
+ * param srcClock_Hz I2S master clock source frequency in Hz.
+ */
 void FLEXIO_I2S_MasterSetFormat(FLEXIO_I2S_Type *base, flexio_i2s_format_t *format, uint32_t srcClock_Hz)
 {
-    uint32_t timDiv = srcClock_Hz / (format->sampleRate_Hz * 32U * 2U);
+    uint32_t timDiv  = srcClock_Hz / (format->sampleRate_Hz * format->bitWidth * 2U);
     uint32_t bclkDiv = 0;
 
     /* Shall keep bclk and fs div an integer */
@@ -325,25 +367,44 @@ void FLEXIO_I2S_MasterSetFormat(FLEXIO_I2S_Type *base, flexio_i2s_format_t *form
         timDiv += 1U;
     }
     /* Set Frame sync timer cmp */
-    base->flexioBase->TIMCMP[base->fsTimerIndex] = FLEXIO_TIMCMP_CMP(32U * timDiv - 1U);
+    base->flexioBase->TIMCMP[base->fsTimerIndex] = FLEXIO_TIMCMP_CMP(format->bitWidth * timDiv - 1U);
 
     /* Set bit clock timer cmp */
-    bclkDiv = ((timDiv / 2U - 1U) | (63U << 8U));
+    bclkDiv                                        = ((timDiv / 2U - 1U) | ((format->bitWidth * 2U - 1U) << 8U));
     base->flexioBase->TIMCMP[base->bclkTimerIndex] = FLEXIO_TIMCMP_CMP(bclkDiv);
 }
 
+/*!
+ * brief Configures the FlexIO I2S audio format in slave mode.
+ *
+ * Audio format can be changed in run-time of FlexIO I2S. This function configures the sample rate and audio data
+ * format to be transferred.
+ *
+ * param base Pointer to FLEXIO_I2S_Type structure
+ * param format Pointer to FlexIO I2S audio data format structure.
+ */
 void FLEXIO_I2S_SlaveSetFormat(FLEXIO_I2S_Type *base, flexio_i2s_format_t *format)
 {
     /* Set Frame sync timer cmp */
-    base->flexioBase->TIMCMP[base->fsTimerIndex] = FLEXIO_TIMCMP_CMP(32U * 4U - 3U);
+    base->flexioBase->TIMCMP[base->fsTimerIndex] = FLEXIO_TIMCMP_CMP(format->bitWidth * 4U - 3U);
 
     /* Set bit clock timer cmp */
-    base->flexioBase->TIMCMP[base->bclkTimerIndex] = FLEXIO_TIMCMP_CMP(32U * 2U - 1U);
+    base->flexioBase->TIMCMP[base->bclkTimerIndex] = FLEXIO_TIMCMP_CMP(format->bitWidth * 2U - 1U);
 }
 
+/*!
+ * brief Sends data using a blocking method.
+ *
+ * note This function blocks via polling until data is ready to be sent.
+ *
+ * param base FlexIO I2S base pointer.
+ * param bitWidth How many bits in a audio word, usually 8/16/24/32 bits.
+ * param txData Pointer to the data to be written.
+ * param size Bytes to be written.
+ */
 void FLEXIO_I2S_WriteBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth, uint8_t *txData, size_t size)
 {
-    uint32_t i = 0;
+    uint32_t i           = 0;
     uint8_t bytesPerWord = bitWidth / 8U;
 
     for (i = 0; i < size / bytesPerWord; i++)
@@ -363,9 +424,19 @@ void FLEXIO_I2S_WriteBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth, uint8_t *
     }
 }
 
+/*!
+ * brief Receives a piece of data using a blocking method.
+ *
+ * note This function blocks via polling until data is ready to be sent.
+ *
+ * param base FlexIO I2S base pointer
+ * param bitWidth How many bits in a audio word, usually 8/16/24/32 bits.
+ * param rxData Pointer to the data to be read.
+ * param size Bytes to be read.
+ */
 void FLEXIO_I2S_ReadBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth, uint8_t *rxData, size_t size)
 {
-    uint32_t i = 0;
+    uint32_t i           = 0;
     uint8_t bytesPerWord = bitWidth / 8U;
 
     for (i = 0; i < size / bytesPerWord; i++)
@@ -380,6 +451,18 @@ void FLEXIO_I2S_ReadBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth, uint8_t *r
     }
 }
 
+/*!
+ * brief Initializes the FlexIO I2S handle.
+ *
+ * This function initializes the FlexIO I2S handle which can be used for other
+ * FlexIO I2S transactional APIs. Call this API once to get the
+ * initialized handle.
+ *
+ * param base Pointer to FLEXIO_I2S_Type structure
+ * param handle Pointer to flexio_i2s_handle_t structure to store the transfer state.
+ * param callback FlexIO I2S callback function, which is called while finished a block.
+ * param userData User parameter for the FlexIO I2S callback.
+ */
 void FLEXIO_I2S_TransferTxCreateHandle(FLEXIO_I2S_Type *base,
                                        flexio_i2s_handle_t *handle,
                                        flexio_i2s_callback_t callback,
@@ -406,6 +489,18 @@ void FLEXIO_I2S_TransferTxCreateHandle(FLEXIO_I2S_Type *base,
     EnableIRQ(flexio_irqs[FLEXIO_I2S_GetInstance(base)]);
 }
 
+/*!
+ * brief Initializes the FlexIO I2S receive handle.
+ *
+ * This function initializes the FlexIO I2S handle which can be used for other
+ * FlexIO I2S transactional APIs. Call this API once to get the
+ * initialized handle.
+ *
+ * param base Pointer to FLEXIO_I2S_Type structure.
+ * param handle Pointer to flexio_i2s_handle_t structure to store the transfer state.
+ * param callback FlexIO I2S callback function, which is called while finished a block.
+ * param userData User parameter for the FlexIO I2S callback.
+ */
 void FLEXIO_I2S_TransferRxCreateHandle(FLEXIO_I2S_Type *base,
                                        flexio_i2s_handle_t *handle,
                                        flexio_i2s_callback_t callback,
@@ -432,6 +527,17 @@ void FLEXIO_I2S_TransferRxCreateHandle(FLEXIO_I2S_Type *base,
     EnableIRQ(flexio_irqs[FLEXIO_I2S_GetInstance(base)]);
 }
 
+/*!
+ * brief Configures the FlexIO I2S audio format.
+ *
+ * Audio format can be changed at run-time of FlexIO I2S. This function configures the sample rate and audio data
+ * format to be transferred.
+ *
+ * param base Pointer to FLEXIO_I2S_Type structure.
+ * param handle FlexIO I2S handle pointer.
+ * param format Pointer to audio data format structure.
+ * param srcClock_Hz FlexIO I2S bit clock source frequency in Hz. This parameter should be 0 while in slave mode.
+ */
 void FLEXIO_I2S_TransferSetFormat(FLEXIO_I2S_Type *base,
                                   flexio_i2s_handle_t *handle,
                                   flexio_i2s_format_t *format,
@@ -454,6 +560,20 @@ void FLEXIO_I2S_TransferSetFormat(FLEXIO_I2S_Type *base,
     }
 }
 
+/*!
+ * brief Performs an interrupt non-blocking send transfer on FlexIO I2S.
+ *
+ * note The API returns immediately after transfer initiates.
+ * Call FLEXIO_I2S_GetRemainingBytes to poll the transfer status and check whether
+ * the transfer is finished. If the return status is 0, the transfer is finished.
+ *
+ * param base Pointer to FLEXIO_I2S_Type structure.
+ * param handle Pointer to flexio_i2s_handle_t structure which stores the transfer state
+ * param xfer Pointer to flexio_i2s_transfer_t structure
+ * retval kStatus_Success Successfully start the data transmission.
+ * retval kStatus_FLEXIO_I2S_TxBusy Previous transmission still not finished, data not all written to TX register yet.
+ * retval kStatus_InvalidArgument The input parameter is invalid.
+ */
 status_t FLEXIO_I2S_TransferSendNonBlocking(FLEXIO_I2S_Type *base,
                                             flexio_i2s_handle_t *handle,
                                             flexio_i2s_transfer_t *xfer)
@@ -471,10 +591,10 @@ status_t FLEXIO_I2S_TransferSendNonBlocking(FLEXIO_I2S_Type *base,
     }
 
     /* Add into queue */
-    handle->queue[handle->queueUser].data = xfer->data;
+    handle->queue[handle->queueUser].data     = xfer->data;
     handle->queue[handle->queueUser].dataSize = xfer->dataSize;
-    handle->transferSize[handle->queueUser] = xfer->dataSize;
-    handle->queueUser = (handle->queueUser + 1) % FLEXIO_I2S_XFER_QUEUE_SIZE;
+    handle->transferSize[handle->queueUser]   = xfer->dataSize;
+    handle->queueUser                         = (handle->queueUser + 1) % FLEXIO_I2S_XFER_QUEUE_SIZE;
 
     /* Set the state to busy */
     handle->state = kFLEXIO_I2S_Busy;
@@ -487,6 +607,20 @@ status_t FLEXIO_I2S_TransferSendNonBlocking(FLEXIO_I2S_Type *base,
     return kStatus_Success;
 }
 
+/*!
+ * brief Performs an interrupt non-blocking receive transfer on FlexIO I2S.
+ *
+ * note The API returns immediately after transfer initiates.
+ * Call FLEXIO_I2S_GetRemainingBytes to poll the transfer status to check whether
+ * the transfer is finished. If the return status is 0, the transfer is finished.
+ *
+ * param base Pointer to FLEXIO_I2S_Type structure.
+ * param handle Pointer to flexio_i2s_handle_t structure which stores the transfer state
+ * param xfer Pointer to flexio_i2s_transfer_t structure
+ * retval kStatus_Success Successfully start the data receive.
+ * retval kStatus_FLEXIO_I2S_RxBusy Previous receive still not finished.
+ * retval kStatus_InvalidArgument The input parameter is invalid.
+ */
 status_t FLEXIO_I2S_TransferReceiveNonBlocking(FLEXIO_I2S_Type *base,
                                                flexio_i2s_handle_t *handle,
                                                flexio_i2s_transfer_t *xfer)
@@ -505,10 +639,10 @@ status_t FLEXIO_I2S_TransferReceiveNonBlocking(FLEXIO_I2S_Type *base,
     }
 
     /* Add into queue */
-    handle->queue[handle->queueUser].data = xfer->data;
+    handle->queue[handle->queueUser].data     = xfer->data;
     handle->queue[handle->queueUser].dataSize = xfer->dataSize;
-    handle->transferSize[handle->queueUser] = xfer->dataSize;
-    handle->queueUser = (handle->queueUser + 1) % FLEXIO_I2S_XFER_QUEUE_SIZE;
+    handle->transferSize[handle->queueUser]   = xfer->dataSize;
+    handle->queueUser                         = (handle->queueUser + 1) % FLEXIO_I2S_XFER_QUEUE_SIZE;
 
     /* Set state to busy */
     handle->state = kFLEXIO_I2S_Busy;
@@ -522,6 +656,15 @@ status_t FLEXIO_I2S_TransferReceiveNonBlocking(FLEXIO_I2S_Type *base,
     return kStatus_Success;
 }
 
+/*!
+ * brief Aborts the current send.
+ *
+ * note This API can be called at any time when interrupt non-blocking transfer initiates
+ * to abort the transfer in a early time.
+ *
+ * param base Pointer to FLEXIO_I2S_Type structure.
+ * param handle Pointer to flexio_i2s_handle_t structure which stores the transfer state
+ */
 void FLEXIO_I2S_TransferAbortSend(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle)
 {
     assert(handle);
@@ -533,9 +676,18 @@ void FLEXIO_I2S_TransferAbortSend(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *ha
     /* Clear the queue */
     memset(handle->queue, 0, sizeof(flexio_i2s_transfer_t) * FLEXIO_I2S_XFER_QUEUE_SIZE);
     handle->queueDriver = 0;
-    handle->queueUser = 0;
+    handle->queueUser   = 0;
 }
 
+/*!
+ * brief Aborts the current receive.
+ *
+ * note This API can be called at any time when interrupt non-blocking transfer initiates
+ * to abort the transfer in a early time.
+ *
+ * param base Pointer to FLEXIO_I2S_Type structure.
+ * param handle Pointer to flexio_i2s_handle_t structure which stores the transfer state
+ */
 void FLEXIO_I2S_TransferAbortReceive(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle)
 {
     assert(handle);
@@ -547,9 +699,18 @@ void FLEXIO_I2S_TransferAbortReceive(FLEXIO_I2S_Type *base, flexio_i2s_handle_t
     /* Clear the queue */
     memset(handle->queue, 0, sizeof(flexio_i2s_transfer_t) * FLEXIO_I2S_XFER_QUEUE_SIZE);
     handle->queueDriver = 0;
-    handle->queueUser = 0;
+    handle->queueUser   = 0;
 }
 
+/*!
+ * brief Gets the remaining bytes to be sent.
+ *
+ * param base Pointer to FLEXIO_I2S_Type structure.
+ * param handle Pointer to flexio_i2s_handle_t structure which stores the transfer state
+ * param count Bytes sent.
+ * retval kStatus_Success Succeed get the transfer count.
+ * retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress.
+ */
 status_t FLEXIO_I2S_TransferGetSendCount(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle, size_t *count)
 {
     assert(handle);
@@ -568,6 +729,15 @@ status_t FLEXIO_I2S_TransferGetSendCount(FLEXIO_I2S_Type *base, flexio_i2s_handl
     return status;
 }
 
+/*!
+ * brief Gets the remaining bytes to be received.
+ *
+ * param base Pointer to FLEXIO_I2S_Type structure.
+ * param handle Pointer to flexio_i2s_handle_t structure which stores the transfer state
+ * return count Bytes received.
+ * retval kStatus_Success Succeed get the transfer count.
+ * retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress.
+ */
 status_t FLEXIO_I2S_TransferGetReceiveCount(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle, size_t *count)
 {
     assert(handle);
@@ -586,14 +756,20 @@ status_t FLEXIO_I2S_TransferGetReceiveCount(FLEXIO_I2S_Type *base, flexio_i2s_ha
     return status;
 }
 
+/*!
+ * brief Tx interrupt handler.
+ *
+ * param i2sBase Pointer to FLEXIO_I2S_Type structure.
+ * param i2sHandle Pointer to flexio_i2s_handle_t structure
+ */
 void FLEXIO_I2S_TransferTxHandleIRQ(void *i2sBase, void *i2sHandle)
 {
     assert(i2sHandle);
 
     flexio_i2s_handle_t *handle = (flexio_i2s_handle_t *)i2sHandle;
-    FLEXIO_I2S_Type *base = (FLEXIO_I2S_Type *)i2sBase;
-    uint8_t *buffer = handle->queue[handle->queueDriver].data;
-    uint8_t dataSize = handle->bitWidth / 8U;
+    FLEXIO_I2S_Type *base       = (FLEXIO_I2S_Type *)i2sBase;
+    uint8_t *buffer             = handle->queue[handle->queueDriver].data;
+    uint8_t dataSize            = handle->bitWidth / 8U;
 
     /* Handle error */
     if (FLEXIO_GetShifterErrorFlags(base->flexioBase) & (1U << base->txShifterIndex))
@@ -611,7 +787,7 @@ void FLEXIO_I2S_TransferTxHandleIRQ(void *i2sBase, void *i2sHandle)
         handle->queue[handle->queueDriver].data += dataSize;
     }
 
-    /* If finished a blcok, call the callback function */
+    /* If finished a block, call the callback function */
     if ((handle->queue[handle->queueDriver].dataSize == 0U) && (handle->queue[handle->queueDriver].data != NULL))
     {
         memset(&handle->queue[handle->queueDriver], 0, sizeof(flexio_i2s_transfer_t));
@@ -629,14 +805,20 @@ void FLEXIO_I2S_TransferTxHandleIRQ(void *i2sBase, void *i2sHandle)
     }
 }
 
+/*!
+ * brief Rx interrupt handler.
+ *
+ * param i2sBase Pointer to FLEXIO_I2S_Type structure.
+ * param i2sHandle Pointer to flexio_i2s_handle_t structure.
+ */
 void FLEXIO_I2S_TransferRxHandleIRQ(void *i2sBase, void *i2sHandle)
 {
     assert(i2sHandle);
 
     flexio_i2s_handle_t *handle = (flexio_i2s_handle_t *)i2sHandle;
-    FLEXIO_I2S_Type *base = (FLEXIO_I2S_Type *)i2sBase;
-    uint8_t *buffer = handle->queue[handle->queueDriver].data;
-    uint8_t dataSize = handle->bitWidth / 8U;
+    FLEXIO_I2S_Type *base       = (FLEXIO_I2S_Type *)i2sBase;
+    uint8_t *buffer             = handle->queue[handle->queueDriver].data;
+    uint8_t dataSize            = handle->bitWidth / 8U;
 
     /* Handle transfer */
     if (((FLEXIO_I2S_GetStatusFlags(base) & kFLEXIO_I2S_RxDataRegFullFlag) != 0) &&
@@ -649,7 +831,7 @@ void FLEXIO_I2S_TransferRxHandleIRQ(void *i2sBase, void *i2sHandle)
         handle->queue[handle->queueDriver].data += dataSize;
     }
 
-    /* If finished a blcok, call the callback function */
+    /* If finished a block, call the callback function */
     if ((handle->queue[handle->queueDriver].dataSize == 0U) && (handle->queue[handle->queueDriver].data != NULL))
     {
         memset(&handle->queue[handle->queueDriver], 0, sizeof(flexio_i2s_transfer_t));
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_i2s.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_i2s.h
index 2d7326c37e0..32e792596b4 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_i2s.h
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_i2s.h
@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
+ * Copyright 2016-2018 NXP
  * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 #ifndef _FSL_FLEXIO_I2S_H_
 #define _FSL_FLEXIO_I2S_H_
@@ -48,17 +22,17 @@
 
 /*! @name Driver version */
 /*@{*/
-/*! @brief FlexIO I2S driver version 2.1.4. */
-#define FSL_FLEXIO_I2S_DRIVER_VERSION (MAKE_VERSION(2, 1, 4))
+/*! @brief FlexIO I2S driver version 2.1.6. */
+#define FSL_FLEXIO_I2S_DRIVER_VERSION (MAKE_VERSION(2, 1, 6))
 /*@}*/
 
 /*! @brief FlexIO I2S transfer status */
 enum _flexio_i2s_status
 {
-    kStatus_FLEXIO_I2S_Idle = MAKE_STATUS(kStatusGroup_FLEXIO_I2S, 0),      /*!< FlexIO I2S is in idle state */
-    kStatus_FLEXIO_I2S_TxBusy = MAKE_STATUS(kStatusGroup_FLEXIO_I2S, 1),    /*!< FlexIO I2S Tx is busy */
-    kStatus_FLEXIO_I2S_RxBusy = MAKE_STATUS(kStatusGroup_FLEXIO_I2S, 2),    /*!< FlexIO I2S Tx is busy */
-    kStatus_FLEXIO_I2S_Error = MAKE_STATUS(kStatusGroup_FLEXIO_I2S, 3),     /*!< FlexIO I2S error occurred */
+    kStatus_FLEXIO_I2S_Idle      = MAKE_STATUS(kStatusGroup_FLEXIO_I2S, 0), /*!< FlexIO I2S is in idle state */
+    kStatus_FLEXIO_I2S_TxBusy    = MAKE_STATUS(kStatusGroup_FLEXIO_I2S, 1), /*!< FlexIO I2S Tx is busy */
+    kStatus_FLEXIO_I2S_RxBusy    = MAKE_STATUS(kStatusGroup_FLEXIO_I2S, 2), /*!< FlexIO I2S Tx is busy */
+    kStatus_FLEXIO_I2S_Error     = MAKE_STATUS(kStatusGroup_FLEXIO_I2S, 3), /*!< FlexIO I2S error occurred */
     kStatus_FLEXIO_I2S_QueueFull = MAKE_STATUS(kStatusGroup_FLEXIO_I2S, 4), /*!< FlexIO I2S transfer queue is full. */
 };
 
@@ -80,21 +54,21 @@ typedef struct _flexio_i2s_type
 typedef enum _flexio_i2s_master_slave
 {
     kFLEXIO_I2S_Master = 0x0U, /*!< Master mode */
-    kFLEXIO_I2S_Slave = 0x1U   /*!< Slave mode */
+    kFLEXIO_I2S_Slave  = 0x1U  /*!< Slave mode */
 } flexio_i2s_master_slave_t;
 
 /*! @brief Define FlexIO FlexIO I2S interrupt mask. */
 enum _flexio_i2s_interrupt_enable
 {
     kFLEXIO_I2S_TxDataRegEmptyInterruptEnable = 0x1U, /*!< Transmit buffer empty interrupt enable. */
-    kFLEXIO_I2S_RxDataRegFullInterruptEnable = 0x2U,  /*!< Receive buffer full interrupt enable. */
+    kFLEXIO_I2S_RxDataRegFullInterruptEnable  = 0x2U, /*!< Receive buffer full interrupt enable. */
 };
 
 /*! @brief Define FlexIO FlexIO I2S status mask. */
 enum _flexio_i2s_status_flags
 {
     kFLEXIO_I2S_TxDataRegEmptyFlag = 0x1U, /*!< Transmit buffer empty flag. */
-    kFLEXIO_I2S_RxDataRegFullFlag = 0x2U,  /*!< Receive buffer full flag. */
+    kFLEXIO_I2S_RxDataRegFullFlag  = 0x2U, /*!< Receive buffer full flag. */
 };
 
 /*! @brief FlexIO I2S configure structure */
@@ -123,22 +97,22 @@ typedef struct _flexio_i2s_format
 /*! @brief Audio sample rate */
 typedef enum _flexio_i2s_sample_rate
 {
-    kFLEXIO_I2S_SampleRate8KHz = 8000U,     /*!< Sample rate 8000Hz */
+    kFLEXIO_I2S_SampleRate8KHz    = 8000U,  /*!< Sample rate 8000Hz */
     kFLEXIO_I2S_SampleRate11025Hz = 11025U, /*!< Sample rate 11025Hz */
-    kFLEXIO_I2S_SampleRate12KHz = 12000U,   /*!< Sample rate 12000Hz */
-    kFLEXIO_I2S_SampleRate16KHz = 16000U,   /*!< Sample rate 16000Hz */
+    kFLEXIO_I2S_SampleRate12KHz   = 12000U, /*!< Sample rate 12000Hz */
+    kFLEXIO_I2S_SampleRate16KHz   = 16000U, /*!< Sample rate 16000Hz */
     kFLEXIO_I2S_SampleRate22050Hz = 22050U, /*!< Sample rate 22050Hz */
-    kFLEXIO_I2S_SampleRate24KHz = 24000U,   /*!< Sample rate 24000Hz */
-    kFLEXIO_I2S_SampleRate32KHz = 32000U,   /*!< Sample rate 32000Hz */
+    kFLEXIO_I2S_SampleRate24KHz   = 24000U, /*!< Sample rate 24000Hz */
+    kFLEXIO_I2S_SampleRate32KHz   = 32000U, /*!< Sample rate 32000Hz */
     kFLEXIO_I2S_SampleRate44100Hz = 44100U, /*!< Sample rate 44100Hz */
-    kFLEXIO_I2S_SampleRate48KHz = 48000U,   /*!< Sample rate 48000Hz */
-    kFLEXIO_I2S_SampleRate96KHz = 96000U    /*!< Sample rate 96000Hz */
+    kFLEXIO_I2S_SampleRate48KHz   = 48000U, /*!< Sample rate 48000Hz */
+    kFLEXIO_I2S_SampleRate96KHz   = 96000U  /*!< Sample rate 96000Hz */
 } flexio_i2s_sample_rate_t;
 
 /*! @brief Audio word width */
 typedef enum _flexio_i2s_word_width
 {
-    kFLEXIO_I2S_WordWidth8bits = 8U,   /*!< Audio data width 8 bits */
+    kFLEXIO_I2S_WordWidth8bits  = 8U,  /*!< Audio data width 8 bits */
     kFLEXIO_I2S_WordWidth16bits = 16U, /*!< Audio data width 16 bits */
     kFLEXIO_I2S_WordWidth24bits = 24U, /*!< Audio data width 24 bits */
     kFLEXIO_I2S_WordWidth32bits = 32U  /*!< Audio data width 32 bits */
@@ -198,7 +172,7 @@ extern "C" {
  *
  * @param base FlexIO I2S base pointer
  * @param config FlexIO I2S configure structure.
-*/
+ */
 void FLEXIO_I2S_Init(FLEXIO_I2S_Type *base, const flexio_i2s_config_t *config);
 
 /*!
@@ -219,7 +193,7 @@ void FLEXIO_I2S_GetDefaultConfig(flexio_i2s_config_t *config);
  * call the FLEXO_I2S_Init to use the FlexIO I2S module.
  *
  * @param base FlexIO I2S base pointer
-*/
+ */
 void FLEXIO_I2S_Deinit(FLEXIO_I2S_Type *base);
 
 /*!
@@ -227,7 +201,7 @@ void FLEXIO_I2S_Deinit(FLEXIO_I2S_Type *base);
  *
  * @param base Pointer to FLEXIO_I2S_Type
  * @param enable True to enable, false dose not have any effect.
-*/
+ */
 static inline void FLEXIO_I2S_Enable(FLEXIO_I2S_Type *base, bool enable)
 {
     if (enable)
@@ -248,7 +222,7 @@ static inline void FLEXIO_I2S_Enable(FLEXIO_I2S_Type *base, bool enable)
  *
  * @param base Pointer to FLEXIO_I2S_Type structure
  * @return Status flag, which are ORed by the enumerators in the _flexio_i2s_status_flags.
-*/
+ */
 uint32_t FLEXIO_I2S_GetStatusFlags(FLEXIO_I2S_Type *base);
 
 /*! @} */
@@ -349,7 +323,7 @@ static inline uint32_t FLEXIO_I2S_RxGetDataRegisterAddress(FLEXIO_I2S_Type *base
  * @param base Pointer to FLEXIO_I2S_Type structure
  * @param format Pointer to FlexIO I2S audio data format structure.
  * @param srcClock_Hz I2S master clock source frequency in Hz.
-*/
+ */
 void FLEXIO_I2S_MasterSetFormat(FLEXIO_I2S_Type *base, flexio_i2s_format_t *format, uint32_t srcClock_Hz);
 
 /*!
@@ -360,7 +334,7 @@ void FLEXIO_I2S_MasterSetFormat(FLEXIO_I2S_Type *base, flexio_i2s_format_t *form
  *
  * @param base Pointer to FLEXIO_I2S_Type structure
  * @param format Pointer to FlexIO I2S audio data format structure.
-*/
+ */
 void FLEXIO_I2S_SlaveSetFormat(FLEXIO_I2S_Type *base, flexio_i2s_format_t *format);
 
 /*!
@@ -444,7 +418,7 @@ void FLEXIO_I2S_TransferTxCreateHandle(FLEXIO_I2S_Type *base,
  * @param handle FlexIO I2S handle pointer.
  * @param format Pointer to audio data format structure.
  * @param srcClock_Hz FlexIO I2S bit clock source frequency in Hz. This parameter should be 0 while in slave mode.
-*/
+ */
 void FLEXIO_I2S_TransferSetFormat(FLEXIO_I2S_Type *base,
                                   flexio_i2s_handle_t *handle,
                                   flexio_i2s_format_t *format,
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_i2s_edma.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_i2s_edma.c
index 223d71d7590..5774768afe0 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_i2s_edma.c
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_i2s_edma.c
@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
+ * Copyright 2016-2018 NXP
  * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
  *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include "fsl_flexio_i2s_edma.h"
@@ -39,7 +13,6 @@
 #define FSL_COMPONENT_ID "platform.drivers.flexio_i2s_edma"
 #endif
 
-
 /*******************************************************************************
  * Definitations
  ******************************************************************************/
@@ -86,14 +59,14 @@ static void FLEXIO_I2S_TxEDMACallback(edma_handle_t *handle, void *userData, boo
 static void FLEXIO_I2S_RxEDMACallback(edma_handle_t *handle, void *userData, bool done, uint32_t tcds);
 
 /*******************************************************************************
-* Code
-******************************************************************************/
+ * Code
+ ******************************************************************************/
 static void FLEXIO_I2S_TxEDMACallback(edma_handle_t *handle, void *userData, bool done, uint32_t tcds)
 {
     flexio_i2s_edma_private_handle_t *privHandle = (flexio_i2s_edma_private_handle_t *)userData;
-    flexio_i2s_edma_handle_t *flexio_i2sHandle = privHandle->handle;
+    flexio_i2s_edma_handle_t *flexio_i2sHandle   = privHandle->handle;
 
-    /* If finished a blcok, call the callback function */
+    /* If finished a block, call the callback function */
     memset(&flexio_i2sHandle->queue[flexio_i2sHandle->queueDriver], 0, sizeof(flexio_i2s_transfer_t));
     flexio_i2sHandle->queueDriver = (flexio_i2sHandle->queueDriver + 1) % FLEXIO_I2S_XFER_QUEUE_SIZE;
     if (flexio_i2sHandle->callback)
@@ -111,9 +84,9 @@ static void FLEXIO_I2S_TxEDMACallback(edma_handle_t *handle, void *userData, boo
 static void FLEXIO_I2S_RxEDMACallback(edma_handle_t *handle, void *userData, bool done, uint32_t tcds)
 {
     flexio_i2s_edma_private_handle_t *privHandle = (flexio_i2s_edma_private_handle_t *)userData;
-    flexio_i2s_edma_handle_t *flexio_i2sHandle = privHandle->handle;
+    flexio_i2s_edma_handle_t *flexio_i2sHandle   = privHandle->handle;
 
-    /* If finished a blcok, call the callback function */
+    /* If finished a block, call the callback function */
     memset(&flexio_i2sHandle->queue[flexio_i2sHandle->queueDriver], 0, sizeof(flexio_i2s_transfer_t));
     flexio_i2sHandle->queueDriver = (flexio_i2sHandle->queueDriver + 1) % FLEXIO_I2S_XFER_QUEUE_SIZE;
     if (flexio_i2sHandle->callback)
@@ -128,6 +101,19 @@ static void FLEXIO_I2S_RxEDMACallback(edma_handle_t *handle, void *userData, boo
     }
 }
 
+/*!
+ * brief Initializes the FlexIO I2S eDMA handle.
+ *
+ * This function initializes the FlexIO I2S master DMA handle which can be used for other FlexIO I2S master
+ * transactional APIs.
+ * Usually, for a specified FlexIO I2S instance, call this API once to get the initialized handle.
+ *
+ * param base FlexIO I2S peripheral base address.
+ * param handle FlexIO I2S eDMA handle pointer.
+ * param callback FlexIO I2S eDMA callback function called while finished a block.
+ * param userData User parameter for callback.
+ * param dmaHandle eDMA handle for FlexIO I2S. This handle is a static value allocated by users.
+ */
 void FLEXIO_I2S_TransferTxCreateHandleEDMA(FLEXIO_I2S_Type *base,
                                            flexio_i2s_edma_handle_t *handle,
                                            flexio_i2s_edma_callback_t callback,
@@ -141,13 +127,13 @@ void FLEXIO_I2S_TransferTxCreateHandleEDMA(FLEXIO_I2S_Type *base,
 
     /* Set flexio_i2s base to handle */
     handle->dmaHandle = dmaHandle;
-    handle->callback = callback;
-    handle->userData = userData;
+    handle->callback  = callback;
+    handle->userData  = userData;
 
     /* Set FLEXIO I2S state to idle */
     handle->state = kFLEXIO_I2S_Idle;
 
-    s_edmaPrivateHandle[0].base = base;
+    s_edmaPrivateHandle[0].base   = base;
     s_edmaPrivateHandle[0].handle = handle;
 
     /* Need to use scatter gather */
@@ -157,6 +143,19 @@ void FLEXIO_I2S_TransferTxCreateHandleEDMA(FLEXIO_I2S_Type *base,
     EDMA_SetCallback(dmaHandle, FLEXIO_I2S_TxEDMACallback, &s_edmaPrivateHandle[0]);
 }
 
+/*!
+ * brief Initializes the FlexIO I2S Rx eDMA handle.
+ *
+ * This function initializes the FlexIO I2S slave DMA handle which can be used for other FlexIO I2S master transactional
+ * APIs.
+ * Usually, for a specified FlexIO I2S instance, call this API once to get the initialized handle.
+ *
+ * param base FlexIO I2S peripheral base address.
+ * param handle FlexIO I2S eDMA handle pointer.
+ * param callback FlexIO I2S eDMA callback function called while finished a block.
+ * param userData User parameter for callback.
+ * param dmaHandle eDMA handle for FlexIO I2S. This handle is a static value allocated by users.
+ */
 void FLEXIO_I2S_TransferRxCreateHandleEDMA(FLEXIO_I2S_Type *base,
                                            flexio_i2s_edma_handle_t *handle,
                                            flexio_i2s_edma_callback_t callback,
@@ -170,13 +169,13 @@ void FLEXIO_I2S_TransferRxCreateHandleEDMA(FLEXIO_I2S_Type *base,
 
     /* Set flexio_i2s base to handle */
     handle->dmaHandle = dmaHandle;
-    handle->callback = callback;
-    handle->userData = userData;
+    handle->callback  = callback;
+    handle->userData  = userData;
 
     /* Set FLEXIO I2S state to idle */
     handle->state = kFLEXIO_I2S_Idle;
 
-    s_edmaPrivateHandle[1].base = base;
+    s_edmaPrivateHandle[1].base   = base;
     s_edmaPrivateHandle[1].handle = handle;
 
     /* Need to use scatter gather */
@@ -186,6 +185,19 @@ void FLEXIO_I2S_TransferRxCreateHandleEDMA(FLEXIO_I2S_Type *base,
     EDMA_SetCallback(dmaHandle, FLEXIO_I2S_RxEDMACallback, &s_edmaPrivateHandle[1]);
 }
 
+/*!
+ * brief Configures the FlexIO I2S Tx audio format.
+ *
+ * Audio format can be changed in run-time of FlexIO I2S. This function configures the sample rate and audio data
+ * format to be transferred. This function also sets the eDMA parameter according to format.
+ *
+ * param base FlexIO I2S peripheral base address.
+ * param handle FlexIO I2S eDMA handle pointer
+ * param format Pointer to FlexIO I2S audio data format structure.
+ * param srcClock_Hz FlexIO I2S clock source frequency in Hz, it should be 0 while in slave mode.
+ * retval kStatus_Success Audio format set successfully.
+ * retval kStatus_InvalidArgument The input arguments is invalid.
+ */
 void FLEXIO_I2S_TransferSetFormatEDMA(FLEXIO_I2S_Type *base,
                                       flexio_i2s_edma_handle_t *handle,
                                       flexio_i2s_format_t *format,
@@ -204,10 +216,23 @@ void FLEXIO_I2S_TransferSetFormatEDMA(FLEXIO_I2S_Type *base,
         FLEXIO_I2S_SlaveSetFormat(base, format);
     }
 
-    /* Get the tranfer size from format, this should be used in EDMA configuration */
+    /* Get the transfer size from format, this should be used in EDMA configuration */
     handle->bytesPerFrame = format->bitWidth / 8U;
 }
 
+/*!
+ * brief Performs a non-blocking FlexIO I2S transfer using DMA.
+ *
+ * note This interface returned immediately after transfer initiates. Users should call
+ * FLEXIO_I2S_GetTransferStatus to poll the transfer status and check whether the FlexIO I2S transfer is finished.
+ *
+ * param base FlexIO I2S peripheral base address.
+ * param handle FlexIO I2S DMA handle pointer.
+ * param xfer Pointer to DMA transfer structure.
+ * retval kStatus_Success Start a FlexIO I2S eDMA send successfully.
+ * retval kStatus_InvalidArgument The input arguments is invalid.
+ * retval kStatus_TxBusy FlexIO I2S is busy sending data.
+ */
 status_t FLEXIO_I2S_TransferSendEDMA(FLEXIO_I2S_Type *base,
                                      flexio_i2s_edma_handle_t *handle,
                                      flexio_i2s_transfer_t *xfer)
@@ -215,7 +240,7 @@ status_t FLEXIO_I2S_TransferSendEDMA(FLEXIO_I2S_Type *base,
     assert(handle && xfer);
 
     edma_transfer_config_t config = {0};
-    uint32_t destAddr = FLEXIO_I2S_TxGetDataRegisterAddress(base) + (4U - handle->bytesPerFrame);
+    uint32_t destAddr             = FLEXIO_I2S_TxGetDataRegisterAddress(base) + (4U - handle->bytesPerFrame);
 
     /* Check if input parameter invalid */
     if ((xfer->data == NULL) || (xfer->dataSize == 0U))
@@ -232,10 +257,10 @@ status_t FLEXIO_I2S_TransferSendEDMA(FLEXIO_I2S_Type *base,
     handle->state = kFLEXIO_I2S_Busy;
 
     /* Update the queue state */
-    handle->queue[handle->queueUser].data = xfer->data;
+    handle->queue[handle->queueUser].data     = xfer->data;
     handle->queue[handle->queueUser].dataSize = xfer->dataSize;
-    handle->transferSize[handle->queueUser] = xfer->dataSize;
-    handle->queueUser = (handle->queueUser + 1) % FLEXIO_I2S_XFER_QUEUE_SIZE;
+    handle->transferSize[handle->queueUser]   = xfer->dataSize;
+    handle->queueUser                         = (handle->queueUser + 1) % FLEXIO_I2S_XFER_QUEUE_SIZE;
 
     /* Prepare edma configure */
     EDMA_PrepareTransfer(&config, xfer->data, handle->bytesPerFrame, (void *)destAddr, handle->bytesPerFrame,
@@ -258,6 +283,20 @@ status_t FLEXIO_I2S_TransferSendEDMA(FLEXIO_I2S_Type *base,
     return kStatus_Success;
 }
 
+/*!
+ * brief Performs a non-blocking FlexIO I2S receive using eDMA.
+ *
+ * note This interface returned immediately after transfer initiates. Users should call
+ * FLEXIO_I2S_GetReceiveRemainingBytes to poll the transfer status and check whether the FlexIO I2S transfer is
+ * finished.
+ *
+ * param base FlexIO I2S peripheral base address.
+ * param handle FlexIO I2S DMA handle pointer.
+ * param xfer Pointer to DMA transfer structure.
+ * retval kStatus_Success Start a FlexIO I2S eDMA receive successfully.
+ * retval kStatus_InvalidArgument The input arguments is invalid.
+ * retval kStatus_RxBusy FlexIO I2S is busy receiving data.
+ */
 status_t FLEXIO_I2S_TransferReceiveEDMA(FLEXIO_I2S_Type *base,
                                         flexio_i2s_edma_handle_t *handle,
                                         flexio_i2s_transfer_t *xfer)
@@ -265,7 +304,7 @@ status_t FLEXIO_I2S_TransferReceiveEDMA(FLEXIO_I2S_Type *base,
     assert(handle && xfer);
 
     edma_transfer_config_t config = {0};
-    uint32_t srcAddr = FLEXIO_I2S_RxGetDataRegisterAddress(base) + (4U - handle->bytesPerFrame);
+    uint32_t srcAddr              = FLEXIO_I2S_RxGetDataRegisterAddress(base);
 
     /* Check if input parameter invalid */
     if ((xfer->data == NULL) || (xfer->dataSize == 0U))
@@ -282,10 +321,10 @@ status_t FLEXIO_I2S_TransferReceiveEDMA(FLEXIO_I2S_Type *base,
     handle->state = kFLEXIO_I2S_Busy;
 
     /* Update queue state  */
-    handle->queue[handle->queueUser].data = xfer->data;
+    handle->queue[handle->queueUser].data     = xfer->data;
     handle->queue[handle->queueUser].dataSize = xfer->dataSize;
-    handle->transferSize[handle->queueUser] = xfer->dataSize;
-    handle->queueUser = (handle->queueUser + 1) % FLEXIO_I2S_XFER_QUEUE_SIZE;
+    handle->transferSize[handle->queueUser]   = xfer->dataSize;
+    handle->queueUser                         = (handle->queueUser + 1) % FLEXIO_I2S_XFER_QUEUE_SIZE;
 
     /* Prepare edma configure */
     EDMA_PrepareTransfer(&config, (void *)srcAddr, handle->bytesPerFrame, xfer->data, handle->bytesPerFrame,
@@ -308,6 +347,12 @@ status_t FLEXIO_I2S_TransferReceiveEDMA(FLEXIO_I2S_Type *base,
     return kStatus_Success;
 }
 
+/*!
+ * brief Aborts a FlexIO I2S transfer using eDMA.
+ *
+ * param base FlexIO I2S peripheral base address.
+ * param handle FlexIO I2S DMA handle pointer.
+ */
 void FLEXIO_I2S_TransferAbortSendEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle)
 {
     assert(handle);
@@ -322,6 +367,12 @@ void FLEXIO_I2S_TransferAbortSendEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_han
     handle->state = kFLEXIO_I2S_Idle;
 }
 
+/*!
+ * brief Aborts a FlexIO I2S receive using eDMA.
+ *
+ * param base FlexIO I2S peripheral base address.
+ * param handle FlexIO I2S DMA handle pointer.
+ */
 void FLEXIO_I2S_TransferAbortReceiveEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle)
 {
     assert(handle);
@@ -336,6 +387,15 @@ void FLEXIO_I2S_TransferAbortReceiveEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_
     handle->state = kFLEXIO_I2S_Idle;
 }
 
+/*!
+ * brief Gets the remaining bytes to be sent.
+ *
+ * param base FlexIO I2S peripheral base address.
+ * param handle FlexIO I2S DMA handle pointer.
+ * param count Bytes sent.
+ * retval kStatus_Success Succeed get the transfer count.
+ * retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress.
+ */
 status_t FLEXIO_I2S_TransferGetSendCountEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle, size_t *count)
 {
     assert(handle);
@@ -356,6 +416,15 @@ status_t FLEXIO_I2S_TransferGetSendCountEDMA(FLEXIO_I2S_Type *base, flexio_i2s_e
     return status;
 }
 
+/*!
+ * brief Get the remaining bytes to be received.
+ *
+ * param base FlexIO I2S peripheral base address.
+ * param handle FlexIO I2S DMA handle pointer.
+ * param count Bytes received.
+ * retval kStatus_Success Succeed get the transfer count.
+ * retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress.
+ */
 status_t FLEXIO_I2S_TransferGetReceiveCountEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle, size_t *count)
 {
     assert(handle);
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_i2s_edma.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_i2s_edma.h
index e529fe23f70..817f1970592 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_i2s_edma.h
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_i2s_edma.h
@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
+ * Copyright 2016-2018 NXP
  * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
  *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 #ifndef _FSL_FLEXIO_I2S_EDMA_H_
 #define _FSL_FLEXIO_I2S_EDMA_H_
@@ -48,8 +22,8 @@
 
 /*! @name Driver version */
 /*@{*/
-/*! @brief FlexIO I2S EDMA driver version 2.1.4. */
-#define FSL_FLEXIO_I2S_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 1, 4))
+/*! @brief FlexIO I2S EDMA driver version 2.1.5. */
+#define FSL_FLEXIO_I2S_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 1, 5))
 /*@}*/
 
 typedef struct _flexio_i2s_edma_handle flexio_i2s_edma_handle_t;
@@ -138,7 +112,7 @@ void FLEXIO_I2S_TransferRxCreateHandleEDMA(FLEXIO_I2S_Type *base,
  * @param srcClock_Hz FlexIO I2S clock source frequency in Hz, it should be 0 while in slave mode.
  * @retval kStatus_Success Audio format set successfully.
  * @retval kStatus_InvalidArgument The input arguments is invalid.
-*/
+ */
 void FLEXIO_I2S_TransferSetFormatEDMA(FLEXIO_I2S_Type *base,
                                       flexio_i2s_edma_handle_t *handle,
                                       flexio_i2s_format_t *format,
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_mculcd.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_mculcd.c
new file mode 100644
index 00000000000..e5d5b5d8c63
--- /dev/null
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_mculcd.c
@@ -0,0 +1,1286 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_flexio_mculcd.h"
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.flexio_mculcd"
+#endif
+
+/*******************************************************************************
+ * Definitations
+ ******************************************************************************/
+
+enum _mculcd_transfer_state
+{
+    kFLEXIO_MCULCD_StateIdle,           /*!< No transfer in progress. */
+    kFLEXIO_MCULCD_StateReadArray,      /*!< Reading array in progress. */
+    kFLEXIO_MCULCD_StateWriteArray,     /*!< Writing array in progress. */
+    kFLEXIO_MCULCD_StateWriteSameValue, /*!< Writing the same value in progress. */
+};
+
+/* The TIMCFG[0:7] is used for baud rate divider in dual 8-bit counters baud/bit mode. */
+#define FLEXIO_BAUDRATE_DIV_MASK 0xFFU
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/*!
+ * brief Ungates the FlexIO clock, resets the FlexIO module, configures the
+ * FlexIO MCULCD hardware, and configures the FlexIO MCULCD with FlexIO MCULCD
+ * configuration.
+ * The configuration structure can be filled by the user, or be set with default
+ * values
+ * by the ref FLEXIO_MCULCD_GetDefaultConfig.
+ *
+ * param base Pointer to the FLEXIO_MCULCD_Type structure.
+ * param config Pointer to the flexio_mculcd_config_t structure.
+ * param srcClock_Hz FlexIO source clock in Hz.
+ * retval kStatus_Success Initialization success.
+ * retval kStatus_InvalidArgument Initialization failed because of invalid
+ * argument.
+ */
+status_t FLEXIO_MCULCD_Init(FLEXIO_MCULCD_Type *base, flexio_mculcd_config_t *config, uint32_t srcClock_Hz)
+{
+    assert(config);
+
+    flexio_config_t flexioConfig = {config->enable, config->enableInDoze, config->enableInDebug,
+                                    config->enableFastAccess};
+
+    FLEXIO_Init(base->flexioBase, &flexioConfig);
+
+    if (kStatus_Success != FLEXIO_MCULCD_SetBaudRate(base, config->baudRate_Bps, srcClock_Hz))
+    {
+        return kStatus_Success;
+    }
+
+    base->setCSPin(true);
+    base->setRSPin(true);
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Resets the FLEXIO_MCULCD timer and shifter configuration.
+ *
+ * param base Pointer to the FLEXIO_MCULCD_Type.
+ */
+void FLEXIO_MCULCD_Deinit(FLEXIO_MCULCD_Type *base)
+{
+    FLEXIO_MCULCD_ClearSingleBeatWriteConfig(base);
+    FLEXIO_MCULCD_ClearSingleBeatReadConfig(base);
+}
+
+/*!
+ * brief Gets the default configuration to configure the FlexIO MCULCD.
+ *
+ * The default configuration value is:
+ * code
+ *  config->enable = true;
+ *  config->enableInDoze = false;
+ *  config->enableInDebug = true;
+ *  config->enableFastAccess = true;
+ *  config->baudRate_Bps = 96000000U;
+ * endcode
+ * param Config Pointer to the flexio_mculcd_config_t structure.
+ */
+void FLEXIO_MCULCD_GetDefaultConfig(flexio_mculcd_config_t *config)
+{
+    assert(config);
+
+    /* Initializes the configure structure to zero. */
+    memset(config, 0, sizeof(*config));
+
+    config->enable           = true;
+    config->enableInDoze     = false;
+    config->enableInDebug    = true;
+    config->enableFastAccess = true;
+    config->baudRate_Bps     = 96000000U;
+}
+
+/*!
+ * brief Set desired baud rate.
+ *
+ * param base Pointer to the FLEXIO_MCULCD_Type structure.
+ * param baudRate_Bps Desired baud rate.
+ * param srcClock_Hz FLEXIO clock frequency in Hz.
+ * retval kStatus_Success Set successfully.
+ * retval kStatus_InvalidArgument Could not set the baud rate.
+ */
+status_t FLEXIO_MCULCD_SetBaudRate(FLEXIO_MCULCD_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz)
+{
+    uint32_t baudRateDiv;
+    uint32_t baudRatePerDataLine;
+    uint32_t timerCompare;
+
+    baudRatePerDataLine = baudRate_Bps / FLEXIO_MCULCD_DATA_BUS_WIDTH;
+
+    baudRateDiv = (srcClock_Hz + baudRatePerDataLine) / (baudRatePerDataLine * 2);
+
+    if ((0 == baudRateDiv) || (baudRateDiv > (FLEXIO_BAUDRATE_DIV_MASK + 1U)))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    baudRateDiv--;
+
+    timerCompare = base->flexioBase->TIMCMP[base->timerIndex];
+
+    timerCompare = (timerCompare & ~FLEXIO_BAUDRATE_DIV_MASK) | baudRateDiv;
+
+    base->flexioBase->TIMCMP[base->timerIndex] = timerCompare;
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Gets FlexIO MCULCD status flags.
+ *
+ * param base Pointer to the FLEXIO_MCULCD_Type structure.
+ * return status flag; OR'ed value or the ref _flexio_mculcd_status_flags.
+ *
+ * note Don't use this function with DMA APIs.
+ */
+uint32_t FLEXIO_MCULCD_GetStatusFlags(FLEXIO_MCULCD_Type *base)
+{
+    uint32_t ret = 0U;
+    uint32_t flags;
+
+    /* Get shifter status. */
+    flags = FLEXIO_GetShifterStatusFlags(base->flexioBase);
+
+    if (flags & (1U << base->rxShifterEndIndex))
+    {
+        ret |= kFLEXIO_MCULCD_RxFullFlag;
+    }
+
+    if (flags & (1U << base->txShifterStartIndex))
+    {
+        ret |= kFLEXIO_MCULCD_TxEmptyFlag;
+    }
+
+    return ret;
+}
+
+/*!
+ * brief Clears FlexIO MCULCD status flags.
+ *
+ * param base Pointer to the FLEXIO_MCULCD_Type structure.
+ * param mask Status to clear, it is the OR'ed value of ref
+ * _flexio_mculcd_status_flags.
+ *
+ * note Don't use this function with DMA APIs.
+ */
+void FLEXIO_MCULCD_ClearStatusFlags(FLEXIO_MCULCD_Type *base, uint32_t mask)
+{
+    uint32_t flags = 0U;
+
+    /* Clear the shifter flags. */
+    if (mask & kFLEXIO_MCULCD_RxFullFlag)
+    {
+        flags |= (1U << base->rxShifterEndIndex);
+    }
+
+    if (mask & kFLEXIO_MCULCD_TxEmptyFlag)
+    {
+        flags |= (1U << base->txShifterStartIndex);
+    }
+
+    FLEXIO_ClearShifterStatusFlags(base->flexioBase, flags);
+}
+
+/*!
+ * brief Enables the FlexIO MCULCD interrupt.
+ *
+ * This function enables the FlexIO MCULCD interrupt.
+ *
+ * param base Pointer to the FLEXIO_MCULCD_Type structure.
+ * param mask Interrupts to enable, it is the OR'ed value of ref
+ * _flexio_mculcd_interrupt_enable.
+ */
+void FLEXIO_MCULCD_EnableInterrupts(FLEXIO_MCULCD_Type *base, uint32_t mask)
+{
+    uint32_t interrupts = 0U;
+
+    /* Enable shifter interrupts. */
+    if (mask & kFLEXIO_MCULCD_RxFullFlag)
+    {
+        interrupts |= (1U << base->rxShifterEndIndex);
+    }
+
+    if (mask & kFLEXIO_MCULCD_TxEmptyFlag)
+    {
+        interrupts |= (1U << base->txShifterStartIndex);
+    }
+
+    FLEXIO_EnableShifterStatusInterrupts(base->flexioBase, interrupts);
+}
+
+/*!
+ * brief Disables the FlexIO MCULCD interrupt.
+ *
+ * This function disables the FlexIO MCULCD interrupt.
+ *
+ * param base Pointer to the FLEXIO_MCULCD_Type structure.
+ * param mask Interrupts to disable, it is the OR'ed value of ref
+ * _flexio_mculcd_interrupt_enable.
+ */
+void FLEXIO_MCULCD_DisableInterrupts(FLEXIO_MCULCD_Type *base, uint32_t mask)
+{
+    uint32_t interrupts = 0U;
+
+    /* Disable shifter interrupts. */
+    if (mask & kFLEXIO_MCULCD_RxFullFlag)
+    {
+        interrupts |= (1U << base->rxShifterEndIndex);
+    }
+
+    if (mask & kFLEXIO_MCULCD_TxEmptyFlag)
+    {
+        interrupts |= (1U << base->txShifterStartIndex);
+    }
+
+    FLEXIO_DisableShifterStatusInterrupts(base->flexioBase, interrupts);
+}
+
+/*!
+ * brief Read data from the FLEXIO MCULCD RX shifter buffer.
+ *
+ * Read data from the RX shift buffer directly, it does no check whether the
+ * buffer is empty or not.
+ *
+ * If the data bus width is 8-bit:
+ * code
+ * uint8_t value;
+ * value = (uint8_t)FLEXIO_MCULCD_ReadData(base);
+ * endcode
+ *
+ * If the data bus width is 16-bit:
+ * code
+ * uint16_t value;
+ * value = (uint16_t)FLEXIO_MCULCD_ReadData(base);
+ * endcode
+ *
+ * note This function returns the RX shifter buffer value (32-bit) directly.
+ * The return value should be converted according to data bus width.
+ *
+ * param base Pointer to the FLEXIO_MCULCD_Type structure.
+ * return The data read out.
+ *
+ * note Don't use this function with DMA APIs.
+ */
+uint32_t FLEXIO_MCULCD_ReadData(FLEXIO_MCULCD_Type *base)
+{
+#if (8 == FLEXIO_MCULCD_DATA_BUS_WIDTH)
+    return base->flexioBase->SHIFTBUFBYS[base->rxShifterEndIndex];
+#else
+    return base->flexioBase->SHIFTBUFHWS[base->rxShifterEndIndex];
+#endif
+}
+
+/*!
+ * brief Configures the FLEXIO MCULCD to multiple beats write mode.
+ *
+ * At the begining multiple beats write operation, the FLEXIO MCULCD is configured to
+ * multiple beats write mode using this function. After write operation, the configuration
+ * is cleared by ref FLEXIO_MCULCD_ClearSingleBeatWriteConfig.
+ *
+ * param base Pointer to the FLEXIO_MCULCD_Type.
+ *
+ * note This is an internal used function, upper layer should not use.
+ */
+void FLEXIO_MCULCD_SetSingleBeatWriteConfig(FLEXIO_MCULCD_Type *base)
+{
+    /*
+     * This function will be called at the beginning of every data writing. For
+     * performance consideration, it access the FlexIO registers directly, but not
+     * call FlexIO driver APIs.
+     */
+
+    uint32_t timerCompare;
+
+    /* Enable the TX Shifter output. */
+    base->flexioBase->SHIFTCFG[base->txShifterStartIndex] =
+        FLEXIO_SHIFTCFG_PWIDTH(FLEXIO_MCULCD_DATA_BUS_WIDTH - 1U) |
+        FLEXIO_SHIFTCFG_INSRC(kFLEXIO_ShifterInputFromNextShifterOutput);
+
+    base->flexioBase->SHIFTCTL[base->txShifterStartIndex] =
+        FLEXIO_SHIFTCTL_TIMSEL(base->timerIndex) | FLEXIO_SHIFTCTL_TIMPOL(kFLEXIO_ShifterTimerPolarityOnPositive) |
+        FLEXIO_SHIFTCTL_PINCFG(kFLEXIO_PinConfigOutput) | FLEXIO_SHIFTCTL_PINSEL(base->dataPinStartIndex) |
+        FLEXIO_SHIFTCTL_PINPOL(kFLEXIO_PinActiveHigh) | FLEXIO_SHIFTCTL_SMOD(kFLEXIO_ShifterModeTransmit);
+
+    timerCompare = base->flexioBase->TIMCMP[base->timerIndex] & 0xFFU;
+
+    /*
+     * TIMCMP[15:8] = (number of beats x 2) - 1. Because the number of beat is 1,
+     * so the TIMCMP[15:8] is 1.
+     */
+    base->flexioBase->TIMCMP[base->timerIndex] = (1U << 8U) | timerCompare;
+
+    /* Use TX shifter flag as the inverted timer trigger. Timer output to WR/EN pin. */
+    base->flexioBase->TIMCFG[base->timerIndex] =
+        FLEXIO_TIMCFG_TIMOUT(kFLEXIO_TimerOutputOneNotAffectedByReset) |
+        FLEXIO_TIMCFG_TIMDEC(kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput) |
+        FLEXIO_TIMCFG_TIMRST(kFLEXIO_TimerResetNever) | FLEXIO_TIMCFG_TIMDIS(kFLEXIO_TimerDisableOnTimerCompare) |
+        FLEXIO_TIMCFG_TIMENA(kFLEXIO_TimerEnableOnTriggerHigh) | FLEXIO_TIMCFG_TSTOP(kFLEXIO_TimerStopBitDisabled) |
+        FLEXIO_TIMCFG_TSTART(kFLEXIO_TimerStartBitDisabled);
+
+    base->flexioBase->TIMCTL[base->timerIndex] =
+        FLEXIO_TIMCTL_TRGSEL(FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->txShifterStartIndex)) |
+        FLEXIO_TIMCTL_TRGPOL(kFLEXIO_TimerTriggerPolarityActiveLow) |
+        FLEXIO_TIMCTL_TRGSRC(kFLEXIO_TimerTriggerSourceInternal) | FLEXIO_TIMCTL_PINCFG(kFLEXIO_PinConfigOutput) |
+        FLEXIO_TIMCTL_PINSEL(base->ENWRPinIndex) | FLEXIO_TIMCTL_PINPOL(kFLEXIO_PinActiveLow) |
+        FLEXIO_TIMCTL_TIMOD(kFLEXIO_TimerModeDual8BitBaudBit);
+}
+
+/*!
+ * brief Clear the FLEXIO MCULCD multiple beats write mode configuration.
+ *
+ * Clear the write configuration set by ref FLEXIO_MCULCD_SetSingleBeatWriteConfig.
+ *
+ * param base Pointer to the FLEXIO_MCULCD_Type.
+ *
+ * note This is an internal used function, upper layer should not use.
+ */
+void FLEXIO_MCULCD_ClearSingleBeatWriteConfig(FLEXIO_MCULCD_Type *base)
+{
+    /* Disable the timer. */
+    base->flexioBase->TIMCTL[base->timerIndex] = 0U;
+    base->flexioBase->TIMCFG[base->timerIndex] = 0U;
+    /* Clear the timer flag. */
+    base->flexioBase->TIMSTAT = (1U << base->timerIndex);
+    /* Stop the TX shifter. */
+    base->flexioBase->SHIFTCTL[base->txShifterStartIndex] = 0U;
+    base->flexioBase->SHIFTCFG[base->txShifterStartIndex] = 0U;
+    /* Clear the shifter flag. */
+    base->flexioBase->SHIFTSTAT = (1U << base->txShifterStartIndex);
+}
+
+/*!
+ * brief Configures the FLEXIO MCULCD to multiple beats read mode.
+ *
+ * At the begining or multiple beats read operation, the FLEXIO MCULCD is configured
+ * to multiple beats read mode using this function. After read operation, the configuration
+ * is cleared by ref FLEXIO_MCULCD_ClearSingleBeatReadConfig.
+ *
+ * param base Pointer to the FLEXIO_MCULCD_Type.
+ *
+ * note This is an internal used function, upper layer should not use.
+ */
+void FLEXIO_MCULCD_SetSingleBeatReadConfig(FLEXIO_MCULCD_Type *base)
+{
+    /*
+     * This function will be called at the beginning of every data reading. For
+     * performance consideration, it access the FlexIO registers directly, but not
+     * call FlexIO driver APIs.
+     */
+
+    uint8_t timerPin;
+    uint32_t timerCompare;
+    flexio_pin_polarity_t timerPinPolarity;
+
+    /* Timer output to RD pin (8080 mode), to WR/EN pin in 6800 mode. */
+    if (kFLEXIO_MCULCD_8080 == base->busType)
+    {
+        timerPin         = base->RDPinIndex;
+        timerPinPolarity = kFLEXIO_PinActiveLow;
+    }
+    else
+    {
+        timerPin         = base->ENWRPinIndex;
+        timerPinPolarity = kFLEXIO_PinActiveHigh;
+    }
+
+    /* Enable the RX Shifter input. */
+    base->flexioBase->SHIFTCFG[base->rxShifterEndIndex] = FLEXIO_SHIFTCFG_PWIDTH(FLEXIO_MCULCD_DATA_BUS_WIDTH - 1U);
+
+    base->flexioBase->SHIFTCTL[base->rxShifterEndIndex] =
+        FLEXIO_SHIFTCTL_TIMSEL(base->timerIndex) | FLEXIO_SHIFTCTL_TIMPOL(kFLEXIO_ShifterTimerPolarityOnNegitive) |
+        FLEXIO_SHIFTCTL_PINCFG(kFLEXIO_PinConfigOutputDisabled) | FLEXIO_SHIFTCTL_PINSEL(base->dataPinStartIndex) |
+        FLEXIO_SHIFTCTL_PINPOL(kFLEXIO_PinActiveHigh) | FLEXIO_SHIFTCTL_SMOD(kFLEXIO_ShifterModeReceive);
+
+    /* Use RX shifter flag as the inverted timer trigger. */
+    base->flexioBase->TIMCFG[base->timerIndex] =
+        FLEXIO_TIMCFG_TIMOUT(kFLEXIO_TimerOutputOneNotAffectedByReset) |
+        FLEXIO_TIMCFG_TIMDEC(kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput) |
+        FLEXIO_TIMCFG_TIMRST(kFLEXIO_TimerResetNever) | FLEXIO_TIMCFG_TIMDIS(kFLEXIO_TimerDisableOnTimerCompare) |
+        FLEXIO_TIMCFG_TIMENA(kFLEXIO_TimerEnableOnTriggerHigh) |
+        FLEXIO_TIMCFG_TSTOP(kFLEXIO_TimerStopBitEnableOnTimerDisable) |
+        FLEXIO_TIMCFG_TSTART(kFLEXIO_TimerStartBitDisabled);
+
+    timerCompare = base->flexioBase->TIMCMP[base->timerIndex] & 0xFFU;
+
+    /*
+     * TIMCMP[15:8] = (number of beats x 2) - 1. Because the number of beat is 1,
+     * so the TIMCMP[15:8] is 1.
+     */
+    base->flexioBase->TIMCMP[base->timerIndex] = (1U << 8U) | timerCompare;
+
+    base->flexioBase->TIMCTL[base->timerIndex] |=
+        FLEXIO_TIMCTL_TRGSEL(FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->rxShifterEndIndex)) |
+        FLEXIO_TIMCTL_TRGPOL(kFLEXIO_TimerTriggerPolarityActiveLow) |
+        FLEXIO_TIMCTL_TRGSRC(kFLEXIO_TimerTriggerSourceInternal) | FLEXIO_TIMCTL_PINCFG(kFLEXIO_PinConfigOutput) |
+        FLEXIO_TIMCTL_PINSEL(timerPin) | FLEXIO_TIMCTL_PINPOL(timerPinPolarity) |
+        FLEXIO_TIMCTL_TIMOD(kFLEXIO_TimerModeDual8BitBaudBit);
+}
+
+/*!
+ * brief Clear the FLEXIO MCULCD multiple beats read mode configuration.
+ *
+ * Clear the read configuration set by ref FLEXIO_MCULCD_SetSingleBeatReadConfig.
+ *
+ * param base Pointer to the FLEXIO_MCULCD_Type.
+ *
+ * note This is an internal used function, upper layer should not use.
+ */
+void FLEXIO_MCULCD_ClearSingleBeatReadConfig(FLEXIO_MCULCD_Type *base)
+{
+    /* Disable the timer. */
+    base->flexioBase->TIMCTL[base->timerIndex] = 0U;
+    base->flexioBase->TIMCFG[base->timerIndex] = 0U;
+    /* Clear the timer flag. */
+    base->flexioBase->TIMSTAT = (1U << base->timerIndex);
+    /* Stop the RX shifter. */
+    base->flexioBase->SHIFTCTL[base->rxShifterEndIndex] = 0U;
+    base->flexioBase->SHIFTCFG[base->rxShifterEndIndex] = 0U;
+    /* Clear the shifter flag. */
+    base->flexioBase->SHIFTSTAT = (1U << base->rxShifterEndIndex);
+}
+
+/*!
+ * brief Configures the FLEXIO MCULCD to multiple beats write mode.
+ *
+ * At the begining multiple beats write operation, the FLEXIO MCULCD is configured to
+ * multiple beats write mode using this function. After write operation, the configuration
+ * is cleared by ref FLEXIO_MCULCD_ClearMultBeatsWriteConfig.
+ *
+ * param base Pointer to the FLEXIO_MCULCD_Type.
+ *
+ * note This is an internal used function, upper layer should not use.
+ */
+void FLEXIO_MCULCD_SetMultiBeatsWriteConfig(FLEXIO_MCULCD_Type *base)
+{
+    /*
+     * This function will be called at the beginning of every data writing. For
+     * performance consideration, it access the FlexIO registers directly, but not
+     * call FlexIO driver APIs.
+     */
+
+    uint32_t timerCompare;
+    uint8_t beats;
+    uint8_t i;
+
+    /* Enable the TX Shifter output. */
+    base->flexioBase->SHIFTCFG[base->txShifterStartIndex] =
+        FLEXIO_SHIFTCFG_PWIDTH(FLEXIO_MCULCD_DATA_BUS_WIDTH - 1U) |
+        FLEXIO_SHIFTCFG_INSRC(kFLEXIO_ShifterInputFromNextShifterOutput);
+
+    base->flexioBase->SHIFTCTL[base->txShifterStartIndex] =
+        FLEXIO_SHIFTCTL_TIMSEL(base->timerIndex) | FLEXIO_SHIFTCTL_TIMPOL(kFLEXIO_ShifterTimerPolarityOnPositive) |
+        FLEXIO_SHIFTCTL_PINCFG(kFLEXIO_PinConfigOutput) | FLEXIO_SHIFTCTL_PINSEL(base->dataPinStartIndex) |
+        FLEXIO_SHIFTCTL_PINPOL(kFLEXIO_PinActiveHigh) | FLEXIO_SHIFTCTL_SMOD(kFLEXIO_ShifterModeTransmit);
+
+    for (i = base->txShifterStartIndex + 1U; i <= base->txShifterEndIndex; i++)
+    {
+        base->flexioBase->SHIFTCFG[i] = FLEXIO_SHIFTCFG_PWIDTH(FLEXIO_MCULCD_DATA_BUS_WIDTH - 1U) |
+                                        FLEXIO_SHIFTCFG_INSRC(kFLEXIO_ShifterInputFromNextShifterOutput);
+
+        base->flexioBase->SHIFTCTL[i] =
+            FLEXIO_SHIFTCTL_TIMSEL(base->timerIndex) | FLEXIO_SHIFTCTL_TIMPOL(kFLEXIO_ShifterTimerPolarityOnPositive) |
+            FLEXIO_SHIFTCTL_PINCFG(kFLEXIO_PinConfigOutputDisabled) | FLEXIO_SHIFTCTL_PINSEL(0) |
+            FLEXIO_SHIFTCTL_PINPOL(kFLEXIO_PinActiveHigh) | FLEXIO_SHIFTCTL_SMOD(kFLEXIO_ShifterModeTransmit);
+    }
+
+    timerCompare = base->flexioBase->TIMCMP[base->timerIndex] & 0xFFU;
+
+#if (8 == FLEXIO_MCULCD_DATA_BUS_WIDTH)
+    beats = 4U * (base->txShifterEndIndex - base->txShifterStartIndex + 1U);
+#else
+    beats = 2U * (base->txShifterEndIndex - base->txShifterStartIndex + 1U);
+#endif
+
+    /*
+     * TIMCMP[15:8] = (number of beats x 2) - 1.
+     */
+    base->flexioBase->TIMCMP[base->timerIndex] = ((beats * 2U - 1U) << 8U) | timerCompare;
+
+    /* Use TX shifter flag as the inverted timer trigger. Timer output to WR/EN pin. */
+    base->flexioBase->TIMCFG[base->timerIndex] =
+        FLEXIO_TIMCFG_TIMOUT(kFLEXIO_TimerOutputOneNotAffectedByReset) |
+        FLEXIO_TIMCFG_TIMDEC(kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput) |
+        FLEXIO_TIMCFG_TIMRST(kFLEXIO_TimerResetNever) | FLEXIO_TIMCFG_TIMDIS(kFLEXIO_TimerDisableOnTimerCompare) |
+        FLEXIO_TIMCFG_TIMENA(kFLEXIO_TimerEnableOnTriggerHigh) | FLEXIO_TIMCFG_TSTOP(kFLEXIO_TimerStopBitDisabled) |
+        FLEXIO_TIMCFG_TSTART(kFLEXIO_TimerStartBitDisabled);
+
+    base->flexioBase->TIMCTL[base->timerIndex] =
+        FLEXIO_TIMCTL_TRGSEL(FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->txShifterEndIndex)) |
+        FLEXIO_TIMCTL_TRGPOL(kFLEXIO_TimerTriggerPolarityActiveLow) |
+        FLEXIO_TIMCTL_TRGSRC(kFLEXIO_TimerTriggerSourceInternal) | FLEXIO_TIMCTL_PINCFG(kFLEXIO_PinConfigOutput) |
+        FLEXIO_TIMCTL_PINSEL(base->ENWRPinIndex) | FLEXIO_TIMCTL_PINPOL(kFLEXIO_PinActiveLow) |
+        FLEXIO_TIMCTL_TIMOD(kFLEXIO_TimerModeDual8BitBaudBit);
+}
+
+/*!
+ * brief Clear the FLEXIO MCULCD multiple beats write mode configuration.
+ *
+ * Clear the write configuration set by ref FLEXIO_MCULCD_SetMultBeatsWriteConfig.
+ *
+ * param base Pointer to the FLEXIO_MCULCD_Type.
+ *
+ * note This is an internal used function, upper layer should not use.
+ */
+void FLEXIO_MCULCD_ClearMultiBeatsWriteConfig(FLEXIO_MCULCD_Type *base)
+{
+    uint8_t i;
+    uint32_t statusFlags = 0U;
+
+    /* Disable the timer. */
+    base->flexioBase->TIMCTL[base->timerIndex] = 0U;
+    base->flexioBase->TIMCFG[base->timerIndex] = 0U;
+    /* Clear the timer flag. */
+    base->flexioBase->TIMSTAT = (1U << base->timerIndex);
+
+    /* Stop the TX shifter. */
+    for (i = base->txShifterStartIndex; i <= base->txShifterEndIndex; i++)
+    {
+        base->flexioBase->SHIFTCFG[i] = 0U;
+        base->flexioBase->SHIFTCTL[i] = 0U;
+        statusFlags |= (1U << i);
+    }
+    /* Clear the shifter flag. */
+    base->flexioBase->SHIFTSTAT = statusFlags;
+}
+
+/*!
+ * brief Configures the FLEXIO MCULCD to multiple beats read mode.
+ *
+ * At the begining or multiple beats read operation, the FLEXIO MCULCD is configured
+ * to multiple beats read mode using this function. After read operation, the configuration
+ * is cleared by ref FLEXIO_MCULCD_ClearMultBeatsReadConfig.
+ *
+ * param base Pointer to the FLEXIO_MCULCD_Type.
+ *
+ * note This is an internal used function, upper layer should not use.
+ */
+void FLEXIO_MCULCD_SetMultiBeatsReadConfig(FLEXIO_MCULCD_Type *base)
+{
+    /*
+     * This function will be called at the beginning of every data reading. For
+     * performance consideration, it access the FlexIO registers directly, but not
+     * call FlexIO driver APIs.
+     */
+
+    uint8_t timerPin;
+    uint8_t beats;
+    uint8_t i;
+    uint32_t timerCompare;
+    flexio_pin_polarity_t timerPinPolarity;
+
+    /* Timer output to RD pin (8080 mode), to WR/EN pin in 6800 mode. */
+    if (kFLEXIO_MCULCD_8080 == base->busType)
+    {
+        timerPin         = base->RDPinIndex;
+        timerPinPolarity = kFLEXIO_PinActiveLow;
+    }
+    else
+    {
+        timerPin         = base->ENWRPinIndex;
+        timerPinPolarity = kFLEXIO_PinActiveHigh;
+    }
+
+    /* Enable the RX Shifter input. */
+    for (i = base->rxShifterStartIndex; i < base->rxShifterEndIndex; i++)
+    {
+        base->flexioBase->SHIFTCFG[i] = FLEXIO_SHIFTCFG_PWIDTH(FLEXIO_MCULCD_DATA_BUS_WIDTH - 1U) |
+                                        FLEXIO_SHIFTCFG_INSRC(kFLEXIO_ShifterInputFromNextShifterOutput);
+
+        base->flexioBase->SHIFTCTL[i] =
+            FLEXIO_SHIFTCTL_TIMSEL(base->timerIndex) | FLEXIO_SHIFTCTL_TIMPOL(kFLEXIO_ShifterTimerPolarityOnNegitive) |
+            FLEXIO_SHIFTCTL_PINCFG(kFLEXIO_PinConfigOutputDisabled) | FLEXIO_SHIFTCTL_PINSEL(base->dataPinStartIndex) |
+            FLEXIO_SHIFTCTL_PINPOL(kFLEXIO_PinActiveHigh) | FLEXIO_SHIFTCTL_SMOD(kFLEXIO_ShifterModeReceive);
+    }
+
+    base->flexioBase->SHIFTCFG[base->rxShifterEndIndex] = FLEXIO_SHIFTCFG_PWIDTH(FLEXIO_MCULCD_DATA_BUS_WIDTH - 1U);
+    base->flexioBase->SHIFTCTL[base->rxShifterEndIndex] =
+        FLEXIO_SHIFTCTL_TIMSEL(base->timerIndex) | FLEXIO_SHIFTCTL_TIMPOL(kFLEXIO_ShifterTimerPolarityOnNegitive) |
+        FLEXIO_SHIFTCTL_PINCFG(kFLEXIO_PinConfigOutputDisabled) | FLEXIO_SHIFTCTL_PINSEL(base->dataPinStartIndex) |
+        FLEXIO_SHIFTCTL_PINPOL(kFLEXIO_PinActiveHigh) | FLEXIO_SHIFTCTL_SMOD(kFLEXIO_ShifterModeReceive);
+
+    timerCompare = base->flexioBase->TIMCMP[base->timerIndex] & 0xFFU;
+
+#if (8 == FLEXIO_MCULCD_DATA_BUS_WIDTH)
+    beats = 4U * (base->rxShifterEndIndex - base->rxShifterStartIndex + 1U);
+#else
+    beats = 2U * (base->rxShifterEndIndex - base->rxShifterStartIndex + 1U);
+#endif
+
+    /*
+     * TIMCMP[15:8] = (number of beats x 2) - 1.
+     */
+    base->flexioBase->TIMCMP[base->timerIndex] = ((beats * 2U - 1U) << 8U) | timerCompare;
+
+    /* Use RX shifter flag as the inverted timer trigger. */
+    base->flexioBase->TIMCFG[base->timerIndex] =
+        FLEXIO_TIMCFG_TIMOUT(kFLEXIO_TimerOutputOneNotAffectedByReset) |
+        FLEXIO_TIMCFG_TIMDEC(kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput) |
+        FLEXIO_TIMCFG_TIMRST(kFLEXIO_TimerResetNever) | FLEXIO_TIMCFG_TIMDIS(kFLEXIO_TimerDisableOnTimerCompare) |
+        FLEXIO_TIMCFG_TIMENA(kFLEXIO_TimerEnableOnTriggerHigh) |
+        FLEXIO_TIMCFG_TSTOP(kFLEXIO_TimerStopBitEnableOnTimerDisable) |
+        FLEXIO_TIMCFG_TSTART(kFLEXIO_TimerStartBitDisabled);
+
+    base->flexioBase->TIMCTL[base->timerIndex] |=
+        FLEXIO_TIMCTL_TRGSEL(FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->rxShifterEndIndex)) |
+        FLEXIO_TIMCTL_TRGPOL(kFLEXIO_TimerTriggerPolarityActiveLow) |
+        FLEXIO_TIMCTL_TRGSRC(kFLEXIO_TimerTriggerSourceInternal) | FLEXIO_TIMCTL_PINCFG(kFLEXIO_PinConfigOutput) |
+        FLEXIO_TIMCTL_PINSEL(timerPin) | FLEXIO_TIMCTL_PINPOL(timerPinPolarity) |
+        FLEXIO_TIMCTL_TIMOD(kFLEXIO_TimerModeDual8BitBaudBit);
+}
+
+/*!
+ * brief Clear the FLEXIO MCULCD multiple beats read mode configuration.
+ *
+ * Clear the read configuration set by ref FLEXIO_MCULCD_SetMultBeatsReadConfig.
+ *
+ * param base Pointer to the FLEXIO_MCULCD_Type.
+ *
+ * note This is an internal used function, upper layer should not use.
+ */
+void FLEXIO_MCULCD_ClearMultiBeatsReadConfig(FLEXIO_MCULCD_Type *base)
+{
+    uint8_t i;
+    uint32_t statusFlags = 0U;
+
+    /* Disable the timer. */
+    base->flexioBase->TIMCTL[base->timerIndex] = 0U;
+    base->flexioBase->TIMCFG[base->timerIndex] = 0U;
+    /* Clear the timer flag. */
+    base->flexioBase->TIMSTAT = (1U << base->timerIndex);
+    /* Stop the RX shifter. */
+    for (i = base->rxShifterStartIndex; i <= base->rxShifterEndIndex; i++)
+    {
+        base->flexioBase->SHIFTCTL[i] = 0U;
+        base->flexioBase->SHIFTCFG[i] = 0U;
+        statusFlags |= (1U << i);
+    }
+    /* Clear the shifter flag. */
+    base->flexioBase->SHIFTSTAT = statusFlags;
+}
+
+/*!
+ * brief Wait for transmit data send out finished.
+ *
+ * Currently there is no effective method to wait for the data send out
+ * from the shiter, so here use a while loop to wait.
+ *
+ * note This is an internal used function.
+ */
+void FLEXIO_MCULCD_WaitTransmitComplete(void)
+{
+    uint32_t i = FLEXIO_MCULCD_WAIT_COMPLETE_TIME;
+
+    while (i--)
+    {
+        __NOP();
+    }
+}
+
+/*!
+ * brief Send command in blocking way.
+ *
+ * This function sends the command and returns when the command has been sent
+ * out.
+ *
+ * param base Pointer to the FLEXIO_MCULCD_Type structure.
+ * param command The command to send.
+ */
+void FLEXIO_MCULCD_WriteCommandBlocking(FLEXIO_MCULCD_Type *base, uint32_t command)
+{
+    FLEXIO_Type *flexioBase = base->flexioBase;
+
+    /* De-assert the RS pin. */
+    base->setRSPin(false);
+
+    /* For 6800, de-assert the RDWR pin. */
+    if (kFLEXIO_MCULCD_6800 == base->busType)
+    {
+        base->setRDWRPin(false);
+    }
+
+    /* Configure the timer and TX shifter. */
+    FLEXIO_MCULCD_SetSingleBeatWriteConfig(base);
+
+    /* Write command to shifter buffer. */
+    flexioBase->SHIFTBUF[base->txShifterStartIndex] = command;
+
+    /* Wait for command send out. */
+    while (!((1U << base->timerIndex) & FLEXIO_GetTimerStatusFlags(flexioBase)))
+    {
+    }
+
+    /* Stop the timer and TX shifter. */
+    FLEXIO_MCULCD_ClearSingleBeatWriteConfig(base);
+
+    /* Assert the RS pin. */
+    base->setRSPin(true);
+    /* For 6800, assert the RDWR pin. */
+    if (kFLEXIO_MCULCD_6800 == base->busType)
+    {
+        base->setRDWRPin(true);
+    }
+}
+
+/*!
+ * brief Send data array in blocking way.
+ *
+ * This function sends the data array and returns when the data sent out.
+ *
+ * param base Pointer to the FLEXIO_MCULCD_Type structure.
+ * param data The data array to send.
+ * param size How many bytes to write.
+ */
+void FLEXIO_MCULCD_WriteDataArrayBlocking(FLEXIO_MCULCD_Type *base, void *data, size_t size)
+{
+    assert(size);
+
+    uint32_t i;
+#if (8 == FLEXIO_MCULCD_DATA_BUS_WIDTH)
+    uint8_t *data8Bit;
+#else
+    uint16_t *data16Bit;
+#endif
+    FLEXIO_Type *flexioBase = base->flexioBase;
+
+    /* Assert the RS pin. */
+    base->setRSPin(true);
+    /* For 6800, de-assert the RDWR pin. */
+    if (kFLEXIO_MCULCD_6800 == base->busType)
+    {
+        base->setRDWRPin(false);
+    }
+
+    /* Configure the timer and TX shifter. */
+    FLEXIO_MCULCD_SetSingleBeatWriteConfig(base);
+
+/* If data bus width is 8. */
+#if (8 == FLEXIO_MCULCD_DATA_BUS_WIDTH)
+    data8Bit = (uint8_t *)data;
+
+    for (i = 0; i < size; i++)
+    {
+        flexioBase->SHIFTBUF[base->txShifterStartIndex] = data8Bit[i];
+
+        /* Wait for the data send out. */
+        while (!((1U << base->timerIndex) & flexioBase->TIMSTAT))
+        {
+        }
+
+        /* Clear the timer stat. */
+        flexioBase->TIMSTAT = 1U << base->timerIndex;
+    }
+#else
+    data16Bit = (uint16_t *)data;
+    size /= 2;
+
+    for (i = 0; i < size; i++)
+    {
+        flexioBase->SHIFTBUF[base->txShifterStartIndex] = data16Bit[i];
+
+        /* Wait for the data send out. */
+        while (!((1U << base->timerIndex) & flexioBase->TIMSTAT))
+        {
+        }
+
+        /* Clear the timer stat. */
+        flexioBase->TIMSTAT = 1U << base->timerIndex;
+    }
+#endif
+
+    /* Stop the timer and TX shifter. */
+    FLEXIO_MCULCD_ClearSingleBeatWriteConfig(base);
+}
+
+/*!
+ * brief Read data into array in blocking way.
+ *
+ * This function reads the data into array and returns when the data read
+ * finished.
+ *
+ * param base Pointer to the FLEXIO_MCULCD_Type structure.
+ * param data The array to save the data.
+ * param size How many bytes to read.
+ */
+void FLEXIO_MCULCD_ReadDataArrayBlocking(FLEXIO_MCULCD_Type *base, void *data, size_t size)
+{
+    assert(size);
+
+    uint32_t i;
+
+#if (8 == FLEXIO_MCULCD_DATA_BUS_WIDTH)
+    uint8_t *data8Bit = (uint8_t *)data;
+#else
+    uint16_t *data16Bit = (uint16_t *)data;
+#endif
+    FLEXIO_Type *flexioBase = base->flexioBase;
+
+    /* Assert the RS pin. */
+    base->setRSPin(true);
+    /* For 6800, de-assert the RDWR pin. */
+    if (kFLEXIO_MCULCD_6800 == base->busType)
+    {
+        base->setRDWRPin(false);
+    }
+
+    /* Enable the timer and RX shifter. */
+    FLEXIO_MCULCD_SetSingleBeatReadConfig(base);
+
+/* If data bus width is 8. */
+#if (8 == FLEXIO_MCULCD_DATA_BUS_WIDTH)
+    for (i = 0; i < (size - 1); i++)
+    {
+        /* Wait for shifter buffer full. */
+        while (!((1U << base->rxShifterEndIndex) & FLEXIO_GetShifterStatusFlags(flexioBase)))
+        {
+        }
+
+        data8Bit[i] = (uint8_t)flexioBase->SHIFTBUFBYS[base->rxShifterEndIndex];
+    }
+#else
+    /* Data bus width is 16. */
+    size /= 2;
+
+    for (i = 0; i < (size - 1); i++)
+    {
+        /* Wait for shifter buffer full. */
+        while (!((1U << base->rxShifterEndIndex) & FLEXIO_GetShifterStatusFlags(flexioBase)))
+        {
+        }
+
+        data16Bit[i] = (uint16_t)flexioBase->SHIFTBUFHWS[base->rxShifterEndIndex];
+    }
+#endif
+
+    /* Wait for shifter buffer full. */
+    while (!((1U << base->rxShifterEndIndex) & FLEXIO_GetShifterStatusFlags(flexioBase)))
+    {
+    }
+
+    /* Stop the timer and disable the RX shifter. */
+    FLEXIO_MCULCD_ClearSingleBeatReadConfig(base);
+
+/* Read out the last data. */
+#if (8 == FLEXIO_MCULCD_DATA_BUS_WIDTH)
+    data8Bit[i] = (uint8_t)flexioBase->SHIFTBUFBYS[base->rxShifterEndIndex];
+#else
+    data16Bit[i] = (uint16_t)flexioBase->SHIFTBUFHWS[base->rxShifterEndIndex];
+#endif
+}
+
+/*!
+ * brief Send the same value many times in blocking way.
+ *
+ * This function sends the same value many times. It could be used to clear the
+ * LCD screen. If the data bus width is 8, this function will send LSB 8 bits of
+ * p sameValue for p size times. If the data bus is 16, this function will send
+ * LSB 16 bits of p sameValue for p size / 2 times.
+ *
+ * param base Pointer to the FLEXIO_MCULCD_Type structure.
+ * param sameValue The same value to send.
+ * param size How many bytes to send.
+ */
+void FLEXIO_MCULCD_WriteSameValueBlocking(FLEXIO_MCULCD_Type *base, uint32_t sameValue, size_t size)
+{
+    assert(size);
+
+    uint32_t i;
+    FLEXIO_Type *flexioBase = base->flexioBase;
+
+#if (16 == FLEXIO_MCULCD_DATA_BUS_WIDTH)
+    size /= 2;
+#endif
+
+    /* Assert the RS pin. */
+    base->setRSPin(true);
+    /* For 6800, de-assert the RDWR pin. */
+    if (kFLEXIO_MCULCD_6800 == base->busType)
+    {
+        base->setRDWRPin(false);
+    }
+
+    /* Configure the timer and TX shifter. */
+    FLEXIO_MCULCD_SetSingleBeatWriteConfig(base);
+
+    for (i = 0; i < size; i++)
+    {
+        flexioBase->SHIFTBUF[base->txShifterStartIndex] = sameValue;
+
+        /* Wait for the data send out. */
+        while (!((1U << base->timerIndex) & flexioBase->TIMSTAT))
+        {
+        }
+
+        /* Clear the timer stat. */
+        flexioBase->TIMSTAT = 1U << base->timerIndex;
+    }
+
+    /* Stop the timer and TX shifter. */
+    FLEXIO_MCULCD_ClearSingleBeatWriteConfig(base);
+}
+
+/*!
+ * brief Performs a polling transfer.
+ *
+ * note The API does not return until the transfer finished.
+ *
+ * param base pointer to FLEXIO_MCULCD_Type structure.
+ * param xfer pointer to flexio_mculcd_transfer_t structure.
+ */
+void FLEXIO_MCULCD_TransferBlocking(FLEXIO_MCULCD_Type *base, flexio_mculcd_transfer_t *xfer)
+{
+    FLEXIO_MCULCD_StartTransfer(base);
+
+    FLEXIO_MCULCD_WriteCommandBlocking(base, xfer->command);
+
+    if (xfer->dataSize > 0)
+    {
+        if (kFLEXIO_MCULCD_ReadArray == xfer->mode)
+        {
+            FLEXIO_MCULCD_ReadDataArrayBlocking(base, (void *)(xfer->dataAddrOrSameValue), xfer->dataSize);
+        }
+        else if (kFLEXIO_MCULCD_WriteArray == xfer->mode)
+        {
+            FLEXIO_MCULCD_WriteDataArrayBlocking(base, (void *)(xfer->dataAddrOrSameValue), xfer->dataSize);
+        }
+        else
+        {
+            FLEXIO_MCULCD_WriteSameValueBlocking(base, xfer->dataAddrOrSameValue, xfer->dataSize);
+        }
+    }
+
+    FLEXIO_MCULCD_StopTransfer(base);
+}
+
+/*!
+ * brief Initializes the FlexIO MCULCD handle, which is used in transactional
+ * functions.
+ *
+ * param base Pointer to the FLEXIO_MCULCD_Type structure.
+ * param handle Pointer to the flexio_mculcd_handle_t structure to store the
+ * transfer state.
+ * param callback The callback function.
+ * param userData The parameter of the callback function.
+ * retval kStatus_Success Successfully create the handle.
+ * retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range.
+ */
+status_t FLEXIO_MCULCD_TransferCreateHandle(FLEXIO_MCULCD_Type *base,
+                                            flexio_mculcd_handle_t *handle,
+                                            flexio_mculcd_transfer_callback_t callback,
+                                            void *userData)
+{
+    assert(handle);
+
+    IRQn_Type flexio_irqs[] = FLEXIO_IRQS;
+
+    /* Zero the handle. */
+    memset(handle, 0, sizeof(*handle));
+
+    handle->state = kFLEXIO_MCULCD_StateIdle;
+
+    /* Register callback and userData. */
+    handle->completionCallback = callback;
+    handle->userData           = userData;
+
+    /* Enable interrupt in NVIC. */
+    EnableIRQ(flexio_irqs[FLEXIO_GetInstance(base->flexioBase)]);
+
+    /* Save the context in global variables to support the double weak mechanism.
+     */
+    return FLEXIO_RegisterHandleIRQ(base, handle, FLEXIO_MCULCD_TransferHandleIRQ);
+}
+
+/*!
+ * brief Transfer data using IRQ.
+ *
+ * This function sends data using IRQ. This is a non-blocking function, which
+ * returns right away. When all data is sent out/received, the callback
+ * function is called.
+ *
+ * param base Pointer to the FLEXIO_MCULCD_Type structure.
+ * param handle Pointer to the flexio_mculcd_handle_t structure to store the
+ * transfer state.
+ * param xfer FlexIO MCULCD transfer structure. See #flexio_mculcd_transfer_t.
+ * retval kStatus_Success Successfully start a transfer.
+ * retval kStatus_InvalidArgument Input argument is invalid.
+ * retval kStatus_FLEXIO_MCULCD_Busy MCULCD is busy with another transfer.
+ */
+status_t FLEXIO_MCULCD_TransferNonBlocking(FLEXIO_MCULCD_Type *base,
+                                           flexio_mculcd_handle_t *handle,
+                                           flexio_mculcd_transfer_t *xfer)
+{
+    /* If previous transfer is in progress. */
+    if (kFLEXIO_MCULCD_StateIdle != handle->state)
+    {
+        return kStatus_FLEXIO_MCULCD_Busy;
+    }
+
+    /* Set the state in handle. */
+    if (kFLEXIO_MCULCD_ReadArray == xfer->mode)
+    {
+        handle->state = kFLEXIO_MCULCD_StateReadArray;
+    }
+    else if (kFLEXIO_MCULCD_WriteArray == xfer->mode)
+    {
+        handle->state = kFLEXIO_MCULCD_StateWriteArray;
+    }
+    else
+    {
+        handle->state = kFLEXIO_MCULCD_StateWriteSameValue;
+    }
+
+    /* Assert the nCS. */
+    FLEXIO_MCULCD_StartTransfer(base);
+
+    /* Send the command. */
+    FLEXIO_MCULCD_WriteCommandBlocking(base, xfer->command);
+
+    /* If transfer count is 0 (only to send command), return directly. */
+    if (0U == xfer->dataSize)
+    {
+        handle->state = kFLEXIO_MCULCD_StateIdle;
+
+        /* De-assert the nCS. */
+        FLEXIO_MCULCD_StopTransfer(base);
+
+        if (handle->completionCallback)
+        {
+            handle->completionCallback(base, handle, kStatus_FLEXIO_MCULCD_Idle, handle->userData);
+        }
+    }
+    else
+    {
+#if (8 == FLEXIO_MCULCD_DATA_BUS_WIDTH)
+        handle->dataCount = xfer->dataSize;
+#else
+        handle->dataCount = xfer->dataSize / 2;
+#endif
+
+        handle->remainingCount = handle->dataCount;
+
+        handle->dataAddrOrSameValue = xfer->dataAddrOrSameValue;
+
+        /* Enable interrupt. */
+        if (kFLEXIO_MCULCD_ReadArray == xfer->mode)
+        {
+            /* For 6800, assert the RDWR pin. */
+            if (kFLEXIO_MCULCD_6800 == base->busType)
+            {
+                base->setRDWRPin(true);
+            }
+            FLEXIO_MCULCD_SetSingleBeatReadConfig(base);
+            FLEXIO_MCULCD_EnableInterrupts(base, kFLEXIO_MCULCD_RxFullInterruptEnable);
+        }
+        else
+        {
+            /* For 6800, de-assert the RDWR pin. */
+            if (kFLEXIO_MCULCD_6800 == base->busType)
+            {
+                base->setRDWRPin(false);
+            }
+            FLEXIO_MCULCD_SetSingleBeatWriteConfig(base);
+            FLEXIO_MCULCD_EnableInterrupts(base, kFLEXIO_MCULCD_TxEmptyInterruptEnable);
+        }
+    }
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Aborts the data transfer, which used IRQ.
+ *
+ * param base Pointer to the FLEXIO_MCULCD_Type structure.
+ * param handle Pointer to the flexio_mculcd_handle_t structure to store the
+ * transfer state.
+ */
+void FLEXIO_MCULCD_TransferAbort(FLEXIO_MCULCD_Type *base, flexio_mculcd_handle_t *handle)
+{
+    /* If no transfer in process, return directly. */
+    if (kFLEXIO_MCULCD_StateIdle == handle->state)
+    {
+        return;
+    }
+
+    /* Disable the interrupt. */
+    FLEXIO_MCULCD_DisableInterrupts(base, kFLEXIO_MCULCD_RxFullInterruptEnable | kFLEXIO_MCULCD_TxEmptyInterruptEnable);
+
+    if (kFLEXIO_MCULCD_ReadArray == handle->state)
+    {
+        /* Stop the timer and disable the RX shifter. */
+        FLEXIO_MCULCD_ClearSingleBeatReadConfig(base);
+    }
+    else
+    {
+        /* Stop the timer and disable the TX shifter. */
+        FLEXIO_MCULCD_ClearSingleBeatWriteConfig(base);
+    }
+
+    /* Clean the flags. */
+    FLEXIO_MCULCD_ClearStatusFlags(base, kFLEXIO_MCULCD_TxEmptyFlag | kFLEXIO_MCULCD_RxFullFlag);
+
+    /* De-assert the nCS. */
+    FLEXIO_MCULCD_StopTransfer(base);
+
+    handle->dataCount      = 0;
+    handle->remainingCount = 0;
+    handle->state          = kFLEXIO_MCULCD_StateIdle;
+}
+
+/*!
+ * brief Gets the data transfer status which used IRQ.
+ *
+ * param base Pointer to the FLEXIO_MCULCD_Type structure.
+ * param handle Pointer to the flexio_mculcd_handle_t structure to store the
+ * transfer state.
+ * param count How many bytes transferred so far by the non-blocking transaction.
+ * retval kStatus_Success Get the transferred count Successfully.
+ * retval kStatus_NoTransferInProgress No transfer in process.
+ */
+status_t FLEXIO_MCULCD_TransferGetCount(FLEXIO_MCULCD_Type *base, flexio_mculcd_handle_t *handle, size_t *count)
+{
+    assert(count);
+
+    if (kFLEXIO_MCULCD_StateIdle == handle->state)
+    {
+        return kStatus_NoTransferInProgress;
+    }
+
+    *count = handle->dataCount - handle->remainingCount;
+
+#if (16 == FLEXIO_MCULCD_DATA_BUS_WIDTH)
+    *count *= 2;
+#endif
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief FlexIO MCULCD IRQ handler function.
+ *
+ * param base Pointer to the FLEXIO_MCULCD_Type structure.
+ * param handle Pointer to the flexio_mculcd_handle_t structure to store the
+ * transfer state.
+ */
+void FLEXIO_MCULCD_TransferHandleIRQ(void *base, void *handle)
+{
+    FLEXIO_MCULCD_Type *flexioLcdMcuBase       = (FLEXIO_MCULCD_Type *)base;
+    flexio_mculcd_handle_t *flexioLcdMcuHandle = (flexio_mculcd_handle_t *)handle;
+    uint32_t statusFlags                       = FLEXIO_MCULCD_GetStatusFlags(flexioLcdMcuBase);
+    uint32_t data;
+
+    if (kFLEXIO_MCULCD_StateReadArray == flexioLcdMcuHandle->state)
+    {
+        /* Handle the reading process. */
+        while ((kFLEXIO_MCULCD_RxFullFlag & statusFlags) && (flexioLcdMcuHandle->remainingCount > 0))
+        {
+            if (1 == flexioLcdMcuHandle->remainingCount)
+            {
+                /* If this is the last data, stop the RX shifter and timer. */
+                FLEXIO_MCULCD_DisableInterrupts(flexioLcdMcuBase, kFLEXIO_MCULCD_RxFullInterruptEnable);
+                FLEXIO_MCULCD_ClearSingleBeatReadConfig(flexioLcdMcuBase);
+                FLEXIO_MCULCD_StopTransfer(flexioLcdMcuBase);
+            }
+
+            /* Read out the data. */
+            data = FLEXIO_MCULCD_ReadData(flexioLcdMcuBase);
+
+#if (8 == FLEXIO_MCULCD_DATA_BUS_WIDTH)
+            *(uint8_t *)(flexioLcdMcuHandle->dataAddrOrSameValue) = (uint8_t)data;
+            flexioLcdMcuHandle->dataAddrOrSameValue++;
+#else
+            *(uint16_t *)(flexioLcdMcuHandle->dataAddrOrSameValue) = (uint16_t)data;
+            flexioLcdMcuHandle->dataAddrOrSameValue += 2U;
+#endif
+
+            flexioLcdMcuHandle->remainingCount--;
+
+            /* Transfer finished, call the callback. */
+            if (0 == flexioLcdMcuHandle->remainingCount)
+            {
+                flexioLcdMcuHandle->state = kFLEXIO_MCULCD_StateIdle;
+
+                if (flexioLcdMcuHandle->completionCallback)
+                {
+                    flexioLcdMcuHandle->completionCallback(flexioLcdMcuBase, flexioLcdMcuHandle,
+                                                           kStatus_FLEXIO_MCULCD_Idle, flexioLcdMcuHandle->userData);
+                }
+            }
+
+            /* Is the shifter buffer ready to send the next data? */
+            statusFlags = FLEXIO_MCULCD_GetStatusFlags(flexioLcdMcuBase);
+        }
+    }
+    else
+    {
+        /* Handle the writing process. */
+        while ((kFLEXIO_MCULCD_TxEmptyFlag & statusFlags) && (flexioLcdMcuHandle->remainingCount > 0))
+        {
+            /* Send the data. */
+            if (kFLEXIO_MCULCD_StateWriteSameValue == flexioLcdMcuHandle->state)
+            {
+                data = flexioLcdMcuHandle->dataAddrOrSameValue;
+            }
+            else
+            {
+#if (8 == FLEXIO_MCULCD_DATA_BUS_WIDTH)
+                data = *(uint8_t *)(flexioLcdMcuHandle->dataAddrOrSameValue);
+                flexioLcdMcuHandle->dataAddrOrSameValue++;
+#else
+                data = *(uint16_t *)(flexioLcdMcuHandle->dataAddrOrSameValue);
+                flexioLcdMcuHandle->dataAddrOrSameValue += 2U;
+#endif
+            }
+
+            /* If this is the last data to send, delay to wait for the data shift out.  */
+            if (1 == flexioLcdMcuHandle->remainingCount)
+            {
+                FLEXIO_MCULCD_DisableInterrupts(flexioLcdMcuBase, kFLEXIO_MCULCD_TxEmptyInterruptEnable);
+
+                /* Write the last data. */
+                FLEXIO_MCULCD_WriteData(flexioLcdMcuBase, data);
+
+                /* Wait for the last data send finished. */
+                FLEXIO_MCULCD_WaitTransmitComplete();
+                flexioLcdMcuHandle->remainingCount = 0;
+
+                FLEXIO_MCULCD_ClearSingleBeatWriteConfig(flexioLcdMcuBase);
+                FLEXIO_MCULCD_StopTransfer(flexioLcdMcuBase);
+                flexioLcdMcuHandle->state = kFLEXIO_MCULCD_StateIdle;
+
+                if (flexioLcdMcuHandle->completionCallback)
+                {
+                    flexioLcdMcuHandle->completionCallback(flexioLcdMcuBase, flexioLcdMcuHandle,
+                                                           kStatus_FLEXIO_MCULCD_Idle, flexioLcdMcuHandle->userData);
+                }
+            }
+            else
+            {
+                FLEXIO_MCULCD_WriteData(flexioLcdMcuBase, data);
+                flexioLcdMcuHandle->remainingCount--;
+            }
+            /* Is the shifter buffer ready to send the next data? */
+            statusFlags = FLEXIO_MCULCD_GetStatusFlags(flexioLcdMcuBase);
+        }
+    }
+}
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_mculcd.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_mculcd.h
new file mode 100644
index 00000000000..feb196cb817
--- /dev/null
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_mculcd.h
@@ -0,0 +1,687 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_FLEXIO_MCULCD_H_
+#define _FSL_FLEXIO_MCULCD_H_
+
+#include "fsl_common.h"
+#include "fsl_flexio.h"
+
+/*!
+ * @addtogroup flexio_mculcd
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief FlexIO MCULCD driver version 2.0.2. */
+#define FSL_FLEXIO_MCULCD_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
+/*@}*/
+
+#ifndef FLEXIO_MCULCD_WAIT_COMPLETE_TIME
+/*!
+ * @brief The delay time to wait for FLEXIO transmit complete.
+ *
+ * Currently there is no method to detect whether the data has been
+ * sent out from the shifter, so the driver use a software delay for this. When
+ * the data is written to shifter buffer, the driver call the delay
+ * function to wait for the data shift out.
+ * If this value is too small, then the last few bytes might be lost when writing
+ * data using interrupt method or DMA method.
+ */
+#define FLEXIO_MCULCD_WAIT_COMPLETE_TIME 512
+#endif
+
+#ifndef FLEXIO_MCULCD_DATA_BUS_WIDTH
+/*!
+ * @brief The data bus width, must be 8 or 16.
+ */
+#define FLEXIO_MCULCD_DATA_BUS_WIDTH 16
+#endif
+
+#if (16 != FLEXIO_MCULCD_DATA_BUS_WIDTH) && (8 != FLEXIO_MCULCD_DATA_BUS_WIDTH)
+#error Only support data bus 8-bit or 16-bit
+#endif
+
+/*! @brief FlexIO LCD transfer status */
+enum _flexio_mculcd_status
+{
+    kStatus_FLEXIO_MCULCD_Idle  = MAKE_STATUS(kStatusGroup_FLEXIO_MCULCD, 0), /*!< FlexIO LCD is idle. */
+    kStatus_FLEXIO_MCULCD_Busy  = MAKE_STATUS(kStatusGroup_FLEXIO_MCULCD, 1), /*!< FlexIO LCD is busy */
+    kStatus_FLEXIO_MCULCD_Error = MAKE_STATUS(kStatusGroup_FLEXIO_MCULCD, 2), /*!< FlexIO LCD error occurred */
+};
+
+/*! @brief Define FlexIO MCULCD pixel format. */
+typedef enum _flexio_mculcd_pixel_format
+{
+    kFLEXIO_MCULCD_RGB565 = 0, /*!< RGB565, 16-bit. */
+    kFLEXIO_MCULCD_BGR565,     /*!< BGR565, 16-bit. */
+    kFLEXIO_MCULCD_RGB888,     /*!< RGB888, 24-bit. */
+    kFLEXIO_MCULCD_BGR888,     /*!< BGR888, 24-bit. */
+} flexio_mculcd_pixel_format_t;
+
+/*! @brief Define FlexIO MCULCD bus type. */
+typedef enum _flexio_mculcd_bus
+{
+    kFLEXIO_MCULCD_8080, /*!< Using Intel 8080 bus. */
+    kFLEXIO_MCULCD_6800, /*!< Using Motorola 6800 bus. */
+} flexio_mculcd_bus_t;
+
+/*! @brief Define FlexIO MCULCD interrupt mask. */
+enum _flexio_mculcd_interrupt_enable
+{
+    kFLEXIO_MCULCD_TxEmptyInterruptEnable = (1U << 0U), /*!< Transmit buffer empty interrupt enable. */
+    kFLEXIO_MCULCD_RxFullInterruptEnable  = (1U << 1U), /*!< Receive buffer full interrupt enable. */
+};
+
+/*! @brief Define FlexIO MCULCD status mask. */
+enum _flexio_mculcd_status_flags
+{
+    kFLEXIO_MCULCD_TxEmptyFlag = (1U << 0U), /*!< Transmit buffer empty flag. */
+    kFLEXIO_MCULCD_RxFullFlag  = (1U << 1U), /*!< Receive buffer full flag. */
+};
+
+/*! @brief Define FlexIO MCULCD DMA mask. */
+enum _flexio_mculcd_dma_enable
+{
+    kFLEXIO_MCULCD_TxDmaEnable = 0x1U, /*!< Tx DMA request source */
+    kFLEXIO_MCULCD_RxDmaEnable = 0x2U, /*!< Rx DMA request source */
+};
+
+/*! @brief Function to set or clear the CS and RS pin. */
+typedef void (*flexio_mculcd_pin_func_t)(bool set);
+
+/*! @brief Define FlexIO MCULCD access structure typedef. */
+typedef struct _flexio_mculcd_type
+{
+    FLEXIO_Type *flexioBase;             /*!< FlexIO base pointer. */
+    flexio_mculcd_bus_t busType;         /*!< The bus type, 8080 or 6800. */
+    uint8_t dataPinStartIndex;           /*!< Start index of the data pin, the FlexIO pin dataPinStartIndex
+                                              to (dataPinStartIndex + FLEXIO_MCULCD_DATA_BUS_WIDTH -1)
+                                              will be used for data transfer. Only support data bus width 8 and 16. */
+    uint8_t ENWRPinIndex;                /*!< Pin select for WR(8080 mode), EN(6800 mode). */
+    uint8_t RDPinIndex;                  /*!< Pin select for RD(8080 mode), not used in 6800 mode. */
+    uint8_t txShifterStartIndex;         /*!< Start index of shifters used for data write, it must be 0 or 4. */
+    uint8_t txShifterEndIndex;           /*!< End index of shifters used for data write. */
+    uint8_t rxShifterStartIndex;         /*!< Start index of shifters used for data read. */
+    uint8_t rxShifterEndIndex;           /*!< End index of shifters used for data read, it must be 3 or 7.  */
+    uint8_t timerIndex;                  /*!< Timer index used in FlexIO MCULCD. */
+    flexio_mculcd_pin_func_t setCSPin;   /*!< Function to set or clear the CS pin. */
+    flexio_mculcd_pin_func_t setRSPin;   /*!< Function to set or clear the RS pin. */
+    flexio_mculcd_pin_func_t setRDWRPin; /*!< Function to set or clear the RD/WR pin, only used in 6800 mode. */
+} FLEXIO_MCULCD_Type;
+
+/*! @brief Define FlexIO MCULCD configuration structure. */
+typedef struct _flexio_mculcd_config
+{
+    bool enable;           /*!< Enable/disable FlexIO MCULCD after configuration. */
+    bool enableInDoze;     /*!< Enable/disable FlexIO operation in doze mode. */
+    bool enableInDebug;    /*!< Enable/disable FlexIO operation in debug mode. */
+    bool enableFastAccess; /*!< Enable/disable fast access to FlexIO registers,
+                           fast access requires the FlexIO clock to be at least
+                           twice the frequency of the bus clock. */
+    uint32_t baudRate_Bps; /*!< Baud rate in Bps. */
+} flexio_mculcd_config_t;
+
+/*! @brief Transfer mode.*/
+typedef enum _flexio_mculcd_transfer_mode
+{
+    kFLEXIO_MCULCD_ReadArray,      /*!< Read data into an array. */
+    kFLEXIO_MCULCD_WriteArray,     /*!< Write data from an array. */
+    kFLEXIO_MCULCD_WriteSameValue, /*!< Write the same value many times. */
+} flexio_mculcd_transfer_mode_t;
+
+/*! @brief Define FlexIO MCULCD transfer structure. */
+typedef struct _flexio_mculcd_transfer
+{
+    uint32_t command;                   /*!< Command to send. */
+    flexio_mculcd_transfer_mode_t mode; /*!< Transfer mode. */
+    uint32_t dataAddrOrSameValue;       /*!< When sending the same value for many times,
+                                           this is the value to send. When writing or reading array,
+                                           this is the address of the data array. */
+    size_t dataSize;                    /*!< How many bytes to transfer. */
+} flexio_mculcd_transfer_t;
+
+/*! @brief typedef for flexio_mculcd_handle_t in advance. */
+typedef struct _flexio_mculcd_handle flexio_mculcd_handle_t;
+
+/*! @brief FlexIO MCULCD callback for finished transfer.
+ *
+ * When transfer finished, the callback function is called and returns the
+ * @p status as kStatus_FLEXIO_MCULCD_Idle.
+ */
+typedef void (*flexio_mculcd_transfer_callback_t)(FLEXIO_MCULCD_Type *base,
+                                                  flexio_mculcd_handle_t *handle,
+                                                  status_t status,
+                                                  void *userData);
+
+/*! @brief Define FlexIO MCULCD handle structure. */
+struct _flexio_mculcd_handle
+{
+    uint32_t dataAddrOrSameValue;                         /*!< When sending the same value for many times,
+                                                             this is the value to send. When writing or reading array,
+                                                             this is the address of the data array. */
+    size_t dataCount;                                     /*!< Total count to be transferred. */
+    volatile size_t remainingCount;                       /*!< Remaining count to transfer. */
+    volatile uint32_t state;                              /*!< FlexIO MCULCD internal state. */
+    flexio_mculcd_transfer_callback_t completionCallback; /*!< FlexIO MCULCD transfer completed callback. */
+    void *userData;                                       /*!< Callback parameter. */
+};
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /*_cplusplus*/
+
+/*!
+ * @name FlexIO MCULCD Configuration
+ * @{
+ */
+
+/*!
+ * @brief Ungates the FlexIO clock, resets the FlexIO module, configures the
+ * FlexIO MCULCD hardware, and configures the FlexIO MCULCD with FlexIO MCULCD
+ * configuration.
+ * The configuration structure can be filled by the user, or be set with default
+ * values
+ * by the @ref FLEXIO_MCULCD_GetDefaultConfig.
+ *
+ * @param base Pointer to the FLEXIO_MCULCD_Type structure.
+ * @param config Pointer to the flexio_mculcd_config_t structure.
+ * @param srcClock_Hz FlexIO source clock in Hz.
+ * @retval kStatus_Success Initialization success.
+ * @retval kStatus_InvalidArgument Initialization failed because of invalid
+ * argument.
+ */
+status_t FLEXIO_MCULCD_Init(FLEXIO_MCULCD_Type *base, flexio_mculcd_config_t *config, uint32_t srcClock_Hz);
+
+/*!
+ * @brief Resets the FLEXIO_MCULCD timer and shifter configuration.
+ *
+ * @param base Pointer to the FLEXIO_MCULCD_Type.
+ */
+void FLEXIO_MCULCD_Deinit(FLEXIO_MCULCD_Type *base);
+
+/*!
+ * @brief Gets the default configuration to configure the FlexIO MCULCD.
+ *
+ * The default configuration value is:
+ * @code
+ *  config->enable = true;
+ *  config->enableInDoze = false;
+ *  config->enableInDebug = true;
+ *  config->enableFastAccess = true;
+ *  config->baudRate_Bps = 96000000U;
+ * @endcode
+ * @param Config Pointer to the flexio_mculcd_config_t structure.
+ */
+void FLEXIO_MCULCD_GetDefaultConfig(flexio_mculcd_config_t *config);
+
+/*@}*/
+
+/*!
+ * @name Status
+ * @{
+ */
+
+/*!
+ * @brief Gets FlexIO MCULCD status flags.
+ *
+ * @param base Pointer to the FLEXIO_MCULCD_Type structure.
+ * @return status flag; OR'ed value or the @ref _flexio_mculcd_status_flags.
+ *
+ * @note Don't use this function with DMA APIs.
+ */
+uint32_t FLEXIO_MCULCD_GetStatusFlags(FLEXIO_MCULCD_Type *base);
+
+/*!
+ * @brief Clears FlexIO MCULCD status flags.
+ *
+ * @param base Pointer to the FLEXIO_MCULCD_Type structure.
+ * @param mask Status to clear, it is the OR'ed value of @ref
+ * _flexio_mculcd_status_flags.
+ *
+ * @note Don't use this function with DMA APIs.
+ */
+void FLEXIO_MCULCD_ClearStatusFlags(FLEXIO_MCULCD_Type *base, uint32_t mask);
+
+/*@}*/
+
+/*!
+ * @name Interrupts
+ * @{
+ */
+
+/*!
+ * @brief Enables the FlexIO MCULCD interrupt.
+ *
+ * This function enables the FlexIO MCULCD interrupt.
+ *
+ * @param base Pointer to the FLEXIO_MCULCD_Type structure.
+ * @param mask Interrupts to enable, it is the OR'ed value of @ref
+ * _flexio_mculcd_interrupt_enable.
+ */
+void FLEXIO_MCULCD_EnableInterrupts(FLEXIO_MCULCD_Type *base, uint32_t mask);
+
+/*!
+ * @brief Disables the FlexIO MCULCD interrupt.
+ *
+ * This function disables the FlexIO MCULCD interrupt.
+ *
+ * @param base Pointer to the FLEXIO_MCULCD_Type structure.
+ * @param mask Interrupts to disable, it is the OR'ed value of @ref
+ * _flexio_mculcd_interrupt_enable.
+ */
+void FLEXIO_MCULCD_DisableInterrupts(FLEXIO_MCULCD_Type *base, uint32_t mask);
+
+/*@}*/
+
+/*!
+ * @name DMA Control
+ * @{
+ */
+
+/*!
+ * @brief Enables/disables the FlexIO MCULCD transmit DMA.
+ *
+ * @param base Pointer to the FLEXIO_MCULCD_Type structure.
+ * @param mask MCULCD DMA source.
+ * @param enable True means enable DMA, false means disable DMA.
+ */
+static inline void FLEXIO_MCULCD_EnableTxDMA(FLEXIO_MCULCD_Type *base, bool enable)
+{
+    FLEXIO_EnableShifterStatusDMA(base->flexioBase, (1U << base->txShifterStartIndex), enable);
+}
+
+/*!
+ * @brief Enables/disables the FlexIO MCULCD receive DMA.
+ *
+ * @param base Pointer to the FLEXIO_MCULCD_Type structure.
+ * @param mask MCULCD DMA source.
+ * @param enable True means enable DMA, false means disable DMA.
+ */
+static inline void FLEXIO_MCULCD_EnableRxDMA(FLEXIO_MCULCD_Type *base, bool enable)
+{
+    FLEXIO_EnableShifterStatusDMA(base->flexioBase, (1U << base->rxShifterEndIndex), enable);
+}
+
+/*!
+ * @brief Gets the FlexIO MCULCD transmit data register address.
+ *
+ * This function returns the MCULCD data register address, which is mainly used
+ * by DMA/eDMA.
+ *
+ * @param base Pointer to the FLEXIO_MCULCD_Type structure.
+ * @return FlexIO MCULCD transmit data register address.
+ */
+static inline uint32_t FLEXIO_MCULCD_GetTxDataRegisterAddress(FLEXIO_MCULCD_Type *base)
+{
+    return (uint32_t) & (base->flexioBase->SHIFTBUF[base->txShifterStartIndex]);
+}
+
+/*!
+ * @brief Gets the FlexIO MCULCD receive data register address.
+ *
+ * This function returns the MCULCD data register address, which is mainly used
+ * by DMA/eDMA.
+ *
+ * @param base Pointer to the FLEXIO_MCULCD_Type structure.
+ * @return FlexIO MCULCD receive data register address.
+ */
+static inline uint32_t FLEXIO_MCULCD_GetRxDataRegisterAddress(FLEXIO_MCULCD_Type *base)
+{
+    return (uint32_t) & (base->flexioBase->SHIFTBUF[base->rxShifterStartIndex]);
+}
+
+/*@}*/
+
+/*!
+ * @name Bus Operations
+ * @{
+ */
+
+/*!
+ * @brief Set desired baud rate.
+ *
+ * @param base Pointer to the FLEXIO_MCULCD_Type structure.
+ * @param baudRate_Bps Desired baud rate.
+ * @param srcClock_Hz FLEXIO clock frequency in Hz.
+ * @retval kStatus_Success Set successfully.
+ * @retval kStatus_InvalidArgument Could not set the baud rate.
+ */
+status_t FLEXIO_MCULCD_SetBaudRate(FLEXIO_MCULCD_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz);
+
+/*!
+ * @brief Configures the FLEXIO MCULCD to multiple beats write mode.
+ *
+ * At the begining multiple beats write operation, the FLEXIO MCULCD is configured to
+ * multiple beats write mode using this function. After write operation, the configuration
+ * is cleared by @ref FLEXIO_MCULCD_ClearSingleBeatWriteConfig.
+ *
+ * @param base Pointer to the FLEXIO_MCULCD_Type.
+ *
+ * @note This is an internal used function, upper layer should not use.
+ */
+void FLEXIO_MCULCD_SetSingleBeatWriteConfig(FLEXIO_MCULCD_Type *base);
+
+/*!
+ * @brief Clear the FLEXIO MCULCD multiple beats write mode configuration.
+ *
+ * Clear the write configuration set by @ref FLEXIO_MCULCD_SetSingleBeatWriteConfig.
+ *
+ * @param base Pointer to the FLEXIO_MCULCD_Type.
+ *
+ * @note This is an internal used function, upper layer should not use.
+ */
+void FLEXIO_MCULCD_ClearSingleBeatWriteConfig(FLEXIO_MCULCD_Type *base);
+
+/*!
+ * @brief Configures the FLEXIO MCULCD to multiple beats read mode.
+ *
+ * At the begining or multiple beats read operation, the FLEXIO MCULCD is configured
+ * to multiple beats read mode using this function. After read operation, the configuration
+ * is cleared by @ref FLEXIO_MCULCD_ClearSingleBeatReadConfig.
+ *
+ * @param base Pointer to the FLEXIO_MCULCD_Type.
+ *
+ * @note This is an internal used function, upper layer should not use.
+ */
+void FLEXIO_MCULCD_SetSingleBeatReadConfig(FLEXIO_MCULCD_Type *base);
+
+/*!
+ * @brief Clear the FLEXIO MCULCD multiple beats read mode configuration.
+ *
+ * Clear the read configuration set by @ref FLEXIO_MCULCD_SetSingleBeatReadConfig.
+ *
+ * @param base Pointer to the FLEXIO_MCULCD_Type.
+ *
+ * @note This is an internal used function, upper layer should not use.
+ */
+void FLEXIO_MCULCD_ClearSingleBeatReadConfig(FLEXIO_MCULCD_Type *base);
+
+/*!
+ * @brief Configures the FLEXIO MCULCD to multiple beats write mode.
+ *
+ * At the begining multiple beats write operation, the FLEXIO MCULCD is configured to
+ * multiple beats write mode using this function. After write operation, the configuration
+ * is cleared by @ref FLEXIO_MCULCD_ClearMultBeatsWriteConfig.
+ *
+ * @param base Pointer to the FLEXIO_MCULCD_Type.
+ *
+ * @note This is an internal used function, upper layer should not use.
+ */
+void FLEXIO_MCULCD_SetMultiBeatsWriteConfig(FLEXIO_MCULCD_Type *base);
+
+/*!
+ * @brief Clear the FLEXIO MCULCD multiple beats write mode configuration.
+ *
+ * Clear the write configuration set by @ref FLEXIO_MCULCD_SetMultBeatsWriteConfig.
+ *
+ * @param base Pointer to the FLEXIO_MCULCD_Type.
+ *
+ * @note This is an internal used function, upper layer should not use.
+ */
+void FLEXIO_MCULCD_ClearMultiBeatsWriteConfig(FLEXIO_MCULCD_Type *base);
+
+/*!
+ * @brief Configures the FLEXIO MCULCD to multiple beats read mode.
+ *
+ * At the begining or multiple beats read operation, the FLEXIO MCULCD is configured
+ * to multiple beats read mode using this function. After read operation, the configuration
+ * is cleared by @ref FLEXIO_MCULCD_ClearMultBeatsReadConfig.
+ *
+ * @param base Pointer to the FLEXIO_MCULCD_Type.
+ *
+ * @note This is an internal used function, upper layer should not use.
+ */
+void FLEXIO_MCULCD_SetMultiBeatsReadConfig(FLEXIO_MCULCD_Type *base);
+
+/*!
+ * @brief Clear the FLEXIO MCULCD multiple beats read mode configuration.
+ *
+ * Clear the read configuration set by @ref FLEXIO_MCULCD_SetMultBeatsReadConfig.
+ *
+ * @param base Pointer to the FLEXIO_MCULCD_Type.
+ *
+ * @note This is an internal used function, upper layer should not use.
+ */
+void FLEXIO_MCULCD_ClearMultiBeatsReadConfig(FLEXIO_MCULCD_Type *base);
+
+/*!
+ * @brief Enables/disables the FlexIO MCULCD module operation.
+ *
+ * @param base Pointer to the FLEXIO_MCULCD_Type.
+ * @param enable True to enable, false does not have any effect.
+ */
+static inline void FLEXIO_MCULCD_Enable(FLEXIO_MCULCD_Type *base, bool enable)
+{
+    if (enable)
+    {
+        FLEXIO_Enable(base->flexioBase, enable);
+    }
+}
+
+/*!
+ * @brief Read data from the FLEXIO MCULCD RX shifter buffer.
+ *
+ * Read data from the RX shift buffer directly, it does no check whether the
+ * buffer is empty or not.
+ *
+ * If the data bus width is 8-bit:
+ * @code
+ * uint8_t value;
+ * value = (uint8_t)FLEXIO_MCULCD_ReadData(base);
+ * @endcode
+ *
+ * If the data bus width is 16-bit:
+ * @code
+ * uint16_t value;
+ * value = (uint16_t)FLEXIO_MCULCD_ReadData(base);
+ * @endcode
+ *
+ * @note This function returns the RX shifter buffer value (32-bit) directly.
+ * The return value should be converted according to data bus width.
+ *
+ * @param base Pointer to the FLEXIO_MCULCD_Type structure.
+ * @return The data read out.
+ *
+ * @note Don't use this function with DMA APIs.
+ */
+uint32_t FLEXIO_MCULCD_ReadData(FLEXIO_MCULCD_Type *base);
+
+/*!
+ * @brief Write data into the FLEXIO MCULCD TX shifter buffer.
+ *
+ * Write data into the TX shift buffer directly, it does no check whether the
+ * buffer is full or not.
+ *
+ * @param base Pointer to the FLEXIO_MCULCD_Type structure.
+ * @param data The data to write.
+ *
+ * @note Don't use this function with DMA APIs.
+ */
+static inline void FLEXIO_MCULCD_WriteData(FLEXIO_MCULCD_Type *base, uint32_t data)
+{
+    base->flexioBase->SHIFTBUF[base->txShifterStartIndex] = data;
+}
+
+/*!
+ * @brief Assert the nCS to start transfer.
+ *
+ * @param base Pointer to the FLEXIO_MCULCD_Type structure.
+ */
+static inline void FLEXIO_MCULCD_StartTransfer(FLEXIO_MCULCD_Type *base)
+{
+    base->setCSPin(false);
+}
+
+/*!
+ * @brief De-assert the nCS to stop transfer.
+ *
+ * @param base Pointer to the FLEXIO_MCULCD_Type structure.
+ */
+static inline void FLEXIO_MCULCD_StopTransfer(FLEXIO_MCULCD_Type *base)
+{
+    base->setCSPin(true);
+}
+
+/*!
+ * @brief Wait for transmit data send out finished.
+ *
+ * Currently there is no effective method to wait for the data send out
+ * from the shiter, so here use a while loop to wait.
+ *
+ * @note This is an internal used function.
+ */
+void FLEXIO_MCULCD_WaitTransmitComplete(void);
+
+/*!
+ * @brief Send command in blocking way.
+ *
+ * This function sends the command and returns when the command has been sent
+ * out.
+ *
+ * @param base Pointer to the FLEXIO_MCULCD_Type structure.
+ * @param command The command to send.
+ */
+void FLEXIO_MCULCD_WriteCommandBlocking(FLEXIO_MCULCD_Type *base, uint32_t command);
+
+/*!
+ * @brief Send data array in blocking way.
+ *
+ * This function sends the data array and returns when the data sent out.
+ *
+ * @param base Pointer to the FLEXIO_MCULCD_Type structure.
+ * @param data The data array to send.
+ * @param size How many bytes to write.
+ */
+void FLEXIO_MCULCD_WriteDataArrayBlocking(FLEXIO_MCULCD_Type *base, void *data, size_t size);
+
+/*!
+ * @brief Read data into array in blocking way.
+ *
+ * This function reads the data into array and returns when the data read
+ * finished.
+ *
+ * @param base Pointer to the FLEXIO_MCULCD_Type structure.
+ * @param data The array to save the data.
+ * @param size How many bytes to read.
+ */
+void FLEXIO_MCULCD_ReadDataArrayBlocking(FLEXIO_MCULCD_Type *base, void *data, size_t size);
+
+/*!
+ * @brief Send the same value many times in blocking way.
+ *
+ * This function sends the same value many times. It could be used to clear the
+ * LCD screen. If the data bus width is 8, this function will send LSB 8 bits of
+ * @p sameValue for @p size times. If the data bus is 16, this function will send
+ * LSB 16 bits of @p sameValue for @p size / 2 times.
+ *
+ * @param base Pointer to the FLEXIO_MCULCD_Type structure.
+ * @param sameValue The same value to send.
+ * @param size How many bytes to send.
+ */
+void FLEXIO_MCULCD_WriteSameValueBlocking(FLEXIO_MCULCD_Type *base, uint32_t sameValue, size_t size);
+
+/*!
+ * @brief Performs a polling transfer.
+ *
+ * @note The API does not return until the transfer finished.
+ *
+ * @param base pointer to FLEXIO_MCULCD_Type structure.
+ * @param xfer pointer to flexio_mculcd_transfer_t structure.
+ */
+void FLEXIO_MCULCD_TransferBlocking(FLEXIO_MCULCD_Type *base, flexio_mculcd_transfer_t *xfer);
+/*@}*/
+
+/*!
+ * @name Transactional
+ * @{
+ */
+
+/*!
+ * @brief Initializes the FlexIO MCULCD handle, which is used in transactional
+ * functions.
+ *
+ * @param base Pointer to the FLEXIO_MCULCD_Type structure.
+ * @param handle Pointer to the flexio_mculcd_handle_t structure to store the
+ * transfer state.
+ * @param callback The callback function.
+ * @param userData The parameter of the callback function.
+ * @retval kStatus_Success Successfully create the handle.
+ * @retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range.
+ */
+status_t FLEXIO_MCULCD_TransferCreateHandle(FLEXIO_MCULCD_Type *base,
+                                            flexio_mculcd_handle_t *handle,
+                                            flexio_mculcd_transfer_callback_t callback,
+                                            void *userData);
+
+/*!
+ * @brief Transfer data using IRQ.
+ *
+ * This function sends data using IRQ. This is a non-blocking function, which
+ * returns right away. When all data is sent out/received, the callback
+ * function is called.
+ *
+ * @param base Pointer to the FLEXIO_MCULCD_Type structure.
+ * @param handle Pointer to the flexio_mculcd_handle_t structure to store the
+ * transfer state.
+ * @param xfer FlexIO MCULCD transfer structure. See #flexio_mculcd_transfer_t.
+ * @retval kStatus_Success Successfully start a transfer.
+ * @retval kStatus_InvalidArgument Input argument is invalid.
+ * @retval kStatus_FLEXIO_MCULCD_Busy MCULCD is busy with another transfer.
+ */
+status_t FLEXIO_MCULCD_TransferNonBlocking(FLEXIO_MCULCD_Type *base,
+                                           flexio_mculcd_handle_t *handle,
+                                           flexio_mculcd_transfer_t *xfer);
+
+/*!
+ * @brief Aborts the data transfer, which used IRQ.
+ *
+ * @param base Pointer to the FLEXIO_MCULCD_Type structure.
+ * @param handle Pointer to the flexio_mculcd_handle_t structure to store the
+ * transfer state.
+ */
+void FLEXIO_MCULCD_TransferAbort(FLEXIO_MCULCD_Type *base, flexio_mculcd_handle_t *handle);
+
+/*!
+ * @brief Gets the data transfer status which used IRQ.
+ *
+ * @param base Pointer to the FLEXIO_MCULCD_Type structure.
+ * @param handle Pointer to the flexio_mculcd_handle_t structure to store the
+ * transfer state.
+ * @param count How many bytes transferred so far by the non-blocking transaction.
+ * @retval kStatus_Success Get the transferred count Successfully.
+ * @retval kStatus_NoTransferInProgress No transfer in process.
+ */
+status_t FLEXIO_MCULCD_TransferGetCount(FLEXIO_MCULCD_Type *base, flexio_mculcd_handle_t *handle, size_t *count);
+
+/*!
+ * @brief FlexIO MCULCD IRQ handler function.
+ *
+ * @param base Pointer to the FLEXIO_MCULCD_Type structure.
+ * @param handle Pointer to the flexio_mculcd_handle_t structure to store the
+ * transfer state.
+ */
+void FLEXIO_MCULCD_TransferHandleIRQ(void *base, void *handle);
+
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif /*_cplusplus*/
+/*@}*/
+
+#endif /*_FSL_FLEXIO_MCULCD_H_*/
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_mculcd_edma.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_mculcd_edma.c
new file mode 100644
index 00000000000..0b5187833f7
--- /dev/null
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_mculcd_edma.c
@@ -0,0 +1,564 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_flexio_mculcd_edma.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.flexio_mculcd_edma"
+#endif
+
+#define EDMA_MAX_MAJOR_COUNT (DMA_CITER_ELINKNO_CITER_MASK >> DMA_CITER_ELINKNO_CITER_SHIFT)
+
+enum _MCULCD_transfer_state
+{
+    kFLEXIO_MCULCD_StateIdle,           /*!< No transfer in progress. */
+    kFLEXIO_MCULCD_StateReadArray,      /*!< Reading array in progress. */
+    kFLEXIO_MCULCD_StateWriteArray,     /*!< Writing array in progress. */
+    kFLEXIO_MCULCD_StateWriteSameValue, /*!< Writing the same value in progress.
+                                         */
+};
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*!
+ * @brief EDMA callback function for FLEXIO MCULCD TX.
+ *
+ * For details, see @ref edma_callback.
+ */
+static void FLEXIO_MCULCD_TxEDMACallback(edma_handle_t *DmaHandle, void *param, bool transferDone, uint32_t tcds);
+
+/*!
+ * @brief EDMA callback function for FLEXIO MCULCD RX.
+ *
+ * For details, see @ref edma_callback.
+ */
+static void FLEXIO_MCULCD_RxEDMACallback(edma_handle_t *DmaHandle, void *param, bool transferDone, uint32_t tcds);
+
+/*!
+ * @brief Set EDMA config for FLEXIO MCULCD transfer.
+ *
+ * @param base pointer to FLEXIO_MCULCD_Type structure.
+ * @param handle pointer to flexio_mculcd_edma_handle_t structure to store the
+ * transfer state.
+ */
+static void FLEXIO_MCULCD_EDMAConfig(FLEXIO_MCULCD_Type *base, flexio_mculcd_edma_handle_t *handle);
+
+/*!
+ * @brief Convert the FlexIO shifter number to eDMA modulo.
+ *
+ * @param shifterNum The FlexIO shifter number.
+ * @param modulo The modulo number.
+ * @retval Get the modulo successfully.
+ * @retval Could not get the modulo for the shifter number.
+ */
+static bool FLEXIO_MCULCD_GetEDMAModulo(uint8_t shifterNum, edma_modulo_t *modulo);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+static void FLEXIO_MCULCD_TxEDMACallback(edma_handle_t *DmaHandle, void *param, bool transferDone, uint32_t tcds)
+{
+    tcds                                            = tcds;
+    flexio_mculcd_edma_handle_t *flexioLcdMcuHandle = (flexio_mculcd_edma_handle_t *)param;
+    FLEXIO_MCULCD_Type *flexioLcdMcuBase            = flexioLcdMcuHandle->base;
+
+    if (transferDone)
+    {
+        if (flexioLcdMcuHandle->remainingCount >= flexioLcdMcuHandle->minorLoopBytes)
+        {
+            FLEXIO_MCULCD_EDMAConfig(flexioLcdMcuBase, flexioLcdMcuHandle);
+            EDMA_StartTransfer(flexioLcdMcuHandle->txDmaHandle);
+        }
+        else
+        {
+            FLEXIO_MCULCD_EnableTxDMA(flexioLcdMcuBase, false);
+
+            /* Now the data are in shifter, wait for the data send out from the shifter. */
+            FLEXIO_MCULCD_WaitTransmitComplete();
+
+            /* Disable the TX shifter and the timer. */
+            FLEXIO_MCULCD_ClearMultiBeatsWriteConfig(flexioLcdMcuBase);
+
+            /* Send the remaining data. */
+            if (flexioLcdMcuHandle->remainingCount)
+            {
+                if (kFLEXIO_MCULCD_StateWriteSameValue == flexioLcdMcuHandle->state)
+                {
+                    FLEXIO_MCULCD_WriteSameValueBlocking(flexioLcdMcuBase, flexioLcdMcuHandle->dataAddrOrSameValue,
+                                                         flexioLcdMcuHandle->remainingCount);
+                }
+                else
+                {
+                    FLEXIO_MCULCD_WriteDataArrayBlocking(flexioLcdMcuBase,
+                                                         (void *)flexioLcdMcuHandle->dataAddrOrSameValue,
+                                                         flexioLcdMcuHandle->remainingCount);
+                }
+            }
+
+            /* De-assert nCS. */
+            FLEXIO_MCULCD_StopTransfer(flexioLcdMcuBase);
+
+            /* Change the state. */
+            flexioLcdMcuHandle->state          = kFLEXIO_MCULCD_StateIdle;
+            flexioLcdMcuHandle->dataCount      = 0;
+            flexioLcdMcuHandle->remainingCount = 0;
+
+            /* Callback to inform upper layer. */
+            if (flexioLcdMcuHandle->completionCallback)
+            {
+                flexioLcdMcuHandle->completionCallback(flexioLcdMcuBase, flexioLcdMcuHandle, kStatus_FLEXIO_MCULCD_Idle,
+                                                       flexioLcdMcuHandle->userData);
+            }
+        }
+    }
+}
+
+static void FLEXIO_MCULCD_RxEDMACallback(edma_handle_t *DmaHandle, void *param, bool transferDone, uint32_t tcds)
+{
+    tcds = tcds;
+    uint32_t i;
+    uint32_t rxBufAddr;
+    flexio_mculcd_edma_handle_t *flexioLcdMcuHandle = (flexio_mculcd_edma_handle_t *)param;
+    FLEXIO_MCULCD_Type *flexioLcdMcuBase            = flexioLcdMcuHandle->base;
+    FLEXIO_Type *flexioBase                         = flexioLcdMcuBase->flexioBase;
+
+    if (transferDone)
+    {
+        if (flexioLcdMcuHandle->remainingCount >= (2 * flexioLcdMcuHandle->minorLoopBytes))
+        {
+            FLEXIO_MCULCD_EDMAConfig(flexioLcdMcuBase, flexioLcdMcuHandle);
+            EDMA_StartTransfer(flexioLcdMcuHandle->rxDmaHandle);
+        }
+        else
+        {
+            FLEXIO_MCULCD_EnableRxDMA(flexioLcdMcuBase, false);
+
+            /* Wait the data saved to the shifter buffer. */
+            while (!((1U << flexioLcdMcuBase->rxShifterEndIndex) & FLEXIO_GetShifterStatusFlags(flexioBase)))
+            {
+            }
+
+            /* Disable the RX shifter and the timer. */
+            FLEXIO_MCULCD_ClearMultiBeatsReadConfig(flexioLcdMcuBase);
+
+            rxBufAddr = FLEXIO_MCULCD_GetRxDataRegisterAddress(flexioLcdMcuBase);
+
+/* Read out the data. */
+#if (defined(__CORTEX_M) && (__CORTEX_M == 0))
+            /* Cortex M0 and M0+ only support aligned access. */
+            for (i = 0; i < flexioLcdMcuHandle->rxShifterNum * 4; i++)
+            {
+                ((uint8_t *)(flexioLcdMcuHandle->dataAddrOrSameValue))[i] = ((volatile uint8_t *)rxBufAddr)[i];
+            }
+#else
+            for (i = 0; i < flexioLcdMcuHandle->rxShifterNum; i++)
+            {
+                ((uint32_t *)(flexioLcdMcuHandle->dataAddrOrSameValue))[i] = ((volatile uint32_t *)rxBufAddr)[i];
+            }
+#endif
+            flexioLcdMcuHandle->remainingCount -= flexioLcdMcuHandle->minorLoopBytes;
+
+            if (flexioLcdMcuHandle->remainingCount)
+            {
+                FLEXIO_MCULCD_ReadDataArrayBlocking(
+                    flexioLcdMcuBase,
+                    (void *)(flexioLcdMcuHandle->dataAddrOrSameValue + flexioLcdMcuHandle->minorLoopBytes),
+                    flexioLcdMcuHandle->remainingCount);
+            }
+
+            /* De-assert nCS. */
+            FLEXIO_MCULCD_StopTransfer(flexioLcdMcuBase);
+
+            /* Change the state. */
+            flexioLcdMcuHandle->state          = kFLEXIO_MCULCD_StateIdle;
+            flexioLcdMcuHandle->dataCount      = 0;
+            flexioLcdMcuHandle->remainingCount = 0;
+
+            /* Callback to inform upper layer. */
+            if (flexioLcdMcuHandle->completionCallback)
+            {
+                flexioLcdMcuHandle->completionCallback(flexioLcdMcuBase, flexioLcdMcuHandle, kStatus_FLEXIO_MCULCD_Idle,
+                                                       flexioLcdMcuHandle->userData);
+            }
+        }
+    }
+}
+
+static void FLEXIO_MCULCD_EDMAConfig(FLEXIO_MCULCD_Type *base, flexio_mculcd_edma_handle_t *handle)
+{
+    edma_transfer_config_t xferConfig = {0};
+    edma_transfer_size_t transferSize = kEDMA_TransferSize1Bytes;
+    int16_t offset;
+    uint32_t majorLoopCounts;
+    uint32_t transferCount;
+
+#if (8 == FLEXIO_MCULCD_DATA_BUS_WIDTH)
+    transferSize = kEDMA_TransferSize1Bytes;
+    offset       = 1;
+#else
+    transferSize = kEDMA_TransferSize2Bytes;
+    offset = 2;
+#endif
+
+    majorLoopCounts = handle->remainingCount / handle->minorLoopBytes;
+
+    /* For reading, the last minor loop data is not tranfered by DMA. */
+    if (kFLEXIO_MCULCD_StateReadArray == handle->state)
+    {
+        majorLoopCounts--;
+    }
+
+    if (majorLoopCounts > EDMA_MAX_MAJOR_COUNT)
+    {
+        majorLoopCounts = EDMA_MAX_MAJOR_COUNT;
+    }
+
+    transferCount = majorLoopCounts * handle->minorLoopBytes;
+
+    if (kFLEXIO_MCULCD_StateReadArray == handle->state)
+    {
+        xferConfig.srcAddr          = FLEXIO_MCULCD_GetRxDataRegisterAddress(base);
+        xferConfig.destAddr         = handle->dataAddrOrSameValue;
+        xferConfig.srcTransferSize  = kEDMA_TransferSize4Bytes;
+        xferConfig.destTransferSize = transferSize;
+        xferConfig.srcOffset        = 4;
+        xferConfig.destOffset       = offset;
+        xferConfig.minorLoopBytes   = handle->minorLoopBytes;
+        xferConfig.majorLoopCounts  = majorLoopCounts;
+        handle->remainingCount -= transferCount;
+        handle->dataAddrOrSameValue += transferCount;
+        EDMA_SubmitTransfer(handle->rxDmaHandle, &xferConfig);
+        EDMA_SetModulo(handle->rxDmaHandle->base, handle->rxDmaHandle->channel, handle->rxEdmaModulo,
+                       kEDMA_ModuloDisable);
+    }
+    else
+    {
+        if (kFLEXIO_MCULCD_StateWriteArray == handle->state)
+        {
+            xferConfig.srcAddr   = handle->dataAddrOrSameValue;
+            xferConfig.srcOffset = offset;
+            handle->dataAddrOrSameValue += transferCount;
+        }
+        else
+        {
+            xferConfig.srcAddr   = (uint32_t)(&(handle->dataAddrOrSameValue));
+            xferConfig.srcOffset = 0;
+        }
+        xferConfig.destAddr         = FLEXIO_MCULCD_GetTxDataRegisterAddress(base);
+        xferConfig.srcTransferSize  = transferSize;
+        xferConfig.destTransferSize = kEDMA_TransferSize4Bytes;
+        xferConfig.destOffset       = 4;
+        xferConfig.minorLoopBytes   = handle->minorLoopBytes;
+        xferConfig.majorLoopCounts  = majorLoopCounts;
+        handle->remainingCount -= transferCount;
+        EDMA_SubmitTransfer(handle->txDmaHandle, &xferConfig);
+        EDMA_SetModulo(handle->txDmaHandle->base, handle->txDmaHandle->channel, kEDMA_ModuloDisable,
+                       handle->txEdmaModulo);
+    }
+}
+
+static bool FLEXIO_MCULCD_GetEDMAModulo(uint8_t shifterNum, edma_modulo_t *modulo)
+{
+    bool ret = true;
+
+    switch (shifterNum)
+    {
+        case 1U:
+            *modulo = kEDMA_Modulo4bytes;
+            break;
+        case 2U:
+            *modulo = kEDMA_Modulo8bytes;
+            break;
+        case 4U:
+            *modulo = kEDMA_Modulo16bytes;
+            break;
+        case 8U:
+            *modulo = kEDMA_Modulo32bytes;
+            break;
+        default:
+            ret = false;
+            break;
+    }
+
+    return ret;
+}
+
+/*!
+ * brief Initializes the FLEXO MCULCD master eDMA handle.
+ *
+ * This function initializes the FLEXO MCULCD master eDMA handle which can be
+ * used for other FLEXO MCULCD transactional APIs. For a specified FLEXO MCULCD
+ * instance, call this API once to get the initialized handle.
+ *
+ * param base Pointer to FLEXIO_MCULCD_Type structure.
+ * param handle Pointer to flexio_mculcd_edma_handle_t structure to store the
+ * transfer state.
+ * param callback MCULCD transfer complete callback, NULL means no callback.
+ * param userData callback function parameter.
+ * param txDmaHandle User requested eDMA handle for FlexIO MCULCD eDMA TX,
+ * the DMA request source of this handle should be the first of TX shifters.
+ * param rxDmaHandle User requested eDMA handle for FlexIO MCULCD eDMA RX,
+ * the DMA request source of this handle should be the last of RX shifters.
+ * retval kStatus_Success Successfully create the handle.
+ */
+status_t FLEXIO_MCULCD_TransferCreateHandleEDMA(FLEXIO_MCULCD_Type *base,
+                                                flexio_mculcd_edma_handle_t *handle,
+                                                flexio_mculcd_edma_transfer_callback_t callback,
+                                                void *userData,
+                                                edma_handle_t *txDmaHandle,
+                                                edma_handle_t *rxDmaHandle)
+{
+    assert(handle);
+
+    /* Zero the handle. */
+    memset(handle, 0, sizeof(*handle));
+
+    /* Initialize the state. */
+    handle->state = kFLEXIO_MCULCD_StateIdle;
+
+    /* Register callback and userData. */
+    handle->completionCallback = callback;
+    handle->userData           = userData;
+
+    handle->base         = base;
+    handle->txShifterNum = base->txShifterEndIndex - base->txShifterStartIndex + 1U;
+    handle->rxShifterNum = base->rxShifterEndIndex - base->rxShifterStartIndex + 1U;
+
+    if (rxDmaHandle)
+    {
+        if (!FLEXIO_MCULCD_GetEDMAModulo(handle->rxShifterNum, &handle->rxEdmaModulo))
+        {
+            return kStatus_InvalidArgument;
+        }
+
+        handle->rxDmaHandle = rxDmaHandle;
+        EDMA_SetCallback(rxDmaHandle, FLEXIO_MCULCD_RxEDMACallback, handle);
+    }
+
+    if (txDmaHandle)
+    {
+        if (!FLEXIO_MCULCD_GetEDMAModulo(handle->txShifterNum, &handle->txEdmaModulo))
+        {
+            return kStatus_InvalidArgument;
+        }
+
+        handle->txDmaHandle = txDmaHandle;
+        EDMA_SetCallback(txDmaHandle, FLEXIO_MCULCD_TxEDMACallback, handle);
+    }
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Performs a non-blocking FlexIO MCULCD transfer using eDMA.
+ *
+ * This function returns immediately after transfer initiates. To check whether
+ * the transfer is completed, user could:
+ * 1. Use the transfer completed callback;
+ * 2. Polling function ref FLEXIO_MCULCD_GetTransferCountEDMA
+ *
+ * param base pointer to FLEXIO_MCULCD_Type structure.
+ * param handle pointer to flexio_mculcd_edma_handle_t structure to store the
+ * transfer state.
+ * param xfer Pointer to FlexIO MCULCD transfer structure.
+ * retval kStatus_Success Successfully start a transfer.
+ * retval kStatus_InvalidArgument Input argument is invalid.
+ * retval kStatus_FLEXIO_MCULCD_Busy FlexIO MCULCD is not idle, it is running another
+ * transfer.
+ */
+status_t FLEXIO_MCULCD_TransferEDMA(FLEXIO_MCULCD_Type *base,
+                                    flexio_mculcd_edma_handle_t *handle,
+                                    flexio_mculcd_transfer_t *xfer)
+{
+    assert(handle);
+    assert(xfer);
+
+    /*
+     * The data transfer mechanism:
+     *
+     * Read:
+     * Assume the data length is Lr = (n1 * minorLoopBytes + n2), where
+     * n2 < minorLoopBytes.
+     * If (n1 <= 1), then all data are sent using blocking method.
+     * If (n1 > 1), then the beginning ((n1-1) * minorLoopBytes) are read
+     * using DMA, the left (minorLoopBytes + n2) are read using blocking method.
+     *
+     * Write:
+     * Assume the data length is Lw = (n1 * minorLoopBytes + n2), where
+     * n2 < minorLoopBytes.
+     * If (n1 = 0), then all data are sent using blocking method.
+     * If (n1 >= 1), then the beginning (n1 * minorLoopBytes) are sent
+     * using DMA, the left n2 are sent using blocking method.
+     */
+
+    /* Check if the device is busy. */
+    if (kFLEXIO_MCULCD_StateIdle != handle->state)
+    {
+        return kStatus_FLEXIO_MCULCD_Busy;
+    }
+
+    /* Set the state in handle. */
+    if (kFLEXIO_MCULCD_ReadArray == xfer->mode)
+    {
+        handle->state          = kFLEXIO_MCULCD_StateReadArray;
+        handle->minorLoopBytes = handle->rxShifterNum * 4U;
+    }
+    else
+    {
+        handle->minorLoopBytes = handle->txShifterNum * 4U;
+
+        if (kFLEXIO_MCULCD_WriteArray == xfer->mode)
+        {
+            handle->state = kFLEXIO_MCULCD_StateWriteArray;
+        }
+        else
+        {
+            handle->state = kFLEXIO_MCULCD_StateWriteSameValue;
+        }
+    }
+
+    /*
+     * For TX, if data is less than one minor loop, then use polling method.
+     * For RX, if data is less than two minor loop, then use polling method.
+     */
+    if ((xfer->dataSize < handle->minorLoopBytes) ||
+        ((kFLEXIO_MCULCD_ReadArray == xfer->mode) && (xfer->dataSize < 2 * (handle->minorLoopBytes))))
+    {
+        FLEXIO_MCULCD_TransferBlocking(base, xfer);
+
+        handle->state = kFLEXIO_MCULCD_StateIdle;
+
+        /* Callback to inform upper layer. */
+        if (handle->completionCallback)
+        {
+            handle->completionCallback(base, handle, kStatus_FLEXIO_MCULCD_Idle, handle->userData);
+        }
+    }
+    else
+    {
+        handle->dataCount           = xfer->dataSize;
+        handle->remainingCount      = xfer->dataSize;
+        handle->dataAddrOrSameValue = xfer->dataAddrOrSameValue;
+
+        /* Setup DMA to transfer data.  */
+        /* Assert the nCS. */
+        FLEXIO_MCULCD_StartTransfer(base);
+        /* Send the command. */
+        FLEXIO_MCULCD_WriteCommandBlocking(base, xfer->command);
+
+        /* Setup the DMA configuration. */
+        FLEXIO_MCULCD_EDMAConfig(base, handle);
+
+        /* Start the transfer. */
+        if (kFLEXIO_MCULCD_ReadArray == xfer->mode)
+        {
+            /* For 6800, assert the RDWR pin. */
+            if (kFLEXIO_MCULCD_6800 == base->busType)
+            {
+                base->setRDWRPin(true);
+            }
+            FLEXIO_MCULCD_SetMultiBeatsReadConfig(base);
+            FLEXIO_MCULCD_EnableRxDMA(base, true);
+            EDMA_StartTransfer(handle->rxDmaHandle);
+        }
+        else
+        {
+            /* For 6800, de-assert the RDWR pin. */
+            if (kFLEXIO_MCULCD_6800 == base->busType)
+            {
+                base->setRDWRPin(false);
+            }
+            FLEXIO_MCULCD_SetMultiBeatsWriteConfig(base);
+            FLEXIO_MCULCD_EnableTxDMA(base, true);
+            EDMA_StartTransfer(handle->txDmaHandle);
+        }
+    }
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Aborts a FlexIO MCULCD transfer using eDMA.
+ *
+ * param base pointer to FLEXIO_MCULCD_Type structure.
+ * param handle FlexIO MCULCD eDMA handle pointer.
+ */
+void FLEXIO_MCULCD_TransferAbortEDMA(FLEXIO_MCULCD_Type *base, flexio_mculcd_edma_handle_t *handle)
+{
+    assert(handle);
+
+    /* Disable dma. */
+    if (handle->txDmaHandle)
+    {
+        EDMA_AbortTransfer(handle->txDmaHandle);
+    }
+    if (handle->rxDmaHandle)
+    {
+        EDMA_AbortTransfer(handle->rxDmaHandle);
+    }
+
+    /* Disable DMA enable bit. */
+    FLEXIO_MCULCD_EnableTxDMA(handle->base, false);
+    FLEXIO_MCULCD_EnableRxDMA(handle->base, false);
+
+    /* Set the handle state. */
+    handle->state     = kFLEXIO_MCULCD_StateIdle;
+    handle->dataCount = 0;
+}
+
+/*!
+ * brief Gets the remaining bytes for FlexIO MCULCD eDMA transfer.
+ *
+ * param base pointer to FLEXIO_MCULCD_Type structure.
+ * param handle FlexIO MCULCD eDMA handle pointer.
+ * param count Number of count transferred so far by the eDMA transaction.
+ * retval kStatus_Success Get the transferred count Successfully.
+ * retval kStatus_NoTransferInProgress No transfer in process.
+ */
+status_t FLEXIO_MCULCD_TransferGetCountEDMA(FLEXIO_MCULCD_Type *base,
+                                            flexio_mculcd_edma_handle_t *handle,
+                                            size_t *count)
+{
+    assert(handle);
+    assert(count);
+    uint32_t state = handle->state;
+
+    if (kFLEXIO_MCULCD_StateIdle == state)
+    {
+        return kStatus_NoTransferInProgress;
+    }
+    else
+    {
+        *count = handle->dataCount - handle->remainingCount;
+
+        if (kFLEXIO_MCULCD_StateReadArray == state)
+        {
+            *count -= handle->minorLoopBytes *
+                      EDMA_GetRemainingMajorLoopCount(handle->rxDmaHandle->base, handle->rxDmaHandle->channel);
+        }
+        else
+        {
+            *count -= handle->minorLoopBytes *
+                      EDMA_GetRemainingMajorLoopCount(handle->txDmaHandle->base, handle->txDmaHandle->channel);
+        }
+    }
+
+    return kStatus_Success;
+}
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_mculcd_edma.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_mculcd_edma.h
new file mode 100644
index 00000000000..c9b000b400b
--- /dev/null
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_mculcd_edma.h
@@ -0,0 +1,153 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_FLEXIO_MCULCD_EDMA_H_
+#define _FSL_FLEXIO_MCULCD_EDMA_H_
+
+#include "fsl_edma.h"
+#include "fsl_flexio_mculcd.h"
+
+/*!
+ * @addtogroup flexio_edma_mculcd
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*@{*/
+/*! @brief FlexIO MCULCD EDMA driver version 2.0.2. */
+#define FSL_FLEXIO_MCULCD_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
+/*@}*/
+
+/*! @brief  typedef for flexio_mculcd_edma_handle_t in advance. */
+typedef struct _flexio_mculcd_edma_handle flexio_mculcd_edma_handle_t;
+
+/*! @brief FlexIO MCULCD master callback for transfer complete.
+ *
+ * When transfer finished, the callback function is called and returns the
+ * @p status as kStatus_FLEXIO_MCULCD_Idle.
+ */
+typedef void (*flexio_mculcd_edma_transfer_callback_t)(FLEXIO_MCULCD_Type *base,
+                                                       flexio_mculcd_edma_handle_t *handle,
+                                                       status_t status,
+                                                       void *userData);
+
+/*! @brief FlexIO MCULCD eDMA transfer handle, users should not touch the
+ * content of the handle.*/
+struct _flexio_mculcd_edma_handle
+{
+    FLEXIO_MCULCD_Type *base;       /*!< Pointer to the FLEXIO_MCULCD_Type. */
+    uint8_t txShifterNum;           /*!< Number of shifters used for TX. */
+    uint8_t rxShifterNum;           /*!< Number of shifters used for RX. */
+    uint32_t minorLoopBytes;        /*!< eDMA transfer minor loop bytes. */
+    edma_modulo_t txEdmaModulo;     /*!< Modulo value for the FlexIO shifter buffer access. */
+    edma_modulo_t rxEdmaModulo;     /*!< Modulo value for the FlexIO shifter buffer access. */
+    uint32_t dataAddrOrSameValue;   /*!< When sending the same value for many times,
+                                         this is the value to send. When writing or
+                                         reading array, this is the address of the
+                                         data array. */
+    size_t dataCount;               /*!< Total count to be transferred. */
+    volatile size_t remainingCount; /*!< Remaining count still not transfered. */
+    volatile uint32_t state;        /*!< FlexIO MCULCD driver internal state. */
+    edma_handle_t *txDmaHandle;     /*!< DMA handle for MCULCD TX */
+    edma_handle_t *rxDmaHandle;     /*!< DMA handle for MCULCD RX */
+    flexio_mculcd_edma_transfer_callback_t completionCallback; /*!< Callback for MCULCD DMA transfer */
+    void *userData;                                            /*!< User Data for MCULCD DMA callback */
+};
+
+/*******************************************************************************
+ * APIs
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name eDMA Transactional
+ * @{
+ */
+
+/*!
+ * @brief Initializes the FLEXO MCULCD master eDMA handle.
+ *
+ * This function initializes the FLEXO MCULCD master eDMA handle which can be
+ * used for other FLEXO MCULCD transactional APIs. For a specified FLEXO MCULCD
+ * instance, call this API once to get the initialized handle.
+ *
+ * @param base Pointer to FLEXIO_MCULCD_Type structure.
+ * @param handle Pointer to flexio_mculcd_edma_handle_t structure to store the
+ * transfer state.
+ * @param callback MCULCD transfer complete callback, NULL means no callback.
+ * @param userData callback function parameter.
+ * @param txDmaHandle User requested eDMA handle for FlexIO MCULCD eDMA TX,
+ * the DMA request source of this handle should be the first of TX shifters.
+ * @param rxDmaHandle User requested eDMA handle for FlexIO MCULCD eDMA RX,
+ * the DMA request source of this handle should be the last of RX shifters.
+ * @retval kStatus_Success Successfully create the handle.
+ */
+status_t FLEXIO_MCULCD_TransferCreateHandleEDMA(FLEXIO_MCULCD_Type *base,
+                                                flexio_mculcd_edma_handle_t *handle,
+                                                flexio_mculcd_edma_transfer_callback_t callback,
+                                                void *userData,
+                                                edma_handle_t *txDmaHandle,
+                                                edma_handle_t *rxDmaHandle);
+
+/*!
+ * @brief Performs a non-blocking FlexIO MCULCD transfer using eDMA.
+ *
+ * This function returns immediately after transfer initiates. To check whether
+ * the transfer is completed, user could:
+ * 1. Use the transfer completed callback;
+ * 2. Polling function @ref FLEXIO_MCULCD_GetTransferCountEDMA
+ *
+ * @param base pointer to FLEXIO_MCULCD_Type structure.
+ * @param handle pointer to flexio_mculcd_edma_handle_t structure to store the
+ * transfer state.
+ * @param xfer Pointer to FlexIO MCULCD transfer structure.
+ * @retval kStatus_Success Successfully start a transfer.
+ * @retval kStatus_InvalidArgument Input argument is invalid.
+ * @retval kStatus_FLEXIO_MCULCD_Busy FlexIO MCULCD is not idle, it is running another
+ * transfer.
+ */
+status_t FLEXIO_MCULCD_TransferEDMA(FLEXIO_MCULCD_Type *base,
+                                    flexio_mculcd_edma_handle_t *handle,
+                                    flexio_mculcd_transfer_t *xfer);
+
+/*!
+ * @brief Aborts a FlexIO MCULCD transfer using eDMA.
+ *
+ * @param base pointer to FLEXIO_MCULCD_Type structure.
+ * @param handle FlexIO MCULCD eDMA handle pointer.
+ */
+void FLEXIO_MCULCD_TransferAbortEDMA(FLEXIO_MCULCD_Type *base, flexio_mculcd_edma_handle_t *handle);
+
+/*!
+ * @brief Gets the remaining bytes for FlexIO MCULCD eDMA transfer.
+ *
+ * @param base pointer to FLEXIO_MCULCD_Type structure.
+ * @param handle FlexIO MCULCD eDMA handle pointer.
+ * @param count Number of count transferred so far by the eDMA transaction.
+ * @retval kStatus_Success Get the transferred count Successfully.
+ * @retval kStatus_NoTransferInProgress No transfer in process.
+ */
+status_t FLEXIO_MCULCD_TransferGetCountEDMA(FLEXIO_MCULCD_Type *base,
+                                            flexio_mculcd_edma_handle_t *handle,
+                                            size_t *count);
+
+/*! @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* _FSL_FLEXIO_MCULCD_EDMA_H_ */
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_spi.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_spi.c
index 5cae486ae87..f21de1fd022 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_spi.c
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_spi.c
@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
  * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include "fsl_flexio_spi.h"
@@ -43,7 +17,6 @@
 #define FSL_COMPONENT_ID "platform.drivers.flexio_spi"
 #endif
 
-
 /*! @brief FLEXIO SPI transfer state, which is used for SPI transactiaonl APIs' internal state. */
 enum _flexio_spi_transfer_states
 {
@@ -163,6 +136,42 @@ static void FLEXIO_SPI_TransferReceiveTransaction(FLEXIO_SPI_Type *base, flexio_
     handle->rxRemainingBytes -= handle->bytePerFrame;
 }
 
+/*!
+ * brief Ungates the FlexIO clock, resets the FlexIO module, configures the FlexIO SPI master hardware,
+ * and configures the FlexIO SPI with FlexIO SPI master configuration. The
+ * configuration structure can be filled by the user, or be set with default values
+ * by the FLEXIO_SPI_MasterGetDefaultConfig().
+ *
+ * note FlexIO SPI master only support CPOL = 0, which means clock inactive low.
+ *
+ * Example
+   code
+   FLEXIO_SPI_Type spiDev = {
+   .flexioBase = FLEXIO,
+   .SDOPinIndex = 0,
+   .SDIPinIndex = 1,
+   .SCKPinIndex = 2,
+   .CSnPinIndex = 3,
+   .shifterIndex = {0,1},
+   .timerIndex = {0,1}
+   };
+   flexio_spi_master_config_t config = {
+   .enableMaster = true,
+   .enableInDoze = false,
+   .enableInDebug = true,
+   .enableFastAccess = false,
+   .baudRate_Bps = 500000,
+   .phase = kFLEXIO_SPI_ClockPhaseFirstEdge,
+   .direction = kFLEXIO_SPI_MsbFirst,
+   .dataMode = kFLEXIO_SPI_8BitMode
+   };
+   FLEXIO_SPI_MasterInit(&spiDev, &config, srcClock_Hz);
+   endcode
+ *
+ * param base Pointer to the FLEXIO_SPI_Type structure.
+ * param masterConfig Pointer to the flexio_spi_master_config_t structure.
+ * param srcClock_Hz FlexIO source clock in Hz.
+*/
 void FLEXIO_SPI_MasterInit(FLEXIO_SPI_Type *base, flexio_spi_master_config_t *masterConfig, uint32_t srcClock_Hz)
 {
     assert(base);
@@ -170,7 +179,7 @@ void FLEXIO_SPI_MasterInit(FLEXIO_SPI_Type *base, flexio_spi_master_config_t *ma
 
     flexio_shifter_config_t shifterConfig;
     flexio_timer_config_t timerConfig;
-    uint32_t ctrlReg = 0;
+    uint32_t ctrlReg  = 0;
     uint16_t timerDiv = 0;
     uint16_t timerCmp = 0;
 
@@ -198,34 +207,34 @@ void FLEXIO_SPI_MasterInit(FLEXIO_SPI_Type *base, flexio_spi_master_config_t *ma
     /* Do hardware configuration. */
     /* 1. Configure the shifter 0 for tx. */
     shifterConfig.timerSelect = base->timerIndex[0];
-    shifterConfig.pinConfig = kFLEXIO_PinConfigOutput;
-    shifterConfig.pinSelect = base->SDOPinIndex;
+    shifterConfig.pinConfig   = kFLEXIO_PinConfigOutput;
+    shifterConfig.pinSelect   = base->SDOPinIndex;
     shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh;
     shifterConfig.shifterMode = kFLEXIO_ShifterModeTransmit;
     shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin;
     if (masterConfig->phase == kFLEXIO_SPI_ClockPhaseFirstEdge)
     {
         shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnNegitive;
-        shifterConfig.shifterStop = kFLEXIO_ShifterStopBitDisable;
-        shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable;
+        shifterConfig.shifterStop   = kFLEXIO_ShifterStopBitDisable;
+        shifterConfig.shifterStart  = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable;
     }
     else
     {
         shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive;
-        shifterConfig.shifterStop = kFLEXIO_ShifterStopBitLow;
-        shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnShift;
+        shifterConfig.shifterStop   = kFLEXIO_ShifterStopBitLow;
+        shifterConfig.shifterStart  = kFLEXIO_ShifterStartBitDisabledLoadDataOnShift;
     }
 
     FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[0], &shifterConfig);
 
     /* 2. Configure the shifter 1 for rx. */
-    shifterConfig.timerSelect = base->timerIndex[0];
-    shifterConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled;
-    shifterConfig.pinSelect = base->SDIPinIndex;
-    shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh;
-    shifterConfig.shifterMode = kFLEXIO_ShifterModeReceive;
-    shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin;
-    shifterConfig.shifterStop = kFLEXIO_ShifterStopBitDisable;
+    shifterConfig.timerSelect  = base->timerIndex[0];
+    shifterConfig.pinConfig    = kFLEXIO_PinConfigOutputDisabled;
+    shifterConfig.pinSelect    = base->SDIPinIndex;
+    shifterConfig.pinPolarity  = kFLEXIO_PinActiveHigh;
+    shifterConfig.shifterMode  = kFLEXIO_ShifterModeReceive;
+    shifterConfig.inputSource  = kFLEXIO_ShifterInputFromPin;
+    shifterConfig.shifterStop  = kFLEXIO_ShifterStopBitDisable;
     shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable;
     if (masterConfig->phase == kFLEXIO_SPI_ClockPhaseFirstEdge)
     {
@@ -239,20 +248,20 @@ void FLEXIO_SPI_MasterInit(FLEXIO_SPI_Type *base, flexio_spi_master_config_t *ma
     FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[1], &shifterConfig);
 
     /*3. Configure the timer 0 for SCK. */
-    timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->shifterIndex[0]);
+    timerConfig.triggerSelect   = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->shifterIndex[0]);
     timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow;
-    timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal;
-    timerConfig.pinConfig = kFLEXIO_PinConfigOutput;
-    timerConfig.pinSelect = base->SCKPinIndex;
-    timerConfig.pinPolarity = kFLEXIO_PinActiveHigh;
-    timerConfig.timerMode = kFLEXIO_TimerModeDual8BitBaudBit;
-    timerConfig.timerOutput = kFLEXIO_TimerOutputZeroNotAffectedByReset;
-    timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput;
-    timerConfig.timerReset = kFLEXIO_TimerResetNever;
-    timerConfig.timerDisable = kFLEXIO_TimerDisableOnTimerCompare;
-    timerConfig.timerEnable = kFLEXIO_TimerEnableOnTriggerHigh;
-    timerConfig.timerStop = kFLEXIO_TimerStopBitEnableOnTimerDisable;
-    timerConfig.timerStart = kFLEXIO_TimerStartBitEnabled;
+    timerConfig.triggerSource   = kFLEXIO_TimerTriggerSourceInternal;
+    timerConfig.pinConfig       = kFLEXIO_PinConfigOutput;
+    timerConfig.pinSelect       = base->SCKPinIndex;
+    timerConfig.pinPolarity     = kFLEXIO_PinActiveHigh;
+    timerConfig.timerMode       = kFLEXIO_TimerModeDual8BitBaudBit;
+    timerConfig.timerOutput     = kFLEXIO_TimerOutputZeroNotAffectedByReset;
+    timerConfig.timerDecrement  = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput;
+    timerConfig.timerReset      = kFLEXIO_TimerResetNever;
+    timerConfig.timerDisable    = kFLEXIO_TimerDisableOnTimerCompare;
+    timerConfig.timerEnable     = kFLEXIO_TimerEnableOnTriggerHigh;
+    timerConfig.timerStop       = kFLEXIO_TimerStopBitEnableOnTimerDisable;
+    timerConfig.timerStart      = kFLEXIO_TimerStartBitEnabled;
 
     timerDiv = srcClock_Hz / masterConfig->baudRate_Bps;
     timerDiv = timerDiv / 2 - 1;
@@ -265,47 +274,65 @@ void FLEXIO_SPI_MasterInit(FLEXIO_SPI_Type *base, flexio_spi_master_config_t *ma
     FLEXIO_SetTimerConfig(base->flexioBase, base->timerIndex[0], &timerConfig);
 
     /* 4. Configure the timer 1 for CSn. */
-    timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_TIMn(base->timerIndex[0]);
+    timerConfig.triggerSelect   = FLEXIO_TIMER_TRIGGER_SEL_TIMn(base->timerIndex[0]);
     timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveHigh;
-    timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal;
-    timerConfig.pinConfig = kFLEXIO_PinConfigOutput;
-    timerConfig.pinSelect = base->CSnPinIndex;
-    timerConfig.pinPolarity = kFLEXIO_PinActiveLow;
-    timerConfig.timerMode = kFLEXIO_TimerModeSingle16Bit;
-    timerConfig.timerOutput = kFLEXIO_TimerOutputOneNotAffectedByReset;
-    timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput;
-    timerConfig.timerReset = kFLEXIO_TimerResetNever;
-    timerConfig.timerDisable = kFLEXIO_TimerDisableOnPreTimerDisable;
-    timerConfig.timerEnable = kFLEXIO_TimerEnableOnPrevTimerEnable;
-    timerConfig.timerStop = kFLEXIO_TimerStopBitDisabled;
-    timerConfig.timerStart = kFLEXIO_TimerStartBitDisabled;
+    timerConfig.triggerSource   = kFLEXIO_TimerTriggerSourceInternal;
+    timerConfig.pinConfig       = kFLEXIO_PinConfigOutput;
+    timerConfig.pinSelect       = base->CSnPinIndex;
+    timerConfig.pinPolarity     = kFLEXIO_PinActiveLow;
+    timerConfig.timerMode       = kFLEXIO_TimerModeSingle16Bit;
+    timerConfig.timerOutput     = kFLEXIO_TimerOutputOneNotAffectedByReset;
+    timerConfig.timerDecrement  = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput;
+    timerConfig.timerReset      = kFLEXIO_TimerResetNever;
+    timerConfig.timerDisable    = kFLEXIO_TimerDisableOnPreTimerDisable;
+    timerConfig.timerEnable     = kFLEXIO_TimerEnableOnPrevTimerEnable;
+    timerConfig.timerStop       = kFLEXIO_TimerStopBitDisabled;
+    timerConfig.timerStart      = kFLEXIO_TimerStartBitDisabled;
 
     timerConfig.timerCompare = 0xFFFFU;
 
     FLEXIO_SetTimerConfig(base->flexioBase, base->timerIndex[1], &timerConfig);
 }
 
+/*!
+ * brief Resets the FlexIO SPI timer and shifter config.
+ *
+ * param base Pointer to the FLEXIO_SPI_Type.
+ */
 void FLEXIO_SPI_MasterDeinit(FLEXIO_SPI_Type *base)
 {
     base->flexioBase->SHIFTCFG[base->shifterIndex[0]] = 0;
     base->flexioBase->SHIFTCTL[base->shifterIndex[0]] = 0;
     base->flexioBase->SHIFTCFG[base->shifterIndex[1]] = 0;
     base->flexioBase->SHIFTCTL[base->shifterIndex[1]] = 0;
-    base->flexioBase->TIMCFG[base->timerIndex[0]] = 0;
-    base->flexioBase->TIMCMP[base->timerIndex[0]] = 0;
-    base->flexioBase->TIMCTL[base->timerIndex[0]] = 0;
-    base->flexioBase->TIMCFG[base->timerIndex[1]] = 0;
-    base->flexioBase->TIMCMP[base->timerIndex[1]] = 0;
-    base->flexioBase->TIMCTL[base->timerIndex[1]] = 0;
+    base->flexioBase->TIMCFG[base->timerIndex[0]]     = 0;
+    base->flexioBase->TIMCMP[base->timerIndex[0]]     = 0;
+    base->flexioBase->TIMCTL[base->timerIndex[0]]     = 0;
+    base->flexioBase->TIMCFG[base->timerIndex[1]]     = 0;
+    base->flexioBase->TIMCMP[base->timerIndex[1]]     = 0;
+    base->flexioBase->TIMCTL[base->timerIndex[1]]     = 0;
 }
 
+/*!
+ * brief Gets the default configuration to configure the FlexIO SPI master. The configuration
+ * can be used directly by calling the FLEXIO_SPI_MasterConfigure().
+ * Example:
+   code
+   flexio_spi_master_config_t masterConfig;
+   FLEXIO_SPI_MasterGetDefaultConfig(&masterConfig);
+   endcode
+ * param masterConfig Pointer to the flexio_spi_master_config_t structure.
+*/
 void FLEXIO_SPI_MasterGetDefaultConfig(flexio_spi_master_config_t *masterConfig)
 {
     assert(masterConfig);
 
-    masterConfig->enableMaster = true;
-    masterConfig->enableInDoze = false;
-    masterConfig->enableInDebug = true;
+    /* Initializes the configure structure to zero. */
+    memset(masterConfig, 0, sizeof(*masterConfig));
+
+    masterConfig->enableMaster     = true;
+    masterConfig->enableInDoze     = false;
+    masterConfig->enableInDebug    = true;
     masterConfig->enableFastAccess = false;
     /* Default baud rate 500kbps. */
     masterConfig->baudRate_Bps = 500000U;
@@ -315,6 +342,39 @@ void FLEXIO_SPI_MasterGetDefaultConfig(flexio_spi_master_config_t *masterConfig)
     masterConfig->dataMode = kFLEXIO_SPI_8BitMode;
 }
 
+/*!
+ * brief Ungates the FlexIO clock, resets the FlexIO module, configures the FlexIO SPI slave hardware
+ * configuration, and configures the FlexIO SPI with FlexIO SPI slave configuration. The
+ * configuration structure can be filled by the user, or be set with default values
+ * by the FLEXIO_SPI_SlaveGetDefaultConfig().
+ *
+ * note Only one timer is needed in the FlexIO SPI slave. As a result, the second timer index is ignored.
+ * FlexIO SPI slave only support CPOL = 0, which means clock inactive low.
+ * Example
+   code
+   FLEXIO_SPI_Type spiDev = {
+   .flexioBase = FLEXIO,
+   .SDOPinIndex = 0,
+   .SDIPinIndex = 1,
+   .SCKPinIndex = 2,
+   .CSnPinIndex = 3,
+   .shifterIndex = {0,1},
+   .timerIndex = {0}
+   };
+   flexio_spi_slave_config_t config = {
+   .enableSlave = true,
+   .enableInDoze = false,
+   .enableInDebug = true,
+   .enableFastAccess = false,
+   .phase = kFLEXIO_SPI_ClockPhaseFirstEdge,
+   .direction = kFLEXIO_SPI_MsbFirst,
+   .dataMode = kFLEXIO_SPI_8BitMode
+   };
+   FLEXIO_SPI_SlaveInit(&spiDev, &config);
+   endcode
+ * param base Pointer to the FLEXIO_SPI_Type structure.
+ * param slaveConfig Pointer to the flexio_spi_slave_config_t structure.
+*/
 void FLEXIO_SPI_SlaveInit(FLEXIO_SPI_Type *base, flexio_spi_slave_config_t *slaveConfig)
 {
     assert(base && slaveConfig);
@@ -347,8 +407,8 @@ void FLEXIO_SPI_SlaveInit(FLEXIO_SPI_Type *base, flexio_spi_slave_config_t *slav
     /* Do hardware configuration. */
     /* 1. Configure the shifter 0 for tx. */
     shifterConfig.timerSelect = base->timerIndex[0];
-    shifterConfig.pinConfig = kFLEXIO_PinConfigOutput;
-    shifterConfig.pinSelect = base->SDOPinIndex;
+    shifterConfig.pinConfig   = kFLEXIO_PinConfigOutput;
+    shifterConfig.pinSelect   = base->SDOPinIndex;
     shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh;
     shifterConfig.shifterMode = kFLEXIO_ShifterModeTransmit;
     shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin;
@@ -356,24 +416,24 @@ void FLEXIO_SPI_SlaveInit(FLEXIO_SPI_Type *base, flexio_spi_slave_config_t *slav
     if (slaveConfig->phase == kFLEXIO_SPI_ClockPhaseFirstEdge)
     {
         shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnNegitive;
-        shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable;
+        shifterConfig.shifterStart  = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable;
     }
     else
     {
         shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive;
-        shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnShift;
+        shifterConfig.shifterStart  = kFLEXIO_ShifterStartBitDisabledLoadDataOnShift;
     }
 
     FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[0], &shifterConfig);
 
     /* 2. Configure the shifter 1 for rx. */
-    shifterConfig.timerSelect = base->timerIndex[0];
-    shifterConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled;
-    shifterConfig.pinSelect = base->SDIPinIndex;
-    shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh;
-    shifterConfig.shifterMode = kFLEXIO_ShifterModeReceive;
-    shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin;
-    shifterConfig.shifterStop = kFLEXIO_ShifterStopBitDisable;
+    shifterConfig.timerSelect  = base->timerIndex[0];
+    shifterConfig.pinConfig    = kFLEXIO_PinConfigOutputDisabled;
+    shifterConfig.pinSelect    = base->SDIPinIndex;
+    shifterConfig.pinPolarity  = kFLEXIO_PinActiveHigh;
+    shifterConfig.shifterMode  = kFLEXIO_ShifterModeReceive;
+    shifterConfig.inputSource  = kFLEXIO_ShifterInputFromPin;
+    shifterConfig.shifterStop  = kFLEXIO_ShifterStopBitDisable;
     shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable;
     if (slaveConfig->phase == kFLEXIO_SPI_ClockPhaseFirstEdge)
     {
@@ -387,29 +447,29 @@ void FLEXIO_SPI_SlaveInit(FLEXIO_SPI_Type *base, flexio_spi_slave_config_t *slav
     FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[1], &shifterConfig);
 
     /*3. Configure the timer 0 for shift clock. */
-    timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_PININPUT(base->CSnPinIndex);
+    timerConfig.triggerSelect   = FLEXIO_TIMER_TRIGGER_SEL_PININPUT(base->CSnPinIndex);
     timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow;
-    timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal;
-    timerConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled;
-    timerConfig.pinSelect = base->SCKPinIndex;
-    timerConfig.pinPolarity = kFLEXIO_PinActiveHigh;
-    timerConfig.timerMode = kFLEXIO_TimerModeSingle16Bit;
-    timerConfig.timerOutput = kFLEXIO_TimerOutputZeroNotAffectedByReset;
-    timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnPinInputShiftPinInput;
-    timerConfig.timerReset = kFLEXIO_TimerResetNever;
-    timerConfig.timerEnable = kFLEXIO_TimerEnableOnTriggerRisingEdge;
-    timerConfig.timerStop = kFLEXIO_TimerStopBitDisabled;
+    timerConfig.triggerSource   = kFLEXIO_TimerTriggerSourceInternal;
+    timerConfig.pinConfig       = kFLEXIO_PinConfigOutputDisabled;
+    timerConfig.pinSelect       = base->SCKPinIndex;
+    timerConfig.pinPolarity     = kFLEXIO_PinActiveHigh;
+    timerConfig.timerMode       = kFLEXIO_TimerModeSingle16Bit;
+    timerConfig.timerOutput     = kFLEXIO_TimerOutputZeroNotAffectedByReset;
+    timerConfig.timerDecrement  = kFLEXIO_TimerDecSrcOnPinInputShiftPinInput;
+    timerConfig.timerReset      = kFLEXIO_TimerResetNever;
+    timerConfig.timerEnable     = kFLEXIO_TimerEnableOnTriggerRisingEdge;
+    timerConfig.timerStop       = kFLEXIO_TimerStopBitDisabled;
     if (slaveConfig->phase == kFLEXIO_SPI_ClockPhaseFirstEdge)
     {
         /* The configuration kFLEXIO_TimerDisableOnTimerCompare only support continuous
         PCS access, change to kFLEXIO_TimerDisableNever to enable discontinuous PCS access. */
         timerConfig.timerDisable = kFLEXIO_TimerDisableOnTimerCompare;
-        timerConfig.timerStart = kFLEXIO_TimerStartBitDisabled;
+        timerConfig.timerStart   = kFLEXIO_TimerStartBitDisabled;
     }
     else
     {
         timerConfig.timerDisable = kFLEXIO_TimerDisableOnTriggerFallingEdge;
-        timerConfig.timerStart = kFLEXIO_TimerStartBitEnabled;
+        timerConfig.timerStart   = kFLEXIO_TimerStartBitEnabled;
     }
 
     timerConfig.timerCompare = slaveConfig->dataMode * 2 - 1U;
@@ -417,18 +477,36 @@ void FLEXIO_SPI_SlaveInit(FLEXIO_SPI_Type *base, flexio_spi_slave_config_t *slav
     FLEXIO_SetTimerConfig(base->flexioBase, base->timerIndex[0], &timerConfig);
 }
 
+/*!
+ * brief Gates the FlexIO clock.
+ *
+ * param base Pointer to the FLEXIO_SPI_Type.
+ */
 void FLEXIO_SPI_SlaveDeinit(FLEXIO_SPI_Type *base)
 {
     FLEXIO_SPI_MasterDeinit(base);
 }
 
+/*!
+ * brief Gets the default configuration to configure the FlexIO SPI slave. The configuration
+ * can be used directly for calling the FLEXIO_SPI_SlaveConfigure().
+ * Example:
+   code
+   flexio_spi_slave_config_t slaveConfig;
+   FLEXIO_SPI_SlaveGetDefaultConfig(&slaveConfig);
+   endcode
+ * param slaveConfig Pointer to the flexio_spi_slave_config_t structure.
+*/
 void FLEXIO_SPI_SlaveGetDefaultConfig(flexio_spi_slave_config_t *slaveConfig)
 {
     assert(slaveConfig);
 
-    slaveConfig->enableSlave = true;
-    slaveConfig->enableInDoze = false;
-    slaveConfig->enableInDebug = true;
+    /* Initializes the configure structure to zero. */
+    memset(slaveConfig, 0, sizeof(*slaveConfig));
+
+    slaveConfig->enableSlave      = true;
+    slaveConfig->enableInDoze     = false;
+    slaveConfig->enableInDebug    = true;
     slaveConfig->enableFastAccess = false;
     /* Default CPHA = 0. */
     slaveConfig->phase = kFLEXIO_SPI_ClockPhaseFirstEdge;
@@ -436,6 +514,16 @@ void FLEXIO_SPI_SlaveGetDefaultConfig(flexio_spi_slave_config_t *slaveConfig)
     slaveConfig->dataMode = kFLEXIO_SPI_8BitMode;
 }
 
+/*!
+ * brief Enables the FlexIO SPI interrupt.
+ *
+ * This function enables the FlexIO SPI interrupt.
+ *
+ * param base Pointer to the FLEXIO_SPI_Type structure.
+ * param mask interrupt source. The parameter can be any combination of the following values:
+ *        arg kFLEXIO_SPI_RxFullInterruptEnable
+ *        arg kFLEXIO_SPI_TxEmptyInterruptEnable
+ */
 void FLEXIO_SPI_EnableInterrupts(FLEXIO_SPI_Type *base, uint32_t mask)
 {
     if (mask & kFLEXIO_SPI_TxEmptyInterruptEnable)
@@ -448,6 +536,16 @@ void FLEXIO_SPI_EnableInterrupts(FLEXIO_SPI_Type *base, uint32_t mask)
     }
 }
 
+/*!
+ * brief Disables the FlexIO SPI interrupt.
+ *
+ * This function disables the FlexIO SPI interrupt.
+ *
+ * param base Pointer to the FLEXIO_SPI_Type structure.
+ * param mask interrupt source The parameter can be any combination of the following values:
+ *        arg kFLEXIO_SPI_RxFullInterruptEnable
+ *        arg kFLEXIO_SPI_TxEmptyInterruptEnable
+ */
 void FLEXIO_SPI_DisableInterrupts(FLEXIO_SPI_Type *base, uint32_t mask)
 {
     if (mask & kFLEXIO_SPI_TxEmptyInterruptEnable)
@@ -460,6 +558,14 @@ void FLEXIO_SPI_DisableInterrupts(FLEXIO_SPI_Type *base, uint32_t mask)
     }
 }
 
+/*!
+ * brief Enables/disables the FlexIO SPI transmit DMA. This function enables/disables the FlexIO SPI Tx DMA,
+ * which means that asserting the kFLEXIO_SPI_TxEmptyFlag does/doesn't trigger the DMA request.
+ *
+ * param base Pointer to the FLEXIO_SPI_Type structure.
+ * param mask SPI DMA source.
+ * param enable True means enable DMA, false means disable DMA.
+ */
 void FLEXIO_SPI_EnableDMA(FLEXIO_SPI_Type *base, uint32_t mask, bool enable)
 {
     if (mask & kFLEXIO_SPI_TxDmaEnable)
@@ -473,10 +579,19 @@ void FLEXIO_SPI_EnableDMA(FLEXIO_SPI_Type *base, uint32_t mask, bool enable)
     }
 }
 
+/*!
+ * brief Gets FlexIO SPI status flags.
+ *
+ * param base Pointer to the FLEXIO_SPI_Type structure.
+ * return status flag; Use the status flag to AND the following flag mask and get the status.
+ *          arg kFLEXIO_SPI_TxEmptyFlag
+ *          arg kFLEXIO_SPI_RxEmptyFlag
+ */
+
 uint32_t FLEXIO_SPI_GetStatusFlags(FLEXIO_SPI_Type *base)
 {
     uint32_t shifterStatus = FLEXIO_GetShifterStatusFlags(base->flexioBase);
-    uint32_t status = 0;
+    uint32_t status        = 0;
 
     status = ((shifterStatus & (1U << base->shifterIndex[0])) >> base->shifterIndex[0]);
     status |= (((shifterStatus & (1U << base->shifterIndex[1])) >> (base->shifterIndex[1])) << 1U);
@@ -484,6 +599,16 @@ uint32_t FLEXIO_SPI_GetStatusFlags(FLEXIO_SPI_Type *base)
     return status;
 }
 
+/*!
+ * brief Clears FlexIO SPI status flags.
+ *
+ * param base Pointer to the FLEXIO_SPI_Type structure.
+ * param mask status flag
+ *      The parameter can be any combination of the following values:
+ *          arg kFLEXIO_SPI_TxEmptyFlag
+ *          arg kFLEXIO_SPI_RxEmptyFlag
+ */
+
 void FLEXIO_SPI_ClearStatusFlags(FLEXIO_SPI_Type *base, uint32_t mask)
 {
     if (mask & kFLEXIO_SPI_TxBufferEmptyFlag)
@@ -496,10 +621,17 @@ void FLEXIO_SPI_ClearStatusFlags(FLEXIO_SPI_Type *base, uint32_t mask)
     }
 }
 
+/*!
+ * brief Sets baud rate for the FlexIO SPI transfer, which is only used for the master.
+ *
+ * param base Pointer to the FLEXIO_SPI_Type structure.
+ * param baudRate_Bps Baud Rate needed in Hz.
+ * param srcClockHz SPI source clock frequency in Hz.
+ */
 void FLEXIO_SPI_MasterSetBaudRate(FLEXIO_SPI_Type *base, uint32_t baudRate_Bps, uint32_t srcClockHz)
 {
-    uint16_t timerDiv = 0;
-    uint16_t timerCmp = 0;
+    uint16_t timerDiv       = 0;
+    uint16_t timerCmp       = 0;
     FLEXIO_Type *flexioBase = base->flexioBase;
 
     /* Set TIMCMP[7:0] = (baud rate divider / 2) - 1.*/
@@ -513,6 +645,16 @@ void FLEXIO_SPI_MasterSetBaudRate(FLEXIO_SPI_Type *base, uint32_t baudRate_Bps,
     flexioBase->TIMCMP[base->timerIndex[0]] = timerCmp;
 }
 
+/*!
+ * brief Sends a buffer of data bytes.
+ *
+ * note This function blocks using the polling method until all bytes have been sent.
+ *
+ * param base Pointer to the FLEXIO_SPI_Type structure.
+ * param direction Shift direction of MSB first or LSB first.
+ * param buffer The data bytes to send.
+ * param size The number of data bytes to send.
+ */
 void FLEXIO_SPI_WriteBlocking(FLEXIO_SPI_Type *base,
                               flexio_spi_shift_direction_t direction,
                               const uint8_t *buffer,
@@ -531,6 +673,17 @@ void FLEXIO_SPI_WriteBlocking(FLEXIO_SPI_Type *base,
     }
 }
 
+/*!
+ * brief Receives a buffer of bytes.
+ *
+ * note This function blocks using the polling method until all bytes have been received.
+ *
+ * param base Pointer to the FLEXIO_SPI_Type structure.
+ * param direction Shift direction of MSB first or LSB first.
+ * param buffer The buffer to store the received bytes.
+ * param size The number of data bytes to be received.
+ * param direction Shift direction of MSB first or LSB first.
+ */
 void FLEXIO_SPI_ReadBlocking(FLEXIO_SPI_Type *base,
                              flexio_spi_shift_direction_t direction,
                              uint8_t *buffer,
@@ -549,46 +702,54 @@ void FLEXIO_SPI_ReadBlocking(FLEXIO_SPI_Type *base,
     }
 }
 
+/*!
+ * brief Receives a buffer of bytes.
+ *
+ * note This function blocks via polling until all bytes have been received.
+ *
+ * param base pointer to FLEXIO_SPI_Type structure
+ * param xfer FlexIO SPI transfer structure, see #flexio_spi_transfer_t.
+ */
 void FLEXIO_SPI_MasterTransferBlocking(FLEXIO_SPI_Type *base, flexio_spi_transfer_t *xfer)
 {
     flexio_spi_shift_direction_t direction;
     uint8_t bytesPerFrame;
     uint32_t dataMode = 0;
     uint16_t timerCmp = base->flexioBase->TIMCMP[base->timerIndex[0]];
-    uint16_t tmpData = FLEXIO_SPI_DUMMYDATA;
+    uint16_t tmpData  = FLEXIO_SPI_DUMMYDATA;
 
     timerCmp &= 0x00FFU;
     /* Configure the values in handle. */
     switch (xfer->flags)
     {
         case kFLEXIO_SPI_8bitMsb:
-            dataMode = (8 * 2 - 1U) << 8U;
+            dataMode      = (8 * 2 - 1U) << 8U;
             bytesPerFrame = 1;
-            direction = kFLEXIO_SPI_MsbFirst;
+            direction     = kFLEXIO_SPI_MsbFirst;
             break;
 
         case kFLEXIO_SPI_8bitLsb:
-            dataMode = (8 * 2 - 1U) << 8U;
+            dataMode      = (8 * 2 - 1U) << 8U;
             bytesPerFrame = 1;
-            direction = kFLEXIO_SPI_LsbFirst;
+            direction     = kFLEXIO_SPI_LsbFirst;
             break;
 
         case kFLEXIO_SPI_16bitMsb:
-            dataMode = (16 * 2 - 1U) << 8U;
+            dataMode      = (16 * 2 - 1U) << 8U;
             bytesPerFrame = 2;
-            direction = kFLEXIO_SPI_MsbFirst;
+            direction     = kFLEXIO_SPI_MsbFirst;
             break;
 
         case kFLEXIO_SPI_16bitLsb:
-            dataMode = (16 * 2 - 1U) << 8U;
+            dataMode      = (16 * 2 - 1U) << 8U;
             bytesPerFrame = 2;
-            direction = kFLEXIO_SPI_LsbFirst;
+            direction     = kFLEXIO_SPI_LsbFirst;
             break;
 
         default:
-            dataMode = (8 * 2 - 1U) << 8U;
+            dataMode      = (8 * 2 - 1U) << 8U;
             bytesPerFrame = 1;
-            direction = kFLEXIO_SPI_MsbFirst;
+            direction     = kFLEXIO_SPI_MsbFirst;
             assert(true);
             break;
     }
@@ -664,6 +825,16 @@ void FLEXIO_SPI_MasterTransferBlocking(FLEXIO_SPI_Type *base, flexio_spi_transfe
     }
 }
 
+/*!
+ * brief Initializes the FlexIO SPI Master handle, which is used in transactional functions.
+ *
+ * param base Pointer to the FLEXIO_SPI_Type structure.
+ * param handle Pointer to the flexio_spi_master_handle_t structure to store the transfer state.
+ * param callback The callback function.
+ * param userData The parameter of the callback function.
+ * retval kStatus_Success Successfully create the handle.
+ * retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range.
+ */
 status_t FLEXIO_SPI_MasterTransferCreateHandle(FLEXIO_SPI_Type *base,
                                                flexio_spi_master_handle_t *handle,
                                                flexio_spi_master_transfer_callback_t callback,
@@ -687,6 +858,19 @@ status_t FLEXIO_SPI_MasterTransferCreateHandle(FLEXIO_SPI_Type *base,
     return FLEXIO_RegisterHandleIRQ(base, handle, FLEXIO_SPI_MasterTransferHandleIRQ);
 }
 
+/*!
+ * brief Master transfer data using IRQ.
+ *
+ * This function sends data using IRQ. This is a non-blocking function, which returns
+ * right away. When all data is sent out/received, the callback function is called.
+ *
+ * param base Pointer to the FLEXIO_SPI_Type structure.
+ * param handle Pointer to the flexio_spi_master_handle_t structure to store the transfer state.
+ * param xfer FlexIO SPI transfer structure. See #flexio_spi_transfer_t.
+ * retval kStatus_Success Successfully start a transfer.
+ * retval kStatus_InvalidArgument Input argument is invalid.
+ * retval kStatus_FLEXIO_SPI_Busy SPI is not idle, is running another transfer.
+ */
 status_t FLEXIO_SPI_MasterTransferNonBlocking(FLEXIO_SPI_Type *base,
                                               flexio_spi_master_handle_t *handle,
                                               flexio_spi_transfer_t *xfer)
@@ -696,7 +880,7 @@ status_t FLEXIO_SPI_MasterTransferNonBlocking(FLEXIO_SPI_Type *base,
 
     uint32_t dataMode = 0;
     uint16_t timerCmp = base->flexioBase->TIMCMP[base->timerIndex[0]];
-    uint16_t tmpData = FLEXIO_SPI_DUMMYDATA;
+    uint16_t tmpData  = FLEXIO_SPI_DUMMYDATA;
 
     timerCmp &= 0x00FFU;
 
@@ -716,29 +900,29 @@ status_t FLEXIO_SPI_MasterTransferNonBlocking(FLEXIO_SPI_Type *base,
     switch (xfer->flags)
     {
         case kFLEXIO_SPI_8bitMsb:
-            dataMode = (8 * 2 - 1U) << 8U;
+            dataMode             = (8 * 2 - 1U) << 8U;
             handle->bytePerFrame = 1U;
-            handle->direction = kFLEXIO_SPI_MsbFirst;
+            handle->direction    = kFLEXIO_SPI_MsbFirst;
             break;
         case kFLEXIO_SPI_8bitLsb:
-            dataMode = (8 * 2 - 1U) << 8U;
+            dataMode             = (8 * 2 - 1U) << 8U;
             handle->bytePerFrame = 1U;
-            handle->direction = kFLEXIO_SPI_LsbFirst;
+            handle->direction    = kFLEXIO_SPI_LsbFirst;
             break;
         case kFLEXIO_SPI_16bitMsb:
-            dataMode = (16 * 2 - 1U) << 8U;
+            dataMode             = (16 * 2 - 1U) << 8U;
             handle->bytePerFrame = 2U;
-            handle->direction = kFLEXIO_SPI_MsbFirst;
+            handle->direction    = kFLEXIO_SPI_MsbFirst;
             break;
         case kFLEXIO_SPI_16bitLsb:
-            dataMode = (16 * 2 - 1U) << 8U;
+            dataMode             = (16 * 2 - 1U) << 8U;
             handle->bytePerFrame = 2U;
-            handle->direction = kFLEXIO_SPI_LsbFirst;
+            handle->direction    = kFLEXIO_SPI_LsbFirst;
             break;
         default:
-            dataMode = (8 * 2 - 1U) << 8U;
+            dataMode             = (8 * 2 - 1U) << 8U;
             handle->bytePerFrame = 1U;
-            handle->direction = kFLEXIO_SPI_MsbFirst;
+            handle->direction    = kFLEXIO_SPI_MsbFirst;
             assert(true);
             break;
     }
@@ -748,9 +932,9 @@ status_t FLEXIO_SPI_MasterTransferNonBlocking(FLEXIO_SPI_Type *base,
     /* Configure transfer size. */
     base->flexioBase->TIMCMP[base->timerIndex[0]] = dataMode;
 
-    handle->state = kFLEXIO_SPI_Busy;
-    handle->txData = xfer->txData;
-    handle->rxData = xfer->rxData;
+    handle->state            = kFLEXIO_SPI_Busy;
+    handle->txData           = xfer->txData;
+    handle->rxData           = xfer->rxData;
     handle->rxRemainingBytes = xfer->dataSize;
 
     /* Save total transfer size. */
@@ -795,6 +979,15 @@ status_t FLEXIO_SPI_MasterTransferNonBlocking(FLEXIO_SPI_Type *base,
     return kStatus_Success;
 }
 
+/*!
+ * brief Gets the data transfer status which used IRQ.
+ *
+ * param base Pointer to the FLEXIO_SPI_Type structure.
+ * param handle Pointer to the flexio_spi_master_handle_t structure to store the transfer state.
+ * param count Number of bytes transferred so far by the non-blocking transaction.
+ * retval kStatus_InvalidArgument count is Invalid.
+ * retval kStatus_Success Successfully return the count.
+ */
 status_t FLEXIO_SPI_MasterTransferGetCount(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle, size_t *count)
 {
     assert(handle);
@@ -817,6 +1010,12 @@ status_t FLEXIO_SPI_MasterTransferGetCount(FLEXIO_SPI_Type *base, flexio_spi_mas
     return kStatus_Success;
 }
 
+/*!
+ * brief Aborts the master data transfer, which used IRQ.
+ *
+ * param base Pointer to the FLEXIO_SPI_Type structure.
+ * param handle Pointer to the flexio_spi_master_handle_t structure to store the transfer state.
+ */
 void FLEXIO_SPI_MasterTransferAbort(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle)
 {
     assert(handle);
@@ -832,6 +1031,12 @@ void FLEXIO_SPI_MasterTransferAbort(FLEXIO_SPI_Type *base, flexio_spi_master_han
     handle->txRemainingBytes = 0;
 }
 
+/*!
+ * brief FlexIO SPI master IRQ handler function.
+ *
+ * param spiType Pointer to the FLEXIO_SPI_Type structure.
+ * param spiHandle Pointer to the flexio_spi_master_handle_t structure to store the transfer state.
+ */
 void FLEXIO_SPI_MasterTransferHandleIRQ(void *spiType, void *spiHandle)
 {
     assert(spiHandle);
@@ -845,7 +1050,7 @@ void FLEXIO_SPI_MasterTransferHandleIRQ(void *spiType, void *spiHandle)
         return;
     }
 
-    base = (FLEXIO_SPI_Type *)spiType;
+    base   = (FLEXIO_SPI_Type *)spiType;
     status = FLEXIO_SPI_GetStatusFlags(base);
 
     /* Handle rx. */
@@ -871,6 +1076,16 @@ void FLEXIO_SPI_MasterTransferHandleIRQ(void *spiType, void *spiHandle)
     }
 }
 
+/*!
+ * brief Initializes the FlexIO SPI Slave handle, which is used in transactional functions.
+ *
+ * param base Pointer to the FLEXIO_SPI_Type structure.
+ * param handle Pointer to the flexio_spi_slave_handle_t structure to store the transfer state.
+ * param callback The callback function.
+ * param userData The parameter of the callback function.
+ * retval kStatus_Success Successfully create the handle.
+ * retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range.
+ */
 status_t FLEXIO_SPI_SlaveTransferCreateHandle(FLEXIO_SPI_Type *base,
                                               flexio_spi_slave_handle_t *handle,
                                               flexio_spi_slave_transfer_callback_t callback,
@@ -894,6 +1109,19 @@ status_t FLEXIO_SPI_SlaveTransferCreateHandle(FLEXIO_SPI_Type *base,
     return FLEXIO_RegisterHandleIRQ(base, handle, FLEXIO_SPI_SlaveTransferHandleIRQ);
 }
 
+/*!
+ * brief Slave transfer data using IRQ.
+ *
+ * This function sends data using IRQ. This is a non-blocking function, which returns
+ * right away. When all data is sent out/received, the callback function is called.
+ * param handle Pointer to the flexio_spi_slave_handle_t structure to store the transfer state.
+ *
+ * param base Pointer to the FLEXIO_SPI_Type structure.
+ * param xfer FlexIO SPI transfer structure. See #flexio_spi_transfer_t.
+ * retval kStatus_Success Successfully start a transfer.
+ * retval kStatus_InvalidArgument Input argument is invalid.
+ * retval kStatus_FLEXIO_SPI_Busy SPI is not idle; it is running another transfer.
+ */
 status_t FLEXIO_SPI_SlaveTransferNonBlocking(FLEXIO_SPI_Type *base,
                                              flexio_spi_slave_handle_t *handle,
                                              flexio_spi_transfer_t *xfer)
@@ -919,29 +1147,29 @@ status_t FLEXIO_SPI_SlaveTransferNonBlocking(FLEXIO_SPI_Type *base,
     switch (xfer->flags)
     {
         case kFLEXIO_SPI_8bitMsb:
-            dataMode = 8 * 2 - 1U;
+            dataMode             = 8 * 2 - 1U;
             handle->bytePerFrame = 1U;
-            handle->direction = kFLEXIO_SPI_MsbFirst;
+            handle->direction    = kFLEXIO_SPI_MsbFirst;
             break;
         case kFLEXIO_SPI_8bitLsb:
-            dataMode = 8 * 2 - 1U;
+            dataMode             = 8 * 2 - 1U;
             handle->bytePerFrame = 1U;
-            handle->direction = kFLEXIO_SPI_LsbFirst;
+            handle->direction    = kFLEXIO_SPI_LsbFirst;
             break;
         case kFLEXIO_SPI_16bitMsb:
-            dataMode = 16 * 2 - 1U;
+            dataMode             = 16 * 2 - 1U;
             handle->bytePerFrame = 2U;
-            handle->direction = kFLEXIO_SPI_MsbFirst;
+            handle->direction    = kFLEXIO_SPI_MsbFirst;
             break;
         case kFLEXIO_SPI_16bitLsb:
-            dataMode = 16 * 2 - 1U;
+            dataMode             = 16 * 2 - 1U;
             handle->bytePerFrame = 2U;
-            handle->direction = kFLEXIO_SPI_LsbFirst;
+            handle->direction    = kFLEXIO_SPI_LsbFirst;
             break;
         default:
-            dataMode = 8 * 2 - 1U;
+            dataMode             = 8 * 2 - 1U;
             handle->bytePerFrame = 1U;
-            handle->direction = kFLEXIO_SPI_MsbFirst;
+            handle->direction    = kFLEXIO_SPI_MsbFirst;
             assert(true);
             break;
     }
@@ -949,9 +1177,9 @@ status_t FLEXIO_SPI_SlaveTransferNonBlocking(FLEXIO_SPI_Type *base,
     /* Configure transfer size. */
     base->flexioBase->TIMCMP[base->timerIndex[0]] = dataMode;
 
-    handle->state = kFLEXIO_SPI_Busy;
-    handle->txData = xfer->txData;
-    handle->rxData = xfer->rxData;
+    handle->state            = kFLEXIO_SPI_Busy;
+    handle->txData           = xfer->txData;
+    handle->rxData           = xfer->rxData;
     handle->txRemainingBytes = xfer->dataSize;
     handle->rxRemainingBytes = xfer->dataSize;
 
@@ -965,6 +1193,12 @@ status_t FLEXIO_SPI_SlaveTransferNonBlocking(FLEXIO_SPI_Type *base,
     return kStatus_Success;
 }
 
+/*!
+ * brief FlexIO SPI slave IRQ handler function.
+ *
+ * param spiType Pointer to the FLEXIO_SPI_Type structure.
+ * param spiHandle Pointer to the flexio_spi_slave_handle_t structure to store the transfer state.
+ */
 void FLEXIO_SPI_SlaveTransferHandleIRQ(void *spiType, void *spiHandle)
 {
     assert(spiHandle);
@@ -978,7 +1212,7 @@ void FLEXIO_SPI_SlaveTransferHandleIRQ(void *spiType, void *spiHandle)
         return;
     }
 
-    base = (FLEXIO_SPI_Type *)spiType;
+    base   = (FLEXIO_SPI_Type *)spiType;
     status = FLEXIO_SPI_GetStatusFlags(base);
 
     /* Handle tx. */
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_spi.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_spi.h
index e72f6e09cdc..575ac0bd141 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_spi.h
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_spi.h
@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
  * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #ifndef _FSL_FLEXIO_SPI_H_
@@ -61,8 +35,8 @@
 /*! @brief Error codes for the FlexIO SPI driver. */
 enum _flexio_spi_status
 {
-    kStatus_FLEXIO_SPI_Busy = MAKE_STATUS(kStatusGroup_FLEXIO_SPI, 1),  /*!< FlexIO SPI is busy. */
-    kStatus_FLEXIO_SPI_Idle = MAKE_STATUS(kStatusGroup_FLEXIO_SPI, 2),  /*!< SPI is idle */
+    kStatus_FLEXIO_SPI_Busy  = MAKE_STATUS(kStatusGroup_FLEXIO_SPI, 1), /*!< FlexIO SPI is busy. */
+    kStatus_FLEXIO_SPI_Idle  = MAKE_STATUS(kStatusGroup_FLEXIO_SPI, 2), /*!< SPI is idle */
     kStatus_FLEXIO_SPI_Error = MAKE_STATUS(kStatusGroup_FLEXIO_SPI, 3), /*!< FlexIO SPI error. */
 };
 
@@ -70,9 +44,9 @@ enum _flexio_spi_status
 typedef enum _flexio_spi_clock_phase
 {
     kFLEXIO_SPI_ClockPhaseFirstEdge = 0x0U,  /*!< First edge on SPSCK occurs at the middle of the first
-                                   *   cycle of a data transfer. */
+                                              *   cycle of a data transfer. */
     kFLEXIO_SPI_ClockPhaseSecondEdge = 0x1U, /*!< First edge on SPSCK occurs at the start of the
-                                   *   first cycle of a data transfer. */
+                                              *   first cycle of a data transfer. */
 } flexio_spi_clock_phase_t;
 
 /*! @brief FlexIO SPI data shifter direction options. */
@@ -85,7 +59,7 @@ typedef enum _flexio_spi_shift_direction
 /*! @brief FlexIO SPI data length mode options. */
 typedef enum _flexio_spi_data_bitcount_mode
 {
-    kFLEXIO_SPI_8BitMode = 0x08U,  /*!< 8-bit data transmission mode. */
+    kFLEXIO_SPI_8BitMode  = 0x08U, /*!< 8-bit data transmission mode. */
     kFLEXIO_SPI_16BitMode = 0x10U, /*!< 16-bit data transmission mode. */
 } flexio_spi_data_bitcount_mode_t;
 
@@ -93,29 +67,29 @@ typedef enum _flexio_spi_data_bitcount_mode
 enum _flexio_spi_interrupt_enable
 {
     kFLEXIO_SPI_TxEmptyInterruptEnable = 0x1U, /*!< Transmit buffer empty interrupt enable. */
-    kFLEXIO_SPI_RxFullInterruptEnable = 0x2U,  /*!< Receive buffer full interrupt enable. */
+    kFLEXIO_SPI_RxFullInterruptEnable  = 0x2U, /*!< Receive buffer full interrupt enable. */
 };
 
 /*! @brief Define FlexIO SPI status mask. */
 enum _flexio_spi_status_flags
 {
     kFLEXIO_SPI_TxBufferEmptyFlag = 0x1U, /*!< Transmit buffer empty flag. */
-    kFLEXIO_SPI_RxBufferFullFlag = 0x2U,  /*!< Receive buffer full flag. */
+    kFLEXIO_SPI_RxBufferFullFlag  = 0x2U, /*!< Receive buffer full flag. */
 };
 
 /*! @brief Define FlexIO SPI DMA mask. */
 enum _flexio_spi_dma_enable
 {
-    kFLEXIO_SPI_TxDmaEnable = 0x1U,  /*!< Tx DMA request source */
-    kFLEXIO_SPI_RxDmaEnable = 0x2U,  /*!< Rx DMA request source */
+    kFLEXIO_SPI_TxDmaEnable  = 0x1U, /*!< Tx DMA request source */
+    kFLEXIO_SPI_RxDmaEnable  = 0x2U, /*!< Rx DMA request source */
     kFLEXIO_SPI_DmaAllEnable = 0x3U, /*!< All DMA request source*/
 };
 
 /*! @brief Define FlexIO SPI transfer flags. */
 enum _flexio_spi_transfer_flags
 {
-    kFLEXIO_SPI_8bitMsb = 0x1U,  /*!< FlexIO SPI 8-bit MSB first */
-    kFLEXIO_SPI_8bitLsb = 0x2U,  /*!< FlexIO SPI 8-bit LSB first */
+    kFLEXIO_SPI_8bitMsb  = 0x1U, /*!< FlexIO SPI 8-bit MSB first */
+    kFLEXIO_SPI_8bitLsb  = 0x2U, /*!< FlexIO SPI 8-bit LSB first */
     kFLEXIO_SPI_16bitMsb = 0x9U, /*!< FlexIO SPI 16-bit MSB first */
     kFLEXIO_SPI_16bitLsb = 0xaU, /*!< FlexIO SPI 16-bit LSB first */
 };
@@ -256,7 +230,7 @@ void FLEXIO_SPI_MasterInit(FLEXIO_SPI_Type *base, flexio_spi_master_config_t *ma
  * @brief Resets the FlexIO SPI timer and shifter config.
  *
  * @param base Pointer to the FLEXIO_SPI_Type.
-*/
+ */
 void FLEXIO_SPI_MasterDeinit(FLEXIO_SPI_Type *base);
 
 /*!
@@ -310,7 +284,7 @@ void FLEXIO_SPI_SlaveInit(FLEXIO_SPI_Type *base, flexio_spi_slave_config_t *slav
  * @brief Gates the FlexIO clock.
  *
  * @param base Pointer to the FLEXIO_SPI_Type.
-*/
+ */
 void FLEXIO_SPI_SlaveDeinit(FLEXIO_SPI_Type *base);
 
 /*!
@@ -339,7 +313,7 @@ void FLEXIO_SPI_SlaveGetDefaultConfig(flexio_spi_slave_config_t *slaveConfig);
  * @return status flag; Use the status flag to AND the following flag mask and get the status.
  *          @arg kFLEXIO_SPI_TxEmptyFlag
  *          @arg kFLEXIO_SPI_RxEmptyFlag
-*/
+ */
 
 uint32_t FLEXIO_SPI_GetStatusFlags(FLEXIO_SPI_Type *base);
 
@@ -351,7 +325,7 @@ uint32_t FLEXIO_SPI_GetStatusFlags(FLEXIO_SPI_Type *base);
  *      The parameter can be any combination of the following values:
  *          @arg kFLEXIO_SPI_TxEmptyFlag
  *          @arg kFLEXIO_SPI_RxEmptyFlag
-*/
+ */
 
 void FLEXIO_SPI_ClearStatusFlags(FLEXIO_SPI_Type *base, uint32_t mask);
 
@@ -461,7 +435,7 @@ static inline uint32_t FLEXIO_SPI_GetRxDataRegisterAddress(FLEXIO_SPI_Type *base
  *
  * @param base Pointer to the FLEXIO_SPI_Type.
  * @param enable True to enable, false does not have any effect.
-*/
+ */
 static inline void FLEXIO_SPI_Enable(FLEXIO_SPI_Type *base, bool enable)
 {
     if (enable)
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_spi_edma.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_spi_edma.c
index 2c6aeda82b4..e680b533716 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_spi_edma.c
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_spi_edma.c
@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
  * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
  *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include "fsl_flexio_spi_edma.h"
@@ -95,12 +69,12 @@ static const uint16_t s_dummyData = FLEXIO_SPI_DUMMYDATA;
 static flexio_spi_master_edma_private_handle_t s_edmaPrivateHandle[FLEXIO_SPI_HANDLE_COUNT];
 
 /*******************************************************************************
-* Code
-******************************************************************************/
+ * Code
+ ******************************************************************************/
 
 static void FLEXIO_SPI_TxEDMACallback(edma_handle_t *handle, void *param, bool transferDone, uint32_t tcds)
 {
-    tcds = tcds;
+    tcds                                                      = tcds;
     flexio_spi_master_edma_private_handle_t *spiPrivateHandle = (flexio_spi_master_edma_private_handle_t *)param;
 
     /* Disable Tx DMA */
@@ -125,7 +99,7 @@ static void FLEXIO_SPI_TxEDMACallback(edma_handle_t *handle, void *param, bool t
 
 static void FLEXIO_SPI_RxEDMACallback(edma_handle_t *handle, void *param, bool transferDone, uint32_t tcds)
 {
-    tcds = tcds;
+    tcds                                                      = tcds;
     flexio_spi_master_edma_private_handle_t *spiPrivateHandle = (flexio_spi_master_edma_private_handle_t *)param;
 
     if (transferDone)
@@ -152,8 +126,8 @@ static void FLEXIO_SPI_EDMAConfig(FLEXIO_SPI_Type *base,
                                   flexio_spi_master_edma_handle_t *handle,
                                   flexio_spi_transfer_t *xfer)
 {
-    edma_transfer_config_t xferConfig;
-    flexio_spi_shift_direction_t direction;
+    edma_transfer_config_t xferConfig      = {0};
+    flexio_spi_shift_direction_t direction = kFLEXIO_SPI_MsbFirst;
     uint8_t bytesPerFrame;
 
     /* Configure the values in handle. */
@@ -161,23 +135,23 @@ static void FLEXIO_SPI_EDMAConfig(FLEXIO_SPI_Type *base,
     {
         case kFLEXIO_SPI_8bitMsb:
             bytesPerFrame = 1;
-            direction = kFLEXIO_SPI_MsbFirst;
+            direction     = kFLEXIO_SPI_MsbFirst;
             break;
         case kFLEXIO_SPI_8bitLsb:
             bytesPerFrame = 1;
-            direction = kFLEXIO_SPI_LsbFirst;
+            direction     = kFLEXIO_SPI_LsbFirst;
             break;
         case kFLEXIO_SPI_16bitMsb:
             bytesPerFrame = 2;
-            direction = kFLEXIO_SPI_MsbFirst;
+            direction     = kFLEXIO_SPI_MsbFirst;
             break;
         case kFLEXIO_SPI_16bitLsb:
             bytesPerFrame = 2;
-            direction = kFLEXIO_SPI_LsbFirst;
+            direction     = kFLEXIO_SPI_LsbFirst;
             break;
         default:
             bytesPerFrame = 1U;
-            direction = kFLEXIO_SPI_MsbFirst;
+            direction     = kFLEXIO_SPI_MsbFirst;
             assert(true);
             break;
     }
@@ -186,13 +160,13 @@ static void FLEXIO_SPI_EDMAConfig(FLEXIO_SPI_Type *base,
     handle->transferSize = xfer->dataSize;
 
     /* Configure tx transfer EDMA. */
-    xferConfig.destAddr = FLEXIO_SPI_GetTxDataRegisterAddress(base, direction);
+    xferConfig.destAddr   = FLEXIO_SPI_GetTxDataRegisterAddress(base, direction);
     xferConfig.destOffset = 0;
     if (bytesPerFrame == 1U)
     {
-        xferConfig.srcTransferSize = kEDMA_TransferSize1Bytes;
+        xferConfig.srcTransferSize  = kEDMA_TransferSize1Bytes;
         xferConfig.destTransferSize = kEDMA_TransferSize1Bytes;
-        xferConfig.minorLoopBytes = 1;
+        xferConfig.minorLoopBytes   = 1;
     }
     else
     {
@@ -200,22 +174,22 @@ static void FLEXIO_SPI_EDMAConfig(FLEXIO_SPI_Type *base,
         {
             xferConfig.destAddr -= 1U;
         }
-        xferConfig.srcTransferSize = kEDMA_TransferSize2Bytes;
+        xferConfig.srcTransferSize  = kEDMA_TransferSize2Bytes;
         xferConfig.destTransferSize = kEDMA_TransferSize2Bytes;
-        xferConfig.minorLoopBytes = 2;
+        xferConfig.minorLoopBytes   = 2;
     }
 
     /* Configure DMA channel. */
     if (xfer->txData)
     {
         xferConfig.srcOffset = bytesPerFrame;
-        xferConfig.srcAddr = (uint32_t)(xfer->txData);
+        xferConfig.srcAddr   = (uint32_t)(xfer->txData);
     }
     else
     {
         /* Disable the source increasement and source set to dummyData. */
         xferConfig.srcOffset = 0;
-        xferConfig.srcAddr = (uint32_t)(&s_dummyData);
+        xferConfig.srcAddr   = (uint32_t)(&s_dummyData);
     }
 
     xferConfig.majorLoopCounts = (xfer->dataSize / xferConfig.minorLoopBytes);
@@ -239,8 +213,8 @@ static void FLEXIO_SPI_EDMAConfig(FLEXIO_SPI_Type *base,
                 xferConfig.srcAddr -= 1U;
             }
         }
-        xferConfig.srcOffset = 0;
-        xferConfig.destAddr = (uint32_t)(xfer->rxData);
+        xferConfig.srcOffset  = 0;
+        xferConfig.destAddr   = (uint32_t)(xfer->rxData);
         xferConfig.destOffset = bytesPerFrame;
         EDMA_SubmitTransfer(handle->rxHandle, &xferConfig);
         handle->rxInProgress = true;
@@ -257,6 +231,23 @@ static void FLEXIO_SPI_EDMAConfig(FLEXIO_SPI_Type *base,
     }
 }
 
+/*!
+ * brief Initializes the FlexIO SPI master eDMA handle.
+ *
+ * This function initializes the FlexIO SPI master eDMA handle which can be used for other FlexIO SPI master
+ * transactional
+ * APIs.
+ * For a specified FlexIO SPI instance, call this API once to get the initialized handle.
+ *
+ * param base Pointer to FLEXIO_SPI_Type structure.
+ * param handle Pointer to flexio_spi_master_edma_handle_t structure to store the transfer state.
+ * param callback SPI callback, NULL means no callback.
+ * param userData callback function parameter.
+ * param txHandle User requested eDMA handle for FlexIO SPI RX eDMA transfer.
+ * param rxHandle User requested eDMA handle for FlexIO SPI TX eDMA transfer.
+ * retval kStatus_Success Successfully create the handle.
+ * retval kStatus_OutOfRange The FlexIO SPI eDMA type/handle table out of range.
+ */
 status_t FLEXIO_SPI_MasterTransferCreateHandleEDMA(FLEXIO_SPI_Type *base,
                                                    flexio_spi_master_edma_handle_t *handle,
                                                    flexio_spi_master_edma_transfer_callback_t callback,
@@ -273,7 +264,7 @@ status_t FLEXIO_SPI_MasterTransferCreateHandleEDMA(FLEXIO_SPI_Type *base,
     {
         if (s_edmaPrivateHandle[index].base == NULL)
         {
-            s_edmaPrivateHandle[index].base = base;
+            s_edmaPrivateHandle[index].base   = base;
             s_edmaPrivateHandle[index].handle = handle;
             break;
         }
@@ -309,6 +300,20 @@ status_t FLEXIO_SPI_MasterTransferCreateHandleEDMA(FLEXIO_SPI_Type *base,
     return kStatus_Success;
 }
 
+/*!
+ * brief Performs a non-blocking FlexIO SPI transfer using eDMA.
+ *
+ * note This interface returns immediately after transfer initiates. Call
+ * FLEXIO_SPI_MasterGetTransferCountEDMA to poll the transfer status and check
+ * whether the FlexIO SPI transfer is finished.
+ *
+ * param base Pointer to FLEXIO_SPI_Type structure.
+ * param handle Pointer to flexio_spi_master_edma_handle_t structure to store the transfer state.
+ * param xfer Pointer to FlexIO SPI transfer structure.
+ * retval kStatus_Success Successfully start a transfer.
+ * retval kStatus_InvalidArgument Input argument is invalid.
+ * retval kStatus_FLEXIO_SPI_Busy FlexIO SPI is not idle, is running another transfer.
+ */
 status_t FLEXIO_SPI_MasterTransferEDMA(FLEXIO_SPI_Type *base,
                                        flexio_spi_master_edma_handle_t *handle,
                                        flexio_spi_transfer_t *xfer)
@@ -356,6 +361,13 @@ status_t FLEXIO_SPI_MasterTransferEDMA(FLEXIO_SPI_Type *base,
     return kStatus_Success;
 }
 
+/*!
+ * brief Gets the remaining bytes for FlexIO SPI eDMA transfer.
+ *
+ * param base Pointer to FLEXIO_SPI_Type structure.
+ * param handle FlexIO SPI eDMA handle pointer.
+ * param count Number of bytes transferred so far by the non-blocking transaction.
+ */
 status_t FLEXIO_SPI_MasterTransferGetCountEDMA(FLEXIO_SPI_Type *base,
                                                flexio_spi_master_edma_handle_t *handle,
                                                size_t *count)
@@ -369,20 +381,26 @@ status_t FLEXIO_SPI_MasterTransferGetCountEDMA(FLEXIO_SPI_Type *base,
 
     if (handle->rxInProgress)
     {
-        *count = (handle->transferSize -
-                  (uint32_t)handle->nbytes *
-                      EDMA_GetRemainingMajorLoopCount(handle->rxHandle->base, handle->rxHandle->channel));
+        *count =
+            (handle->transferSize - (uint32_t)handle->nbytes * EDMA_GetRemainingMajorLoopCount(
+                                                                   handle->rxHandle->base, handle->rxHandle->channel));
     }
     else
     {
-        *count = (handle->transferSize -
-                  (uint32_t)handle->nbytes *
-                      EDMA_GetRemainingMajorLoopCount(handle->txHandle->base, handle->txHandle->channel));
+        *count =
+            (handle->transferSize - (uint32_t)handle->nbytes * EDMA_GetRemainingMajorLoopCount(
+                                                                   handle->txHandle->base, handle->txHandle->channel));
     }
 
     return kStatus_Success;
 }
 
+/*!
+ * brief Aborts a FlexIO SPI transfer using eDMA.
+ *
+ * param base Pointer to FLEXIO_SPI_Type structure.
+ * param handle FlexIO SPI eDMA handle pointer.
+ */
 void FLEXIO_SPI_MasterTransferAbortEDMA(FLEXIO_SPI_Type *base, flexio_spi_master_edma_handle_t *handle)
 {
     assert(handle);
@@ -399,6 +417,20 @@ void FLEXIO_SPI_MasterTransferAbortEDMA(FLEXIO_SPI_Type *base, flexio_spi_master
     handle->rxInProgress = false;
 }
 
+/*!
+ * brief Performs a non-blocking FlexIO SPI transfer using eDMA.
+ *
+ * note This interface returns immediately after transfer initiates. Call
+ * FLEXIO_SPI_SlaveGetTransferCountEDMA to poll the transfer status and
+ * check whether the FlexIO SPI transfer is finished.
+ *
+ * param base Pointer to FLEXIO_SPI_Type structure.
+ * param handle Pointer to flexio_spi_slave_edma_handle_t structure to store the transfer state.
+ * param xfer Pointer to FlexIO SPI transfer structure.
+ * retval kStatus_Success Successfully start a transfer.
+ * retval kStatus_InvalidArgument Input argument is invalid.
+ * retval kStatus_FLEXIO_SPI_Busy FlexIO SPI is not idle, is running another transfer.
+ */
 status_t FLEXIO_SPI_SlaveTransferEDMA(FLEXIO_SPI_Type *base,
                                       flexio_spi_slave_edma_handle_t *handle,
                                       flexio_spi_transfer_t *xfer)
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_spi_edma.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_spi_edma.h
index 5dba8de5a16..79c6e235236 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_spi_edma.h
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_spi_edma.h
@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
  * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
  *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 #ifndef _FSL_FLEXIO_SPI_EDMA_H_
 #define _FSL_FLEXIO_SPI_EDMA_H_
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_uart.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_uart.c
index fd7d550ad49..41d872add9b 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_uart.c
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_uart.c
@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
+ * Copyright 2016-2018 NXP
  * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include "fsl_flexio_uart.h"
@@ -43,7 +17,6 @@
 #define FSL_COMPONENT_ID "platform.drivers.flexio_uart"
 #endif
 
-
 /*<! @brief uart transfer state. */
 enum _flexio_uart_transfer_states
 {
@@ -115,16 +88,47 @@ static bool FLEXIO_UART_TransferIsRxRingBufferFull(flexio_uart_handle_t *handle)
     return full;
 }
 
+/*!
+ * brief Ungates the FlexIO clock, resets the FlexIO module, configures FlexIO UART
+ * hardware, and configures the FlexIO UART with FlexIO UART configuration.
+ * The configuration structure can be filled by the user or be set with
+ * default values by FLEXIO_UART_GetDefaultConfig().
+ *
+ * Example
+   code
+   FLEXIO_UART_Type base = {
+   .flexioBase = FLEXIO,
+   .TxPinIndex = 0,
+   .RxPinIndex = 1,
+   .shifterIndex = {0,1},
+   .timerIndex = {0,1}
+   };
+   flexio_uart_config_t config = {
+   .enableInDoze = false,
+   .enableInDebug = true,
+   .enableFastAccess = false,
+   .baudRate_Bps = 115200U,
+   .bitCountPerChar = 8
+   };
+   FLEXIO_UART_Init(base, &config, srcClock_Hz);
+   endcode
+ *
+ * param base Pointer to the FLEXIO_UART_Type structure.
+ * param userConfig Pointer to the flexio_uart_config_t structure.
+ * param srcClock_Hz FlexIO source clock in Hz.
+ * retval kStatus_Success Configuration success
+ * retval kStatus_InvalidArgument Buadrate configuration out of range
+*/
 status_t FLEXIO_UART_Init(FLEXIO_UART_Type *base, const flexio_uart_config_t *userConfig, uint32_t srcClock_Hz)
 {
     assert(base && userConfig);
 
     flexio_shifter_config_t shifterConfig;
     flexio_timer_config_t timerConfig;
-    uint32_t ctrlReg = 0;
+    uint32_t ctrlReg  = 0;
     uint16_t timerDiv = 0;
     uint16_t timerCmp = 0;
-    status_t result = kStatus_Success;
+    status_t result   = kStatus_Success;
 
     /* Clear the shifterConfig & timerConfig struct. */
     memset(&shifterConfig, 0, sizeof(shifterConfig));
@@ -149,33 +153,33 @@ status_t FLEXIO_UART_Init(FLEXIO_UART_Type *base, const flexio_uart_config_t *us
 
     /* Do hardware configuration. */
     /* 1. Configure the shifter 0 for tx. */
-    shifterConfig.timerSelect = base->timerIndex[0];
+    shifterConfig.timerSelect   = base->timerIndex[0];
     shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive;
-    shifterConfig.pinConfig = kFLEXIO_PinConfigOutput;
-    shifterConfig.pinSelect = base->TxPinIndex;
-    shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh;
-    shifterConfig.shifterMode = kFLEXIO_ShifterModeTransmit;
-    shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin;
-    shifterConfig.shifterStop = kFLEXIO_ShifterStopBitHigh;
-    shifterConfig.shifterStart = kFLEXIO_ShifterStartBitLow;
+    shifterConfig.pinConfig     = kFLEXIO_PinConfigOutput;
+    shifterConfig.pinSelect     = base->TxPinIndex;
+    shifterConfig.pinPolarity   = kFLEXIO_PinActiveHigh;
+    shifterConfig.shifterMode   = kFLEXIO_ShifterModeTransmit;
+    shifterConfig.inputSource   = kFLEXIO_ShifterInputFromPin;
+    shifterConfig.shifterStop   = kFLEXIO_ShifterStopBitHigh;
+    shifterConfig.shifterStart  = kFLEXIO_ShifterStartBitLow;
 
     FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[0], &shifterConfig);
 
     /*2. Configure the timer 0 for tx. */
-    timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->shifterIndex[0]);
+    timerConfig.triggerSelect   = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->shifterIndex[0]);
     timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow;
-    timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal;
-    timerConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled;
-    timerConfig.pinSelect = base->TxPinIndex;
-    timerConfig.pinPolarity = kFLEXIO_PinActiveHigh;
-    timerConfig.timerMode = kFLEXIO_TimerModeDual8BitBaudBit;
-    timerConfig.timerOutput = kFLEXIO_TimerOutputOneNotAffectedByReset;
-    timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput;
-    timerConfig.timerReset = kFLEXIO_TimerResetNever;
-    timerConfig.timerDisable = kFLEXIO_TimerDisableOnTimerCompare;
-    timerConfig.timerEnable = kFLEXIO_TimerEnableOnTriggerHigh;
-    timerConfig.timerStop = kFLEXIO_TimerStopBitEnableOnTimerDisable;
-    timerConfig.timerStart = kFLEXIO_TimerStartBitEnabled;
+    timerConfig.triggerSource   = kFLEXIO_TimerTriggerSourceInternal;
+    timerConfig.pinConfig       = kFLEXIO_PinConfigOutputDisabled;
+    timerConfig.pinSelect       = base->TxPinIndex;
+    timerConfig.pinPolarity     = kFLEXIO_PinActiveHigh;
+    timerConfig.timerMode       = kFLEXIO_TimerModeDual8BitBaudBit;
+    timerConfig.timerOutput     = kFLEXIO_TimerOutputOneNotAffectedByReset;
+    timerConfig.timerDecrement  = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput;
+    timerConfig.timerReset      = kFLEXIO_TimerResetNever;
+    timerConfig.timerDisable    = kFLEXIO_TimerDisableOnTimerCompare;
+    timerConfig.timerEnable     = kFLEXIO_TimerEnableOnTriggerHigh;
+    timerConfig.timerStop       = kFLEXIO_TimerStopBitEnableOnTimerDisable;
+    timerConfig.timerStart      = kFLEXIO_TimerStartBitEnabled;
 
     timerDiv = srcClock_Hz / userConfig->baudRate_Bps;
     timerDiv = timerDiv / 2 - 1;
@@ -193,33 +197,33 @@ status_t FLEXIO_UART_Init(FLEXIO_UART_Type *base, const flexio_uart_config_t *us
     FLEXIO_SetTimerConfig(base->flexioBase, base->timerIndex[0], &timerConfig);
 
     /* 3. Configure the shifter 1 for rx. */
-    shifterConfig.timerSelect = base->timerIndex[1];
+    shifterConfig.timerSelect   = base->timerIndex[1];
     shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnNegitive;
-    shifterConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled;
-    shifterConfig.pinSelect = base->RxPinIndex;
-    shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh;
-    shifterConfig.shifterMode = kFLEXIO_ShifterModeReceive;
-    shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin;
-    shifterConfig.shifterStop = kFLEXIO_ShifterStopBitHigh;
-    shifterConfig.shifterStart = kFLEXIO_ShifterStartBitLow;
+    shifterConfig.pinConfig     = kFLEXIO_PinConfigOutputDisabled;
+    shifterConfig.pinSelect     = base->RxPinIndex;
+    shifterConfig.pinPolarity   = kFLEXIO_PinActiveHigh;
+    shifterConfig.shifterMode   = kFLEXIO_ShifterModeReceive;
+    shifterConfig.inputSource   = kFLEXIO_ShifterInputFromPin;
+    shifterConfig.shifterStop   = kFLEXIO_ShifterStopBitHigh;
+    shifterConfig.shifterStart  = kFLEXIO_ShifterStartBitLow;
 
     FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[1], &shifterConfig);
 
     /* 4. Configure the timer 1 for rx. */
-    timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_PININPUT(base->RxPinIndex);
+    timerConfig.triggerSelect   = FLEXIO_TIMER_TRIGGER_SEL_PININPUT(base->RxPinIndex);
     timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveHigh;
-    timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceExternal;
-    timerConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled;
-    timerConfig.pinSelect = base->RxPinIndex;
-    timerConfig.pinPolarity = kFLEXIO_PinActiveLow;
-    timerConfig.timerMode = kFLEXIO_TimerModeDual8BitBaudBit;
-    timerConfig.timerOutput = kFLEXIO_TimerOutputOneAffectedByReset;
-    timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput;
-    timerConfig.timerReset = kFLEXIO_TimerResetOnTimerPinRisingEdge;
-    timerConfig.timerDisable = kFLEXIO_TimerDisableOnTimerCompare;
-    timerConfig.timerEnable = kFLEXIO_TimerEnableOnPinRisingEdge;
-    timerConfig.timerStop = kFLEXIO_TimerStopBitEnableOnTimerDisable;
-    timerConfig.timerStart = kFLEXIO_TimerStartBitEnabled;
+    timerConfig.triggerSource   = kFLEXIO_TimerTriggerSourceExternal;
+    timerConfig.pinConfig       = kFLEXIO_PinConfigOutputDisabled;
+    timerConfig.pinSelect       = base->RxPinIndex;
+    timerConfig.pinPolarity     = kFLEXIO_PinActiveLow;
+    timerConfig.timerMode       = kFLEXIO_TimerModeDual8BitBaudBit;
+    timerConfig.timerOutput     = kFLEXIO_TimerOutputOneAffectedByReset;
+    timerConfig.timerDecrement  = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput;
+    timerConfig.timerReset      = kFLEXIO_TimerResetOnTimerPinRisingEdge;
+    timerConfig.timerDisable    = kFLEXIO_TimerDisableOnTimerCompare;
+    timerConfig.timerEnable     = kFLEXIO_TimerEnableOnPinRisingEdge;
+    timerConfig.timerStop       = kFLEXIO_TimerStopBitEnableOnTimerDisable;
+    timerConfig.timerStart      = kFLEXIO_TimerStartBitEnabled;
 
     timerConfig.timerCompare = timerCmp;
 
@@ -228,18 +232,25 @@ status_t FLEXIO_UART_Init(FLEXIO_UART_Type *base, const flexio_uart_config_t *us
     return result;
 }
 
+/*!
+ * brief Resets the FlexIO UART shifter and timer config.
+ *
+ * note After calling this API, call the FLEXO_UART_Init to use the FlexIO UART module.
+ *
+ * param base Pointer to FLEXIO_UART_Type structure
+ */
 void FLEXIO_UART_Deinit(FLEXIO_UART_Type *base)
 {
     base->flexioBase->SHIFTCFG[base->shifterIndex[0]] = 0;
     base->flexioBase->SHIFTCTL[base->shifterIndex[0]] = 0;
     base->flexioBase->SHIFTCFG[base->shifterIndex[1]] = 0;
     base->flexioBase->SHIFTCTL[base->shifterIndex[1]] = 0;
-    base->flexioBase->TIMCFG[base->timerIndex[0]] = 0;
-    base->flexioBase->TIMCMP[base->timerIndex[0]] = 0;
-    base->flexioBase->TIMCTL[base->timerIndex[0]] = 0;
-    base->flexioBase->TIMCFG[base->timerIndex[1]] = 0;
-    base->flexioBase->TIMCMP[base->timerIndex[1]] = 0;
-    base->flexioBase->TIMCTL[base->timerIndex[1]] = 0;
+    base->flexioBase->TIMCFG[base->timerIndex[0]]     = 0;
+    base->flexioBase->TIMCMP[base->timerIndex[0]]     = 0;
+    base->flexioBase->TIMCTL[base->timerIndex[0]]     = 0;
+    base->flexioBase->TIMCFG[base->timerIndex[1]]     = 0;
+    base->flexioBase->TIMCMP[base->timerIndex[1]]     = 0;
+    base->flexioBase->TIMCTL[base->timerIndex[1]]     = 0;
     /* Clear the shifter flag. */
     base->flexioBase->SHIFTSTAT = (1U << base->shifterIndex[0]);
     base->flexioBase->SHIFTSTAT = (1U << base->shifterIndex[1]);
@@ -248,13 +259,26 @@ void FLEXIO_UART_Deinit(FLEXIO_UART_Type *base)
     base->flexioBase->TIMSTAT = (1U << base->timerIndex[1]);
 }
 
+/*!
+ * brief Gets the default configuration to configure the FlexIO UART. The configuration
+ * can be used directly for calling the FLEXIO_UART_Init().
+ * Example:
+   code
+   flexio_uart_config_t config;
+   FLEXIO_UART_GetDefaultConfig(&userConfig);
+   endcode
+ * param userConfig Pointer to the flexio_uart_config_t structure.
+*/
 void FLEXIO_UART_GetDefaultConfig(flexio_uart_config_t *userConfig)
 {
     assert(userConfig);
 
-    userConfig->enableUart = true;
-    userConfig->enableInDoze = false;
-    userConfig->enableInDebug = true;
+    /* Initializes the configure structure to zero. */
+    memset(userConfig, 0, sizeof(*userConfig));
+
+    userConfig->enableUart       = true;
+    userConfig->enableInDoze     = false;
+    userConfig->enableInDebug    = true;
     userConfig->enableFastAccess = false;
     /* Default baud rate 115200. */
     userConfig->baudRate_Bps = 115200U;
@@ -262,6 +286,14 @@ void FLEXIO_UART_GetDefaultConfig(flexio_uart_config_t *userConfig)
     userConfig->bitCountPerChar = kFLEXIO_UART_8BitsPerChar;
 }
 
+/*!
+ * brief Enables the FlexIO UART interrupt.
+ *
+ * This function enables the FlexIO UART interrupt.
+ *
+ * param base Pointer to the FLEXIO_UART_Type structure.
+ * param mask Interrupt source.
+ */
 void FLEXIO_UART_EnableInterrupts(FLEXIO_UART_Type *base, uint32_t mask)
 {
     if (mask & kFLEXIO_UART_TxDataRegEmptyInterruptEnable)
@@ -274,6 +306,14 @@ void FLEXIO_UART_EnableInterrupts(FLEXIO_UART_Type *base, uint32_t mask)
     }
 }
 
+/*!
+ * brief Disables the FlexIO UART interrupt.
+ *
+ * This function disables the FlexIO UART interrupt.
+ *
+ * param base Pointer to the FLEXIO_UART_Type structure.
+ * param mask Interrupt source.
+ */
 void FLEXIO_UART_DisableInterrupts(FLEXIO_UART_Type *base, uint32_t mask)
 {
     if (mask & kFLEXIO_UART_TxDataRegEmptyInterruptEnable)
@@ -286,6 +326,13 @@ void FLEXIO_UART_DisableInterrupts(FLEXIO_UART_Type *base, uint32_t mask)
     }
 }
 
+/*!
+ * brief Gets the FlexIO UART status flags.
+ *
+ * param base Pointer to the FLEXIO_UART_Type structure.
+ * return FlexIO UART status flags.
+ */
+
 uint32_t FLEXIO_UART_GetStatusFlags(FLEXIO_UART_Type *base)
 {
     uint32_t status = 0;
@@ -300,6 +347,17 @@ uint32_t FLEXIO_UART_GetStatusFlags(FLEXIO_UART_Type *base)
     return status;
 }
 
+/*!
+ * brief Gets the FlexIO UART status flags.
+ *
+ * param base Pointer to the FLEXIO_UART_Type structure.
+ * param mask Status flag.
+ *      The parameter can be any combination of the following values:
+ *          arg kFLEXIO_UART_TxDataRegEmptyFlag
+ *          arg kFLEXIO_UART_RxEmptyFlag
+ *          arg kFLEXIO_UART_RxOverRunFlag
+ */
+
 void FLEXIO_UART_ClearStatusFlags(FLEXIO_UART_Type *base, uint32_t mask)
 {
     if (mask & kFLEXIO_UART_TxDataRegEmptyFlag)
@@ -316,6 +374,15 @@ void FLEXIO_UART_ClearStatusFlags(FLEXIO_UART_Type *base, uint32_t mask)
     }
 }
 
+/*!
+ * brief Sends a buffer of data bytes.
+ *
+ * note This function blocks using the polling method until all bytes have been sent.
+ *
+ * param base Pointer to the FLEXIO_UART_Type structure.
+ * param txData The data bytes to send.
+ * param txSize The number of data bytes to send.
+ */
 void FLEXIO_UART_WriteBlocking(FLEXIO_UART_Type *base, const uint8_t *txData, size_t txSize)
 {
     assert(txData);
@@ -332,6 +399,15 @@ void FLEXIO_UART_WriteBlocking(FLEXIO_UART_Type *base, const uint8_t *txData, si
     }
 }
 
+/*!
+ * brief Receives a buffer of bytes.
+ *
+ * note This function blocks using the polling method until all bytes have been received.
+ *
+ * param base Pointer to the FLEXIO_UART_Type structure.
+ * param rxData The buffer to store the received bytes.
+ * param rxSize The number of data bytes to be received.
+ */
 void FLEXIO_UART_ReadBlocking(FLEXIO_UART_Type *base, uint8_t *rxData, size_t rxSize)
 {
     assert(rxData);
@@ -348,6 +424,26 @@ void FLEXIO_UART_ReadBlocking(FLEXIO_UART_Type *base, uint8_t *rxData, size_t rx
     }
 }
 
+/*!
+ * brief Initializes the UART handle.
+ *
+ * This function initializes the FlexIO UART handle, which can be used for other FlexIO
+ * UART transactional APIs. Call this API once to get the
+ * initialized handle.
+ *
+ * The UART driver supports the "background" receiving, which means that users can set up
+ * a RX ring buffer optionally. Data received is stored into the ring buffer even when
+ * the user doesn't call the FLEXIO_UART_TransferReceiveNonBlocking() API. If there is already data
+ * received in the ring buffer, users can get the received data from the ring buffer
+ * directly. The ring buffer is disabled if passing NULL as p ringBuffer.
+ *
+ * param base to FLEXIO_UART_Type structure.
+ * param handle Pointer to the flexio_uart_handle_t structure to store the transfer state.
+ * param callback The callback function.
+ * param userData The parameter of the callback function.
+ * retval kStatus_Success Successfully create the handle.
+ * retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range.
+ */
 status_t FLEXIO_UART_TransferCreateHandle(FLEXIO_UART_Type *base,
                                           flexio_uart_handle_t *handle,
                                           flexio_uart_transfer_callback_t callback,
@@ -375,6 +471,23 @@ status_t FLEXIO_UART_TransferCreateHandle(FLEXIO_UART_Type *base,
     return FLEXIO_RegisterHandleIRQ(base, handle, FLEXIO_UART_TransferHandleIRQ);
 }
 
+/*!
+ * brief Sets up the RX ring buffer.
+ *
+ * This function sets up the RX ring buffer to a specific UART handle.
+ *
+ * When the RX ring buffer is used, data received is stored into the ring buffer even when
+ * the user doesn't call the UART_ReceiveNonBlocking() API. If there is already data received
+ * in the ring buffer, users can get the received data from the ring buffer directly.
+ *
+ * note When using the RX ring buffer, one byte is reserved for internal use. In other
+ * words, if p ringBufferSize is 32, only 31 bytes are used for saving data.
+ *
+ * param base Pointer to the FLEXIO_UART_Type structure.
+ * param handle Pointer to the flexio_uart_handle_t structure to store the transfer state.
+ * param ringBuffer Start address of ring buffer for background receiving. Pass NULL to disable the ring buffer.
+ * param ringBufferSize Size of the ring buffer.
+ */
 void FLEXIO_UART_TransferStartRingBuffer(FLEXIO_UART_Type *base,
                                          flexio_uart_handle_t *handle,
                                          uint8_t *ringBuffer,
@@ -385,7 +498,7 @@ void FLEXIO_UART_TransferStartRingBuffer(FLEXIO_UART_Type *base,
     /* Setup the ringbuffer address */
     if (ringBuffer)
     {
-        handle->rxRingBuffer = ringBuffer;
+        handle->rxRingBuffer     = ringBuffer;
         handle->rxRingBufferSize = ringBufferSize;
         handle->rxRingBufferHead = 0U;
         handle->rxRingBufferTail = 0U;
@@ -395,6 +508,14 @@ void FLEXIO_UART_TransferStartRingBuffer(FLEXIO_UART_Type *base,
     }
 }
 
+/*!
+ * brief Aborts the background transfer and uninstalls the ring buffer.
+ *
+ * This function aborts the background transfer and uninstalls the ring buffer.
+ *
+ * param base Pointer to the FLEXIO_UART_Type structure.
+ * param handle Pointer to the flexio_uart_handle_t structure to store the transfer state.
+ */
 void FLEXIO_UART_TransferStopRingBuffer(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle)
 {
     assert(handle);
@@ -404,12 +525,29 @@ void FLEXIO_UART_TransferStopRingBuffer(FLEXIO_UART_Type *base, flexio_uart_hand
         FLEXIO_UART_DisableInterrupts(base, kFLEXIO_UART_RxDataRegFullInterruptEnable);
     }
 
-    handle->rxRingBuffer = NULL;
+    handle->rxRingBuffer     = NULL;
     handle->rxRingBufferSize = 0U;
     handle->rxRingBufferHead = 0U;
     handle->rxRingBufferTail = 0U;
 }
 
+/*!
+ * brief Transmits a buffer of data using the interrupt method.
+ *
+ * This function sends data using an interrupt method. This is a non-blocking function,
+ * which returns directly without waiting for all data to be written to the TX register. When
+ * all data is written to the TX register in ISR, the FlexIO UART driver calls the callback
+ * function and passes the ref kStatus_FLEXIO_UART_TxIdle as status parameter.
+ *
+ * note The kStatus_FLEXIO_UART_TxIdle is passed to the upper layer when all data is written
+ * to the TX register. However, it does not ensure that all data is sent out.
+ *
+ * param base Pointer to the FLEXIO_UART_Type structure.
+ * param handle Pointer to the flexio_uart_handle_t structure to store the transfer state.
+ * param xfer FlexIO UART transfer structure. See #flexio_uart_transfer_t.
+ * retval kStatus_Success Successfully starts the data transmission.
+ * retval kStatus_UART_TxBusy Previous transmission still not finished, data not written to the TX register.
+ */
 status_t FLEXIO_UART_TransferSendNonBlocking(FLEXIO_UART_Type *base,
                                              flexio_uart_handle_t *handle,
                                              flexio_uart_transfer_t *xfer)
@@ -429,10 +567,10 @@ status_t FLEXIO_UART_TransferSendNonBlocking(FLEXIO_UART_Type *base,
     }
     else
     {
-        handle->txData = xfer->data;
-        handle->txDataSize = xfer->dataSize;
+        handle->txData        = xfer->data;
+        handle->txDataSize    = xfer->dataSize;
         handle->txDataSizeAll = xfer->dataSize;
-        handle->txState = kFLEXIO_UART_TxBusy;
+        handle->txState       = kFLEXIO_UART_TxBusy;
 
         /* Enable transmiter interrupt. */
         FLEXIO_UART_EnableInterrupts(base, kFLEXIO_UART_TxDataRegEmptyInterruptEnable);
@@ -443,15 +581,35 @@ status_t FLEXIO_UART_TransferSendNonBlocking(FLEXIO_UART_Type *base,
     return status;
 }
 
+/*!
+ * brief Aborts the interrupt-driven data transmit.
+ *
+ * This function aborts the interrupt-driven data sending. Get the remainBytes to find out
+ * how many bytes are still not sent out.
+ *
+ * param base Pointer to the FLEXIO_UART_Type structure.
+ * param handle Pointer to the flexio_uart_handle_t structure to store the transfer state.
+ */
 void FLEXIO_UART_TransferAbortSend(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle)
 {
     /* Disable the transmitter and disable the interrupt. */
     FLEXIO_UART_DisableInterrupts(base, kFLEXIO_UART_TxDataRegEmptyInterruptEnable);
 
     handle->txDataSize = 0;
-    handle->txState = kFLEXIO_UART_TxIdle;
+    handle->txState    = kFLEXIO_UART_TxIdle;
 }
 
+/*!
+ * brief Gets the number of bytes sent.
+ *
+ * This function gets the number of bytes sent driven by interrupt.
+ *
+ * param base Pointer to the FLEXIO_UART_Type structure.
+ * param handle Pointer to the flexio_uart_handle_t structure to store the transfer state.
+ * param count Number of bytes sent so far by the non-blocking transaction.
+ * retval kStatus_NoTransferInProgress transfer has finished or no transfer in progress.
+ * retval kStatus_Success Successfully return the count.
+ */
 status_t FLEXIO_UART_TransferGetSendCount(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle, size_t *count)
 {
     assert(handle);
@@ -467,6 +625,31 @@ status_t FLEXIO_UART_TransferGetSendCount(FLEXIO_UART_Type *base, flexio_uart_ha
     return kStatus_Success;
 }
 
+/*!
+ * brief Receives a buffer of data using the interrupt method.
+ *
+ * This function receives data using the interrupt method. This is a non-blocking function,
+ * which returns without waiting for all data to be received.
+ * If the RX ring buffer is used and not empty, the data in ring buffer is copied and
+ * the parameter p receivedBytes shows how many bytes are copied from the ring buffer.
+ * After copying, if the data in ring buffer is not enough to read, the receive
+ * request is saved by the UART driver. When new data arrives, the receive request
+ * is serviced first. When all data is received, the UART driver notifies the upper layer
+ * through a callback function and passes the status parameter ref kStatus_UART_RxIdle.
+ * For example, if the upper layer needs 10 bytes but there are only 5 bytes in the ring buffer,
+ * the 5 bytes are copied to xfer->data. This function returns with the
+ * parameter p receivedBytes set to 5. For the last 5 bytes, newly arrived data is
+ * saved from the xfer->data[5]. When 5 bytes are received, the UART driver notifies upper layer.
+ * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt
+ * to receive data to xfer->data. When all data is received, the upper layer is notified.
+ *
+ * param base Pointer to the FLEXIO_UART_Type structure.
+ * param handle Pointer to the flexio_uart_handle_t structure to store the transfer state.
+ * param xfer UART transfer structure. See #flexio_uart_transfer_t.
+ * param receivedBytes Bytes received from the ring buffer directly.
+ * retval kStatus_Success Successfully queue the transfer into the transmit queue.
+ * retval kStatus_FLEXIO_UART_RxBusy Previous receive request is not finished.
+ */
 status_t FLEXIO_UART_TransferReceiveNonBlocking(FLEXIO_UART_Type *base,
                                                 flexio_uart_handle_t *handle,
                                                 flexio_uart_transfer_t *xfer,
@@ -503,7 +686,7 @@ status_t FLEXIO_UART_TransferReceiveNonBlocking(FLEXIO_UART_Type *base,
     }
     else
     {
-        bytesToReceive = xfer->dataSize;
+        bytesToReceive       = xfer->dataSize;
         bytesCurrentReceived = 0U;
 
         /* If RX ring buffer is used. */
@@ -542,22 +725,31 @@ status_t FLEXIO_UART_TransferReceiveNonBlocking(FLEXIO_UART_Type *base,
             if (bytesToReceive)
             {
                 /* No data in ring buffer, save the request to UART handle. */
-                handle->rxData = xfer->data + bytesCurrentReceived;
-                handle->rxDataSize = bytesToReceive;
+                handle->rxData        = xfer->data + bytesCurrentReceived;
+                handle->rxDataSize    = bytesToReceive;
                 handle->rxDataSizeAll = bytesToReceive;
-                handle->rxState = kFLEXIO_UART_RxBusy;
+                handle->rxState       = kFLEXIO_UART_RxBusy;
             }
 
             /* Enable FLEXIO_UART RX IRQ if previously enabled. */
             FLEXIO_UART_EnableInterrupts(base, kFLEXIO_UART_RxDataRegFullInterruptEnable);
+
+            /* Call user callback since all data are received. */
+            if (0 == bytesToReceive)
+            {
+                if (handle->callback)
+                {
+                    handle->callback(base, handle, kStatus_FLEXIO_UART_RxIdle, handle->userData);
+                }
+            }
         }
         /* Ring buffer not used. */
         else
         {
-            handle->rxData = xfer->data + bytesCurrentReceived;
-            handle->rxDataSize = bytesToReceive;
+            handle->rxData        = xfer->data + bytesCurrentReceived;
+            handle->rxDataSize    = bytesToReceive;
             handle->rxDataSizeAll = bytesToReceive;
-            handle->rxState = kFLEXIO_UART_RxBusy;
+            handle->rxState       = kFLEXIO_UART_RxBusy;
 
             /* Enable RX interrupt. */
             FLEXIO_UART_EnableInterrupts(base, kFLEXIO_UART_RxDataRegFullInterruptEnable);
@@ -575,6 +767,14 @@ status_t FLEXIO_UART_TransferReceiveNonBlocking(FLEXIO_UART_Type *base,
     return status;
 }
 
+/*!
+ * brief Aborts the receive data which was using IRQ.
+ *
+ * This function aborts the receive data which was using IRQ.
+ *
+ * param base Pointer to the FLEXIO_UART_Type structure.
+ * param handle Pointer to the flexio_uart_handle_t structure to store the transfer state.
+ */
 void FLEXIO_UART_TransferAbortReceive(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle)
 {
     /* Only abort the receive to handle->rxData, the RX ring buffer is still working. */
@@ -585,9 +785,20 @@ void FLEXIO_UART_TransferAbortReceive(FLEXIO_UART_Type *base, flexio_uart_handle
     }
 
     handle->rxDataSize = 0U;
-    handle->rxState = kFLEXIO_UART_RxIdle;
+    handle->rxState    = kFLEXIO_UART_RxIdle;
 }
 
+/*!
+ * brief Gets the number of bytes received.
+ *
+ * This function gets the number of bytes received driven by interrupt.
+ *
+ * param base Pointer to the FLEXIO_UART_Type structure.
+ * param handle Pointer to the flexio_uart_handle_t structure to store the transfer state.
+ * param count Number of bytes received so far by the non-blocking transaction.
+ * retval kStatus_NoTransferInProgress transfer has finished or no transfer in progress.
+ * retval kStatus_Success Successfully return the count.
+ */
 status_t FLEXIO_UART_TransferGetReceiveCount(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle, size_t *count)
 {
     assert(handle);
@@ -603,10 +814,18 @@ status_t FLEXIO_UART_TransferGetReceiveCount(FLEXIO_UART_Type *base, flexio_uart
     return kStatus_Success;
 }
 
+/*!
+ * brief FlexIO UART IRQ handler function.
+ *
+ * This function processes the FlexIO UART transmit and receives the IRQ request.
+ *
+ * param uartType Pointer to the FLEXIO_UART_Type structure.
+ * param uartHandle Pointer to the flexio_uart_handle_t structure to store the transfer state.
+ */
 void FLEXIO_UART_TransferHandleIRQ(void *uartType, void *uartHandle)
 {
-    uint8_t count = 1;
-    FLEXIO_UART_Type *base = (FLEXIO_UART_Type *)uartType;
+    uint8_t count                = 1;
+    FLEXIO_UART_Type *base       = (FLEXIO_UART_Type *)uartType;
     flexio_uart_handle_t *handle = (flexio_uart_handle_t *)uartHandle;
 
     /* Read the status back. */
@@ -662,7 +881,7 @@ void FLEXIO_UART_TransferHandleIRQ(void *uartType, void *uartHandle)
                     }
                 }
 
-                /* If ring buffer is still full after callback function, the oldest data is overrided. */
+                /* If ring buffer is still full after callback function, the oldest data is overridden. */
                 if (FLEXIO_UART_TransferIsRxRingBufferFull(handle))
                 {
                     /* Increase handle->rxRingBufferTail to make room for new data. */
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_uart.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_uart.h
index 356752a14ac..0634c62c697 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_uart.h
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_uart.h
@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
+ * Copyright 2016-2018 NXP
  * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #ifndef _FSL_FLEXIO_UART_H_
@@ -49,8 +23,8 @@
 
 /*! @name Driver version */
 /*@{*/
-/*! @brief FlexIO UART driver version 2.1.4. */
-#define FSL_FLEXIO_UART_DRIVER_VERSION (MAKE_VERSION(2, 1, 4))
+/*! @brief FlexIO UART driver version 2.1.5. */
+#define FSL_FLEXIO_UART_DRIVER_VERSION (MAKE_VERSION(2, 1, 5))
 /*@}*/
 
 /*! @brief Error codes for the UART driver. */
@@ -60,7 +34,7 @@ enum _flexio_uart_status
     kStatus_FLEXIO_UART_RxBusy = MAKE_STATUS(kStatusGroup_FLEXIO_UART, 1), /*!< Receiver is busy. */
     kStatus_FLEXIO_UART_TxIdle = MAKE_STATUS(kStatusGroup_FLEXIO_UART, 2), /*!< UART transmitter is idle. */
     kStatus_FLEXIO_UART_RxIdle = MAKE_STATUS(kStatusGroup_FLEXIO_UART, 3), /*!< UART receiver is idle. */
-    kStatus_FLEXIO_UART_ERROR = MAKE_STATUS(kStatusGroup_FLEXIO_UART, 4),  /*!< ERROR happens on UART. */
+    kStatus_FLEXIO_UART_ERROR  = MAKE_STATUS(kStatusGroup_FLEXIO_UART, 4), /*!< ERROR happens on UART. */
     kStatus_FLEXIO_UART_RxRingBufferOverrun =
         MAKE_STATUS(kStatusGroup_FLEXIO_UART, 5), /*!< UART RX software ring buffer overrun. */
     kStatus_FLEXIO_UART_RxHardwareOverrun = MAKE_STATUS(kStatusGroup_FLEXIO_UART, 6) /*!< UART RX receiver overrun. */
@@ -78,15 +52,15 @@ typedef enum _flexio_uart_bit_count_per_char
 enum _flexio_uart_interrupt_enable
 {
     kFLEXIO_UART_TxDataRegEmptyInterruptEnable = 0x1U, /*!< Transmit buffer empty interrupt enable. */
-    kFLEXIO_UART_RxDataRegFullInterruptEnable = 0x2U,  /*!< Receive buffer full interrupt enable. */
+    kFLEXIO_UART_RxDataRegFullInterruptEnable  = 0x2U, /*!< Receive buffer full interrupt enable. */
 };
 
 /*! @brief Define FlexIO UART status mask. */
 enum _flexio_uart_status_flags
 {
     kFLEXIO_UART_TxDataRegEmptyFlag = 0x1U, /*!< Transmit buffer empty flag. */
-    kFLEXIO_UART_RxDataRegFullFlag = 0x2U,  /*!< Receive buffer full flag. */
-    kFLEXIO_UART_RxOverRunFlag = 0x4U,      /*!< Receive buffer over run flag. */
+    kFLEXIO_UART_RxDataRegFullFlag  = 0x2U, /*!< Receive buffer full flag. */
+    kFLEXIO_UART_RxOverRunFlag      = 0x4U, /*!< Receive buffer over run flag. */
 };
 
 /*! @brief Define FlexIO UART access structure typedef. */
@@ -202,7 +176,7 @@ status_t FLEXIO_UART_Init(FLEXIO_UART_Type *base, const flexio_uart_config_t *us
  * @note After calling this API, call the FLEXO_UART_Init to use the FlexIO UART module.
  *
  * @param base Pointer to FLEXIO_UART_Type structure
-*/
+ */
 void FLEXIO_UART_Deinit(FLEXIO_UART_Type *base);
 
 /*!
@@ -229,7 +203,7 @@ void FLEXIO_UART_GetDefaultConfig(flexio_uart_config_t *userConfig);
  *
  * @param base Pointer to the FLEXIO_UART_Type structure.
  * @return FlexIO UART status flags.
-*/
+ */
 
 uint32_t FLEXIO_UART_GetStatusFlags(FLEXIO_UART_Type *base);
 
@@ -242,7 +216,7 @@ uint32_t FLEXIO_UART_GetStatusFlags(FLEXIO_UART_Type *base);
  *          @arg kFLEXIO_UART_TxDataRegEmptyFlag
  *          @arg kFLEXIO_UART_RxEmptyFlag
  *          @arg kFLEXIO_UART_RxOverRunFlag
-*/
+ */
 
 void FLEXIO_UART_ClearStatusFlags(FLEXIO_UART_Type *base, uint32_t mask);
 
@@ -344,7 +318,7 @@ static inline void FLEXIO_UART_EnableRxDMA(FLEXIO_UART_Type *base, bool enable)
  *
  * @param base Pointer to the FLEXIO_UART_Type.
  * @param enable True to enable, false does not have any effect.
-*/
+ */
 static inline void FLEXIO_UART_Enable(FLEXIO_UART_Type *base, bool enable)
 {
     if (enable)
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_uart_edma.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_uart_edma.c
index 3b008e620f8..bb8b1ee30ff 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_uart_edma.c
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_uart_edma.c
@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
  * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
  *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include "fsl_flexio_uart_edma.h"
@@ -43,7 +17,6 @@
 #define FSL_COMPONENT_ID "platform.drivers.flexio_uart_edma"
 #endif
 
-
 /*<! Structure definition for uart_edma_private_handle_t. The structure is private. */
 typedef struct _flexio_uart_edma_private_handle
 {
@@ -111,7 +84,7 @@ static void FLEXIO_UART_TransferSendEDMACallback(edma_handle_t *handle, void *pa
 
     /* Avoid the warning for unused variables. */
     handle = handle;
-    tcds = tcds;
+    tcds   = tcds;
 
     if (transferDone)
     {
@@ -136,7 +109,7 @@ static void FLEXIO_UART_TransferReceiveEDMACallback(edma_handle_t *handle,
 
     /* Avoid the warning for unused variables. */
     handle = handle;
-    tcds = tcds;
+    tcds   = tcds;
 
     if (transferDone)
     {
@@ -151,6 +124,18 @@ static void FLEXIO_UART_TransferReceiveEDMACallback(edma_handle_t *handle,
     }
 }
 
+/*!
+ * brief Initializes the UART handle which is used in transactional functions.
+ *
+ * param base Pointer to FLEXIO_UART_Type.
+ * param handle Pointer to flexio_uart_edma_handle_t structure.
+ * param callback The callback function.
+ * param userData The parameter of the callback function.
+ * param rxEdmaHandle User requested DMA handle for RX DMA transfer.
+ * param txEdmaHandle User requested DMA handle for TX DMA transfer.
+ * retval kStatus_Success Successfully create the handle.
+ * retval kStatus_OutOfRange The FlexIO SPI eDMA type/handle table out of range.
+ */
 status_t FLEXIO_UART_TransferCreateHandleEDMA(FLEXIO_UART_Type *base,
                                               flexio_uart_edma_handle_t *handle,
                                               flexio_uart_edma_transfer_callback_t callback,
@@ -167,7 +152,7 @@ status_t FLEXIO_UART_TransferCreateHandleEDMA(FLEXIO_UART_Type *base,
     {
         if (s_edmaPrivateHandle[index].base == NULL)
         {
-            s_edmaPrivateHandle[index].base = base;
+            s_edmaPrivateHandle[index].base   = base;
             s_edmaPrivateHandle[index].handle = handle;
             break;
         }
@@ -204,6 +189,18 @@ status_t FLEXIO_UART_TransferCreateHandleEDMA(FLEXIO_UART_Type *base,
     return kStatus_Success;
 }
 
+/*!
+ * brief Sends data using eDMA.
+ *
+ * This function sends data using eDMA. This is a non-blocking function, which returns
+ * right away. When all data is sent out, the send callback function is called.
+ *
+ * param base Pointer to FLEXIO_UART_Type
+ * param handle UART handle pointer.
+ * param xfer UART eDMA transfer structure, see #flexio_uart_transfer_t.
+ * retval kStatus_Success if succeed, others failed.
+ * retval kStatus_FLEXIO_UART_TxBusy Previous transfer on going.
+ */
 status_t FLEXIO_UART_TransferSendEDMA(FLEXIO_UART_Type *base,
                                       flexio_uart_edma_handle_t *handle,
                                       flexio_uart_transfer_t *xfer)
@@ -226,7 +223,7 @@ status_t FLEXIO_UART_TransferSendEDMA(FLEXIO_UART_Type *base,
     }
     else
     {
-        handle->txState = kFLEXIO_UART_TxBusy;
+        handle->txState       = kFLEXIO_UART_TxBusy;
         handle->txDataSizeAll = xfer->dataSize;
 
         /* Prepare transfer. */
@@ -250,6 +247,18 @@ status_t FLEXIO_UART_TransferSendEDMA(FLEXIO_UART_Type *base,
     return status;
 }
 
+/*!
+ * brief Receives data using eDMA.
+ *
+ * This function receives data using eDMA. This is a non-blocking function, which returns
+ * right away. When all data is received, the receive callback function is called.
+ *
+ * param base Pointer to FLEXIO_UART_Type
+ * param handle Pointer to flexio_uart_edma_handle_t structure
+ * param xfer UART eDMA transfer structure, see #flexio_uart_transfer_t.
+ * retval kStatus_Success if succeed, others failed.
+ * retval kStatus_UART_RxBusy Previous transfer on going.
+ */
 status_t FLEXIO_UART_TransferReceiveEDMA(FLEXIO_UART_Type *base,
                                          flexio_uart_edma_handle_t *handle,
                                          flexio_uart_transfer_t *xfer)
@@ -272,7 +281,7 @@ status_t FLEXIO_UART_TransferReceiveEDMA(FLEXIO_UART_Type *base,
     }
     else
     {
-        handle->rxState = kFLEXIO_UART_RxBusy;
+        handle->rxState       = kFLEXIO_UART_RxBusy;
         handle->rxDataSizeAll = xfer->dataSize;
 
         /* Prepare transfer. */
@@ -295,6 +304,14 @@ status_t FLEXIO_UART_TransferReceiveEDMA(FLEXIO_UART_Type *base,
     return status;
 }
 
+/*!
+ * brief Aborts the sent data which using eDMA.
+ *
+ * This function aborts sent data which using eDMA.
+ *
+ * param base Pointer to FLEXIO_UART_Type
+ * param handle Pointer to flexio_uart_edma_handle_t structure
+ */
 void FLEXIO_UART_TransferAbortSendEDMA(FLEXIO_UART_Type *base, flexio_uart_edma_handle_t *handle)
 {
     assert(handle->txEdmaHandle);
@@ -308,6 +325,14 @@ void FLEXIO_UART_TransferAbortSendEDMA(FLEXIO_UART_Type *base, flexio_uart_edma_
     handle->txState = kFLEXIO_UART_TxIdle;
 }
 
+/*!
+ * brief Aborts the receive data which using eDMA.
+ *
+ * This function aborts the receive data which using eDMA.
+ *
+ * param base Pointer to FLEXIO_UART_Type
+ * param handle Pointer to flexio_uart_edma_handle_t structure
+ */
 void FLEXIO_UART_TransferAbortReceiveEDMA(FLEXIO_UART_Type *base, flexio_uart_edma_handle_t *handle)
 {
     assert(handle->rxEdmaHandle);
@@ -321,6 +346,17 @@ void FLEXIO_UART_TransferAbortReceiveEDMA(FLEXIO_UART_Type *base, flexio_uart_ed
     handle->rxState = kFLEXIO_UART_RxIdle;
 }
 
+/*!
+ * brief Gets the number of bytes received.
+ *
+ * This function gets the number of bytes received.
+ *
+ * param base Pointer to FLEXIO_UART_Type
+ * param handle Pointer to flexio_uart_edma_handle_t structure
+ * param count Number of bytes received so far by the non-blocking transaction.
+ * retval kStatus_NoTransferInProgress transfer has finished or no transfer in progress.
+ * retval kStatus_Success Successfully return the count.
+ */
 status_t FLEXIO_UART_TransferGetReceiveCountEDMA(FLEXIO_UART_Type *base,
                                                  flexio_uart_edma_handle_t *handle,
                                                  size_t *count)
@@ -341,6 +377,17 @@ status_t FLEXIO_UART_TransferGetReceiveCountEDMA(FLEXIO_UART_Type *base,
     return kStatus_Success;
 }
 
+/*!
+ * brief Gets the number of bytes sent out.
+ *
+ * This function gets the number of bytes sent out.
+ *
+ * param base Pointer to FLEXIO_UART_Type
+ * param handle Pointer to flexio_uart_edma_handle_t structure
+ * param count Number of bytes sent so far by the non-blocking transaction.
+ * retval kStatus_NoTransferInProgress transfer has finished or no transfer in progress.
+ * retval kStatus_Success Successfully return the count.
+ */
 status_t FLEXIO_UART_TransferGetSendCountEDMA(FLEXIO_UART_Type *base, flexio_uart_edma_handle_t *handle, size_t *count)
 {
     assert(handle);
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_uart_edma.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_uart_edma.h
index 153525abf38..5a6b36f6eb2 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_uart_edma.h
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexio_uart_edma.h
@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
  * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
  *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 #ifndef _FSL_FLEXIO_UART_EDMA_H_
 #define _FSL_FLEXIO_UART_EDMA_H_
@@ -62,8 +36,8 @@ typedef void (*flexio_uart_edma_transfer_callback_t)(FLEXIO_UART_Type *base,
                                                      void *userData);
 
 /*!
-* @brief UART eDMA handle
-*/
+ * @brief UART eDMA handle
+ */
 struct _flexio_uart_edma_handle
 {
     flexio_uart_edma_transfer_callback_t callback; /*!< Callback function. */
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexram.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexram.c
index 45e3f62be2f..ee93440d94a 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexram.c
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexram.c
@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright 2017 NXP
  * All rights reserved.
  *
- * 
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
  *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include "fsl_flexram.h"
@@ -60,18 +34,9 @@ static uint32_t FLEXRAM_GetInstance(FLEXRAM_Type *base);
  *
  * @param tcmBankNum tcm banknumber
  * @retval register value correspond to the tcm size
-  */
+ */
 static uint8_t FLEXRAM_MapTcmSizeToRegister(uint8_t tcmBankNum);
 
-/*!
- * @brief FLEXRAM configure TCM size
- * This function  is used to set the TCM to the actual size.When access to the TCM memory boundary ,hardfault will
- * raised by core.
- * @param itcmBankNum itcm bank number to allocate
- * @param dtcmBankNum dtcm bank number to allocate
-  */
-static status_t FLEXRAM_SetTCMSize(uint8_t itcmBankNum, uint8_t dtcmBankNum);
-
 /*******************************************************************************
  * Variables
  ******************************************************************************/
@@ -104,6 +69,11 @@ static uint32_t FLEXRAM_GetInstance(FLEXRAM_Type *base)
     return instance;
 }
 
+/*!
+ * brief FLEXRAM module initialization function.
+ *
+ * param base FLEXRAM base address.
+ */
 void FLEXRAM_Init(FLEXRAM_Type *base)
 {
 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
@@ -119,6 +89,10 @@ void FLEXRAM_Init(FLEXRAM_Type *base)
     base->INT_SIG_EN = 0U;
 }
 
+/*!
+ * brief Deinitializes the FLEXRAM.
+ *
+ */
 void FLEXRAN_Deinit(FLEXRAM_Type *base)
 {
 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
@@ -130,38 +104,40 @@ void FLEXRAN_Deinit(FLEXRAM_Type *base)
 static uint8_t FLEXRAM_MapTcmSizeToRegister(uint8_t tcmBankNum)
 {
     uint8_t tcmSizeConfig = 0U;
+    uint32_t totalTcmSize = 0U;
 
-    switch (tcmBankNum * FSL_FEATURE_FLEXRAM_INTERNAL_RAM_BANK_SIZE)
+    /* if bank number is a odd value, use a new bank number which bigger than target */
+    do
     {
-        case kFLEXRAM_TCMSize32KB:
-            tcmSizeConfig = 6U;
-            break;
-
-        case kFLEXRAM_TCMSize64KB:
-            tcmSizeConfig = 7U;
-            break;
-
-        case kFLEXRAM_TCMSize128KB:
-            tcmSizeConfig = 8U;
-            break;
-
-        case kFLEXRAM_TCMSize256KB:
-            tcmSizeConfig = 9U;
-            break;
-
-        case kFLEXRAM_TCMSize512KB:
-            tcmSizeConfig = 10U;
+        if ((tcmBankNum & (tcmBankNum - 1U)) == 0U)
+        {
             break;
+        }
+    } while (++tcmBankNum < FSL_FEATURE_FLEXRAM_INTERNAL_RAM_TOTAL_BANK_NUMBERS);
 
-        default:
+    totalTcmSize = tcmBankNum * (FSL_FEATURE_FLEXRAM_INTERNAL_RAM_BANK_SIZE >> 10U);
+    /* get bit '1' position */
+    while (totalTcmSize)
+    {
+        if ((totalTcmSize & 1U) == 0U)
+        {
+            tcmSizeConfig++;
+        }
+        else
+        {
             break;
+        }
+        totalTcmSize >>= 1U;
     }
 
-    return tcmSizeConfig;
+    return tcmSizeConfig + 1U;
 }
 
-static status_t FLEXRAM_SetTCMSize(uint8_t itcmBankNum, uint8_t dtcmBankNum)
+void FLEXRAM_SetTCMSize(uint8_t itcmBankNum, uint8_t dtcmBankNum)
 {
+    assert(itcmBankNum <= FSL_FEATURE_FLEXRAM_INTERNAL_RAM_TOTAL_BANK_NUMBERS);
+    assert(dtcmBankNum <= FSL_FEATURE_FLEXRAM_INTERNAL_RAM_TOTAL_BANK_NUMBERS);
+
     /* dtcm configuration */
     if (dtcmBankNum != 0U)
     {
@@ -173,6 +149,7 @@ static status_t FLEXRAM_SetTCMSize(uint8_t itcmBankNum, uint8_t dtcmBankNum)
     {
         IOMUXC_GPR->GPR16 &= ~IOMUXC_GPR_GPR16_INIT_DTCM_EN_MASK;
     }
+
     /* itcm configuration */
     if (itcmBankNum != 0U)
     {
@@ -184,21 +161,27 @@ static status_t FLEXRAM_SetTCMSize(uint8_t itcmBankNum, uint8_t dtcmBankNum)
     {
         IOMUXC_GPR->GPR16 &= ~IOMUXC_GPR_GPR16_INIT_ITCM_EN_MASK;
     }
-
-    return kStatus_Success;
 }
 
+/*!
+ * brief FLEXRAM allocate on-chip ram for OCRAM,ITCM,DTCM
+ * This function is independent of FLEXRAM_Init, it can be called directly if ram re-allocate
+ * is needed.
+ * param config allocate configuration.
+ * retval kStatus_InvalidArgument the argument is invalid
+ * 		   kStatus_Success allocate success
+ */
 status_t FLEXRAM_AllocateRam(flexram_allocate_ram_t *config)
 {
-    uint8_t dtcmBankNum = config->dtcmBankNum;
-    uint8_t itcmBankNum = config->itcmBankNum;
+    assert(config != NULL);
+
+    uint8_t dtcmBankNum  = config->dtcmBankNum;
+    uint8_t itcmBankNum  = config->itcmBankNum;
     uint8_t ocramBankNum = config->ocramBankNum;
     uint32_t bankCfg = 0U, i = 0U;
 
     /* check the arguments */
-    if ((FSL_FEATURE_FLEXRAM_INTERNAL_RAM_TOTAL_BANK_NUMBERS < (dtcmBankNum + itcmBankNum + ocramBankNum)) ||
-        ((dtcmBankNum != 0U) && ((dtcmBankNum & (dtcmBankNum - 1u)) != 0U)) ||
-        ((itcmBankNum != 0U) && ((itcmBankNum & (itcmBankNum - 1u)) != 0U)))
+    if (FSL_FEATURE_FLEXRAM_INTERNAL_RAM_TOTAL_BANK_NUMBERS < (dtcmBankNum + itcmBankNum + ocramBankNum))
     {
         return kStatus_InvalidArgument;
     }
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexram.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexram.h
index b84e8daec97..f5e1859e9fb 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexram.h
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexram.h
@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright 2017 NXP
  * All rights reserved.
  *
- * 
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
  *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #ifndef _FSL_FLEXRAM_H_
@@ -48,37 +22,35 @@
 
 /*! @name Driver version */
 /*@{*/
-/*! @brief Driver version 2.0.2. */
-#define FSL_FLEXRAM_DRIVER_VERSION (MAKE_VERSION(2U, 0U, 2U))
+/*! @brief Driver version 2.0.4. */
+#define FSL_FLEXRAM_DRIVER_VERSION (MAKE_VERSION(2U, 0U, 4U))
 /*@}*/
 
 /*! @brief flexram write read sel */
 enum _flexram_wr_rd_sel
 {
-    kFLEXRAM_Read = 0U,  /*!< read */
+    kFLEXRAM_Read  = 0U, /*!< read */
     kFLEXRAM_Write = 1U, /*!< write */
 };
 
 /*! @brief Interrupt status flag mask */
 enum _flexram_interrupt_status
 {
-    kFLEXRAM_OCRAMAccessError = FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK,    /*!< ocram access unallocated address */
-    kFLEXRAM_DTCMAccessError = FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK,      /*!< dtcm access unallocated address */
-    kFLEXRAM_ITCMAccessError = FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK,      /*!< itcm access unallocated address */
-    kFLEXRAM_OCRAMMagicAddrMatch = FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS_MASK, /*!< ocram maigc address match */
-    kFLEXRAM_DTCMMagicAddrMatch = FLEXRAM_INT_STATUS_DTCM_MAM_STATUS_MASK,   /*!< dtcm maigc address match */
-    kFLEXRAM_ITCMMagicAddrMatch = FLEXRAM_INT_STATUS_ITCM_MAM_STATUS_MASK,   /*!< itcm maigc address match */
-
-    kFLEXRAM_InterruptStatusAll = 0x3FU, /*!< all the interrupt status mask */
+    kFLEXRAM_OCRAMAccessError = FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK, /*!< ocram access unallocated address */
+    kFLEXRAM_DTCMAccessError  = FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK,  /*!< dtcm access unallocated address */
+    kFLEXRAM_ITCMAccessError  = FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK,  /*!< itcm access unallocated address */
+
+    kFLEXRAM_InterruptStatusAll = FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK | FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK |
+                                  FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK, /*!< all the interrupt status mask */
 };
 
 /*! @brief FLEXRAM TCM access mode
-* Fast access mode expected to be finished in 1-cycle
-* Wait access mode expected to be finished in 2-cycle
-* Wait access mode is a feature of the flexram and it should be used when
-* the cpu clock too fast to finish tcm access in 1-cycle.
-* Normally, fast mode is the default mode, the efficiency of the tcm access will better.
-*/
+ * Fast access mode expected to be finished in 1-cycle
+ * Wait access mode expected to be finished in 2-cycle
+ * Wait access mode is a feature of the flexram and it should be used when
+ * the cpu clock too fast to finish tcm access in 1-cycle.
+ * Normally, fast mode is the default mode, the efficiency of the tcm access will better.
+ */
 typedef enum _flexram_tcm_access_mode
 {
     kFLEXRAM_TCMAccessFastMode = 0U, /*!< fast access mode */
@@ -89,16 +61,16 @@ typedef enum _flexram_tcm_access_mode
 enum _flexram_bank_type
 {
     kFLEXRAM_BankNotUsed = 0U, /*!< bank is not used */
-    kFLEXRAM_BankOCRAM = 1U,   /*!< bank is OCRAM */
-    kFLEXRAM_BankDTCM = 2U,    /*!< bank is DTCM */
-    kFLEXRAM_BankITCM = 3U,    /*!< bank is ITCM */
+    kFLEXRAM_BankOCRAM   = 1U, /*!< bank is OCRAM */
+    kFLEXRAM_BankDTCM    = 2U, /*!< bank is DTCM */
+    kFLEXRAM_BankITCM    = 3U, /*!< bank is ITCM */
 };
 
 /*! @brief FLEXRAM tcm support size */
 enum _flexram_tcm_size
 {
-    kFLEXRAM_TCMSize32KB = 32 * 1024U,   /*!< TCM total size 32KB */
-    kFLEXRAM_TCMSize64KB = 64 * 1024U,   /*!< TCM total size 64KB */
+    kFLEXRAM_TCMSize32KB  = 32 * 1024U,  /*!< TCM total size 32KB */
+    kFLEXRAM_TCMSize64KB  = 64 * 1024U,  /*!< TCM total size 64KB */
     kFLEXRAM_TCMSize128KB = 128 * 1024U, /*!< TCM total size 128KB */
     kFLEXRAM_TCMSize256KB = 256 * 1024U, /*!< TCM total size 256KB */
     kFLEXRAM_TCMSize512KB = 512 * 1024U, /*!< TCM total size 512KB */
@@ -108,7 +80,7 @@ enum _flexram_tcm_size
 typedef enum _flexram_bank_allocate_src
 {
     kFLEXRAM_BankAllocateThroughHardwareFuse = 0U, /*!< allocate ram through hardware fuse value */
-    kFLEXRAM_BankAllocateThroughBankCfg = 1U,      /*!< allocate ram through FLEXRAM_BANK_CFG */
+    kFLEXRAM_BankAllocateThroughBankCfg      = 1U, /*!< allocate ram through FLEXRAM_BANK_CFG */
 } flexram_bank_allocate_src_t;
 
 /*! @brief FLEXRAM allocate ocram, itcm, dtcm size */
@@ -118,6 +90,15 @@ typedef struct _flexram_allocate_ram
     const uint8_t dtcmBankNum;  /*!< dtcm bank number to allocate, the number should be power of 2 */
     const uint8_t itcmBankNum;  /*!< itcm bank number to allocate, the number should be power of 2 */
 } flexram_allocate_ram_t;
+
+/*******************************************************************************
+ * APIs
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
 /*!
  * @name Initialization and deinitialization
  * @{
@@ -262,42 +243,6 @@ static inline void FLEXRAM_EnableForceRamClockOn(FLEXRAM_Type *base, bool enable
     }
 }
 
-/*!
- * @brief FLEXRAM OCRAM magic addr configuration
- * When read/write access hit magic address, it will generate interrupt
- * @param magicAddr magic address.
- * @param rwsel read write select, 0 read access , 1 write access
- */
-static inline void FLEXRAM_SetOCRAMMagicAddr(FLEXRAM_Type *base, uint16_t magicAddr, uint32_t rwSel)
-{
-    base->OCRAM_MAGIC_ADDR =
-        FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL(rwSel) | FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR(magicAddr >> 3U);
-}
-
-/*!
- * @brief FLEXRAM DTCM magic addr configuration
- * When read/write access hit magic address, it will generate interrupt
- * @param magicAddr magic address.
- * @param rwsel read write select, 0 read access , 1 write access
- */
-static inline void FLEXRAM_SetDTCMMagicAddr(FLEXRAM_Type *base, uint16_t magicAddr, uint32_t rwSel)
-{
-    base->DTCM_MAGIC_ADDR =
-        FLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL(rwSel) | FLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR(magicAddr >> 3U);
-}
-
-/*!
- * @brief FLEXRAM ITCM magic addr configuration
- * When read/write access hit magic address, it will generate interrupt
- * @param magicAddr magic address.
- * @param rwsel read write select, 0 read access , 1 write access
- */
-static inline void FLEXRAM_SetITCMMagicAddr(FLEXRAM_Type *base, uint16_t magicAddr, uint32_t rwSel)
-{
-    base->ITCM_MAGIC_ADDR =
-        FLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL(rwSel) | FLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR(magicAddr >> 3U);
-}
-
 /*!
  * @brief FLEXRAM allocate on-chip ram for OCRAM,ITCM,DTCM
  * This function is independent of FLEXRAM_Init, it can be called directly if ram re-allocate
@@ -318,6 +263,22 @@ static inline void FLEXRAM_SetAllocateRamSrc(flexram_bank_allocate_src_t src)
     IOMUXC_GPR->GPR16 |= IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL(src);
 }
 
+/*!
+ * @brief FLEXRAM configure TCM size
+ * This function  is used to set the TCM to the target size. If a odd bank number is used,
+ * a new banknumber will be used which is bigger than target value, application can set tcm
+ * size to the biggest bank number always, then boundary access error can be captured by flexram only.
+ * When access to the TCM memory boundary ,hardfault will raised by core.
+ * @param itcmBankNum itcm bank number to allocate
+ * @param dtcmBankNum dtcm bank number to allocate
+ *
+ */
+void FLEXRAM_SetTCMSize(uint8_t itcmBankNum, uint8_t dtcmBankNum);
+
+#if defined(__cplusplus)
+}
+#endif
+
 /*! @}*/
 
 #endif
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexspi.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexspi.c
index d74ab47e233..ec1e6382002 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexspi.c
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexspi.c
@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
+ * Copyright 2016-2019 NXP
  * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
  *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include "fsl_flexspi.h"
@@ -39,14 +13,13 @@
 #define FSL_COMPONENT_ID "platform.drivers.flexspi"
 #endif
 
-
 /*******************************************************************************
- * Definitations
+ * Definitions
  ******************************************************************************/
 
 #define FREQ_1MHz (1000000UL)
 #define FLEXSPI_DLLCR_DEFAULT (0x100UL)
-#define FLEXSPI_LUT_KEY_VAL (0x5AF05AF0ul)
+#define FLEXSPI_LUT_KEY_VAL (0x5AF05AF0UL)
 
 enum
 {
@@ -54,13 +27,25 @@ enum
     kFLEXSPI_DelayCellUnitMax = 225, /* 225ps. */
 };
 
+enum
+{
+    kFLEXSPI_FlashASampleClockSlaveDelayLocked =
+        FLEXSPI_STS2_ASLVLOCK_MASK, /* Flash A sample clock slave delay line locked. */
+    kFLEXSPI_FlashASampleClockRefDelayLocked =
+        FLEXSPI_STS2_AREFLOCK_MASK, /* Flash A sample clock reference delay line locked. */
+    kFLEXSPI_FlashBSampleClockSlaveDelayLocked =
+        FLEXSPI_STS2_BSLVLOCK_MASK, /* Flash B sample clock slave delay line locked. */
+    kFLEXSPI_FlashBSampleClockRefDelayLocked =
+        FLEXSPI_STS2_BREFLOCK_MASK, /* Flash B sample clock reference delay line locked. */
+};
+
 /*! @brief Common sets of flags used by the driver. */
 enum _flexspi_flag_constants
 {
     /*! IRQ sources enabled by the non-blocking transactional API. */
-    kIrqFlags = kFLEXSPI_IpTxFifoWatermarkEmpltyFlag | kFLEXSPI_IpRxFifoWatermarkAvailableFlag |
+    kIrqFlags = kFLEXSPI_IpTxFifoWatermarkEmptyFlag | kFLEXSPI_IpRxFifoWatermarkAvailableFlag |
                 kFLEXSPI_SequenceExecutionTimeoutFlag | kFLEXSPI_IpCommandSequenceErrorFlag |
-                kFLEXSPI_IpCommandGrantTimeoutFlag | kFLEXSPI_IpCommandExcutionDoneFlag,
+                kFLEXSPI_IpCommandGrantTimeoutFlag | kFLEXSPI_IpCommandExecutionDoneFlag,
 
     /*! Errors to check for. */
     kErrorFlags = kFLEXSPI_SequenceExecutionTimeoutFlag | kFLEXSPI_IpCommandSequenceErrorFlag |
@@ -69,49 +54,43 @@ enum _flexspi_flag_constants
 
 enum _flexspi_transfer_state
 {
-    kFLEXSPI_Idle = 0x0U,      /*!< Transfer is done. */
+    kFLEXSPI_Idle      = 0x0U, /*!< Transfer is done. */
     kFLEXSPI_BusyWrite = 0x1U, /*!< FLEXSPI is busy write transfer. */
-    kFLEXSPI_BusyRead = 0x2U,  /*!< FLEXSPI is busy write transfer. */
+    kFLEXSPI_BusyRead  = 0x2U, /*!< FLEXSPI is busy write transfer. */
 };
 
 /*! @brief Typedef for interrupt handler. */
-typedef void (*flexspi_isr_t)(FLEXSPI_Type *base, void *flexspiHandle);
+typedef void (*flexspi_isr_t)(FLEXSPI_Type *base, flexspi_handle_t *handle);
 
 /*******************************************************************************
  * Prototypes
  ******************************************************************************/
 /*!
-* @brief Get the instance number for FLEXSPI.
-*
-* @param base FLEXSPI base pointer.
-*/
+ * @brief Get the instance number for FLEXSPI.
+ *
+ * @param base FLEXSPI base pointer.
+ */
 uint32_t FLEXSPI_GetInstance(FLEXSPI_Type *base);
 
 /*!
-* @brief Configure flash A/B sample clock DLL.
-*
-* @param base FLEXSPI base pointer.
-* @param config Flash configuration parameters.
-*/
-static uint32_t FLEXSPI_ConfigureDll(FLEXSPI_Type *base, flexspi_device_config_t *config);
+ * @brief Configure flash A/B sample clock DLL.
+ *
+ * @param base FLEXSPI base pointer.
+ * @param config Flash configuration parameters.
+ */
+AT_QUICKACCESS_SECTION_CODE(uint32_t FLEXSPI_ConfigureDll(FLEXSPI_Type *base, flexspi_device_config_t *config));
 
 /*!
-* @brief Check and clear IP command execution errors.
-*
-* @param base FLEXSPI base pointer.
-* @param status interrupt status.
-*/
-status_t FLEXSPI_CheckAndClearError(FLEXSPI_Type *base, uint32_t status);
+ * @brief Check and clear IP command execution errors.
+ *
+ * @param base FLEXSPI base pointer.
+ * @param status interrupt status.
+ */
+AT_QUICKACCESS_SECTION_CODE(status_t FLEXSPI_CheckAndClearError(FLEXSPI_Type *base, uint32_t status));
 
 /*******************************************************************************
  * Variables
  ******************************************************************************/
-
-#if defined(FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ) && FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ
-/*! @brief Pointers to flexspi handles for each instance. */
-static void *s_flexspiHandle[FSL_FEATURE_SOC_FLEXSPI_COUNT];
-#endif
-
 /*! @brief Pointers to flexspi bases for each instance. */
 static FLEXSPI_Type *const s_flexspiBases[] = FLEXSPI_BASE_PTRS;
 
@@ -123,6 +102,20 @@ static const IRQn_Type s_flexspiIrqs[] = FLEXSPI_IRQS;
 static const clock_ip_name_t s_flexspiClock[] = FLEXSPI_CLOCKS;
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
+#if defined(FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ) && FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ
+/*! @brief Pointers to flexspi handles for each instance. */
+static flexspi_handle_t *s_flexspiHandle[ARRAY_SIZE(s_flexspiBases)];
+#endif
+
+#if defined(FSL_FEATURE_FLEXSPI_HAS_RESET) && FSL_FEATURE_FLEXSPI_HAS_RESET
+/*! @brief Pointers to FLEXSPI resets for each instance. */
+static const reset_ip_name_t s_flexspiResets[] = FLEXSPI_RSTS;
+#endif
+
+#if defined(FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ) && FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ
+/*! @brief Pointer to flexspi IRQ handler. */
+static flexspi_isr_t s_flexspiIsr;
+#endif
 /*******************************************************************************
  * Code
  ******************************************************************************/
@@ -132,7 +125,7 @@ uint32_t FLEXSPI_GetInstance(FLEXSPI_Type *base)
     uint32_t instance;
 
     /* Find the instance index from base address mappings. */
-    for (instance = 0; instance < FSL_FEATURE_SOC_FLEXSPI_COUNT; instance++)
+    for (instance = 0; instance < ARRAY_SIZE(s_flexspiBases); instance++)
     {
         if (s_flexspiBases[instance] == base)
         {
@@ -140,27 +133,27 @@ uint32_t FLEXSPI_GetInstance(FLEXSPI_Type *base)
         }
     }
 
-    assert(instance < FSL_FEATURE_SOC_FLEXSPI_COUNT);
+    assert(instance < ARRAY_SIZE(s_flexspiBases));
 
     return instance;
 }
 
-static uint32_t FLEXSPI_ConfigureDll(FLEXSPI_Type *base, flexspi_device_config_t *config)
+uint32_t FLEXSPI_ConfigureDll(FLEXSPI_Type *base, flexspi_device_config_t *config)
 {
     bool isUnifiedConfig = true;
     uint32_t flexspiDllValue;
     uint32_t dllValue;
     uint32_t temp;
 
-    uint8_t rxSampleClock = (base->MCR0 & FLEXSPI_MCR0_RXCLKSRC_MASK) >> FLEXSPI_MCR0_RXCLKSRC_SHIFT;
+    uint32_t rxSampleClock = (base->MCR0 & FLEXSPI_MCR0_RXCLKSRC_MASK) >> FLEXSPI_MCR0_RXCLKSRC_SHIFT;
     switch (rxSampleClock)
     {
-        case kFLEXSPI_ReadSampleClkLoopbackInternally:
-        case kFLEXSPI_ReadSampleClkLoopbackFromDqsPad:
-        case kFLEXSPI_ReadSampleClkLoopbackFromSckPad:
+        case (uint32_t)kFLEXSPI_ReadSampleClkLoopbackInternally:
+        case (uint32_t)kFLEXSPI_ReadSampleClkLoopbackFromDqsPad:
+        case (uint32_t)kFLEXSPI_ReadSampleClkLoopbackFromSckPad:
             isUnifiedConfig = true;
             break;
-        case kFLEXSPI_ReadSampleClkExternalInputFromDqsPad:
+        case (uint32_t)kFLEXSPI_ReadSampleClkExternalInputFromDqsPad:
             if (config->isSck2Enabled)
             {
                 isUnifiedConfig = true;
@@ -171,6 +164,7 @@ static uint32_t FLEXSPI_ConfigureDll(FLEXSPI_Type *base, flexspi_device_config_t
             }
             break;
         default:
+            //assert(false);
             break;
     }
 
@@ -180,16 +174,16 @@ static uint32_t FLEXSPI_ConfigureDll(FLEXSPI_Type *base, flexspi_device_config_t
     }
     else
     {
-        if (config->flexspiRootClk >= 100 * FREQ_1MHz)
+        if (config->flexspiRootClk >= 100U * FREQ_1MHz)
         {
             /* DLLEN = 1, SLVDLYTARGET = 0xF, */
             flexspiDllValue = FLEXSPI_DLLCR_DLLEN(1) | FLEXSPI_DLLCR_SLVDLYTARGET(0x0F);
         }
         else
         {
-            temp = config->dataValidTime * 1000; /* Convert data valid time in ns to ps. */
-            dllValue = temp / kFLEXSPI_DelayCellUnitMin;
-            if (dllValue * kFLEXSPI_DelayCellUnitMin < temp)
+            temp     = (uint32_t)config->dataValidTime * 1000U; /* Convert data valid time in ns to ps. */
+            dllValue = temp / (uint32_t)kFLEXSPI_DelayCellUnitMin;
+            if (dllValue * (uint32_t)kFLEXSPI_DelayCellUnitMin < temp)
             {
                 dllValue++;
             }
@@ -204,25 +198,25 @@ status_t FLEXSPI_CheckAndClearError(FLEXSPI_Type *base, uint32_t status)
     status_t result = kStatus_Success;
 
     /* Check for error. */
-    status &= kErrorFlags;
-    if (status)
+    status &= (uint32_t)kErrorFlags;
+    if (0U != status)
     {
         /* Select the correct error code.. */
-        if (status & kFLEXSPI_SequenceExecutionTimeoutFlag)
+        if (0U != (status & (uint32_t)kFLEXSPI_SequenceExecutionTimeoutFlag))
         {
             result = kStatus_FLEXSPI_SequenceExecutionTimeout;
         }
-        else if (status & kFLEXSPI_IpCommandSequenceErrorFlag)
+        else if (0U != (status & (uint32_t)kFLEXSPI_IpCommandSequenceErrorFlag))
         {
             result = kStatus_FLEXSPI_IpCommandSequenceError;
         }
-        else if (status & kFLEXSPI_IpCommandGrantTimeoutFlag)
+        else if (0U != (status & (uint32_t)kFLEXSPI_IpCommandGrantTimeoutFlag))
         {
             result = kStatus_FLEXSPI_IpCommandGrantTimeout;
         }
         else
         {
-            assert(false);
+            //assert(false);
         }
 
         /* Clear the flags. */
@@ -236,17 +230,32 @@ status_t FLEXSPI_CheckAndClearError(FLEXSPI_Type *base, uint32_t status)
     return result;
 }
 
+/*!
+ * brief Initializes the FLEXSPI module and internal state.
+ *
+ * This function enables the clock for FLEXSPI and also configures the FLEXSPI with the
+ * input configure parameters. Users should call this function before any FLEXSPI operations.
+ *
+ * param base FLEXSPI peripheral base address.
+ * param config FLEXSPI configure structure.
+ */
 void FLEXSPI_Init(FLEXSPI_Type *base, const flexspi_config_t *config)
 {
     uint32_t configValue = 0;
-    uint8_t i = 0;
+    uint8_t i            = 0;
 
 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* Enable the flexspi clock */
-    CLOCK_EnableClock(s_flexspiClock[FLEXSPI_GetInstance(base)]);
-
+    //CLOCK_EnableClock(s_flexspiClock[FLEXSPI_GetInstance(base)]);
+    /* Access the register directly to avoid warnings accessing non ran functions */
+    CCM->CCGR6 |= CCM_CCGR6_CG5_MASK;
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
+#if defined(FSL_FEATURE_FLEXSPI_HAS_RESET) && FSL_FEATURE_FLEXSPI_HAS_RESET
+    /* Reset the FLEXSPI module */
+    RESET_PeripheralReset(s_flexspiResets[FLEXSPI_GetInstance(base)]);
+#endif
+
     /* Reset peripheral before configuring it. */
     base->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK;
     FLEXSPI_SoftwareReset(base);
@@ -258,8 +267,13 @@ void FLEXSPI_Init(FLEXSPI_Type *base, const flexspi_config_t *config)
                   FLEXSPI_MCR0_SCKFREERUNEN(config->enableSckFreeRunning) |
                   FLEXSPI_MCR0_HSEN(config->enableHalfSpeedAccess) |
                   FLEXSPI_MCR0_COMBINATIONEN(config->enableCombination) |
+#if !(defined(FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN) && FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN)
                   FLEXSPI_MCR0_ATDFEN(config->ahbConfig.enableAHBWriteIpTxFifo) |
-                  FLEXSPI_MCR0_ARDFEN(config->ahbConfig.enableAHBWriteIpRxFifo) | FLEXSPI_MCR0_MDIS_MASK;
+#endif
+#if !(defined(FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN) && FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN)
+                  FLEXSPI_MCR0_ARDFEN(config->ahbConfig.enableAHBWriteIpRxFifo) |
+#endif
+                  FLEXSPI_MCR0_MDIS_MASK;
     base->MCR0 = configValue;
 
     /* Configure MCR1 configurations. */
@@ -289,7 +303,7 @@ void FLEXSPI_Init(FLEXSPI_Type *base, const flexspi_config_t *config)
     base->AHBCR = configValue;
 
     /* Configure AHB rx buffers. */
-    for (i = 0; i < FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNT; i++)
+    for (i = 0; i < (uint32_t)FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNT; i++)
     {
         configValue = base->AHBRXBUFCR0[i];
 
@@ -298,57 +312,94 @@ void FLEXSPI_Init(FLEXSPI_Type *base, const flexspi_config_t *config)
         configValue |= FLEXSPI_AHBRXBUFCR0_PREFETCHEN(config->ahbConfig.buffer[i].enablePrefetch) |
                        FLEXSPI_AHBRXBUFCR0_PRIORITY(config->ahbConfig.buffer[i].priority) |
                        FLEXSPI_AHBRXBUFCR0_MSTRID(config->ahbConfig.buffer[i].masterIndex) |
-                       FLEXSPI_AHBRXBUFCR0_BUFSZ(config->ahbConfig.buffer[i].bufferSize * 8);
+                       FLEXSPI_AHBRXBUFCR0_BUFSZ((uint32_t)config->ahbConfig.buffer[i].bufferSize / 8U);
         base->AHBRXBUFCR0[i] = configValue;
     }
 
     /* Configure IP Fifo watermarks. */
     base->IPRXFCR &= ~FLEXSPI_IPRXFCR_RXWMRK_MASK;
-    base->IPRXFCR |= FLEXSPI_IPRXFCR_RXWMRK(config->rxWatermark / 8 - 1);
+    base->IPRXFCR |= FLEXSPI_IPRXFCR_RXWMRK((uint32_t)config->rxWatermark / 8U - 1U);
     base->IPTXFCR &= ~FLEXSPI_IPTXFCR_TXWMRK_MASK;
-    base->IPTXFCR |= FLEXSPI_IPTXFCR_TXWMRK(config->txWatermark / 8 - 1);
+    base->IPTXFCR |= FLEXSPI_IPTXFCR_TXWMRK((uint32_t)config->txWatermark / 8U - 1U);
+
+    /* Reset flash size on all ports */
+    for (i = 0; i < (uint32_t)kFLEXSPI_PortCount; i++)
+    {
+        base->FLSHCR0[i] = 0;
+    }
 }
 
+/*!
+ * brief Gets default settings for FLEXSPI.
+ *
+ * param config FLEXSPI configuration structure.
+ */
 void FLEXSPI_GetDefaultConfig(flexspi_config_t *config)
 {
-    config->rxSampleClock = kFLEXSPI_ReadSampleClkLoopbackInternally;
-    config->enableSckFreeRunning = false;
-    config->enableCombination = false;
-    config->enableDoze = true;
-    config->enableHalfSpeedAccess = false;
-    config->enableSckBDiffOpt = false;
+    /* Initializes the configure structure to zero. */
+    (void)flexspi_memset(config, 0, sizeof(*config));
+
+    config->rxSampleClock          = kFLEXSPI_ReadSampleClkLoopbackInternally;
+    config->enableSckFreeRunning   = false;
+    config->enableCombination      = false;
+    config->enableDoze             = true;
+    config->enableHalfSpeedAccess  = false;
+    config->enableSckBDiffOpt      = false;
     config->enableSameConfigForAll = false;
-    config->seqTimeoutCycle = 0xFFFFU;
-    config->ipGrantTimeoutCycle = 0xFFU;
-    config->txWatermark = 8;
-    config->rxWatermark = 8;
+    config->seqTimeoutCycle        = 0xFFFFU;
+    config->ipGrantTimeoutCycle    = 0xFFU;
+    config->txWatermark            = 8;
+    config->rxWatermark            = 8;
+#if !(defined(FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN) && FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN)
     config->ahbConfig.enableAHBWriteIpTxFifo = false;
+#endif
+#if !(defined(FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN) && FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN)
     config->ahbConfig.enableAHBWriteIpRxFifo = false;
+#endif
     config->ahbConfig.ahbGrantTimeoutCycle = 0xFFU;
-    config->ahbConfig.ahbBusTimeoutCycle = 0xFFFFU;
-    config->ahbConfig.resumeWaitCycle = 0x20U;
-    memset(config->ahbConfig.buffer, 0, sizeof(config->ahbConfig.buffer));
-    for (uint8_t i = 0; i < FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNT; i++)
+    config->ahbConfig.ahbBusTimeoutCycle   = 0xFFFFU;
+    config->ahbConfig.resumeWaitCycle      = 0x20U;
+    (void)flexspi_memset(config->ahbConfig.buffer, 0, sizeof(config->ahbConfig.buffer));
+    for (uint8_t i = 0; i < (uint32_t)FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNT; i++)
     {
-        config->ahbConfig.buffer[i].bufferSize = 256; /* Default buffer size 256 bytes*/
+        config->ahbConfig.buffer[i].enablePrefetch = true; /* Default enable AHB prefetch. */
+        config->ahbConfig.buffer[i].bufferSize     = 256;  /* Default buffer size 256 bytes*/
     }
     config->ahbConfig.enableClearAHBBufferOpt = false;
-    config->ahbConfig.enableReadAddressOpt = false;
-    config->ahbConfig.enableAHBPrefetch = false;
-    config->ahbConfig.enableAHBBufferable = false;
-    config->ahbConfig.enableAHBCachable = false;
+    config->ahbConfig.enableReadAddressOpt    = false;
+    config->ahbConfig.enableAHBPrefetch       = false;
+    config->ahbConfig.enableAHBBufferable     = false;
+    config->ahbConfig.enableAHBCachable       = false;
 }
 
+/*!
+ * brief Deinitializes the FLEXSPI module.
+ *
+ * Clears the FLEXSPI state and  FLEXSPI module registers.
+ * param base FLEXSPI peripheral base address.
+ */
 void FLEXSPI_Deinit(FLEXSPI_Type *base)
 {
     /* Reset peripheral. */
     FLEXSPI_SoftwareReset(base);
 }
 
+/*!
+ * brief Configures the connected device parameter.
+ *
+ * This function configures the connected device relevant parameters, such as the size, command, and so on.
+ * The flash configuration value cannot have a default value. The user needs to configure it according to the
+ * connected device.
+ *
+ * param base FLEXSPI peripheral base address.
+ * param config Flash configuration parameters.
+ * param port FLEXSPI Operation port.
+ */
 void FLEXSPI_SetFlashConfig(FLEXSPI_Type *base, flexspi_device_config_t *config, flexspi_port_t port)
 {
     uint32_t configValue = 0;
-    uint8_t index = port >> 1; /* PortA with index 0, PortB with index 1. */
+    uint32_t statusValue = 0;
+    uint8_t index        = (uint8_t)port >> 1U; /* PortA with index 0, PortB with index 1. */
 
     /* Wait for bus idle before change flash configuration. */
     while (!FLEXSPI_GetBusIdleStatus(base))
@@ -356,7 +407,6 @@ void FLEXSPI_SetFlashConfig(FLEXSPI_Type *base, flexspi_device_config_t *config,
     }
 
     /* Configure flash size. */
-    base->FLSHCR0[index] = 0;
     base->FLSHCR0[port] = config->flashSize;
 
     /* Configure flash parameters. */
@@ -369,27 +419,28 @@ void FLEXSPI_SetFlashConfig(FLEXSPI_Type *base, flexspi_device_config_t *config,
     configValue = base->FLSHCR2[port];
 
     configValue &= ~(FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK | FLEXSPI_FLSHCR2_AWRWAIT_MASK | FLEXSPI_FLSHCR2_AWRSEQNUM_MASK |
-                     FLEXSPI_FLSHCR2_AWRSEQID_MASK | FLEXSPI_FLSHCR2_ARDSEQNUM_MASK | FLEXSPI_FLSHCR2_AWRSEQID_MASK);
+                     FLEXSPI_FLSHCR2_AWRSEQID_MASK | FLEXSPI_FLSHCR2_ARDSEQNUM_MASK | FLEXSPI_FLSHCR2_ARDSEQID_MASK);
 
     configValue |=
         FLEXSPI_FLSHCR2_AWRWAITUNIT(config->AHBWriteWaitUnit) | FLEXSPI_FLSHCR2_AWRWAIT(config->AHBWriteWaitInterval);
 
     if (config->AWRSeqNumber > 0U)
     {
-        configValue |=
-            FLEXSPI_FLSHCR2_AWRSEQID(config->AWRSeqIndex) | FLEXSPI_FLSHCR2_AWRSEQNUM(config->AWRSeqNumber - 1U);
+        configValue |= FLEXSPI_FLSHCR2_AWRSEQID((uint32_t)config->AWRSeqIndex) |
+                       FLEXSPI_FLSHCR2_AWRSEQNUM((uint32_t)config->AWRSeqNumber - 1U);
     }
 
     if (config->ARDSeqNumber > 0U)
     {
-        configValue |=
-            FLEXSPI_FLSHCR2_ARDSEQID(config->ARDSeqIndex) | FLEXSPI_FLSHCR2_ARDSEQNUM(config->ARDSeqNumber - 1U);
+        configValue |= FLEXSPI_FLSHCR2_ARDSEQID((uint32_t)config->ARDSeqIndex) |
+                       FLEXSPI_FLSHCR2_ARDSEQNUM((uint32_t)config->ARDSeqNumber - 1U);
     }
 
     base->FLSHCR2[port] = configValue;
 
     /* Configure DLL. */
-    base->DLLCR[index] = FLEXSPI_ConfigureDll(base, config);
+    configValue        = FLEXSPI_ConfigureDll(base, config);
+    base->DLLCR[index] = configValue;
 
     /* Configure write mask. */
     if (config->enableWriteMask)
@@ -401,7 +452,7 @@ void FLEXSPI_SetFlashConfig(FLEXSPI_Type *base, flexspi_device_config_t *config,
         base->FLSHCR4 |= FLEXSPI_FLSHCR4_WMOPT1_MASK;
     }
 
-    if (index == 0) /*PortA*/
+    if (index == 0U) /*PortA*/
     {
         base->FLSHCR4 &= ~FLEXSPI_FLSHCR4_WMENA_MASK;
         base->FLSHCR4 |= FLEXSPI_FLSHCR4_WMENA(config->enableWriteMask);
@@ -414,11 +465,41 @@ void FLEXSPI_SetFlashConfig(FLEXSPI_Type *base, flexspi_device_config_t *config,
 
     /* Exit stop mode. */
     base->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK;
+
+    /* According to ERR011377, need to delay at least 100 NOPs to ensure the DLL is locked. */
+    statusValue =
+        (index == 0U) ?
+            ((uint32_t)kFLEXSPI_FlashASampleClockSlaveDelayLocked |
+             (uint32_t)kFLEXSPI_FlashASampleClockRefDelayLocked) :
+            ((uint32_t)kFLEXSPI_FlashBSampleClockSlaveDelayLocked | (uint32_t)kFLEXSPI_FlashBSampleClockRefDelayLocked);
+
+    if (0U != (configValue & FLEXSPI_DLLCR_DLLEN_MASK))
+    {
+        /* Wait slave delay line locked and slave reference delay line locked. */
+        while ((base->STS2 & statusValue) != statusValue)
+        {
+        }
+
+        /* Wait at least 100 NOPs*/
+        for (uint8_t delay = 100U; delay > 0U; delay--)
+        {
+            __NOP();
+        }
+    }
 }
 
+/*! brief Updates the LUT table.
+ *
+ * param base FLEXSPI peripheral base address.
+ * param index From which index start to update. It could be any index of the LUT table, which
+ * also allows user to update command content inside a command. Each command consists of up to
+ * 8 instructions and occupy 4*32-bit memory.
+ * param cmd Command sequence array.
+ * param count Number of sequences.
+ */
 void FLEXSPI_UpdateLUT(FLEXSPI_Type *base, uint32_t index, const uint32_t *cmd, uint32_t count)
 {
-    assert(index < 64U);
+    //assert(index < 64U);
 
     uint8_t i = 0;
     volatile uint32_t *lutBase;
@@ -430,87 +511,134 @@ void FLEXSPI_UpdateLUT(FLEXSPI_Type *base, uint32_t index, const uint32_t *cmd,
 
     /* Unlock LUT for update. */
     base->LUTKEY = FLEXSPI_LUT_KEY_VAL;
-    base->LUTCR = 0x02;
+    base->LUTCR  = 0x02;
 
     lutBase = &base->LUT[index];
-    for (i = index; i < count; i++)
+    for (i = 0; i < count; i++)
     {
         *lutBase++ = *cmd++;
     }
 
     /* Lock LUT. */
     base->LUTKEY = FLEXSPI_LUT_KEY_VAL;
-    base->LUTCR = 0x01;
+    base->LUTCR  = 0x01;
 }
 
+/*! brief Update read sample clock source
+ *
+ * param base FLEXSPI peripheral base address.
+ * param clockSource clockSource of type #flexspi_read_sample_clock_t
+ */
+void FLEXSPI_UpdateRxSampleClock(FLEXSPI_Type *base, flexspi_read_sample_clock_t clockSource)
+{
+    uint32_t mcr0Val;
+
+    /* Wait for bus idle before change flash configuration. */
+    while (!FLEXSPI_GetBusIdleStatus(base))
+    {
+    }
+
+    mcr0Val = base->MCR0;
+    mcr0Val &= ~FLEXSPI_MCR0_RXCLKSRC_MASK;
+    mcr0Val |= FLEXSPI_MCR0_RXCLKSRC(clockSource);
+    base->MCR0 = mcr0Val;
+
+    /* Reset peripheral. */
+    FLEXSPI_SoftwareReset(base);
+}
+
+/*!
+ * brief Sends a buffer of data bytes using blocking method.
+ * note This function blocks via polling until all bytes have been sent.
+ * param base FLEXSPI peripheral base address
+ * param buffer The data bytes to send
+ * param size The number of data bytes to send
+ * retval kStatus_Success write success without error
+ * retval kStatus_FLEXSPI_SequenceExecutionTimeout sequence execution timeout
+ * retval kStatus_FLEXSPI_IpCommandSequenceError IP command sequence error detected
+ * retval kStatus_FLEXSPI_IpCommandGrantTimeout IP command grant timeout detected
+ */
 status_t FLEXSPI_WriteBlocking(FLEXSPI_Type *base, uint32_t *buffer, size_t size)
 {
-    uint8_t txWatermark = ((base->IPTXFCR & FLEXSPI_IPTXFCR_TXWMRK_MASK) >> FLEXSPI_IPTXFCR_TXWMRK_SHIFT) + 1;
+    uint32_t txWatermark = ((base->IPTXFCR & FLEXSPI_IPTXFCR_TXWMRK_MASK) >> FLEXSPI_IPTXFCR_TXWMRK_SHIFT) + 1U;
     uint32_t status;
     status_t result = kStatus_Success;
-    uint32_t i = 0;
+    uint32_t i      = 0;
 
     /* Send data buffer */
-    while (size)
+    while (0U != size)
     {
         /* Wait until there is room in the fifo. This also checks for errors. */
-        while (!((status = base->INTR) & kFLEXSPI_IpTxFifoWatermarkEmpltyFlag))
+        while (0U == ((status = base->INTR) & (uint32_t)kFLEXSPI_IpTxFifoWatermarkEmptyFlag))
         {
         }
 
         result = FLEXSPI_CheckAndClearError(base, status);
 
-        if (result)
+        if (kStatus_Success != result)
         {
             return result;
         }
 
         /* Write watermark level data into tx fifo . */
-        if (size >= 8 * txWatermark)
+        if (size >= 8U * txWatermark)
         {
-            for (i = 0; i < 2 * txWatermark; i++)
+            for (i = 0U; i < 2U * txWatermark; i++)
             {
                 base->TFDR[i] = *buffer++;
             }
 
-            size = size - 8 * txWatermark;
+            size = size - 8U * txWatermark;
         }
         else
         {
-            for (i = 0; i < (size / 4 + 1); i++)
+            for (i = 0U; i < (size / 4U + 1U); i++)
             {
                 base->TFDR[i] = *buffer++;
             }
-            size = 0;
+            size = 0U;
         }
 
-        /* Push a watermark level datas into IP TX FIFO. */
-        base->INTR |= kFLEXSPI_IpTxFifoWatermarkEmpltyFlag;
+        /* Push a watermark level data into IP TX FIFO. */
+        base->INTR |= (uint32_t)kFLEXSPI_IpTxFifoWatermarkEmptyFlag;
     }
 
     return result;
 }
 
+/*!
+ * brief Receives a buffer of data bytes using a blocking method.
+ * note This function blocks via polling until all bytes have been sent.
+ * param base FLEXSPI peripheral base address
+ * param buffer The data bytes to send
+ * param size The number of data bytes to receive
+ * retval kStatus_Success read success without error
+ * retval kStatus_FLEXSPI_SequenceExecutionTimeout sequence execution timeout
+ * retval kStatus_FLEXSPI_IpCommandSequenceError IP command sequence error detected
+ * retval kStatus_FLEXSPI_IpCommandGrantTimeout IP command grant timeout detected
+ */
 status_t FLEXSPI_ReadBlocking(FLEXSPI_Type *base, uint32_t *buffer, size_t size)
 {
-    uint8_t rxWatermark = ((base->IPRXFCR & FLEXSPI_IPRXFCR_RXWMRK_MASK) >> FLEXSPI_IPRXFCR_RXWMRK_SHIFT) + 1;
+    uint32_t rxWatermark = ((base->IPRXFCR & FLEXSPI_IPRXFCR_RXWMRK_MASK) >> FLEXSPI_IPRXFCR_RXWMRK_SHIFT) + 1U;
     uint32_t status;
     status_t result = kStatus_Success;
-    uint32_t i = 0;
+    uint32_t i      = 0;
+    bool isReturn   = false;
 
     /* Send data buffer */
-    while (size)
+    while (0U != size)
     {
-        if (size >= 8 * rxWatermark)
+        if (size >= 8U * rxWatermark)
         {
             /* Wait until there is room in the fifo. This also checks for errors. */
-            while (!((status = base->INTR) & kFLEXSPI_IpRxFifoWatermarkAvailableFlag))
+            while (0U == ((status = base->INTR) & (uint32_t)kFLEXSPI_IpRxFifoWatermarkAvailableFlag))
             {
                 result = FLEXSPI_CheckAndClearError(base, status);
 
-                if (result)
+                if (kStatus_Success != result)
                 {
-                    return result;
+                    isReturn = true;
+                    break;
                 }
             }
         }
@@ -521,33 +649,39 @@ status_t FLEXSPI_ReadBlocking(FLEXSPI_Type *base, uint32_t *buffer, size_t size)
             {
                 result = FLEXSPI_CheckAndClearError(base, base->INTR);
 
-                if (result)
+                if (kStatus_Success != result)
                 {
-                    return result;
+                    isReturn = true;
+                    break;
                 }
             }
         }
 
+        if (isReturn)
+        {
+            break;
+        }
+
         result = FLEXSPI_CheckAndClearError(base, base->INTR);
 
-        if (result)
+        if (kStatus_Success != result)
         {
-            return result;
+            break;
         }
 
         /* Read watermark level data from rx fifo . */
-        if (size >= 8 * rxWatermark)
+        if (size >= 8U * rxWatermark)
         {
-            for (i = 0; i < 2 * rxWatermark; i++)
+            for (i = 0U; i < 2U * rxWatermark; i++)
             {
                 *buffer++ = base->RFDR[i];
             }
 
-            size = size - 8 * rxWatermark;
+            size = size - 8U * rxWatermark;
         }
         else
         {
-            for (i = 0; i < (size / 4 + 1); i++)
+            for (i = 0U; i < ((size + 3U) / 4U); i++)
             {
                 *buffer++ = base->RFDR[i];
             }
@@ -555,25 +689,34 @@ status_t FLEXSPI_ReadBlocking(FLEXSPI_Type *base, uint32_t *buffer, size_t size)
         }
 
         /* Pop out a watermark level datas from IP RX FIFO. */
-        base->INTR |= kFLEXSPI_IpRxFifoWatermarkAvailableFlag;
+        base->INTR |= (uint32_t)kFLEXSPI_IpRxFifoWatermarkAvailableFlag;
     }
 
     return result;
 }
 
+/*!
+ * brief Execute command to transfer a buffer data bytes using a blocking method.
+ * param base FLEXSPI peripheral base address
+ * param xfer pointer to the transfer structure.
+ * retval kStatus_Success command transfer success without error
+ * retval kStatus_FLEXSPI_SequenceExecutionTimeout sequence execution timeout
+ * retval kStatus_FLEXSPI_IpCommandSequenceError IP command sequence error detected
+ * retval kStatus_FLEXSPI_IpCommandGrantTimeout IP command grant timeout detected
+ */
 status_t FLEXSPI_TransferBlocking(FLEXSPI_Type *base, flexspi_transfer_t *xfer)
 {
     uint32_t configValue = 0;
-    status_t result = kStatus_Success;
+    status_t result      = kStatus_Success;
 
     /* Clear sequence pointer before sending data to external devices. */
     base->FLSHCR2[xfer->port] |= FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK;
 
-    /* Clear former pending status before start this tranfer. */
+    /* Clear former pending status before start this transfer. */
     base->INTR |= FLEXSPI_INTR_AHBCMDERR_MASK | FLEXSPI_INTR_IPCMDERR_MASK | FLEXSPI_INTR_AHBCMDGE_MASK |
                   FLEXSPI_INTR_IPCMDGE_MASK;
 
-    /* Configure base addresss. */
+    /* Configure base address. */
     base->IPCR0 = xfer->deviceAddress;
 
     /* Reset fifos. */
@@ -587,7 +730,8 @@ status_t FLEXSPI_TransferBlocking(FLEXSPI_Type *base, flexspi_transfer_t *xfer)
     }
 
     /* Configure sequence ID. */
-    configValue |= FLEXSPI_IPCR1_ISEQID(xfer->seqIndex) | FLEXSPI_IPCR1_ISEQNUM(xfer->SeqNumber - 1);
+    configValue |=
+        FLEXSPI_IPCR1_ISEQID((uint32_t)xfer->seqIndex) | FLEXSPI_IPCR1_ISEQNUM((uint32_t)xfer->SeqNumber - 1U);
     base->IPCR1 = configValue;
 
     /* Start Transfer. */
@@ -603,6 +747,7 @@ status_t FLEXSPI_TransferBlocking(FLEXSPI_Type *base, flexspi_transfer_t *xfer)
     }
     else
     {
+        /* Empty else. */
     }
 
     /* Wait for bus idle. */
@@ -618,59 +763,83 @@ status_t FLEXSPI_TransferBlocking(FLEXSPI_Type *base, flexspi_transfer_t *xfer)
     return result;
 }
 
+/*!
+ * brief Initializes the FLEXSPI handle which is used in transactional functions.
+ *
+ * param base FLEXSPI peripheral base address.
+ * param handle pointer to flexspi_handle_t structure to store the transfer state.
+ * param callback pointer to user callback function.
+ * param userData user parameter passed to the callback function.
+ */
 void FLEXSPI_TransferCreateHandle(FLEXSPI_Type *base,
                                   flexspi_handle_t *handle,
                                   flexspi_transfer_callback_t callback,
                                   void *userData)
 {
-    assert(handle);
+    assert(NULL != handle);
 
     uint32_t instance = FLEXSPI_GetInstance(base);
 
     /* Zero handle. */
-    memset(handle, 0, sizeof(*handle));
+    (void)memset(handle, 0, sizeof(*handle));
 
     /* Set callback and userData. */
     handle->completionCallback = callback;
-    handle->userData = userData;
+    handle->userData           = userData;
 
 #if defined(FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ) && FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ
     /* Save the context in global variables to support the double weak mechanism. */
     s_flexspiHandle[instance] = handle;
+    s_flexspiIsr              = FLEXSPI_TransferHandleIRQ;
 #endif
 
     /* Enable NVIC interrupt. */
-    EnableIRQ(s_flexspiIrqs[instance]);
+    (void)EnableIRQ(s_flexspiIrqs[instance]);
 }
 
+/*!
+ * brief Performs a interrupt non-blocking transfer on the FLEXSPI bus.
+ *
+ * note Calling the API returns immediately after transfer initiates. The user needs
+ * to call FLEXSPI_GetTransferCount to poll the transfer status to check whether
+ * the transfer is finished. If the return status is not kStatus_FLEXSPI_Busy, the transfer
+ * is finished. For FLEXSPI_Read, the dataSize should be multiple of rx watermark level, or
+ * FLEXSPI could not read data properly.
+ *
+ * param base FLEXSPI peripheral base address.
+ * param handle pointer to flexspi_handle_t structure which stores the transfer state.
+ * param xfer pointer to flexspi_transfer_t structure.
+ * retval kStatus_Success Successfully start the data transmission.
+ * retval kStatus_FLEXSPI_Busy Previous transmission still not finished.
+ */
 status_t FLEXSPI_TransferNonBlocking(FLEXSPI_Type *base, flexspi_handle_t *handle, flexspi_transfer_t *xfer)
 {
     uint32_t configValue = 0;
-    status_t result = kStatus_Success;
+    status_t result      = kStatus_Success;
 
-    assert(handle);
-    assert(xfer);
+    assert(NULL != handle);
+    assert(NULL != xfer);
 
     /* Check if the I2C bus is idle - if not return busy status. */
-    if (handle->state != kFLEXSPI_Idle)
+    if (handle->state != (uint32_t)kFLEXSPI_Idle)
     {
         result = kStatus_FLEXSPI_Busy;
     }
     else
     {
-        handle->data = xfer->data;
-        handle->dataSize = xfer->dataSize;
+        handle->data              = xfer->data;
+        handle->dataSize          = xfer->dataSize;
         handle->transferTotalSize = xfer->dataSize;
-        handle->state = (xfer->cmdType == kFLEXSPI_Read) ? kFLEXSPI_BusyRead : kFLEXSPI_BusyWrite;
+        handle->state = (xfer->cmdType == kFLEXSPI_Read) ? (uint32_t)kFLEXSPI_BusyRead : (uint32_t)kFLEXSPI_BusyWrite;
 
         /* Clear sequence pointer before sending data to external devices. */
         base->FLSHCR2[xfer->port] |= FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK;
 
-        /* Clear former pending status before start this tranfer. */
+        /* Clear former pending status before start this transfer. */
         base->INTR |= FLEXSPI_INTR_AHBCMDERR_MASK | FLEXSPI_INTR_IPCMDERR_MASK | FLEXSPI_INTR_AHBCMDGE_MASK |
                       FLEXSPI_INTR_IPCMDGE_MASK;
 
-        /* Configure base addresss. */
+        /* Configure base address. */
         base->IPCR0 = xfer->deviceAddress;
 
         /* Reset fifos. */
@@ -684,38 +853,49 @@ status_t FLEXSPI_TransferNonBlocking(FLEXSPI_Type *base, flexspi_handle_t *handl
         }
 
         /* Configure sequence ID. */
-        configValue |= FLEXSPI_IPCR1_ISEQID(xfer->seqIndex) | FLEXSPI_IPCR1_ISEQNUM(xfer->SeqNumber - 1);
+        configValue |=
+            FLEXSPI_IPCR1_ISEQID((uint32_t)xfer->seqIndex) | FLEXSPI_IPCR1_ISEQNUM((uint32_t)xfer->SeqNumber - 1U);
         base->IPCR1 = configValue;
 
         /* Start Transfer. */
         base->IPCMD |= FLEXSPI_IPCMD_TRG_MASK;
 
-        if (handle->state == kFLEXSPI_BusyRead)
+        if (handle->state == (uint32_t)kFLEXSPI_BusyRead)
         {
-            FLEXSPI_EnableInterrupts(base, kFLEXSPI_IpRxFifoWatermarkAvailableFlag |
-                                               kFLEXSPI_SequenceExecutionTimeoutFlag |
-                                               kFLEXSPI_IpCommandSequenceErrorFlag |
-                                               kFLEXSPI_IpCommandGrantTimeoutFlag | kFLEXSPI_IpCommandExcutionDoneFlag);
+            FLEXSPI_EnableInterrupts(base, (uint32_t)kFLEXSPI_IpRxFifoWatermarkAvailableFlag |
+                                               (uint32_t)kFLEXSPI_SequenceExecutionTimeoutFlag |
+                                               (uint32_t)kFLEXSPI_IpCommandSequenceErrorFlag |
+                                               (uint32_t)kFLEXSPI_IpCommandGrantTimeoutFlag |
+                                               (uint32_t)kFLEXSPI_IpCommandExecutionDoneFlag);
         }
         else
         {
-            FLEXSPI_EnableInterrupts(base, kFLEXSPI_IpTxFifoWatermarkEmpltyFlag |
-                                               kFLEXSPI_SequenceExecutionTimeoutFlag |
-                                               kFLEXSPI_IpCommandSequenceErrorFlag |
-                                               kFLEXSPI_IpCommandGrantTimeoutFlag | kFLEXSPI_IpCommandExcutionDoneFlag);
+            FLEXSPI_EnableInterrupts(
+                base, (uint32_t)kFLEXSPI_IpTxFifoWatermarkEmptyFlag | (uint32_t)kFLEXSPI_SequenceExecutionTimeoutFlag |
+                          (uint32_t)kFLEXSPI_IpCommandSequenceErrorFlag | (uint32_t)kFLEXSPI_IpCommandGrantTimeoutFlag |
+                          (uint32_t)kFLEXSPI_IpCommandExecutionDoneFlag);
         }
     }
 
     return result;
 }
 
+/*!
+ * brief Gets the master transfer status during a interrupt non-blocking transfer.
+ *
+ * param base FLEXSPI peripheral base address.
+ * param handle pointer to flexspi_handle_t structure which stores the transfer state.
+ * param count Number of bytes transferred so far by the non-blocking transaction.
+ * retval kStatus_InvalidArgument count is Invalid.
+ * retval kStatus_Success Successfully return the count.
+ */
 status_t FLEXSPI_TransferGetCount(FLEXSPI_Type *base, flexspi_handle_t *handle, size_t *count)
 {
-    assert(handle);
+    assert(NULL != handle);
 
     status_t result = kStatus_Success;
 
-    if (handle->state == kFLEXSPI_Idle)
+    if (handle->state == (uint32_t)kFLEXSPI_Idle)
     {
         result = kStatus_NoTransferInProgress;
     }
@@ -727,106 +907,135 @@ status_t FLEXSPI_TransferGetCount(FLEXSPI_Type *base, flexspi_handle_t *handle,
     return result;
 }
 
+/*!
+ * brief Aborts an interrupt non-blocking transfer early.
+ *
+ * note This API can be called at any time when an interrupt non-blocking transfer initiates
+ * to abort the transfer early.
+ *
+ * param base FLEXSPI peripheral base address.
+ * param handle pointer to flexspi_handle_t structure which stores the transfer state
+ */
 void FLEXSPI_TransferAbort(FLEXSPI_Type *base, flexspi_handle_t *handle)
 {
-    assert(handle);
+    assert(NULL != handle);
 
-    FLEXSPI_DisableInterrupts(base, kIrqFlags);
-    handle->state = kFLEXSPI_Idle;
+    FLEXSPI_DisableInterrupts(base, (uint32_t)kIrqFlags);
+    handle->state = (uint32_t)kFLEXSPI_Idle;
 }
 
+/*!
+ * brief Master interrupt handler.
+ *
+ * param base FLEXSPI peripheral base address.
+ * param handle pointer to flexspi_handle_t structure.
+ */
 void FLEXSPI_TransferHandleIRQ(FLEXSPI_Type *base, flexspi_handle_t *handle)
 {
-    uint8_t status;
+    uint32_t status;
     status_t result;
-    uint8_t txWatermark;
-    uint8_t rxWatermark;
+    uint32_t intEnableStatus;
+    uint32_t txWatermark;
+    uint32_t rxWatermark;
     uint8_t i = 0;
 
-    status = base->INTR;
-
-    result = FLEXSPI_CheckAndClearError(base, status);
-
-    if ((result != kStatus_Success) && (handle->completionCallback != NULL))
-    {
-        FLEXSPI_TransferAbort(base, handle);
-        if (handle->completionCallback)
-        {
-            handle->completionCallback(base, handle, result, handle->userData);
-        }
-        return;
-    }
+    status          = base->INTR;
+    intEnableStatus = base->INTEN;
 
-    if ((status & kFLEXSPI_IpRxFifoWatermarkAvailableFlag) && (handle->state == kFLEXSPI_BusyRead))
+    /* Check if interrupt is enabled and status is alerted. */
+    if ((status & intEnableStatus) != 0U)
     {
-        rxWatermark = ((base->IPRXFCR & FLEXSPI_IPRXFCR_RXWMRK_MASK) >> FLEXSPI_IPRXFCR_RXWMRK_SHIFT) + 1;
+        result = FLEXSPI_CheckAndClearError(base, status);
 
-        /* Read watermark level data from rx fifo . */
-        if (handle->dataSize >= 8 * rxWatermark)
+        if ((result != kStatus_Success) && (handle->completionCallback != NULL))
         {
-            /* Read watermark level data from rx fifo . */
-            for (i = 0; i < 2 * rxWatermark; i++)
+            FLEXSPI_TransferAbort(base, handle);
+            if (NULL != handle->completionCallback)
             {
-                *handle->data++ = base->RFDR[i];
+                handle->completionCallback(base, handle, result, handle->userData);
             }
-
-            handle->dataSize = handle->dataSize - 8 * rxWatermark;
         }
         else
         {
-            for (i = 0; i < (handle->dataSize / 4 + 1); i++)
+            if ((0U != (status & (uint32_t)kFLEXSPI_IpRxFifoWatermarkAvailableFlag)) &&
+                (handle->state == (uint32_t)kFLEXSPI_BusyRead))
             {
-                *handle->data++ = base->RFDR[i];
+                rxWatermark = ((base->IPRXFCR & FLEXSPI_IPRXFCR_RXWMRK_MASK) >> FLEXSPI_IPRXFCR_RXWMRK_SHIFT) + 1U;
+
+                /* Read watermark level data from rx fifo . */
+                if (handle->dataSize >= 8U * rxWatermark)
+                {
+                    /* Read watermark level data from rx fifo . */
+                    for (i = 0U; i < 2U * rxWatermark; i++)
+                    {
+                        *handle->data++ = base->RFDR[i];
+                    }
+
+                    handle->dataSize = handle->dataSize - 8U * rxWatermark;
+                }
+                else
+                {
+                    for (i = 0; i < (handle->dataSize + 3U) / 4U; i++)
+                    {
+                        *handle->data++ = base->RFDR[i];
+                    }
+                    handle->dataSize = 0;
+                }
+                /* Pop out a watermark level data from IP RX FIFO. */
+                base->INTR |= (uint32_t)kFLEXSPI_IpRxFifoWatermarkAvailableFlag;
             }
-            handle->dataSize = 0;
-        }
-        /* Pop out a watermark level datas from IP RX FIFO. */
-        base->INTR |= kFLEXSPI_IpRxFifoWatermarkAvailableFlag;
-    }
 
-    if (status & kFLEXSPI_IpCommandExcutionDoneFlag)
-    {
-        base->INTR |= kFLEXSPI_IpCommandExcutionDoneFlag;
+            if (0U != (status & (uint32_t)kFLEXSPI_IpCommandExecutionDoneFlag))
+            {
+                base->INTR |= (uint32_t)kFLEXSPI_IpCommandExecutionDoneFlag;
 
-        FLEXSPI_TransferAbort(base, handle);
+                FLEXSPI_TransferAbort(base, handle);
 
-        if (handle->completionCallback)
-        {
-            handle->completionCallback(base, handle, kStatus_Success, handle->userData);
-        }
-    }
+                if (NULL != handle->completionCallback)
+                {
+                    handle->completionCallback(base, handle, kStatus_Success, handle->userData);
+                }
+            }
 
-    /* TX FIFO empty interrupt, push watermark level data into tx FIFO. */
-    if ((status & kFLEXSPI_IpTxFifoWatermarkEmpltyFlag) && (handle->state == kFLEXSPI_BusyWrite))
-    {
-        if (handle->dataSize)
-        {
-            txWatermark = ((base->IPTXFCR & FLEXSPI_IPTXFCR_TXWMRK_MASK) >> FLEXSPI_IPTXFCR_TXWMRK_SHIFT) + 1;
-            /* Write watermark level data into tx fifo . */
-            if (handle->dataSize >= 8 * txWatermark)
+            /* TX FIFO empty interrupt, push watermark level data into tx FIFO. */
+            if ((0U != (status & (uint32_t)kFLEXSPI_IpTxFifoWatermarkEmptyFlag)) &&
+                (handle->state == (uint32_t)kFLEXSPI_BusyWrite))
             {
-                for (i = 0; i < 2 * txWatermark; i++)
+                if (0U != handle->dataSize)
                 {
-                    base->TFDR[i] = *handle->data++;
+                    txWatermark = ((base->IPTXFCR & FLEXSPI_IPTXFCR_TXWMRK_MASK) >> FLEXSPI_IPTXFCR_TXWMRK_SHIFT) + 1U;
+                    /* Write watermark level data into tx fifo . */
+                    if (handle->dataSize >= 8U * txWatermark)
+                    {
+                        for (i = 0; i < 2U * txWatermark; i++)
+                        {
+                            base->TFDR[i] = *handle->data++;
+                        }
+
+                        handle->dataSize = handle->dataSize - 8U * txWatermark;
+                    }
+                    else
+                    {
+                        for (i = 0; i < (handle->dataSize / 4U + 1U); i++)
+                        {
+                            base->TFDR[i] = *handle->data++;
+                        }
+                        handle->dataSize = 0;
+                    }
+
+                    /* Push a watermark level data into IP TX FIFO. */
+                    base->INTR |= (uint32_t)kFLEXSPI_IpTxFifoWatermarkEmptyFlag;
                 }
-
-                handle->dataSize = handle->dataSize - 8 * txWatermark;
             }
             else
             {
-                for (i = 0; i < (handle->dataSize / 4 + 1); i++)
-                {
-                    base->TFDR[i] = *handle->data++;
-                }
-                handle->dataSize = 0;
+                /* Empty else */
             }
-
-            /* Push a watermark level datas into IP TX FIFO. */
-            base->INTR |= kFLEXSPI_IpTxFifoWatermarkEmpltyFlag;
         }
     }
     else
     {
+        /* Empty else */
     }
 }
 
@@ -834,7 +1043,7 @@ void FLEXSPI_TransferHandleIRQ(FLEXSPI_Type *base, flexspi_handle_t *handle)
 #if defined(FLEXSPI)
 void FLEXSPI_DriverIRQHandler(void)
 {
-    FLEXSPI_TransferHandleIRQ(FLEXSPI, s_flexspiHandle[0]);
+    s_flexspiIsr(FLEXSPI, s_flexspiHandle[0]);
 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
   exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
@@ -846,7 +1055,7 @@ void FLEXSPI_DriverIRQHandler(void)
 #if defined(FLEXSPI0)
 void FLEXSPI0_DriverIRQHandler(void)
 {
-    FLEXSPI_TransferHandleIRQ(FLEXSPI0, s_flexspiHandle[0]);
+    s_flexspiIsr(FLEXSPI0, s_flexspiHandle[0]);
 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
   exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
@@ -857,7 +1066,7 @@ void FLEXSPI0_DriverIRQHandler(void)
 #if defined(FLEXSPI1)
 void FLEXSPI1_DriverIRQHandler(void)
 {
-    FLEXSPI_TransferHandleIRQ(FLEXSPI1, s_flexspiHandle[1]);
+    s_flexspiIsr(FLEXSPI1, s_flexspiHandle[1]);
 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
   exception return operation might vector to incorrect interrupt */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
@@ -865,4 +1074,44 @@ void FLEXSPI1_DriverIRQHandler(void)
 #endif
 }
 #endif
+
+#if defined(LSIO__FLEXSPI0)
+void LSIO_OCTASPI0_INT_DriverIRQHandler(void)
+{
+    s_flexspiIsr(LSIO__FLEXSPI0, s_flexspiHandle[0]);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+    __DSB();
+#endif
+}
+#endif
+#if defined(LSIO__FLEXSPI1)
+void LSIO_OCTASPI1_INT_DriverIRQHandler(void)
+{
+    s_flexspiIsr(LSIO__FLEXSPI1, s_flexspiHandle[1]);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+    __DSB();
+#endif
+}
+#endif
+
+#if defined(FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1) && FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1
+
+void FLEXSPI0_FLEXSPI1_DriverIRQHandler(void)
+{
+    /* If handle is registered, treat the transfer function is enabled. */
+    if (NULL != s_flexspiHandle[0])
+    {
+        s_flexspiIsr(FLEXSPI0, s_flexspiHandle[0]);
+    }
+    if (NULL != s_flexspiHandle[1])
+    {
+        s_flexspiIsr(FLEXSPI1, s_flexspiHandle[1]);
+    }
+}
+#endif
+
 #endif
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexspi.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexspi.h
index e2f00393b3d..eb05a4b9723 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexspi.h
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexspi.h
@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
+ * Copyright 2016-2019 NXP
  * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #ifndef __FSL_FLEXSPI_H_
@@ -50,21 +24,21 @@
 
 /*! @name Driver version */
 /*@{*/
-/*! @brief FLEXSPI driver version 2.0.2. */
-#define FSL_FLEXSPI_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
+/*! @brief FLEXSPI driver version 2.1.3. */
+#define FSL_FLEXSPI_DRIVER_VERSION (MAKE_VERSION(2, 1, 3))
 /*@}*/
 
 #define FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNT FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNTn(0)
 
-/*! @breif Formula to form FLEXSPI instructions in LUT table. */
+/*! @brief Formula to form FLEXSPI instructions in LUT table. */
 #define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1)                                                              \
     (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \
      FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
 
 /*! @brief Status structure of FLEXSPI.*/
-enum _flexspi_status
+enum
 {
-    kStatus_FLEXSPI_Busy = MAKE_STATUS(kStatusGroup_FLEXSPI, 0),                     /*!< FLEXSPI is busy */
+    kStatus_FLEXSPI_Busy                     = MAKE_STATUS(kStatusGroup_FLEXSPI, 0), /*!< FLEXSPI is busy */
     kStatus_FLEXSPI_SequenceExecutionTimeout = MAKE_STATUS(kStatusGroup_FLEXSPI, 1), /*!< Sequence execution timeout
                                                                             error occurred during FLEXSPI transfer. */
     kStatus_FLEXSPI_IpCommandSequenceError = MAKE_STATUS(kStatusGroup_FLEXSPI, 2),   /*!< IP command Sequence execution
@@ -76,33 +50,33 @@ enum _flexspi_status
 /*! @brief CMD definition of FLEXSPI, use to form LUT instruction. */
 enum _flexspi_command
 {
-    kFLEXSPI_Command_STOP = 0x00U,           /*!< Stop execution, deassert CS. */
-    kFLEXSPI_Command_SDR = 0x01U,            /*!< Transmit Command code to Flash, using SDR mode. */
-    kFLEXSPI_Command_RADDR_SDR = 0x02U,      /*!< Transmit Row Address to Flash, using SDR mode. */
-    kFLEXSPI_Command_CADDR_SDR = 0x03U,      /*!< Transmit Column Address to Flash, using SDR mode. */
-    kFLEXSPI_Command_MODE1_SDR = 0x04U,      /*!< Transmit 1-bit Mode bits to Flash, using SDR mode. */
-    kFLEXSPI_Command_MODE2_SDR = 0x05U,      /*!< Transmit 2-bit Mode bits to Flash, using SDR mode. */
-    kFLEXSPI_Command_MODE4_SDR = 0x06U,      /*!< Transmit 4-bit Mode bits to Flash, using SDR mode. */
-    kFLEXSPI_Command_MODE8_SDR = 0x07U,      /*!< Transmit 8-bit Mode bits to Flash, using SDR mode. */
-    kFLEXSPI_Command_WRITE_SDR = 0x08U,      /*!< Transmit Programming Data to Flash, using SDR mode. */
-    kFLEXSPI_Command_READ_SDR = 0x09U,       /*!< Receive Read Data from Flash, using SDR mode. */
-    kFLEXSPI_Command_LEARN_SDR = 0x0AU,      /*!< Receive Read Data or Preamble bit from Flash, SDR mode. */
-    kFLEXSPI_Command_DATSZ_SDR = 0x0BU,      /*!< Transmit Read/Program Data size (byte) to Flash, SDR mode. */
-    kFLEXSPI_Command_DUMMY_SDR = 0x0CU,      /*!< Leave data lines undriven by FlexSPI controller.*/
+    kFLEXSPI_Command_STOP           = 0x00U, /*!< Stop execution, deassert CS. */
+    kFLEXSPI_Command_SDR            = 0x01U, /*!< Transmit Command code to Flash, using SDR mode. */
+    kFLEXSPI_Command_RADDR_SDR      = 0x02U, /*!< Transmit Row Address to Flash, using SDR mode. */
+    kFLEXSPI_Command_CADDR_SDR      = 0x03U, /*!< Transmit Column Address to Flash, using SDR mode. */
+    kFLEXSPI_Command_MODE1_SDR      = 0x04U, /*!< Transmit 1-bit Mode bits to Flash, using SDR mode. */
+    kFLEXSPI_Command_MODE2_SDR      = 0x05U, /*!< Transmit 2-bit Mode bits to Flash, using SDR mode. */
+    kFLEXSPI_Command_MODE4_SDR      = 0x06U, /*!< Transmit 4-bit Mode bits to Flash, using SDR mode. */
+    kFLEXSPI_Command_MODE8_SDR      = 0x07U, /*!< Transmit 8-bit Mode bits to Flash, using SDR mode. */
+    kFLEXSPI_Command_WRITE_SDR      = 0x08U, /*!< Transmit Programming Data to Flash, using SDR mode. */
+    kFLEXSPI_Command_READ_SDR       = 0x09U, /*!< Receive Read Data from Flash, using SDR mode. */
+    kFLEXSPI_Command_LEARN_SDR      = 0x0AU, /*!< Receive Read Data or Preamble bit from Flash, SDR mode. */
+    kFLEXSPI_Command_DATSZ_SDR      = 0x0BU, /*!< Transmit Read/Program Data size (byte) to Flash, SDR mode. */
+    kFLEXSPI_Command_DUMMY_SDR      = 0x0CU, /*!< Leave data lines undriven by FlexSPI controller.*/
     kFLEXSPI_Command_DUMMY_RWDS_SDR = 0x0DU, /*!< Leave data lines undriven by FlexSPI controller,
                                                   dummy cycles decided by RWDS. */
-    kFLEXSPI_Command_DDR = 0x21U,            /*!< Transmit Command code to Flash, using DDR mode. */
-    kFLEXSPI_Command_RADDR_DDR = 0x22U,      /*!< Transmit Row Address to Flash, using DDR mode. */
-    kFLEXSPI_Command_CADDR_DDR = 0x23U,      /*!< Transmit Column Address to Flash, using DDR mode. */
-    kFLEXSPI_Command_MODE1_DDR = 0x24U,      /*!< Transmit 1-bit Mode bits to Flash, using DDR mode. */
-    kFLEXSPI_Command_MODE2_DDR = 0x25U,      /*!< Transmit 2-bit Mode bits to Flash, using DDR mode. */
-    kFLEXSPI_Command_MODE4_DDR = 0x26U,      /*!< Transmit 4-bit Mode bits to Flash, using DDR mode. */
-    kFLEXSPI_Command_MODE8_DDR = 0x27U,      /*!< Transmit 8-bit Mode bits to Flash, using DDR mode. */
-    kFLEXSPI_Command_WRITE_DDR = 0x28U,      /*!< Transmit Programming Data to Flash, using DDR mode. */
-    kFLEXSPI_Command_READ_DDR = 0x29U,       /*!< Receive Read Data from Flash, using DDR mode. */
-    kFLEXSPI_Command_LEARN_DDR = 0x2AU,      /*!< Receive Read Data or Preamble bit from Flash, DDR mode. */
-    kFLEXSPI_Command_DATSZ_DDR = 0x2BU,      /*!< Transmit Read/Program Data size (byte) to Flash, DDR mode. */
-    kFLEXSPI_Command_DUMMY_DDR = 0x2CU,      /*!< Leave data lines undriven by FlexSPI controller.*/
+    kFLEXSPI_Command_DDR            = 0x21U, /*!< Transmit Command code to Flash, using DDR mode. */
+    kFLEXSPI_Command_RADDR_DDR      = 0x22U, /*!< Transmit Row Address to Flash, using DDR mode. */
+    kFLEXSPI_Command_CADDR_DDR      = 0x23U, /*!< Transmit Column Address to Flash, using DDR mode. */
+    kFLEXSPI_Command_MODE1_DDR      = 0x24U, /*!< Transmit 1-bit Mode bits to Flash, using DDR mode. */
+    kFLEXSPI_Command_MODE2_DDR      = 0x25U, /*!< Transmit 2-bit Mode bits to Flash, using DDR mode. */
+    kFLEXSPI_Command_MODE4_DDR      = 0x26U, /*!< Transmit 4-bit Mode bits to Flash, using DDR mode. */
+    kFLEXSPI_Command_MODE8_DDR      = 0x27U, /*!< Transmit 8-bit Mode bits to Flash, using DDR mode. */
+    kFLEXSPI_Command_WRITE_DDR      = 0x28U, /*!< Transmit Programming Data to Flash, using DDR mode. */
+    kFLEXSPI_Command_READ_DDR       = 0x29U, /*!< Receive Read Data from Flash, using DDR mode. */
+    kFLEXSPI_Command_LEARN_DDR      = 0x2AU, /*!< Receive Read Data or Preamble bit from Flash, DDR mode. */
+    kFLEXSPI_Command_DATSZ_DDR      = 0x2BU, /*!< Transmit Read/Program Data size (byte) to Flash, DDR mode. */
+    kFLEXSPI_Command_DUMMY_DDR      = 0x2CU, /*!< Leave data lines undriven by FlexSPI controller.*/
     kFLEXSPI_Command_DUMMY_RWDS_DDR = 0x2DU, /*!< Leave data lines undriven by FlexSPI controller,
                                                dummy cycles decided by RWDS. */
     kFLEXSPI_Command_JUMP_ON_CS = 0x1FU,     /*!< Stop execution, deassert CS and save operand[7:0] as the
@@ -110,19 +84,23 @@ enum _flexspi_command
 };
 
 /*! @brief pad definition of FLEXSPI, use to form LUT instruction. */
-enum _flexspi_pad
+typedef enum _flexspi_pad
 {
     kFLEXSPI_1PAD = 0x00U, /*!< Transmit command/address and transmit/receive data only through DATA0/DATA1. */
     kFLEXSPI_2PAD = 0x01U, /*!< Transmit command/address and transmit/receive data only through DATA[1:0]. */
     kFLEXSPI_4PAD = 0x02U, /*!< Transmit command/address and transmit/receive data only through DATA[3:0]. */
     kFLEXSPI_8PAD = 0x03U, /*!< Transmit command/address and transmit/receive data only through DATA[7:0]. */
-};
+} flexspi_pad_t;
 
 /*! @brief FLEXSPI interrupt status flags.*/
 typedef enum _flexspi_flags
 {
     kFLEXSPI_SequenceExecutionTimeoutFlag = FLEXSPI_INTEN_SEQTIMEOUTEN_MASK, /*!< Sequence execution timeout. */
-    kFLEXSPI_AhbBusTimeoutFlag = FLEXSPI_INTEN_AHBBUSTIMEOUTEN_MASK,         /*!< AHB Bus timeout. */
+#if defined(FSL_FEATURE_FLEXSPI_HAS_INTEN_AHBBUSERROREN) && FSL_FEATURE_FLEXSPI_HAS_INTEN_AHBBUSERROREN
+    kFLEXSPI_AhbBusErrorFlag = FLEXSPI_INTEN_AHBBUSERROREN_MASK, /*!< AHB Bus error flag. */
+#else
+    kFLEXSPI_AhbBusTimeoutFlag = FLEXSPI_INTEN_AHBBUSTIMEOUTEN_MASK, /*!< AHB Bus timeout. */
+#endif
     kFLEXSPI_SckStoppedBecauseTxEmptyFlag =
         FLEXSPI_INTEN_SCKSTOPBYWREN_MASK, /*!< SCK is stopped during command
                                                sequence because Async TX FIFO empty. */
@@ -132,7 +110,7 @@ typedef enum _flexspi_flags
 #if !((defined(FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN)) && (FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN))
     kFLEXSPI_DataLearningFailedFlag = FLEXSPI_INTEN_DATALEARNFAILEN_MASK, /*!< Data learning failed. */
 #endif
-    kFLEXSPI_IpTxFifoWatermarkEmpltyFlag = FLEXSPI_INTEN_IPTXWEEN_MASK,    /*!< IP TX FIFO WaterMark empty. */
+    kFLEXSPI_IpTxFifoWatermarkEmptyFlag     = FLEXSPI_INTEN_IPTXWEEN_MASK, /*!< IP TX FIFO WaterMark empty. */
     kFLEXSPI_IpRxFifoWatermarkAvailableFlag = FLEXSPI_INTEN_IPRXWAEN_MASK, /*!< IP RX FIFO WaterMark available. */
     kFLEXSPI_AhbCommandSequenceErrorFlag =
         FLEXSPI_INTEN_AHBCMDERREN_MASK,                                  /*!< AHB triggered Command Sequences Error. */
@@ -141,7 +119,7 @@ typedef enum _flexspi_flags
         FLEXSPI_INTEN_AHBCMDGEEN_MASK, /*!< AHB triggered Command Sequences Grant Timeout. */
     kFLEXSPI_IpCommandGrantTimeoutFlag =
         FLEXSPI_INTEN_IPCMDGEEN_MASK, /*!< IP triggered Command Sequences Grant Timeout. */
-    kFLEXSPI_IpCommandExcutionDoneFlag =
+    kFLEXSPI_IpCommandExecutionDoneFlag =
         FLEXSPI_INTEN_IPCMDDONEEN_MASK,  /*!< IP triggered Command Sequences Execution finished. */
     kFLEXSPI_AllInterruptFlags = 0xFFFU, /*!< All flags. */
 } flexspi_flags_t;
@@ -153,36 +131,36 @@ typedef enum _flexspi_read_sample_clock
                                                                and loopback internally. */
     kFLEXSPI_ReadSampleClkLoopbackFromDqsPad = 0x1U,      /*!< Dummy Read strobe generated by FlexSPI Controller
                                                                and loopback from DQS pad. */
-    kFLEXSPI_ReadSampleClkLoopbackFromSckPad = 0x2U,      /*!< SCK output clock and loopback from SCK pad. */
+    kFLEXSPI_ReadSampleClkLoopbackFromSckPad      = 0x2U, /*!< SCK output clock and loopback from SCK pad. */
     kFLEXSPI_ReadSampleClkExternalInputFromDqsPad = 0x3U, /*!< Flash provided Read strobe and input from DQS pad. */
 } flexspi_read_sample_clock_t;
 
 /*! @brief FLEXSPI interval unit for flash device select.*/
 typedef enum _flexspi_cs_interval_cycle_unit
 {
-    kFLEXSPI_CsIntervalUnit1SckCycle = 0x0U,   /*!< Chip selection interval: CSINTERVAL * 1 serial clock cycle. */
+    kFLEXSPI_CsIntervalUnit1SckCycle   = 0x0U, /*!< Chip selection interval: CSINTERVAL * 1 serial clock cycle. */
     kFLEXSPI_CsIntervalUnit256SckCycle = 0x1U, /*!< Chip selection interval: CSINTERVAL * 256 serial clock cycle. */
 } flexspi_cs_interval_cycle_unit_t;
 
-/*! @brief FLEXSPI AHB wait interval unit for writting.*/
+/*! @brief FLEXSPI AHB wait interval unit for writing.*/
 typedef enum _flexspi_ahb_write_wait_unit
 {
-    kFLEXSPI_AhbWriteWaitUnit2AhbCycle = 0x0U,     /*!< AWRWAIT unit is 2 ahb clock cycle. */
-    kFLEXSPI_AhbWriteWaitUnit8AhbCycle = 0x1U,     /*!< AWRWAIT unit is 8 ahb clock cycle. */
-    kFLEXSPI_AhbWriteWaitUnit32AhbCycle = 0x2U,    /*!< AWRWAIT unit is 32 ahb clock cycle. */
-    kFLEXSPI_AhbWriteWaitUnit128AhbCycle = 0x3U,   /*!< AWRWAIT unit is 128 ahb clock cycle. */
-    kFLEXSPI_AhbWriteWaitUnit512AhbCycle = 0x4U,   /*!< AWRWAIT unit is 512 ahb clock cycle. */
-    kFLEXSPI_AhbWriteWaitUnit2048AhbCycle = 0x5U,  /*!< AWRWAIT unit is 2048 ahb clock cycle. */
-    kFLEXSPI_AhbWriteWaitUnit8192AhbCycle = 0x6U,  /*!< AWRWAIT unit is 8192 ahb clock cycle. */
+    kFLEXSPI_AhbWriteWaitUnit2AhbCycle     = 0x0U, /*!< AWRWAIT unit is 2 ahb clock cycle. */
+    kFLEXSPI_AhbWriteWaitUnit8AhbCycle     = 0x1U, /*!< AWRWAIT unit is 8 ahb clock cycle. */
+    kFLEXSPI_AhbWriteWaitUnit32AhbCycle    = 0x2U, /*!< AWRWAIT unit is 32 ahb clock cycle. */
+    kFLEXSPI_AhbWriteWaitUnit128AhbCycle   = 0x3U, /*!< AWRWAIT unit is 128 ahb clock cycle. */
+    kFLEXSPI_AhbWriteWaitUnit512AhbCycle   = 0x4U, /*!< AWRWAIT unit is 512 ahb clock cycle. */
+    kFLEXSPI_AhbWriteWaitUnit2048AhbCycle  = 0x5U, /*!< AWRWAIT unit is 2048 ahb clock cycle. */
+    kFLEXSPI_AhbWriteWaitUnit8192AhbCycle  = 0x6U, /*!< AWRWAIT unit is 8192 ahb clock cycle. */
     kFLEXSPI_AhbWriteWaitUnit32768AhbCycle = 0x7U, /*!< AWRWAIT unit is 32768 ahb clock cycle. */
 } flexspi_ahb_write_wait_unit_t;
 
 /*! @brief Error Code when IP command Error detected.*/
 typedef enum _flexspi_ip_error_code
 {
-    kFLEXSPI_IpCmdErrorNoError = 0x0U,                  /*!< No error. */
-    kFLEXSPI_IpCmdErrorJumpOnCsInIpCmd = 0x2U,          /*!< IP command with JMP_ON_CS instruction used. */
-    kFLEXSPI_IpCmdErrorUnknownOpCode = 0x3U,            /*!< Unknown instruction opcode in the sequence. */
+    kFLEXSPI_IpCmdErrorNoError               = 0x0U,    /*!< No error. */
+    kFLEXSPI_IpCmdErrorJumpOnCsInIpCmd       = 0x2U,    /*!< IP command with JMP_ON_CS instruction used. */
+    kFLEXSPI_IpCmdErrorUnknownOpCode         = 0x3U,    /*!< Unknown instruction opcode in the sequence. */
     kFLEXSPI_IpCmdErrorSdrDummyInDdrSequence = 0x4U,    /*!< Instruction DUMMY_SDR/DUMMY_RWDS_SDR
                                                              used in DDR sequence. */
     kFLEXSPI_IpCmdErrorDdrDummyInSdrSequence = 0x5U,    /*!< Instruction DUMMY_DDR/DUMMY_RWDS_DDR
@@ -190,16 +168,16 @@ typedef enum _flexspi_ip_error_code
     kFLEXSPI_IpCmdErrorInvalidAddress = 0x6U,           /*!< Flash access start address exceed the whole
                                                             flash address range (A1/A2/B1/B2). */
     kFLEXSPI_IpCmdErrorSequenceExecutionTimeout = 0xEU, /*!< Sequence execution timeout. */
-    kFLEXSPI_IpCmdErrorFlashBoundaryAcrosss = 0xFU,     /*!< Flash boundary crossed. */
+    kFLEXSPI_IpCmdErrorFlashBoundaryAcrosss     = 0xFU, /*!< Flash boundary crossed. */
 } flexspi_ip_error_code_t;
 
 /*! @brief Error Code when AHB command Error detected.*/
 typedef enum _flexspi_ahb_error_code
 {
-    kFLEXSPI_AhbCmdErrorNoError = 0x0U,               /*!< No error. */
+    kFLEXSPI_AhbCmdErrorNoError            = 0x0U,    /*!< No error. */
     kFLEXSPI_AhbCmdErrorJumpOnCsInWriteCmd = 0x2U,    /*!< AHB Write command with JMP_ON_CS instruction
                                                            used in the sequence. */
-    kFLEXSPI_AhbCmdErrorUnknownOpCode = 0x3U,         /*!< Unknown instruction opcode in the sequence. */
+    kFLEXSPI_AhbCmdErrorUnknownOpCode         = 0x3U, /*!< Unknown instruction opcode in the sequence. */
     kFLEXSPI_AhbCmdErrorSdrDummyInDdrSequence = 0x4U, /*!< Instruction DUMMY_SDR/DUMMY_RWDS_SDR used
                                                            in DDR sequence. */
     kFLEXSPI_AhbCmdErrorDdrDummyInSdrSequence = 0x5U, /*!< Instruction DUMMY_DDR/DUMMY_RWDS_DDR
@@ -211,17 +189,18 @@ typedef enum _flexspi_ahb_error_code
 typedef enum _flexspi_port
 {
     kFLEXSPI_PortA1 = 0x0U, /*!< Access flash on A1 port. */
-    kFLEXSPI_PortA2 = 0x1U, /*!< Access flash on A2 port. */
-    kFLEXSPI_PortB1 = 0x2U, /*!< Access flash on B1 port. */
-    kFLEXSPI_PortB2 = 0x3U, /*!< Access flash on B2 port. */
+    kFLEXSPI_PortA2,        /*!< Access flash on A2 port. */
+    kFLEXSPI_PortB1,        /*!< Access flash on B1 port. */
+    kFLEXSPI_PortB2,        /*!< Access flash on B2 port. */
+    kFLEXSPI_PortCount
 } flexspi_port_t;
 
 /*! @brief Trigger source of current command sequence granted by arbitrator.*/
 typedef enum _flexspi_arb_command_source
 {
-    kFLEXSPI_AhbReadCommand = 0x0U,
-    kFLEXSPI_AhbWriteCommand = 0x1U,
-    kFLEXSPI_IpCommand = 0x2U,
+    kFLEXSPI_AhbReadCommand   = 0x0U,
+    kFLEXSPI_AhbWriteCommand  = 0x1U,
+    kFLEXSPI_IpCommand        = 0x2U,
     kFLEXSPI_SuspendedCommand = 0x3U,
 } flexspi_arb_command_source_t;
 
@@ -239,7 +218,7 @@ typedef struct _flexspi_ahbBuffer_config
     uint8_t masterIndex; /*!< AHB Master ID the AHB RX Buffer is assigned. */
     uint16_t bufferSize; /*!< AHB buffer size in byte. */
     bool enablePrefetch; /*!< AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master, allows
-                          prefetch disable/enable seperately for each master. */
+                          prefetch disable/enable separately for each master. */
 } flexspi_ahbBuffer_config_t;
 
 /*! @brief FLEXSPI configuration structure. */
@@ -264,8 +243,12 @@ typedef struct _flexspi_config
     uint8_t rxWatermark;                       /*!< FLEXSPI receive watermark value. */
     struct
     {
-        bool enableAHBWriteIpTxFifo;  /*!< Enable AHB bus write access to IP TX FIFO. */
-        bool enableAHBWriteIpRxFifo;  /*!< Enable AHB bus write access to IP RX FIFO. */
+#if !(defined(FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN) && FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN)
+        bool enableAHBWriteIpTxFifo; /*!< Enable AHB bus write access to IP TX FIFO. */
+#endif
+#if !(defined(FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN) && FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN)
+        bool enableAHBWriteIpRxFifo; /*!< Enable AHB bus write access to IP RX FIFO. */
+#endif
         uint8_t ahbGrantTimeoutCycle; /*!< Timeout wait cycle for AHB command grant,
                                        timeout after ahbGrantTimeoutCyle*1024 AHB clock cycles. */
         uint16_t ahbBusTimeoutCycle;  /*!< Timeout wait cycle for AHB read/write access,
@@ -276,11 +259,11 @@ typedef struct _flexspi_config
         bool enableClearAHBBufferOpt; /*!< Enable/disable automatically clean AHB RX Buffer and TX Buffer
                                        when FLEXSPI returns STOP mode ACK. */
         bool enableReadAddressOpt;    /*!< Enable/disable remove AHB read burst start address alignment limitation.
-                                       when eanble, there is no AHB read burst start address alignment limitation. */
+                                       when enable, there is no AHB read burst start address alignment limitation. */
         bool enableAHBPrefetch;       /*!< Enable/disable AHB read prefetch feature, when enabled, FLEXSPI
                                        will fetch more data than current AHB burst. */
         bool enableAHBBufferable;     /*!< Enable/disable AHB bufferable write access support, when enabled,
-                                       FLEXSPI return before waiting for command excution finished. */
+                                       FLEXSPI return before waiting for command execution finished. */
         bool enableAHBCachable;       /*!< Enable AHB bus cachable read access support. */
     } ahbConfig;
 } flexspi_config_t;
@@ -292,7 +275,7 @@ typedef struct _flexspi_device_config
     bool isSck2Enabled;                              /*!< FLEXSPI use SCK2. */
     uint32_t flashSize;                              /*!< Flash size in KByte. */
     flexspi_cs_interval_cycle_unit_t CSIntervalUnit; /*!< CS interval unit, 1 or 256 cycle. */
-    uint16_t CSInterval;                             /*!< CS line assert interval, mutiply CS interval unit to
+    uint16_t CSInterval;                             /*!< CS line assert interval, multiply CS interval unit to
                                                       get the CS line assert interval cycles. */
     uint8_t CSHoldTime;                              /*!< CS line hold time. */
     uint8_t CSSetupTime;                             /*!< CS line setup time. */
@@ -304,7 +287,7 @@ typedef struct _flexspi_device_config
     uint8_t ARDSeqIndex;                             /*!< Sequence ID for AHB read command. */
     uint8_t ARDSeqNumber;                            /*!< Sequence number for AHB read command. */
     flexspi_ahb_write_wait_unit_t AHBWriteWaitUnit;  /*!< AHB write wait unit. */
-    uint16_t AHBWriteWaitInterval;                   /*!< AHB write wait interval, mutiply AHB write interval
+    uint16_t AHBWriteWaitInterval;                   /*!< AHB write wait interval, multiply AHB write interval
                                                       unit to get the AHB write wait cycles. */
     bool enableWriteMask;                            /*!< Enable/Disable FLEXSPI drive DQS pin as write mask
                                                       when writing to external device. */
@@ -350,6 +333,14 @@ struct _flexspi_handle
 extern "C" {
 #endif /*_cplusplus. */
 
+/**
+ * @brief Set bytes in memory. If put this code in SRAM, Make sure this code
+ * does not call functions in Flash.
+ *
+ * @return pointer to start of buffer
+ */
+extern void *flexspi_memset(void *buf, int c, size_t n);
+
 /*!
  * @name Initialization and deinitialization
  * @{
@@ -363,14 +354,14 @@ extern "C" {
  * @param base FLEXSPI peripheral base address.
  * @param config FLEXSPI configure structure.
  */
-void FLEXSPI_Init(FLEXSPI_Type *base, const flexspi_config_t *config);
+AT_QUICKACCESS_SECTION_CODE(void FLEXSPI_Init(FLEXSPI_Type *base, const flexspi_config_t *config));
 
 /*!
  * @brief Gets default settings for FLEXSPI.
  *
  * @param config FLEXSPI configuration structure.
  */
-void FLEXSPI_GetDefaultConfig(flexspi_config_t *config);
+AT_QUICKACCESS_SECTION_CODE(void FLEXSPI_GetDefaultConfig(flexspi_config_t *config));
 
 /*!
  * @brief Deinitializes the FLEXSPI module.
@@ -391,7 +382,9 @@ void FLEXSPI_Deinit(FLEXSPI_Type *base);
  * @param config Flash configuration parameters.
  * @param port FLEXSPI Operation port.
  */
-void FLEXSPI_SetFlashConfig(FLEXSPI_Type *base, flexspi_device_config_t *config, flexspi_port_t port);
+AT_QUICKACCESS_SECTION_CODE(void FLEXSPI_SetFlashConfig(FLEXSPI_Type *base,
+                                                        flexspi_device_config_t *config,
+                                                        flexspi_port_t port));
 
 /*!
  * @brief Software reset for the FLEXSPI logic.
@@ -401,10 +394,10 @@ void FLEXSPI_SetFlashConfig(FLEXSPI_Type *base, flexspi_device_config_t *config,
  *
  * @param base FLEXSPI peripheral base address.
  */
-static inline void FLEXSPI_SoftwareReset(FLEXSPI_Type *base)
+AT_QUICKACCESS_SECTION_CODE(static inline void FLEXSPI_SoftwareReset(FLEXSPI_Type *base))
 {
     base->MCR0 |= FLEXSPI_MCR0_SWRESET_MASK;
-    while (base->MCR0 & FLEXSPI_MCR0_SWRESET_MASK)
+    while (0U != (base->MCR0 & FLEXSPI_MCR0_SWRESET_MASK))
     {
     }
 }
@@ -415,7 +408,7 @@ static inline void FLEXSPI_SoftwareReset(FLEXSPI_Type *base)
  * @param base FLEXSPI peripheral base address.
  * @param enable True means enable FLEXSPI, false means disable.
  */
-static inline void FLEXSPI_Enable(FLEXSPI_Type *base, bool enable)
+AT_QUICKACCESS_SECTION_CODE(static inline void FLEXSPI_Enable(FLEXSPI_Type *base, bool enable))
 {
     if (enable)
     {
@@ -552,11 +545,11 @@ static inline void FLEXSPI_ResetFifos(FLEXSPI_Type *base, bool txFifo, bool rxFi
  */
 static inline void FLEXSPI_GetFifoCounts(FLEXSPI_Type *base, size_t *txCount, size_t *rxCount)
 {
-    if (txCount)
+    if (NULL != txCount)
     {
         *txCount = (((base->IPTXFSTS) & FLEXSPI_IPTXFSTS_FILL_MASK) >> FLEXSPI_IPTXFSTS_FILL_SHIFT) * 8U;
     }
-    if (rxCount)
+    if (NULL != rxCount)
     {
         *rxCount = (((base->IPRXFSTS) & FLEXSPI_IPRXFSTS_FILL_MASK) >> FLEXSPI_IPRXFSTS_FILL_SHIFT) * 8U;
     }
@@ -585,7 +578,7 @@ static inline uint32_t FLEXSPI_GetInterruptStatusFlags(FLEXSPI_Type *base)
  * @param base FLEXSPI peripheral base address.
  * @param interrupt status flag.
  */
-static inline void FLEXSPI_ClearInterruptStatusFlags(FLEXSPI_Type *base, uint32_t mask)
+AT_QUICKACCESS_SECTION_CODE(static inline void FLEXSPI_ClearInterruptStatusFlags(FLEXSPI_Type *base, uint32_t mask))
 {
     base->INTR |= mask;
 }
@@ -618,7 +611,8 @@ static inline void FLEXSPI_GetDataLearningPhase(FLEXSPI_Type *base, uint8_t *por
  */
 static inline flexspi_arb_command_source_t FLEXSPI_GetArbitratorCommandSource(FLEXSPI_Type *base)
 {
-    return (flexspi_arb_command_source_t)((base->STS0 & FLEXSPI_STS0_ARBCMDSRC_MASK) >> FLEXSPI_STS0_ARBCMDSRC_SHIFT);
+    return (flexspi_arb_command_source_t)(
+        (uint32_t)((base->STS0 & FLEXSPI_STS0_ARBCMDSRC_MASK) >> FLEXSPI_STS0_ARBCMDSRC_SHIFT));
 }
 
 /*! @brief Gets the error code when IP command error detected.
@@ -629,8 +623,9 @@ static inline flexspi_arb_command_source_t FLEXSPI_GetArbitratorCommandSource(FL
  */
 static inline flexspi_ip_error_code_t FLEXSPI_GetIPCommandErrorCode(FLEXSPI_Type *base, uint8_t *index)
 {
-    *index = (base->STS1 & FLEXSPI_STS1_IPCMDERRID_MASK) >> FLEXSPI_STS1_IPCMDERRID_SHIFT;
-    return (flexspi_ip_error_code_t)((base->STS1 & FLEXSPI_STS1_IPCMDERRCODE_MASK) >> FLEXSPI_STS1_IPCMDERRCODE_SHIFT);
+    *index = (uint8_t)((base->STS1 & FLEXSPI_STS1_IPCMDERRID_MASK) >> FLEXSPI_STS1_IPCMDERRID_SHIFT);
+    return (flexspi_ip_error_code_t)(
+        (uint32_t)((base->STS1 & FLEXSPI_STS1_IPCMDERRCODE_MASK) >> FLEXSPI_STS1_IPCMDERRCODE_SHIFT));
 }
 
 /*! @brief Gets the error code when AHB command error detected.
@@ -641,9 +636,9 @@ static inline flexspi_ip_error_code_t FLEXSPI_GetIPCommandErrorCode(FLEXSPI_Type
  */
 static inline flexspi_ahb_error_code_t FLEXSPI_GetAHBCommandErrorCode(FLEXSPI_Type *base, uint8_t *index)
 {
-    *index = (base->STS1 & FLEXSPI_STS1_AHBCMDERRID_MASK) >> FLEXSPI_STS1_AHBCMDERRID_SHIFT;
-    return (flexspi_ahb_error_code_t)((base->STS1 & FLEXSPI_STS1_AHBCMDERRCODE_MASK) >>
-                                      FLEXSPI_STS1_AHBCMDERRCODE_SHIFT);
+    *index = (uint8_t)(base->STS1 & FLEXSPI_STS1_AHBCMDERRID_MASK) >> FLEXSPI_STS1_AHBCMDERRID_SHIFT;
+    return (flexspi_ahb_error_code_t)(
+        (uint32_t)((base->STS1 & FLEXSPI_STS1_AHBCMDERRCODE_MASK) >> FLEXSPI_STS1_AHBCMDERRCODE_SHIFT));
 }
 
 /*! @brief Returns whether the bus is idle.
@@ -652,9 +647,9 @@ static inline flexspi_ahb_error_code_t FLEXSPI_GetAHBCommandErrorCode(FLEXSPI_Ty
  * @retval true Bus is idle.
  * @retval false Bus is busy.
  */
-static inline bool FLEXSPI_GetBusIdleStatus(FLEXSPI_Type *base)
+AT_QUICKACCESS_SECTION_CODE(static inline bool FLEXSPI_GetBusIdleStatus(FLEXSPI_Type *base))
 {
-    return (base->STS0 & FLEXSPI_STS0_ARBIDLE_MASK) && (base->STS0 & FLEXSPI_STS0_SEQIDLE_MASK);
+    return (0U != (base->STS0 & FLEXSPI_STS0_ARBIDLE_MASK)) && (0U != (base->STS0 & FLEXSPI_STS0_SEQIDLE_MASK));
 }
 /*@}*/
 
@@ -663,6 +658,13 @@ static inline bool FLEXSPI_GetBusIdleStatus(FLEXSPI_Type *base)
  * @{
  */
 
+/*! @brief Update read sample clock source
+ *
+ * @param base FLEXSPI peripheral base address.
+ * @param clockSource clockSource of type #flexspi_read_sample_clock_t
+ */
+void FLEXSPI_UpdateRxSampleClock(FLEXSPI_Type *base, flexspi_read_sample_clock_t clockSource);
+
 /*! @brief Enables/disables the FLEXSPI IP command parallel mode.
  *
  * @param base FLEXSPI peripheral base address.
@@ -698,15 +700,16 @@ static inline void FLEXSPI_EnableAHBParallelMode(FLEXSPI_Type *base, bool enable
 }
 
 /*! @brief Updates the LUT table.
-*
-* @param base FLEXSPI peripheral base address.
-* @param index From which index start to update. It could be any index of the LUT table, which
-* also allows user to update command content inside a command. Each command consists of up to
-* 8 instructions and occupy 4*32-bit memory.
-* @param cmd Command sequence array.
-* @param count Number of sequences.
-*/
-void FLEXSPI_UpdateLUT(FLEXSPI_Type *base, uint32_t index, const uint32_t *cmd, uint32_t count);
+ *
+ * @param base FLEXSPI peripheral base address.
+ * @param index From which index start to update. It could be any index of the LUT table, which
+ * also allows user to update command content inside a command. Each command consists of up to
+ * 8 instructions and occupy 4*32-bit memory.
+ * @param cmd Command sequence array.
+ * @param count Number of sequences.
+ */
+AT_QUICKACCESS_SECTION_CODE(void FLEXSPI_UpdateLUT(FLEXSPI_Type *base, uint32_t index,
+                                                   const uint32_t *cmd, uint32_t count));
 
 /*!
  * @brief Writes data into FIFO.
@@ -740,10 +743,11 @@ static inline uint32_t FLEXSPI_ReadData(FLEXSPI_Type *base, uint8_t fifoIndex)
  * @param size The number of data bytes to send
  * @retval kStatus_Success write success without error
  * @retval kStatus_FLEXSPI_SequenceExecutionTimeout sequence execution timeout
- * @retval kStatus_FLEXSPI_IpCommandSequenceError IP command sequencen error detected
+ * @retval kStatus_FLEXSPI_IpCommandSequenceError IP command sequence error detected
  * @retval kStatus_FLEXSPI_IpCommandGrantTimeout IP command grant timeout detected
  */
-status_t FLEXSPI_WriteBlocking(FLEXSPI_Type *base, uint32_t *buffer, size_t size);
+AT_QUICKACCESS_SECTION_CODE(status_t FLEXSPI_WriteBlocking(FLEXSPI_Type *base,
+                                                           uint32_t *buffer, size_t size));
 
 /*!
  * @brief Receives a buffer of data bytes using a blocking method.
@@ -756,7 +760,8 @@ status_t FLEXSPI_WriteBlocking(FLEXSPI_Type *base, uint32_t *buffer, size_t size
  * @retval kStatus_FLEXSPI_IpCommandSequenceError IP command sequencen error detected
  * @retval kStatus_FLEXSPI_IpCommandGrantTimeout IP command grant timeout detected
  */
-status_t FLEXSPI_ReadBlocking(FLEXSPI_Type *base, uint32_t *buffer, size_t size);
+AT_QUICKACCESS_SECTION_CODE(status_t FLEXSPI_ReadBlocking(FLEXSPI_Type *base,
+                                                          uint32_t *buffer, size_t size));
 
 /*!
  * @brief Execute command to transfer a buffer data bytes using a blocking method.
@@ -764,10 +769,11 @@ status_t FLEXSPI_ReadBlocking(FLEXSPI_Type *base, uint32_t *buffer, size_t size)
  * @param xfer pointer to the transfer structure.
  * @retval kStatus_Success command transfer success without error
  * @retval kStatus_FLEXSPI_SequenceExecutionTimeout sequence execution timeout
- * @retval kStatus_FLEXSPI_IpCommandSequenceError IP command sequencen error detected
+ * @retval kStatus_FLEXSPI_IpCommandSequenceError IP command sequence error detected
  * @retval kStatus_FLEXSPI_IpCommandGrantTimeout IP command grant timeout detected
-*/
-status_t FLEXSPI_TransferBlocking(FLEXSPI_Type *base, flexspi_transfer_t *xfer);
+ */
+AT_QUICKACCESS_SECTION_CODE(status_t FLEXSPI_TransferBlocking(FLEXSPI_Type *base,
+                                                              flexspi_transfer_t *xfer));
 /*! @} */
 
 /*!
@@ -794,7 +800,7 @@ void FLEXSPI_TransferCreateHandle(FLEXSPI_Type *base,
  * @note Calling the API returns immediately after transfer initiates. The user needs
  * to call FLEXSPI_GetTransferCount to poll the transfer status to check whether
  * the transfer is finished. If the return status is not kStatus_FLEXSPI_Busy, the transfer
- * is finished. For FLEXSPI_Read, the dataSize should be multiple of rx watermark levle, or
+ * is finished. For FLEXSPI_Read, the dataSize should be multiple of rx watermark level, or
  * FLEXSPI could not read data properly.
  *
  * @param base FLEXSPI peripheral base address.
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexspi_nor_boot.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexspi_nor_boot.c
index 3147fa40ccd..41b273f70b4 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexspi_nor_boot.c
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexspi_nor_boot.c
@@ -1,38 +1,17 @@
 /*
- * The Clear BSD License
  * Copyright 2017 NXP
  * All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- * that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include "fsl_flexspi_nor_boot.h"
 
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.xip_device"
+#endif
+
 #if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
 #if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
     __attribute__((section(".boot_hdr.ivt")))
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexspi_nor_boot.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexspi_nor_boot.h
index 897d7e9bd47..07bbfcae6b5 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexspi_nor_boot.h
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexspi_nor_boot.h
@@ -1,34 +1,8 @@
 /*
- * The Clear BSD License
  * Copyright 2017 NXP
  * All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- * that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #ifndef __FLEXSPI_NOR_BOOT_H__
@@ -37,8 +11,14 @@
 #include <stdint.h>
 #include "device.h"
 
-/*************************************
- *  IVT Data
+/*! @name Driver version */
+/*@{*/
+/*! @brief XIP_DEVICE driver version 2.0.0. */
+#define FSL_XIP_DEVICE_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*@}*/
+
+/************************************* 
+ *  IVT Data 
  *************************************/
 typedef struct _ivt_ {
     /** @ref hdr with tag #HAB_TAG_IVT, length and HAB version fields
@@ -76,7 +56,7 @@ typedef struct _ivt_ {
   ((((major) & IVT_MAJOR_VERSION_MASK) << IVT_MAJOR_VERSION_SHIFT) |  \
   (((minor) & IVT_MINOR_VERSION_MASK) << IVT_MINOR_VERSION_SHIFT))
 
-/* IVT header */
+/* IVT header */  
 #define IVT_TAG_HEADER        0xD1       /**< Image Vector Table */
 #define IVT_SIZE              0x2000
 #define IVT_PAR               IVT_VERSION(IVT_MAJOR_VERSION, IVT_MINOR_VERSION)
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_gpc.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_gpc.c
index 90b7eb1542f..a91e16377b1 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_gpc.c
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_gpc.c
@@ -1,36 +1,10 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2016, Freescale Semiconductor, Inc.
  * Copyright 2016 NXP
  * All rights reserved.
  *
- * 
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
  *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include "fsl_gpc.h"
@@ -40,10 +14,15 @@
 #define FSL_COMPONENT_ID "platform.drivers.gpc_1"
 #endif
 
-
+/*!
+ * brief Enable the IRQ.
+ *
+ * param base GPC peripheral base address.
+ * param irqId ID number of IRQ to be enabled, available range is 32-159.
+ */
 void GPC_EnableIRQ(GPC_Type *base, uint32_t irqId)
 {
-    uint32_t irqRegNum = irqId / 32U;
+    uint32_t irqRegNum      = irqId / 32U;
     uint32_t irqRegShiftNum = irqId % 32U;
 
     assert(irqRegNum > 0U);
@@ -63,9 +42,15 @@ void GPC_EnableIRQ(GPC_Type *base, uint32_t irqId)
 #endif /* FSL_FEATURE_GPC_HAS_IRQ_0_31 */
 }
 
+/*!
+ * brief Disable the IRQ.
+ *
+ * param base GPC peripheral base address.
+ * param irqId ID number of IRQ to be disabled, available range is 32-159.
+ */
 void GPC_DisableIRQ(GPC_Type *base, uint32_t irqId)
 {
-    uint32_t irqRegNum = irqId / 32U;
+    uint32_t irqRegNum      = irqId / 32U;
     uint32_t irqRegShiftNum = irqId % 32U;
 
     assert(irqRegNum > 0U);
@@ -85,9 +70,16 @@ void GPC_DisableIRQ(GPC_Type *base, uint32_t irqId)
 #endif /* FSL_FEATURE_GPC_HAS_IRQ_0_31 */
 }
 
+/*!
+ * brief Get the IRQ/Event flag.
+ *
+ * param base GPC peripheral base address.
+ * param irqId ID number of IRQ to be enabled, available range is 32-159.
+ * return Indicated IRQ/Event is asserted or not.
+ */
 bool GPC_GetIRQStatusFlag(GPC_Type *base, uint32_t irqId)
 {
-    uint32_t irqRegNum = irqId / 32U;
+    uint32_t irqRegNum      = irqId / 32U;
     uint32_t irqRegShiftNum = irqId % 32U;
     uint32_t ret;
 
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_gpc.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_gpc.h
index 5ba31ecf658..09dbaa15deb 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_gpc.h
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_gpc.h
@@ -1,36 +1,10 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2016, Freescale Semiconductor, Inc.
  * Copyright 2016 NXP
  * All rights reserved.
  *
- * 
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
  *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #ifndef _FSL_GPC_H_
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_gpio.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_gpio.c
index f4714aa53e0..98434f323da 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_gpio.c
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_gpio.c
@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2016, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
  * All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include "fsl_gpio.h"
@@ -39,7 +13,6 @@
 #define FSL_COMPONENT_ID "platform.drivers.igpio"
 #endif
 
-
 /*******************************************************************************
  * Variables
  ******************************************************************************/
@@ -53,15 +26,15 @@ static const clock_ip_name_t s_gpioClock[] = GPIO_CLOCKS;
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
 /*******************************************************************************
-* Prototypes
-******************************************************************************/
+ * Prototypes
+ ******************************************************************************/
 
 /*!
-* @brief Gets the GPIO instance according to the GPIO base
-*
-* @param base    GPIO peripheral base pointer(PTA, PTB, PTC, etc.)
-* @retval GPIO instance
-*/
+ * @brief Gets the GPIO instance according to the GPIO base
+ *
+ * @param base    GPIO peripheral base pointer(PTA, PTB, PTC, etc.)
+ * @retval GPIO instance
+ */
 static uint32_t GPIO_GetInstance(GPIO_Type *base);
 
 /*******************************************************************************
@@ -86,11 +59,26 @@ static uint32_t GPIO_GetInstance(GPIO_Type *base)
     return instance;
 }
 
+/*!
+ * brief Initializes the GPIO peripheral according to the specified
+ *        parameters in the initConfig.
+ *
+ * param base GPIO base pointer.
+ * param pin Specifies the pin number
+ * param initConfig pointer to a ref gpio_pin_config_t structure that
+ *        contains the configuration information.
+ */
 void GPIO_PinInit(GPIO_Type *base, uint32_t pin, const gpio_pin_config_t *Config)
 {
 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* Enable GPIO clock. */
-    CLOCK_EnableClock(s_gpioClock[GPIO_GetInstance(base)]);
+    uint32_t instance = GPIO_GetInstance(base);
+
+    /* If The clock IP is valid, enable the clock gate. */
+    if ((instance < ARRAY_SIZE(s_gpioClock)) && (kCLOCK_IpInvalid != s_gpioClock[instance]))
+    {
+        CLOCK_EnableClock(s_gpioClock[instance]);
+    }
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
     /* Register reset to default value */
@@ -111,6 +99,15 @@ void GPIO_PinInit(GPIO_Type *base, uint32_t pin, const gpio_pin_config_t *Config
     GPIO_SetPinInterruptConfig(base, pin, Config->interruptMode);
 }
 
+/*!
+ * brief Sets the output level of the individual GPIO pin to logic 1 or 0.
+ *
+ * param base GPIO base pointer.
+ * param pin GPIO port pin number.
+ * param output GPIOpin output logic level.
+ *        - 0: corresponding pin output low-logic level.
+ *        - 1: corresponding pin output high-logic level.
+ */
 void GPIO_PinWrite(GPIO_Type *base, uint32_t pin, uint8_t output)
 {
     assert(pin < 32);
@@ -124,6 +121,14 @@ void GPIO_PinWrite(GPIO_Type *base, uint32_t pin, uint8_t output)
     }
 }
 
+/*!
+ * brief Sets the current pin interrupt mode.
+ *
+ * param base GPIO base pointer.
+ * param pin GPIO port pin number.
+ * param pininterruptMode pointer to a ref gpio_interrupt_mode_t structure
+ *        that contains the interrupt mode information.
+ */
 void GPIO_PinSetInterruptConfig(GPIO_Type *base, uint32_t pin, gpio_interrupt_mode_t pinInterruptMode)
 {
     volatile uint32_t *icr;
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_gpio.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_gpio.h
index 834a9c981ad..99b30f89362 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_gpio.h
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_gpio.h
@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
+ * Copyright 2016-2019 NXP
  * All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #ifndef _FSL_GPIO_H_
@@ -48,25 +22,25 @@
 
 /*! @name Driver version */
 /*@{*/
-/*! @brief GPIO driver version 2.0.1. */
-#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
+/*! @brief GPIO driver version 2.0.2. */
+#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
 /*@}*/
 
 /*! @brief GPIO direction definition. */
 typedef enum _gpio_pin_direction
 {
-    kGPIO_DigitalInput = 0U,  /*!< Set current pin as digital input.*/
+    kGPIO_DigitalInput  = 0U, /*!< Set current pin as digital input.*/
     kGPIO_DigitalOutput = 1U, /*!< Set current pin as digital output.*/
 } gpio_pin_direction_t;
 
 /*! @brief GPIO interrupt mode definition. */
 typedef enum _gpio_interrupt_mode
 {
-    kGPIO_NoIntmode = 0U,              /*!< Set current pin general IO functionality.*/
-    kGPIO_IntLowLevel = 1U,            /*!< Set current pin interrupt is low-level sensitive.*/
-    kGPIO_IntHighLevel = 2U,           /*!< Set current pin interrupt is high-level sensitive.*/
-    kGPIO_IntRisingEdge = 3U,          /*!< Set current pin interrupt is rising-edge sensitive.*/
-    kGPIO_IntFallingEdge = 4U,         /*!< Set current pin interrupt is falling-edge sensitive.*/
+    kGPIO_NoIntmode              = 0U, /*!< Set current pin general IO functionality.*/
+    kGPIO_IntLowLevel            = 1U, /*!< Set current pin interrupt is low-level sensitive.*/
+    kGPIO_IntHighLevel           = 2U, /*!< Set current pin interrupt is high-level sensitive.*/
+    kGPIO_IntRisingEdge          = 3U, /*!< Set current pin interrupt is rising-edge sensitive.*/
+    kGPIO_IntFallingEdge         = 4U, /*!< Set current pin interrupt is falling-edge sensitive.*/
     kGPIO_IntRisingOrFallingEdge = 5U, /*!< Enable the edge select bit to override the ICR register's configuration.*/
 } gpio_interrupt_mode_t;
 
@@ -220,12 +194,12 @@ static inline uint32_t GPIO_ReadPinInput(GPIO_Type *base, uint32_t pin)
  */
 
 /*!
-* @brief Reads the current GPIO pin pad status.
-*
-* @param base GPIO base pointer.
-* @param pin GPIO port pin number.
-* @retval GPIO pin pad status value.
-*/
+ * @brief Reads the current GPIO pin pad status.
+ *
+ * @param base GPIO base pointer.
+ * @param pin GPIO port pin number.
+ * @retval GPIO pin pad status value.
+ */
 static inline uint8_t GPIO_PinReadPadStatus(GPIO_Type *base, uint32_t pin)
 {
     assert(pin < 32);
@@ -234,9 +208,9 @@ static inline uint8_t GPIO_PinReadPadStatus(GPIO_Type *base, uint32_t pin)
 }
 
 /*!
-* @brief Reads the current GPIO pin pad status.
-* @deprecated Do not use this function.  It has been superceded by @ref GPIO_PinReadPadStatus.
-*/
+ * @brief Reads the current GPIO pin pad status.
+ * @deprecated Do not use this function.  It has been superceded by @ref GPIO_PinReadPadStatus.
+ */
 static inline uint8_t GPIO_ReadPadStatus(GPIO_Type *base, uint32_t pin)
 {
     return GPIO_PinReadPadStatus(base, pin);
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_gpt.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_gpt.c
index 39b0e89fb59..697be010a7b 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_gpt.c
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_gpt.c
@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
  * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
  *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include "fsl_gpt.h"
@@ -39,7 +13,6 @@
 #define FSL_COMPONENT_ID "platform.drivers.gpt"
 #endif
 
-
 /*******************************************************************************
  * Prototypes
  ******************************************************************************/
@@ -76,6 +49,12 @@ static uint32_t GPT_GetInstance(GPT_Type *base)
     return instance;
 }
 
+/*!
+ * brief Initialize GPT to reset state and initialize running mode.
+ *
+ * param base GPT peripheral base address.
+ * param initConfig GPT mode setting configuration.
+ */
 void GPT_Init(GPT_Type *base, const gpt_config_t *initConfig)
 {
     assert(initConfig);
@@ -98,6 +77,11 @@ void GPT_Init(GPT_Type *base, const gpt_config_t *initConfig)
     GPT_SetClockDivider(base, initConfig->divider);
 }
 
+/*!
+ * brief Disables the module and gates the GPT clock.
+ *
+ * param base GPT peripheral base address.
+ */
 void GPT_Deinit(GPT_Type *base)
 {
     /* Disable GPT timers */
@@ -109,16 +93,35 @@ void GPT_Deinit(GPT_Type *base)
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }
 
+/*!
+ * brief Fills in the GPT configuration structure with default settings.
+ *
+ * The default values are:
+ * code
+ *    config->clockSource = kGPT_ClockSource_Periph;
+ *    config->divider = 1U;
+ *    config->enableRunInStop = true;
+ *    config->enableRunInWait = true;
+ *    config->enableRunInDoze = false;
+ *    config->enableRunInDbg = false;
+ *    config->enableFreeRun = true;
+ *    config->enableMode  = true;
+ * endcode
+ * param config Pointer to the user configuration structure.
+ */
 void GPT_GetDefaultConfig(gpt_config_t *config)
 {
     assert(config);
 
-    config->clockSource = kGPT_ClockSource_Periph;
-    config->divider = 1U;
+    /* Initializes the configure structure to zero. */
+    memset(config, 0, sizeof(*config));
+
+    config->clockSource     = kGPT_ClockSource_Periph;
+    config->divider         = 1U;
     config->enableRunInStop = true;
     config->enableRunInWait = true;
     config->enableRunInDoze = false;
-    config->enableRunInDbg = false;
-    config->enableFreeRun = false;
-    config->enableMode = true;
+    config->enableRunInDbg  = false;
+    config->enableFreeRun   = false;
+    config->enableMode      = true;
 }
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_gpt.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_gpt.h
index 1cea0545571..36665059054 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_gpt.h
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_gpt.h
@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
  * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
  *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #ifndef _FSL_GPT_H_
@@ -57,12 +31,12 @@
  */
 typedef enum _gpt_clock_source
 {
-    kGPT_ClockSource_Off = 0U,      /*!< GPT Clock Source Off.*/
-    kGPT_ClockSource_Periph = 1U,   /*!< GPT Clock Source from Peripheral Clock.*/
+    kGPT_ClockSource_Off      = 0U, /*!< GPT Clock Source Off.*/
+    kGPT_ClockSource_Periph   = 1U, /*!< GPT Clock Source from Peripheral Clock.*/
     kGPT_ClockSource_HighFreq = 2U, /*!< GPT Clock Source from High Frequency Reference Clock.*/
-    kGPT_ClockSource_Ext = 3U,      /*!< GPT Clock Source from external pin.*/
-    kGPT_ClockSource_LowFreq = 4U,  /*!< GPT Clock Source from Low Frequency Reference Clock.*/
-    kGPT_ClockSource_Osc = 5U,      /*!< GPT Clock Source from Crystal oscillator.*/
+    kGPT_ClockSource_Ext      = 3U, /*!< GPT Clock Source from external pin.*/
+    kGPT_ClockSource_LowFreq  = 4U, /*!< GPT Clock Source from Low Frequency Reference Clock.*/
+    kGPT_ClockSource_Osc      = 5U, /*!< GPT Clock Source from Crystal oscillator.*/
 } gpt_clock_source_t;
 
 /*! @brief List of input capture channel number. */
@@ -93,10 +67,10 @@ typedef enum _gpt_output_compare_channel
 typedef enum _gpt_output_operation_mode
 {
     kGPT_OutputOperation_Disconnected = 0U, /*!< Don't change output pin.*/
-    kGPT_OutputOperation_Toggle = 1U,       /*!< Toggle output pin.*/
-    kGPT_OutputOperation_Clear = 2U,        /*!< Set output pin low.*/
-    kGPT_OutputOperation_Set = 3U,          /*!< Set output pin high.*/
-    kGPT_OutputOperation_Activelow = 4U,    /*!< Generate a active low pulse on output pin.*/
+    kGPT_OutputOperation_Toggle       = 1U, /*!< Toggle output pin.*/
+    kGPT_OutputOperation_Clear        = 2U, /*!< Set output pin low.*/
+    kGPT_OutputOperation_Set          = 3U, /*!< Set output pin high.*/
+    kGPT_OutputOperation_Activelow    = 4U, /*!< Generate a active low pulse on output pin.*/
 } gpt_output_operation_mode_t;
 
 /*! @brief List of GPT interrupts */
@@ -105,9 +79,9 @@ typedef enum _gpt_interrupt_enable
     kGPT_OutputCompare1InterruptEnable = GPT_IR_OF1IE_MASK, /*!< Output Compare Channel1 interrupt enable*/
     kGPT_OutputCompare2InterruptEnable = GPT_IR_OF2IE_MASK, /*!< Output Compare Channel2 interrupt enable*/
     kGPT_OutputCompare3InterruptEnable = GPT_IR_OF3IE_MASK, /*!< Output Compare Channel3 interrupt enable*/
-    kGPT_InputCapture1InterruptEnable = GPT_IR_IF1IE_MASK,  /*!< Input Capture Channel1 interrupt enable*/
-    kGPT_InputCapture2InterruptEnable = GPT_IR_IF2IE_MASK,  /*!< Input Capture Channel1 interrupt enable*/
-    kGPT_RollOverFlagInterruptEnable = GPT_IR_ROVIE_MASK,   /*!< Counter rolled over interrupt enable*/
+    kGPT_InputCapture1InterruptEnable  = GPT_IR_IF1IE_MASK, /*!< Input Capture Channel1 interrupt enable*/
+    kGPT_InputCapture2InterruptEnable  = GPT_IR_IF2IE_MASK, /*!< Input Capture Channel1 interrupt enable*/
+    kGPT_RollOverFlagInterruptEnable   = GPT_IR_ROVIE_MASK, /*!< Counter rolled over interrupt enable*/
 } gpt_interrupt_enable_t;
 
 /*! @brief Status flag. */
@@ -116,9 +90,9 @@ typedef enum _gpt_status_flag
     kGPT_OutputCompare1Flag = GPT_SR_OF1_MASK, /*!< Output compare channel 1 event.*/
     kGPT_OutputCompare2Flag = GPT_SR_OF2_MASK, /*!< Output compare channel 2 event.*/
     kGPT_OutputCompare3Flag = GPT_SR_OF3_MASK, /*!< Output compare channel 3 event.*/
-    kGPT_InputCapture1Flag = GPT_SR_IF1_MASK,  /*!< Input Capture channel 1 event.*/
-    kGPT_InputCapture2Flag = GPT_SR_IF2_MASK,  /*!< Input Capture channel 2 event.*/
-    kGPT_RollOverFlag = GPT_SR_ROV_MASK,       /*!< Counter reaches maximum value and rolled over to 0 event.*/
+    kGPT_InputCapture1Flag  = GPT_SR_IF1_MASK, /*!< Input Capture channel 1 event.*/
+    kGPT_InputCapture2Flag  = GPT_SR_IF2_MASK, /*!< Input Capture channel 2 event.*/
+    kGPT_RollOverFlag       = GPT_SR_ROV_MASK, /*!< Counter reaches maximum value and rolled over to 0 event.*/
 } gpt_status_flag_t;
 
 /*! @brief Structure to configure the running mode. */
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_iomuxc.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_iomuxc.h
index 2a7dabb8022..d6f335592b2 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_iomuxc.h
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_iomuxc.h
@@ -1,37 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright 2016 Freescale Semiconductor, Inc.
  * Copyright 2016-2018 NXP
  * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted (subject to the limitations in the
- * disclaimer below) provided that the following conditions are met:
- * 
- * * Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
- * 
- * * Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in the
- *   documentation and/or other materials provided with the distribution.
- * 
- * * Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from
- *   this software without specific prior written permission.
- * 
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
- * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
- * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
- * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
- * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #ifndef _FSL_IOMUXC_H_
@@ -1067,16 +1039,16 @@ typedef enum _iomuxc_gpr_mode
     kIOMUXC_GPR_SAI3MClkOutputDir = IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_MASK,
     kIOMUXC_GPR_ExcMonitorSlavErrResponse = IOMUXC_GPR_GPR1_EXC_MON_MASK,
     kIOMUXC_GPR_ENETIpgClkOn = IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN_MASK,
-    kIOMUXC_GPR_AHBClockEnable = IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_MASK,  
-}  iomuxc_gpr_mode_t;
+    kIOMUXC_GPR_AHBClockEnable = (int)IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_MASK,
+} iomuxc_gpr_mode_t;
 
 typedef enum _iomuxc_gpr_saimclk
 {
     kIOMUXC_GPR_SAI1MClk1Sel = IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_SHIFT,
     kIOMUXC_GPR_SAI1MClk2Sel = IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_SHIFT,
-    kIOMUXC_GPR_SAI1MClk3Sel = IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_SHIFT, 
-    kIOMUXC_GPR_SAI2MClk3Sel = IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_SHIFT, 
-    kIOMUXC_GPR_SAI3MClk3Sel = IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_SHIFT,  
+    kIOMUXC_GPR_SAI1MClk3Sel = IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_SHIFT,
+    kIOMUXC_GPR_SAI2MClk3Sel = IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_SHIFT,
+    kIOMUXC_GPR_SAI3MClk3Sel = IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_SHIFT,
 } iomuxc_gpr_saimclk_t;
 
 typedef enum _iomuxc_mqs_pwm_oversample_rate
@@ -1169,11 +1141,9 @@ static inline void IOMUXC_SetPinConfig(uint32_t muxRegister,
  */
 static inline void IOMUXC_EnableMode(IOMUXC_GPR_Type *base, uint32_t mode, bool enable)
 {
-    mode &= ~(IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_MASK
-            | IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_MASK
-            | IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_MASK
-            | IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK
-            | IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_MASK);
+    mode &= ~(IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_MASK | IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_MASK |
+              IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_MASK | IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK |
+              IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_MASK);
 
     if (enable)
     {
@@ -1199,17 +1169,17 @@ static inline void IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR_Type *base, iomuxc_gp
     if (mclk > kIOMUXC_GPR_SAI1MClk2Sel)
     {
         gpr = base->GPR1 & ~(IOMUXC_GPR_SAIMCLK_HIGHBITMASK << mclk);
-        base->GPR1 = ((clkSrc & IOMUXC_GPR_SAIMCLK_HIGHBITMASK) << mclk) | gpr;    
+        base->GPR1 = ((clkSrc & IOMUXC_GPR_SAIMCLK_HIGHBITMASK) << mclk) | gpr;
     }
     else
     {
         gpr = base->GPR1 & ~(IOMUXC_GPR_SAIMCLK_LOWBITMASK << mclk);
-        base->GPR1 = ((clkSrc & IOMUXC_GPR_SAIMCLK_LOWBITMASK) << mclk) | gpr;            
+        base->GPR1 = ((clkSrc & IOMUXC_GPR_SAIMCLK_LOWBITMASK) << mclk) | gpr;
     }
 }
 
 /*!
- * @brief Enters or exit MQS software reset.  
+ * @brief Enters or exit MQS software reset.
  *
  * @param base     The IOMUXC GPR base address.
  * @param enable   Enter or exit MQS software reset.
@@ -1218,17 +1188,16 @@ static inline void IOMUXC_MQSEnterSoftwareReset(IOMUXC_GPR_Type *base, bool enab
 {
     if (enable)
     {
-        base->GPR2 |= IOMUXC_GPR_GPR2_MQS_SW_RST_MASK;        
+        base->GPR2 |= IOMUXC_GPR_GPR2_MQS_SW_RST_MASK;
     }
     else
     {
-        base->GPR2 &= ~IOMUXC_GPR_GPR2_MQS_SW_RST_MASK;        
+        base->GPR2 &= ~IOMUXC_GPR_GPR2_MQS_SW_RST_MASK;
     }
 }
 
-
 /*!
- * @brief Enables or disables MQS.  
+ * @brief Enables or disables MQS.
  *
  * @param base     The IOMUXC GPR base address.
  * @param enable   Enable or disable the MQS.
@@ -1237,16 +1206,16 @@ static inline void IOMUXC_MQSEnable(IOMUXC_GPR_Type *base, bool enable)
 {
     if (enable)
     {
-        base->GPR2 |= IOMUXC_GPR_GPR2_MQS_EN_MASK;   
+        base->GPR2 |= IOMUXC_GPR_GPR2_MQS_EN_MASK;
     }
     else
     {
-        base->GPR2 &= ~IOMUXC_GPR_GPR2_MQS_EN_MASK;           
+        base->GPR2 &= ~IOMUXC_GPR_GPR2_MQS_EN_MASK;
     }
 }
 
 /*!
- * @brief Configure MQS PWM oversampling rate compared with mclk and divider ratio control for mclk from hmclk.  
+ * @brief Configure MQS PWM oversampling rate compared with mclk and divider ratio control for mclk from hmclk.
  *
  * @param base     The IOMUXC GPR base address.
  * @param rate     The MQS PWM oversampling rate, refer to "iomuxc_mqs_pwm_oversample_rate_t".
@@ -1256,7 +1225,7 @@ static inline void IOMUXC_MQSEnable(IOMUXC_GPR_Type *base, bool enable)
 static inline void IOMUXC_MQSConfig(IOMUXC_GPR_Type *base, iomuxc_mqs_pwm_oversample_rate_t rate, uint8_t divider)
 {
     uint32_t gpr = base->GPR2 & ~(IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_MASK | IOMUXC_GPR_GPR2_MQS_CLK_DIV_MASK);
-    
+
     base->GPR2 = gpr | IOMUXC_GPR_GPR2_MQS_OVERSAMPLE(rate) | IOMUXC_GPR_GPR2_MQS_CLK_DIV(divider);
 }
 
@@ -1269,4 +1238,3 @@ static inline void IOMUXC_MQSConfig(IOMUXC_GPR_Type *base, iomuxc_mqs_pwm_oversa
 /*! @}*/
 
 #endif /* _FSL_IOMUXC_H_ */
-
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_kpp.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_kpp.c
index f83fd257056..a7c8b3475f7 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_kpp.c
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_kpp.c
@@ -1,34 +1,8 @@
 /*
- * The Clear BSD License
  * Copyright 2017 NXP
  * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
  *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include "fsl_kpp.h"
@@ -89,6 +63,14 @@ static void KPP_Mdelay(uint64_t tickets)
     }
 }
 
+/*!
+ * brief KPP initialize.
+ * This function ungates the KPP clock and initializes KPP.
+ * This function must be called before calling any other KPP driver functions.
+ *
+ * param base KPP peripheral base address.
+ * param configure The KPP configuration structure pointer.
+ */
 void KPP_Init(KPP_Type *base, kpp_config_t *configure)
 {
     assert(configure);
@@ -105,15 +87,14 @@ void KPP_Init(KPP_Type *base, kpp_config_t *configure)
 
     /* Enable the keypad row and set the column strobe output to open drain. */
     base->KPCR = KPP_KPCR_KRE(configure->activeRow);
-    base->KPDR = KPP_KPDR_KCD((uint8_t)~(configure->activeColumn));
+    base->KPDR = KPP_KPDR_KCD((uint8_t) ~(configure->activeColumn));
     base->KPCR |= KPP_KPCR_KCO(configure->activeColumn);
 
     /* Set the input direction for row and output direction for column. */
-    base->KDDR = KPP_KDDR_KCDD(configure->activeColumn) | KPP_KDDR_KRDD((uint8_t)~(configure->activeRow));
+    base->KDDR = KPP_KDDR_KCDD(configure->activeColumn) | KPP_KDDR_KRDD((uint8_t) ~(configure->activeRow));
 
     /* Clear the status flag and enable the interrupt. */
-    base->KPSR =
-        KPP_KPSR_KPKR_MASK | KPP_KPSR_KPKD_MASK | KPP_KPSR_KDSC_MASK | configure->interrupt;
+    base->KPSR = KPP_KPSR_KPKR_MASK | KPP_KPSR_KPKD_MASK | KPP_KPSR_KDSC_MASK | configure->interrupt;
 
     if (configure->interrupt)
     {
@@ -122,6 +103,13 @@ void KPP_Init(KPP_Type *base, kpp_config_t *configure)
     }
 }
 
+/*!
+ * brief Deinitializes the KPP module and gates the clock.
+ * This function gates the KPP clock. As a result, the KPP
+ * module doesn't work after calling this function.
+ *
+ * param base KPP peripheral base address.
+ */
 void KPP_Deinit(KPP_Type *base)
 {
     /* Disable interrupts and disable all rows. */
@@ -134,12 +122,24 @@ void KPP_Deinit(KPP_Type *base)
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }
 
+/*!
+ * brief Keypad press scanning.
+ *
+ * This function will scanning all columns and rows. so
+ * all scanning data will be stored in the data pointer.
+ *
+ * param base  KPP peripheral base address.
+ * param data  KPP key press scanning data. The data buffer should be prepared with
+ * length at least equal to KPP_KEYPAD_COLUMNNUM_MAX * KPP_KEYPAD_ROWNUM_MAX.
+ * the data pointer is recommended to be a array like uint8_t data[KPP_KEYPAD_COLUMNNUM_MAX].
+ * for example the data[2] = 4, that means in column 1 row 2 has a key press event.
+ */
 void KPP_keyPressScanning(KPP_Type *base, uint8_t *data, uint32_t clockSrc_Hz)
 {
     assert(data);
 
-    uint16_t kppKCO = base->KPCR & KPP_KPCR_KCO_MASK;
-    uint8_t columIndex = 0;
+    uint16_t kppKCO      = base->KPCR & KPP_KPCR_KCO_MASK;
+    uint8_t columIndex   = 0;
     uint8_t activeColumn = (base->KPCR & KPP_KPCR_KCO_MASK) >> KPP_KPCR_KCO_SHIFT;
     uint8_t times;
     uint8_t rowData[KPP_KEYPAD_SCAN_TIMES][KPP_KEYPAD_COLUMNNUM_MAX];
@@ -178,7 +178,7 @@ void KPP_keyPressScanning(KPP_Type *base, uint8_t *data, uint32_t clockSrc_Hz)
             }
         }
     }
-    
+
     /* Return all columns to 0 in preparation for standby mode. */
     base->KPDR &= ~KPP_KPDR_KCD_MASK;
 
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_kpp.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_kpp.h
index 46eb3aab578..e462a38f633 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_kpp.h
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_kpp.h
@@ -1,34 +1,8 @@
 /*
- * The Clear BSD License
  * Copyright 2017 NXP
  * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
  *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 #ifndef _FSL_KPP_H_
 #define _FSL_KPP_H_
@@ -58,15 +32,17 @@
  * members. Members usually map to interrupt enable bits in one or more
  * peripheral registers.
  */
-typedef enum _kpp_interrupt_enable {
+typedef enum _kpp_interrupt_enable
+{
     kKPP_keyDepressInterrupt = KPP_KPSR_KDIE_MASK, /*!< Keypad depress interrupt source */
     kKPP_keyReleaseInterrupt = KPP_KPSR_KRIE_MASK  /*!< Keypad release interrupt source */
 } kpp_interrupt_enable_t;
 
 /*! @brief Lists of KPP synchronize chain operation. */
-typedef enum _kpp_sync_operation {
+typedef enum _kpp_sync_operation
+{
     kKPP_ClearKeyDepressSyncChain = KPP_KPSR_KDSC_MASK, /*!< Keypad depress interrupt status. */
-    kKPP_SetKeyReleasesSyncChain = KPP_KPSR_KRSS_MASK,  /*!< Keypad release interrupt status. */
+    kKPP_SetKeyReleasesSyncChain  = KPP_KPSR_KRSS_MASK, /*!< Keypad release interrupt status. */
 } kpp_sync_operation_t;
 
 /*! @brief Lists of KPP status. */
@@ -86,9 +62,9 @@ extern "C" {
 #endif
 
 /*!
-  * @name Initialization and De-initialization
-  * @{
-  */
+ * @name Initialization and De-initialization
+ * @{
+ */
 
 /*!
  * @brief KPP initialize.
@@ -126,7 +102,7 @@ void KPP_Deinit(KPP_Type *base);
 static inline void KPP_EnableInterrupts(KPP_Type *base, uint16_t mask)
 {
     uint16_t data = base->KPSR & ~(KPP_KPSR_KPKR_MASK | KPP_KPSR_KPKD_MASK);
-    base->KPSR = data | mask;
+    base->KPSR    = data | mask;
 }
 
 /*!
@@ -175,7 +151,7 @@ static inline void KPP_ClearStatusFlag(KPP_Type *base, uint16_t mask)
 static inline void KPP_SetSynchronizeChain(KPP_Type *base, uint16_t mask)
 {
     uint16_t data = base->KPSR & (KPP_KPSR_KRSS_MASK | KPP_KPSR_KDSC_MASK | KPP_KPSR_KRIE_MASK | KPP_KPSR_KDIE_MASK);
-    base->KPSR = data | mask;
+    base->KPSR    = data | mask;
 }
 
 /*!
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_lpi2c.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_lpi2c.c
index 7ce2c37213c..67b81fde793 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_lpi2c.c
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_lpi2c.c
@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
+ * Copyright 2016-2019 NXP
  * All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include "fsl_lpi2c.h"
@@ -80,8 +54,8 @@ enum _lpi2c_master_fifo_cmd
 {
     kTxDataCmd = LPI2C_MTDR_CMD(0x0U), /*!< Transmit DATA[7:0] */
     kRxDataCmd = LPI2C_MTDR_CMD(0X1U), /*!< Receive (DATA[7:0] + 1) bytes */
-    kStopCmd = LPI2C_MTDR_CMD(0x2U),   /*!< Generate STOP condition */
-    kStartCmd = LPI2C_MTDR_CMD(0x4U),  /*!< Generate(repeated) START and transmit address in DATA[[7:0] */
+    kStopCmd   = LPI2C_MTDR_CMD(0x2U), /*!< Generate STOP condition */
+    kStartCmd  = LPI2C_MTDR_CMD(0x4U), /*!< Generate(repeated) START and transmit address in DATA[[7:0] */
 };
 
 /*!
@@ -211,7 +185,7 @@ static uint32_t LPI2C_GetCyclesForWidth(uint32_t sourceClock_Hz,
     assert(prescaler > 0);
 
     uint32_t busCycle_ns = 1000000 / (sourceClock_Hz / prescaler / 1000);
-    uint32_t cycles = 0;
+    uint32_t cycles      = 0;
 
     /* Search for the cycle count just below the desired glitch width. */
     while ((((cycles + 1) * busCycle_ns) < width_ns) && (cycles + 1 < maxCycles))
@@ -239,6 +213,7 @@ static uint32_t LPI2C_GetCyclesForWidth(uint32_t sourceClock_Hz,
  * @retval #kStatus_LPI2C_Nak
  * @retval #kStatus_LPI2C_FifoError
  */
+/* Not static so it can be used from fsl_lpi2c_edma.c. */
 status_t LPI2C_MasterCheckAndClearError(LPI2C_Type *base, uint32_t status)
 {
     status_t result = kStatus_Success;
@@ -336,6 +311,7 @@ static status_t LPI2C_MasterWaitForTxReady(LPI2C_Type *base)
  * @retval #kStatus_Success
  * @retval #kStatus_LPI2C_Busy
  */
+/* Not static so it can be used from fsl_lpi2c_edma.c. */
 status_t LPI2C_CheckForBusyBus(LPI2C_Type *base)
 {
     uint32_t status = LPI2C_MasterGetStatusFlags(base);
@@ -347,23 +323,63 @@ status_t LPI2C_CheckForBusyBus(LPI2C_Type *base)
     return kStatus_Success;
 }
 
+/*!
+ * brief Provides a default configuration for the LPI2C master peripheral.
+ *
+ * This function provides the following default configuration for the LPI2C master peripheral:
+ * code
+ *  masterConfig->enableMaster            = true;
+ *  masterConfig->debugEnable             = false;
+ *  masterConfig->ignoreAck               = false;
+ *  masterConfig->pinConfig               = kLPI2C_2PinOpenDrain;
+ *  masterConfig->baudRate_Hz             = 100000U;
+ *  masterConfig->busIdleTimeout_ns       = 0;
+ *  masterConfig->pinLowTimeout_ns        = 0;
+ *  masterConfig->sdaGlitchFilterWidth_ns = 0;
+ *  masterConfig->sclGlitchFilterWidth_ns = 0;
+ *  masterConfig->hostRequest.enable      = false;
+ *  masterConfig->hostRequest.source      = kLPI2C_HostRequestExternalPin;
+ *  masterConfig->hostRequest.polarity    = kLPI2C_HostRequestPinActiveHigh;
+ * endcode
+ *
+ * After calling this function, you can override any settings in order to customize the configuration,
+ * prior to initializing the master driver with LPI2C_MasterInit().
+ *
+ * param[out] masterConfig User provided configuration structure for default values. Refer to #lpi2c_master_config_t.
+ */
 void LPI2C_MasterGetDefaultConfig(lpi2c_master_config_t *masterConfig)
 {
-    masterConfig->enableMaster = true;
-    masterConfig->debugEnable = false;
-    masterConfig->enableDoze = true;
-    masterConfig->ignoreAck = false;
-    masterConfig->pinConfig = kLPI2C_2PinOpenDrain;
-    masterConfig->baudRate_Hz = 100000U;
-    masterConfig->busIdleTimeout_ns = 0;
-    masterConfig->pinLowTimeout_ns = 0;
+    /* Initializes the configure structure to zero. */
+    memset(masterConfig, 0, sizeof(*masterConfig));
+
+    masterConfig->enableMaster            = true;
+    masterConfig->debugEnable             = false;
+    masterConfig->enableDoze              = true;
+    masterConfig->ignoreAck               = false;
+    masterConfig->pinConfig               = kLPI2C_2PinOpenDrain;
+    masterConfig->baudRate_Hz             = 100000U;
+    masterConfig->busIdleTimeout_ns       = 0;
+    masterConfig->pinLowTimeout_ns        = 0;
     masterConfig->sdaGlitchFilterWidth_ns = 0;
     masterConfig->sclGlitchFilterWidth_ns = 0;
-    masterConfig->hostRequest.enable = false;
-    masterConfig->hostRequest.source = kLPI2C_HostRequestExternalPin;
-    masterConfig->hostRequest.polarity = kLPI2C_HostRequestPinActiveHigh;
+    masterConfig->hostRequest.enable      = false;
+    masterConfig->hostRequest.source      = kLPI2C_HostRequestExternalPin;
+    masterConfig->hostRequest.polarity    = kLPI2C_HostRequestPinActiveHigh;
 }
 
+/*!
+ * brief Initializes the LPI2C master peripheral.
+ *
+ * This function enables the peripheral clock and initializes the LPI2C master peripheral as described by the user
+ * provided configuration. A software reset is performed prior to configuration.
+ *
+ * param base The LPI2C peripheral base address.
+ * param masterConfig User provided peripheral configuration. Use LPI2C_MasterGetDefaultConfig() to get a set of
+ * defaults
+ *      that you can override.
+ * param sourceClock_Hz Frequency in Hertz of the LPI2C functional clock. Used to calculate the baud rate divisors,
+ *      filter widths, and timeout periods.
+ */
 void LPI2C_MasterInit(LPI2C_Type *base, const lpi2c_master_config_t *masterConfig, uint32_t sourceClock_Hz)
 {
     uint32_t prescaler;
@@ -411,7 +427,7 @@ void LPI2C_MasterInit(LPI2C_Type *base, const lpi2c_master_config_t *masterConfi
 
     /* Configure glitch filters and bus idle and pin low timeouts. */
     prescaler = (base->MCFGR1 & LPI2C_MCFGR1_PRESCALE_MASK) >> LPI2C_MCFGR1_PRESCALE_SHIFT;
-    cfgr2 = base->MCFGR2;
+    cfgr2     = base->MCFGR2;
     if (masterConfig->busIdleTimeout_ns)
     {
         cycles = LPI2C_GetCyclesForWidth(sourceClock_Hz, masterConfig->busIdleTimeout_ns,
@@ -436,7 +452,7 @@ void LPI2C_MasterInit(LPI2C_Type *base, const lpi2c_master_config_t *masterConfi
     base->MCFGR2 = cfgr2;
     if (masterConfig->pinLowTimeout_ns)
     {
-        cycles = LPI2C_GetCyclesForWidth(sourceClock_Hz, masterConfig->pinLowTimeout_ns / 256,
+        cycles       = LPI2C_GetCyclesForWidth(sourceClock_Hz, masterConfig->pinLowTimeout_ns / 256,
                                          (LPI2C_MCFGR2_BUSIDLE_MASK >> LPI2C_MCFGR2_BUSIDLE_SHIFT), prescaler);
         base->MCFGR3 = (base->MCFGR3 & ~LPI2C_MCFGR3_PINLOW_MASK) | LPI2C_MCFGR3_PINLOW(cycles);
     }
@@ -444,6 +460,14 @@ void LPI2C_MasterInit(LPI2C_Type *base, const lpi2c_master_config_t *masterConfi
     LPI2C_MasterEnable(base, masterConfig->enableMaster);
 }
 
+/*!
+ * brief Deinitializes the LPI2C master peripheral.
+ *
+ * This function disables the LPI2C master peripheral and gates the clock. It also performs a software
+ * reset to restore the peripheral to reset conditions.
+ *
+ * param base The LPI2C peripheral base address.
+ */
 void LPI2C_MasterDeinit(LPI2C_Type *base)
 {
     /* Restore to reset state. */
@@ -463,6 +487,12 @@ void LPI2C_MasterDeinit(LPI2C_Type *base)
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }
 
+/*!
+ * brief Configures LPI2C master data match feature.
+ *
+ * param base The LPI2C peripheral base address.
+ * param config Settings for the data match feature.
+ */
 void LPI2C_MasterConfigureDataMatch(LPI2C_Type *base, const lpi2c_data_match_config_t *config)
 {
     /* Disable master mode. */
@@ -471,7 +501,7 @@ void LPI2C_MasterConfigureDataMatch(LPI2C_Type *base, const lpi2c_data_match_con
 
     base->MCFGR1 = (base->MCFGR1 & ~LPI2C_MCFGR1_MATCFG_MASK) | LPI2C_MCFGR1_MATCFG(config->matchMode);
     base->MCFGR0 = (base->MCFGR0 & ~LPI2C_MCFGR0_RDMO_MASK) | LPI2C_MCFGR0_RDMO(config->rxDataMatchOnly);
-    base->MDMR = LPI2C_MDMR_MATCH0(config->match0) | LPI2C_MDMR_MATCH1(config->match1);
+    base->MDMR   = LPI2C_MDMR_MATCH0(config->match0) | LPI2C_MDMR_MATCH1(config->match1);
 
     /* Restore master mode. */
     if (wasEnabled)
@@ -480,12 +510,26 @@ void LPI2C_MasterConfigureDataMatch(LPI2C_Type *base, const lpi2c_data_match_con
     }
 }
 
+/*!
+ * brief Sets the I2C bus frequency for master transactions.
+ *
+ * The LPI2C master is automatically disabled and re-enabled as necessary to configure the baud
+ * rate. Do not call this function during a transfer, or the transfer is aborted.
+ *
+ * note Please note that the second parameter is the clock frequency of LPI2C module, the third
+ * parameter means user configured bus baudrate, this implementation is different from other I2C drivers
+ * which use baudrate configuration as second parameter and source clock frequency as third parameter.
+ *
+ * param base The LPI2C peripheral base address.
+ * param sourceClock_Hz LPI2C functional clock frequency in Hertz.
+ * param baudRate_Hz Requested bus frequency in Hertz.
+ */
 void LPI2C_MasterSetBaudRate(LPI2C_Type *base, uint32_t sourceClock_Hz, uint32_t baudRate_Hz)
 {
-    uint32_t prescale = 0;
-    uint32_t bestPre = 0;
+    uint32_t prescale  = 0;
+    uint32_t bestPre   = 0;
     uint32_t bestClkHi = 0;
-    uint32_t absError = 0;
+    uint32_t absError  = 0;
     uint32_t bestError = 0xffffffffu;
     uint32_t value;
     uint32_t clkHiCycle;
@@ -516,7 +560,7 @@ void LPI2C_MasterSetBaudRate(LPI2C_Type *base, uint32_t sourceClock_Hz, uint32_t
 
             if (absError < bestError)
             {
-                bestPre = prescale;
+                bestPre   = prescale;
                 bestClkHi = clkHiCycle;
                 bestError = absError;
 
@@ -560,6 +604,21 @@ void LPI2C_MasterSetBaudRate(LPI2C_Type *base, uint32_t sourceClock_Hz, uint32_t
     }
 }
 
+/*!
+ * brief Sends a START signal and slave address on the I2C bus.
+ *
+ * This function is used to initiate a new master mode transfer. First, the bus state is checked to ensure
+ * that another master is not occupying the bus. Then a START signal is transmitted, followed by the
+ * 7-bit address specified in the a address parameter. Note that this function does not actually wait
+ * until the START and address are successfully sent on the bus before returning.
+ *
+ * param base The LPI2C peripheral base address.
+ * param address 7-bit slave device address, in bits [6:0].
+ * param dir Master transfer direction, either #kLPI2C_Read or #kLPI2C_Write. This parameter is used to set
+ *      the R/w bit (bit 0) in the transmitted slave address.
+ * retval #kStatus_Success START signal and address were successfully enqueued in the transmit FIFO.
+ * retval #kStatus_LPI2C_Busy Another master is currently utilizing the bus.
+ */
 status_t LPI2C_MasterStart(LPI2C_Type *base, uint8_t address, lpi2c_direction_t dir)
 {
     /* Return an error if the bus is already in use not by us. */
@@ -588,6 +647,19 @@ status_t LPI2C_MasterStart(LPI2C_Type *base, uint8_t address, lpi2c_direction_t
     return kStatus_Success;
 }
 
+/*!
+ * brief Sends a STOP signal on the I2C bus.
+ *
+ * This function does not return until the STOP signal is seen on the bus, or an error occurs.
+ *
+ * param base The LPI2C peripheral base address.
+ * retval #kStatus_Success The STOP signal was successfully sent on the bus and the transaction terminated.
+ * retval #kStatus_LPI2C_Busy Another master is currently utilizing the bus.
+ * retval #kStatus_LPI2C_Nak The slave device sent a NAK in response to a byte.
+ * retval #kStatus_LPI2C_FifoError FIFO under run or overrun.
+ * retval #kStatus_LPI2C_ArbitrationLost Arbitration lost error.
+ * retval #kStatus_LPI2C_PinLowTimeout SCL or SDA were held low longer than the timeout.
+ */
 status_t LPI2C_MasterStop(LPI2C_Type *base)
 {
     /* Wait until there is room in the fifo. */
@@ -618,7 +690,7 @@ status_t LPI2C_MasterStop(LPI2C_Type *base)
         result = LPI2C_MasterCheckAndClearError(base, status);
 
         /* Check if the stop was sent successfully. */
-        if (status & kLPI2C_MasterStopDetectFlag)
+        if ((status & kLPI2C_MasterStopDetectFlag) && (status & kLPI2C_MasterTxReadyFlag))
         {
             LPI2C_MasterClearStatusFlags(base, kLPI2C_MasterStopDetectFlag);
             break;
@@ -635,6 +707,19 @@ status_t LPI2C_MasterStop(LPI2C_Type *base)
     return result;
 }
 
+/*!
+ * brief Performs a polling receive transfer on the I2C bus.
+ *
+ * param base  The LPI2C peripheral base address.
+ * param rxBuff The pointer to the data to be transferred.
+ * param rxSize The length in bytes of the data to be transferred.
+ * retval #kStatus_Success Data was received successfully.
+ * retval #kStatus_LPI2C_Busy Another master is currently utilizing the bus.
+ * retval #kStatus_LPI2C_Nak The slave device sent a NAK in response to a byte.
+ * retval #kStatus_LPI2C_FifoError FIFO under run or overrun.
+ * retval #kStatus_LPI2C_ArbitrationLost Arbitration lost error.
+ * retval #kStatus_LPI2C_PinLowTimeout SCL or SDA were held low longer than the timeout.
+ */
 status_t LPI2C_MasterReceive(LPI2C_Type *base, void *rxBuff, size_t rxSize)
 {
     status_t result;
@@ -696,9 +781,26 @@ status_t LPI2C_MasterReceive(LPI2C_Type *base, void *rxBuff, size_t rxSize)
     return kStatus_Success;
 }
 
-status_t LPI2C_MasterSend(LPI2C_Type *base, const void *txBuff, size_t txSize)
+/*!
+ * brief Performs a polling send transfer on the I2C bus.
+ *
+ * Sends up to a txSize number of bytes to the previously addressed slave device. The slave may
+ * reply with a NAK to any byte in order to terminate the transfer early. If this happens, this
+ * function returns #kStatus_LPI2C_Nak.
+ *
+ * param base  The LPI2C peripheral base address.
+ * param txBuff The pointer to the data to be transferred.
+ * param txSize The length in bytes of the data to be transferred.
+ * retval #kStatus_Success Data was sent successfully.
+ * retval #kStatus_LPI2C_Busy Another master is currently utilizing the bus.
+ * retval #kStatus_LPI2C_Nak The slave device sent a NAK in response to a byte.
+ * retval #kStatus_LPI2C_FifoError FIFO under run or over run.
+ * retval #kStatus_LPI2C_ArbitrationLost Arbitration lost error.
+ * retval #kStatus_LPI2C_PinLowTimeout SCL or SDA were held low longer than the timeout.
+ */
+status_t LPI2C_MasterSend(LPI2C_Type *base, void *txBuff, size_t txSize)
 {
-    const uint8_t *buf = (const uint8_t *)((const void *)txBuff);
+    uint8_t *buf = (uint8_t *)txBuff;
 
     assert(txBuff);
 
@@ -719,6 +821,21 @@ status_t LPI2C_MasterSend(LPI2C_Type *base, const void *txBuff, size_t txSize)
     return kStatus_Success;
 }
 
+/*!
+ * brief Performs a master polling transfer on the I2C bus.
+ *
+ * note The API does not return until the transfer succeeds or fails due
+ * to error happens during transfer.
+ *
+ * param base The LPI2C peripheral base address.
+ * param transfer Pointer to the transfer structure.
+ * retval #kStatus_Success Data was received successfully.
+ * retval #kStatus_LPI2C_Busy Another master is currently utilizing the bus.
+ * retval #kStatus_LPI2C_Nak The slave device sent a NAK in response to a byte.
+ * retval #kStatus_LPI2C_FifoError FIFO under run or overrun.
+ * retval #kStatus_LPI2C_ArbitrationLost Arbitration lost error.
+ * retval #kStatus_LPI2C_PinLowTimeout SCL or SDA were held low longer than the timeout.
+ */
 status_t LPI2C_MasterTransferBlocking(LPI2C_Type *base, lpi2c_master_transfer_t *transfer)
 {
     status_t result = kStatus_Success;
@@ -754,7 +871,7 @@ status_t LPI2C_MasterTransferBlocking(LPI2C_Type *base, lpi2c_master_transfer_t
         uint32_t subaddressRemaining = transfer->subaddressSize;
         while (subaddressRemaining--)
         {
-            uint8_t subaddressByte = (transfer->subaddress >> (8 * subaddressRemaining)) & 0xff;
+            uint8_t subaddressByte    = (transfer->subaddress >> (8 * subaddressRemaining)) & 0xff;
             commandBuffer[cmdCount++] = subaddressByte;
         }
     }
@@ -813,6 +930,23 @@ status_t LPI2C_MasterTransferBlocking(LPI2C_Type *base, lpi2c_master_transfer_t
     return result;
 }
 
+/*!
+ * brief Creates a new handle for the LPI2C master non-blocking APIs.
+ *
+ * The creation of a handle is for use with the non-blocking APIs. Once a handle
+ * is created, there is not a corresponding destroy handle. If the user wants to
+ * terminate a transfer, the LPI2C_MasterTransferAbort() API shall be called.
+ *
+ *
+ * note The function also enables the NVIC IRQ for the input LPI2C. Need to notice
+ * that on some SoCs the LPI2C IRQ is connected to INTMUX, in this case user needs to
+ * enable the associated INTMUX IRQ in application.
+ *
+ * param base The LPI2C peripheral base address.
+ * param[out] handle Pointer to the LPI2C master driver handle.
+ * param callback User provided pointer to the asynchronous callback function.
+ * param userData User provided pointer to the application callback data.
+ */
 void LPI2C_MasterTransferCreateHandle(LPI2C_Type *base,
                                       lpi2c_master_handle_t *handle,
                                       lpi2c_master_transfer_callback_t callback,
@@ -830,7 +964,7 @@ void LPI2C_MasterTransferCreateHandle(LPI2C_Type *base,
 
     /* Save base and instance. */
     handle->completionCallback = callback;
-    handle->userData = userData;
+    handle->userData           = userData;
 
     /* Save this handle for IRQ use. */
     s_lpi2cMasterHandle[instance] = handle;
@@ -864,7 +998,7 @@ static status_t LPI2C_RunTransferStateMachine(LPI2C_Type *base, lpi2c_master_han
     lpi2c_master_transfer_t *xfer;
     size_t txCount;
     size_t rxCount;
-    size_t txFifoSize = FSL_FEATURE_LPI2C_FIFO_SIZEn(base);
+    size_t txFifoSize   = FSL_FEATURE_LPI2C_FIFO_SIZEn(base);
     bool state_complete = false;
 
     /* Set default isDone return value. */
@@ -910,8 +1044,8 @@ static status_t LPI2C_RunTransferStateMachine(LPI2C_Type *base, lpi2c_master_han
                     if (xfer->dataSize)
                     {
                         /* Either a send or receive transfer is next. */
-                        handle->state = kTransferDataState;
-                        handle->buf = (uint8_t *)xfer->data;
+                        handle->state          = kTransferDataState;
+                        handle->buf            = (uint8_t *)xfer->data;
                         handle->remainingBytes = xfer->dataSize;
                         if (xfer->direction == kLPI2C_Read)
                         {
@@ -977,6 +1111,10 @@ static status_t LPI2C_RunTransferStateMachine(LPI2C_Type *base, lpi2c_master_han
                 /* Move to stop when the transfer is done. */
                 if (--handle->remainingBytes == 0)
                 {
+                    if (xfer->direction == kLPI2C_Write)
+                    {
+                        state_complete = true;
+                    }
                     handle->state = kStopState;
                 }
                 break;
@@ -997,7 +1135,7 @@ static status_t LPI2C_RunTransferStateMachine(LPI2C_Type *base, lpi2c_master_han
                 else
                 {
                     /* Caller doesn't want to send a stop, so we're done now. */
-                    *isDone = true;
+                    *isDone        = true;
                     state_complete = true;
                     break;
                 }
@@ -1042,12 +1180,12 @@ static void LPI2C_InitTransferStateMachine(lpi2c_master_handle_t *handle)
             handle->state = kTransferDataState;
         }
 
-        handle->buf = (uint8_t *)xfer->data;
+        handle->buf            = (uint8_t *)xfer->data;
         handle->remainingBytes = xfer->dataSize;
     }
     else
     {
-        uint16_t *cmd = (uint16_t *)&handle->commandBuffer;
+        uint16_t *cmd     = (uint16_t *)&handle->commandBuffer;
         uint32_t cmdCount = 0;
 
         /* Initial direction depends on whether a subaddress was provided, and of course the actual */
@@ -1065,7 +1203,7 @@ static void LPI2C_InitTransferStateMachine(lpi2c_master_handle_t *handle)
             while (subaddressRemaining--)
             {
                 uint8_t subaddressByte = (xfer->subaddress >> (8 * subaddressRemaining)) & 0xff;
-                cmd[cmdCount++] = subaddressByte;
+                cmd[cmdCount++]        = subaddressByte;
             }
         }
 
@@ -1084,12 +1222,22 @@ static void LPI2C_InitTransferStateMachine(lpi2c_master_handle_t *handle)
         }
 
         /* Set up state machine for transferring the commands. */
-        handle->state = kSendCommandState;
+        handle->state          = kSendCommandState;
         handle->remainingBytes = cmdCount;
-        handle->buf = (uint8_t *)&handle->commandBuffer;
+        handle->buf            = (uint8_t *)&handle->commandBuffer;
     }
 }
 
+/*!
+ * brief Performs a non-blocking transaction on the I2C bus.
+ *
+ * param base The LPI2C peripheral base address.
+ * param handle Pointer to the LPI2C master driver handle.
+ * param transfer The pointer to the transfer descriptor.
+ * retval #kStatus_Success The transaction was started successfully.
+ * retval #kStatus_LPI2C_Busy Either another master is currently utilizing the bus, or a non-blocking
+ *      transaction is already in progress.
+ */
 status_t LPI2C_MasterTransferNonBlocking(LPI2C_Type *base,
                                          lpi2c_master_handle_t *handle,
                                          lpi2c_master_transfer_t *transfer)
@@ -1134,6 +1282,14 @@ status_t LPI2C_MasterTransferNonBlocking(LPI2C_Type *base,
     return result;
 }
 
+/*!
+ * brief Returns number of bytes transferred so far.
+ * param base The LPI2C peripheral base address.
+ * param handle Pointer to the LPI2C master driver handle.
+ * param[out] count Number of bytes transferred so far by the non-blocking transaction.
+ * retval #kStatus_Success
+ * retval #kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress.
+ */
 status_t LPI2C_MasterTransferGetCount(LPI2C_Type *base, lpi2c_master_handle_t *handle, size_t *count)
 {
     assert(handle);
@@ -1158,9 +1314,9 @@ status_t LPI2C_MasterTransferGetCount(LPI2C_Type *base, lpi2c_master_handle_t *h
     /* are synchronized with each other during an ongoing transfer. */
     uint32_t irqs = LPI2C_MasterGetEnabledInterrupts(base);
     LPI2C_MasterDisableInterrupts(base, irqs);
-    state = handle->state;
+    state          = handle->state;
     remainingBytes = handle->remainingBytes;
-    dataSize = handle->transfer.dataSize;
+    dataSize       = handle->transfer.dataSize;
     LPI2C_MasterEnableInterrupts(base, irqs);
 
     /* Get transfer count based on current transfer state. */
@@ -1186,6 +1342,17 @@ status_t LPI2C_MasterTransferGetCount(LPI2C_Type *base, lpi2c_master_handle_t *h
     return kStatus_Success;
 }
 
+/*!
+ * brief Terminates a non-blocking LPI2C master transmission early.
+ *
+ * note It is not safe to call this function from an IRQ handler that has a higher priority than the
+ *      LPI2C peripheral's IRQ priority.
+ *
+ * param base The LPI2C peripheral base address.
+ * param handle Pointer to the LPI2C master driver handle.
+ * retval #kStatus_Success A transaction was successfully aborted.
+ * retval #kStatus_LPI2C_Idle There is not a non-blocking transaction currently in progress.
+ */
 void LPI2C_MasterTransferAbort(LPI2C_Type *base, lpi2c_master_handle_t *handle)
 {
     if (handle->state != kIdleState)
@@ -1204,6 +1371,13 @@ void LPI2C_MasterTransferAbort(LPI2C_Type *base, lpi2c_master_handle_t *handle)
     }
 }
 
+/*!
+ * brief Reusable routine to handle master interrupts.
+ * note This function does not need to be called unless you are reimplementing the
+ *  nonblocking API's interrupt handler routines to add special functionality.
+ * param base The LPI2C peripheral base address.
+ * param handle Pointer to the LPI2C master driver handle.
+ */
 void LPI2C_MasterTransferHandleIRQ(LPI2C_Type *base, lpi2c_master_handle_t *handle)
 {
     bool isDone;
@@ -1242,27 +1416,73 @@ void LPI2C_MasterTransferHandleIRQ(LPI2C_Type *base, lpi2c_master_handle_t *hand
     }
 }
 
+/*!
+ * brief Provides a default configuration for the LPI2C slave peripheral.
+ *
+ * This function provides the following default configuration for the LPI2C slave peripheral:
+ * code
+ *  slaveConfig->enableSlave               = true;
+ *  slaveConfig->address0                  = 0U;
+ *  slaveConfig->address1                  = 0U;
+ *  slaveConfig->addressMatchMode          = kLPI2C_MatchAddress0;
+ *  slaveConfig->filterDozeEnable          = true;
+ *  slaveConfig->filterEnable              = true;
+ *  slaveConfig->enableGeneralCall         = false;
+ *  slaveConfig->sclStall.enableAck        = false;
+ *  slaveConfig->sclStall.enableTx         = true;
+ *  slaveConfig->sclStall.enableRx         = true;
+ *  slaveConfig->sclStall.enableAddress    = true;
+ *  slaveConfig->ignoreAck                 = false;
+ *  slaveConfig->enableReceivedAddressRead = false;
+ *  slaveConfig->sdaGlitchFilterWidth_ns   = 0;
+ *  slaveConfig->sclGlitchFilterWidth_ns   = 0;
+ *  slaveConfig->dataValidDelay_ns         = 0;
+ *  slaveConfig->clockHoldTime_ns          = 0;
+ * endcode
+ *
+ * After calling this function, override any settings  to customize the configuration,
+ * prior to initializing the master driver with LPI2C_SlaveInit(). Be sure to override at least the a
+ * address0 member of the configuration structure with the desired slave address.
+ *
+ * param[out] slaveConfig User provided configuration structure that is set to default values. Refer to
+ *      #lpi2c_slave_config_t.
+ */
 void LPI2C_SlaveGetDefaultConfig(lpi2c_slave_config_t *slaveConfig)
 {
-    slaveConfig->enableSlave = true;
-    slaveConfig->address0 = 0U;
-    slaveConfig->address1 = 0U;
-    slaveConfig->addressMatchMode = kLPI2C_MatchAddress0;
-    slaveConfig->filterDozeEnable = true;
-    slaveConfig->filterEnable = true;
-    slaveConfig->enableGeneralCall = false;
-    slaveConfig->sclStall.enableAck = false;
-    slaveConfig->sclStall.enableTx = true;
-    slaveConfig->sclStall.enableRx = true;
-    slaveConfig->sclStall.enableAddress = false;
-    slaveConfig->ignoreAck = false;
+    /* Initializes the configure structure to zero. */
+    memset(slaveConfig, 0, sizeof(*slaveConfig));
+
+    slaveConfig->enableSlave               = true;
+    slaveConfig->address0                  = 0U;
+    slaveConfig->address1                  = 0U;
+    slaveConfig->addressMatchMode          = kLPI2C_MatchAddress0;
+    slaveConfig->filterDozeEnable          = true;
+    slaveConfig->filterEnable              = true;
+    slaveConfig->enableGeneralCall         = false;
+    slaveConfig->sclStall.enableAck        = false;
+    slaveConfig->sclStall.enableTx         = true;
+    slaveConfig->sclStall.enableRx         = true;
+    slaveConfig->sclStall.enableAddress    = false;
+    slaveConfig->ignoreAck                 = false;
     slaveConfig->enableReceivedAddressRead = false;
-    slaveConfig->sdaGlitchFilterWidth_ns = 0; /* TODO determine default width values */
-    slaveConfig->sclGlitchFilterWidth_ns = 0;
-    slaveConfig->dataValidDelay_ns = 0;
-    slaveConfig->clockHoldTime_ns = 0;
+    slaveConfig->sdaGlitchFilterWidth_ns   = 0; /* TODO determine default width values */
+    slaveConfig->sclGlitchFilterWidth_ns   = 0;
+    slaveConfig->dataValidDelay_ns         = 0;
+    slaveConfig->clockHoldTime_ns          = 0;
 }
 
+/*!
+ * brief Initializes the LPI2C slave peripheral.
+ *
+ * This function enables the peripheral clock and initializes the LPI2C slave peripheral as described by the user
+ * provided configuration.
+ *
+ * param base The LPI2C peripheral base address.
+ * param slaveConfig User provided peripheral configuration. Use LPI2C_SlaveGetDefaultConfig() to get a set of defaults
+ *      that you can override.
+ * param sourceClock_Hz Frequency in Hertz of the LPI2C functional clock. Used to calculate the filter widths,
+ *      data valid delay, and clock hold time.
+ */
 void LPI2C_SlaveInit(LPI2C_Type *base, const lpi2c_slave_config_t *slaveConfig, uint32_t sourceClock_Hz)
 {
 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
@@ -1306,6 +1526,14 @@ void LPI2C_SlaveInit(LPI2C_Type *base, const lpi2c_slave_config_t *slaveConfig,
                 LPI2C_SCR_SEN(slaveConfig->enableSlave);
 }
 
+/*!
+ * brief Deinitializes the LPI2C slave peripheral.
+ *
+ * This function disables the LPI2C slave peripheral and gates the clock. It also performs a software
+ * reset to restore the peripheral to reset conditions.
+ *
+ * param base The LPI2C peripheral base address.
+ */
 void LPI2C_SlaveDeinit(LPI2C_Type *base)
 {
     LPI2C_SlaveReset(base);
@@ -1360,9 +1588,18 @@ static status_t LPI2C_SlaveCheckAndClearError(LPI2C_Type *base, uint32_t flags)
     return result;
 }
 
-status_t LPI2C_SlaveSend(LPI2C_Type *base, const void *txBuff, size_t txSize, size_t *actualTxSize)
+/*!
+ * brief Performs a polling send transfer on the I2C bus.
+ *
+ * param base  The LPI2C peripheral base address.
+ * param txBuff The pointer to the data to be transferred.
+ * param txSize The length in bytes of the data to be transferred.
+ * param[out] actualTxSize
+ * return Error or success status returned by API.
+ */
+status_t LPI2C_SlaveSend(LPI2C_Type *base, void *txBuff, size_t txSize, size_t *actualTxSize)
 {
-    const uint8_t *buf = (const uint8_t *)((const void *)txBuff);
+    uint8_t *buf     = (uint8_t *)txBuff;
     size_t remaining = txSize;
 
     assert(txBuff);
@@ -1371,6 +1608,9 @@ status_t LPI2C_SlaveSend(LPI2C_Type *base, const void *txBuff, size_t txSize, si
     uint32_t waitTimes = LPI2C_WAIT_TIMEOUT;
 #endif
 
+    /* Clear stop flag. */
+    LPI2C_SlaveClearStatusFlags(base, kLPI2C_SlaveStopDetectFlag | kLPI2C_SlaveRepeatedStartDetectFlag);
+
     while (remaining)
     {
         uint32_t flags;
@@ -1380,7 +1620,7 @@ status_t LPI2C_SlaveSend(LPI2C_Type *base, const void *txBuff, size_t txSize, si
         do
         {
             /* Check for errors */
-            flags = LPI2C_SlaveGetStatusFlags(base);
+            flags  = LPI2C_SlaveGetStatusFlags(base);
             result = LPI2C_SlaveCheckAndClearError(base, flags);
             if (result)
             {
@@ -1410,8 +1650,8 @@ status_t LPI2C_SlaveSend(LPI2C_Type *base, const void *txBuff, size_t txSize, si
             --remaining;
         }
 
-        /* Exit loop if we see a stop or restart */
-        if (flags & (kLPI2C_SlaveStopDetectFlag | kLPI2C_SlaveRepeatedStartDetectFlag))
+        /* Exit loop if we see a stop or restart in transfer*/
+        if ((flags & (kLPI2C_SlaveStopDetectFlag | kLPI2C_SlaveRepeatedStartDetectFlag)) && (remaining != 0U))
         {
             LPI2C_SlaveClearStatusFlags(base, kLPI2C_SlaveStopDetectFlag | kLPI2C_SlaveRepeatedStartDetectFlag);
             break;
@@ -1426,9 +1666,18 @@ status_t LPI2C_SlaveSend(LPI2C_Type *base, const void *txBuff, size_t txSize, si
     return kStatus_Success;
 }
 
+/*!
+ * brief Performs a polling receive transfer on the I2C bus.
+ *
+ * param base  The LPI2C peripheral base address.
+ * param rxBuff The pointer to the data to be transferred.
+ * param rxSize The length in bytes of the data to be transferred.
+ * param[out] actualRxSize
+ * return Error or success status returned by API.
+ */
 status_t LPI2C_SlaveReceive(LPI2C_Type *base, void *rxBuff, size_t rxSize, size_t *actualRxSize)
 {
-    uint8_t *buf = (uint8_t *)rxBuff;
+    uint8_t *buf     = (uint8_t *)rxBuff;
     size_t remaining = rxSize;
 
     assert(rxBuff);
@@ -1437,6 +1686,9 @@ status_t LPI2C_SlaveReceive(LPI2C_Type *base, void *rxBuff, size_t rxSize, size_
     uint32_t waitTimes = LPI2C_WAIT_TIMEOUT;
 #endif
 
+    /* Clear stop flag. */
+    LPI2C_SlaveClearStatusFlags(base, kLPI2C_SlaveStopDetectFlag | kLPI2C_SlaveRepeatedStartDetectFlag);
+
     while (remaining)
     {
         uint32_t flags;
@@ -1446,7 +1698,7 @@ status_t LPI2C_SlaveReceive(LPI2C_Type *base, void *rxBuff, size_t rxSize, size_
         do
         {
             /* Check for errors */
-            flags = LPI2C_SlaveGetStatusFlags(base);
+            flags  = LPI2C_SlaveGetStatusFlags(base);
             result = LPI2C_SlaveCheckAndClearError(base, flags);
             if (result)
             {
@@ -1477,7 +1729,7 @@ status_t LPI2C_SlaveReceive(LPI2C_Type *base, void *rxBuff, size_t rxSize, size_
         }
 
         /* Exit loop if we see a stop or restart */
-        if (flags & (kLPI2C_SlaveStopDetectFlag | kLPI2C_SlaveRepeatedStartDetectFlag))
+        if ((flags & (kLPI2C_SlaveStopDetectFlag | kLPI2C_SlaveRepeatedStartDetectFlag)) && (remaining != 0U))
         {
             LPI2C_SlaveClearStatusFlags(base, kLPI2C_SlaveStopDetectFlag | kLPI2C_SlaveRepeatedStartDetectFlag);
             break;
@@ -1492,6 +1744,22 @@ status_t LPI2C_SlaveReceive(LPI2C_Type *base, void *rxBuff, size_t rxSize, size_
     return kStatus_Success;
 }
 
+/*!
+ * brief Creates a new handle for the LPI2C slave non-blocking APIs.
+ *
+ * The creation of a handle is for use with the non-blocking APIs. Once a handle
+ * is created, there is not a corresponding destroy handle. If the user wants to
+ * terminate a transfer, the LPI2C_SlaveTransferAbort() API shall be called.
+ *
+ * note The function also enables the NVIC IRQ for the input LPI2C. Need to notice
+ * that on some SoCs the LPI2C IRQ is connected to INTMUX, in this case user needs to
+ * enable the associated INTMUX IRQ in application.
+
+ * param base The LPI2C peripheral base address.
+ * param[out] handle Pointer to the LPI2C slave driver handle.
+ * param callback User provided pointer to the asynchronous callback function.
+ * param userData User provided pointer to the application callback data.
+ */
 void LPI2C_SlaveTransferCreateHandle(LPI2C_Type *base,
                                      lpi2c_slave_handle_t *handle,
                                      lpi2c_slave_transfer_callback_t callback,
@@ -1525,6 +1793,30 @@ void LPI2C_SlaveTransferCreateHandle(LPI2C_Type *base,
     base->STAR = LPI2C_STAR_TXNACK_MASK;
 }
 
+/*!
+ * brief Starts accepting slave transfers.
+ *
+ * Call this API after calling I2C_SlaveInit() and LPI2C_SlaveTransferCreateHandle() to start processing
+ * transactions driven by an I2C master. The slave monitors the I2C bus and pass events to the
+ * callback that was passed into the call to LPI2C_SlaveTransferCreateHandle(). The callback is always invoked
+ * from the interrupt context.
+ *
+ * The set of events received by the callback is customizable. To do so, set the a eventMask parameter to
+ * the OR'd combination of #lpi2c_slave_transfer_event_t enumerators for the events you wish to receive.
+ * The #kLPI2C_SlaveTransmitEvent and #kLPI2C_SlaveReceiveEvent events are always enabled and do not need
+ * to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and
+ * receive events that are always enabled. In addition, the #kLPI2C_SlaveAllEvents constant is provided as
+ * a convenient way to enable all events.
+ *
+ * param base The LPI2C peripheral base address.
+ * param handle Pointer to #lpi2c_slave_handle_t structure which stores the transfer state.
+ * param eventMask Bit mask formed by OR'ing together #lpi2c_slave_transfer_event_t enumerators to specify
+ *      which events to send to the callback. Other accepted values are 0 to get a default set of
+ *      only the transmit and receive events, and #kLPI2C_SlaveAllEvents to enable all events.
+ *
+ * retval #kStatus_Success Slave transfers were successfully started.
+ * retval #kStatus_LPI2C_Busy Slave transfers have already been started on this handle.
+ */
 status_t LPI2C_SlaveTransferNonBlocking(LPI2C_Type *base, lpi2c_slave_handle_t *handle, uint32_t eventMask)
 {
     uint32_t status;
@@ -1568,6 +1860,15 @@ status_t LPI2C_SlaveTransferNonBlocking(LPI2C_Type *base, lpi2c_slave_handle_t *
     return kStatus_Success;
 }
 
+/*!
+ * brief Gets the slave transfer status during a non-blocking transfer.
+ * param base The LPI2C peripheral base address.
+ * param handle Pointer to i2c_slave_handle_t structure.
+ * param[out] count Pointer to a value to hold the number of bytes transferred. May be NULL if the count is not
+ *      required.
+ * retval #kStatus_Success
+ * retval #kStatus_NoTransferInProgress
+ */
 status_t LPI2C_SlaveTransferGetCount(LPI2C_Type *base, lpi2c_slave_handle_t *handle, size_t *count)
 {
     assert(handle);
@@ -1590,6 +1891,14 @@ status_t LPI2C_SlaveTransferGetCount(LPI2C_Type *base, lpi2c_slave_handle_t *han
     return kStatus_Success;
 }
 
+/*!
+ * brief Aborts the slave non-blocking transfers.
+ * note This API could be called at any time to stop slave for handling the bus events.
+ * param base The LPI2C peripheral base address.
+ * param handle Pointer to #lpi2c_slave_handle_t structure which stores the transfer state.
+ * retval #kStatus_Success
+ * retval #kStatus_LPI2C_Idle
+ */
 void LPI2C_SlaveTransferAbort(LPI2C_Type *base, lpi2c_slave_handle_t *handle)
 {
     assert(handle);
@@ -1611,6 +1920,13 @@ void LPI2C_SlaveTransferAbort(LPI2C_Type *base, lpi2c_slave_handle_t *handle)
     }
 }
 
+/*!
+ * brief Reusable routine to handle slave interrupts.
+ * note This function does not need to be called unless you are reimplementing the
+ *  non blocking API's interrupt handler routines to add special functionality.
+ * param base The LPI2C peripheral base address.
+ * param handle Pointer to #lpi2c_slave_handle_t structure which stores the transfer state.
+ */
 void LPI2C_SlaveTransferHandleIRQ(LPI2C_Type *base, lpi2c_slave_handle_t *handle)
 {
     uint32_t flags;
@@ -1629,7 +1945,7 @@ void LPI2C_SlaveTransferHandleIRQ(LPI2C_Type *base, lpi2c_slave_handle_t *handle
 
     if (flags & (kLPI2C_SlaveBitErrFlag | kLPI2C_SlaveFifoErrFlag))
     {
-        xfer->event = kLPI2C_SlaveCompletionEvent;
+        xfer->event            = kLPI2C_SlaveCompletionEvent;
         xfer->completionStatus = LPI2C_SlaveCheckAndClearError(base, flags);
 
         if ((handle->eventMask & kLPI2C_SlaveCompletionEvent) && (handle->callback))
@@ -1642,7 +1958,7 @@ void LPI2C_SlaveTransferHandleIRQ(LPI2C_Type *base, lpi2c_slave_handle_t *handle
     {
         xfer->event = (flags & kLPI2C_SlaveRepeatedStartDetectFlag) ? kLPI2C_SlaveRepeatedStartEvent :
                                                                       kLPI2C_SlaveCompletionEvent;
-        xfer->receivedAddress = 0;
+        xfer->receivedAddress  = 0;
         xfer->completionStatus = kStatus_Success;
         xfer->transferredCount = handle->transferredCount;
 
@@ -1676,9 +1992,11 @@ void LPI2C_SlaveTransferHandleIRQ(LPI2C_Type *base, lpi2c_slave_handle_t *handle
     }
     if (flags & kLPI2C_SlaveAddressValidFlag)
     {
-        xfer->event = kLPI2C_SlaveAddressMatchEvent;
+        xfer->event           = kLPI2C_SlaveAddressMatchEvent;
         xfer->receivedAddress = base->SASR & LPI2C_SASR_RADDR_MASK;
 
+        /* Update handle status to busy because slave is addressed. */
+        handle->isBusy = true;
         if ((handle->eventMask & kLPI2C_SlaveAddressMatchEvent) && (handle->callback))
         {
             handle->callback(base, xfer, handle->userData);
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_lpi2c.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_lpi2c.h
index 1706a548ef7..41f83369b79 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_lpi2c.h
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_lpi2c.h
@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
+ * Copyright 2016-2019 NXP
  * All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 #ifndef _FSL_LPI2C_H_
 #define _FSL_LPI2C_H_
@@ -49,8 +23,8 @@
 
 /*! @name Driver version */
 /*@{*/
-/*! @brief LPI2C driver version 2.1.5. */
-#define FSL_LPI2C_DRIVER_VERSION (MAKE_VERSION(2, 1, 5))
+/*! @brief LPI2C driver version 2.1.9. */
+#define FSL_LPI2C_DRIVER_VERSION (MAKE_VERSION(2, 1, 9))
 /*@}*/
 
 /*! @brief Timeout times for waiting flag. */
@@ -63,16 +37,16 @@ enum _lpi2c_status
 {
     kStatus_LPI2C_Busy = MAKE_STATUS(kStatusGroup_LPI2C, 0), /*!< The master is already performing a transfer. */
     kStatus_LPI2C_Idle = MAKE_STATUS(kStatusGroup_LPI2C, 1), /*!< The slave driver is idle. */
-    kStatus_LPI2C_Nak = MAKE_STATUS(kStatusGroup_LPI2C, 2),  /*!< The slave device sent a NAK in response to a byte. */
-    kStatus_LPI2C_FifoError = MAKE_STATUS(kStatusGroup_LPI2C, 3),       /*!< FIFO under run or overrun. */
-    kStatus_LPI2C_BitError = MAKE_STATUS(kStatusGroup_LPI2C, 4),        /*!< Transferred bit was not seen on the bus. */
+    kStatus_LPI2C_Nak  = MAKE_STATUS(kStatusGroup_LPI2C, 2), /*!< The slave device sent a NAK in response to a byte. */
+    kStatus_LPI2C_FifoError       = MAKE_STATUS(kStatusGroup_LPI2C, 3), /*!< FIFO under run or overrun. */
+    kStatus_LPI2C_BitError        = MAKE_STATUS(kStatusGroup_LPI2C, 4), /*!< Transferred bit was not seen on the bus. */
     kStatus_LPI2C_ArbitrationLost = MAKE_STATUS(kStatusGroup_LPI2C, 5), /*!< Arbitration lost error. */
     kStatus_LPI2C_PinLowTimeout =
         MAKE_STATUS(kStatusGroup_LPI2C, 6), /*!< SCL or SDA were held low longer than the timeout. */
     kStatus_LPI2C_NoTransferInProgress =
         MAKE_STATUS(kStatusGroup_LPI2C, 7), /*!< Attempt to abort a transfer when one is not in progress. */
     kStatus_LPI2C_DmaRequestFail = MAKE_STATUS(kStatusGroup_LPI2C, 8), /*!< DMA request failed. */
-    kStatus_LPI2C_Timeout = MAKE_STATUS(kStatusGroup_LPI2C, 9),        /*!< Timeout poling status flags. */
+    kStatus_LPI2C_Timeout        = MAKE_STATUS(kStatusGroup_LPI2C, 9), /*!< Timeout poling status flags. */
 };
 
 /*! @} */
@@ -101,33 +75,33 @@ enum _lpi2c_status
  */
 enum _lpi2c_master_flags
 {
-    kLPI2C_MasterTxReadyFlag = LPI2C_MSR_TDF_MASK,         /*!< Transmit data flag */
-    kLPI2C_MasterRxReadyFlag = LPI2C_MSR_RDF_MASK,         /*!< Receive data flag */
-    kLPI2C_MasterEndOfPacketFlag = LPI2C_MSR_EPF_MASK,     /*!< End Packet flag */
-    kLPI2C_MasterStopDetectFlag = LPI2C_MSR_SDF_MASK,      /*!< Stop detect flag */
-    kLPI2C_MasterNackDetectFlag = LPI2C_MSR_NDF_MASK,      /*!< NACK detect flag */
-    kLPI2C_MasterArbitrationLostFlag = LPI2C_MSR_ALF_MASK, /*!< Arbitration lost flag */
-    kLPI2C_MasterFifoErrFlag = LPI2C_MSR_FEF_MASK,         /*!< FIFO error flag */
-    kLPI2C_MasterPinLowTimeoutFlag = LPI2C_MSR_PLTF_MASK,  /*!< Pin low timeout flag */
-    kLPI2C_MasterDataMatchFlag = LPI2C_MSR_DMF_MASK,       /*!< Data match flag */
-    kLPI2C_MasterBusyFlag = LPI2C_MSR_MBF_MASK,            /*!< Master busy flag */
-    kLPI2C_MasterBusBusyFlag = LPI2C_MSR_BBF_MASK          /*!< Bus busy flag */
+    kLPI2C_MasterTxReadyFlag         = LPI2C_MSR_TDF_MASK,  /*!< Transmit data flag */
+    kLPI2C_MasterRxReadyFlag         = LPI2C_MSR_RDF_MASK,  /*!< Receive data flag */
+    kLPI2C_MasterEndOfPacketFlag     = LPI2C_MSR_EPF_MASK,  /*!< End Packet flag */
+    kLPI2C_MasterStopDetectFlag      = LPI2C_MSR_SDF_MASK,  /*!< Stop detect flag */
+    kLPI2C_MasterNackDetectFlag      = LPI2C_MSR_NDF_MASK,  /*!< NACK detect flag */
+    kLPI2C_MasterArbitrationLostFlag = LPI2C_MSR_ALF_MASK,  /*!< Arbitration lost flag */
+    kLPI2C_MasterFifoErrFlag         = LPI2C_MSR_FEF_MASK,  /*!< FIFO error flag */
+    kLPI2C_MasterPinLowTimeoutFlag   = LPI2C_MSR_PLTF_MASK, /*!< Pin low timeout flag */
+    kLPI2C_MasterDataMatchFlag       = LPI2C_MSR_DMF_MASK,  /*!< Data match flag */
+    kLPI2C_MasterBusyFlag            = LPI2C_MSR_MBF_MASK,  /*!< Master busy flag */
+    kLPI2C_MasterBusBusyFlag         = LPI2C_MSR_BBF_MASK   /*!< Bus busy flag */
 };
 
 /*! @brief Direction of master and slave transfers. */
 typedef enum _lpi2c_direction
 {
     kLPI2C_Write = 0U, /*!< Master transmit. */
-    kLPI2C_Read = 1U   /*!< Master receive. */
+    kLPI2C_Read  = 1U  /*!< Master receive. */
 } lpi2c_direction_t;
 
 /*! @brief LPI2C pin configuration. */
 typedef enum _lpi2c_master_pin_config
 {
-    kLPI2C_2PinOpenDrain = 0x0U,  /*!< LPI2C Configured for 2-pin open drain mode */
+    kLPI2C_2PinOpenDrain  = 0x0U, /*!< LPI2C Configured for 2-pin open drain mode */
     kLPI2C_2PinOutputOnly = 0x1U, /*!< LPI2C Configured for 2-pin output only mode (ultra-fast mode) */
-    kLPI2C_2PinPushPull = 0x2U,   /*!< LPI2C Configured for 2-pin push-pull mode */
-    kLPI2C_4PinPushPull = 0x3U,   /*!< LPI2C Configured for 4-pin push-pull mode */
+    kLPI2C_2PinPushPull   = 0x2U, /*!< LPI2C Configured for 2-pin push-pull mode */
+    kLPI2C_4PinPushPull   = 0x3U, /*!< LPI2C Configured for 4-pin push-pull mode */
     kLPI2C_2PinOpenDrainWithSeparateSlave =
         0x4U, /*!< LPI2C Configured for 2-pin open drain mode with separate LPI2C slave */
     kLPI2C_2PinOutputOnlyWithSeparateSlave =
@@ -140,15 +114,15 @@ typedef enum _lpi2c_master_pin_config
 /*! @brief LPI2C master host request selection. */
 typedef enum _lpi2c_host_request_source
 {
-    kLPI2C_HostRequestExternalPin = 0x0U,  /*!< Select the LPI2C_HREQ pin as the host request input */
+    kLPI2C_HostRequestExternalPin  = 0x0U, /*!< Select the LPI2C_HREQ pin as the host request input */
     kLPI2C_HostRequestInputTrigger = 0x1U, /*!< Select the input trigger as the host request input */
 } lpi2c_host_request_source_t;
 
 /*! @brief LPI2C master host request pin polarity configuration. */
 typedef enum _lpi2c_host_request_polarity
 {
-    kLPI2C_HostRequestPinActiveLow = 0x0U, /*!< Configure the LPI2C_HREQ pin active low */
-    kLPI2C_HostRequestPinActiveHigh = 0x1U /*!< Configure the LPI2C_HREQ pin active high */
+    kLPI2C_HostRequestPinActiveLow  = 0x0U, /*!< Configure the LPI2C_HREQ pin active low */
+    kLPI2C_HostRequestPinActiveHigh = 0x1U  /*!< Configure the LPI2C_HREQ pin active high */
 } lpi2c_host_request_polarity_t;
 
 /*!
@@ -183,7 +157,7 @@ typedef struct _lpi2c_master_config
 /*! @brief LPI2C master data match configuration modes. */
 typedef enum _lpi2c_data_match_config_mode
 {
-    kLPI2C_MatchDisabled = 0x0U,       /*!< LPI2C Match Disabled */
+    kLPI2C_MatchDisabled       = 0x0U, /*!< LPI2C Match Disabled */
     kLPI2C_1stWordEqualsM0OrM1 = 0x2U, /*!< LPI2C Match Enabled and 1st data word equals MATCH0 OR MATCH1 */
     kLPI2C_AnyWordEqualsM0OrM1 = 0x3U, /*!< LPI2C Match Enabled and any data word equals MATCH0 OR MATCH1 */
     kLPI2C_1stWordEqualsM0And2ndWordEqualsM1 =
@@ -232,10 +206,10 @@ typedef void (*lpi2c_master_transfer_callback_t)(LPI2C_Type *base,
  */
 enum _lpi2c_master_transfer_flags
 {
-    kLPI2C_TransferDefaultFlag = 0x00U,       /*!< Transfer starts with a start signal, stops with a stop signal. */
-    kLPI2C_TransferNoStartFlag = 0x01U,       /*!< Don't send a start condition, address, and sub address */
+    kLPI2C_TransferDefaultFlag       = 0x00U, /*!< Transfer starts with a start signal, stops with a stop signal. */
+    kLPI2C_TransferNoStartFlag       = 0x01U, /*!< Don't send a start condition, address, and sub address */
     kLPI2C_TransferRepeatedStartFlag = 0x02U, /*!< Send a repeated start condition */
-    kLPI2C_TransferNoStopFlag = 0x04U,        /*!< Don't send a stop condition. */
+    kLPI2C_TransferNoStopFlag        = 0x04U, /*!< Don't send a stop condition. */
 };
 
 /*!
@@ -245,10 +219,9 @@ enum _lpi2c_master_transfer_flags
  */
 struct _lpi2c_master_transfer
 {
-    uint32_t
-        flags; /*!< Bit mask of options for the transfer. See enumeration #_lpi2c_master_transfer_flags for available
-                  options. Set to 0 or #kLPI2C_TransferDefaultFlag for normal transfers. */
-    uint16_t slaveAddress;       /*!< The 7-bit slave address. */
+    uint32_t flags;        /*!< Bit mask of options for the transfer. See enumeration #_lpi2c_master_transfer_flags for
+                              available options. Set to 0 or #kLPI2C_TransferDefaultFlag for normal transfers. */
+    uint16_t slaveAddress; /*!< The 7-bit slave address. */
     lpi2c_direction_t direction; /*!< Either #kLPI2C_Read or #kLPI2C_Write. */
     uint32_t subaddress;         /*!< Sub address. Transferred MSB first. */
     size_t subaddressSize;       /*!< Length of sub address to send in bytes. Maximum size is 4 bytes. */
@@ -294,26 +267,26 @@ struct _lpi2c_master_handle
  */
 enum _lpi2c_slave_flags
 {
-    kLPI2C_SlaveTxReadyFlag = LPI2C_SSR_TDF_MASK,             /*!< Transmit data flag */
-    kLPI2C_SlaveRxReadyFlag = LPI2C_SSR_RDF_MASK,             /*!< Receive data flag */
-    kLPI2C_SlaveAddressValidFlag = LPI2C_SSR_AVF_MASK,        /*!< Address valid flag */
-    kLPI2C_SlaveTransmitAckFlag = LPI2C_SSR_TAF_MASK,         /*!< Transmit ACK flag */
-    kLPI2C_SlaveRepeatedStartDetectFlag = LPI2C_SSR_RSF_MASK, /*!< Repeated start detect flag */
-    kLPI2C_SlaveStopDetectFlag = LPI2C_SSR_SDF_MASK,          /*!< Stop detect flag */
-    kLPI2C_SlaveBitErrFlag = LPI2C_SSR_BEF_MASK,              /*!< Bit error flag */
-    kLPI2C_SlaveFifoErrFlag = LPI2C_SSR_FEF_MASK,             /*!< FIFO error flag */
-    kLPI2C_SlaveAddressMatch0Flag = LPI2C_SSR_AM0F_MASK,      /*!< Address match 0 flag */
-    kLPI2C_SlaveAddressMatch1Flag = LPI2C_SSR_AM1F_MASK,      /*!< Address match 1 flag */
-    kLPI2C_SlaveGeneralCallFlag = LPI2C_SSR_GCF_MASK,         /*!< General call flag */
-    kLPI2C_SlaveBusyFlag = LPI2C_SSR_SBF_MASK,                /*!< Master busy flag */
-    kLPI2C_SlaveBusBusyFlag = LPI2C_SSR_BBF_MASK,             /*!< Bus busy flag */
+    kLPI2C_SlaveTxReadyFlag             = LPI2C_SSR_TDF_MASK,  /*!< Transmit data flag */
+    kLPI2C_SlaveRxReadyFlag             = LPI2C_SSR_RDF_MASK,  /*!< Receive data flag */
+    kLPI2C_SlaveAddressValidFlag        = LPI2C_SSR_AVF_MASK,  /*!< Address valid flag */
+    kLPI2C_SlaveTransmitAckFlag         = LPI2C_SSR_TAF_MASK,  /*!< Transmit ACK flag */
+    kLPI2C_SlaveRepeatedStartDetectFlag = LPI2C_SSR_RSF_MASK,  /*!< Repeated start detect flag */
+    kLPI2C_SlaveStopDetectFlag          = LPI2C_SSR_SDF_MASK,  /*!< Stop detect flag */
+    kLPI2C_SlaveBitErrFlag              = LPI2C_SSR_BEF_MASK,  /*!< Bit error flag */
+    kLPI2C_SlaveFifoErrFlag             = LPI2C_SSR_FEF_MASK,  /*!< FIFO error flag */
+    kLPI2C_SlaveAddressMatch0Flag       = LPI2C_SSR_AM0F_MASK, /*!< Address match 0 flag */
+    kLPI2C_SlaveAddressMatch1Flag       = LPI2C_SSR_AM1F_MASK, /*!< Address match 1 flag */
+    kLPI2C_SlaveGeneralCallFlag         = LPI2C_SSR_GCF_MASK,  /*!< General call flag */
+    kLPI2C_SlaveBusyFlag                = LPI2C_SSR_SBF_MASK,  /*!< Master busy flag */
+    kLPI2C_SlaveBusBusyFlag             = LPI2C_SSR_BBF_MASK,  /*!< Bus busy flag */
 };
 
 /*! @brief LPI2C slave address match options. */
 typedef enum _lpi2c_slave_address_match
 {
-    kLPI2C_MatchAddress0 = 0U,                /*!< Match only address 0. */
-    kLPI2C_MatchAddress0OrAddress1 = 2U,      /*!< Match either address 0 or address 1. */
+    kLPI2C_MatchAddress0                = 0U, /*!< Match only address 0. */
+    kLPI2C_MatchAddress0OrAddress1      = 2U, /*!< Match either address 0 or address 1. */
     kLPI2C_MatchAddress0ThroughAddress1 = 6U, /*!< Match a range of slave addresses from address 0 through address 1. */
 } lpi2c_slave_address_match_t;
 
@@ -370,13 +343,13 @@ typedef struct _lpi2c_slave_config
 typedef enum _lpi2c_slave_transfer_event
 {
     kLPI2C_SlaveAddressMatchEvent = 0x01U,  /*!< Received the slave address after a start or repeated start. */
-    kLPI2C_SlaveTransmitEvent = 0x02U,      /*!< Callback is requested to provide data to transmit
+    kLPI2C_SlaveTransmitEvent     = 0x02U,  /*!< Callback is requested to provide data to transmit
                                                  (slave-transmitter role). */
     kLPI2C_SlaveReceiveEvent = 0x04U,       /*!< Callback is requested to provide a buffer in which to place received
                                                   data (slave-receiver role). */
-    kLPI2C_SlaveTransmitAckEvent = 0x08U,   /*!< Callback needs to either transmit an ACK or NACK. */
+    kLPI2C_SlaveTransmitAckEvent   = 0x08U, /*!< Callback needs to either transmit an ACK or NACK. */
     kLPI2C_SlaveRepeatedStartEvent = 0x10U, /*!< A repeated start was detected. */
-    kLPI2C_SlaveCompletionEvent = 0x20U,    /*!< A stop was detected, completing the transfer. */
+    kLPI2C_SlaveCompletionEvent    = 0x20U, /*!< A stop was detected, completing the transfer. */
 
     /*! Bit mask of all available events. */
     kLPI2C_SlaveAllEvents = kLPI2C_SlaveAddressMatchEvent | kLPI2C_SlaveTransmitEvent | kLPI2C_SlaveReceiveEvent |
@@ -485,8 +458,8 @@ void LPI2C_MasterGetDefaultConfig(lpi2c_master_config_t *masterConfig);
 void LPI2C_MasterInit(LPI2C_Type *base, const lpi2c_master_config_t *masterConfig, uint32_t sourceClock_Hz);
 
 /*!
-* @brief Deinitializes the LPI2C master peripheral.
-*
+ * @brief Deinitializes the LPI2C master peripheral.
+ *
  * This function disables the LPI2C master peripheral and gates the clock. It also performs a software
  * reset to restore the peripheral to reset conditions.
  *
@@ -797,7 +770,7 @@ static inline status_t LPI2C_MasterRepeatedStart(LPI2C_Type *base, uint8_t addre
  * @retval #kStatus_LPI2C_ArbitrationLost Arbitration lost error.
  * @retval #kStatus_LPI2C_PinLowTimeout SCL or SDA were held low longer than the timeout.
  */
-status_t LPI2C_MasterSend(LPI2C_Type *base, const void *txBuff, size_t txSize);
+status_t LPI2C_MasterSend(LPI2C_Type *base, void *txBuff, size_t txSize);
 
 /*!
  * @brief Performs a polling receive transfer on the I2C bus.
@@ -984,8 +957,8 @@ void LPI2C_SlaveGetDefaultConfig(lpi2c_slave_config_t *slaveConfig);
 void LPI2C_SlaveInit(LPI2C_Type *base, const lpi2c_slave_config_t *slaveConfig, uint32_t sourceClock_Hz);
 
 /*!
-* @brief Deinitializes the LPI2C slave peripheral.
-*
+ * @brief Deinitializes the LPI2C slave peripheral.
+ *
  * This function disables the LPI2C slave peripheral and gates the clock. It also performs a software
  * reset to restore the peripheral to reset conditions.
  *
@@ -1182,7 +1155,7 @@ static inline uint32_t LPI2C_SlaveGetReceivedAddress(LPI2C_Type *base)
  * @param[out] actualTxSize
  * @return Error or success status returned by API.
  */
-status_t LPI2C_SlaveSend(LPI2C_Type *base, const void *txBuff, size_t txSize, size_t *actualTxSize);
+status_t LPI2C_SlaveSend(LPI2C_Type *base, void *txBuff, size_t txSize, size_t *actualTxSize);
 
 /*!
  * @brief Performs a polling receive transfer on the I2C bus.
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_lpi2c_edma.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_lpi2c_edma.c
index b79dea63a1c..e8de4a1c897 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_lpi2c_edma.c
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_lpi2c_edma.c
@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
  * All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include "fsl_lpi2c_edma.h"
@@ -83,8 +57,8 @@ enum _lpi2c_master_fifo_cmd
 {
     kTxDataCmd = LPI2C_MTDR_CMD(0x0U), /*!< Transmit DATA[7:0] */
     kRxDataCmd = LPI2C_MTDR_CMD(0X1U), /*!< Receive (DATA[7:0] + 1) bytes */
-    kStopCmd = LPI2C_MTDR_CMD(0x2U),   /*!< Generate STOP condition */
-    kStartCmd = LPI2C_MTDR_CMD(0x4U),  /*!< Generate(repeated) START and transmit address in DATA[[7:0] */
+    kStopCmd   = LPI2C_MTDR_CMD(0x2U), /*!< Generate STOP condition */
+    kStartCmd  = LPI2C_MTDR_CMD(0x4U), /*!< Generate(repeated) START and transmit address in DATA[[7:0] */
 };
 
 /*! @brief States for the state machine used by transactional APIs. */
@@ -113,6 +87,23 @@ static void LPI2C_MasterEDMACallback(edma_handle_t *dmaHandle, void *userData, b
  * Code
  ******************************************************************************/
 
+/*!
+ * brief Create a new handle for the LPI2C master DMA APIs.
+ *
+ * The creation of a handle is for use with the DMA APIs. Once a handle
+ * is created, there is not a corresponding destroy handle. If the user wants to
+ * terminate a transfer, the LPI2C_MasterTransferAbortEDMA() API shall be called.
+ *
+ * For devices where the LPI2C send and receive DMA requests are OR'd together, the a txDmaHandle
+ * parameter is ignored and may be set to NULL.
+ *
+ * param base The LPI2C peripheral base address.
+ * param[out] handle Pointer to the LPI2C master driver handle.
+ * param rxDmaHandle Handle for the eDMA receive channel. Created by the user prior to calling this function.
+ * param txDmaHandle Handle for the eDMA transmit channel. Created by the user prior to calling this function.
+ * param callback User provided pointer to the asynchronous callback function.
+ * param userData User provided pointer to the application callback data.
+ */
 void LPI2C_MasterCreateEDMAHandle(LPI2C_Type *base,
                                   lpi2c_master_edma_handle_t *handle,
                                   edma_handle_t *rxDmaHandle,
@@ -129,11 +120,11 @@ void LPI2C_MasterCreateEDMAHandle(LPI2C_Type *base,
 
     /* Set up the handle. For combined rx/tx DMA requests, the tx channel handle is set to the rx handle */
     /* in order to make the transfer API code simpler. */
-    handle->base = base;
+    handle->base               = base;
     handle->completionCallback = callback;
-    handle->userData = userData;
-    handle->rx = rxDmaHandle;
-    handle->tx = FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(base) ? txDmaHandle : rxDmaHandle;
+    handle->userData           = userData;
+    handle->rx                 = rxDmaHandle;
+    handle->tx                 = FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(base) ? txDmaHandle : rxDmaHandle;
 
     /* Set DMA channel completion callbacks. */
     EDMA_SetCallback(handle->rx, LPI2C_MasterEDMACallback, handle);
@@ -151,8 +142,8 @@ void LPI2C_MasterCreateEDMAHandle(LPI2C_Type *base,
 static uint32_t LPI2C_GenerateCommands(lpi2c_master_edma_handle_t *handle)
 {
     lpi2c_master_transfer_t *xfer = &handle->transfer;
-    uint16_t *cmd = (uint16_t *)&handle->commandBuffer;
-    uint32_t cmdCount = 0;
+    uint16_t *cmd                 = (uint16_t *)&handle->commandBuffer;
+    uint32_t cmdCount             = 0;
 
     /* Handle no start option. */
     if (xfer->flags & kLPI2C_TransferNoStartFlag)
@@ -182,7 +173,7 @@ static uint32_t LPI2C_GenerateCommands(lpi2c_master_edma_handle_t *handle)
             while (subaddressRemaining--)
             {
                 uint8_t subaddressByte = (xfer->subaddress >> (8 * subaddressRemaining)) & 0xff;
-                cmd[cmdCount++] = subaddressByte;
+                cmd[cmdCount++]        = subaddressByte;
             }
         }
 
@@ -204,6 +195,19 @@ static uint32_t LPI2C_GenerateCommands(lpi2c_master_edma_handle_t *handle)
     return cmdCount;
 }
 
+/*!
+ * brief Performs a non-blocking DMA-based transaction on the I2C bus.
+ *
+ * The callback specified when the a handle was created is invoked when the transaction has
+ * completed.
+ *
+ * param base The LPI2C peripheral base address.
+ * param handle Pointer to the LPI2C master driver handle.
+ * param transfer The pointer to the transfer descriptor.
+ * retval #kStatus_Success The transaction was started successfully.
+ * retval #kStatus_LPI2C_Busy Either another master is currently utilizing the bus, or another DMA
+ *      transaction is already in progress.
+ */
 status_t LPI2C_MasterTransferEDMA(LPI2C_Type *base,
                                   lpi2c_master_edma_handle_t *handle,
                                   lpi2c_master_transfer_t *transfer)
@@ -263,7 +267,7 @@ status_t LPI2C_MasterTransferEDMA(LPI2C_Type *base,
     /* Get a 32-byte aligned TCD pointer. */
     edma_tcd_t *tcd = (edma_tcd_t *)((uint32_t)(&handle->tcds[1]) & (~ALIGN_32_MASK));
 
-    bool hasSendData = (transfer->direction == kLPI2C_Write) && (transfer->dataSize);
+    bool hasSendData    = (transfer->direction == kLPI2C_Write) && (transfer->dataSize);
     bool hasReceiveData = (transfer->direction == kLPI2C_Read) && (transfer->dataSize);
 
     edma_transfer_config_t transferConfig;
@@ -272,14 +276,14 @@ status_t LPI2C_MasterTransferEDMA(LPI2C_Type *base,
     /* Set up data transmit. */
     if (hasSendData)
     {
-        transferConfig.srcAddr = (uint32_t)transfer->data;
-        transferConfig.destAddr = (uint32_t)LPI2C_MasterGetTxFifoAddress(base);
-        transferConfig.srcTransferSize = kEDMA_TransferSize1Bytes;
+        transferConfig.srcAddr          = (uint32_t)transfer->data;
+        transferConfig.destAddr         = (uint32_t)LPI2C_MasterGetTxFifoAddress(base);
+        transferConfig.srcTransferSize  = kEDMA_TransferSize1Bytes;
         transferConfig.destTransferSize = kEDMA_TransferSize1Bytes;
-        transferConfig.srcOffset = sizeof(uint8_t);
-        transferConfig.destOffset = 0;
-        transferConfig.minorLoopBytes = sizeof(uint8_t); /* TODO optimize to fill fifo */
-        transferConfig.majorLoopCounts = transfer->dataSize;
+        transferConfig.srcOffset        = sizeof(uint8_t);
+        transferConfig.destOffset       = 0;
+        transferConfig.minorLoopBytes   = sizeof(uint8_t); /* TODO optimize to fill fifo */
+        transferConfig.majorLoopCounts  = transfer->dataSize;
 
         /* Store the initially configured eDMA minor byte transfer count into the LPI2C handle */
         handle->nbytes = transferConfig.minorLoopBytes;
@@ -302,14 +306,14 @@ status_t LPI2C_MasterTransferEDMA(LPI2C_Type *base,
     else if (hasReceiveData)
     {
         /* Set up data receive. */
-        transferConfig.srcAddr = (uint32_t)LPI2C_MasterGetRxFifoAddress(base);
-        transferConfig.destAddr = (uint32_t)transfer->data;
-        transferConfig.srcTransferSize = kEDMA_TransferSize1Bytes;
+        transferConfig.srcAddr          = (uint32_t)LPI2C_MasterGetRxFifoAddress(base);
+        transferConfig.destAddr         = (uint32_t)transfer->data;
+        transferConfig.srcTransferSize  = kEDMA_TransferSize1Bytes;
         transferConfig.destTransferSize = kEDMA_TransferSize1Bytes;
-        transferConfig.srcOffset = 0;
-        transferConfig.destOffset = sizeof(uint8_t);
-        transferConfig.minorLoopBytes = sizeof(uint8_t); /* TODO optimize to empty fifo */
-        transferConfig.majorLoopCounts = transfer->dataSize;
+        transferConfig.srcOffset        = 0;
+        transferConfig.destOffset       = sizeof(uint8_t);
+        transferConfig.minorLoopBytes   = sizeof(uint8_t); /* TODO optimize to empty fifo */
+        transferConfig.majorLoopCounts  = transfer->dataSize;
 
         /* Store the initially configured eDMA minor byte transfer count into the LPI2C handle */
         handle->nbytes = transferConfig.minorLoopBytes;
@@ -338,14 +342,14 @@ status_t LPI2C_MasterTransferEDMA(LPI2C_Type *base,
     /* Set up commands transfer. */
     if (commandCount)
     {
-        transferConfig.srcAddr = (uint32_t)handle->commandBuffer;
-        transferConfig.destAddr = (uint32_t)LPI2C_MasterGetTxFifoAddress(base);
-        transferConfig.srcTransferSize = kEDMA_TransferSize2Bytes;
+        transferConfig.srcAddr          = (uint32_t)handle->commandBuffer;
+        transferConfig.destAddr         = (uint32_t)LPI2C_MasterGetTxFifoAddress(base);
+        transferConfig.srcTransferSize  = kEDMA_TransferSize2Bytes;
         transferConfig.destTransferSize = kEDMA_TransferSize2Bytes;
-        transferConfig.srcOffset = sizeof(uint16_t);
-        transferConfig.destOffset = 0;
-        transferConfig.minorLoopBytes = sizeof(uint16_t); /* TODO optimize to fill fifo */
-        transferConfig.majorLoopCounts = commandCount;
+        transferConfig.srcOffset        = sizeof(uint16_t);
+        transferConfig.destOffset       = 0;
+        transferConfig.minorLoopBytes   = sizeof(uint16_t); /* TODO optimize to fill fifo */
+        transferConfig.majorLoopCounts  = commandCount;
 
         EDMA_SetTransferConfig(handle->tx->base, handle->tx->channel, &transferConfig, linkTcd);
     }
@@ -372,6 +376,15 @@ status_t LPI2C_MasterTransferEDMA(LPI2C_Type *base,
     return result;
 }
 
+/*!
+ * brief Returns number of bytes transferred so far.
+ *
+ * param base The LPI2C peripheral base address.
+ * param handle Pointer to the LPI2C master driver handle.
+ * param[out] count Number of bytes transferred so far by the non-blocking transaction.
+ * retval #kStatus_Success
+ * retval #kStatus_NoTransferInProgress There is not a DMA transaction currently in progress.
+ */
 status_t LPI2C_MasterTransferGetCountEDMA(LPI2C_Type *base, lpi2c_master_edma_handle_t *handle, size_t *count)
 {
     assert(handle);
@@ -411,6 +424,17 @@ status_t LPI2C_MasterTransferGetCountEDMA(LPI2C_Type *base, lpi2c_master_edma_ha
     return kStatus_Success;
 }
 
+/*!
+ * brief Terminates a non-blocking LPI2C master transmission early.
+ *
+ * note It is not safe to call this function from an IRQ handler that has a higher priority than the
+ *      eDMA peripheral's IRQ priority.
+ *
+ * param base The LPI2C peripheral base address.
+ * param handle Pointer to the LPI2C master driver handle.
+ * retval #kStatus_Success A transaction was successfully aborted.
+ * retval #kStatus_LPI2C_Idle There is not a DMA transaction currently in progress.
+ */
 status_t LPI2C_MasterTransferAbortEDMA(LPI2C_Type *base, lpi2c_master_edma_handle_t *handle)
 {
     /* Catch when there is not an active transfer. */
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_lpi2c_edma.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_lpi2c_edma.h
index b66edbfd4b6..30d528e5558 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_lpi2c_edma.h
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_lpi2c_edma.h
@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
  * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
  *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 #ifndef _FSL_LPI2C_EDMA_H_
 #define _FSL_LPI2C_EDMA_H_
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_lpspi.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_lpspi.c
old mode 100644
new mode 100755
index 3a515e17394..13b902877a8
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_lpspi.c
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_lpspi.c
@@ -1,42 +1,16 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
  * All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include "fsl_lpspi.h"
 
 /*******************************************************************************
-* Definitions
-******************************************************************************/
+ * Definitions
+ ******************************************************************************/
 
 /* Component ID definition, used by tools. */
 #ifndef FSL_COMPONENT_ID
@@ -61,73 +35,81 @@ typedef void (*lpspi_master_isr_t)(LPSPI_Type *base, lpspi_master_handle_t *hand
 typedef void (*lpspi_slave_isr_t)(LPSPI_Type *base, lpspi_slave_handle_t *handle);
 
 /*******************************************************************************
-* Prototypes
-******************************************************************************/
+ * Prototypes
+ ******************************************************************************/
 
 /*!
-* @brief Configures the LPSPI peripheral chip select polarity.
-*
-* This function  takes in the desired peripheral chip select (Pcs) and it's corresponding desired polarity and
-* configures the Pcs signal to operate with the desired characteristic.
-*
-* @param base LPSPI peripheral address.
-* @param pcs The particular peripheral chip select (parameter value is of type lpspi_which_pcs_t) for which we wish to
-*            apply the active high or active low characteristic.
-* @param activeLowOrHigh The setting for either "active high, inactive low (0)"  or "active low, inactive high(1)" of
-*                        type lpspi_pcs_polarity_config_t.
-*/
+ * @brief Get instance number for LPSPI module.
+ *
+ * @param base LPSPI peripheral base address.
+ * @return Return the value of LPSPI instance.
+ */
+uint32_t LPSPI_GetInstance(LPSPI_Type *base);
+
+/*!
+ * @brief Configures the LPSPI peripheral chip select polarity.
+ *
+ * This function  takes in the desired peripheral chip select (Pcs) and it's corresponding desired polarity and
+ * configures the Pcs signal to operate with the desired characteristic.
+ *
+ * @param base LPSPI peripheral address.
+ * @param pcs The particular peripheral chip select (parameter value is of type lpspi_which_pcs_t) for which we wish to
+ *            apply the active high or active low characteristic.
+ * @param activeLowOrHigh The setting for either "active high, inactive low (0)"  or "active low, inactive high(1)" of
+ *                        type lpspi_pcs_polarity_config_t.
+ */
 static void LPSPI_SetOnePcsPolarity(LPSPI_Type *base,
                                     lpspi_which_pcs_t pcs,
                                     lpspi_pcs_polarity_config_t activeLowOrHigh);
 
 /*!
-* @brief Combine the write data for 1 byte to 4 bytes.
-* This is not a public API.
-*/
+ * @brief Combine the write data for 1 byte to 4 bytes.
+ * This is not a public API.
+ */
 static uint32_t LPSPI_CombineWriteData(uint8_t *txData, uint32_t bytesEachWrite, bool isByteSwap);
 
 /*!
-* @brief Separate the read data for 1 byte to 4 bytes.
-* This is not a public API.
-*/
+ * @brief Separate the read data for 1 byte to 4 bytes.
+ * This is not a public API.
+ */
 static void LPSPI_SeparateReadData(uint8_t *rxData, uint32_t readData, uint32_t bytesEachRead, bool isByteSwap);
 
 /*!
-* @brief Master fill up the TX FIFO with data.
-* This is not a public API.
-*/
+ * @brief Master fill up the TX FIFO with data.
+ * This is not a public API.
+ */
 static void LPSPI_MasterTransferFillUpTxFifo(LPSPI_Type *base, lpspi_master_handle_t *handle);
 
 /*!
-* @brief Master finish up a transfer.
-* It would call back if there is callback function and set the state to idle.
-* This is not a public API.
-*/
+ * @brief Master finish up a transfer.
+ * It would call back if there is callback function and set the state to idle.
+ * This is not a public API.
+ */
 static void LPSPI_MasterTransferComplete(LPSPI_Type *base, lpspi_master_handle_t *handle);
 
 /*!
-* @brief Slave fill up the TX FIFO with data.
-* This is not a public API.
-*/
+ * @brief Slave fill up the TX FIFO with data.
+ * This is not a public API.
+ */
 static void LPSPI_SlaveTransferFillUpTxFifo(LPSPI_Type *base, lpspi_slave_handle_t *handle);
 
 /*!
-* @brief Slave finish up a transfer.
-* It would call back if there is callback function and set the state to idle.
-* This is not a public API.
-*/
+ * @brief Slave finish up a transfer.
+ * It would call back if there is callback function and set the state to idle.
+ * This is not a public API.
+ */
 static void LPSPI_SlaveTransferComplete(LPSPI_Type *base, lpspi_slave_handle_t *handle);
 
 /*!
-* @brief LPSPI common interrupt handler.
-*
-* @param handle pointer to s_lpspiHandle which stores the transfer state.
-*/
+ * @brief LPSPI common interrupt handler.
+ *
+ * @param handle pointer to s_lpspiHandle which stores the transfer state.
+ */
 static void LPSPI_CommonIRQHandler(LPSPI_Type *base, void *param);
 
 /*******************************************************************************
-* Variables
-******************************************************************************/
+ * Variables
+ ******************************************************************************/
 
 /* Defines constant value arrays for the baud rate pre-scalar and scalar divider values.*/
 static const uint8_t s_baudratePrescaler[] = {1, 2, 4, 8, 16, 32, 64, 128};
@@ -158,8 +140,8 @@ static lpspi_slave_isr_t s_lpspiSlaveIsr;
 /* @brief Dummy data for each instance. This data is used when user's tx buffer is NULL*/
 volatile uint8_t g_lpspiDummyData[ARRAY_SIZE(s_lpspiBases)] = {0};
 /**********************************************************************************************************************
-* Code
-*********************************************************************************************************************/
+ * Code
+ *********************************************************************************************************************/
 uint32_t LPSPI_GetInstance(LPSPI_Type *base)
 {
     uint8_t instance = 0;
@@ -178,12 +160,29 @@ uint32_t LPSPI_GetInstance(LPSPI_Type *base)
     return instance;
 }
 
+/*!
+ * brief Set up the dummy data.
+ *
+ * param base LPSPI peripheral address.
+ * param dummyData Data to be transferred when tx buffer is NULL.
+ * Note:
+ *      This API has no effect when LPSPI in slave interrupt mode, because driver
+ *      will set the TXMSK bit to 1 if txData is NULL, no data is loaded from transmit
+ *      FIFO and output pin is tristated.
+ */
 void LPSPI_SetDummyData(LPSPI_Type *base, uint8_t dummyData)
 {
-    uint32_t instance = LPSPI_GetInstance(base);
+    uint32_t instance          = LPSPI_GetInstance(base);
     g_lpspiDummyData[instance] = dummyData;
 }
 
+/*!
+ * brief Initializes the LPSPI master.
+ *
+ * param base LPSPI peripheral address.
+ * param masterConfig Pointer to structure lpspi_master_config_t.
+ * param srcClock_Hz Module source input clock in Hertz
+ */
 void LPSPI_MasterInit(LPSPI_Type *base, const lpspi_master_config_t *masterConfig, uint32_t srcClock_Hz)
 {
     assert(masterConfig);
@@ -202,9 +201,6 @@ void LPSPI_MasterInit(LPSPI_Type *base, const lpspi_master_config_t *masterConfi
 
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
-    /* Reset to known status */
-    LPSPI_Reset(base);
-
     /* Set LPSPI to master */
     LPSPI_SetMasterSlaveMode(base, kLPSPI_Master);
 
@@ -236,27 +232,49 @@ void LPSPI_MasterInit(LPSPI_Type *base, const lpspi_master_config_t *masterConfi
     LPSPI_SetDummyData(base, LPSPI_DUMMY_DATA);
 }
 
+/*!
+ * brief Sets the lpspi_master_config_t structure to default values.
+ *
+ * This API initializes the configuration structure  for LPSPI_MasterInit().
+ * The initialized structure can remain unchanged in LPSPI_MasterInit(), or can be modified
+ * before calling the LPSPI_MasterInit().
+ * Example:
+ * code
+ *  lpspi_master_config_t  masterConfig;
+ *  LPSPI_MasterGetDefaultConfig(&masterConfig);
+ * endcode
+ * param masterConfig pointer to lpspi_master_config_t structure
+ */
 void LPSPI_MasterGetDefaultConfig(lpspi_master_config_t *masterConfig)
 {
     assert(masterConfig);
 
-    masterConfig->baudRate = 500000;
+    /* Initializes the configure structure to zero. */
+    memset(masterConfig, 0, sizeof(*masterConfig));
+
+    masterConfig->baudRate     = 500000;
     masterConfig->bitsPerFrame = 8;
-    masterConfig->cpol = kLPSPI_ClockPolarityActiveHigh;
-    masterConfig->cpha = kLPSPI_ClockPhaseFirstEdge;
-    masterConfig->direction = kLPSPI_MsbFirst;
+    masterConfig->cpol         = kLPSPI_ClockPolarityActiveHigh;
+    masterConfig->cpha         = kLPSPI_ClockPhaseFirstEdge;
+    masterConfig->direction    = kLPSPI_MsbFirst;
 
-    masterConfig->pcsToSckDelayInNanoSec = 1000000000 / masterConfig->baudRate * 2;
-    masterConfig->lastSckToPcsDelayInNanoSec = 1000000000 / masterConfig->baudRate * 2;
-    masterConfig->betweenTransferDelayInNanoSec = 1000000000 / masterConfig->baudRate * 2;
+    masterConfig->pcsToSckDelayInNanoSec        = 80;
+    masterConfig->lastSckToPcsDelayInNanoSec    = 60;
+    masterConfig->betweenTransferDelayInNanoSec = 160;
 
-    masterConfig->whichPcs = kLPSPI_Pcs0;
+    masterConfig->whichPcs           = kLPSPI_Pcs0;
     masterConfig->pcsActiveHighOrLow = kLPSPI_PcsActiveLow;
 
-    masterConfig->pinCfg = kLPSPI_SdiInSdoOut;
+    masterConfig->pinCfg        = kLPSPI_SdiInSdoOut;
     masterConfig->dataOutConfig = kLpspiDataOutRetained;
 }
 
+/*!
+ * brief LPSPI slave configuration.
+ *
+ * param base LPSPI peripheral address.
+ * param slaveConfig Pointer to a structure lpspi_slave_config_t.
+ */
 void LPSPI_SlaveInit(LPSPI_Type *base, const lpspi_slave_config_t *slaveConfig)
 {
     assert(slaveConfig);
@@ -273,9 +291,6 @@ void LPSPI_SlaveInit(LPSPI_Type *base, const lpspi_slave_config_t *slaveConfig)
 
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
-    /* Reset to known status */
-    LPSPI_Reset(base);
-
     LPSPI_SetMasterSlaveMode(base, kLPSPI_Slave);
 
     LPSPI_SetOnePcsPolarity(base, slaveConfig->whichPcs, slaveConfig->pcsActiveHighOrLow);
@@ -294,22 +309,44 @@ void LPSPI_SlaveInit(LPSPI_Type *base, const lpspi_slave_config_t *slaveConfig)
     LPSPI_Enable(base, true);
 }
 
+/*!
+ * brief Sets the lpspi_slave_config_t structure to default values.
+ *
+ * This API initializes the configuration structure for LPSPI_SlaveInit().
+ * The initialized structure can remain unchanged in LPSPI_SlaveInit() or can be modified
+ * before calling the LPSPI_SlaveInit().
+ * Example:
+ * code
+ *  lpspi_slave_config_t  slaveConfig;
+ *  LPSPI_SlaveGetDefaultConfig(&slaveConfig);
+ * endcode
+ * param slaveConfig pointer to lpspi_slave_config_t structure.
+ */
 void LPSPI_SlaveGetDefaultConfig(lpspi_slave_config_t *slaveConfig)
 {
     assert(slaveConfig);
 
-    slaveConfig->bitsPerFrame = 8;                      /*!< Bits per frame, minimum 8, maximum 4096.*/
-    slaveConfig->cpol = kLPSPI_ClockPolarityActiveHigh; /*!< Clock polarity. */
-    slaveConfig->cpha = kLPSPI_ClockPhaseFirstEdge;     /*!< Clock phase. */
-    slaveConfig->direction = kLPSPI_MsbFirst;           /*!< MSB or LSB data shift direction. */
+    /* Initializes the configure structure to zero. */
+    memset(slaveConfig, 0, sizeof(*slaveConfig));
+
+    slaveConfig->bitsPerFrame = 8;                              /*!< Bits per frame, minimum 8, maximum 4096.*/
+    slaveConfig->cpol         = kLPSPI_ClockPolarityActiveHigh; /*!< Clock polarity. */
+    slaveConfig->cpha         = kLPSPI_ClockPhaseFirstEdge;     /*!< Clock phase. */
+    slaveConfig->direction    = kLPSPI_MsbFirst;                /*!< MSB or LSB data shift direction. */
 
-    slaveConfig->whichPcs = kLPSPI_Pcs0;                   /*!< Desired Peripheral Chip Select (pcs) */
+    slaveConfig->whichPcs           = kLPSPI_Pcs0;         /*!< Desired Peripheral Chip Select (pcs) */
     slaveConfig->pcsActiveHighOrLow = kLPSPI_PcsActiveLow; /*!< Desired PCS active high or low */
 
-    slaveConfig->pinCfg = kLPSPI_SdiInSdoOut;
+    slaveConfig->pinCfg        = kLPSPI_SdiInSdoOut;
     slaveConfig->dataOutConfig = kLpspiDataOutRetained;
 }
 
+/*!
+ * brief Restores the LPSPI peripheral to reset state. Note that this function
+ * sets all registers to reset state. As a result, the LPSPI module can't work after calling
+ * this API.
+ * param base LPSPI peripheral address.
+ */
 void LPSPI_Reset(LPSPI_Type *base)
 {
     /* Reset all internal logic and registers, except the Control Register. Remains set until cleared by software.*/
@@ -322,6 +359,10 @@ void LPSPI_Reset(LPSPI_Type *base)
     base->CR = 0x00U;
 }
 
+/*!
+ * brief De-initializes the LPSPI peripheral. Call this API to disable the LPSPI clock.
+ * param base LPSPI peripheral address.
+ */
 void LPSPI_Deinit(LPSPI_Type *base)
 {
     /* Reset to default value */
@@ -352,6 +393,29 @@ static void LPSPI_SetOnePcsPolarity(LPSPI_Type *base,
     base->CFGR1 = cfgr1Value | ((uint32_t)activeLowOrHigh << (LPSPI_CFGR1_PCSPOL_SHIFT + pcs));
 }
 
+/*!
+ * brief Sets the LPSPI baud rate in bits per second.
+ *
+ * This function takes in the desired bitsPerSec (baud rate) and calculates the nearest
+ * possible baud rate without exceeding the desired baud rate and returns the
+ * calculated baud rate in bits-per-second. It requires the caller to provide
+ * the frequency of the module source clock (in Hertz). Note that the baud rate
+ * does not go into effect until the Transmit Control Register (TCR) is programmed
+ * with the prescale value. Hence, this function returns the prescale tcrPrescaleValue
+ * parameter for later programming in the TCR.  The higher level
+ * peripheral driver should alert the user of an out of range baud rate input.
+ *
+ * Note that the LPSPI module must first be disabled before configuring this.
+ * Note that the LPSPI module must be configured for master mode before configuring this.
+ *
+ * param base LPSPI peripheral address.
+ * param baudRate_Bps The desired baud rate in bits per second.
+ * param srcClock_Hz Module source input clock in Hertz.
+ * param tcrPrescaleValue The TCR prescale value needed to program the TCR.
+ * return  The actual calculated baud rate. This function may also return a "0" if the
+ *          LPSPI is not configured for master mode or if the LPSPI module is not disabled.
+ */
+
 uint32_t LPSPI_MasterSetBaudRate(LPSPI_Type *base,
                                  uint32_t baudRate_Bps,
                                  uint32_t srcClock_Hz,
@@ -360,8 +424,8 @@ uint32_t LPSPI_MasterSetBaudRate(LPSPI_Type *base,
     assert(tcrPrescaleValue);
 
     /* For master mode configuration only, if slave mode detected, return 0.
-    * Also, the LPSPI module needs to be disabled first, if enabled, return 0
-    */
+     * Also, the LPSPI module needs to be disabled first, if enabled, return 0
+     */
     if ((!LPSPI_IsMaster(base)) || (base->CR & LPSPI_CR_MEN_MASK))
     {
         return 0;
@@ -374,16 +438,16 @@ uint32_t LPSPI_MasterSetBaudRate(LPSPI_Type *base,
     uint32_t desiredBaudrate = baudRate_Bps;
 
     /* find combination of prescaler and scaler resulting in baudrate closest to the
-    * requested value
-    */
+     * requested value
+     */
     min_diff = 0xFFFFFFFFU;
 
     /* Set to maximum divisor value bit settings so that if baud rate passed in is less
-    * than the minimum possible baud rate, then the SPI will be configured to the lowest
-    * possible baud rate
-    */
+     * than the minimum possible baud rate, then the SPI will be configured to the lowest
+     * possible baud rate
+     */
     bestPrescaler = 7;
-    bestScaler = 255;
+    bestScaler    = 255;
 
     bestBaudrate = 0; /* required to avoid compilation warning */
 
@@ -395,28 +459,28 @@ uint32_t LPSPI_MasterSetBaudRate(LPSPI_Type *base,
             realBaudrate = (srcClock_Hz / (s_baudratePrescaler[prescaler] * (scaler + 2U)));
 
             /* calculate the baud rate difference based on the conditional statement
-            * that states that the calculated baud rate must not exceed the desired baud rate
-            */
+             * that states that the calculated baud rate must not exceed the desired baud rate
+             */
             if (desiredBaudrate >= realBaudrate)
             {
                 diff = desiredBaudrate - realBaudrate;
                 if (min_diff > diff)
                 {
                     /* a better match found */
-                    min_diff = diff;
+                    min_diff      = diff;
                     bestPrescaler = prescaler;
-                    bestScaler = scaler;
-                    bestBaudrate = realBaudrate;
+                    bestScaler    = scaler;
+                    bestBaudrate  = realBaudrate;
                 }
             }
         }
     }
 
     /* Write the best baud rate scalar to the CCR.
-    * Note, no need to check for error since we've already checked to make sure the module is
-    * disabled and in master mode. Also, there is a limit on the maximum divider so we will not
-    * exceed this.
-    */
+     * Note, no need to check for error since we've already checked to make sure the module is
+     * disabled and in master mode. Also, there is a limit on the maximum divider so we will not
+     * exceed this.
+     */
     base->CCR = (base->CCR & ~LPSPI_CCR_SCKDIV_MASK) | LPSPI_CCR_SCKDIV(bestScaler);
 
     /* return the best prescaler value for user to use later */
@@ -426,6 +490,28 @@ uint32_t LPSPI_MasterSetBaudRate(LPSPI_Type *base,
     return bestBaudrate;
 }
 
+/*!
+ * brief Manually configures a specific LPSPI delay parameter (module must be disabled to
+ *        change the delay values).
+ *
+ * This function configures the following:
+ * SCK to PCS delay, or
+ * PCS to SCK delay, or
+ * The configurations must occur between the transfer delay.
+ *
+ * The delay names are available in type lpspi_delay_type_t.
+ *
+ * The user passes the desired delay along with the delay value.
+ * This allows the user to directly set the delay values if they have
+ * pre-calculated them or if they simply wish to manually increment the value.
+ *
+ * Note that the LPSPI module must first be disabled before configuring this.
+ * Note that the LPSPI module must be configured for master mode before configuring this.
+ *
+ * param base LPSPI peripheral address.
+ * param scaler The 8-bit delay value 0x00 to 0xFF (255).
+ * param whichDelay The desired delay to configure, must be of type lpspi_delay_type_t.
+ */
 void LPSPI_MasterSetDelayScaler(LPSPI_Type *base, uint32_t scaler, lpspi_delay_type_t whichDelay)
 {
     /*These settings are only relevant in master mode */
@@ -449,6 +535,34 @@ void LPSPI_MasterSetDelayScaler(LPSPI_Type *base, uint32_t scaler, lpspi_delay_t
     }
 }
 
+/*!
+ * brief Calculates the delay based on the desired delay input in nanoseconds (module must be
+ *        disabled to change the delay values).
+ *
+ * This function calculates the values for the following:
+ * SCK to PCS delay, or
+ * PCS to SCK delay, or
+ * The configurations must occur between the transfer delay.
+ *
+ * The delay names are available in type lpspi_delay_type_t.
+ *
+ * The user passes the desired delay and the desired delay value in
+ * nano-seconds.  The function calculates the value needed for the desired delay parameter
+ * and returns the actual calculated delay because an exact delay match may not be possible. In this
+ * case, the closest match is calculated without going below the desired delay value input.
+ * It is possible to input a very large delay value that exceeds the capability of the part, in
+ * which case the maximum supported delay is returned. It is up to the higher level
+ * peripheral driver to alert the user of an out of range delay input.
+ *
+ * Note that the LPSPI module must be configured for master mode before configuring this. And note that
+ * the delayTime = LPSPI_clockSource / (PRESCALE * Delay_scaler).
+ *
+ * param base LPSPI peripheral address.
+ * param delayTimeInNanoSec The desired delay value in nano-seconds.
+ * param whichDelay The desired delay to configuration, which must be of type lpspi_delay_type_t.
+ * param srcClock_Hz  Module source input clock in Hertz.
+ * return actual Calculated delay value in nano-seconds.
+ */
 uint32_t LPSPI_MasterSetDelayTimes(LPSPI_Type *base,
                                    uint32_t delayTimeInNanoSec,
                                    lpspi_delay_type_t whichDelay,
@@ -475,8 +589,8 @@ uint32_t LPSPI_MasterSetDelayTimes(LPSPI_Type *base,
     bestScaler = 0xFFU;
 
     /* Calculate the initial (min) delay and maximum possible delay based on the specific delay as
-    * the delay divisors are slightly different based on which delay we are configuring.
-    */
+     * the delay divisors are slightly different based on which delay we are configuring.
+     */
     if (whichDelay == kLPSPI_BetweenTransfer)
     {
         /* First calculate the initial, default delay, note min delay is 2 clock cycles. Due to large size of
@@ -512,9 +626,9 @@ uint32_t LPSPI_MasterSetDelayTimes(LPSPI_Type *base,
     }
 
     /* If the initial, default delay is already greater than the desired delay, then
-    * set the delay to their initial value (0) and return the delay. In other words,
-    * there is no way to decrease the delay value further.
-    */
+     * set the delay to their initial value (0) and return the delay. In other words,
+     * there is no way to decrease the delay value further.
+     */
     if (initialDelayNanoSec >= delayTimeInNanoSec)
     {
         LPSPI_MasterSetDelayScaler(base, 0, whichDelay);
@@ -533,17 +647,17 @@ uint32_t LPSPI_MasterSetDelayTimes(LPSPI_Type *base,
         realDelay /= clockDividedPrescaler;
 
         /* calculate the delay difference based on the conditional statement
-        * that states that the calculated delay must not be less then the desired delay
-        */
+         * that states that the calculated delay must not be less then the desired delay
+         */
         if (realDelay >= delayTimeInNanoSec)
         {
             diff = realDelay - delayTimeInNanoSec;
             if (min_diff > diff)
             {
                 /* a better match found */
-                min_diff = diff;
+                min_diff   = diff;
                 bestScaler = scaler;
-                bestDelay = realDelay;
+                bestDelay  = realDelay;
             }
         }
     }
@@ -557,6 +671,17 @@ uint32_t LPSPI_MasterSetDelayTimes(LPSPI_Type *base,
 
 /*Transactional APIs -- Master*/
 
+/*!
+ * brief Initializes the LPSPI master handle.
+ *
+ * This function initializes the LPSPI handle, which can be used for other LPSPI transactional APIs.  Usually, for a
+ * specified LPSPI instance, call this API once to get the initialized handle.
+
+ * param base LPSPI peripheral address.
+ * param handle LPSPI handle pointer to lpspi_master_handle_t.
+ * param callback DSPI callback.
+ * param userData callback function parameter.
+ */
 void LPSPI_MasterTransferCreateHandle(LPSPI_Type *base,
                                       lpspi_master_handle_t *handle,
                                       lpspi_master_transfer_callback_t callback,
@@ -576,6 +701,14 @@ void LPSPI_MasterTransferCreateHandle(LPSPI_Type *base,
     handle->userData = userData;
 }
 
+/*!
+ * brief Check the argument for transfer .
+ *
+ * param transfer the transfer struct to be used.
+ * param bitPerFrame The bit size of one frame.
+ * param bytePerFrame The byte size of one frame.
+ * return Return true for right and false for wrong.
+ */
 bool LPSPI_CheckTransferArgument(lpspi_transfer_t *transfer, uint32_t bitsPerFrame, uint32_t bytesPerFrame)
 {
     assert(transfer);
@@ -625,14 +758,31 @@ bool LPSPI_CheckTransferArgument(lpspi_transfer_t *transfer, uint32_t bitsPerFra
     return true;
 }
 
+/*!
+ * brief LPSPI master transfer data using a polling method.
+ *
+ * This function transfers data using a  polling method. This is a blocking function, which does not return until all
+ * transfers have been
+ * completed.
+ *
+ * Note:
+ * The transfer data size should be integer multiples of bytesPerFrame if bytesPerFrame is less than or equal to 4.
+ * For bytesPerFrame greater than 4:
+ * The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not integer multiples of 4.
+ * Otherwise, the transfer data size can be an integer multiple of bytesPerFrame.
+ *
+ * param base LPSPI peripheral address.
+ * param transfer pointer to lpspi_transfer_t structure.
+ * return status of status_t.
+ */
 status_t LPSPI_MasterTransferBlocking(LPSPI_Type *base, lpspi_transfer_t *transfer)
 {
     assert(transfer);
 
-    uint32_t bitsPerFrame = ((base->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT) + 1;
+    uint32_t bitsPerFrame  = ((base->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT) + 1;
     uint32_t bytesPerFrame = (bitsPerFrame + 7) / 8;
-    uint32_t temp = 0U;
-    uint8_t dummyData = g_lpspiDummyData[LPSPI_GetInstance(base)];
+    uint32_t temp          = 0U;
+    uint8_t dummyData      = g_lpspiDummyData[LPSPI_GetInstance(base)];
 
     if (!LPSPI_CheckTransferArgument(transfer, bitsPerFrame, bytesPerFrame))
     {
@@ -645,8 +795,8 @@ status_t LPSPI_MasterTransferBlocking(LPSPI_Type *base, lpspi_transfer_t *transf
         return kStatus_LPSPI_Busy;
     }
 
-    uint8_t *txData = transfer->txData;
-    uint8_t *rxData = transfer->rxData;
+    uint8_t *txData               = transfer->txData;
+    uint8_t *rxData               = transfer->rxData;
     uint32_t txRemainingByteCount = transfer->dataSize;
     uint32_t rxRemainingByteCount = transfer->dataSize;
 
@@ -663,8 +813,8 @@ status_t LPSPI_MasterTransferBlocking(LPSPI_Type *base, lpspi_transfer_t *transf
     uint32_t whichPcs = (transfer->configFlags & LPSPI_MASTER_PCS_MASK) >> LPSPI_MASTER_PCS_SHIFT;
 
     bool isPcsContinuous = (bool)(transfer->configFlags & kLPSPI_MasterPcsContinuous);
-    bool isRxMask = false;
-    bool isByteSwap = (bool)(transfer->configFlags & kLPSPI_MasterByteSwap);
+    bool isRxMask        = false;
+    bool isByteSwap      = (bool)(transfer->configFlags & kLPSPI_MasterByteSwap);
 
     LPSPI_FlushFifo(base, true, true);
     LPSPI_ClearStatusFlags(base, kLPSPI_AllStatusFlag);
@@ -700,12 +850,12 @@ status_t LPSPI_MasterTransferBlocking(LPSPI_Type *base, lpspi_transfer_t *transf
     if (bytesPerFrame <= 4)
     {
         bytesEachWrite = bytesPerFrame;
-        bytesEachRead = bytesPerFrame;
+        bytesEachRead  = bytesPerFrame;
     }
     else
     {
         bytesEachWrite = 4;
-        bytesEachRead = 4;
+        bytesEachRead  = 4;
     }
 
     /*Write the TX data until txRemainingByteCount is equal to 0 */
@@ -721,14 +871,18 @@ status_t LPSPI_MasterTransferBlocking(LPSPI_Type *base, lpspi_transfer_t *transf
         {
         }
 
-        if (txData)
+        /* To prevent rxfifo overflow, ensure transmitting and receiving are executed in parallel */
+        if(((NULL == rxData) || (rxRemainingByteCount - txRemainingByteCount)/bytesEachRead < fifoSize))
         {
-            wordToSend = LPSPI_CombineWriteData(txData, bytesEachWrite, isByteSwap);
-            txData += bytesEachWrite;
-        }
+            if (txData)
+            {
+                wordToSend = LPSPI_CombineWriteData(txData, bytesEachWrite, isByteSwap);
+                txData += bytesEachWrite;
+            }
 
-        LPSPI_WriteData(base, wordToSend);
-        txRemainingByteCount -= bytesEachWrite;
+            LPSPI_WriteData(base, wordToSend);
+            txRemainingByteCount -= bytesEachWrite;
+        }
 
         /*Check whether there is RX data in RX FIFO . Read out the RX data so that the RX FIFO would not overrun.*/
         if (rxData)
@@ -789,15 +943,33 @@ status_t LPSPI_MasterTransferBlocking(LPSPI_Type *base, lpspi_transfer_t *transf
     return kStatus_Success;
 }
 
+/*!
+ * brief LPSPI master transfer data using an interrupt method.
+ *
+ * This function transfers data using an interrupt method. This is a non-blocking function, which returns right away.
+ * When all data
+ * is transferred, the callback function is called.
+ *
+ * Note:
+ * The transfer data size should be integer multiples of bytesPerFrame if bytesPerFrame is less than or equal to 4.
+ * For bytesPerFrame greater than 4:
+ * The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not integer multiples of 4.
+ * Otherwise, the transfer data size can be an integer multiple of bytesPerFrame.
+ *
+ * param base LPSPI peripheral address.
+ * param handle pointer to lpspi_master_handle_t structure which stores the transfer state.
+ * param transfer pointer to lpspi_transfer_t structure.
+ * return status of status_t.
+ */
 status_t LPSPI_MasterTransferNonBlocking(LPSPI_Type *base, lpspi_master_handle_t *handle, lpspi_transfer_t *transfer)
 {
     assert(handle);
     assert(transfer);
 
-    uint32_t bitsPerFrame = ((base->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT) + 1;
+    uint32_t bitsPerFrame  = ((base->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT) + 1;
     uint32_t bytesPerFrame = (bitsPerFrame + 7) / 8;
-    uint32_t temp = 0U;
-    uint8_t dummyData = g_lpspiDummyData[LPSPI_GetInstance(base)];
+    uint32_t temp          = 0U;
+    uint8_t dummyData      = g_lpspiDummyData[LPSPI_GetInstance(base)];
 
     if (!LPSPI_CheckTransferArgument(transfer, bitsPerFrame, bytesPerFrame))
     {
@@ -818,16 +990,16 @@ status_t LPSPI_MasterTransferNonBlocking(LPSPI_Type *base, lpspi_master_handle_t
 
     uint32_t whichPcs = (transfer->configFlags & LPSPI_MASTER_PCS_MASK) >> LPSPI_MASTER_PCS_SHIFT;
 
-    handle->txData = transfer->txData;
-    handle->rxData = transfer->rxData;
+    handle->txData               = transfer->txData;
+    handle->rxData               = transfer->rxData;
     handle->txRemainingByteCount = transfer->dataSize;
     handle->rxRemainingByteCount = transfer->dataSize;
-    handle->totalByteCount = transfer->dataSize;
+    handle->totalByteCount       = transfer->dataSize;
 
     handle->writeTcrInIsr = false;
 
     handle->writeRegRemainingTimes = (transfer->dataSize / bytesPerFrame) * ((bytesPerFrame + 3) / 4);
-    handle->readRegRemainingTimes = handle->writeRegRemainingTimes;
+    handle->readRegRemainingTimes  = handle->writeRegRemainingTimes;
 
     handle->txBuffIfNull =
         ((uint32_t)dummyData) | ((uint32_t)dummyData << 8) | ((uint32_t)dummyData << 16) | ((uint32_t)dummyData << 24);
@@ -836,17 +1008,17 @@ status_t LPSPI_MasterTransferNonBlocking(LPSPI_Type *base, lpspi_master_handle_t
     handle->fifoSize = LPSPI_GetRxFifoSize(base);
 
     handle->isPcsContinuous = (bool)(transfer->configFlags & kLPSPI_MasterPcsContinuous);
-    handle->isByteSwap = (bool)(transfer->configFlags & kLPSPI_MasterByteSwap);
+    handle->isByteSwap      = (bool)(transfer->configFlags & kLPSPI_MasterByteSwap);
 
     /*Set the RX and TX watermarks to reduce the ISR times.*/
     if (handle->fifoSize > 1)
     {
-        txWatermark = 1;
+        txWatermark         = 1;
         handle->rxWatermark = handle->fifoSize - 2;
     }
     else
     {
-        txWatermark = 0;
+        txWatermark         = 0;
         handle->rxWatermark = 0;
     }
 
@@ -882,7 +1054,7 @@ status_t LPSPI_MasterTransferNonBlocking(LPSPI_Type *base, lpspi_master_handle_t
      * controlled by software.*/
     if (handle->rxData == NULL)
     {
-        isRxMask = true;
+        isRxMask                     = true;
         handle->rxRemainingByteCount = 0;
     }
 
@@ -895,12 +1067,12 @@ status_t LPSPI_MasterTransferNonBlocking(LPSPI_Type *base, lpspi_master_handle_t
     if (bytesPerFrame <= 4)
     {
         handle->bytesEachWrite = bytesPerFrame;
-        handle->bytesEachRead = bytesPerFrame;
+        handle->bytesEachRead  = bytesPerFrame;
     }
     else
     {
         handle->bytesEachWrite = 4;
-        handle->bytesEachRead = 4;
+        handle->bytesEachRead  = 4;
     }
 
     /* Enable the NVIC for LPSPI peripheral. Note that below code is useless if the LPSPI interrupt is in INTMUX ,
@@ -945,9 +1117,9 @@ static void LPSPI_MasterTransferFillUpTxFifo(LPSPI_Type *base, lpspi_master_hand
     uint32_t wordToSend = 0;
 
     /* Make sure the difference in remaining TX and RX byte counts does not exceed FIFO depth
-    * and that the number of TX FIFO entries does not exceed the FIFO depth.
-    * But no need to make the protection if there is no rxData.
-    */
+     * and that the number of TX FIFO entries does not exceed the FIFO depth.
+     * But no need to make the protection if there is no rxData.
+     */
     while ((LPSPI_GetTxFifoCount(base) < (handle->fifoSize)) &&
            (((handle->readRegRemainingTimes - handle->writeRegRemainingTimes) < handle->fifoSize) ||
             (handle->rxData == NULL)))
@@ -984,7 +1156,7 @@ static void LPSPI_MasterTransferFillUpTxFifo(LPSPI_Type *base, lpspi_master_hand
                 /* Only write to the TCR if the FIFO has room */
                 if ((LPSPI_GetTxFifoCount(base) < (handle->fifoSize)))
                 {
-                    base->TCR = (base->TCR & ~(LPSPI_TCR_CONTC_MASK));
+                    base->TCR             = (base->TCR & ~(LPSPI_TCR_CONTC_MASK));
                     handle->writeTcrInIsr = false;
                 }
                 /* Else, set a global flag to tell the ISR to do write to the TCR */
@@ -1013,6 +1185,16 @@ static void LPSPI_MasterTransferComplete(LPSPI_Type *base, lpspi_master_handle_t
     }
 }
 
+/*!
+ * brief Gets the master transfer remaining bytes.
+ *
+ * This function gets the master transfer remaining bytes.
+ *
+ * param base LPSPI peripheral address.
+ * param handle pointer to lpspi_master_handle_t structure which stores the transfer state.
+ * param count Number of bytes transferred so far by the non-blocking transaction.
+ * return status of status_t.
+ */
 status_t LPSPI_MasterTransferGetCount(LPSPI_Type *base, lpspi_master_handle_t *handle, size_t *count)
 {
     assert(handle);
@@ -1045,6 +1227,14 @@ status_t LPSPI_MasterTransferGetCount(LPSPI_Type *base, lpspi_master_handle_t *h
     return kStatus_Success;
 }
 
+/*!
+ * brief LPSPI master abort transfer which uses an interrupt method.
+ *
+ * This function aborts a transfer which uses an interrupt method.
+ *
+ * param base LPSPI peripheral address.
+ * param handle pointer to lpspi_master_handle_t structure which stores the transfer state.
+ */
 void LPSPI_MasterTransferAbort(LPSPI_Type *base, lpspi_master_handle_t *handle)
 {
     assert(handle);
@@ -1054,11 +1244,19 @@ void LPSPI_MasterTransferAbort(LPSPI_Type *base, lpspi_master_handle_t *handle)
 
     LPSPI_Reset(base);
 
-    handle->state = kLPSPI_Idle;
+    handle->state                = kLPSPI_Idle;
     handle->txRemainingByteCount = 0;
     handle->rxRemainingByteCount = 0;
 }
 
+/*!
+ * brief LPSPI Master IRQ handler function.
+ *
+ * This function processes the LPSPI transmit and receive IRQ.
+ *
+ * param base LPSPI peripheral address.
+ * param handle pointer to lpspi_master_handle_t structure which stores the transfer state.
+ */
 void LPSPI_MasterTransferHandleIRQ(LPSPI_Type *base, lpspi_master_handle_t *handle)
 {
     assert(handle);
@@ -1070,9 +1268,9 @@ void LPSPI_MasterTransferHandleIRQ(LPSPI_Type *base, lpspi_master_handle_t *hand
         if (handle->rxRemainingByteCount)
         {
             /* First, disable the interrupts to avoid potentially triggering another interrupt
-            * while reading out the RX FIFO as more data may be coming into the RX FIFO. We'll
-            * re-enable the interrupts based on the LPSPI state after reading out the FIFO.
-            */
+             * while reading out the RX FIFO as more data may be coming into the RX FIFO. We'll
+             * re-enable the interrupts based on the LPSPI state after reading out the FIFO.
+             */
             LPSPI_DisableInterrupts(base, kLPSPI_RxInterruptEnable);
 
             while ((LPSPI_GetRxFifoCount(base)) && (handle->rxRemainingByteCount))
@@ -1096,8 +1294,8 @@ void LPSPI_MasterTransferHandleIRQ(LPSPI_Type *base, lpspi_master_handle_t *hand
             }
 
             /* Re-enable the interrupts only if rxCount indicates there is more data to receive,
-            * else we may get a spurious interrupt.
-            * */
+             * else we may get a spurious interrupt.
+             * */
             if (handle->rxRemainingByteCount)
             {
                 /* Set the TDF and RDF interrupt enables simultaneously to avoid race conditions */
@@ -1126,7 +1324,7 @@ void LPSPI_MasterTransferHandleIRQ(LPSPI_Type *base, lpspi_master_handle_t *hand
         {
             if ((handle->isPcsContinuous) && (handle->writeTcrInIsr))
             {
-                base->TCR = (base->TCR & ~(LPSPI_TCR_CONTC_MASK));
+                base->TCR             = (base->TCR & ~(LPSPI_TCR_CONTC_MASK));
                 handle->writeTcrInIsr = false;
             }
         }
@@ -1157,6 +1355,17 @@ void LPSPI_MasterTransferHandleIRQ(LPSPI_Type *base, lpspi_master_handle_t *hand
 }
 
 /*Transactional APIs -- Slave*/
+/*!
+ * brief Initializes the LPSPI slave handle.
+ *
+ * This function initializes the LPSPI handle, which can be used for other LPSPI transactional APIs.  Usually, for a
+ * specified LPSPI instance, call this API once to get the initialized handle.
+ *
+ * param base LPSPI peripheral address.
+ * param handle LPSPI handle pointer to lpspi_slave_handle_t.
+ * param callback DSPI callback.
+ * param userData callback function parameter.
+ */
 void LPSPI_SlaveTransferCreateHandle(LPSPI_Type *base,
                                      lpspi_slave_handle_t *handle,
                                      lpspi_slave_transfer_callback_t callback,
@@ -1176,14 +1385,32 @@ void LPSPI_SlaveTransferCreateHandle(LPSPI_Type *base,
     handle->userData = userData;
 }
 
+/*!
+ * brief LPSPI slave transfer data using an interrupt method.
+ *
+ * This function transfer data using an interrupt method. This is a non-blocking function, which returns right away.
+ * When all data
+ * is transferred, the callback function is called.
+ *
+ * Note:
+ * The transfer data size should be integer multiples of bytesPerFrame if bytesPerFrame is less than or equal to 4.
+ * For bytesPerFrame greater than 4:
+ * The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not an integer multiple of 4.
+ * Otherwise, the transfer data size can be an integer multiple of bytesPerFrame.
+ *
+ * param base LPSPI peripheral address.
+ * param handle pointer to lpspi_slave_handle_t structure which stores the transfer state.
+ * param transfer pointer to lpspi_transfer_t structure.
+ * return status of status_t.
+ */
 status_t LPSPI_SlaveTransferNonBlocking(LPSPI_Type *base, lpspi_slave_handle_t *handle, lpspi_transfer_t *transfer)
 {
     assert(handle);
     assert(transfer);
 
-    uint32_t bitsPerFrame = ((base->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT) + 1;
+    uint32_t bitsPerFrame  = ((base->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT) + 1;
     uint32_t bytesPerFrame = (bitsPerFrame + 7) / 8;
-    uint32_t temp = 0U;
+    uint32_t temp          = 0U;
 
     if (!LPSPI_CheckTransferArgument(transfer, bitsPerFrame, bytesPerFrame))
     {
@@ -1202,14 +1429,14 @@ status_t LPSPI_SlaveTransferNonBlocking(LPSPI_Type *base, lpspi_slave_handle_t *
 
     uint32_t whichPcs = (transfer->configFlags & LPSPI_SLAVE_PCS_MASK) >> LPSPI_SLAVE_PCS_SHIFT;
 
-    handle->txData = transfer->txData;
-    handle->rxData = transfer->rxData;
+    handle->txData               = transfer->txData;
+    handle->rxData               = transfer->rxData;
     handle->txRemainingByteCount = transfer->dataSize;
     handle->rxRemainingByteCount = transfer->dataSize;
-    handle->totalByteCount = transfer->dataSize;
+    handle->totalByteCount       = transfer->dataSize;
 
     handle->writeRegRemainingTimes = (transfer->dataSize / bytesPerFrame) * ((bytesPerFrame + 3) / 4);
-    handle->readRegRemainingTimes = handle->writeRegRemainingTimes;
+    handle->readRegRemainingTimes  = handle->writeRegRemainingTimes;
 
     /*The TX and RX FIFO sizes are always the same*/
     handle->fifoSize = LPSPI_GetRxFifoSize(base);
@@ -1220,12 +1447,12 @@ status_t LPSPI_SlaveTransferNonBlocking(LPSPI_Type *base, lpspi_slave_handle_t *
     uint8_t txWatermark;
     if (handle->fifoSize > 1)
     {
-        txWatermark = 1;
+        txWatermark         = 1;
         handle->rxWatermark = handle->fifoSize - 2;
     }
     else
     {
-        txWatermark = 0;
+        txWatermark         = 0;
         handle->rxWatermark = 0;
     }
     LPSPI_SetFifoWatermarks(base, txWatermark, handle->rxWatermark);
@@ -1256,7 +1483,7 @@ status_t LPSPI_SlaveTransferNonBlocking(LPSPI_Type *base, lpspi_slave_handle_t *
     /*If there is not rxData , can mask the receive data (receive data is not stored in receive FIFO).*/
     if (handle->rxData == NULL)
     {
-        isRxMask = true;
+        isRxMask                     = true;
         handle->rxRemainingByteCount = 0;
     }
 
@@ -1265,13 +1492,12 @@ status_t LPSPI_SlaveTransferNonBlocking(LPSPI_Type *base, lpspi_slave_handle_t *
      */
     if (handle->txData == NULL)
     {
-        isTxMask = true;
+        isTxMask                     = true;
         handle->txRemainingByteCount = 0;
     }
 
-    base->TCR = (base->TCR &
-                 ~(LPSPI_TCR_CONT_MASK | LPSPI_TCR_CONTC_MASK | LPSPI_TCR_RXMSK_MASK | LPSPI_TCR_TXMSK_MASK |
-                   LPSPI_TCR_PCS_MASK)) |
+    base->TCR = (base->TCR & ~(LPSPI_TCR_CONT_MASK | LPSPI_TCR_CONTC_MASK | LPSPI_TCR_RXMSK_MASK |
+                               LPSPI_TCR_TXMSK_MASK | LPSPI_TCR_PCS_MASK)) |
                 LPSPI_TCR_CONT(0) | LPSPI_TCR_CONTC(0) | LPSPI_TCR_RXMSK(isRxMask) | LPSPI_TCR_TXMSK(isTxMask) |
                 LPSPI_TCR_PCS(whichPcs);
 
@@ -1279,12 +1505,12 @@ status_t LPSPI_SlaveTransferNonBlocking(LPSPI_Type *base, lpspi_slave_handle_t *
     if (bytesPerFrame <= 4)
     {
         handle->bytesEachWrite = bytesPerFrame;
-        handle->bytesEachRead = bytesPerFrame;
+        handle->bytesEachRead  = bytesPerFrame;
     }
     else
     {
         handle->bytesEachWrite = 4;
-        handle->bytesEachRead = 4;
+        handle->bytesEachRead  = 4;
     }
 
     /* Enable the NVIC for LPSPI peripheral. Note that below code is useless if the LPSPI interrupt is in INTMUX ,
@@ -1392,6 +1618,16 @@ static void LPSPI_SlaveTransferComplete(LPSPI_Type *base, lpspi_slave_handle_t *
     }
 }
 
+/*!
+ * brief Gets the slave transfer remaining bytes.
+ *
+ * This function gets the slave transfer remaining bytes.
+ *
+ * param base LPSPI peripheral address.
+ * param handle pointer to lpspi_slave_handle_t structure which stores the transfer state.
+ * param count Number of bytes transferred so far by the non-blocking transaction.
+ * return status of status_t.
+ */
 status_t LPSPI_SlaveTransferGetCount(LPSPI_Type *base, lpspi_slave_handle_t *handle, size_t *count)
 {
     assert(handle);
@@ -1424,6 +1660,14 @@ status_t LPSPI_SlaveTransferGetCount(LPSPI_Type *base, lpspi_slave_handle_t *han
     return kStatus_Success;
 }
 
+/*!
+ * brief LPSPI slave aborts a transfer which uses an interrupt method.
+ *
+ * This function aborts a transfer which uses an interrupt method.
+ *
+ * param base LPSPI peripheral address.
+ * param handle pointer to lpspi_slave_handle_t structure which stores the transfer state.
+ */
 void LPSPI_SlaveTransferAbort(LPSPI_Type *base, lpspi_slave_handle_t *handle)
 {
     assert(handle);
@@ -1433,11 +1677,19 @@ void LPSPI_SlaveTransferAbort(LPSPI_Type *base, lpspi_slave_handle_t *handle)
 
     LPSPI_Reset(base);
 
-    handle->state = kLPSPI_Idle;
+    handle->state                = kLPSPI_Idle;
     handle->txRemainingByteCount = 0;
     handle->rxRemainingByteCount = 0;
 }
 
+/*!
+ * brief LPSPI Slave IRQ handler function.
+ *
+ * This function processes the LPSPI transmit and receives an IRQ.
+ *
+ * param base LPSPI peripheral address.
+ * param handle pointer to lpspi_slave_handle_t structure which stores the transfer state.
+ */
 void LPSPI_SlaveTransferHandleIRQ(LPSPI_Type *base, lpspi_slave_handle_t *handle)
 {
     assert(handle);
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_lpspi.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_lpspi.h
index 72895a225b7..40236798d15 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_lpspi.h
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_lpspi.h
@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
  * All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 #ifndef _FSL_LPSPI_H_
 #define _FSL_LPSPI_H_
@@ -47,8 +21,8 @@
 
 /*! @name Driver version */
 /*@{*/
-/*! @brief LPSPI driver version 2.0.1. */
-#define FSL_LPSPI_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
+/*! @brief LPSPI driver version 2.0.3. */
+#define FSL_LPSPI_DRIVER_VERSION (MAKE_VERSION(2, 0, 3))
 /*@}*/
 
 #ifndef LPSPI_DUMMY_DATA
@@ -62,25 +36,25 @@ extern volatile uint8_t g_lpspiDummyData[];
 /*! @brief Status for the LPSPI driver.*/
 enum _lpspi_status
 {
-    kStatus_LPSPI_Busy = MAKE_STATUS(kStatusGroup_LPSPI, 0),      /*!< LPSPI transfer is busy.*/
-    kStatus_LPSPI_Error = MAKE_STATUS(kStatusGroup_LPSPI, 1),     /*!< LPSPI driver error. */
-    kStatus_LPSPI_Idle = MAKE_STATUS(kStatusGroup_LPSPI, 2),      /*!< LPSPI is idle.*/
-    kStatus_LPSPI_OutOfRange = MAKE_STATUS(kStatusGroup_LPSPI, 3) /*!< LPSPI transfer out Of range. */
+    kStatus_LPSPI_Busy       = MAKE_STATUS(kStatusGroup_LPSPI, 0), /*!< LPSPI transfer is busy.*/
+    kStatus_LPSPI_Error      = MAKE_STATUS(kStatusGroup_LPSPI, 1), /*!< LPSPI driver error. */
+    kStatus_LPSPI_Idle       = MAKE_STATUS(kStatusGroup_LPSPI, 2), /*!< LPSPI is idle.*/
+    kStatus_LPSPI_OutOfRange = MAKE_STATUS(kStatusGroup_LPSPI, 3)  /*!< LPSPI transfer out Of range. */
 };
 
 /*! @brief LPSPI status flags in SPIx_SR register.*/
 enum _lpspi_flags
 {
-    kLPSPI_TxDataRequestFlag = LPSPI_SR_TDF_MASK,    /*!< Transmit data flag */
-    kLPSPI_RxDataReadyFlag = LPSPI_SR_RDF_MASK,      /*!< Receive data flag */
-    kLPSPI_WordCompleteFlag = LPSPI_SR_WCF_MASK,     /*!< Word Complete flag */
-    kLPSPI_FrameCompleteFlag = LPSPI_SR_FCF_MASK,    /*!< Frame Complete flag */
+    kLPSPI_TxDataRequestFlag    = LPSPI_SR_TDF_MASK, /*!< Transmit data flag */
+    kLPSPI_RxDataReadyFlag      = LPSPI_SR_RDF_MASK, /*!< Receive data flag */
+    kLPSPI_WordCompleteFlag     = LPSPI_SR_WCF_MASK, /*!< Word Complete flag */
+    kLPSPI_FrameCompleteFlag    = LPSPI_SR_FCF_MASK, /*!< Frame Complete flag */
     kLPSPI_TransferCompleteFlag = LPSPI_SR_TCF_MASK, /*!< Transfer Complete flag */
-    kLPSPI_TransmitErrorFlag = LPSPI_SR_TEF_MASK,    /*!< Transmit Error flag (FIFO underrun) */
-    kLPSPI_ReceiveErrorFlag = LPSPI_SR_REF_MASK,     /*!< Receive Error flag (FIFO overrun) */
-    kLPSPI_DataMatchFlag = LPSPI_SR_DMF_MASK,        /*!< Data Match flag */
-    kLPSPI_ModuleBusyFlag = LPSPI_SR_MBF_MASK,       /*!< Module Busy flag */
-    kLPSPI_AllStatusFlag = (LPSPI_SR_TDF_MASK | LPSPI_SR_RDF_MASK | LPSPI_SR_WCF_MASK | LPSPI_SR_FCF_MASK |
+    kLPSPI_TransmitErrorFlag    = LPSPI_SR_TEF_MASK, /*!< Transmit Error flag (FIFO underrun) */
+    kLPSPI_ReceiveErrorFlag     = LPSPI_SR_REF_MASK, /*!< Receive Error flag (FIFO overrun) */
+    kLPSPI_DataMatchFlag        = LPSPI_SR_DMF_MASK, /*!< Data Match flag */
+    kLPSPI_ModuleBusyFlag       = LPSPI_SR_MBF_MASK, /*!< Module Busy flag */
+    kLPSPI_AllStatusFlag        = (LPSPI_SR_TDF_MASK | LPSPI_SR_RDF_MASK | LPSPI_SR_WCF_MASK | LPSPI_SR_FCF_MASK |
                             LPSPI_SR_TCF_MASK | LPSPI_SR_TEF_MASK | LPSPI_SR_REF_MASK | LPSPI_SR_DMF_MASK |
                             LPSPI_SR_MBF_MASK) /*!< Used for clearing all w1c status flags */
 };
@@ -88,14 +62,14 @@ enum _lpspi_flags
 /*! @brief LPSPI interrupt source.*/
 enum _lpspi_interrupt_enable
 {
-    kLPSPI_TxInterruptEnable = LPSPI_IER_TDIE_MASK,               /*!< Transmit data interrupt enable */
-    kLPSPI_RxInterruptEnable = LPSPI_IER_RDIE_MASK,               /*!< Receive data interrupt enable */
-    kLPSPI_WordCompleteInterruptEnable = LPSPI_IER_WCIE_MASK,     /*!< Word complete interrupt enable */
-    kLPSPI_FrameCompleteInterruptEnable = LPSPI_IER_FCIE_MASK,    /*!< Frame complete interrupt enable */
+    kLPSPI_TxInterruptEnable               = LPSPI_IER_TDIE_MASK, /*!< Transmit data interrupt enable */
+    kLPSPI_RxInterruptEnable               = LPSPI_IER_RDIE_MASK, /*!< Receive data interrupt enable */
+    kLPSPI_WordCompleteInterruptEnable     = LPSPI_IER_WCIE_MASK, /*!< Word complete interrupt enable */
+    kLPSPI_FrameCompleteInterruptEnable    = LPSPI_IER_FCIE_MASK, /*!< Frame complete interrupt enable */
     kLPSPI_TransferCompleteInterruptEnable = LPSPI_IER_TCIE_MASK, /*!< Transfer complete interrupt enable */
-    kLPSPI_TransmitErrorInterruptEnable = LPSPI_IER_TEIE_MASK,    /*!< Transmit error interrupt enable(FIFO underrun)*/
-    kLPSPI_ReceiveErrorInterruptEnable = LPSPI_IER_REIE_MASK,     /*!< Receive Error interrupt enable (FIFO overrun) */
-    kLPSPI_DataMatchInterruptEnable = LPSPI_IER_DMIE_MASK,        /*!< Data Match interrupt enable */
+    kLPSPI_TransmitErrorInterruptEnable    = LPSPI_IER_TEIE_MASK, /*!< Transmit error interrupt enable(FIFO underrun)*/
+    kLPSPI_ReceiveErrorInterruptEnable     = LPSPI_IER_REIE_MASK, /*!< Receive Error interrupt enable (FIFO overrun) */
+    kLPSPI_DataMatchInterruptEnable        = LPSPI_IER_DMIE_MASK, /*!< Data Match interrupt enable */
     kLPSPI_AllInterruptEnable =
         (LPSPI_IER_TDIE_MASK | LPSPI_IER_RDIE_MASK | LPSPI_IER_WCIE_MASK | LPSPI_IER_FCIE_MASK | LPSPI_IER_TCIE_MASK |
          LPSPI_IER_TEIE_MASK | LPSPI_IER_REIE_MASK | LPSPI_IER_DMIE_MASK) /*!< All above interrupts enable.*/
@@ -112,7 +86,7 @@ enum _lpspi_dma_enable
 typedef enum _lpspi_master_slave_mode
 {
     kLPSPI_Master = 1U, /*!< LPSPI peripheral operates in master mode.*/
-    kLPSPI_Slave = 0U   /*!< LPSPI peripheral operates in slave mode.*/
+    kLPSPI_Slave  = 0U  /*!< LPSPI peripheral operates in slave mode.*/
 } lpspi_master_slave_mode_t;
 
 /*! @brief LPSPI Peripheral Chip Select (PCS) configuration (which PCS to configure).*/
@@ -128,24 +102,24 @@ typedef enum _lpspi_which_pcs_config
 typedef enum _lpspi_pcs_polarity_config
 {
     kLPSPI_PcsActiveHigh = 1U, /*!< PCS Active High (idles low) */
-    kLPSPI_PcsActiveLow = 0U   /*!< PCS Active Low (idles high) */
+    kLPSPI_PcsActiveLow  = 0U  /*!< PCS Active Low (idles high) */
 } lpspi_pcs_polarity_config_t;
 
 /*! @brief LPSPI Peripheral Chip Select (PCS) Polarity.*/
 enum _lpspi_pcs_polarity
 {
-    kLPSPI_Pcs0ActiveLow = 1U << 0, /*!< Pcs0 Active Low (idles high). */
-    kLPSPI_Pcs1ActiveLow = 1U << 1, /*!< Pcs1 Active Low (idles high). */
-    kLPSPI_Pcs2ActiveLow = 1U << 2, /*!< Pcs2 Active Low (idles high). */
-    kLPSPI_Pcs3ActiveLow = 1U << 3, /*!< Pcs3 Active Low (idles high). */
-    kLPSPI_PcsAllActiveLow = 0xFU   /*!< Pcs0 to Pcs5 Active Low (idles high). */
+    kLPSPI_Pcs0ActiveLow   = 1U << 0, /*!< Pcs0 Active Low (idles high). */
+    kLPSPI_Pcs1ActiveLow   = 1U << 1, /*!< Pcs1 Active Low (idles high). */
+    kLPSPI_Pcs2ActiveLow   = 1U << 2, /*!< Pcs2 Active Low (idles high). */
+    kLPSPI_Pcs3ActiveLow   = 1U << 3, /*!< Pcs3 Active Low (idles high). */
+    kLPSPI_PcsAllActiveLow = 0xFU     /*!< Pcs0 to Pcs5 Active Low (idles high). */
 };
 
 /*! @brief LPSPI clock polarity configuration.*/
 typedef enum _lpspi_clock_polarity
 {
     kLPSPI_ClockPolarityActiveHigh = 0U, /*!< CPOL=0. Active-high LPSPI clock (idles low)*/
-    kLPSPI_ClockPolarityActiveLow = 1U   /*!< CPOL=1. Active-low LPSPI clock (idles high)*/
+    kLPSPI_ClockPolarityActiveLow  = 1U  /*!< CPOL=1. Active-low LPSPI clock (idles high)*/
 } lpspi_clock_polarity_t;
 
 /*! @brief LPSPI clock phase configuration.*/
@@ -167,20 +141,20 @@ typedef enum _lpspi_shift_direction
 /*! @brief LPSPI Host Request select configuration. */
 typedef enum _lpspi_host_request_select
 {
-    kLPSPI_HostReqExtPin = 0U,         /*!< Host Request is an ext pin. */
-    kLPSPI_HostReqInternalTrigger = 1U /*!< Host Request is an internal trigger. */
+    kLPSPI_HostReqExtPin          = 0U, /*!< Host Request is an ext pin. */
+    kLPSPI_HostReqInternalTrigger = 1U  /*!< Host Request is an internal trigger. */
 } lpspi_host_request_select_t;
 
 /*! @brief LPSPI Match configuration options. */
 typedef enum _lpspi_match_config
 {
-    kLPSI_MatchDisabled = 0x0U,                     /*!< LPSPI Match Disabled. */
-    kLPSI_1stWordEqualsM0orM1 = 0x2U,               /*!< LPSPI Match Enabled. */
-    kLPSI_AnyWordEqualsM0orM1 = 0x3U,               /*!< LPSPI Match Enabled. */
+    kLPSI_MatchDisabled                     = 0x0U, /*!< LPSPI Match Disabled. */
+    kLPSI_1stWordEqualsM0orM1               = 0x2U, /*!< LPSPI Match Enabled. */
+    kLPSI_AnyWordEqualsM0orM1               = 0x3U, /*!< LPSPI Match Enabled. */
     kLPSI_1stWordEqualsM0and2ndWordEqualsM1 = 0x4U, /*!< LPSPI Match Enabled. */
     kLPSI_AnyWordEqualsM0andNxtWordEqualsM1 = 0x5U, /*!< LPSPI Match Enabled. */
-    kLPSI_1stWordAndM1EqualsM0andM1 = 0x6U,         /*!< LPSPI Match Enabled. */
-    kLPSI_AnyWordAndM1EqualsM0andM1 = 0x7U,         /*!< LPSPI Match Enabled. */
+    kLPSI_1stWordAndM1EqualsM0andM1         = 0x6U, /*!< LPSPI Match Enabled. */
+    kLPSI_AnyWordAndM1EqualsM0andM1         = 0x7U, /*!< LPSPI Match Enabled. */
 } lpspi_match_config_t;
 
 /*! @brief LPSPI pin (SDO and SDI) configuration. */
@@ -203,8 +177,8 @@ typedef enum _lpspi_data_out_config
 typedef enum _lpspi_transfer_width
 {
     kLPSPI_SingleBitXfer = 0U, /*!< 1-bit shift at a time, data out on SDO, in on SDI (normal mode) */
-    kLPSPI_TwoBitXfer = 1U,    /*!< 2-bits shift out on SDO/SDI and in on SDO/SDI */
-    kLPSPI_FourBitXfer = 2U    /*!< 4-bits shift out on SDO/SDI/PCS[3:2] and in on SDO/SDI/PCS[3:2] */
+    kLPSPI_TwoBitXfer    = 1U, /*!< 2-bits shift out on SDO/SDI and in on SDO/SDI */
+    kLPSPI_FourBitXfer   = 2U  /*!< 4-bits shift out on SDO/SDI/PCS[3:2] and in on SDO/SDI/PCS[3:2] */
 } lpspi_transfer_width_t;
 
 /*! @brief LPSPI delay type selection.*/
@@ -230,17 +204,17 @@ enum _lpspi_transfer_config_flag_for_master
 
     kLPSPI_MasterByteSwap =
         1U << 22 /*!< Is master swap the byte.
-                     * For example, when want to send data 1 2 3 4 5 6 7 8 (suppose you set
-                     * lpspi_shift_direction_t to MSB).
-                     * 1. If you set bitPerFrame = 8 , no matter the kLPSPI_MasterByteSwapyou flag is used
-                     * or not, the waveform is 1 2 3 4 5 6 7 8.
-                     * 2. If you set bitPerFrame = 16 :
-                     * (1) the waveform is 2 1 4 3 6 5 8 7 if you do not use the kLPSPI_MasterByteSwap flag.
-                     * (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_MasterByteSwap flag.
-                     * 3. If you set bitPerFrame = 32 :
-                     * (1) the waveform is 4 3 2 1 8 7 6 5 if you do not use the kLPSPI_MasterByteSwap flag.
-                     * (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_MasterByteSwap flag.
-                     */
+                  * For example, when want to send data 1 2 3 4 5 6 7 8 (suppose you set
+                  * lpspi_shift_direction_t to MSB).
+                  * 1. If you set bitPerFrame = 8 , no matter the kLPSPI_MasterByteSwapyou flag is used
+                  * or not, the waveform is 1 2 3 4 5 6 7 8.
+                  * 2. If you set bitPerFrame = 16 :
+                  * (1) the waveform is 2 1 4 3 6 5 8 7 if you do not use the kLPSPI_MasterByteSwap flag.
+                  * (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_MasterByteSwap flag.
+                  * 3. If you set bitPerFrame = 32 :
+                  * (1) the waveform is 4 3 2 1 8 7 6 5 if you do not use the kLPSPI_MasterByteSwap flag.
+                  * (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_MasterByteSwap flag.
+                  */
 };
 
 #define LPSPI_SLAVE_PCS_SHIFT (4U)   /*!< LPSPI slave PCS shift macro , internal used. */
@@ -256,17 +230,17 @@ enum _lpspi_transfer_config_flag_for_slave
 
     kLPSPI_SlaveByteSwap =
         1U << 22 /*!< Is slave swap the byte.
-                      * For example, when want to send data 1 2 3 4 5 6 7 8 (suppose you set
-                      * lpspi_shift_direction_t to MSB).
-                      * 1. If you set bitPerFrame = 8 , no matter the kLPSPI_SlaveByteSwap flag is used
-                      * or not, the waveform is 1 2 3 4 5 6 7 8.
-                      * 2. If you set bitPerFrame = 16 :
-                      * (1) the waveform is 2 1 4 3 6 5 8 7 if you do not use the kLPSPI_SlaveByteSwap flag.
-                      * (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_SlaveByteSwap flag.
-                      * 3. If you set bitPerFrame = 32 :
-                      * (1) the waveform is 4 3 2 1 8 7 6 5 if you do not use the kLPSPI_SlaveByteSwap flag.
-                      * (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_SlaveByteSwap flag.
-                      */
+                  * For example, when want to send data 1 2 3 4 5 6 7 8 (suppose you set
+                  * lpspi_shift_direction_t to MSB).
+                  * 1. If you set bitPerFrame = 8 , no matter the kLPSPI_SlaveByteSwap flag is used
+                  * or not, the waveform is 1 2 3 4 5 6 7 8.
+                  * 2. If you set bitPerFrame = 16 :
+                  * (1) the waveform is 2 1 4 3 6 5 8 7 if you do not use the kLPSPI_SlaveByteSwap flag.
+                  * (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_SlaveByteSwap flag.
+                  * 3. If you set bitPerFrame = 32 :
+                  * (1) the waveform is 4 3 2 1 8 7 6 5 if you do not use the kLPSPI_SlaveByteSwap flag.
+                  * (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_SlaveByteSwap flag.
+                  */
 };
 
 /*! @brief LPSPI transfer state, which is used for LPSPI transactional API state machine. */
@@ -290,9 +264,8 @@ typedef struct _lpspi_master_config
                                             It sets the boundary value if out of range.*/
     uint32_t lastSckToPcsDelayInNanoSec; /*!< Last SCK to PCS delay time in nanoseconds, setting to 0 sets the minimum
                                             delay. It sets the boundary value if out of range.*/
-    uint32_t
-        betweenTransferDelayInNanoSec; /*!< After the SCK delay time with nanoseconds, setting to 0 sets the minimum
-                                        delay. It sets the boundary value if out of range.*/
+    uint32_t betweenTransferDelayInNanoSec; /*!< After the SCK delay time with nanoseconds, setting to 0 sets the
+                                             minimum delay. It sets the boundary value if out of range.*/
 
     lpspi_which_pcs_t whichPcs;                     /*!< Desired Peripheral Chip Select (PCS). */
     lpspi_pcs_polarity_config_t pcsActiveHighOrLow; /*!< Desired PCS active high or low */
@@ -323,13 +296,13 @@ typedef struct _lpspi_slave_config
 } lpspi_slave_config_t;
 
 /*!
-* @brief Forward declaration of the _lpspi_master_handle typedefs.
-*/
+ * @brief Forward declaration of the _lpspi_master_handle typedefs.
+ */
 typedef struct _lpspi_master_handle lpspi_master_handle_t;
 
 /*!
-* @brief Forward declaration of the _lpspi_slave_handle typedefs.
-*/
+ * @brief Forward declaration of the _lpspi_slave_handle typedefs.
+ */
 typedef struct _lpspi_slave_handle lpspi_slave_handle_t;
 
 /*!
@@ -365,10 +338,9 @@ typedef struct _lpspi_transfer
     uint8_t *rxData;          /*!< Receive buffer. */
     volatile size_t dataSize; /*!< Transfer bytes. */
 
-    uint32_t
-        configFlags; /*!< Transfer transfer configuration flags. Set from _lpspi_transfer_config_flag_for_master if the
-                        transfer is used for master or _lpspi_transfer_config_flag_for_slave enumeration if the transfer
-                        is used for slave.*/
+    uint32_t configFlags; /*!< Transfer transfer configuration flags. Set from _lpspi_transfer_config_flag_for_master if
+                             the transfer is used for master or _lpspi_transfer_config_flag_for_slave enumeration if the
+                             transfer is used for slave.*/
 } lpspi_transfer_t;
 
 /*! @brief LPSPI master transfer handle structure used for transactional API. */
@@ -505,7 +477,7 @@ void LPSPI_Deinit(LPSPI_Type *base);
  * sets all registers to reset state. As a result, the LPSPI module can't work after calling
  * this API.
  * @param base LPSPI peripheral address.
-*/
+ */
 void LPSPI_Reset(LPSPI_Type *base);
 
 /*!
@@ -528,7 +500,7 @@ static inline void LPSPI_Enable(LPSPI_Type *base, bool enable)
 
 /*!
  *@}
-*/
+ */
 
 /*!
  * @name Status
@@ -605,7 +577,7 @@ static inline void LPSPI_ClearStatusFlags(LPSPI_Type *base, uint32_t statusFlags
 
 /*!
  *@}
-*/
+ */
 
 /*!
  * @name Interrupts
@@ -647,7 +619,7 @@ static inline void LPSPI_DisableInterrupts(LPSPI_Type *base, uint32_t mask)
 
 /*!
  *@}
-*/
+ */
 
 /*!
  * @name DMA Control
@@ -718,7 +690,7 @@ static inline uint32_t LPSPI_GetRxRegisterAddress(LPSPI_Type *base)
 
 /*!
  *@}
-*/
+ */
 
 /*!
  * @name Bus Operations
@@ -726,21 +698,13 @@ static inline uint32_t LPSPI_GetRxRegisterAddress(LPSPI_Type *base)
  */
 
 /*!
-* @brief Get instance number for LPSPI module.
-*
-* @param base LPSPI peripheral base address.
-* @return Return the value of LPSPI instance.
-*/
-uint32_t LPSPI_GetInstance(LPSPI_Type *base);
-
-/*!
-* @brief Check the argument for transfer .
-*
-* @param transfer the transfer struct to be used.
-* @param bitPerFrame The bit size of one frame.
-* @param bytePerFrame The byte size of one frame.
-* @return Return true for right and false for wrong.
-*/
+ * @brief Check the argument for transfer .
+ *
+ * @param transfer the transfer struct to be used.
+ * @param bitPerFrame The bit size of one frame.
+ * @param bytePerFrame The byte size of one frame.
+ * @return Return true for right and false for wrong.
+ */
 bool LPSPI_CheckTransferArgument(lpspi_transfer_t *transfer, uint32_t bitsPerFrame, uint32_t bytesPerFrame);
 
 /*!
@@ -968,7 +932,7 @@ void LPSPI_SetDummyData(LPSPI_Type *base, uint8_t dummyData);
 
 /*!
  *@}
-*/
+ */
 
 /*!
  * @name Transactional
@@ -1133,13 +1097,13 @@ void LPSPI_SlaveTransferHandleIRQ(LPSPI_Type *base, lpspi_slave_handle_t *handle
 
 /*!
  *@}
-*/
+ */
 
 #if defined(__cplusplus)
 }
 #endif /*_cplusplus*/
        /*!
         *@}
-       */
+        */
 
 #endif /*_FSL_LPSPI_H_*/
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_lpspi_edma.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_lpspi_edma.c
index cbc7af7e761..a26599bd215 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_lpspi_edma.c
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_lpspi_edma.c
@@ -1,42 +1,16 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
  * All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include "fsl_lpspi_edma.h"
 
 /***********************************************************************************************************************
-* Definitions
-***********************************************************************************************************************/
+ * Definitions
+ ***********************************************************************************************************************/
 
 /* Component ID definition, used by tools. */
 #ifndef FSL_COMPONENT_ID
@@ -44,8 +18,8 @@
 #endif
 
 /*!
-* @brief Structure definition for dspi_master_edma_private_handle_t. The structure is private.
-*/
+ * @brief Structure definition for dspi_master_edma_private_handle_t. The structure is private.
+ */
 typedef struct _lpspi_master_edma_private_handle
 {
     LPSPI_Type *base;                   /*!< LPSPI peripheral base address. */
@@ -53,8 +27,8 @@ typedef struct _lpspi_master_edma_private_handle
 } lpspi_master_edma_private_handle_t;
 
 /*!
-* @brief Structure definition for dspi_slave_edma_private_handle_t. The structure is private.
-*/
+ * @brief Structure definition for dspi_slave_edma_private_handle_t. The structure is private.
+ */
 typedef struct _lpspi_slave_edma_private_handle
 {
     LPSPI_Type *base;                  /*!< LPSPI peripheral base address. */
@@ -62,21 +36,30 @@ typedef struct _lpspi_slave_edma_private_handle
 } lpspi_slave_edma_private_handle_t;
 
 /***********************************************************************************************************************
-* Prototypes
-***********************************************************************************************************************/
+ * Prototypes
+ ***********************************************************************************************************************/
+
 /*!
-* @brief EDMA_LpspiMasterCallback after the LPSPI master transfer completed by using EDMA.
-* This is not a public API.
-*/
+ * @brief Get instance number for LPSPI module.
+ *
+ * @param base LPSPI peripheral base address.
+ * @return Return the value of LPSPI instance.
+ */
+static uint32_t LPSPI_GetInstance(LPSPI_Type *base);
+
+/*!
+ * @brief EDMA_LpspiMasterCallback after the LPSPI master transfer completed by using EDMA.
+ * This is not a public API.
+ */
 static void EDMA_LpspiMasterCallback(edma_handle_t *edmaHandle,
                                      void *g_lpspiEdmaPrivateHandle,
                                      bool transferDone,
                                      uint32_t tcds);
 
 /*!
-* @brief EDMA_LpspiSlaveCallback after the LPSPI slave transfer completed by using EDMA.
-* This is not a public API.
-*/
+ * @brief EDMA_LpspiSlaveCallback after the LPSPI slave transfer completed by using EDMA.
+ * This is not a public API.
+ */
 static void EDMA_LpspiSlaveCallback(edma_handle_t *edmaHandle,
                                     void *g_lpspiEdmaPrivateHandle,
                                     bool transferDone,
@@ -85,16 +68,37 @@ static void EDMA_LpspiSlaveCallback(edma_handle_t *edmaHandle,
 static void LPSPI_SeparateEdmaReadData(uint8_t *rxData, uint32_t readData, uint32_t bytesEachRead, bool isByteSwap);
 
 /***********************************************************************************************************************
-* Variables
-***********************************************************************************************************************/
+ * Variables
+ ***********************************************************************************************************************/
+/*! @brief Pointers to lpspi bases for each instance. */
+static LPSPI_Type *const s_lpspiBases[] = LPSPI_BASE_PTRS;
 
 /*! @brief Pointers to lpspi edma handles for each instance. */
-static lpspi_master_edma_private_handle_t s_lpspiMasterEdmaPrivateHandle[FSL_FEATURE_SOC_LPSPI_COUNT];
-static lpspi_slave_edma_private_handle_t s_lpspiSlaveEdmaPrivateHandle[FSL_FEATURE_SOC_LPSPI_COUNT];
+static lpspi_master_edma_private_handle_t s_lpspiMasterEdmaPrivateHandle[ARRAY_SIZE(s_lpspiBases)];
+static lpspi_slave_edma_private_handle_t s_lpspiSlaveEdmaPrivateHandle[ARRAY_SIZE(s_lpspiBases)];
 
 /***********************************************************************************************************************
-* Code
-***********************************************************************************************************************/
+ * Code
+ ***********************************************************************************************************************/
+
+static uint32_t LPSPI_GetInstance(LPSPI_Type *base)
+{
+    uint8_t instance = 0;
+
+    /* Find the instance index from base address mappings. */
+    for (instance = 0; instance < ARRAY_SIZE(s_lpspiBases); instance++)
+    {
+        if (s_lpspiBases[instance] == base)
+        {
+            break;
+        }
+    }
+
+    assert(instance < ARRAY_SIZE(s_lpspiBases));
+
+    return instance;
+}
+
 static void LPSPI_SeparateEdmaReadData(uint8_t *rxData, uint32_t readData, uint32_t bytesEachRead, bool isByteSwap)
 {
     assert(rxData);
@@ -150,6 +154,25 @@ static void LPSPI_SeparateEdmaReadData(uint8_t *rxData, uint32_t readData, uint3
     }
 }
 
+/*!
+ * brief Initializes the LPSPI master eDMA handle.
+ *
+ * This function initializes the LPSPI eDMA handle which can be used for other LPSPI transactional APIs.  Usually, for a
+ * specified LPSPI instance, call this API once to get the initialized handle.
+ *
+ * Note that the LPSPI eDMA has a separated (Rx and Rx as two sources) or shared (Rx  and Tx are the same source) DMA
+ * request source.
+ * (1) For a separated DMA request source, enable and set the Rx DMAMUX source for edmaRxRegToRxDataHandle and
+ * Tx DMAMUX source for edmaIntermediaryToTxRegHandle.
+ * (2) For a shared DMA request source, enable and set the Rx/Rx DMAMUX source for edmaRxRegToRxDataHandle.
+ *
+ * param base LPSPI peripheral base address.
+ * param handle LPSPI handle pointer to lpspi_master_edma_handle_t.
+ * param callback LPSPI callback.
+ * param userData callback function parameter.
+ * param edmaRxRegToRxDataHandle edmaRxRegToRxDataHandle pointer to edma_handle_t.
+ * param edmaTxDataToTxRegHandle edmaTxDataToTxRegHandle pointer to edma_handle_t.
+ */
 void LPSPI_MasterTransferCreateHandleEDMA(LPSPI_Type *base,
                                           lpspi_master_edma_handle_t *handle,
                                           lpspi_master_edma_transfer_callback_t callback,
@@ -166,7 +189,7 @@ void LPSPI_MasterTransferCreateHandleEDMA(LPSPI_Type *base,
 
     uint32_t instance = LPSPI_GetInstance(base);
 
-    s_lpspiMasterEdmaPrivateHandle[instance].base = base;
+    s_lpspiMasterEdmaPrivateHandle[instance].base   = base;
     s_lpspiMasterEdmaPrivateHandle[instance].handle = handle;
 
     handle->callback = callback;
@@ -176,14 +199,31 @@ void LPSPI_MasterTransferCreateHandleEDMA(LPSPI_Type *base,
     handle->edmaTxDataToTxRegHandle = edmaTxDataToTxRegHandle;
 }
 
+/*!
+ * brief LPSPI master transfer data using eDMA.
+ *
+ * This function transfers data using eDMA. This is a non-blocking function, which returns right away. When all data
+ * is transferred, the callback function is called.
+ *
+ * Note:
+ * The transfer data size should be an integer multiple of bytesPerFrame if bytesPerFrame is less than or equal to 4.
+ * For bytesPerFrame greater than 4:
+ * The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not an integer multiple of 4.
+ * Otherwise, the transfer data size can be an integer multiple of bytesPerFrame.
+ *
+ * param base LPSPI peripheral base address.
+ * param handle pointer to lpspi_master_edma_handle_t structure which stores the transfer state.
+ * param transfer pointer to lpspi_transfer_t structure.
+ * return status of status_t.
+ */
 status_t LPSPI_MasterTransferEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t *handle, lpspi_transfer_t *transfer)
 {
     assert(handle);
     assert(transfer);
 
-    uint32_t bitsPerFrame = ((base->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT) + 1;
+    uint32_t bitsPerFrame  = ((base->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT) + 1;
     uint32_t bytesPerFrame = (bitsPerFrame + 7) / 8;
-    uint32_t temp = 0U;
+    uint32_t temp          = 0U;
 
     if (!LPSPI_CheckTransferArgument(transfer, bitsPerFrame, bytesPerFrame))
     {
@@ -205,8 +245,8 @@ status_t LPSPI_MasterTransferEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t *
     handle->state = kLPSPI_Busy;
 
     uint32_t instance = LPSPI_GetInstance(base);
-    uint32_t rxAddr = LPSPI_GetRxRegisterAddress(base);
-    uint32_t txAddr = LPSPI_GetTxRegisterAddress(base);
+    uint32_t rxAddr   = LPSPI_GetRxRegisterAddress(base);
+    uint32_t txAddr   = LPSPI_GetTxRegisterAddress(base);
 
     uint32_t whichPcs = (transfer->configFlags & LPSPI_MASTER_PCS_MASK) >> LPSPI_MASTER_PCS_SHIFT;
 
@@ -226,17 +266,17 @@ status_t LPSPI_MasterTransferEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t *
     edma_transfer_config_t transferConfigRx;
     edma_transfer_config_t transferConfigTx;
 
-    edma_tcd_t *softwareTCD_extraBytes = (edma_tcd_t *)((uint32_t)(&handle->lpspiSoftwareTCD[1]) & (~0x1FU));
+    edma_tcd_t *softwareTCD_extraBytes    = (edma_tcd_t *)((uint32_t)(&handle->lpspiSoftwareTCD[1]) & (~0x1FU));
     edma_tcd_t *softwareTCD_pcsContinuous = (edma_tcd_t *)((uint32_t)(&handle->lpspiSoftwareTCD[2]) & (~0x1FU));
 
-    handle->txData = transfer->txData;
-    handle->rxData = transfer->rxData;
+    handle->txData               = transfer->txData;
+    handle->rxData               = transfer->rxData;
     handle->txRemainingByteCount = transfer->dataSize;
     handle->rxRemainingByteCount = transfer->dataSize;
-    handle->totalByteCount = transfer->dataSize;
+    handle->totalByteCount       = transfer->dataSize;
 
     handle->writeRegRemainingTimes = (transfer->dataSize / bytesPerFrame) * ((bytesPerFrame + 3) / 4);
-    handle->readRegRemainingTimes = handle->writeRegRemainingTimes;
+    handle->readRegRemainingTimes  = handle->writeRegRemainingTimes;
 
     handle->txBuffIfNull =
         ((uint32_t)dummyData) | ((uint32_t)dummyData << 8) | ((uint32_t)dummyData << 16) | ((uint32_t)dummyData << 24);
@@ -245,7 +285,7 @@ status_t LPSPI_MasterTransferEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t *
     handle->fifoSize = LPSPI_GetRxFifoSize(base);
 
     handle->isPcsContinuous = (bool)(transfer->configFlags & kLPSPI_MasterPcsContinuous);
-    handle->isByteSwap = (bool)(transfer->configFlags & kLPSPI_MasterByteSwap);
+    handle->isByteSwap      = (bool)(transfer->configFlags & kLPSPI_MasterByteSwap);
 
     LPSPI_SetFifoWatermarks(base, txWatermark, rxWatermark);
 
@@ -268,6 +308,8 @@ status_t LPSPI_MasterTransferEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t *
         }
     }
 
+    LPSPI_Enable(base, true);
+
     /*Flush FIFO , clear status , disable all the inerrupts.*/
     LPSPI_FlushFifo(base, true, true);
     LPSPI_ClearStatusFlags(base, kLPSPI_AllStatusFlag);
@@ -280,27 +322,27 @@ status_t LPSPI_MasterTransferEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t *
                 LPSPI_TCR_CONT(handle->isPcsContinuous) | LPSPI_TCR_CONTC(0U) | LPSPI_TCR_BYSW(handle->isByteSwap) |
                 LPSPI_TCR_PCS(whichPcs);
 
-    isThereExtraTxBytes = false;
+    isThereExtraTxBytes         = false;
     handle->isThereExtraRxBytes = false;
 
     /*Calculate the bytes for write/read the TX/RX register each time*/
     if (bytesPerFrame <= 4)
     {
         handle->bytesEachWrite = bytesPerFrame;
-        handle->bytesEachRead = bytesPerFrame;
+        handle->bytesEachRead  = bytesPerFrame;
 
         handle->bytesLastRead = bytesPerFrame;
     }
     else
     {
         handle->bytesEachWrite = 4;
-        handle->bytesEachRead = 4;
+        handle->bytesEachRead  = 4;
 
         handle->bytesLastRead = 4;
 
         if ((transfer->dataSize % 4) != 0)
         {
-            bytesLastWrite = transfer->dataSize % 4;
+            bytesLastWrite        = transfer->dataSize % 4;
             handle->bytesLastRead = bytesLastWrite;
 
             isThereExtraTxBytes = true;
@@ -322,12 +364,12 @@ status_t LPSPI_MasterTransferEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t *
 
     if (handle->rxData)
     {
-        transferConfigRx.destAddr = (uint32_t) & (handle->rxData[0]);
+        transferConfigRx.destAddr   = (uint32_t) & (handle->rxData[0]);
         transferConfigRx.destOffset = 1;
     }
     else
     {
-        transferConfigRx.destAddr = (uint32_t) & (handle->rxBuffIfNull);
+        transferConfigRx.destAddr   = (uint32_t) & (handle->rxBuffIfNull);
         transferConfigRx.destOffset = 0;
     }
     transferConfigRx.destTransferSize = kEDMA_TransferSize1Bytes;
@@ -337,7 +379,7 @@ status_t LPSPI_MasterTransferEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t *
     {
         case (1U):
             transferConfigRx.srcTransferSize = kEDMA_TransferSize1Bytes;
-            transferConfigRx.minorLoopBytes = 1;
+            transferConfigRx.minorLoopBytes  = 1;
             if (handle->isByteSwap)
             {
                 dif = 3;
@@ -346,7 +388,7 @@ status_t LPSPI_MasterTransferEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t *
 
         case (2U):
             transferConfigRx.srcTransferSize = kEDMA_TransferSize2Bytes;
-            transferConfigRx.minorLoopBytes = 2;
+            transferConfigRx.minorLoopBytes  = 2;
             if (handle->isByteSwap)
             {
                 dif = 2;
@@ -355,17 +397,17 @@ status_t LPSPI_MasterTransferEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t *
 
         case (4U):
             transferConfigRx.srcTransferSize = kEDMA_TransferSize4Bytes;
-            transferConfigRx.minorLoopBytes = 4;
+            transferConfigRx.minorLoopBytes  = 4;
             break;
 
         default:
             transferConfigRx.srcTransferSize = kEDMA_TransferSize1Bytes;
-            transferConfigRx.minorLoopBytes = 1;
+            transferConfigRx.minorLoopBytes  = 1;
             assert(false);
             break;
     }
 
-    transferConfigRx.srcAddr = (uint32_t)rxAddr + dif;
+    transferConfigRx.srcAddr   = (uint32_t)rxAddr + dif;
     transferConfigRx.srcOffset = 0;
 
     transferConfigRx.majorLoopCounts = handle->readRegRemainingTimes;
@@ -385,12 +427,12 @@ status_t LPSPI_MasterTransferEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t *
     {
         if (handle->txData)
         {
-            transferConfigTx.srcAddr = (uint32_t) & (transfer->txData[transfer->dataSize - bytesLastWrite]);
+            transferConfigTx.srcAddr   = (uint32_t) & (transfer->txData[transfer->dataSize - bytesLastWrite]);
             transferConfigTx.srcOffset = 1;
         }
         else
         {
-            transferConfigTx.srcAddr = (uint32_t)(&handle->txBuffIfNull);
+            transferConfigTx.srcAddr   = (uint32_t)(&handle->txBuffIfNull);
             transferConfigTx.srcOffset = 0;
         }
 
@@ -403,7 +445,7 @@ status_t LPSPI_MasterTransferEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t *
         {
             case (1U):
                 transferConfigTx.destTransferSize = kEDMA_TransferSize1Bytes;
-                transferConfigTx.minorLoopBytes = 1;
+                transferConfigTx.minorLoopBytes   = 1;
                 if (handle->isByteSwap)
                 {
                     dif = 3;
@@ -412,7 +454,7 @@ status_t LPSPI_MasterTransferEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t *
 
             case (2U):
                 transferConfigTx.destTransferSize = kEDMA_TransferSize2Bytes;
-                transferConfigTx.minorLoopBytes = 2;
+                transferConfigTx.minorLoopBytes   = 2;
                 if (handle->isByteSwap)
                 {
                     dif = 2;
@@ -421,12 +463,12 @@ status_t LPSPI_MasterTransferEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t *
 
             default:
                 transferConfigTx.destTransferSize = kEDMA_TransferSize1Bytes;
-                transferConfigTx.minorLoopBytes = 1;
+                transferConfigTx.minorLoopBytes   = 1;
                 assert(false);
                 break;
         }
 
-        transferConfigTx.destAddr = (uint32_t)txAddr + dif;
+        transferConfigTx.destAddr        = (uint32_t)txAddr + dif;
         transferConfigTx.majorLoopCounts = 1;
 
         EDMA_TcdReset(softwareTCD_extraBytes);
@@ -445,16 +487,16 @@ status_t LPSPI_MasterTransferEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t *
     {
         handle->transmitCommand = base->TCR & ~(LPSPI_TCR_CONTC_MASK | LPSPI_TCR_CONT_MASK);
 
-        transferConfigTx.srcAddr = (uint32_t) & (handle->transmitCommand);
+        transferConfigTx.srcAddr   = (uint32_t) & (handle->transmitCommand);
         transferConfigTx.srcOffset = 0;
 
-        transferConfigTx.destAddr = (uint32_t) & (base->TCR);
+        transferConfigTx.destAddr   = (uint32_t) & (base->TCR);
         transferConfigTx.destOffset = 0;
 
-        transferConfigTx.srcTransferSize = kEDMA_TransferSize4Bytes;
+        transferConfigTx.srcTransferSize  = kEDMA_TransferSize4Bytes;
         transferConfigTx.destTransferSize = kEDMA_TransferSize4Bytes;
-        transferConfigTx.minorLoopBytes = 4;
-        transferConfigTx.majorLoopCounts = 1;
+        transferConfigTx.minorLoopBytes   = 4;
+        transferConfigTx.majorLoopCounts  = 1;
 
         EDMA_TcdReset(softwareTCD_pcsContinuous);
         EDMA_TcdSetTransferConfig(softwareTCD_pcsContinuous, &transferConfigTx, NULL);
@@ -462,12 +504,12 @@ status_t LPSPI_MasterTransferEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t *
 
     if (handle->txData)
     {
-        transferConfigTx.srcAddr = (uint32_t)(handle->txData);
+        transferConfigTx.srcAddr   = (uint32_t)(handle->txData);
         transferConfigTx.srcOffset = 1;
     }
     else
     {
-        transferConfigTx.srcAddr = (uint32_t)(&handle->txBuffIfNull);
+        transferConfigTx.srcAddr   = (uint32_t)(&handle->txBuffIfNull);
         transferConfigTx.srcOffset = 0;
     }
 
@@ -480,7 +522,7 @@ status_t LPSPI_MasterTransferEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t *
     {
         case (1U):
             transferConfigTx.destTransferSize = kEDMA_TransferSize1Bytes;
-            transferConfigTx.minorLoopBytes = 1;
+            transferConfigTx.minorLoopBytes   = 1;
             if (handle->isByteSwap)
             {
                 dif = 3;
@@ -489,7 +531,7 @@ status_t LPSPI_MasterTransferEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t *
 
         case (2U):
             transferConfigTx.destTransferSize = kEDMA_TransferSize2Bytes;
-            transferConfigTx.minorLoopBytes = 2;
+            transferConfigTx.minorLoopBytes   = 2;
 
             if (handle->isByteSwap)
             {
@@ -499,12 +541,12 @@ status_t LPSPI_MasterTransferEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t *
 
         case (4U):
             transferConfigTx.destTransferSize = kEDMA_TransferSize4Bytes;
-            transferConfigTx.minorLoopBytes = 4;
+            transferConfigTx.minorLoopBytes   = 4;
             break;
 
         default:
             transferConfigTx.destTransferSize = kEDMA_TransferSize1Bytes;
-            transferConfigTx.minorLoopBytes = 1;
+            transferConfigTx.minorLoopBytes   = 1;
             assert(false);
             break;
     }
@@ -533,7 +575,6 @@ status_t LPSPI_MasterTransferEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t *
     EDMA_StartTransfer(handle->edmaRxRegToRxDataHandle);
 
     LPSPI_EnableDMA(base, kLPSPI_RxDmaEnable | kLPSPI_TxDmaEnable);
-    LPSPI_Enable(base, true);
 
     return kStatus_Success;
 }
@@ -579,6 +620,14 @@ static void EDMA_LpspiMasterCallback(edma_handle_t *edmaHandle,
     }
 }
 
+/*!
+ * brief LPSPI master aborts a transfer which is using eDMA.
+ *
+ * This function aborts a transfer which is using eDMA.
+ *
+ * param base LPSPI peripheral base address.
+ * param handle pointer to lpspi_master_edma_handle_t structure which stores the transfer state.
+ */
 void LPSPI_MasterTransferAbortEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t *handle)
 {
     assert(handle);
@@ -591,6 +640,16 @@ void LPSPI_MasterTransferAbortEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t
     handle->state = kLPSPI_Idle;
 }
 
+/*!
+ * brief Gets the master eDMA transfer remaining bytes.
+ *
+ * This function gets the master eDMA transfer remaining bytes.
+ *
+ * param base LPSPI peripheral base address.
+ * param handle pointer to lpspi_master_edma_handle_t structure which stores the transfer state.
+ * param count Number of bytes transferred so far by the EDMA transaction.
+ * return status of status_t.
+ */
 status_t LPSPI_MasterTransferGetCountEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t *handle, size_t *count)
 {
     assert(handle);
@@ -618,6 +677,26 @@ status_t LPSPI_MasterTransferGetCountEDMA(LPSPI_Type *base, lpspi_master_edma_ha
     return kStatus_Success;
 }
 
+/*!
+ * brief Initializes the LPSPI slave eDMA handle.
+ *
+ * This function initializes the LPSPI eDMA handle which can be used for other LPSPI transactional APIs.  Usually, for a
+ * specified LPSPI instance, call this API once to get the initialized handle.
+ *
+ * Note that LPSPI eDMA has a separated (Rx and Tx as two sources) or shared (Rx  and Tx as the same source) DMA request
+ * source.
+ *
+ * (1) For a separated DMA request source, enable and set the Rx DMAMUX source for edmaRxRegToRxDataHandle and
+ * Tx DMAMUX source for edmaTxDataToTxRegHandle.
+ * (2) For a shared DMA request source, enable and set the Rx/Rx DMAMUX source for edmaRxRegToRxDataHandle .
+ *
+ * param base LPSPI peripheral base address.
+ * param handle LPSPI handle pointer to lpspi_slave_edma_handle_t.
+ * param callback LPSPI callback.
+ * param userData callback function parameter.
+ * param edmaRxRegToRxDataHandle edmaRxRegToRxDataHandle pointer to edma_handle_t.
+ * param edmaTxDataToTxRegHandle edmaTxDataToTxRegHandle pointer to edma_handle_t.
+ */
 void LPSPI_SlaveTransferCreateHandleEDMA(LPSPI_Type *base,
                                          lpspi_slave_edma_handle_t *handle,
                                          lpspi_slave_edma_transfer_callback_t callback,
@@ -634,7 +713,7 @@ void LPSPI_SlaveTransferCreateHandleEDMA(LPSPI_Type *base,
 
     uint32_t instance = LPSPI_GetInstance(base);
 
-    s_lpspiSlaveEdmaPrivateHandle[instance].base = base;
+    s_lpspiSlaveEdmaPrivateHandle[instance].base   = base;
     s_lpspiSlaveEdmaPrivateHandle[instance].handle = handle;
 
     handle->callback = callback;
@@ -644,14 +723,31 @@ void LPSPI_SlaveTransferCreateHandleEDMA(LPSPI_Type *base,
     handle->edmaTxDataToTxRegHandle = edmaTxDataToTxRegHandle;
 }
 
+/*!
+ * brief LPSPI slave transfers data using eDMA.
+ *
+ * This function transfers data using eDMA. This is a non-blocking function, which return right away. When all data
+ * is transferred, the callback function is called.
+ *
+ * Note:
+ * The transfer data size should be an integer multiple of bytesPerFrame if bytesPerFrame is less than or equal to 4.
+ * For bytesPerFrame greater than 4:
+ * The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not an integer multiple of 4.
+ * Otherwise, the transfer data size can be an integer multiple of bytesPerFrame.
+ *
+ * param base LPSPI peripheral base address.
+ * param handle pointer to lpspi_slave_edma_handle_t structure which stores the transfer state.
+ * param transfer pointer to lpspi_transfer_t structure.
+ * return status of status_t.
+ */
 status_t LPSPI_SlaveTransferEDMA(LPSPI_Type *base, lpspi_slave_edma_handle_t *handle, lpspi_transfer_t *transfer)
 {
     assert(handle);
     assert(transfer);
 
-    uint32_t bitsPerFrame = ((base->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT) + 1;
+    uint32_t bitsPerFrame  = ((base->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT) + 1;
     uint32_t bytesPerFrame = (bitsPerFrame + 7) / 8;
-    uint32_t temp = 0U;
+    uint32_t temp          = 0U;
 
     uint8_t dummyData = g_lpspiDummyData[LPSPI_GetInstance(base)];
 
@@ -697,14 +793,14 @@ status_t LPSPI_SlaveTransferEDMA(LPSPI_Type *base, lpspi_slave_edma_handle_t *ha
 
     bool isThereExtraTxBytes = false;
 
-    handle->txData = transfer->txData;
-    handle->rxData = transfer->rxData;
+    handle->txData               = transfer->txData;
+    handle->rxData               = transfer->rxData;
     handle->txRemainingByteCount = transfer->dataSize;
     handle->rxRemainingByteCount = transfer->dataSize;
-    handle->totalByteCount = transfer->dataSize;
+    handle->totalByteCount       = transfer->dataSize;
 
     handle->writeRegRemainingTimes = (transfer->dataSize / bytesPerFrame) * ((bytesPerFrame + 3) / 4);
-    handle->readRegRemainingTimes = handle->writeRegRemainingTimes;
+    handle->readRegRemainingTimes  = handle->writeRegRemainingTimes;
 
     handle->txBuffIfNull =
         ((uint32_t)dummyData) | ((uint32_t)dummyData << 8) | ((uint32_t)dummyData << 16) | ((uint32_t)dummyData << 24);
@@ -735,6 +831,8 @@ status_t LPSPI_SlaveTransferEDMA(LPSPI_Type *base, lpspi_slave_edma_handle_t *ha
         }
     }
 
+    LPSPI_Enable(base, true);
+
     /*Flush FIFO , clear status , disable all the inerrupts.*/
     LPSPI_FlushFifo(base, true, true);
     LPSPI_ClearStatusFlags(base, kLPSPI_AllStatusFlag);
@@ -746,27 +844,27 @@ status_t LPSPI_SlaveTransferEDMA(LPSPI_Type *base, lpspi_slave_edma_handle_t *ha
     base->TCR = (base->TCR & ~(LPSPI_TCR_CONT_MASK | LPSPI_TCR_CONTC_MASK | LPSPI_TCR_BYSW_MASK)) |
                 LPSPI_TCR_CONTC(0U) | LPSPI_TCR_BYSW(handle->isByteSwap) | LPSPI_TCR_PCS(whichPcs);
 
-    isThereExtraTxBytes = false;
+    isThereExtraTxBytes         = false;
     handle->isThereExtraRxBytes = false;
 
     /*Calculate the bytes for write/read the TX/RX register each time*/
     if (bytesPerFrame <= 4)
     {
         handle->bytesEachWrite = bytesPerFrame;
-        handle->bytesEachRead = bytesPerFrame;
+        handle->bytesEachRead  = bytesPerFrame;
 
         handle->bytesLastRead = bytesPerFrame;
     }
     else
     {
         handle->bytesEachWrite = 4;
-        handle->bytesEachRead = 4;
+        handle->bytesEachRead  = 4;
 
         handle->bytesLastRead = 4;
 
         if ((transfer->dataSize % 4) != 0)
         {
-            bytesLastWrite = transfer->dataSize % 4;
+            bytesLastWrite        = transfer->dataSize % 4;
             handle->bytesLastRead = bytesLastWrite;
 
             isThereExtraTxBytes = true;
@@ -789,12 +887,12 @@ status_t LPSPI_SlaveTransferEDMA(LPSPI_Type *base, lpspi_slave_edma_handle_t *ha
 
         if (handle->rxData)
         {
-            transferConfigRx.destAddr = (uint32_t) & (handle->rxData[0]);
+            transferConfigRx.destAddr   = (uint32_t) & (handle->rxData[0]);
             transferConfigRx.destOffset = 1;
         }
         else
         {
-            transferConfigRx.destAddr = (uint32_t) & (handle->rxBuffIfNull);
+            transferConfigRx.destAddr   = (uint32_t) & (handle->rxBuffIfNull);
             transferConfigRx.destOffset = 0;
         }
         transferConfigRx.destTransferSize = kEDMA_TransferSize1Bytes;
@@ -804,7 +902,7 @@ status_t LPSPI_SlaveTransferEDMA(LPSPI_Type *base, lpspi_slave_edma_handle_t *ha
         {
             case (1U):
                 transferConfigRx.srcTransferSize = kEDMA_TransferSize1Bytes;
-                transferConfigRx.minorLoopBytes = 1;
+                transferConfigRx.minorLoopBytes  = 1;
                 if (handle->isByteSwap)
                 {
                     dif = 3;
@@ -813,7 +911,7 @@ status_t LPSPI_SlaveTransferEDMA(LPSPI_Type *base, lpspi_slave_edma_handle_t *ha
 
             case (2U):
                 transferConfigRx.srcTransferSize = kEDMA_TransferSize2Bytes;
-                transferConfigRx.minorLoopBytes = 2;
+                transferConfigRx.minorLoopBytes  = 2;
                 if (handle->isByteSwap)
                 {
                     dif = 2;
@@ -822,17 +920,17 @@ status_t LPSPI_SlaveTransferEDMA(LPSPI_Type *base, lpspi_slave_edma_handle_t *ha
 
             case (4U):
                 transferConfigRx.srcTransferSize = kEDMA_TransferSize4Bytes;
-                transferConfigRx.minorLoopBytes = 4;
+                transferConfigRx.minorLoopBytes  = 4;
                 break;
 
             default:
                 transferConfigRx.srcTransferSize = kEDMA_TransferSize1Bytes;
-                transferConfigRx.minorLoopBytes = 1;
+                transferConfigRx.minorLoopBytes  = 1;
                 assert(false);
                 break;
         }
 
-        transferConfigRx.srcAddr = (uint32_t)rxAddr + dif;
+        transferConfigRx.srcAddr   = (uint32_t)rxAddr + dif;
         transferConfigRx.srcOffset = 0;
 
         transferConfigRx.majorLoopCounts = handle->readRegRemainingTimes;
@@ -853,12 +951,12 @@ status_t LPSPI_SlaveTransferEDMA(LPSPI_Type *base, lpspi_slave_edma_handle_t *ha
     {
         if (handle->txData)
         {
-            transferConfigTx.srcAddr = (uint32_t) & (transfer->txData[transfer->dataSize - bytesLastWrite]);
+            transferConfigTx.srcAddr   = (uint32_t) & (transfer->txData[transfer->dataSize - bytesLastWrite]);
             transferConfigTx.srcOffset = 1;
         }
         else
         {
-            transferConfigTx.srcAddr = (uint32_t)(&handle->txBuffIfNull);
+            transferConfigTx.srcAddr   = (uint32_t)(&handle->txBuffIfNull);
             transferConfigTx.srcOffset = 0;
         }
 
@@ -871,7 +969,7 @@ status_t LPSPI_SlaveTransferEDMA(LPSPI_Type *base, lpspi_slave_edma_handle_t *ha
         {
             case (1U):
                 transferConfigTx.destTransferSize = kEDMA_TransferSize1Bytes;
-                transferConfigTx.minorLoopBytes = 1;
+                transferConfigTx.minorLoopBytes   = 1;
                 if (handle->isByteSwap)
                 {
                     dif = 3;
@@ -880,7 +978,7 @@ status_t LPSPI_SlaveTransferEDMA(LPSPI_Type *base, lpspi_slave_edma_handle_t *ha
 
             case (2U):
                 transferConfigTx.destTransferSize = kEDMA_TransferSize2Bytes;
-                transferConfigTx.minorLoopBytes = 2;
+                transferConfigTx.minorLoopBytes   = 2;
                 if (handle->isByteSwap)
                 {
                     dif = 2;
@@ -889,12 +987,12 @@ status_t LPSPI_SlaveTransferEDMA(LPSPI_Type *base, lpspi_slave_edma_handle_t *ha
 
             default:
                 transferConfigTx.destTransferSize = kEDMA_TransferSize1Bytes;
-                transferConfigTx.minorLoopBytes = 1;
+                transferConfigTx.minorLoopBytes   = 1;
                 assert(false);
                 break;
         }
 
-        transferConfigTx.destAddr = (uint32_t)txAddr + dif;
+        transferConfigTx.destAddr        = (uint32_t)txAddr + dif;
         transferConfigTx.majorLoopCounts = 1;
 
         EDMA_TcdReset(softwareTCD_extraBytes);
@@ -904,12 +1002,12 @@ status_t LPSPI_SlaveTransferEDMA(LPSPI_Type *base, lpspi_slave_edma_handle_t *ha
 
     if (handle->txData)
     {
-        transferConfigTx.srcAddr = (uint32_t)(handle->txData);
+        transferConfigTx.srcAddr   = (uint32_t)(handle->txData);
         transferConfigTx.srcOffset = 1;
     }
     else
     {
-        transferConfigTx.srcAddr = (uint32_t)(&handle->txBuffIfNull);
+        transferConfigTx.srcAddr   = (uint32_t)(&handle->txBuffIfNull);
         transferConfigTx.srcOffset = 0;
     }
 
@@ -922,7 +1020,7 @@ status_t LPSPI_SlaveTransferEDMA(LPSPI_Type *base, lpspi_slave_edma_handle_t *ha
     {
         case (1U):
             transferConfigTx.destTransferSize = kEDMA_TransferSize1Bytes;
-            transferConfigTx.minorLoopBytes = 1;
+            transferConfigTx.minorLoopBytes   = 1;
             if (handle->isByteSwap)
             {
                 dif = 3;
@@ -931,7 +1029,7 @@ status_t LPSPI_SlaveTransferEDMA(LPSPI_Type *base, lpspi_slave_edma_handle_t *ha
 
         case (2U):
             transferConfigTx.destTransferSize = kEDMA_TransferSize2Bytes;
-            transferConfigTx.minorLoopBytes = 2;
+            transferConfigTx.minorLoopBytes   = 2;
 
             if (handle->isByteSwap)
             {
@@ -941,12 +1039,12 @@ status_t LPSPI_SlaveTransferEDMA(LPSPI_Type *base, lpspi_slave_edma_handle_t *ha
 
         case (4U):
             transferConfigTx.destTransferSize = kEDMA_TransferSize4Bytes;
-            transferConfigTx.minorLoopBytes = 4;
+            transferConfigTx.minorLoopBytes   = 4;
             break;
 
         default:
             transferConfigTx.destTransferSize = kEDMA_TransferSize1Bytes;
-            transferConfigTx.minorLoopBytes = 1;
+            transferConfigTx.minorLoopBytes   = 1;
             assert(false);
             break;
     }
@@ -970,7 +1068,6 @@ status_t LPSPI_SlaveTransferEDMA(LPSPI_Type *base, lpspi_slave_edma_handle_t *ha
     EDMA_StartTransfer(handle->edmaRxRegToRxDataHandle);
 
     LPSPI_EnableDMA(base, kLPSPI_RxDmaEnable | kLPSPI_TxDmaEnable);
-    LPSPI_Enable(base, true);
 
     return kStatus_Success;
 }
@@ -1016,6 +1113,14 @@ static void EDMA_LpspiSlaveCallback(edma_handle_t *edmaHandle,
     }
 }
 
+/*!
+ * brief LPSPI slave aborts a transfer which is using eDMA.
+ *
+ * This function aborts a transfer which is using eDMA.
+ *
+ * param base LPSPI peripheral base address.
+ * param handle pointer to lpspi_slave_edma_handle_t structure which stores the transfer state.
+ */
 void LPSPI_SlaveTransferAbortEDMA(LPSPI_Type *base, lpspi_slave_edma_handle_t *handle)
 {
     assert(handle);
@@ -1028,6 +1133,16 @@ void LPSPI_SlaveTransferAbortEDMA(LPSPI_Type *base, lpspi_slave_edma_handle_t *h
     handle->state = kLPSPI_Idle;
 }
 
+/*!
+ * brief Gets the slave eDMA transfer remaining bytes.
+ *
+ * This function gets the slave eDMA transfer remaining bytes.
+ *
+ * param base LPSPI peripheral base address.
+ * param handle pointer to lpspi_slave_edma_handle_t structure which stores the transfer state.
+ * param count Number of bytes transferred so far by the eDMA transaction.
+ * return status of status_t.
+ */
 status_t LPSPI_SlaveTransferGetCountEDMA(LPSPI_Type *base, lpspi_slave_edma_handle_t *handle, size_t *count)
 {
     assert(handle);
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_lpspi_edma.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_lpspi_edma.h
index 54b71bed439..a2f9ef55e0a 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_lpspi_edma.h
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_lpspi_edma.h
@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
  * All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 #ifndef _FSL_LPSPI_EDMA_H_
 #define _FSL_LPSPI_EDMA_H_
@@ -52,13 +26,13 @@
 /*@}*/
 
 /*!
-* @brief Forward declaration of the _lpspi_master_edma_handle typedefs.
-*/
+ * @brief Forward declaration of the _lpspi_master_edma_handle typedefs.
+ */
 typedef struct _lpspi_master_edma_handle lpspi_master_edma_handle_t;
 
 /*!
-* @brief Forward declaration of the _lpspi_slave_edma_handle typedefs.
-*/
+ * @brief Forward declaration of the _lpspi_slave_edma_handle typedefs.
+ */
 typedef struct _lpspi_slave_edma_handle lpspi_slave_edma_handle_t;
 
 /*!
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_lpuart.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_lpuart.c
index 9664469c246..3a8a4370360 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_lpuart.c
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_lpuart.c
@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
+ * Copyright 2016-2018 NXP
  * All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include "fsl_lpuart.h"
@@ -78,7 +52,7 @@ static bool LPUART_TransferIsRxRingBufferFull(LPUART_Type *base, lpuart_handle_t
  * finished.
  *
  * @param base LPUART peripheral base address.
- * @param data Start addresss of the data to write.
+ * @param data Start address of the data to write.
  * @param length Size of the buffer to be sent.
  */
 static void LPUART_WriteNonBlocking(LPUART_Type *base, const uint8_t *data, size_t length);
@@ -90,7 +64,7 @@ static void LPUART_WriteNonBlocking(LPUART_Type *base, const uint8_t *data, size
  * sure the RX register is full or TX FIFO has data before calling this function.
  *
  * @param base LPUART peripheral base address.
- * @param data Start addresss of the buffer to store the received data.
+ * @param data Start address of the buffer to store the received data.
  * @param length Size of the buffer.
  */
 static void LPUART_ReadNonBlocking(LPUART_Type *base, uint8_t *data, size_t length);
@@ -126,6 +100,12 @@ static lpuart_isr_t s_lpuartIsr;
 /*******************************************************************************
  * Code
  ******************************************************************************/
+/*!
+ * brief Get the LPUART instance from peripheral base address.
+ *
+ * param base LPUART peripheral base address.
+ * return LPUART instance.
+ */
 uint32_t LPUART_GetInstance(LPUART_Type *base)
 {
     uint32_t instance;
@@ -144,19 +124,28 @@ uint32_t LPUART_GetInstance(LPUART_Type *base)
     return instance;
 }
 
+/*!
+ * brief Get the length of received data in RX ring buffer.
+ *
+ * userData handle LPUART handle pointer.
+ * return Length of received data in RX ring buffer.
+ */
 size_t LPUART_TransferGetRxRingBufferLength(LPUART_Type *base, lpuart_handle_t *handle)
 {
-    assert(handle);
+    assert(NULL != handle);
 
     size_t size;
+    size_t tmpRxRingBufferSize   = handle->rxRingBufferSize;
+    uint16_t tmpRxRingBufferTail = handle->rxRingBufferTail;
+    uint16_t tmpRxRingBufferHead = handle->rxRingBufferHead;
 
-    if (handle->rxRingBufferTail > handle->rxRingBufferHead)
+    if (tmpRxRingBufferTail > tmpRxRingBufferHead)
     {
-        size = (size_t)(handle->rxRingBufferHead + handle->rxRingBufferSize - handle->rxRingBufferTail);
+        size = ((size_t)tmpRxRingBufferHead + tmpRxRingBufferSize - (size_t)tmpRxRingBufferTail);
     }
     else
     {
-        size = (size_t)(handle->rxRingBufferHead - handle->rxRingBufferTail);
+        size = ((size_t)tmpRxRingBufferHead - (size_t)tmpRxRingBufferTail);
     }
 
     return size;
@@ -164,7 +153,7 @@ size_t LPUART_TransferGetRxRingBufferLength(LPUART_Type *base, lpuart_handle_t *
 
 static bool LPUART_TransferIsRxRingBufferFull(LPUART_Type *base, lpuart_handle_t *handle)
 {
-    assert(handle);
+    assert(NULL != handle);
 
     bool full;
 
@@ -181,7 +170,7 @@ static bool LPUART_TransferIsRxRingBufferFull(LPUART_Type *base, lpuart_handle_t
 
 static void LPUART_WriteNonBlocking(LPUART_Type *base, const uint8_t *data, size_t length)
 {
-    assert(data);
+    assert(NULL != data);
 
     size_t i;
 
@@ -195,7 +184,7 @@ static void LPUART_WriteNonBlocking(LPUART_Type *base, const uint8_t *data, size
 
 static void LPUART_ReadNonBlocking(LPUART_Type *base, uint8_t *data, size_t length)
 {
-    assert(data);
+    assert(NULL != data);
 
     size_t i;
 #if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
@@ -218,18 +207,42 @@ static void LPUART_ReadNonBlocking(LPUART_Type *base, uint8_t *data, size_t leng
             data[i] = base->DATA;
         }
 #else
-        data[i] = base->DATA;
+        data[i] = (uint8_t)(base->DATA);
 #endif
     }
 }
 
+/*!
+ * brief Initializes an LPUART instance with the user configuration structure and the peripheral clock.
+ *
+ * This function configures the LPUART module with user-defined settings. Call the LPUART_GetDefaultConfig() function
+ * to configure the configuration structure and get the default configuration.
+ * The example below shows how to use this API to configure the LPUART.
+ * code
+ *  lpuart_config_t lpuartConfig;
+ *  lpuartConfig.baudRate_Bps = 115200U;
+ *  lpuartConfig.parityMode = kLPUART_ParityDisabled;
+ *  lpuartConfig.dataBitsCount = kLPUART_EightDataBits;
+ *  lpuartConfig.isMsb = false;
+ *  lpuartConfig.stopBitCount = kLPUART_OneStopBit;
+ *  lpuartConfig.txFifoWatermark = 0;
+ *  lpuartConfig.rxFifoWatermark = 1;
+ *  LPUART_Init(LPUART1, &lpuartConfig, 20000000U);
+ * endcode
+ *
+ * param base LPUART peripheral base address.
+ * param config Pointer to a user-defined configuration structure.
+ * param srcClock_Hz LPUART clock source frequency in HZ.
+ * retval kStatus_LPUART_BaudrateNotSupport Baudrate is not support in current clock source.
+ * retval kStatus_Success LPUART initialize succeed
+ */
 status_t LPUART_Init(LPUART_Type *base, const lpuart_config_t *config, uint32_t srcClock_Hz)
 {
-    assert(config);
-    assert(config->baudRate_Bps);
+    assert(NULL != config);
+    assert(0U < config->baudRate_Bps);
 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
-    assert(FSL_FEATURE_LPUART_FIFO_SIZEn(base) >= config->txFifoWatermark);
-    assert(FSL_FEATURE_LPUART_FIFO_SIZEn(base) >= config->rxFifoWatermark);
+    assert((uint8_t)FSL_FEATURE_LPUART_FIFO_SIZEn(base) >= config->txFifoWatermark);
+    assert((uint8_t)FSL_FEATURE_LPUART_FIFO_SIZEn(base) >= config->rxFifoWatermark);
 #endif
 
     uint32_t temp;
@@ -243,16 +256,16 @@ status_t LPUART_Init(LPUART_Type *base, const lpuart_config_t *config, uint32_t
      * iterate through the rest of the supported values of OSR */
 
     baudDiff = config->baudRate_Bps;
-    osr = 0;
-    sbr = 0;
-    for (osrTemp = 4; osrTemp <= 32; osrTemp++)
+    osr      = 0;
+    sbr      = 0;
+    for (osrTemp = 4U; osrTemp <= 32U; osrTemp++)
     {
         /* calculate the temporary sbr value   */
-        sbrTemp = (srcClock_Hz / (config->baudRate_Bps * osrTemp));
+        sbrTemp = (uint16_t)((srcClock_Hz / (config->baudRate_Bps * osrTemp)));
         /*set sbrTemp to 1 if the sourceClockInHz can not satisfy the desired baud rate*/
-        if (sbrTemp == 0)
+        if (sbrTemp == 0U)
         {
-            sbrTemp = 1;
+            sbrTemp = 1U;
         }
         /* Calculate the baud rate based on the temporary OSR and SBR values */
         calculatedBaud = (srcClock_Hz / (osrTemp * sbrTemp));
@@ -260,23 +273,23 @@ status_t LPUART_Init(LPUART_Type *base, const lpuart_config_t *config, uint32_t
         tempDiff = calculatedBaud - config->baudRate_Bps;
 
         /* Select the better value between srb and (sbr + 1) */
-        if (tempDiff > (config->baudRate_Bps - (srcClock_Hz / (osrTemp * (sbrTemp + 1)))))
+        if (tempDiff > (config->baudRate_Bps - (srcClock_Hz / (osrTemp * ((uint32_t)sbrTemp + 1U)))))
         {
-            tempDiff = config->baudRate_Bps - (srcClock_Hz / (osrTemp * (sbrTemp + 1)));
+            tempDiff = config->baudRate_Bps - (srcClock_Hz / (osrTemp * ((uint32_t)sbrTemp + 1U)));
             sbrTemp++;
         }
 
         if (tempDiff <= baudDiff)
         {
             baudDiff = tempDiff;
-            osr = osrTemp; /* update and store the best OSR value calculated */
-            sbr = sbrTemp; /* update store the best SBR value calculated */
+            osr      = osrTemp; /* update and store the best OSR value calculated */
+            sbr      = sbrTemp; /* update store the best SBR value calculated */
         }
     }
 
     /* Check to see if actual baud rate is within 3% of desired baud rate
      * based on the best calculate OSR value */
-    if (baudDiff > ((config->baudRate_Bps / 100) * 3))
+    if (baudDiff > ((config->baudRate_Bps / 100U) * 3U))
     {
         /* Unacceptable baud rate difference of more than 3%*/
         return kStatus_LPUART_BaudrateNotSupport;
@@ -306,14 +319,14 @@ status_t LPUART_Init(LPUART_Type *base, const lpuart_config_t *config, uint32_t
 
     /* Acceptable baud rate, check if OSR is between 4x and 7x oversampling.
      * If so, then "BOTHEDGE" sampling must be turned on */
-    if ((osr > 3) && (osr < 8))
+    if ((osr > 3U) && (osr < 8U))
     {
         temp |= LPUART_BAUD_BOTHEDGE_MASK;
     }
 
     /* program the osr value (bit value is one less than actual value) */
     temp &= ~LPUART_BAUD_OSR_MASK;
-    temp |= LPUART_BAUD_OSR(osr - 1);
+    temp |= LPUART_BAUD_OSR(osr - 1U);
 
     /* write the sbr value to the BAUD registers */
     temp &= ~LPUART_BAUD_SBR_MASK;
@@ -322,9 +335,8 @@ status_t LPUART_Init(LPUART_Type *base, const lpuart_config_t *config, uint32_t
     /* Set bit count and parity mode. */
     base->BAUD &= ~LPUART_BAUD_M10_MASK;
 
-    temp = base->CTRL &
-           ~(LPUART_CTRL_PE_MASK | LPUART_CTRL_PT_MASK | LPUART_CTRL_M_MASK | LPUART_CTRL_ILT_MASK |
-             LPUART_CTRL_IDLECFG_MASK);
+    temp = base->CTRL & ~(LPUART_CTRL_PE_MASK | LPUART_CTRL_PT_MASK | LPUART_CTRL_M_MASK | LPUART_CTRL_ILT_MASK |
+                          LPUART_CTRL_IDLECFG_MASK);
 
     temp |=
         (uint8_t)config->parityMode | LPUART_CTRL_IDLECFG(config->rxIdleConfig) | LPUART_CTRL_ILT(config->rxIdleType);
@@ -354,7 +366,7 @@ status_t LPUART_Init(LPUART_Type *base, const lpuart_config_t *config, uint32_t
 
 #if defined(FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT
     /* set stop bit per char */
-    temp = base->BAUD & ~LPUART_BAUD_SBNS_MASK;
+    temp       = base->BAUD & ~LPUART_BAUD_SBNS_MASK;
     base->BAUD = temp | LPUART_BAUD_SBNS((uint8_t)config->stopBitCount);
 #endif
 
@@ -368,7 +380,7 @@ status_t LPUART_Init(LPUART_Type *base, const lpuart_config_t *config, uint32_t
        5 bytes are received. the last byte will be saved in FIFO but not trigger
        RX interrupt because the water mark is 2.
      */
-    base->WATER = (((uint32_t)(config->rxFifoWatermark) << 16) | config->txFifoWatermark);
+    base->WATER = (((uint32_t)(config->rxFifoWatermark) << 16U) | config->txFifoWatermark);
 
     /* Enable tx/rx FIFO */
     base->FIFO |= (LPUART_FIFO_TXFE_MASK | LPUART_FIFO_RXFE_MASK);
@@ -392,12 +404,12 @@ status_t LPUART_Init(LPUART_Type *base, const lpuart_config_t *config, uint32_t
 #if defined(FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT) && FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT
     /* Set the CTS configuration/TX CTS source. */
     base->MODIR |= LPUART_MODIR_TXCTSC(config->txCtsConfig) | LPUART_MODIR_TXCTSSRC(config->txCtsSource);
-    if (config->enableRxRTS)
+    if (true == config->enableRxRTS)
     {
         /* Enable the receiver RTS(request-to-send) function. */
         base->MODIR |= LPUART_MODIR_RXRTSE_MASK;
     }
-    if (config->enableTxCTS)
+    if (true == config->enableTxCTS)
     {
         /* Enable the CTS(clear-to-send) function. */
         base->MODIR |= LPUART_MODIR_TXCTSE_MASK;
@@ -405,7 +417,7 @@ status_t LPUART_Init(LPUART_Type *base, const lpuart_config_t *config, uint32_t
 #endif
 
     /* Set data bits order. */
-    if (config->isMsb)
+    if (true == config->isMsb)
     {
         temp |= LPUART_STAT_MSBF_MASK;
     }
@@ -418,12 +430,12 @@ status_t LPUART_Init(LPUART_Type *base, const lpuart_config_t *config, uint32_t
 
     /* Enable TX/RX base on configure structure. */
     temp = base->CTRL;
-    if (config->enableTx)
+    if (true == config->enableTx)
     {
         temp |= LPUART_CTRL_TE_MASK;
     }
 
-    if (config->enableRx)
+    if (true == config->enableRx)
     {
         temp |= LPUART_CTRL_RE_MASK;
     }
@@ -432,18 +444,25 @@ status_t LPUART_Init(LPUART_Type *base, const lpuart_config_t *config, uint32_t
 
     return kStatus_Success;
 }
+/*!
+ * brief Deinitializes a LPUART instance.
+ *
+ * This function waits for transmit to complete, disables TX and RX, and disables the LPUART clock.
+ *
+ * param base LPUART peripheral base address.
+ */
 void LPUART_Deinit(LPUART_Type *base)
 {
     uint32_t temp;
 
 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
     /* Wait tx FIFO send out*/
-    while (0 != ((base->WATER & LPUART_WATER_TXCOUNT_MASK) >> LPUART_WATER_TXWATER_SHIFT))
+    while (0U != ((base->WATER & LPUART_WATER_TXCOUNT_MASK) >> LPUART_WATER_TXWATER_SHIFT))
     {
     }
 #endif
-    /* Wait last char shoft out */
-    while (0 == (base->STAT & LPUART_STAT_TC_MASK))
+    /* Wait last char shift out */
+    while (0U == (base->STAT & LPUART_STAT_TC_MASK))
     {
     }
 
@@ -477,14 +496,36 @@ void LPUART_Deinit(LPUART_Type *base)
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }
 
+/*!
+ * brief Gets the default configuration structure.
+ *
+ * This function initializes the LPUART configuration structure to a default value. The default
+ * values are:
+ *   lpuartConfig->baudRate_Bps = 115200U;
+ *   lpuartConfig->parityMode = kLPUART_ParityDisabled;
+ *   lpuartConfig->dataBitsCount = kLPUART_EightDataBits;
+ *   lpuartConfig->isMsb = false;
+ *   lpuartConfig->stopBitCount = kLPUART_OneStopBit;
+ *   lpuartConfig->txFifoWatermark = 0;
+ *   lpuartConfig->rxFifoWatermark = 1;
+ *   lpuartConfig->rxIdleType = kLPUART_IdleTypeStartBit;
+ *   lpuartConfig->rxIdleConfig = kLPUART_IdleCharacter1;
+ *   lpuartConfig->enableTx = false;
+ *   lpuartConfig->enableRx = false;
+ *
+ * param config Pointer to a configuration structure.
+ */
 void LPUART_GetDefaultConfig(lpuart_config_t *config)
 {
-    assert(config);
+    assert(NULL != config);
 
-    config->baudRate_Bps = 115200U;
-    config->parityMode = kLPUART_ParityDisabled;
+    /* Initializes the configure structure to zero. */
+    (void)memset(config, 0, sizeof(*config));
+
+    config->baudRate_Bps  = 115200U;
+    config->parityMode    = kLPUART_ParityDisabled;
     config->dataBitsCount = kLPUART_EightDataBits;
-    config->isMsb = false;
+    config->isMsb         = false;
 #if defined(FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT
     config->stopBitCount = kLPUART_OneStopBit;
 #endif
@@ -498,15 +539,30 @@ void LPUART_GetDefaultConfig(lpuart_config_t *config)
     config->txCtsConfig = kLPUART_CtsSampleAtStart;
     config->txCtsSource = kLPUART_CtsSourcePin;
 #endif
-    config->rxIdleType = kLPUART_IdleTypeStartBit;
+    config->rxIdleType   = kLPUART_IdleTypeStartBit;
     config->rxIdleConfig = kLPUART_IdleCharacter1;
-    config->enableTx = false;
-    config->enableRx = false;
+    config->enableTx     = false;
+    config->enableRx     = false;
 }
 
+/*!
+ * brief Sets the LPUART instance baudrate.
+ *
+ * This function configures the LPUART module baudrate. This function is used to update
+ * the LPUART module baudrate after the LPUART module is initialized by the LPUART_Init.
+ * code
+ *  LPUART_SetBaudRate(LPUART1, 115200U, 20000000U);
+ * endcode
+ *
+ * param base LPUART peripheral base address.
+ * param baudRate_Bps LPUART baudrate to be set.
+ * param srcClock_Hz LPUART clock source frequency in HZ.
+ * retval kStatus_LPUART_BaudrateNotSupport Baudrate is not supported in the current clock source.
+ * retval kStatus_Success Set baudrate succeeded.
+ */
 status_t LPUART_SetBaudRate(LPUART_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz)
 {
-    assert(baudRate_Bps);
+    assert(0U < baudRate_Bps);
 
     uint32_t temp, oldCtrl;
     uint16_t sbr, sbrTemp;
@@ -519,40 +575,40 @@ status_t LPUART_SetBaudRate(LPUART_Type *base, uint32_t baudRate_Bps, uint32_t s
      * iterate through the rest of the supported values of OSR */
 
     baudDiff = baudRate_Bps;
-    osr = 0;
-    sbr = 0;
-    for (osrTemp = 4; osrTemp <= 32; osrTemp++)
+    osr      = 0;
+    sbr      = 0;
+    for (osrTemp = 4u; osrTemp <= 32u; osrTemp++)
     {
         /* calculate the temporary sbr value   */
-        sbrTemp = (srcClock_Hz / (baudRate_Bps * osrTemp));
+        sbrTemp = (uint16_t)(srcClock_Hz / (baudRate_Bps * osrTemp));
         /*set sbrTemp to 1 if the sourceClockInHz can not satisfy the desired baud rate*/
-        if (sbrTemp == 0)
+        if (sbrTemp == 0u)
         {
-            sbrTemp = 1;
+            sbrTemp = 1u;
         }
         /* Calculate the baud rate based on the temporary OSR and SBR values */
-        calculatedBaud = (srcClock_Hz / (osrTemp * sbrTemp));
+        calculatedBaud = (uint16_t)((srcClock_Hz / (osrTemp * sbrTemp)));
 
         tempDiff = calculatedBaud - baudRate_Bps;
 
         /* Select the better value between srb and (sbr + 1) */
-        if (tempDiff > (baudRate_Bps - (srcClock_Hz / (osrTemp * (sbrTemp + 1)))))
+        if (tempDiff > (baudRate_Bps - (srcClock_Hz / (osrTemp * ((uint32_t)sbrTemp + 1u)))))
         {
-            tempDiff = baudRate_Bps - (srcClock_Hz / (osrTemp * (sbrTemp + 1)));
+            tempDiff = baudRate_Bps - (srcClock_Hz / (osrTemp * ((uint32_t)sbrTemp + 1u)));
             sbrTemp++;
         }
 
         if (tempDiff <= baudDiff)
         {
             baudDiff = tempDiff;
-            osr = osrTemp; /* update and store the best OSR value calculated */
-            sbr = sbrTemp; /* update store the best SBR value calculated */
+            osr      = osrTemp; /* update and store the best OSR value calculated */
+            sbr      = sbrTemp; /* update store the best SBR value calculated */
         }
     }
 
     /* Check to see if actual baud rate is within 3% of desired baud rate
      * based on the best calculate OSR value */
-    if (baudDiff < ((baudRate_Bps / 100) * 3))
+    if (baudDiff < (uint32_t)((baudRate_Bps / 100u) * 3u))
     {
         /* Store CTRL before disable Tx and Rx */
         oldCtrl = base->CTRL;
@@ -564,14 +620,14 @@ status_t LPUART_SetBaudRate(LPUART_Type *base, uint32_t baudRate_Bps, uint32_t s
 
         /* Acceptable baud rate, check if OSR is between 4x and 7x oversampling.
          * If so, then "BOTHEDGE" sampling must be turned on */
-        if ((osr > 3) && (osr < 8))
+        if ((osr > 3u) && (osr < 8u))
         {
             temp |= LPUART_BAUD_BOTHEDGE_MASK;
         }
 
         /* program the osr value (bit value is one less than actual value) */
         temp &= ~LPUART_BAUD_OSR_MASK;
-        temp |= LPUART_BAUD_OSR(osr - 1);
+        temp |= LPUART_BAUD_OSR(osr - 1u);
 
         /* write the sbr value to the BAUD registers */
         temp &= ~LPUART_BAUD_SBR_MASK;
@@ -589,40 +645,103 @@ status_t LPUART_SetBaudRate(LPUART_Type *base, uint32_t baudRate_Bps, uint32_t s
     }
 }
 
+/*!
+ * brief Enables LPUART interrupts according to a provided mask.
+ *
+ * This function enables the LPUART interrupts according to a provided mask. The mask
+ * is a logical OR of enumeration members. See the ref _lpuart_interrupt_enable.
+ * This examples shows how to enable TX empty interrupt and RX full interrupt:
+ * code
+ *     LPUART_EnableInterrupts(LPUART1,kLPUART_TxDataRegEmptyInterruptEnable | kLPUART_RxDataRegFullInterruptEnable);
+ * endcode
+ *
+ * param base LPUART peripheral base address.
+ * param mask The interrupts to enable. Logical OR of ref _uart_interrupt_enable.
+ */
 void LPUART_EnableInterrupts(LPUART_Type *base, uint32_t mask)
 {
-    base->BAUD |= ((mask << 8) & (LPUART_BAUD_LBKDIE_MASK | LPUART_BAUD_RXEDGIE_MASK));
+    base->BAUD |= ((mask << 8U) & (LPUART_BAUD_LBKDIE_MASK | LPUART_BAUD_RXEDGIE_MASK));
 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
     base->FIFO = (base->FIFO & ~(LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK)) |
-                 ((mask << 8) & (LPUART_FIFO_TXOFE_MASK | LPUART_FIFO_RXUFE_MASK));
+                 ((mask << 8U) & (LPUART_FIFO_TXOFE_MASK | LPUART_FIFO_RXUFE_MASK));
 #endif
     mask &= 0xFFFFFF00U;
     base->CTRL |= mask;
 }
 
+/*!
+ * brief Disables  LPUART interrupts according to a provided mask.
+ *
+ * This function disables the LPUART interrupts according to a provided mask. The mask
+ * is a logical OR of enumeration members. See ref _lpuart_interrupt_enable.
+ * This example shows how to disable the TX empty interrupt and RX full interrupt:
+ * code
+ *     LPUART_DisableInterrupts(LPUART1,kLPUART_TxDataRegEmptyInterruptEnable | kLPUART_RxDataRegFullInterruptEnable);
+ * endcode
+ *
+ * param base LPUART peripheral base address.
+ * param mask The interrupts to disable. Logical OR of ref _lpuart_interrupt_enable.
+ */
 void LPUART_DisableInterrupts(LPUART_Type *base, uint32_t mask)
 {
-    base->BAUD &= ~((mask << 8) & (LPUART_BAUD_LBKDIE_MASK | LPUART_BAUD_RXEDGIE_MASK));
+    base->BAUD &= ~((mask << 8U) & (LPUART_BAUD_LBKDIE_MASK | LPUART_BAUD_RXEDGIE_MASK));
 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
     base->FIFO = (base->FIFO & ~(LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK)) &
-                 ~((mask << 8) & (LPUART_FIFO_TXOFE_MASK | LPUART_FIFO_RXUFE_MASK));
+                 ~((mask << 8U) & (LPUART_FIFO_TXOFE_MASK | LPUART_FIFO_RXUFE_MASK));
 #endif
     mask &= 0xFFFFFF00U;
     base->CTRL &= ~mask;
 }
 
+/*!
+ * brief Gets enabled LPUART interrupts.
+ *
+ * This function gets the enabled LPUART interrupts. The enabled interrupts are returned
+ * as the logical OR value of the enumerators ref _lpuart_interrupt_enable. To check
+ * a specific interrupt enable status, compare the return value with enumerators
+ * in ref _lpuart_interrupt_enable.
+ * For example, to check whether the TX empty interrupt is enabled:
+ * code
+ *     uint32_t enabledInterrupts = LPUART_GetEnabledInterrupts(LPUART1);
+ *
+ *     if (kLPUART_TxDataRegEmptyInterruptEnable & enabledInterrupts)
+ *     {
+ *         ...
+ *     }
+ * endcode
+ *
+ * param base LPUART peripheral base address.
+ * return LPUART interrupt flags which are logical OR of the enumerators in ref _lpuart_interrupt_enable.
+ */
 uint32_t LPUART_GetEnabledInterrupts(LPUART_Type *base)
 {
     uint32_t temp;
-    temp = (base->BAUD & (LPUART_BAUD_LBKDIE_MASK | LPUART_BAUD_RXEDGIE_MASK)) >> 8;
+    temp = (base->BAUD & (LPUART_BAUD_LBKDIE_MASK | LPUART_BAUD_RXEDGIE_MASK)) >> 8U;
 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
-    temp |= (base->FIFO & (LPUART_FIFO_TXOFE_MASK | LPUART_FIFO_RXUFE_MASK)) >> 8;
+    temp |= (base->FIFO & (LPUART_FIFO_TXOFE_MASK | LPUART_FIFO_RXUFE_MASK)) >> 8U;
 #endif
-    temp |= (base->CTRL & 0xFF0C000);
+    temp |= (uint32_t)(base->CTRL & 0xFF0C000u);
 
     return temp;
 }
 
+/*!
+ * brief Gets LPUART status flags.
+ *
+ * This function gets all LPUART status flags. The flags are returned as the logical
+ * OR value of the enumerators ref _lpuart_flags. To check for a specific status,
+ * compare the return value with enumerators in the ref _lpuart_flags.
+ * For example, to check whether the TX is empty:
+ * code
+ *     if (kLPUART_TxDataRegEmptyFlag & LPUART_GetStatusFlags(LPUART1))
+ *     {
+ *         ...
+ *     }
+ * endcode
+ *
+ * param base LPUART peripheral base address.
+ * return LPUART status flags which are ORed by the enumerators in the _lpuart_flags.
+ */
 uint32_t LPUART_GetStatusFlags(LPUART_Type *base)
 {
     uint32_t temp;
@@ -630,11 +749,30 @@ uint32_t LPUART_GetStatusFlags(LPUART_Type *base)
 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
     temp |= (base->FIFO &
              (LPUART_FIFO_TXEMPT_MASK | LPUART_FIFO_RXEMPT_MASK | LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK)) >>
-            16;
+            16U;
 #endif
     return temp;
 }
 
+/*!
+ * brief Clears status flags with a provided mask.
+ *
+ * This function clears LPUART status flags with a provided mask. Automatically cleared flags
+ * can't be cleared by this function.
+ * Flags that can only cleared or set by hardware are:
+ *    kLPUART_TxDataRegEmptyFlag, kLPUART_TransmissionCompleteFlag, kLPUART_RxDataRegFullFlag,
+ *    kLPUART_RxActiveFlag, kLPUART_NoiseErrorInRxDataRegFlag, kLPUART_ParityErrorInRxDataRegFlag,
+ *    kLPUART_TxFifoEmptyFlag,kLPUART_RxFifoEmptyFlag
+ * Note: This API should be called when the Tx/Rx is idle, otherwise it takes no effects.
+ *
+ * param base LPUART peripheral base address.
+ * param mask the status flags to be cleared. The user can use the enumerators in the
+ *  _lpuart_status_flag_t to do the OR operation and get the mask.
+ * return 0 succeed, others failed.
+ * retval kStatus_LPUART_FlagCannotClearManually The flag can't be cleared by this function but
+ *         it is cleared automatically by hardware.
+ * retval kStatus_Success Status in the mask are cleared.
+ */
 status_t LPUART_ClearStatusFlags(LPUART_Type *base, uint32_t mask)
 {
     uint32_t temp;
@@ -642,7 +780,7 @@ status_t LPUART_ClearStatusFlags(LPUART_Type *base, uint32_t mask)
 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
     temp = (uint32_t)base->FIFO;
     temp &= (uint32_t)(~(LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK));
-    temp |= (mask << 16) & (LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK);
+    temp |= (mask << 16U) & (LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK);
     base->FIFO = temp;
 #endif
     temp = (uint32_t)base->STAT;
@@ -660,7 +798,7 @@ status_t LPUART_ClearStatusFlags(LPUART_Type *base, uint32_t mask)
 #endif
     base->STAT = temp;
     /* If some flags still pending. */
-    if (mask & LPUART_GetStatusFlags(base))
+    if (0U != (mask & LPUART_GetStatusFlags(base)))
     {
         /* Some flags can only clear or set by the hardware itself, these flags are: kLPUART_TxDataRegEmptyFlag,
         kLPUART_TransmissionCompleteFlag, kLPUART_RxDataRegFullFlag, kLPUART_RxActiveFlag,
@@ -676,91 +814,153 @@ status_t LPUART_ClearStatusFlags(LPUART_Type *base, uint32_t mask)
     return status;
 }
 
+/*!
+ * brief Writes to the transmitter register using a blocking method.
+ *
+ * This function polls the transmitter register, waits for the register to be empty or  for TX FIFO to have
+ * room, and writes data to the transmitter buffer.
+ *
+ * note This function does not check whether all data has been sent out to the bus.
+ * Before disabling the transmitter, check the kLPUART_TransmissionCompleteFlag to ensure that the transmit is
+ * finished.
+ *
+ * param base LPUART peripheral base address.
+ * param data Start address of the data to write.
+ * param length Size of the data to write.
+ */
 void LPUART_WriteBlocking(LPUART_Type *base, const uint8_t *data, size_t length)
 {
-    assert(data);
+    assert(NULL != data);
+
+    const uint8_t *dataAddress = data;
+    size_t transferSize        = length;
 
     /* This API can only ensure that the data is written into the data buffer but can't
     ensure all data in the data buffer are sent into the transmit shift buffer. */
-    while (length--)
+    while (0U != transferSize)
     {
-        while (!(base->STAT & LPUART_STAT_TDRE_MASK))
+        while (0U == (base->STAT & LPUART_STAT_TDRE_MASK))
         {
         }
-        base->DATA = *(data++);
+        base->DATA = *(dataAddress);
+        dataAddress++;
+        transferSize--;
     }
 }
 
+/*!
+ * brief Reads the receiver data register using a blocking method.
+ *
+ * This function polls the receiver register, waits for the receiver register full or receiver FIFO
+ * has data, and reads data from the TX register.
+ *
+ * param base LPUART peripheral base address.
+ * param data Start address of the buffer to store the received data.
+ * param length Size of the buffer.
+ * retval kStatus_LPUART_RxHardwareOverrun Receiver overrun happened while receiving data.
+ * retval kStatus_LPUART_NoiseError Noise error happened while receiving data.
+ * retval kStatus_LPUART_FramingError Framing error happened while receiving data.
+ * retval kStatus_LPUART_ParityError Parity error happened while receiving data.
+ * retval kStatus_Success Successfully received all data.
+ */
 status_t LPUART_ReadBlocking(LPUART_Type *base, uint8_t *data, size_t length)
 {
-    assert(data);
+    assert(NULL != data);
 
     uint32_t statusFlag;
+    uint8_t *dataAddress = data;
+
 #if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
     uint32_t ctrl = base->CTRL;
     bool isSevenDataBits =
         ((ctrl & LPUART_CTRL_M7_MASK) || ((!(ctrl & LPUART_CTRL_M_MASK)) && (ctrl & LPUART_CTRL_PE_MASK)));
 #endif
 
-    while (length--)
+    while (0U != (length--))
     {
 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
-        while (0 == ((base->WATER & LPUART_WATER_RXCOUNT_MASK) >> LPUART_WATER_RXCOUNT_SHIFT))
+        while (0U == ((base->WATER & LPUART_WATER_RXCOUNT_MASK) >> LPUART_WATER_RXCOUNT_SHIFT))
 #else
-        while (!(base->STAT & LPUART_STAT_RDRF_MASK))
+        while (0U == (base->STAT & LPUART_STAT_RDRF_MASK))
 #endif
         {
             statusFlag = LPUART_GetStatusFlags(base);
 
-            if (statusFlag & kLPUART_RxOverrunFlag)
+            if ((uint32_t)kLPUART_RxOverrunFlag == (statusFlag & (uint32_t)kLPUART_RxOverrunFlag))
             {
-                LPUART_ClearStatusFlags(base, kLPUART_RxOverrunFlag);
-                return kStatus_LPUART_RxHardwareOverrun;
+                return ((kStatus_Success == LPUART_ClearStatusFlags(base, (uint32_t)kLPUART_RxOverrunFlag)) ?
+                            (kStatus_LPUART_RxHardwareOverrun) :
+                            (kStatus_LPUART_FlagCannotClearManually));
             }
 
-            if (statusFlag & kLPUART_NoiseErrorFlag)
+            if ((uint32_t)kLPUART_NoiseErrorFlag == (statusFlag & (uint32_t)kLPUART_NoiseErrorFlag))
             {
-                LPUART_ClearStatusFlags(base, kLPUART_NoiseErrorFlag);
-                return kStatus_LPUART_NoiseError;
+                return ((kStatus_Success == LPUART_ClearStatusFlags(base, (uint32_t)kLPUART_NoiseErrorFlag)) ?
+                            (kStatus_LPUART_NoiseError) :
+                            (kStatus_LPUART_FlagCannotClearManually));
             }
 
-            if (statusFlag & kLPUART_FramingErrorFlag)
+            if ((uint32_t)kLPUART_FramingErrorFlag == (statusFlag & (uint32_t)kLPUART_FramingErrorFlag))
             {
-                LPUART_ClearStatusFlags(base, kLPUART_FramingErrorFlag);
-                return kStatus_LPUART_FramingError;
+                return ((kStatus_Success == LPUART_ClearStatusFlags(base, (uint32_t)kLPUART_FramingErrorFlag)) ?
+                            (kStatus_LPUART_FramingError) :
+                            (kStatus_LPUART_FlagCannotClearManually));
             }
 
-            if (statusFlag & kLPUART_ParityErrorFlag)
+            if ((uint32_t)kLPUART_ParityErrorFlag == (statusFlag & (uint32_t)kLPUART_ParityErrorFlag))
             {
-                LPUART_ClearStatusFlags(base, kLPUART_ParityErrorFlag);
-                return kStatus_LPUART_ParityError;
+                return ((kStatus_Success == LPUART_ClearStatusFlags(base, (uint32_t)kLPUART_ParityErrorFlag)) ?
+                            (kStatus_LPUART_ParityError) :
+                            (kStatus_LPUART_FlagCannotClearManually));
             }
         }
 #if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
         if (isSevenDataBits)
         {
-            *(data++) = (base->DATA & 0x7F);
+            *(dataAddress) = (uint8_t)(base->DATA & 0x7F);
+            dataAddress++;
         }
         else
         {
-            *(data++) = base->DATA;
+            *(dataAddress) = (uint8_t)base->DATA;
+            dataAddress++;
         }
 #else
-        *(data++) = base->DATA;
+        *(dataAddress) = (uint8_t)base->DATA;
+        dataAddress++;
 #endif
     }
 
     return kStatus_Success;
 }
 
+/*!
+ * brief Initializes the LPUART handle.
+ *
+ * This function initializes the LPUART handle, which can be used for other LPUART
+ * transactional APIs. Usually, for a specified LPUART instance,
+ * call this API once to get the initialized handle.
+ *
+ * The LPUART driver supports the "background" receiving, which means that user can set up
+ * an RX ring buffer optionally. Data received is stored into the ring buffer even when the
+ * user doesn't call the LPUART_TransferReceiveNonBlocking() API. If there is already data received
+ * in the ring buffer, the user can get the received data from the ring buffer directly.
+ * The ring buffer is disabled if passing NULL as p ringBuffer.
+ *
+ * param base LPUART peripheral base address.
+ * param handle LPUART handle pointer.
+ * param callback Callback function.
+ * param userData User data.
+ */
 void LPUART_TransferCreateHandle(LPUART_Type *base,
                                  lpuart_handle_t *handle,
                                  lpuart_transfer_callback_t callback,
                                  void *userData)
 {
-    assert(handle);
+    assert(NULL != handle);
 
     uint32_t instance;
+
 #if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
     uint32_t ctrl = base->CTRL;
     bool isSevenDataBits =
@@ -768,11 +968,11 @@ void LPUART_TransferCreateHandle(LPUART_Type *base,
 #endif
 
     /* Zero the handle. */
-    memset(handle, 0, sizeof(lpuart_handle_t));
+    (void)memset(handle, 0, sizeof(lpuart_handle_t));
 
     /* Set the TX/RX state. */
-    handle->rxState = kLPUART_RxIdle;
-    handle->txState = kLPUART_TxIdle;
+    handle->rxState = (uint8_t)kLPUART_RxIdle;
+    handle->txState = (uint8_t)kLPUART_TxIdle;
 
     /* Set the callback and user data. */
     handle->callback = callback;
@@ -793,69 +993,115 @@ void LPUART_TransferCreateHandle(LPUART_Type *base,
 
 /* Enable interrupt in NVIC. */
 #if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
-    EnableIRQ(s_lpuartRxIRQ[instance]);
-    EnableIRQ(s_lpuartTxIRQ[instance]);
+    (void)EnableIRQ(s_lpuartRxIRQ[instance]);
+    (void)EnableIRQ(s_lpuartTxIRQ[instance]);
 #else
-    EnableIRQ(s_lpuartIRQ[instance]);
+    (void)EnableIRQ(s_lpuartIRQ[instance]);
 #endif
 }
 
+/*!
+ * brief Sets up the RX ring buffer.
+ *
+ * This function sets up the RX ring buffer to a specific UART handle.
+ *
+ * When the RX ring buffer is used, data received is stored into the ring buffer even when
+ * the user doesn't call the UART_TransferReceiveNonBlocking() API. If there is already data received
+ * in the ring buffer, the user can get the received data from the ring buffer directly.
+ *
+ * note When using RX ring buffer, one byte is reserved for internal use. In other
+ * words, if p ringBufferSize is 32, then only 31 bytes are used for saving data.
+ *
+ * param base LPUART peripheral base address.
+ * param handle LPUART handle pointer.
+ * param ringBuffer Start address of ring buffer for background receiving. Pass NULL to disable the ring buffer.
+ * param ringBufferSize size of the ring buffer.
+ */
 void LPUART_TransferStartRingBuffer(LPUART_Type *base,
                                     lpuart_handle_t *handle,
                                     uint8_t *ringBuffer,
                                     size_t ringBufferSize)
 {
-    assert(handle);
-    assert(ringBuffer);
+    assert(NULL != handle);
+    assert(NULL != ringBuffer);
 
     /* Setup the ring buffer address */
-    handle->rxRingBuffer = ringBuffer;
+    handle->rxRingBuffer     = ringBuffer;
     handle->rxRingBufferSize = ringBufferSize;
     handle->rxRingBufferHead = 0U;
     handle->rxRingBufferTail = 0U;
 
     /* Enable the interrupt to accept the data when user need the ring buffer. */
-    LPUART_EnableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable | kLPUART_RxOverrunInterruptEnable);
+    LPUART_EnableInterrupts(
+        base, (uint32_t)kLPUART_RxDataRegFullInterruptEnable | (uint32_t)kLPUART_RxOverrunInterruptEnable);
 }
 
+/*!
+ * brief Aborts the background transfer and uninstalls the ring buffer.
+ *
+ * This function aborts the background transfer and uninstalls the ring buffer.
+ *
+ * param base LPUART peripheral base address.
+ * param handle LPUART handle pointer.
+ */
 void LPUART_TransferStopRingBuffer(LPUART_Type *base, lpuart_handle_t *handle)
 {
-    assert(handle);
+    assert(NULL != handle);
 
-    if (handle->rxState == kLPUART_RxIdle)
+    if (handle->rxState == (uint8_t)kLPUART_RxIdle)
     {
-        LPUART_DisableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable | kLPUART_RxOverrunInterruptEnable);
+        LPUART_DisableInterrupts(
+            base, (uint32_t)kLPUART_RxDataRegFullInterruptEnable | (uint32_t)kLPUART_RxOverrunInterruptEnable);
     }
 
-    handle->rxRingBuffer = NULL;
+    handle->rxRingBuffer     = NULL;
     handle->rxRingBufferSize = 0U;
     handle->rxRingBufferHead = 0U;
     handle->rxRingBufferTail = 0U;
 }
 
+/*!
+ * brief Transmits a buffer of data using the interrupt method.
+ *
+ * This function send data using an interrupt method. This is a non-blocking function, which
+ * returns directly without waiting for all data written to the transmitter register. When
+ * all data is written to the TX register in the ISR, the LPUART driver calls the callback
+ * function and passes the ref kStatus_LPUART_TxIdle as status parameter.
+ *
+ * note The kStatus_LPUART_TxIdle is passed to the upper layer when all data are written
+ * to the TX register. However, there is no check to ensure that all the data sent out. Before disabling the TX,
+ * check the kLPUART_TransmissionCompleteFlag to ensure that the transmit is finished.
+ *
+ * param base LPUART peripheral base address.
+ * param handle LPUART handle pointer.
+ * param xfer LPUART transfer structure, see #lpuart_transfer_t.
+ * retval kStatus_Success Successfully start the data transmission.
+ * retval kStatus_LPUART_TxBusy Previous transmission still not finished, data not all written to the TX register.
+ * retval kStatus_InvalidArgument Invalid argument.
+ */
 status_t LPUART_TransferSendNonBlocking(LPUART_Type *base, lpuart_handle_t *handle, lpuart_transfer_t *xfer)
 {
-    assert(handle);
-    assert(xfer);
-    assert(xfer->data);
-    assert(xfer->dataSize);
+    assert(NULL != handle);
+    assert(NULL != xfer);
+    assert(NULL != xfer->data);
+    assert(0U != xfer->dataSize);
 
     status_t status;
 
     /* Return error if current TX busy. */
-    if (kLPUART_TxBusy == handle->txState)
+    if ((uint8_t)kLPUART_TxBusy == handle->txState)
     {
         status = kStatus_LPUART_TxBusy;
     }
     else
     {
-        handle->txData = xfer->data;
-        handle->txDataSize = xfer->dataSize;
+        handle->txData        = xfer->data;
+        handle->txDataSize    = xfer->dataSize;
         handle->txDataSizeAll = xfer->dataSize;
-        handle->txState = kLPUART_TxBusy;
+        handle->txState       = (uint8_t)kLPUART_TxBusy;
 
-        /* Enable transmiter interrupt. */
-        LPUART_EnableInterrupts(base, kLPUART_TxDataRegEmptyInterruptEnable);
+        /* Enable transmitter interrupt. */
+        LPUART_EnableInterrupts(base, (uint32_t)kLPUART_TxDataRegEmptyInterruptEnable);
 
         status = kStatus_Success;
     }
@@ -863,22 +1109,45 @@ status_t LPUART_TransferSendNonBlocking(LPUART_Type *base, lpuart_handle_t *hand
     return status;
 }
 
+/*!
+ * brief Aborts the interrupt-driven data transmit.
+ *
+ * This function aborts the interrupt driven data sending. The user can get the remainBtyes to find out
+ * how many bytes are not sent out.
+ *
+ * param base LPUART peripheral base address.
+ * param handle LPUART handle pointer.
+ */
 void LPUART_TransferAbortSend(LPUART_Type *base, lpuart_handle_t *handle)
 {
-    assert(handle);
+    assert(NULL != handle);
 
-    LPUART_DisableInterrupts(base, kLPUART_TxDataRegEmptyInterruptEnable | kLPUART_TransmissionCompleteInterruptEnable);
+    LPUART_DisableInterrupts(
+        base, (uint32_t)kLPUART_TxDataRegEmptyInterruptEnable | (uint32_t)kLPUART_TransmissionCompleteInterruptEnable);
 
     handle->txDataSize = 0;
-    handle->txState = kLPUART_TxIdle;
+    handle->txState    = (uint8_t)kLPUART_TxIdle;
 }
 
+/*!
+ * brief Gets the number of bytes that have been written to the LPUART transmitter register.
+ *
+ * This function gets the number of bytes that have been written to LPUART TX
+ * register by an interrupt method.
+ *
+ * param base LPUART peripheral base address.
+ * param handle LPUART handle pointer.
+ * param count Send bytes count.
+ * retval kStatus_NoTransferInProgress No send in progress.
+ * retval kStatus_InvalidArgument Parameter is invalid.
+ * retval kStatus_Success Get successfully through the parameter \p count;
+ */
 status_t LPUART_TransferGetSendCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count)
 {
-    assert(handle);
-    assert(count);
+    assert(NULL != handle);
+    assert(NULL != count);
 
-    if (kLPUART_TxIdle == handle->txState)
+    if ((uint8_t)kLPUART_TxIdle == handle->txState)
     {
         return kStatus_NoTransferInProgress;
     }
@@ -888,15 +1157,41 @@ status_t LPUART_TransferGetSendCount(LPUART_Type *base, lpuart_handle_t *handle,
     return kStatus_Success;
 }
 
+/*!
+ * brief Receives a buffer of data using the interrupt method.
+ *
+ * This function receives data using an interrupt method. This is a non-blocking function
+ * which returns without waiting to ensure that all data are received.
+ * If the RX ring buffer is used and not empty, the data in the ring buffer is copied and
+ * the parameter p receivedBytes shows how many bytes are copied from the ring buffer.
+ * After copying, if the data in the ring buffer is not enough for read, the receive
+ * request is saved by the LPUART driver. When the new data arrives, the receive request
+ * is serviced first. When all data is received, the LPUART driver notifies the upper layer
+ * through a callback function and passes a status parameter ref kStatus_UART_RxIdle.
+ * For example, the upper layer needs 10 bytes but there are only 5 bytes in ring buffer.
+ * The 5 bytes are copied to xfer->data, which returns with the
+ * parameter p receivedBytes set to 5. For the remaining 5 bytes, the newly arrived data is
+ * saved from xfer->data[5]. When 5 bytes are received, the LPUART driver notifies the upper layer.
+ * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt
+ * to receive data to xfer->data. When all data is received, the upper layer is notified.
+ *
+ * param base LPUART peripheral base address.
+ * param handle LPUART handle pointer.
+ * param xfer LPUART transfer structure, see #uart_transfer_t.
+ * param receivedBytes Bytes received from the ring buffer directly.
+ * retval kStatus_Success Successfully queue the transfer into the transmit queue.
+ * retval kStatus_LPUART_RxBusy Previous receive request is not finished.
+ * retval kStatus_InvalidArgument Invalid argument.
+ */
 status_t LPUART_TransferReceiveNonBlocking(LPUART_Type *base,
                                            lpuart_handle_t *handle,
                                            lpuart_transfer_t *xfer,
                                            size_t *receivedBytes)
 {
-    assert(handle);
-    assert(xfer);
-    assert(xfer->data);
-    assert(xfer->dataSize);
+    assert(NULL != handle);
+    assert(NULL != xfer);
+    assert(NULL != xfer->data);
+    assert(0U != xfer->dataSize);
 
     uint32_t i;
     status_t status;
@@ -917,25 +1212,25 @@ status_t LPUART_TransferReceiveNonBlocking(LPUART_Type *base,
           save the xfer->data remained empty space to lpuart handle, receive data
           to this empty space and trigger callback when finished. */
 
-    if (kLPUART_RxBusy == handle->rxState)
+    if ((uint8_t)kLPUART_RxBusy == handle->rxState)
     {
         status = kStatus_LPUART_RxBusy;
     }
     else
     {
-        bytesToReceive = xfer->dataSize;
+        bytesToReceive       = xfer->dataSize;
         bytesCurrentReceived = 0;
 
         /* If RX ring buffer is used. */
-        if (handle->rxRingBuffer)
+        if (NULL != handle->rxRingBuffer)
         {
             /* Disable LPUART RX IRQ, protect ring buffer. */
-            LPUART_DisableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable);
+            LPUART_DisableInterrupts(base, (uint32_t)kLPUART_RxDataRegFullInterruptEnable);
 
             /* How many bytes in RX ring buffer currently. */
             bytesToCopy = LPUART_TransferGetRxRingBufferLength(base, handle);
 
-            if (bytesToCopy)
+            if (0U != bytesToCopy)
             {
                 bytesToCopy = MIN(bytesToReceive, bytesToCopy);
 
@@ -944,10 +1239,11 @@ status_t LPUART_TransferReceiveNonBlocking(LPUART_Type *base,
                 /* Copy data from ring buffer to user memory. */
                 for (i = 0U; i < bytesToCopy; i++)
                 {
-                    xfer->data[bytesCurrentReceived++] = handle->rxRingBuffer[handle->rxRingBufferTail];
+                    xfer->data[bytesCurrentReceived] = handle->rxRingBuffer[handle->rxRingBufferTail];
+                    bytesCurrentReceived++;
 
                     /* Wrap to 0. Not use modulo (%) because it might be large and slow. */
-                    if (handle->rxRingBufferTail + 1U == handle->rxRingBufferSize)
+                    if (((uint32_t)handle->rxRingBufferTail + 1U) == handle->rxRingBufferSize)
                     {
                         handle->rxRingBufferTail = 0U;
                     }
@@ -959,21 +1255,21 @@ status_t LPUART_TransferReceiveNonBlocking(LPUART_Type *base,
             }
 
             /* If ring buffer does not have enough data, still need to read more data. */
-            if (bytesToReceive)
+            if (0U != bytesToReceive)
             {
                 /* No data in ring buffer, save the request to LPUART handle. */
-                handle->rxData = xfer->data + bytesCurrentReceived;
-                handle->rxDataSize = bytesToReceive;
+                handle->rxData        = xfer->data + bytesCurrentReceived;
+                handle->rxDataSize    = bytesToReceive;
                 handle->rxDataSizeAll = bytesToReceive;
-                handle->rxState = kLPUART_RxBusy;
+                handle->rxState       = (uint8_t)kLPUART_RxBusy;
             }
             /* Enable LPUART RX IRQ if previously enabled. */
-            LPUART_EnableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable);
+            LPUART_EnableInterrupts(base, (uint32_t)kLPUART_RxDataRegFullInterruptEnable);
 
             /* Call user callback since all data are received. */
-            if (0 == bytesToReceive)
+            if (0U == bytesToReceive)
             {
-                if (handle->callback)
+                if (NULL != handle->callback)
                 {
                     handle->callback(base, handle, kStatus_LPUART_RxIdle, handle->userData);
                 }
@@ -982,18 +1278,19 @@ status_t LPUART_TransferReceiveNonBlocking(LPUART_Type *base,
         /* Ring buffer not used. */
         else
         {
-            handle->rxData = xfer->data + bytesCurrentReceived;
-            handle->rxDataSize = bytesToReceive;
+            handle->rxData        = xfer->data + bytesCurrentReceived;
+            handle->rxDataSize    = bytesToReceive;
             handle->rxDataSizeAll = bytesToReceive;
-            handle->rxState = kLPUART_RxBusy;
+            handle->rxState       = (uint8_t)kLPUART_RxBusy;
 
             /* Enable RX interrupt. */
-            LPUART_EnableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable | kLPUART_RxOverrunInterruptEnable |
-                                              kLPUART_IdleLineInterruptEnable);
+            LPUART_EnableInterrupts(base, (uint32_t)kLPUART_RxDataRegFullInterruptEnable |
+                                              (uint32_t)kLPUART_RxOverrunInterruptEnable |
+                                              (uint32_t)kLPUART_IdleLineInterruptEnable);
         }
 
         /* Return the how many bytes have read. */
-        if (receivedBytes)
+        if (NULL != receivedBytes)
         {
             *receivedBytes = bytesCurrentReceived;
         }
@@ -1004,28 +1301,50 @@ status_t LPUART_TransferReceiveNonBlocking(LPUART_Type *base,
     return status;
 }
 
+/*!
+ * brief Aborts the interrupt-driven data receiving.
+ *
+ * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to find out
+ * how many bytes not received yet.
+ *
+ * param base LPUART peripheral base address.
+ * param handle LPUART handle pointer.
+ */
 void LPUART_TransferAbortReceive(LPUART_Type *base, lpuart_handle_t *handle)
 {
-    assert(handle);
+    assert(NULL != handle);
 
     /* Only abort the receive to handle->rxData, the RX ring buffer is still working. */
-    if (!handle->rxRingBuffer)
+    if (NULL == handle->rxRingBuffer)
     {
         /* Disable RX interrupt. */
-        LPUART_DisableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable | kLPUART_RxOverrunInterruptEnable |
-                                           kLPUART_IdleLineInterruptEnable);
+        LPUART_DisableInterrupts(base, (uint32_t)kLPUART_RxDataRegFullInterruptEnable |
+                                           (uint32_t)kLPUART_RxOverrunInterruptEnable |
+                                           (uint32_t)kLPUART_IdleLineInterruptEnable);
     }
 
     handle->rxDataSize = 0U;
-    handle->rxState = kLPUART_RxIdle;
+    handle->rxState    = (uint8_t)kLPUART_RxIdle;
 }
 
+/*!
+ * brief Gets the number of bytes that have been received.
+ *
+ * This function gets the number of bytes that have been received.
+ *
+ * param base LPUART peripheral base address.
+ * param handle LPUART handle pointer.
+ * param count Receive bytes count.
+ * retval kStatus_NoTransferInProgress No receive in progress.
+ * retval kStatus_InvalidArgument Parameter is invalid.
+ * retval kStatus_Success Get successfully through the parameter \p count;
+ */
 status_t LPUART_TransferGetReceiveCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count)
 {
-    assert(handle);
-    assert(count);
+    assert(NULL != handle);
+    assert(NULL != count);
 
-    if (kLPUART_RxIdle == handle->rxState)
+    if ((uint8_t)kLPUART_RxIdle == handle->rxState)
     {
         return kStatus_NoTransferInProgress;
     }
@@ -1035,35 +1354,46 @@ status_t LPUART_TransferGetReceiveCount(LPUART_Type *base, lpuart_handle_t *hand
     return kStatus_Success;
 }
 
+/*!
+ * brief LPUART IRQ handle function.
+ *
+ * This function handles the LPUART transmit and receive IRQ request.
+ *
+ * param base LPUART peripheral base address.
+ * param handle LPUART handle pointer.
+ */
 void LPUART_TransferHandleIRQ(LPUART_Type *base, lpuart_handle_t *handle)
 {
-    assert(handle);
+    assert(NULL != handle);
 
     uint8_t count;
     uint8_t tempCount;
+    uint32_t status            = LPUART_GetStatusFlags(base);
+    uint32_t enabledInterrupts = LPUART_GetEnabledInterrupts(base);
 
     /* If RX overrun. */
-    if (LPUART_STAT_OR_MASK & base->STAT)
+    if ((uint32_t)kLPUART_RxOverrunFlag == ((uint32_t)kLPUART_RxOverrunFlag & status))
     {
         /* Clear overrun flag, otherwise the RX does not work. */
         base->STAT = ((base->STAT & 0x3FE00000U) | LPUART_STAT_OR_MASK);
 
         /* Trigger callback. */
-        if (handle->callback)
+        if (NULL != (handle->callback))
         {
             handle->callback(base, handle, kStatus_LPUART_RxHardwareOverrun, handle->userData);
         }
     }
 
     /* If IDLE flag is set and the IDLE interrupt is enabled. */
-    if ((LPUART_STAT_IDLE_MASK & base->STAT) && (LPUART_CTRL_ILIE_MASK & base->CTRL))
+    if ((0U != ((uint32_t)kLPUART_IdleLineFlag & status)) &&
+        (0U != ((uint32_t)kLPUART_IdleLineInterruptEnable & enabledInterrupts)))
     {
 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
         count = ((uint8_t)((base->WATER & LPUART_WATER_RXCOUNT_MASK) >> LPUART_WATER_RXCOUNT_SHIFT));
 
-        while ((count) && (handle->rxDataSize))
+        while ((0U != handle->rxDataSize) && (0U != count))
         {
-            tempCount = MIN(handle->rxDataSize, count);
+            tempCount = (uint8_t)MIN(handle->rxDataSize, count);
 
             /* Using non block API to read the data from the registers. */
             LPUART_ReadNonBlocking(base, handle->rxData, tempCount);
@@ -1072,12 +1402,13 @@ void LPUART_TransferHandleIRQ(LPUART_Type *base, lpuart_handle_t *handle)
             count -= tempCount;
 
             /* If rxDataSize is 0, disable idle line interrupt.*/
-            if (!(handle->rxDataSize))
+            if (0U == (handle->rxDataSize))
             {
-                handle->rxState = kLPUART_RxIdle;
+                handle->rxState = (uint8_t)kLPUART_RxIdle;
 
-                LPUART_DisableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable | kLPUART_RxOverrunInterruptEnable);
-                if (handle->callback)
+                LPUART_DisableInterrupts(
+                    base, (uint32_t)kLPUART_RxDataRegFullInterruptEnable | (uint32_t)kLPUART_RxOverrunInterruptEnable);
+                if (NULL != handle->callback)
                 {
                     handle->callback(base, handle, kStatus_LPUART_RxIdle, handle->userData);
                 }
@@ -1088,18 +1419,19 @@ void LPUART_TransferHandleIRQ(LPUART_Type *base, lpuart_handle_t *handle)
         base->STAT |= LPUART_STAT_IDLE_MASK;
 
         /* If rxDataSize is 0, disable idle line interrupt.*/
-        if (!(handle->rxDataSize))
+        if (0U != (handle->rxDataSize))
         {
-            LPUART_DisableInterrupts(base, kLPUART_IdleLineInterruptEnable);
+            LPUART_DisableInterrupts(base, (uint32_t)kLPUART_IdleLineInterruptEnable);
         }
         /* If callback is not NULL and rxDataSize is not 0. */
-        if ((handle->callback) && (handle->rxDataSize))
+        if ((0U != handle->rxDataSize) && (NULL != handle->callback))
         {
             handle->callback(base, handle, kStatus_LPUART_IdleLineDetected, handle->userData);
         }
     }
     /* Receive data register full */
-    if ((LPUART_STAT_RDRF_MASK & base->STAT) && (LPUART_CTRL_RIE_MASK & base->CTRL))
+    if ((0U != ((uint32_t)kLPUART_RxDataRegFullFlag & status)) &&
+        (0U != ((uint32_t)kLPUART_RxDataRegFullInterruptEnable & enabledInterrupts)))
     {
 /* Get the size that can be stored into buffer for this interrupt. */
 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
@@ -1109,10 +1441,10 @@ void LPUART_TransferHandleIRQ(LPUART_Type *base, lpuart_handle_t *handle)
 #endif
 
         /* If handle->rxDataSize is not 0, first save data to handle->rxData. */
-        while ((count) && (handle->rxDataSize))
+        while ((0U != handle->rxDataSize) && (0U != count))
         {
 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
-            tempCount = MIN(handle->rxDataSize, count);
+            tempCount = (uint8_t)MIN(handle->rxDataSize, count);
 #else
             tempCount = 1;
 #endif
@@ -1124,11 +1456,11 @@ void LPUART_TransferHandleIRQ(LPUART_Type *base, lpuart_handle_t *handle)
             count -= tempCount;
 
             /* If all the data required for upper layer is ready, trigger callback. */
-            if (!handle->rxDataSize)
+            if (0U == handle->rxDataSize)
             {
-                handle->rxState = kLPUART_RxIdle;
+                handle->rxState = (uint8_t)kLPUART_RxIdle;
 
-                if (handle->callback)
+                if (NULL != handle->callback)
                 {
                     handle->callback(base, handle, kStatus_LPUART_RxIdle, handle->userData);
                 }
@@ -1136,24 +1468,24 @@ void LPUART_TransferHandleIRQ(LPUART_Type *base, lpuart_handle_t *handle)
         }
 
         /* If use RX ring buffer, receive data to ring buffer. */
-        if (handle->rxRingBuffer)
+        if (NULL != handle->rxRingBuffer)
         {
-            while (count--)
+            while (0U != count--)
             {
                 /* If RX ring buffer is full, trigger callback to notify over run. */
                 if (LPUART_TransferIsRxRingBufferFull(base, handle))
                 {
-                    if (handle->callback)
+                    if (NULL != handle->callback)
                     {
                         handle->callback(base, handle, kStatus_LPUART_RxRingBufferOverrun, handle->userData);
                     }
                 }
 
-                /* If ring buffer is still full after callback function, the oldest data is overrided. */
+                /* If ring buffer is still full after callback function, the oldest data is overridden. */
                 if (LPUART_TransferIsRxRingBufferFull(base, handle))
                 {
                     /* Increase handle->rxRingBufferTail to make room for new data. */
-                    if (handle->rxRingBufferTail + 1U == handle->rxRingBufferSize)
+                    if (((uint32_t)handle->rxRingBufferTail + 1U) == handle->rxRingBufferSize)
                     {
                         handle->rxRingBufferTail = 0U;
                     }
@@ -1174,11 +1506,13 @@ void LPUART_TransferHandleIRQ(LPUART_Type *base, lpuart_handle_t *handle)
                     handle->rxRingBuffer[handle->rxRingBufferHead] = base->DATA;
                 }
 #else
-                handle->rxRingBuffer[handle->rxRingBufferHead] = base->DATA;
+                uint16_t tpmRxRingBufferHead              = handle->rxRingBufferHead;
+                uint32_t tpmData                          = base->DATA;
+                handle->rxRingBuffer[tpmRxRingBufferHead] = (uint8_t)tpmData;
 #endif
 
                 /* Increase handle->rxRingBufferHead. */
-                if (handle->rxRingBufferHead + 1U == handle->rxRingBufferSize)
+                if (((uint32_t)handle->rxRingBufferHead + 1U) == handle->rxRingBufferSize)
                 {
                     handle->rxRingBufferHead = 0U;
                 }
@@ -1189,9 +1523,10 @@ void LPUART_TransferHandleIRQ(LPUART_Type *base, lpuart_handle_t *handle)
             }
         }
         /* If no receive requst pending, stop RX interrupt. */
-        else if (!handle->rxDataSize)
+        else if (0U == handle->rxDataSize)
         {
-            LPUART_DisableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable | kLPUART_RxOverrunInterruptEnable);
+            LPUART_DisableInterrupts(
+                base, (uint32_t)kLPUART_RxDataRegFullInterruptEnable | (uint32_t)kLPUART_RxOverrunInterruptEnable);
         }
         else
         {
@@ -1199,20 +1534,21 @@ void LPUART_TransferHandleIRQ(LPUART_Type *base, lpuart_handle_t *handle)
     }
 
     /* Send data register empty and the interrupt is enabled. */
-    if ((base->STAT & LPUART_STAT_TDRE_MASK) && (base->CTRL & LPUART_CTRL_TIE_MASK))
+    if ((0U != ((uint32_t)kLPUART_TxDataRegEmptyFlag & status)) &&
+        (0U != ((uint32_t)kLPUART_TxDataRegEmptyInterruptEnable & enabledInterrupts)))
     {
 /* Get the bytes that available at this moment. */
 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
-        count = FSL_FEATURE_LPUART_FIFO_SIZEn(base) -
-                ((base->WATER & LPUART_WATER_TXCOUNT_MASK) >> LPUART_WATER_TXCOUNT_SHIFT);
+        count = (uint8_t)FSL_FEATURE_LPUART_FIFO_SIZEn(base) -
+                (uint8_t)((base->WATER & LPUART_WATER_TXCOUNT_MASK) >> LPUART_WATER_TXCOUNT_SHIFT);
 #else
         count = 1;
 #endif
 
-        while ((count) && (handle->txDataSize))
+        while ((0U != handle->txDataSize) && (0U != count))
         {
 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
-            tempCount = MIN(handle->txDataSize, count);
+            tempCount = (uint8_t)MIN(handle->txDataSize, count);
 #else
             tempCount = 1;
 #endif
@@ -1224,15 +1560,15 @@ void LPUART_TransferHandleIRQ(LPUART_Type *base, lpuart_handle_t *handle)
             count -= tempCount;
 
             /* If all the data are written to data register, notify user with the callback, then TX finished. */
-            if (!handle->txDataSize)
+            if (0U == handle->txDataSize)
             {
-                handle->txState = kLPUART_TxIdle;
+                handle->txState = (uint8_t)kLPUART_TxIdle;
 
                 /* Disable TX register empty interrupt. */
                 base->CTRL = (base->CTRL & ~LPUART_CTRL_TIE_MASK);
 
                 /* Trigger callback. */
-                if (handle->callback)
+                if (NULL != handle->callback)
                 {
                     handle->callback(base, handle, kStatus_LPUART_TxIdle, handle->userData);
                 }
@@ -1241,6 +1577,14 @@ void LPUART_TransferHandleIRQ(LPUART_Type *base, lpuart_handle_t *handle)
     }
 }
 
+/*!
+ * brief LPUART Error IRQ handle function.
+ *
+ * This function handles the LPUART error IRQ request.
+ *
+ * param base LPUART peripheral base address.
+ * param handle LPUART handle pointer.
+ */
 void LPUART_TransferHandleErrorIRQ(LPUART_Type *base, lpuart_handle_t *handle)
 {
     /* To be implemented by User. */
@@ -1249,18 +1593,23 @@ void LPUART_TransferHandleErrorIRQ(LPUART_Type *base, lpuart_handle_t *handle)
 #if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
 void LPUART0_LPUART1_RX_DriverIRQHandler(void)
 {
+    uint32_t stat = 0U;
+    uint32_t ctrl = 0U;
+
     if (CLOCK_isEnabledClock(s_lpuartClock[0]))
     {
-        if ((LPUART_STAT_OR_MASK & LPUART0->STAT) ||
-            ((LPUART_STAT_RDRF_MASK & LPUART0->STAT) && (LPUART_CTRL_RIE_MASK & LPUART0->CTRL)))
+        stat = LPUART0->STAT;
+        ctrl = LPUART0->CTRL;
+        if ((LPUART_STAT_OR_MASK & stat) || ((LPUART_STAT_RDRF_MASK & stat) && (LPUART_CTRL_RIE_MASK & ctrl)))
         {
             s_lpuartIsr(LPUART0, s_lpuartHandle[0]);
         }
     }
     if (CLOCK_isEnabledClock(s_lpuartClock[1]))
     {
-        if ((LPUART_STAT_OR_MASK & LPUART1->STAT) ||
-            ((LPUART_STAT_RDRF_MASK & LPUART1->STAT) && (LPUART_CTRL_RIE_MASK & LPUART1->CTRL)))
+        stat = LPUART1->STAT;
+        ctrl = LPUART1->CTRL;
+        if ((LPUART_STAT_OR_MASK & stat) || ((LPUART_STAT_RDRF_MASK & stat) && (LPUART_CTRL_RIE_MASK & ctrl)))
         {
             s_lpuartIsr(LPUART1, s_lpuartHandle[1]);
         }
@@ -1273,18 +1622,23 @@ void LPUART0_LPUART1_RX_DriverIRQHandler(void)
 }
 void LPUART0_LPUART1_TX_DriverIRQHandler(void)
 {
+    uint32_t stat = 0U;
+    uint32_t ctrl = 0U;
+
     if (CLOCK_isEnabledClock(s_lpuartClock[0]))
     {
-        if ((LPUART_STAT_OR_MASK & LPUART0->STAT) ||
-            ((LPUART0->STAT & LPUART_STAT_TDRE_MASK) && (LPUART0->CTRL & LPUART_CTRL_TIE_MASK)))
+        stat = LPUART0->STAT;
+        ctrl = LPUART0->CTRL;
+        if ((LPUART_STAT_OR_MASK & stat) || ((stat & LPUART_STAT_TDRE_MASK) && (ctrl & LPUART_CTRL_TIE_MASK)))
         {
             s_lpuartIsr(LPUART0, s_lpuartHandle[0]);
         }
     }
     if (CLOCK_isEnabledClock(s_lpuartClock[1]))
     {
-        if ((LPUART_STAT_OR_MASK & LPUART1->STAT) ||
-            ((LPUART1->STAT & LPUART_STAT_TDRE_MASK) && (LPUART1->CTRL & LPUART_CTRL_TIE_MASK)))
+        stat = LPUART1->STAT;
+        ctrl = LPUART1->CTRL;
+        if ((LPUART_STAT_OR_MASK & stat) || ((stat & LPUART_STAT_TDRE_MASK) && (ctrl & LPUART_CTRL_TIE_MASK)))
         {
             s_lpuartIsr(LPUART1, s_lpuartHandle[1]);
         }
@@ -1298,20 +1652,27 @@ void LPUART0_LPUART1_TX_DriverIRQHandler(void)
 #else
 void LPUART0_LPUART1_DriverIRQHandler(void)
 {
+    uint32_t stat = 0U;
+    uint32_t ctrl = 0U;
+
     if (CLOCK_isEnabledClock(s_lpuartClock[0]))
     {
-        if ((LPUART_STAT_OR_MASK & LPUART0->STAT) ||
-            ((LPUART_STAT_RDRF_MASK & LPUART0->STAT) && (LPUART_CTRL_RIE_MASK & LPUART0->CTRL)) ||
-            ((LPUART0->STAT & LPUART_STAT_TDRE_MASK) && (LPUART0->CTRL & LPUART_CTRL_TIE_MASK)))
+        stat = LPUART0->STAT;
+        ctrl = LPUART0->CTRL;
+        if ((0U != (LPUART_STAT_OR_MASK & stat)) ||
+            ((0U != (LPUART_STAT_RDRF_MASK & stat)) && (0U != (LPUART_CTRL_RIE_MASK & ctrl))) ||
+            ((0U != (stat & LPUART_STAT_TDRE_MASK)) && (0U != (ctrl & LPUART_CTRL_TIE_MASK))))
         {
             s_lpuartIsr(LPUART0, s_lpuartHandle[0]);
         }
     }
     if (CLOCK_isEnabledClock(s_lpuartClock[1]))
     {
-        if ((LPUART_STAT_OR_MASK & LPUART1->STAT) ||
-            ((LPUART_STAT_RDRF_MASK & LPUART1->STAT) && (LPUART_CTRL_RIE_MASK & LPUART1->CTRL)) ||
-            ((LPUART1->STAT & LPUART_STAT_TDRE_MASK) && (LPUART1->CTRL & LPUART_CTRL_TIE_MASK)))
+        stat = LPUART1->STAT;
+        ctrl = LPUART1->CTRL;
+        if ((0U != (LPUART_STAT_OR_MASK & stat)) ||
+            ((0U != (LPUART_STAT_RDRF_MASK & stat)) && (0U != (LPUART_CTRL_RIE_MASK & ctrl))) ||
+            ((0U != (stat & LPUART_STAT_TDRE_MASK)) && (0U != (ctrl & LPUART_CTRL_TIE_MASK))))
         {
             s_lpuartIsr(LPUART1, s_lpuartHandle[1]);
         }
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_lpuart.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_lpuart.h
index 395c27a68dc..ddfa6f6d6b4 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_lpuart.h
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_lpuart.h
@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
+ * Copyright 2016-2018 NXP
  * All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 #ifndef _FSL_LPUART_H_
 #define _FSL_LPUART_H_
@@ -47,27 +21,27 @@
 
 /*! @name Driver version */
 /*@{*/
-/*! @brief LPUART driver version 2.2.5. */
-#define FSL_LPUART_DRIVER_VERSION (MAKE_VERSION(2, 2, 5))
+/*! @brief LPUART driver version 2.2.7. */
+#define FSL_LPUART_DRIVER_VERSION (MAKE_VERSION(2, 2, 7))
 /*@}*/
 
 /*! @brief Error codes for the LPUART driver. */
 enum _lpuart_status
 {
-    kStatus_LPUART_TxBusy = MAKE_STATUS(kStatusGroup_LPUART, 0),                  /*!< TX busy */
-    kStatus_LPUART_RxBusy = MAKE_STATUS(kStatusGroup_LPUART, 1),                  /*!< RX busy */
-    kStatus_LPUART_TxIdle = MAKE_STATUS(kStatusGroup_LPUART, 2),                  /*!< LPUART transmitter is idle. */
-    kStatus_LPUART_RxIdle = MAKE_STATUS(kStatusGroup_LPUART, 3),                  /*!< LPUART receiver is idle. */
-    kStatus_LPUART_TxWatermarkTooLarge = MAKE_STATUS(kStatusGroup_LPUART, 4),     /*!< TX FIFO watermark too large  */
-    kStatus_LPUART_RxWatermarkTooLarge = MAKE_STATUS(kStatusGroup_LPUART, 5),     /*!< RX FIFO watermark too large  */
+    kStatus_LPUART_TxBusy                  = MAKE_STATUS(kStatusGroup_LPUART, 0), /*!< TX busy */
+    kStatus_LPUART_RxBusy                  = MAKE_STATUS(kStatusGroup_LPUART, 1), /*!< RX busy */
+    kStatus_LPUART_TxIdle                  = MAKE_STATUS(kStatusGroup_LPUART, 2), /*!< LPUART transmitter is idle. */
+    kStatus_LPUART_RxIdle                  = MAKE_STATUS(kStatusGroup_LPUART, 3), /*!< LPUART receiver is idle. */
+    kStatus_LPUART_TxWatermarkTooLarge     = MAKE_STATUS(kStatusGroup_LPUART, 4), /*!< TX FIFO watermark too large  */
+    kStatus_LPUART_RxWatermarkTooLarge     = MAKE_STATUS(kStatusGroup_LPUART, 5), /*!< RX FIFO watermark too large  */
     kStatus_LPUART_FlagCannotClearManually = MAKE_STATUS(kStatusGroup_LPUART, 6), /*!< Some flag can't manually clear */
-    kStatus_LPUART_Error = MAKE_STATUS(kStatusGroup_LPUART, 7),                   /*!< Error happens on LPUART. */
+    kStatus_LPUART_Error                   = MAKE_STATUS(kStatusGroup_LPUART, 7), /*!< Error happens on LPUART. */
     kStatus_LPUART_RxRingBufferOverrun =
         MAKE_STATUS(kStatusGroup_LPUART, 8), /*!< LPUART RX software ring buffer overrun. */
-    kStatus_LPUART_RxHardwareOverrun = MAKE_STATUS(kStatusGroup_LPUART, 9), /*!< LPUART RX receiver overrun. */
-    kStatus_LPUART_NoiseError = MAKE_STATUS(kStatusGroup_LPUART, 10),       /*!< LPUART noise error. */
-    kStatus_LPUART_FramingError = MAKE_STATUS(kStatusGroup_LPUART, 11),     /*!< LPUART framing error. */
-    kStatus_LPUART_ParityError = MAKE_STATUS(kStatusGroup_LPUART, 12),      /*!< LPUART parity error. */
+    kStatus_LPUART_RxHardwareOverrun = MAKE_STATUS(kStatusGroup_LPUART, 9),  /*!< LPUART RX receiver overrun. */
+    kStatus_LPUART_NoiseError        = MAKE_STATUS(kStatusGroup_LPUART, 10), /*!< LPUART noise error. */
+    kStatus_LPUART_FramingError      = MAKE_STATUS(kStatusGroup_LPUART, 11), /*!< LPUART framing error. */
+    kStatus_LPUART_ParityError       = MAKE_STATUS(kStatusGroup_LPUART, 12), /*!< LPUART parity error. */
     kStatus_LPUART_BaudrateNotSupport =
         MAKE_STATUS(kStatusGroup_LPUART, 13), /*!< Baudrate is not support in current clock source */
     kStatus_LPUART_IdleLineDetected = MAKE_STATUS(kStatusGroup_LPUART, 14), /*!< IDLE flag. */
@@ -77,8 +51,8 @@ enum _lpuart_status
 typedef enum _lpuart_parity_mode
 {
     kLPUART_ParityDisabled = 0x0U, /*!< Parity disabled */
-    kLPUART_ParityEven = 0x2U,     /*!< Parity enabled, type even, bit setting: PE|PT = 10 */
-    kLPUART_ParityOdd = 0x3U,      /*!< Parity enabled, type odd,  bit setting: PE|PT = 11 */
+    kLPUART_ParityEven     = 0x2U, /*!< Parity enabled, type even, bit setting: PE|PT = 10 */
+    kLPUART_ParityOdd      = 0x3U, /*!< Parity enabled, type odd,  bit setting: PE|PT = 11 */
 } lpuart_parity_mode_t;
 
 /*! @brief LPUART data bits count. */
@@ -101,7 +75,7 @@ typedef enum _lpuart_stop_bit_count
 /*! @brief LPUART transmit CTS source. */
 typedef enum _lpuart_transmit_cts_source
 {
-    kLPUART_CtsSourcePin = 0U,         /*!< CTS resource is the LPUART_CTS pin. */
+    kLPUART_CtsSourcePin         = 0U, /*!< CTS resource is the LPUART_CTS pin. */
     kLPUART_CtsSourceMatchResult = 1U, /*!< CTS resource is the match result. */
 } lpuart_transmit_cts_source_t;
 
@@ -109,7 +83,7 @@ typedef enum _lpuart_transmit_cts_source
 typedef enum _lpuart_transmit_cts_config
 {
     kLPUART_CtsSampleAtStart = 0U, /*!< CTS input is sampled at the start of each character. */
-    kLPUART_CtsSampleAtIdle = 1U,  /*!< CTS input is sampled when the transmitter is idle */
+    kLPUART_CtsSampleAtIdle  = 1U, /*!< CTS input is sampled when the transmitter is idle */
 } lpuart_transmit_cts_config_t;
 #endif
 
@@ -117,7 +91,7 @@ typedef enum _lpuart_transmit_cts_config
 typedef enum _lpuart_idle_type_select
 {
     kLPUART_IdleTypeStartBit = 0U, /*!< Start counting after a valid start bit. */
-    kLPUART_IdleTypeStopBit = 1U,  /*!< Start conuting after a stop bit. */
+    kLPUART_IdleTypeStopBit  = 1U, /*!< Start counting after a stop bit. */
 } lpuart_idle_type_select_t;
 
 /*! @brief LPUART idle detected configuration.
@@ -126,13 +100,13 @@ typedef enum _lpuart_idle_type_select
  */
 typedef enum _lpuart_idle_config
 {
-    kLPUART_IdleCharacter1 = 0U,   /*!< the number of idle characters. */
-    kLPUART_IdleCharacter2 = 1U,   /*!< the number of idle characters. */
-    kLPUART_IdleCharacter4 = 2U,   /*!< the number of idle characters. */
-    kLPUART_IdleCharacter8 = 3U,   /*!< the number of idle characters. */
-    kLPUART_IdleCharacter16 = 4U,  /*!< the number of idle characters. */
-    kLPUART_IdleCharacter32 = 5U,  /*!< the number of idle characters. */
-    kLPUART_IdleCharacter64 = 6U,  /*!< the number of idle characters. */
+    kLPUART_IdleCharacter1   = 0U, /*!< the number of idle characters. */
+    kLPUART_IdleCharacter2   = 1U, /*!< the number of idle characters. */
+    kLPUART_IdleCharacter4   = 2U, /*!< the number of idle characters. */
+    kLPUART_IdleCharacter8   = 3U, /*!< the number of idle characters. */
+    kLPUART_IdleCharacter16  = 4U, /*!< the number of idle characters. */
+    kLPUART_IdleCharacter32  = 5U, /*!< the number of idle characters. */
+    kLPUART_IdleCharacter64  = 6U, /*!< the number of idle characters. */
     kLPUART_IdleCharacter128 = 7U, /*!< the number of idle characters. */
 } lpuart_idle_config_t;
 
@@ -146,17 +120,17 @@ enum _lpuart_interrupt_enable
 #if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT
     kLPUART_LinBreakInterruptEnable = (LPUART_BAUD_LBKDIE_MASK >> 8), /*!< LIN break detect. */
 #endif
-    kLPUART_RxActiveEdgeInterruptEnable = (LPUART_BAUD_RXEDGIE_MASK >> 8), /*!< Receive Active Edge. */
-    kLPUART_TxDataRegEmptyInterruptEnable = (LPUART_CTRL_TIE_MASK),        /*!< Transmit data register empty. */
-    kLPUART_TransmissionCompleteInterruptEnable = (LPUART_CTRL_TCIE_MASK), /*!< Transmission complete. */
-    kLPUART_RxDataRegFullInterruptEnable = (LPUART_CTRL_RIE_MASK),         /*!< Receiver data register full. */
-    kLPUART_IdleLineInterruptEnable = (LPUART_CTRL_ILIE_MASK),             /*!< Idle line. */
-    kLPUART_RxOverrunInterruptEnable = (LPUART_CTRL_ORIE_MASK),            /*!< Receiver Overrun. */
-    kLPUART_NoiseErrorInterruptEnable = (LPUART_CTRL_NEIE_MASK),           /*!< Noise error flag. */
-    kLPUART_FramingErrorInterruptEnable = (LPUART_CTRL_FEIE_MASK),         /*!< Framing error flag. */
-    kLPUART_ParityErrorInterruptEnable = (LPUART_CTRL_PEIE_MASK),          /*!< Parity error flag. */
+    kLPUART_RxActiveEdgeInterruptEnable         = (LPUART_BAUD_RXEDGIE_MASK >> 8), /*!< Receive Active Edge. */
+    kLPUART_TxDataRegEmptyInterruptEnable       = (LPUART_CTRL_TIE_MASK),          /*!< Transmit data register empty. */
+    kLPUART_TransmissionCompleteInterruptEnable = (LPUART_CTRL_TCIE_MASK),         /*!< Transmission complete. */
+    kLPUART_RxDataRegFullInterruptEnable        = (LPUART_CTRL_RIE_MASK),          /*!< Receiver data register full. */
+    kLPUART_IdleLineInterruptEnable             = (LPUART_CTRL_ILIE_MASK),         /*!< Idle line. */
+    kLPUART_RxOverrunInterruptEnable            = (LPUART_CTRL_ORIE_MASK),         /*!< Receiver Overrun. */
+    kLPUART_NoiseErrorInterruptEnable           = (LPUART_CTRL_NEIE_MASK),         /*!< Noise error flag. */
+    kLPUART_FramingErrorInterruptEnable         = (LPUART_CTRL_FEIE_MASK),         /*!< Framing error flag. */
+    kLPUART_ParityErrorInterruptEnable          = (LPUART_CTRL_PEIE_MASK),         /*!< Parity error flag. */
 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
-    kLPUART_TxFifoOverflowInterruptEnable = (LPUART_FIFO_TXOFE_MASK >> 8),  /*!< Transmit FIFO Overflow. */
+    kLPUART_TxFifoOverflowInterruptEnable  = (LPUART_FIFO_TXOFE_MASK >> 8), /*!< Transmit FIFO Overflow. */
     kLPUART_RxFifoUnderflowInterruptEnable = (LPUART_FIFO_RXUFE_MASK >> 8), /*!< Receive FIFO Underflow. */
 #endif
 };
@@ -174,17 +148,17 @@ enum _lpuart_flags
         (LPUART_STAT_TC_MASK), /*!< Transmission complete flag, sets when transmission activity complete */
     kLPUART_RxDataRegFullFlag =
         (LPUART_STAT_RDRF_MASK), /*!< Receive data register full flag, sets when the receive data buffer is full */
-    kLPUART_IdleLineFlag = (LPUART_STAT_IDLE_MASK), /*!< Idle line detect flag, sets when idle line detected */
-    kLPUART_RxOverrunFlag = (LPUART_STAT_OR_MASK),  /*!< Receive Overrun, sets when new data is received before data is
-                                                       read from receive register */
-    kLPUART_NoiseErrorFlag = (LPUART_STAT_NF_MASK), /*!< Receive takes 3 samples of each received bit.  If any of these
-                                                       samples differ, noise flag sets */
+    kLPUART_IdleLineFlag  = (LPUART_STAT_IDLE_MASK), /*!< Idle line detect flag, sets when idle line detected */
+    kLPUART_RxOverrunFlag = (LPUART_STAT_OR_MASK),   /*!< Receive Overrun, sets when new data is received before data is
+                                                        read from receive register */
+    kLPUART_NoiseErrorFlag = (LPUART_STAT_NF_MASK),  /*!< Receive takes 3 samples of each received bit.  If any of these
+                                                        samples differ, noise flag sets */
     kLPUART_FramingErrorFlag =
         (LPUART_STAT_FE_MASK), /*!< Frame error flag, sets if logic 0 was detected where stop bit expected */
     kLPUART_ParityErrorFlag = (LPUART_STAT_PF_MASK), /*!< If parity enabled, sets upon parity error detection */
 #if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT
-    kLPUART_LinBreakFlag = (LPUART_STAT_LBKDIF_MASK), /*!< LIN break detect interrupt flag, sets when LIN break char
-                                                         detected and LIN circuit enabled */
+    kLPUART_LinBreakFlag = (int)(LPUART_STAT_LBKDIF_MASK), /*!< LIN break detect interrupt flag, sets when LIN break
+                                                         char detected and LIN circuit enabled */
 #endif
     kLPUART_RxActiveEdgeFlag =
         (LPUART_STAT_RXEDGIF_MASK), /*!< Receive pin active edge interrupt flag, sets when active edge detected */
@@ -198,7 +172,7 @@ enum _lpuart_flags
     kLPUART_NoiseErrorInRxDataRegFlag =
         (LPUART_DATA_NOISY_MASK >> 10), /*!< NOISY bit, sets if noise detected in current data word */
     kLPUART_ParityErrorInRxDataRegFlag =
-        (LPUART_DATA_PARITYE_MASK >> 10), /*!< PARITYE bit, sets if noise detected in current data word */
+        (LPUART_DATA_PARITYE_MASK >> 10), /*!< PARITY bit, sets if noise detected in current data word */
 #endif
 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
     kLPUART_TxFifoEmptyFlag = (LPUART_FIFO_TXEMPT_MASK >> 16), /*!< TXEMPT bit, sets if transmit buffer is empty */
@@ -640,7 +614,7 @@ static inline uint8_t LPUART_ReadByte(LPUART_Type *base)
         return base->DATA;
     }
 #else
-    return base->DATA;
+    return (uint8_t)(base->DATA);
 #endif
 }
 
@@ -661,7 +635,7 @@ static inline uint8_t LPUART_ReadByte(LPUART_Type *base)
 void LPUART_WriteBlocking(LPUART_Type *base, const uint8_t *data, size_t length);
 
 /*!
-* @brief Reads the receiver data register using a blocking method.
+ * @brief Reads the receiver data register using a blocking method.
  *
  * This function polls the receiver register, waits for the receiver register full or receiver FIFO
  * has data, and reads data from the TX register.
@@ -762,7 +736,7 @@ void LPUART_TransferStopRingBuffer(LPUART_Type *base, lpuart_handle_t *handle);
 /*!
  * @brief Get the length of received data in RX ring buffer.
  *
- * @userData handle LPUART handle pointer.
+ * @param handle LPUART handle pointer.
  * @return Length of received data in RX ring buffer.
  */
 size_t LPUART_TransferGetRxRingBufferLength(LPUART_Type *base, lpuart_handle_t *handle);
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_lpuart_edma.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_lpuart_edma.c
index add94881796..5e7561399cd 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_lpuart_edma.c
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_lpuart_edma.c
@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
+ * Copyright 2016-2018 NXP
  * All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include "fsl_lpuart_edma.h"
@@ -103,7 +77,7 @@ enum _lpuart_edma_tansfer_states
 #endif /* LPUART 8 */
 
 /*<! Private handle only used for internally. */
-static lpuart_edma_private_handle_t s_edmaPrivateHandle[LPUART_HANDLE_ARRAY_SIZE];
+static lpuart_edma_private_handle_t s_lpuartEdmaPrivateHandle[LPUART_HANDLE_ARRAY_SIZE];
 
 /*******************************************************************************
  * Prototypes
@@ -137,19 +111,19 @@ static void LPUART_ReceiveEDMACallback(edma_handle_t *handle, void *param, bool
 
 static void LPUART_SendEDMACallback(edma_handle_t *handle, void *param, bool transferDone, uint32_t tcds)
 {
-    assert(param);
+    assert(NULL != param);
 
     lpuart_edma_private_handle_t *lpuartPrivateHandle = (lpuart_edma_private_handle_t *)param;
 
     /* Avoid the warning for unused variables. */
     handle = handle;
-    tcds = tcds;
+    tcds   = tcds;
 
     if (transferDone)
     {
         LPUART_TransferAbortSendEDMA(lpuartPrivateHandle->base, lpuartPrivateHandle->handle);
 
-        if (lpuartPrivateHandle->handle->callback)
+        if (NULL != lpuartPrivateHandle->handle->callback)
         {
             lpuartPrivateHandle->handle->callback(lpuartPrivateHandle->base, lpuartPrivateHandle->handle,
                                                   kStatus_LPUART_TxIdle, lpuartPrivateHandle->handle->userData);
@@ -159,20 +133,20 @@ static void LPUART_SendEDMACallback(edma_handle_t *handle, void *param, bool tra
 
 static void LPUART_ReceiveEDMACallback(edma_handle_t *handle, void *param, bool transferDone, uint32_t tcds)
 {
-    assert(param);
+    assert(NULL != param);
 
     lpuart_edma_private_handle_t *lpuartPrivateHandle = (lpuart_edma_private_handle_t *)param;
 
     /* Avoid warning for unused parameters. */
     handle = handle;
-    tcds = tcds;
+    tcds   = tcds;
 
     if (transferDone)
     {
         /* Disable transfer. */
         LPUART_TransferAbortReceiveEDMA(lpuartPrivateHandle->base, lpuartPrivateHandle->handle);
 
-        if (lpuartPrivateHandle->handle->callback)
+        if (NULL != lpuartPrivateHandle->handle->callback)
         {
             lpuartPrivateHandle->handle->callback(lpuartPrivateHandle->base, lpuartPrivateHandle->handle,
                                                   kStatus_LPUART_RxIdle, lpuartPrivateHandle->handle->userData);
@@ -180,6 +154,15 @@ static void LPUART_ReceiveEDMACallback(edma_handle_t *handle, void *param, bool
     }
 }
 
+/*!
+ * brief Initializes the LPUART handle which is used in transactional functions.
+ * param base LPUART peripheral base address.
+ * param handle Pointer to lpuart_edma_handle_t structure.
+ * param callback Callback function.
+ * param userData User data.
+ * param txEdmaHandle User requested DMA handle for TX DMA transfer.
+ * param rxEdmaHandle User requested DMA handle for RX DMA transfer.
+ */
 void LPUART_TransferCreateHandleEDMA(LPUART_Type *base,
                                      lpuart_edma_handle_t *handle,
                                      lpuart_edma_transfer_callback_t callback,
@@ -187,17 +170,17 @@ void LPUART_TransferCreateHandleEDMA(LPUART_Type *base,
                                      edma_handle_t *txEdmaHandle,
                                      edma_handle_t *rxEdmaHandle)
 {
-    assert(handle);
+    assert(NULL != handle);
 
     uint32_t instance = LPUART_GetInstance(base);
 
-    s_edmaPrivateHandle[instance].base = base;
-    s_edmaPrivateHandle[instance].handle = handle;
+    s_lpuartEdmaPrivateHandle[instance].base   = base;
+    s_lpuartEdmaPrivateHandle[instance].handle = handle;
 
-    memset(handle, 0, sizeof(*handle));
+    (void)memset(handle, 0, sizeof(*handle));
 
-    handle->rxState = kLPUART_RxIdle;
-    handle->txState = kLPUART_TxIdle;
+    handle->rxState = (uint8_t)kLPUART_RxIdle;
+    handle->txState = (uint8_t)kLPUART_TxIdle;
 
     handle->rxEdmaHandle = rxEdmaHandle;
     handle->txEdmaHandle = txEdmaHandle;
@@ -214,55 +197,73 @@ void LPUART_TransferCreateHandleEDMA(LPUART_Type *base,
        5 bytes are received. the last byte will be saved in FIFO but not trigger
        EDMA transfer because the water mark is 2.
      */
-    if (rxEdmaHandle)
+    if (NULL != rxEdmaHandle)
     {
         base->WATER &= (~LPUART_WATER_RXWATER_MASK);
     }
 #endif
 
     /* Configure TX. */
-    if (txEdmaHandle)
+    if (NULL != txEdmaHandle)
     {
-        EDMA_SetCallback(handle->txEdmaHandle, LPUART_SendEDMACallback, &s_edmaPrivateHandle[instance]);
+        EDMA_SetCallback(handle->txEdmaHandle, LPUART_SendEDMACallback, &s_lpuartEdmaPrivateHandle[instance]);
     }
 
     /* Configure RX. */
-    if (rxEdmaHandle)
+    if (NULL != rxEdmaHandle)
     {
-        EDMA_SetCallback(handle->rxEdmaHandle, LPUART_ReceiveEDMACallback, &s_edmaPrivateHandle[instance]);
+        EDMA_SetCallback(handle->rxEdmaHandle, LPUART_ReceiveEDMACallback, &s_lpuartEdmaPrivateHandle[instance]);
     }
 }
 
+/*!
+ * brief Sends data using eDMA.
+ *
+ * This function sends data using eDMA. This is a non-blocking function, which returns
+ * right away. When all data is sent, the send callback function is called.
+ *
+ * param base LPUART peripheral base address.
+ * param handle LPUART handle pointer.
+ * param xfer LPUART eDMA transfer structure. See #lpuart_transfer_t.
+ * retval kStatus_Success if succeed, others failed.
+ * retval kStatus_LPUART_TxBusy Previous transfer on going.
+ * retval kStatus_InvalidArgument Invalid argument.
+ */
 status_t LPUART_SendEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, lpuart_transfer_t *xfer)
 {
-    assert(handle);
-    assert(handle->txEdmaHandle);
-    assert(xfer);
-    assert(xfer->data);
-    assert(xfer->dataSize);
+    assert(NULL != handle);
+    assert(NULL != handle->txEdmaHandle);
+    assert(NULL != xfer);
+    assert(NULL != xfer->data);
+    assert(0U != xfer->dataSize);
 
     edma_transfer_config_t xferConfig;
     status_t status;
 
     /* If previous TX not finished. */
-    if (kLPUART_TxBusy == handle->txState)
+    if ((uint8_t)kLPUART_TxBusy == handle->txState)
     {
         status = kStatus_LPUART_TxBusy;
     }
     else
     {
-        handle->txState = kLPUART_TxBusy;
+        handle->txState       = (uint8_t)kLPUART_TxBusy;
         handle->txDataSizeAll = xfer->dataSize;
 
         /* Prepare transfer. */
-        EDMA_PrepareTransfer(&xferConfig, xfer->data, sizeof(uint8_t), (void *)LPUART_GetDataRegisterAddress(base),
-                             sizeof(uint8_t), sizeof(uint8_t), xfer->dataSize, kEDMA_MemoryToPeripheral);
+        EDMA_PrepareTransfer(&xferConfig, xfer->data, sizeof(uint8_t),
+                             (void *)(uint32_t *)LPUART_GetDataRegisterAddress(base), sizeof(uint8_t), sizeof(uint8_t),
+                             xfer->dataSize, kEDMA_MemoryToPeripheral);
 
         /* Store the initially configured eDMA minor byte transfer count into the LPUART handle */
-        handle->nbytes = sizeof(uint8_t);
+        handle->nbytes = (uint8_t)sizeof(uint8_t);
 
         /* Submit transfer. */
-        EDMA_SubmitTransfer(handle->txEdmaHandle, &xferConfig);
+        if (kStatus_Success !=
+            EDMA_SubmitTransfer(handle->txEdmaHandle, (const edma_transfer_config_t *)(uint32_t)&xferConfig))
+        {
+            return kStatus_Fail;
+        }
         EDMA_StartTransfer(handle->txEdmaHandle);
 
         /* Enable LPUART TX EDMA. */
@@ -274,36 +275,53 @@ status_t LPUART_SendEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, lpuart
     return status;
 }
 
+/*!
+ * brief Receives data using eDMA.
+ *
+ * This function receives data using eDMA. This is non-blocking function, which returns
+ * right away. When all data is received, the receive callback function is called.
+ *
+ * param base LPUART peripheral base address.
+ * param handle Pointer to lpuart_edma_handle_t structure.
+ * param xfer LPUART eDMA transfer structure, see #lpuart_transfer_t.
+ * retval kStatus_Success if succeed, others fail.
+ * retval kStatus_LPUART_RxBusy Previous transfer ongoing.
+ * retval kStatus_InvalidArgument Invalid argument.
+ */
 status_t LPUART_ReceiveEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, lpuart_transfer_t *xfer)
 {
-    assert(handle);
-    assert(handle->rxEdmaHandle);
-    assert(xfer);
-    assert(xfer->data);
-    assert(xfer->dataSize);
+    assert(NULL != handle);
+    assert(NULL != handle->rxEdmaHandle);
+    assert(NULL != xfer);
+    assert(NULL != xfer->data);
+    assert(0U != xfer->dataSize);
 
     edma_transfer_config_t xferConfig;
     status_t status;
 
     /* If previous RX not finished. */
-    if (kLPUART_RxBusy == handle->rxState)
+    if ((uint8_t)kLPUART_RxBusy == handle->rxState)
     {
         status = kStatus_LPUART_RxBusy;
     }
     else
     {
-        handle->rxState = kLPUART_RxBusy;
+        handle->rxState       = (uint8_t)kLPUART_RxBusy;
         handle->rxDataSizeAll = xfer->dataSize;
 
         /* Prepare transfer. */
-        EDMA_PrepareTransfer(&xferConfig, (void *)LPUART_GetDataRegisterAddress(base), sizeof(uint8_t), xfer->data,
-                             sizeof(uint8_t), sizeof(uint8_t), xfer->dataSize, kEDMA_PeripheralToMemory);
+        EDMA_PrepareTransfer(&xferConfig, (void *)(uint32_t *)LPUART_GetDataRegisterAddress(base), sizeof(uint8_t),
+                             xfer->data, sizeof(uint8_t), sizeof(uint8_t), xfer->dataSize, kEDMA_PeripheralToMemory);
 
         /* Store the initially configured eDMA minor byte transfer count into the LPUART handle */
-        handle->nbytes = sizeof(uint8_t);
+        handle->nbytes = (uint8_t)sizeof(uint8_t);
 
         /* Submit transfer. */
-        EDMA_SubmitTransfer(handle->rxEdmaHandle, &xferConfig);
+        if (kStatus_Success !=
+            EDMA_SubmitTransfer(handle->rxEdmaHandle, (const edma_transfer_config_t *)(uint32_t)&xferConfig))
+        {
+            return kStatus_Fail;
+        }
         EDMA_StartTransfer(handle->rxEdmaHandle);
 
         /* Enable LPUART RX EDMA. */
@@ -315,10 +333,18 @@ status_t LPUART_ReceiveEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, lpu
     return status;
 }
 
+/*!
+ * brief Aborts the sent data using eDMA.
+ *
+ * This function aborts the sent data using eDMA.
+ *
+ * param base LPUART peripheral base address.
+ * param handle Pointer to lpuart_edma_handle_t structure.
+ */
 void LPUART_TransferAbortSendEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle)
 {
-    assert(handle);
-    assert(handle->txEdmaHandle);
+    assert(NULL != handle);
+    assert(NULL != handle->txEdmaHandle);
 
     /* Disable LPUART TX EDMA. */
     LPUART_EnableTxDMA(base, false);
@@ -326,13 +352,21 @@ void LPUART_TransferAbortSendEDMA(LPUART_Type *base, lpuart_edma_handle_t *handl
     /* Stop transfer. */
     EDMA_AbortTransfer(handle->txEdmaHandle);
 
-    handle->txState = kLPUART_TxIdle;
+    handle->txState = (uint8_t)kLPUART_TxIdle;
 }
 
+/*!
+ * brief Aborts the received data using eDMA.
+ *
+ * This function aborts the received data using eDMA.
+ *
+ * param base LPUART peripheral base address.
+ * param handle Pointer to lpuart_edma_handle_t structure.
+ */
 void LPUART_TransferAbortReceiveEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle)
 {
-    assert(handle);
-    assert(handle->rxEdmaHandle);
+    assert(NULL != handle);
+    assert(NULL != handle->rxEdmaHandle);
 
     /* Disable LPUART RX EDMA. */
     LPUART_EnableRxDMA(base, false);
@@ -340,41 +374,66 @@ void LPUART_TransferAbortReceiveEDMA(LPUART_Type *base, lpuart_edma_handle_t *ha
     /* Stop transfer. */
     EDMA_AbortTransfer(handle->rxEdmaHandle);
 
-    handle->rxState = kLPUART_RxIdle;
+    handle->rxState = (uint8_t)kLPUART_RxIdle;
 }
 
+/*!
+ * brief Gets the number of received bytes.
+ *
+ * This function gets the number of received bytes.
+ *
+ * param base LPUART peripheral base address.
+ * param handle LPUART handle pointer.
+ * param count Receive bytes count.
+ * retval kStatus_NoTransferInProgress No receive in progress.
+ * retval kStatus_InvalidArgument Parameter is invalid.
+ * retval kStatus_Success Get successfully through the parameter \p count;
+ */
 status_t LPUART_TransferGetReceiveCountEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, uint32_t *count)
 {
-    assert(handle);
-    assert(handle->rxEdmaHandle);
-    assert(count);
+    assert(NULL != handle);
+    assert(NULL != handle->rxEdmaHandle);
+    assert(NULL != count);
 
-    if (kLPUART_RxIdle == handle->rxState)
+    if ((uint8_t)kLPUART_RxIdle == handle->rxState)
     {
         return kStatus_NoTransferInProgress;
     }
 
     *count = handle->rxDataSizeAll -
-             (uint32_t)handle->nbytes *
-                 EDMA_GetRemainingMajorLoopCount(handle->rxEdmaHandle->base, handle->rxEdmaHandle->channel);
+             ((uint32_t)handle->nbytes *
+              EDMA_GetRemainingMajorLoopCount(handle->rxEdmaHandle->base, handle->rxEdmaHandle->channel));
 
     return kStatus_Success;
 }
 
+/*!
+ * brief Gets the number of bytes written to the LPUART TX register.
+ *
+ * This function gets the number of bytes written to the LPUART TX
+ * register by DMA.
+ *
+ * param base LPUART peripheral base address.
+ * param handle LPUART handle pointer.
+ * param count Send bytes count.
+ * retval kStatus_NoTransferInProgress No send in progress.
+ * retval kStatus_InvalidArgument Parameter is invalid.
+ * retval kStatus_Success Get successfully through the parameter \p count;
+ */
 status_t LPUART_TransferGetSendCountEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, uint32_t *count)
 {
-    assert(handle);
-    assert(handle->txEdmaHandle);
-    assert(count);
+    assert(NULL != handle);
+    assert(NULL != handle->txEdmaHandle);
+    assert(NULL != count);
 
-    if (kLPUART_TxIdle == handle->txState)
+    if ((uint8_t)kLPUART_TxIdle == handle->txState)
     {
         return kStatus_NoTransferInProgress;
     }
 
     *count = handle->txDataSizeAll -
-             (uint32_t)handle->nbytes *
-                 EDMA_GetRemainingMajorLoopCount(handle->txEdmaHandle->base, handle->txEdmaHandle->channel);
+             ((uint32_t)handle->nbytes *
+              EDMA_GetRemainingMajorLoopCount(handle->txEdmaHandle->base, handle->txEdmaHandle->channel));
 
     return kStatus_Success;
 }
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_lpuart_edma.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_lpuart_edma.h
index a6f240147a8..53ac71036bf 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_lpuart_edma.h
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_lpuart_edma.h
@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
+ * Copyright 2016-2018 NXP
  * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
  *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 #ifndef _FSL_LPUART_EDMA_H_
 #define _FSL_LPUART_EDMA_H_
@@ -48,8 +22,8 @@
 
 /*! @name Driver version */
 /*@{*/
-/*! @brief LPUART EDMA driver version 2.2.5. */
-#define FSL_LPUART_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 2, 5))
+/*! @brief LPUART EDMA driver version 2.2.7. */
+#define FSL_LPUART_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 2, 7))
 /*@}*/
 
 /* Forward declaration of the handle typedef. */
@@ -62,8 +36,8 @@ typedef void (*lpuart_edma_transfer_callback_t)(LPUART_Type *base,
                                                 void *userData);
 
 /*!
-* @brief LPUART eDMA handle
-*/
+ * @brief LPUART eDMA handle
+ */
 struct _lpuart_edma_handle
 {
     lpuart_edma_transfer_callback_t callback; /*!< Callback function. */
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_ocotp.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_ocotp.c
new file mode 100644
index 00000000000..9ac6f0056b8
--- /dev/null
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_ocotp.c
@@ -0,0 +1,263 @@
+/*
+ * Copyright 2019 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_ocotp.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.ocotp"
+#endif
+
+/* Wait time should be not less than 150ns . */
+#define OCOTP_TIMING_WAIT_NS (uint64_t)150
+/* Relex time should be not less than 100ns . */
+#define OCOTP_TIMING_RELEX_NS (uint64_t)100
+/* Program time should be rang from 9000ns~11000ns. */
+#define OCOTP_TIMING_PROGRAM_NS (uint64_t)10000
+/* Read time should be less than 40ns. */
+#define OCOTP_TIMING_READ_NS (uint64_t)40
+
+/* Unlock key is 0x3E77. */
+#define OCOTP_WRITE_UNLOCK_KEY (0x3E77)
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*!
+ * @brief Set read timing configuration.
+ *
+ * @param base          OCOTP peripheral base addess.
+ * @param timingConfig  configuration of timing.
+ */
+static void OCOTP_SetReadTiming(OCOTP_Type *base, ocotp_timing_t timingConfig);
+
+/*!
+ * @brief Set write timing configuration.
+ *
+ * @param base          OCOTP peripheral base addess.
+ * @param timingConfig  configuration of timing.
+ */
+static void OCOTP_SetWriteTiming(OCOTP_Type *base, ocotp_timing_t timingConfig);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/* Timing configuration for OCOTP controller. */
+ocotp_timing_t s_timingConfig;
+
+/*******************************************************************************
+ * Code
+ *******************************************************************************/
+/* Reload the shadow register. */
+void OCOTP_ReloadShadowRegister(OCOTP_Type *base)
+{
+    assert(NULL != base);
+
+    /* Make sure the OCOTP is ready, Overlapped accesses are not supported by the controller. */
+    while (OCOTP_CheckBusyStatus(base))
+    {
+    }
+
+    /* Clear access error status bit. */
+    OCOTP_ClearErrorStatus(base);
+
+    /* Set the read timing. */
+    OCOTP_SetReadTiming(base, s_timingConfig);
+
+    /* Wait for the OCOTP controller not busy. */
+    while (OCOTP_CheckBusyStatus(base))
+    {
+    }
+
+    /* Set reload bit. */
+    base->CTRL_SET = OCOTP_CTRL_RELOAD_SHADOWS(1);
+
+    /* Wait for the OCOTP controller not busy. */
+    while (OCOTP_CheckBusyStatus(base))
+    {
+    }
+    /* Wait for shadow register reload complete. this bit will be auto clear by OCOTP once operation is complete. */
+    while (OCOTP_CTRL_RELOAD_SHADOWS_MASK == (base->CTRL & OCOTP_CTRL_RELOAD_SHADOWS_MASK))
+    {
+    }
+}
+
+static void OCOTP_SetReadTiming(OCOTP_Type *base, ocotp_timing_t timingConfig)
+{
+    uint32_t timingValue = base->TIMING;
+
+    timingValue &= ~(OCOTP_TIMING_RELAX_MASK | OCOTP_TIMING_STROBE_READ_MASK | OCOTP_TIMING_WAIT_MASK);
+    timingValue |= OCOTP_TIMING_RELAX(timingConfig.relax) | OCOTP_TIMING_STROBE_READ(timingConfig.strobe_read) |
+                   OCOTP_TIMING_WAIT(timingConfig.wait);
+    base->TIMING = timingValue;
+}
+
+static void OCOTP_SetWriteTiming(OCOTP_Type *base, ocotp_timing_t timingConfig)
+{
+    uint32_t timingValue = base->TIMING;
+
+    timingValue &= ~(OCOTP_TIMING_RELAX_MASK | OCOTP_TIMING_STROBE_PROG_MASK | OCOTP_TIMING_WAIT_MASK);
+    timingValue |= OCOTP_TIMING_RELAX(timingConfig.relax) | OCOTP_TIMING_STROBE_PROG(timingConfig.strobe_prog) |
+                   OCOTP_TIMING_WAIT(timingConfig.wait);
+
+    base->TIMING = timingValue;
+}
+
+/* Initializes OCOTP controller. */
+void OCOTP_Init(OCOTP_Type *base, uint32_t srcClock_Hz)
+{
+    assert(NULL != base);
+    assert(0UL != srcClock_Hz);
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Enable OCOTP clock */
+    CLOCK_EnableClock(kCLOCK_Ocotp);
+#endif
+
+    /* tWait time shoule be higher than OCOTP_TIMING_WAIT_NS. */
+    s_timingConfig.wait = (OCOTP_TIMING_WAIT_NS * srcClock_Hz + 1000000000) / 1000000000 - 1;
+
+    /* tRelax time shoule be higher than OCOTP_TIMING_RELEX_NS. */
+    s_timingConfig.relax = (OCOTP_TIMING_RELEX_NS * srcClock_Hz + 1000000000) / 1000000000 - 1;
+
+    /* tStrobe_prog time should be close to OCOTP_TIMING_PROGRAM_NS, only add half of 1000000000. */
+    s_timingConfig.strobe_prog =
+        (OCOTP_TIMING_PROGRAM_NS * srcClock_Hz + 500000000) / 1000000000 + 2 * (s_timingConfig.relax + 1) - 1;
+
+    /* tStrobe_read time should be higher than OCOTP_TIMING_READ_NS. */
+    s_timingConfig.strobe_read =
+        (OCOTP_TIMING_READ_NS * srcClock_Hz + 1000000000) / 1000000000 + 2 * (s_timingConfig.relax + 1) - 1;
+}
+
+/* De-init OCOTP controller. */
+void OCOTP_Deinit(OCOTP_Type *base)
+{
+    assert(NULL != base);
+
+    s_timingConfig.wait        = 0UL;
+    s_timingConfig.relax       = 0UL;
+    s_timingConfig.strobe_prog = 0UL;
+    s_timingConfig.strobe_read = 0UL;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Disable OCOTP clock */
+    CLOCK_DisableClock(kCLOCK_Ocotp);
+#endif
+}
+
+/* Read the fuse shadow register. */
+uint32_t OCOTP_ReadFuseShadowRegister(OCOTP_Type *base, uint32_t address)
+{
+    assert(NULL != base);
+
+    /* Make sure the OCOTP is ready, Overlapped accesses are not supported by the controller. */
+    while (OCOTP_CheckBusyStatus(base))
+    {
+    }
+
+    /* If ERROR bit was set, clear access error status bit. */
+    if (OCOTP_CheckErrorStatus(base))
+    {
+        OCOTP_ClearErrorStatus(base);
+    }
+
+    /* Set the read timing. */
+    OCOTP_SetReadTiming(base, s_timingConfig);
+
+    /* Wait for busy bit is cleared. */
+    while (OCOTP_CheckBusyStatus(base))
+    {
+    }
+
+    /* Clear access error status bit. */
+    if (OCOTP_CheckErrorStatus(base))
+    {
+        OCOTP_ClearErrorStatus(base);
+    }
+
+    /* Write requested address to register. */
+    base->CTRL_CLR = OCOTP_CTRL_CLR_ADDR_MASK;
+    base->CTRL_SET = OCOTP_CTRL_SET_ADDR(address);
+
+    /* Set OCOTP auto read enable. */
+    base->READ_CTRL = OCOTP_READ_CTRL_READ_FUSE_MASK;
+
+    /* Wait for busy bit is cleared, and no error occurred on controller. */
+    while (OCOTP_CheckBusyStatus(base))
+    {
+    }
+
+    /* If ERROR bit was set, this may be mean that the accsee to the register was wrong. */
+    if (OCOTP_CheckErrorStatus(base))
+    {
+        /* Clear access error status bit. */
+        OCOTP_ClearErrorStatus(base);
+    }
+
+    /* Read the fuse data. */
+    return (base->READ_FUSE_DATA);
+}
+
+/* Write the fuse shadow register. */
+status_t OCOTP_WriteFuseShadowRegister(OCOTP_Type *base, uint32_t address, uint32_t data)
+{
+    assert(NULL != base);
+
+    /* Make sure the OCOTP is ready, Overlapped accesses are not supported by the controller. */
+    while (OCOTP_CheckBusyStatus(base))
+    {
+    }
+
+    /* Clear access error status bit. */
+    if (OCOTP_CheckErrorStatus(base))
+    {
+        OCOTP_ClearErrorStatus(base);
+    }
+
+    /* Set write timing for OCOTP controller. */
+    OCOTP_SetWriteTiming(base, s_timingConfig);
+
+    /* Wait for busy bit is cleared. */
+    while (OCOTP_CheckBusyStatus(base))
+    {
+    }
+
+    /* Clear access error status bit. */
+    if (OCOTP_CheckErrorStatus(base))
+    {
+        OCOTP_ClearErrorStatus(base);
+    }
+
+    /* Write requested address and unlock key to register. */
+    base->CTRL_CLR = OCOTP_CTRL_CLR_ADDR_MASK | OCOTP_CTRL_WR_UNLOCK_MASK;
+    base->CTRL_SET = OCOTP_CTRL_SET_ADDR(address) | OCOTP_CTRL_WR_UNLOCK(OCOTP_WRITE_UNLOCK_KEY);
+
+    /* Write data to register. */
+    base->DATA = data;
+
+    /* Wait for busy bit is cleared, and no error occurred on controller. */
+    while (OCOTP_CheckBusyStatus(base))
+    {
+    }
+
+    /* If ERROR bit was set, this may be mean that the accsee to the register was wrong. */
+    if (OCOTP_CheckErrorStatus(base))
+    {
+        /* Clear access error status bit. */
+        OCOTP_ClearErrorStatus(base);
+
+        return kStatus_OCOTP_AccessError;
+    }
+
+    /* Reload the fuse register. */
+    OCOTP_ReloadShadowRegister(base);
+
+    return kStatus_Success;
+}
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_ocotp.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_ocotp.h
new file mode 100644
index 00000000000..d962187337d
--- /dev/null
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_ocotp.h
@@ -0,0 +1,153 @@
+/*
+ * Copyright 2019 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _FSL_OCOTP_H_
+#define _FSL_OCOTP_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup ocotp
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ *******************************************************************************/
+/*! @name Driver version */
+/*@{*/
+/*! @brief OCOTP driver version 2.0.0 */
+#define FSL_OCOTP_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*@}*/
+
+/*! @brief Error codes for the OCOTP driver. */
+enum _ocotp_status
+{
+    kStatus_OCOTP_AccessError = MAKE_STATUS(kStatusGroup_SDK_OCOTP, 0), /*!< eFuse and shadow register access error. */
+    kStatus_OCOTP_CrcFail     = MAKE_STATUS(kStatusGroup_SDK_OCOTP, 1), /*!< CRC check failed. */
+};
+
+/*! @brief OCOTP timing structure.
+ *  Note that, these value are used for calcalating the read/write timings.
+ *  And the values should statisfy below rules:
+ *
+ *  Tsp_rd=(WAIT+1)/ipg_clk_freq should be >= 150ns;
+ *  Tsp_pgm=(RELAX+1)/ipg_clk_freq should be >= 100ns;
+ *  Trd = ((STROBE_READ+1)- 2*(RELAX_READ+1)) /ipg_clk_freq,
+ *  The Trd is required to be larger than 40 ns.
+ *  Tpgm = ((STROBE_PROG+1)- 2*(RELAX_PROG+1)) /ipg_clk_freq;
+ *  The Tpgm should be configured within the range of 9000 ns < Tpgm < 11000 ns;
+ */
+typedef struct _ocotp_timing
+{
+    uint32_t wait;        /*!< Wait time value to fill in the TIMING register. */
+    uint32_t relax;       /*!< Relax time value to fill in the TIMING register. */
+    uint32_t strobe_prog; /*!< Storbe program time value to fill in the TIMING register. */
+    uint32_t strobe_read; /*!< Storbe read time value to fill in the TIMING register. */
+} ocotp_timing_t;
+
+/*******************************************************************************
+ * API
+ *******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Initializes OCOTP controller.
+ *
+ * @param base         OCOTP peripheral base address.
+ * @param srcClock_Hz  source clock frequency in unit of Hz.
+ */
+void OCOTP_Init(OCOTP_Type *base, uint32_t srcClock_Hz);
+
+/*!
+ * @brief De-initializes OCOTP controller.
+ *
+ * @retval kStatus_Success upon successful execution, error status otherwise.
+ */
+void OCOTP_Deinit(OCOTP_Type *base);
+
+/*!
+ * @brief Checking the BUSY bit in CTRL register.
+ * Checking this BUSY bit will help confirm if the OCOTP controller is ready for access.
+ *
+ * @param base         OCOTP peripheral base address.
+ * @retval       true for bit set and false for cleared.
+ */
+static inline bool OCOTP_CheckBusyStatus(OCOTP_Type *base)
+{
+    return ((OCOTP_CTRL_BUSY_MASK == (base->CTRL & OCOTP_CTRL_BUSY_MASK)) ? (true) : (false));
+}
+
+/*!
+ * @brief Checking the ERROR bit in CTRL register.
+ *
+ * @param base         OCOTP peripheral base address.
+ * @retval       true for bit set and false for cleared.
+ */
+static inline bool OCOTP_CheckErrorStatus(OCOTP_Type *base)
+{
+    return ((OCOTP_CTRL_ERROR_MASK == (base->CTRL & OCOTP_CTRL_ERROR_MASK)) ? (true) : (false));
+}
+
+/*!
+ * @brief Clear the error bit if this bit is set.
+ *
+ * @param base  OCOTP peripheral base address.
+ */
+static inline void OCOTP_ClearErrorStatus(OCOTP_Type *base)
+{
+    base->CTRL_CLR = OCOTP_CTRL_CLR_ERROR_MASK;
+}
+
+/*!
+ * @brief Reload the shadow register.
+ * This function will help reload the shadow register without reseting the OCOTP module.
+ * Please make sure the OCOTP has been initialized before calling this API.
+ *
+ * @param base OCOTP peripheral base addess.
+ */
+void OCOTP_ReloadShadowRegister(OCOTP_Type *base);
+
+/*!
+ * @brief Read the fuse shadow register with the fuse addess.
+ *
+ * @param base     OCOTP peripheral base address.
+ * @param address  the fuse address to be read from.
+ */
+uint32_t OCOTP_ReadFuseShadowRegister(OCOTP_Type *base, uint32_t address);
+
+/*!
+ * @brief Write the fuse shadow register with the fuse addess and data.
+ * Please make sure the wrtie address is not locked while calling this API.
+ *
+ * @param base     OCOTP peripheral base address.
+ * @param address  the fuse address to be written.
+ * @param data     the value will be writen to fuse address.
+ * @retval   write status, kStatus_Success for success and kStatus_Fail for failed.
+ */
+status_t OCOTP_WriteFuseShadowRegister(OCOTP_Type *base, uint32_t address, uint32_t data);
+
+/*!
+ * @brief Get the OCOTP controller version from the register.
+ *
+ * @param base    OCOTP peripheral base address.
+ * @retval  return the version value.
+ */
+static inline uint32_t OCOTP_GetVersion(OCOTP_Type *base)
+{
+    return (base->VERSION);
+}
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* _FSL_OCOTP_H_ */
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_pit.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_pit.c
index e6ff9c8745e..2d15e76865e 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_pit.c
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_pit.c
@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
  * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
  *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include "fsl_pit.h"
@@ -39,7 +13,6 @@
 #define FSL_COMPONENT_ID "platform.drivers.pit"
 #endif
 
-
 /*******************************************************************************
  * Prototypes
  ******************************************************************************/
@@ -84,9 +57,17 @@ static uint32_t PIT_GetInstance(PIT_Type *base)
     return instance;
 }
 
+/*!
+ * brief Ungates the PIT clock, enables the PIT module, and configures the peripheral for basic operations.
+ *
+ * note This API should be called at the beginning of the application using the PIT driver.
+ *
+ * param base   PIT peripheral base address
+ * param config Pointer to the user's PIT config structure
+ */
 void PIT_Init(PIT_Type *base, const pit_config_t *config)
 {
-    assert(config);
+    assert(NULL != config);
 
 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* Ungate the PIT clock*/
@@ -97,8 +78,17 @@ void PIT_Init(PIT_Type *base, const pit_config_t *config)
     /* Enable PIT timers */
     base->MCR &= ~PIT_MCR_MDIS_MASK;
 #endif
+
+#if defined(FSL_FEATURE_PIT_TIMER_COUNT) && (FSL_FEATURE_PIT_TIMER_COUNT)
+    /* Clear the timer enable bit for all channels to make sure the channel's timer is disabled. */
+    for (uint8_t i = 0U; i < (uint32_t)FSL_FEATURE_PIT_TIMER_COUNT; i++)
+    {
+        base->CHANNEL[i].TCTRL &= ~PIT_TCTRL_TEN_MASK;
+    }
+#endif /* FSL_FEATURE_PIT_TIMER_COUNT */
+
     /* Config timer operation when in debug mode */
-    if (config->enableRunInDebug)
+    if (true == config->enableRunInDebug)
     {
         base->MCR &= ~PIT_MCR_FRZ_MASK;
     }
@@ -108,6 +98,11 @@ void PIT_Init(PIT_Type *base, const pit_config_t *config)
     }
 }
 
+/*!
+ * brief Gates the PIT clock and disables the PIT module.
+ *
+ * param base PIT peripheral base address
+ */
 void PIT_Deinit(PIT_Type *base)
 {
 #if defined(FSL_FEATURE_PIT_HAS_MDIS) && FSL_FEATURE_PIT_HAS_MDIS
@@ -123,6 +118,19 @@ void PIT_Deinit(PIT_Type *base)
 
 #if defined(FSL_FEATURE_PIT_HAS_LIFETIME_TIMER) && FSL_FEATURE_PIT_HAS_LIFETIME_TIMER
 
+/*!
+ * brief Reads the current lifetime counter value.
+ *
+ * The lifetime timer is a 64-bit timer which chains timer 0 and timer 1 together.
+ * Timer 0 and 1 are chained by calling the PIT_SetTimerChainMode before using this timer.
+ * The period of lifetime timer is equal to the "period of timer 0 * period of timer 1".
+ * For the 64-bit value, the higher 32-bit has the value of timer 1, and the lower 32-bit
+ * has the value of timer 0.
+ *
+ * param base PIT peripheral base address
+ *
+ * return Current lifetime timer value
+ */
 uint64_t PIT_GetLifetimeTimerCount(PIT_Type *base)
 {
     uint32_t valueH = 0U;
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_pit.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_pit.h
index 55abdd5db8b..1de4984358f 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_pit.h
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_pit.h
@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
  * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
  *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 #ifndef _FSL_PIT_H_
 #define _FSL_PIT_H_
@@ -41,14 +15,14 @@
  * @{
  */
 
-
 /*******************************************************************************
  * Definitions
  ******************************************************************************/
 
 /*! @name Driver version */
 /*@{*/
-#define FSL_PIT_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */
+/*! @brief PIT Driver Version 2.0.2 */
+#define FSL_PIT_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
 /*@}*/
 
 /*!
@@ -126,11 +100,11 @@ void PIT_Deinit(PIT_Type *base);
  * @code
  *     config->enableRunInDebug = false;
  * @endcode
- * @param config Pointer to the onfiguration structure.
+ * @param config Pointer to the configuration structure.
  */
 static inline void PIT_GetDefaultConfig(pit_config_t *config)
 {
-    assert(config);
+    assert(NULL != config);
 
     /* Timers are stopped in Debug mode */
     config->enableRunInDebug = false;
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_pmu.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_pmu.c
index 717f5f8a693..f3e0571f0d1 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_pmu.c
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_pmu.c
@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2016, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
  * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
  *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 #include "fsl_pmu.h"
 
@@ -38,6 +12,10 @@
 #define FSL_COMPONENT_ID "platform.drivers.pmu"
 #endif
 
+/*!
+ * name Status.
+ * {
+ */
 
 uint32_t PMU_GetStatusFlags(PMU_Type *base)
 {
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_pmu.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_pmu.h
index b7108941de6..6d9639d22eb 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_pmu.h
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_pmu.h
@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2016, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
  * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 #ifndef _FSL_PMU_H_
 #define _FSL_PMU_H_
@@ -91,10 +65,10 @@ typedef enum _pmu_3p0_vbus_voltage_source
  */
 typedef enum _pmu_core_reg_voltage_ramp_rate
 {
-    kPMU_CoreRegVoltageRampRateFast = 0U,       /*!< Fast. */
+    kPMU_CoreRegVoltageRampRateFast       = 0U, /*!< Fast. */
     kPMU_CoreRegVoltageRampRateMediumFast = 1U, /*!< Medium Fast. */
     kPMU_CoreRegVoltageRampRateMediumSlow = 2U, /*!< Medium Slow. */
-    kPMU_CoreRegVoltageRampRateSlow = 0U,       /*!< Slow. */
+    kPMU_CoreRegVoltageRampRateSlow       = 0U, /*!< Slow. */
 } pmu_core_reg_voltage_ramp_rate_t;
 
 #if defined(FSL_FEATURE_PMU_HAS_LOWPWR_CTRL) && FSL_FEATURE_PMU_HAS_LOWPWR_CTRL
@@ -103,11 +77,11 @@ typedef enum _pmu_core_reg_voltage_ramp_rate
  */
 enum _pmu_power_gate
 {
-    kPMU_PowerGateDisplay = PMU_LOWPWR_CTRL_MIX_PWRGATE_MASK,          /*!< Display power gate control. */
-    kPMU_PowerGateDisplayLogic = PMU_LOWPWR_CTRL_DISPLAY_PWRGATE_MASK, /*!< Display logic power gate control. */
-    kPMU_PowerGateL2 = PMU_LOWPWR_CTRL_L2_PWRGATE_MASK,                /*!< L2 power gate control. */
-    kPMU_PowerGateL1 = PMU_LOWPWR_CTRL_L1_PWRGATE_MASK,                /*!< L1 power gate control. */
-    kPMU_PowerGateRefTopIBias = PMU_LOWPWR_CTRL_REFTOP_IBIAS_OFF_MASK, /*!< Low power reftop ibias disable. */
+    kPMU_PowerGateDisplay      = PMU_LOWPWR_CTRL_MIX_PWRGATE_MASK,      /*!< Display power gate control. */
+    kPMU_PowerGateDisplayLogic = PMU_LOWPWR_CTRL_DISPLAY_PWRGATE_MASK,  /*!< Display logic power gate control. */
+    kPMU_PowerGateL2           = PMU_LOWPWR_CTRL_L2_PWRGATE_MASK,       /*!< L2 power gate control. */
+    kPMU_PowerGateL1           = PMU_LOWPWR_CTRL_L1_PWRGATE_MASK,       /*!< L1 power gate control. */
+    kPMU_PowerGateRefTopIBias  = PMU_LOWPWR_CTRL_REFTOP_IBIAS_OFF_MASK, /*!< Low power reftop ibias disable. */
 };
 #endif /*  FSL_FEATURE_PMU_HAS_LOWPWR_CTRL. */
 
@@ -117,7 +91,7 @@ enum _pmu_power_gate
 typedef enum _pmu_power_bandgap
 {
     kPMU_NormalPowerBandgap = 0U, /*!< Normal power bandgap. */
-    kPMU_LowPowerBandgap = 1U,    /*!< Low power bandgap. */
+    kPMU_LowPowerBandgap    = 1U, /*!< Low power bandgap. */
 } pmu_power_bandgap_t;
 
 /*******************************************************************************
@@ -133,6 +107,13 @@ extern "C" {
  * @{
  */
 
+/*!
+ * @brief Get PMU status flags.
+ *
+ * @param base PMU peripheral base address.
+ * @return PMU status flags.It indicate if regulator output of 1P1,3P0 and 2P5 is ok
+ * and brownout output of 1P1,3P0 and 2P5 is detected.
+ */
 uint32_t PMU_GetStatusFlags(PMU_Type *base);
 
 /*@}*/
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_pwm.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_pwm.c
index a244750f80c..ebb9d283ddd 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_pwm.c
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_pwm.c
@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
  * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
  *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include "fsl_pwm.h"
@@ -39,7 +13,6 @@
 #define FSL_COMPONENT_ID "platform.drivers.pwm"
 #endif
 
-
 /*******************************************************************************
  * Prototypes
  ******************************************************************************/
@@ -84,6 +57,17 @@ static uint32_t PWM_GetInstance(PWM_Type *base)
     return instance;
 }
 
+/*!
+ * brief Ungates the PWM submodule clock and configures the peripheral for basic operation.
+ *
+ * note This API should be called at the beginning of the application using the PWM driver.
+ *
+ * param base      PWM peripheral base address
+ * param subModule PWM submodule to configure
+ * param config    Pointer to user's PWM config structure.
+ *
+ * return kStatus_Success means success; else failed.
+ */
 status_t PWM_Init(PWM_Type *base, pwm_submodule_t subModule, const pwm_config_t *config)
 {
     assert(config);
@@ -187,6 +171,12 @@ status_t PWM_Init(PWM_Type *base, pwm_submodule_t subModule, const pwm_config_t
     return kStatus_Success;
 }
 
+/*!
+ * brief Gate the PWM submodule clock
+ *
+ * param base      PWM peripheral base address
+ * param subModule PWM submodule to deinitialize
+ */
 void PWM_Deinit(PWM_Type *base, pwm_submodule_t subModule)
 {
     /* Stop the submodule */
@@ -198,10 +188,33 @@ void PWM_Deinit(PWM_Type *base, pwm_submodule_t subModule)
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }
 
+/*!
+ * brief  Fill in the PWM config struct with the default settings
+ *
+ * The default values are:
+ * code
+ *   config->enableDebugMode = false;
+ *   config->enableWait = false;
+ *   config->reloadSelect = kPWM_LocalReload;
+ *   config->faultFilterCount = 0;
+ *   config->faultFilterPeriod = 0;
+ *   config->clockSource = kPWM_BusClock;
+ *   config->prescale = kPWM_Prescale_Divide_1;
+ *   config->initializationControl = kPWM_Initialize_LocalSync;
+ *   config->forceTrigger = kPWM_Force_Local;
+ *   config->reloadFrequency = kPWM_LoadEveryOportunity;
+ *   config->reloadLogic = kPWM_ReloadImmediate;
+ *   config->pairOperation = kPWM_Independent;
+ * endcode
+ * param config Pointer to user's PWM config structure.
+ */
 void PWM_GetDefaultConfig(pwm_config_t *config)
 {
     assert(config);
 
+    /* Initializes the configure structure to zero. */
+    memset(config, 0, sizeof(*config));
+
     /* PWM is paused in debug mode */
     config->enableDebugMode = false;
     /* PWM is paused in wait mode */
@@ -230,6 +243,25 @@ void PWM_GetDefaultConfig(pwm_config_t *config)
     config->pairOperation = kPWM_Independent;
 }
 
+/*!
+ * brief Sets up the PWM signals for a PWM submodule.
+ *
+ * The function initializes the submodule according to the parameters passed in by the user. The function
+ * also sets up the value compare registers to match the PWM signal requirements.
+ * If the dead time insertion logic is enabled, the pulse period is reduced by the
+ * dead time period specified by the user.
+ *
+ * param base        PWM peripheral base address
+ * param subModule   PWM submodule to configure
+ * param chnlParams  Array of PWM channel parameters to configure the channel(s)
+ * param numOfChnls  Number of channels to configure, this should be the size of the array passed in.
+ *                    Array size should not be more than 2 as each submodule has 2 pins to output PWM
+ * param mode        PWM operation mode, options available in enumeration ::pwm_mode_t
+ * param pwmFreq_Hz  PWM signal frequency in Hz
+ * param srcClock_Hz PWM main counter clock in Hz.
+ *
+ * return Returns kStatusFail if there was error setting up the signal; kStatusSuccess otherwise
+ */
 status_t PWM_SetupPwm(PWM_Type *base,
                       pwm_submodule_t subModule,
                       const pwm_signal_param_t *chnlParams,
@@ -361,14 +393,14 @@ status_t PWM_SetupPwm(PWM_Type *base,
          */
         if (chnlParams->pwmChannel == kPWM_PwmA)
         {
-            polarityShift = PWM_OCTRL_POLA_SHIFT;
-            outputEnableShift = PWM_OUTEN_PWMA_EN_SHIFT;
+            polarityShift              = PWM_OCTRL_POLA_SHIFT;
+            outputEnableShift          = PWM_OUTEN_PWMA_EN_SHIFT;
             base->SM[subModule].DTCNT0 = PWM_DTCNT0_DTCNT0(chnlParams->deadtimeValue);
         }
         else
         {
-            polarityShift = PWM_OCTRL_POLB_SHIFT;
-            outputEnableShift = PWM_OUTEN_PWMB_EN_SHIFT;
+            polarityShift              = PWM_OCTRL_POLB_SHIFT;
+            outputEnableShift          = PWM_OUTEN_PWMB_EN_SHIFT;
             base->SM[subModule].DTCNT1 = PWM_DTCNT1_DTCNT1(chnlParams->deadtimeValue);
         }
 
@@ -391,6 +423,21 @@ status_t PWM_SetupPwm(PWM_Type *base,
     return kStatus_Success;
 }
 
+/*!
+ * brief Updates the PWM signal's dutycycle.
+ *
+ * The function updates the PWM dutycyle to the new value that is passed in.
+ * If the dead time insertion logic is enabled then the pulse period is reduced by the
+ * dead time period specified by the user.
+ *
+ * param base              PWM peripheral base address
+ * param subModule         PWM submodule to configure
+ * param pwmSignal         Signal (PWM A or PWM B) to update
+ * param currPwmMode       The current PWM mode set during PWM setup
+ * param dutyCyclePercent  New PWM pulse width, value should be between 0 to 100
+ *                          0=inactive signal(0% duty cycle)...
+ *                          100=active signal (100% duty cycle)
+ */
 void PWM_UpdatePwmDutycycle(PWM_Type *base,
                             pwm_submodule_t subModule,
                             pwm_channels_t pwmSignal,
@@ -405,7 +452,7 @@ void PWM_UpdatePwmDutycycle(PWM_Type *base,
     switch (currPwmMode)
     {
         case kPWM_SignedCenterAligned:
-            modulo = base->SM[subModule].VAL1;
+            modulo   = base->SM[subModule].VAL1;
             pulseCnt = modulo * 2;
             /* Calculate pulse width */
             pwmHighPulse = (pulseCnt * dutyCyclePercent) / 100;
@@ -440,7 +487,7 @@ void PWM_UpdatePwmDutycycle(PWM_Type *base,
             }
             break;
         case kPWM_SignedEdgeAligned:
-            modulo = base->SM[subModule].VAL1;
+            modulo   = base->SM[subModule].VAL1;
             pulseCnt = modulo * 2;
             /* Calculate pulse width */
             pwmHighPulse = (pulseCnt * dutyCyclePercent) / 100;
@@ -479,6 +526,17 @@ void PWM_UpdatePwmDutycycle(PWM_Type *base,
     }
 }
 
+/*!
+ * brief Sets up the PWM input capture
+ *
+ * Each PWM submodule has 3 pins that can be configured for use as input capture pins. This function
+ * sets up the capture parameters for each pin and enables the pin for input capture operation.
+ *
+ * param base               PWM peripheral base address
+ * param subModule          PWM submodule to configure
+ * param pwmChannel         Channel in the submodule to setup
+ * param inputCaptureParams Parameters passed in to set up the input pin
+ */
 void PWM_SetupInputCapture(PWM_Type *base,
                            pwm_submodule_t subModule,
                            pwm_channels_t pwmChannel,
@@ -555,6 +613,15 @@ void PWM_SetupInputCapture(PWM_Type *base,
     }
 }
 
+/*!
+ * brief Sets up the PWM fault protection.
+ *
+ * PWM has 4 fault inputs.
+ *
+ * param base        PWM peripheral base address
+ * param faultNum    PWM fault to configure.
+ * param faultParams Pointer to the PWM fault config structure
+ */
 void PWM_SetupFaults(PWM_Type *base, pwm_fault_input_t faultNum, const pwm_fault_param_t *faultParams)
 {
     assert(faultParams);
@@ -629,6 +696,17 @@ void PWM_SetupFaults(PWM_Type *base, pwm_fault_input_t faultNum, const pwm_fault
     base->FSTS = reg;
 }
 
+/*!
+ * brief Selects the signal to output on a PWM pin when a FORCE_OUT signal is asserted.
+ *
+ * The user specifies which channel to configure by supplying the submodule number and whether
+ * to modify PWM A or PWM B within that submodule.
+ *
+ * param base       PWM peripheral base address
+ * param subModule  PWM submodule to configure
+ * param pwmChannel Channel to configure
+ * param mode       Signal to output when a FORCE_OUT is triggered
+ */
 void PWM_SetupForceSignal(PWM_Type *base, pwm_submodule_t subModule, pwm_channels_t pwmChannel, pwm_force_signal_t mode)
 
 {
@@ -645,6 +723,14 @@ void PWM_SetupForceSignal(PWM_Type *base, pwm_submodule_t subModule, pwm_channel
     base->DTSRCSEL = reg;
 }
 
+/*!
+ * brief Enables the selected PWM interrupts
+ *
+ * param base      PWM peripheral base address
+ * param subModule PWM submodule to configure
+ * param mask      The interrupts to enable. This is a logical OR of members of the
+ *                  enumeration ::pwm_interrupt_enable_t
+ */
 void PWM_EnableInterrupts(PWM_Type *base, pwm_submodule_t subModule, uint32_t mask)
 {
     /* Upper 16 bits are for related to the submodule */
@@ -653,12 +739,29 @@ void PWM_EnableInterrupts(PWM_Type *base, pwm_submodule_t subModule, uint32_t ma
     base->FCTRL |= ((mask >> 16U) & PWM_FCTRL_FIE_MASK);
 }
 
+/*!
+ * brief Disables the selected PWM interrupts
+ *
+ * param base      PWM peripheral base address
+ * param subModule PWM submodule to configure
+ * param mask      The interrupts to enable. This is a logical OR of members of the
+ *                  enumeration ::pwm_interrupt_enable_t
+ */
 void PWM_DisableInterrupts(PWM_Type *base, pwm_submodule_t subModule, uint32_t mask)
 {
     base->SM[subModule].INTEN &= ~(mask & 0xFFFF);
     base->FCTRL &= ~((mask >> 16U) & PWM_FCTRL_FIE_MASK);
 }
 
+/*!
+ * brief Gets the enabled PWM interrupts
+ *
+ * param base      PWM peripheral base address
+ * param subModule PWM submodule to configure
+ *
+ * return The enabled interrupts. This is the logical OR of members of the
+ *         enumeration ::pwm_interrupt_enable_t
+ */
 uint32_t PWM_GetEnabledInterrupts(PWM_Type *base, pwm_submodule_t subModule)
 {
     uint32_t enabledInterrupts;
@@ -668,6 +771,15 @@ uint32_t PWM_GetEnabledInterrupts(PWM_Type *base, pwm_submodule_t subModule)
     return enabledInterrupts;
 }
 
+/*!
+ * brief Gets the PWM status flags
+ *
+ * param base      PWM peripheral base address
+ * param subModule PWM submodule to configure
+ *
+ * return The status flags. This is the logical OR of members of the
+ *         enumeration ::pwm_status_flags_t
+ */
 uint32_t PWM_GetStatusFlags(PWM_Type *base, pwm_submodule_t subModule)
 {
     uint32_t statusFlags;
@@ -678,12 +790,20 @@ uint32_t PWM_GetStatusFlags(PWM_Type *base, pwm_submodule_t subModule)
     return statusFlags;
 }
 
+/*!
+ * brief Clears the PWM status flags
+ *
+ * param base      PWM peripheral base address
+ * param subModule PWM submodule to configure
+ * param mask      The status flags to clear. This is a logical OR of members of the
+ *                  enumeration ::pwm_status_flags_t
+ */
 void PWM_ClearStatusFlags(PWM_Type *base, pwm_submodule_t subModule, uint32_t mask)
 {
     uint16_t reg;
 
     base->SM[subModule].STS = (mask & 0xFFFFU);
-    reg = base->FSTS;
+    reg                     = base->FSTS;
     /* Clear the fault flags and set only the ones we wish to clear as the fault flags are cleared
      * by writing a login one
      */
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_pwm.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_pwm.h
index 26619202d91..29e78a2be1a 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_pwm.h
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_pwm.h
@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
  * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 #ifndef _FSL_PWM_H_
 #define _FSL_PWM_H_
@@ -41,7 +15,6 @@
  * @{
  */
 
-
 /*******************************************************************************
  * Definitions
  ******************************************************************************/
@@ -209,18 +182,18 @@ typedef enum _pwm_interrupt_enable
     kPWM_CompareVal3InterruptEnable = (1U << 3),  /*!< PWM VAL3 compare interrupt */
     kPWM_CompareVal4InterruptEnable = (1U << 4),  /*!< PWM VAL4 compare interrupt */
     kPWM_CompareVal5InterruptEnable = (1U << 5),  /*!< PWM VAL5 compare interrupt */
-    kPWM_CaptureX0InterruptEnable = (1U << 6),    /*!< PWM capture X0 interrupt */
-    kPWM_CaptureX1InterruptEnable = (1U << 7),    /*!< PWM capture X1 interrupt */
-    kPWM_CaptureB0InterruptEnable = (1U << 8),    /*!< PWM capture B0 interrupt */
-    kPWM_CaptureB1InterruptEnable = (1U << 9),    /*!< PWM capture B1 interrupt */
-    kPWM_CaptureA0InterruptEnable = (1U << 10),   /*!< PWM capture A0 interrupt */
-    kPWM_CaptureA1InterruptEnable = (1U << 11),   /*!< PWM capture A1 interrupt */
-    kPWM_ReloadInterruptEnable = (1U << 12),      /*!< PWM reload interrupt */
+    kPWM_CaptureX0InterruptEnable   = (1U << 6),  /*!< PWM capture X0 interrupt */
+    kPWM_CaptureX1InterruptEnable   = (1U << 7),  /*!< PWM capture X1 interrupt */
+    kPWM_CaptureB0InterruptEnable   = (1U << 8),  /*!< PWM capture B0 interrupt */
+    kPWM_CaptureB1InterruptEnable   = (1U << 9),  /*!< PWM capture B1 interrupt */
+    kPWM_CaptureA0InterruptEnable   = (1U << 10), /*!< PWM capture A0 interrupt */
+    kPWM_CaptureA1InterruptEnable   = (1U << 11), /*!< PWM capture A1 interrupt */
+    kPWM_ReloadInterruptEnable      = (1U << 12), /*!< PWM reload interrupt */
     kPWM_ReloadErrorInterruptEnable = (1U << 13), /*!< PWM reload error interrupt */
-    kPWM_Fault0InterruptEnable = (1U << 16),      /*!< PWM fault 0 interrupt */
-    kPWM_Fault1InterruptEnable = (1U << 17),      /*!< PWM fault 1 interrupt */
-    kPWM_Fault2InterruptEnable = (1U << 18),      /*!< PWM fault 2 interrupt */
-    kPWM_Fault3InterruptEnable = (1U << 19)       /*!< PWM fault 3 interrupt */
+    kPWM_Fault0InterruptEnable      = (1U << 16), /*!< PWM fault 0 interrupt */
+    kPWM_Fault1InterruptEnable      = (1U << 17), /*!< PWM fault 1 interrupt */
+    kPWM_Fault2InterruptEnable      = (1U << 18), /*!< PWM fault 2 interrupt */
+    kPWM_Fault3InterruptEnable      = (1U << 19)  /*!< PWM fault 3 interrupt */
 } pwm_interrupt_enable_t;
 
 /*! @brief List of PWM status flags */
@@ -232,19 +205,19 @@ typedef enum _pwm_status_flags
     kPWM_CompareVal3Flag = (1U << 3),  /*!< PWM VAL3 compare flag */
     kPWM_CompareVal4Flag = (1U << 4),  /*!< PWM VAL4 compare flag */
     kPWM_CompareVal5Flag = (1U << 5),  /*!< PWM VAL5 compare flag */
-    kPWM_CaptureX0Flag = (1U << 6),    /*!< PWM capture X0 flag */
-    kPWM_CaptureX1Flag = (1U << 7),    /*!< PWM capture X1 flag */
-    kPWM_CaptureB0Flag = (1U << 8),    /*!< PWM capture B0 flag */
-    kPWM_CaptureB1Flag = (1U << 9),    /*!< PWM capture B1 flag */
-    kPWM_CaptureA0Flag = (1U << 10),   /*!< PWM capture A0 flag */
-    kPWM_CaptureA1Flag = (1U << 11),   /*!< PWM capture A1 flag */
-    kPWM_ReloadFlag = (1U << 12),      /*!< PWM reload flag */
+    kPWM_CaptureX0Flag   = (1U << 6),  /*!< PWM capture X0 flag */
+    kPWM_CaptureX1Flag   = (1U << 7),  /*!< PWM capture X1 flag */
+    kPWM_CaptureB0Flag   = (1U << 8),  /*!< PWM capture B0 flag */
+    kPWM_CaptureB1Flag   = (1U << 9),  /*!< PWM capture B1 flag */
+    kPWM_CaptureA0Flag   = (1U << 10), /*!< PWM capture A0 flag */
+    kPWM_CaptureA1Flag   = (1U << 11), /*!< PWM capture A1 flag */
+    kPWM_ReloadFlag      = (1U << 12), /*!< PWM reload flag */
     kPWM_ReloadErrorFlag = (1U << 13), /*!< PWM reload error flag */
-    kPWM_RegUpdatedFlag = (1U << 14),  /*!< PWM registers updated flag */
-    kPWM_Fault0Flag = (1U << 16),      /*!< PWM fault 0 flag */
-    kPWM_Fault1Flag = (1U << 17),      /*!< PWM fault 1 flag */
-    kPWM_Fault2Flag = (1U << 18),      /*!< PWM fault 2 flag */
-    kPWM_Fault3Flag = (1U << 19)       /*!< PWM fault 3 flag */
+    kPWM_RegUpdatedFlag  = (1U << 14), /*!< PWM registers updated flag */
+    kPWM_Fault0Flag      = (1U << 16), /*!< PWM fault 0 flag */
+    kPWM_Fault1Flag      = (1U << 17), /*!< PWM fault 1 flag */
+    kPWM_Fault2Flag      = (1U << 18), /*!< PWM fault 2 flag */
+    kPWM_Fault3Flag      = (1U << 19)  /*!< PWM fault 3 flag */
 } pwm_status_flags_t;
 
 /*! @brief PWM operation mode */
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_pxp.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_pxp.c
index 4bc424c9679..33675b43328 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_pxp.c
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_pxp.c
@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
- * Copyright (c) 2017, NXP Semiconductors, Inc.
+ * Copyright  2017 NXP
  * All rights reserved.
  *
- * 
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include "fsl_pxp.h"
@@ -148,9 +122,9 @@ static uint32_t PXP_ConvertFloat(float floatValue, uint8_t intBits, uint8_t frac
     u32_f32_t u32_f32;
     uint32_t ret;
 
-    u32_f32.f32 = floatValue;
+    u32_f32.f32        = floatValue;
     uint32_t floatBits = u32_f32.u32;
-    int32_t expValue = (int32_t)((floatBits & 0x7F800000U) >> 23U) - 127;
+    int32_t expValue   = (int32_t)((floatBits & 0x7F800000U) >> 23U) - 127;
 
     ret = (floatBits & 0x007FFFFFU) | 0x00800000U;
     expValue += fracBits;
@@ -187,7 +161,7 @@ static void PXP_GetScalerParam(uint16_t inputDimension, uint16_t outputDimension
     if (scaleFact >= (16U << 12U))
     {
         /* Desired fact is two large, use the largest support value. */
-        *dec = 3U;
+        *dec   = 3U;
         *scale = 0x2000U;
     }
     else
@@ -218,6 +192,14 @@ static void PXP_GetScalerParam(uint16_t inputDimension, uint16_t outputDimension
     }
 }
 
+/*!
+ * brief Initialize the PXP.
+ *
+ * This function enables the PXP peripheral clock, and resets the PXP registers
+ * to default status.
+ *
+ * param base PXP peripheral base address.
+ */
 void PXP_Init(PXP_Type *base)
 {
     uint32_t ctrl = 0U;
@@ -248,6 +230,13 @@ void PXP_Init(PXP_Type *base)
     base->CTRL = ctrl;
 }
 
+/*!
+ * brief De-initialize the PXP.
+ *
+ * This function disables the PXP peripheral clock.
+ *
+ * param base PXP peripheral base address.
+ */
 void PXP_Deinit(PXP_Type *base)
 {
 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
@@ -256,22 +245,41 @@ void PXP_Deinit(PXP_Type *base)
 #endif
 }
 
+/*!
+ * brief Reset the PXP.
+ *
+ * This function resets the PXP peripheral registers to default status.
+ *
+ * param base PXP peripheral base address.
+ */
 void PXP_Reset(PXP_Type *base)
 {
     base->CTRL_SET = PXP_CTRL_SFTRST_MASK;
     base->CTRL_CLR = (PXP_CTRL_SFTRST_MASK | PXP_CTRL_CLKGATE_MASK);
 }
 
+/*!
+ * brief Set the alpha surface input buffer configuration.
+ *
+ * param base PXP peripheral base address.
+ * param config Pointer to the configuration.
+ */
 void PXP_SetAlphaSurfaceBufferConfig(PXP_Type *base, const pxp_as_buffer_config_t *config)
 {
     assert(config);
 
     base->AS_CTRL = (base->AS_CTRL & ~PXP_AS_CTRL_FORMAT_MASK) | PXP_AS_CTRL_FORMAT(config->pixelFormat);
 
-    base->AS_BUF = config->bufferAddr;
+    base->AS_BUF   = config->bufferAddr;
     base->AS_PITCH = config->pitchBytes;
 }
 
+/*!
+ * brief Set the alpha surface blending configuration.
+ *
+ * param base PXP peripheral base address.
+ * param config Pointer to the configuration structure.
+ */
 void PXP_SetAlphaSurfaceBlendConfig(PXP_Type *base, const pxp_as_blend_config_t *config)
 {
     assert(config);
@@ -291,6 +299,15 @@ void PXP_SetAlphaSurfaceBlendConfig(PXP_Type *base, const pxp_as_blend_config_t
     base->AS_CTRL = reg;
 }
 
+/*!
+ * brief Set the alpha surface position in output buffer.
+ *
+ * param base PXP peripheral base address.
+ * param upperLeftX X of the upper left corner.
+ * param upperLeftY Y of the upper left corner.
+ * param lowerRightX X of the lower right corner.
+ * param lowerRightY Y of the lower right corner.
+ */
 void PXP_SetAlphaSurfacePosition(
     PXP_Type *base, uint16_t upperLeftX, uint16_t upperLeftY, uint16_t lowerRightX, uint16_t lowerRightY)
 {
@@ -298,12 +315,32 @@ void PXP_SetAlphaSurfacePosition(
     base->OUT_AS_LRC = PXP_OUT_AS_LRC_Y(lowerRightY) | PXP_OUT_AS_LRC_X(lowerRightX);
 }
 
+/*!
+ * brief Set the alpha surface overlay color key.
+ *
+ * If a pixel in the current overlay image with a color that falls in the range
+ * from the p colorKeyLow to p colorKeyHigh range, it will use the process surface
+ * pixel value for that location. If no PS image is present or if the PS image also
+ * matches its colorkey range, the PS background color is used.
+ *
+ * param base PXP peripheral base address.
+ * param colorKeyLow Color key low range.
+ * param colorKeyHigh Color key high range.
+ *
+ * note Colorkey operations are higher priority than alpha or ROP operations
+ */
 void PXP_SetAlphaSurfaceOverlayColorKey(PXP_Type *base, uint32_t colorKeyLow, uint32_t colorKeyHigh)
 {
-    base->AS_CLRKEYLOW = colorKeyLow;
+    base->AS_CLRKEYLOW  = colorKeyLow;
     base->AS_CLRKEYHIGH = colorKeyHigh;
 }
 
+/*!
+ * brief Set the process surface input buffer configuration.
+ *
+ * param base PXP peripheral base address.
+ * param config Pointer to the configuration.
+ */
 void PXP_SetProcessSurfaceBufferConfig(PXP_Type *base, const pxp_ps_buffer_config_t *config)
 {
     assert(config);
@@ -311,12 +348,23 @@ void PXP_SetProcessSurfaceBufferConfig(PXP_Type *base, const pxp_ps_buffer_confi
     base->PS_CTRL = ((base->PS_CTRL & ~(PXP_PS_CTRL_FORMAT_MASK | PXP_PS_CTRL_WB_SWAP_MASK)) |
                      PXP_PS_CTRL_FORMAT(config->pixelFormat) | PXP_PS_CTRL_WB_SWAP(config->swapByte));
 
-    base->PS_BUF = config->bufferAddr;
-    base->PS_UBUF = config->bufferAddrU;
-    base->PS_VBUF = config->bufferAddrV;
+    base->PS_BUF   = config->bufferAddr;
+    base->PS_UBUF  = config->bufferAddrU;
+    base->PS_VBUF  = config->bufferAddrV;
     base->PS_PITCH = config->pitchBytes;
 }
 
+/*!
+ * brief Set the process surface scaler configuration.
+ *
+ * The valid down scale fact is 1/(2^12) ~ 16.
+ *
+ * param base PXP peripheral base address.
+ * param inputWidth Input image width.
+ * param inputHeight Input image height.
+ * param outputWidth Output image width.
+ * param outputHeight Output image height.
+ */
 void PXP_SetProcessSurfaceScaler(
     PXP_Type *base, uint16_t inputWidth, uint16_t inputHeight, uint16_t outputWidth, uint16_t outputHeight)
 {
@@ -332,6 +380,15 @@ void PXP_SetProcessSurfaceScaler(
     base->PS_SCALE = PXP_PS_SCALE_XSCALE(scaleX) | PXP_PS_SCALE_YSCALE(scaleY);
 }
 
+/*!
+ * brief Set the process surface position in output buffer.
+ *
+ * param base PXP peripheral base address.
+ * param upperLeftX X of the upper left corner.
+ * param upperLeftY Y of the upper left corner.
+ * param lowerRightX X of the lower right corner.
+ * param lowerRightY Y of the lower right corner.
+ */
 void PXP_SetProcessSurfacePosition(
     PXP_Type *base, uint16_t upperLeftX, uint16_t upperLeftY, uint16_t lowerRightX, uint16_t lowerRightY)
 {
@@ -339,12 +396,28 @@ void PXP_SetProcessSurfacePosition(
     base->OUT_PS_LRC = PXP_OUT_PS_LRC_Y(lowerRightY) | PXP_OUT_PS_LRC_X(lowerRightX);
 }
 
+/*!
+ * brief Set the process surface color key.
+ *
+ * If the PS image matches colorkey range, the PS background color is output. Set
+ * p colorKeyLow to 0xFFFFFFFF and p colorKeyHigh to 0 will disable the colorkeying.
+ *
+ * param base PXP peripheral base address.
+ * param colorKeyLow Color key low range.
+ * param colorKeyHigh Color key high range.
+ */
 void PXP_SetProcessSurfaceColorKey(PXP_Type *base, uint32_t colorKeyLow, uint32_t colorKeyHigh)
 {
-    base->PS_CLRKEYLOW = colorKeyLow;
+    base->PS_CLRKEYLOW  = colorKeyLow;
     base->PS_CLRKEYHIGH = colorKeyHigh;
 }
 
+/*!
+ * brief Set the PXP outpt buffer configuration.
+ *
+ * param base PXP peripheral base address.
+ * param config Pointer to the configuration.
+ */
 void PXP_SetOutputBufferConfig(PXP_Type *base, const pxp_output_buffer_config_t *config)
 {
     assert(config);
@@ -352,11 +425,11 @@ void PXP_SetOutputBufferConfig(PXP_Type *base, const pxp_output_buffer_config_t
     base->OUT_CTRL = (base->OUT_CTRL & ~(PXP_OUT_CTRL_FORMAT_MASK | PXP_OUT_CTRL_INTERLACED_OUTPUT_MASK)) |
                      PXP_OUT_CTRL_FORMAT(config->pixelFormat) | PXP_OUT_CTRL_INTERLACED_OUTPUT(config->interlacedMode);
 
-    base->OUT_BUF = config->buffer0Addr;
+    base->OUT_BUF  = config->buffer0Addr;
     base->OUT_BUF2 = config->buffer1Addr;
 
     base->OUT_PITCH = config->pitchBytes;
-    base->OUT_LRC = PXP_OUT_LRC_Y(config->height - 1U) | PXP_OUT_LRC_X(config->width - 1U);
+    base->OUT_LRC   = PXP_OUT_LRC_Y(config->height - 1U) | PXP_OUT_LRC_X(config->width - 1U);
 
 /*
  * The dither store size must be set to the same with the output buffer size,
@@ -369,6 +442,16 @@ void PXP_SetOutputBufferConfig(PXP_Type *base, const pxp_output_buffer_config_t
 }
 
 #if !(defined(FSL_FEATURE_PXP_HAS_NO_CSC2) && FSL_FEATURE_PXP_HAS_NO_CSC2)
+/*!
+ * brief Set the CSC2 configuration.
+ *
+ * The CSC2 module receives pixels in any color space and can convert the pixels
+ * into any of RGB, YUV, or YCbCr color spaces. The output pixels are passed
+ * onto the LUT and rotation engine for further processing
+ *
+ * param base PXP peripheral base address.
+ * param config Pointer to the configuration.
+ */
 void PXP_SetCsc2Config(PXP_Type *base, const pxp_csc2_config_t *config)
 {
     assert(config);
@@ -399,6 +482,16 @@ void PXP_SetCsc2Config(PXP_Type *base, const pxp_csc2_config_t *config)
 }
 #endif
 
+/*!
+ * brief Set the CSC1 mode.
+ *
+ * The CSC1 module receives scaled YUV/YCbCr444 pixels from the scale engine and
+ * converts the pixels to the RGB888 color space. It could only be used by process
+ * surface.
+ *
+ * param base PXP peripheral base address.
+ * param mode The conversion mode.
+ */
 void PXP_SetCsc1Mode(PXP_Type *base, pxp_csc1_mode_t mode)
 {
     /*
@@ -411,9 +504,8 @@ void PXP_SetCsc1Mode(PXP_Type *base, pxp_csc1_mode_t mode)
 
     if (kPXP_Csc1YUV2RGB == mode)
     {
-        base->CSC1_COEF0 = (base->CSC1_COEF0 &
-                            ~(PXP_CSC1_COEF0_C0_MASK | PXP_CSC1_COEF0_Y_OFFSET_MASK | PXP_CSC1_COEF0_UV_OFFSET_MASK |
-                              PXP_CSC1_COEF0_YCBCR_MODE_MASK)) |
+        base->CSC1_COEF0 = (base->CSC1_COEF0 & ~(PXP_CSC1_COEF0_C0_MASK | PXP_CSC1_COEF0_Y_OFFSET_MASK |
+                                                 PXP_CSC1_COEF0_UV_OFFSET_MASK | PXP_CSC1_COEF0_YCBCR_MODE_MASK)) |
                            PXP_CSC1_COEF0_C0(0x100U)         /* 1.00. */
                            | PXP_CSC1_COEF0_Y_OFFSET(0x0U)   /* 0. */
                            | PXP_CSC1_COEF0_UV_OFFSET(0x0U); /* 0. */
@@ -437,6 +529,19 @@ void PXP_SetCsc1Mode(PXP_Type *base, pxp_csc1_mode_t mode)
 }
 
 #if !(defined(FSL_FEATURE_PXP_HAS_NO_LUT) && FSL_FEATURE_PXP_HAS_NO_LUT)
+/*!
+ * brief Set the LUT configuration.
+ *
+ * The lookup table (LUT) is used to modify pixels in a manner that is not linear
+ * and that cannot be achieved by the color space conversion modules. To setup
+ * the LUT, the complete workflow is:
+ * 1. Use ref PXP_SetLutConfig to set the configuration, such as the lookup mode.
+ * 2. Use ref PXP_LoadLutTable to load the lookup table to PXP.
+ * 3. Use ref PXP_EnableLut to enable the function.
+ *
+ * param base PXP peripheral base address.
+ * param config Pointer to the configuration.
+ */
 void PXP_SetLutConfig(PXP_Type *base, const pxp_lut_config_t *config)
 {
     base->LUT_CTRL = (base->LUT_CTRL & ~(PXP_LUT_CTRL_OUT_MODE_MASK | PXP_LUT_CTRL_LOOKUP_MODE_MASK)) |
@@ -449,6 +554,28 @@ void PXP_SetLutConfig(PXP_Type *base, const pxp_lut_config_t *config)
     }
 }
 
+/*!
+ * brief Set the look up table to PXP.
+ *
+ * If lookup mode is DIRECT mode, this function loads p bytesNum of values
+ * from the address p memAddr into PXP LUT address p lutStartAddr. So this
+ * function allows only update part of the PXP LUT.
+ *
+ * If lookup mode is CACHE mode, this function sets the new address to p memAddr
+ * and invalid the PXP LUT cache.
+ *
+ * param base PXP peripheral base address.
+ * param lookupMode Which lookup mode is used. Note that this parameter is only
+ * used to distinguish DIRECT mode and CACHE mode, it does not change the register
+ * value PXP_LUT_CTRL[LOOKUP_MODE]. To change that value, use function ref PXP_SetLutConfig.
+ * param bytesNum How many bytes to set. This value must be divisable by 8.
+ * param memAddr Address of look up table to set.
+ * param lutStartAddr The LUT value will be loaded to LUT from index lutAddr. It should
+ * be 8 bytes aligned.
+ *
+ * retval kStatus_Success Load successfully.
+ * retval kStatus_InvalidArgument Failed because of invalid argument.
+ */
 status_t PXP_LoadLutTable(
     PXP_Type *base, pxp_lut_lookup_mode_t lookupMode, uint32_t bytesNum, uint32_t memAddr, uint16_t lutStartAddr)
 {
@@ -471,7 +598,7 @@ status_t PXP_LoadLutTable(
         }
 
         base->LUT_EXTMEM = memAddr;
-        base->LUT_ADDR = PXP_LUT_ADDR_ADDR(lutStartAddr) | PXP_LUT_ADDR_NUM_BYTES(bytesNum);
+        base->LUT_ADDR   = PXP_LUT_ADDR_ADDR(lutStartAddr) | PXP_LUT_ADDR_NUM_BYTES(bytesNum);
 
         base->STAT_CLR = PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_MASK;
 
@@ -491,6 +618,15 @@ status_t PXP_LoadLutTable(
 #endif /* FSL_FEATURE_PXP_HAS_NO_LUT */
 
 #if (defined(FSL_FEATURE_PXP_HAS_DITHER) && FSL_FEATURE_PXP_HAS_DITHER)
+/*!
+ * brief Write data to the PXP internal memory.
+ *
+ * param base PXP peripheral base address.
+ * param ram Which internal memory to write.
+ * param bytesNum How many bytes to write.
+ * param data Pointer to the data to write.
+ * param memStartAddr The start address in the internal memory to write the data.
+ */
 void PXP_SetInternalRamData(PXP_Type *base, pxp_ram_t ram, uint32_t bytesNum, uint8_t *data, uint16_t memStartAddr)
 {
     assert((memStartAddr + bytesNum) <= PXP_INTERNAL_RAM_LUT_BYTE);
@@ -507,6 +643,16 @@ void PXP_SetInternalRamData(PXP_Type *base, pxp_ram_t ram, uint32_t bytesNum, ui
     base->INIT_MEM_CTRL = 0U;
 }
 
+/*!
+ * brief Set the dither final LUT data.
+ *
+ * The dither final LUT is only applicble to dither engine 0. It takes the bits[7:4]
+ * of the output pixel and looks up and 8 bit value from the 16 value LUT to generate
+ * the final output pixel to the next process module.
+ *
+ * param base PXP peripheral base address.
+ * param data Pointer to the LUT data to set.
+ */
 void PXP_SetDitherFinalLutData(PXP_Type *base, const pxp_dither_final_lut_data_t *data)
 {
     base->DITHER_FINAL_LUT_DATA0 = data->data_3_0;
@@ -515,6 +661,19 @@ void PXP_SetDitherFinalLutData(PXP_Type *base, const pxp_dither_final_lut_data_t
     base->DITHER_FINAL_LUT_DATA3 = data->data_15_12;
 }
 
+/*!
+ * brief Enable or disable dither engine in the PXP process path.
+ *
+ * After the initialize function ref PXP_Init, the dither engine is disabled and not
+ * use in the PXP processing path. This function enables the dither engine and
+ * routes the dither engine output to the output buffer. When the dither engine
+ * is enabled using this function, ref PXP_SetDitherConfig must be called to
+ * configure dither engine correctly, otherwise there is not output to the output
+ * buffer.
+ *
+ * param base PXP peripheral base address.
+ * param enable Pass in true to enable, false to disable.
+ */
 void PXP_EnableDither(PXP_Type *base, bool enable)
 {
     if (enable)
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_pxp.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_pxp.h
index 98f9d22cb83..0209fa73776 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_pxp.h
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_pxp.h
@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
- * Copyright (c) 2017, NXP Semiconductors, Inc.
+ * Copyright  2017 NXP
  * All rights reserved.
  *
- * 
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #ifndef _FSL_PXP_H_
@@ -74,7 +48,7 @@
 
 /*! @name Driver version */
 /*@{*/
-#define FSL_PXP_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */
+#define FSL_PXP_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) /*!< Version 2.0.1 */
 /*@}*/
 
 /* This macto indicates whether the rotate sub module is shared by process surface and output buffer. */
@@ -123,10 +97,10 @@ enum _pxp_flags
 /*! @brief PXP output flip mode. */
 typedef enum _pxp_flip_mode
 {
-    kPXP_FlipDisable = 0U,       /*!< Flip disable. */
+    kPXP_FlipDisable    = 0U,    /*!< Flip disable. */
     kPXP_FlipHorizontal = 0x01U, /*!< Horizontal flip. */
-    kPXP_FlipVertical = 0x02U,   /*!< Vertical flip. */
-    kPXP_FlipBoth = 0x03U,       /*!< Flip both directions. */
+    kPXP_FlipVertical   = 0x02U, /*!< Vertical flip. */
+    kPXP_FlipBoth       = 0x03U, /*!< Flip both directions. */
 } pxp_flip_mode_t;
 
 /*! @brief PXP rotate mode. */
@@ -157,23 +131,23 @@ typedef enum _pxp_interlaced_output_mode
 /*! @brief PXP output buffer format. */
 typedef enum _pxp_output_pixel_format
 {
-    kPXP_OutputPixelFormatARGB8888 = 0x0,   /*!< 32-bit pixels with alpha. */
-    kPXP_OutputPixelFormatRGB888 = 0x4,     /*!< 32-bit pixels without alpha (unpacked 24-bit format) */
-    kPXP_OutputPixelFormatRGB888P = 0x5,    /*!< 24-bit pixels without alpha (packed 24-bit format) */
-    kPXP_OutputPixelFormatARGB1555 = 0x8,   /*!< 16-bit pixels with alpha. */
-    kPXP_OutputPixelFormatARGB4444 = 0x9,   /*!< 16-bit pixels with alpha. */
-    kPXP_OutputPixelFormatRGB555 = 0xC,     /*!< 16-bit pixels without alpha. */
-    kPXP_OutputPixelFormatRGB444 = 0xD,     /*!< 16-bit pixels without alpha. */
-    kPXP_OutputPixelFormatRGB565 = 0xE,     /*!< 16-bit pixels without alpha. */
-    kPXP_OutputPixelFormatYUV1P444 = 0x10,  /*!< 32-bit pixels (1-plane XYUV unpacked). */
+    kPXP_OutputPixelFormatARGB8888  = 0x0,  /*!< 32-bit pixels with alpha. */
+    kPXP_OutputPixelFormatRGB888    = 0x4,  /*!< 32-bit pixels without alpha (unpacked 24-bit format) */
+    kPXP_OutputPixelFormatRGB888P   = 0x5,  /*!< 24-bit pixels without alpha (packed 24-bit format) */
+    kPXP_OutputPixelFormatARGB1555  = 0x8,  /*!< 16-bit pixels with alpha. */
+    kPXP_OutputPixelFormatARGB4444  = 0x9,  /*!< 16-bit pixels with alpha. */
+    kPXP_OutputPixelFormatRGB555    = 0xC,  /*!< 16-bit pixels without alpha. */
+    kPXP_OutputPixelFormatRGB444    = 0xD,  /*!< 16-bit pixels without alpha. */
+    kPXP_OutputPixelFormatRGB565    = 0xE,  /*!< 16-bit pixels without alpha. */
+    kPXP_OutputPixelFormatYUV1P444  = 0x10, /*!< 32-bit pixels (1-plane XYUV unpacked). */
     kPXP_OutputPixelFormatUYVY1P422 = 0x12, /*!< 16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes) */
     kPXP_OutputPixelFormatVYUY1P422 = 0x13, /*!< 16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes) */
-    kPXP_OutputPixelFormatY8 = 0x14,        /*!< 8-bit monochrome pixels (1-plane Y luma output) */
-    kPXP_OutputPixelFormatY4 = 0x15,        /*!< 4-bit monochrome pixels (1-plane Y luma, 4 bit truncation) */
-    kPXP_OutputPixelFormatYUV2P422 = 0x18,  /*!< 16-bit pixels (2-plane UV interleaved bytes) */
-    kPXP_OutputPixelFormatYUV2P420 = 0x19,  /*!< 16-bit pixels (2-plane UV) */
-    kPXP_OutputPixelFormatYVU2P422 = 0x1A,  /*!< 16-bit pixels (2-plane VU interleaved bytes) */
-    kPXP_OutputPixelFormatYVU2P420 = 0x1B,  /*!< 16-bit pixels (2-plane VU) */
+    kPXP_OutputPixelFormatY8        = 0x14, /*!< 8-bit monochrome pixels (1-plane Y luma output) */
+    kPXP_OutputPixelFormatY4        = 0x15, /*!< 4-bit monochrome pixels (1-plane Y luma, 4 bit truncation) */
+    kPXP_OutputPixelFormatYUV2P422  = 0x18, /*!< 16-bit pixels (2-plane UV interleaved bytes) */
+    kPXP_OutputPixelFormatYUV2P420  = 0x19, /*!< 16-bit pixels (2-plane UV) */
+    kPXP_OutputPixelFormatYVU2P422  = 0x1A, /*!< 16-bit pixels (2-plane VU interleaved bytes) */
+    kPXP_OutputPixelFormatYVU2P420  = 0x1B, /*!< 16-bit pixels (2-plane VU) */
 } pxp_output_pixel_format_t;
 
 /*! @brief PXP output buffer configuration. */
@@ -192,21 +166,21 @@ typedef struct _pxp_output_buffer_config
 /*! @brief PXP process surface buffer pixel format. */
 typedef enum _pxp_ps_pixel_format
 {
-    kPXP_PsPixelFormatRGB888 = 0x4,     /*!< 32-bit pixels without alpha (unpacked 24-bit format) */
-    kPXP_PsPixelFormatRGB555 = 0xC,     /*!< 16-bit pixels without alpha. */
-    kPXP_PsPixelFormatRGB444 = 0xD,     /*!< 16-bit pixels without alpha. */
-    kPXP_PsPixelFormatRGB565 = 0xE,     /*!< 16-bit pixels without alpha. */
-    kPXP_PsPixelFormatYUV1P444 = 0x10,  /*!< 32-bit pixels (1-plane XYUV unpacked). */
+    kPXP_PsPixelFormatRGB888    = 0x4,  /*!< 32-bit pixels without alpha (unpacked 24-bit format) */
+    kPXP_PsPixelFormatRGB555    = 0xC,  /*!< 16-bit pixels without alpha. */
+    kPXP_PsPixelFormatRGB444    = 0xD,  /*!< 16-bit pixels without alpha. */
+    kPXP_PsPixelFormatRGB565    = 0xE,  /*!< 16-bit pixels without alpha. */
+    kPXP_PsPixelFormatYUV1P444  = 0x10, /*!< 32-bit pixels (1-plane XYUV unpacked). */
     kPXP_PsPixelFormatUYVY1P422 = 0x12, /*!< 16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes) */
     kPXP_PsPixelFormatVYUY1P422 = 0x13, /*!< 16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes) */
-    kPXP_PsPixelFormatY8 = 0x14,        /*!< 8-bit monochrome pixels (1-plane Y luma output) */
-    kPXP_PsPixelFormatY4 = 0x15,        /*!< 4-bit monochrome pixels (1-plane Y luma, 4 bit truncation) */
-    kPXP_PsPixelFormatYUV2P422 = 0x18,  /*!< 16-bit pixels (2-plane UV interleaved bytes) */
-    kPXP_PsPixelFormatYUV2P420 = 0x19,  /*!< 16-bit pixels (2-plane UV) */
-    kPXP_PsPixelFormatYVU2P422 = 0x1A,  /*!< 16-bit pixels (2-plane VU interleaved bytes) */
-    kPXP_PsPixelFormatYVU2P420 = 0x1B,  /*!< 16-bit pixels (2-plane VU) */
-    kPXP_PsPixelFormatYVU422 = 0x1E,    /*!< 16-bit pixels (3-plane) */
-    kPXP_PsPixelFormatYVU420 = 0x1F,    /*!< 16-bit pixels (3-plane) */
+    kPXP_PsPixelFormatY8        = 0x14, /*!< 8-bit monochrome pixels (1-plane Y luma output) */
+    kPXP_PsPixelFormatY4        = 0x15, /*!< 4-bit monochrome pixels (1-plane Y luma, 4 bit truncation) */
+    kPXP_PsPixelFormatYUV2P422  = 0x18, /*!< 16-bit pixels (2-plane UV interleaved bytes) */
+    kPXP_PsPixelFormatYUV2P420  = 0x19, /*!< 16-bit pixels (2-plane UV) */
+    kPXP_PsPixelFormatYVU2P422  = 0x1A, /*!< 16-bit pixels (2-plane VU interleaved bytes) */
+    kPXP_PsPixelFormatYVU2P420  = 0x1B, /*!< 16-bit pixels (2-plane VU) */
+    kPXP_PsPixelFormatYVU422    = 0x1E, /*!< 16-bit pixels (3-plane) */
+    kPXP_PsPixelFormatYVU420    = 0x1F, /*!< 16-bit pixels (3-plane) */
 } pxp_ps_pixel_format_t;
 
 /*! @brief PXP process surface buffer configuration. */
@@ -224,12 +198,12 @@ typedef struct _pxp_ps_buffer_config
 typedef enum _pxp_as_pixel_format
 {
     kPXP_AsPixelFormatARGB8888 = 0x0, /*!< 32-bit pixels with alpha. */
-    kPXP_AsPixelFormatRGB888 = 0x4,   /*!< 32-bit pixels without alpha (unpacked 24-bit format) */
+    kPXP_AsPixelFormatRGB888   = 0x4, /*!< 32-bit pixels without alpha (unpacked 24-bit format) */
     kPXP_AsPixelFormatARGB1555 = 0x8, /*!< 16-bit pixels with alpha. */
     kPXP_AsPixelFormatARGB4444 = 0x9, /*!< 16-bit pixels with alpha. */
-    kPXP_AsPixelFormatRGB555 = 0xC,   /*!< 16-bit pixels without alpha. */
-    kPXP_AsPixelFormatRGB444 = 0xD,   /*!< 16-bit pixels without alpha. */
-    kPXP_AsPixelFormatRGB565 = 0xE,   /*!< 16-bit pixels without alpha. */
+    kPXP_AsPixelFormatRGB555   = 0xC, /*!< 16-bit pixels without alpha. */
+    kPXP_AsPixelFormatRGB444   = 0xD, /*!< 16-bit pixels without alpha. */
+    kPXP_AsPixelFormatRGB565   = 0xE, /*!< 16-bit pixels without alpha. */
 } pxp_as_pixel_format_t;
 
 /*! @brief PXP alphs surface buffer configuration. */
@@ -265,18 +239,18 @@ typedef enum _pxp_alpha_mode
  */
 typedef enum _pxp_rop_mode
 {
-    kPXP_RopMaskAs = 0x0,     /*!< AS AND PS. */
-    kPXP_RopMaskNotAs = 0x1,  /*!< nAS AND PS. */
-    kPXP_RopMaskAsNot = 0x2,  /*!< AS AND nPS. */
-    kPXP_RopMergeAs = 0x3,    /*!< AS OR PS. */
+    kPXP_RopMaskAs     = 0x0, /*!< AS AND PS. */
+    kPXP_RopMaskNotAs  = 0x1, /*!< nAS AND PS. */
+    kPXP_RopMaskAsNot  = 0x2, /*!< AS AND nPS. */
+    kPXP_RopMergeAs    = 0x3, /*!< AS OR PS. */
     kPXP_RopMergeNotAs = 0x4, /*!< nAS OR PS. */
     kPXP_RopMergeAsNot = 0x5, /*!< AS OR nPS. */
-    kPXP_RopNotCopyAs = 0x6,  /*!< nAS. */
-    kPXP_RopNot = 0x7,        /*!< nPS. */
-    kPXP_RopNotMaskAs = 0x8,  /*!< AS NAND PS. */
+    kPXP_RopNotCopyAs  = 0x6, /*!< nAS. */
+    kPXP_RopNot        = 0x7, /*!< nPS. */
+    kPXP_RopNotMaskAs  = 0x8, /*!< AS NAND PS. */
     kPXP_RopNotMergeAs = 0x9, /*!< AS NOR PS. */
-    kPXP_RopXorAs = 0xA,      /*!< AS XOR PS. */
-    kPXP_RopNotXorAs = 0xB    /*!< AS XNOR PS. */
+    kPXP_RopXorAs      = 0xA, /*!< AS XOR PS. */
+    kPXP_RopNotXorAs   = 0xB  /*!< AS XNOR PS. */
 } pxp_rop_mode_t;
 
 /*!
@@ -397,8 +371,8 @@ typedef enum _pxp_ram
 enum _pxp_dither_mode
 {
     kPXP_DitherPassThrough = 0U, /*!< Pass through, no dither. */
-    kPXP_DitherOrdered = 3U,     /*!< Ordered dither. */
-    kPXP_DitherQuantOnly = 4U,   /*!< No dithering, only quantization. */
+    kPXP_DitherOrdered     = 3U, /*!< Ordered dither. */
+    kPXP_DitherQuantOnly   = 4U, /*!< No dithering, only quantization. */
 };
 
 /*! @brief PXP dither LUT mode. */
@@ -910,15 +884,35 @@ static inline void PXP_SetRotateConfig(PXP_Type *base,
         (base->CTRL & ~(PXP_CTRL_ROTATE_MASK | PXP_CTRL_ROT_POS_MASK | PXP_CTRL_VFLIP_MASK | PXP_CTRL_HFLIP_MASK)) |
         PXP_CTRL_ROTATE(degree) | PXP_CTRL_ROT_POS(position) | ((uint32_t)flipMode << PXP_CTRL_HFLIP_SHIFT);
 #else
-    uint32_t ctrl = base->CTRL;
+    uint32_t ctrl       = base->CTRL;
 
     if (kPXP_RotateOutputBuffer == position)
     {
+        if ((degree != kPXP_Rotate0) || (flipMode != kPXP_FlipDisable))
+        {
+            base->DATA_PATH_CTRL0 =
+                (base->DATA_PATH_CTRL0 & (~PXP_DATA_PATH_CTRL0_MUX12_SEL_MASK)) | PXP_DATA_PATH_CTRL0_MUX12_SEL(0);
+        }
+        else
+        {
+            base->DATA_PATH_CTRL0 =
+                (base->DATA_PATH_CTRL0 & (~PXP_DATA_PATH_CTRL0_MUX12_SEL_MASK)) | PXP_DATA_PATH_CTRL0_MUX12_SEL(1);
+        }
         ctrl &= ~(PXP_CTRL_HFLIP0_MASK | PXP_CTRL_VFLIP0_MASK | PXP_CTRL_ROTATE0_MASK);
         ctrl |= (PXP_CTRL_ROTATE0(degree) | ((uint32_t)flipMode << PXP_CTRL_HFLIP0_SHIFT));
     }
     else
     {
+        if ((degree != kPXP_Rotate0) || (flipMode != kPXP_FlipDisable))
+        {
+            base->DATA_PATH_CTRL0 =
+                (base->DATA_PATH_CTRL0 & (~PXP_DATA_PATH_CTRL0_MUX3_SEL_MASK)) | PXP_DATA_PATH_CTRL0_MUX3_SEL(1);
+        }
+        else
+        {
+            base->DATA_PATH_CTRL0 =
+                (base->DATA_PATH_CTRL0 & (~PXP_DATA_PATH_CTRL0_MUX3_SEL_MASK)) | PXP_DATA_PATH_CTRL0_MUX3_SEL(0);
+        }
         ctrl &= ~(PXP_CTRL_HFLIP1_MASK | PXP_CTRL_VFLIP1_MASK | PXP_CTRL_ROTATE1_MASK);
         ctrl |= (PXP_CTRL_ROTATE1(degree) | ((uint32_t)flipMode << PXP_CTRL_HFLIP1_SHIFT));
     }
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_qtmr.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_qtmr.c
index 8373fa03594..88294a994fa 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_qtmr.c
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_qtmr.c
@@ -1,34 +1,8 @@
 /*
- * The Clear BSD License
  * Copyright 2017 NXP
  * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
  *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include "fsl_qtmr.h"
@@ -38,7 +12,6 @@
 #define FSL_COMPONENT_ID "platform.drivers.qtmr"
 #endif
 
-
 /*******************************************************************************
  * Prototypes
  ******************************************************************************/
@@ -83,6 +56,15 @@ static uint32_t QTMR_GetInstance(TMR_Type *base)
     return instance;
 }
 
+/*!
+ * brief Ungates the Quad Timer clock and configures the peripheral for basic operation.
+ *
+ * note This API should be called at the beginning of the application using the Quad Timer driver.
+ *
+ * param base     Quad Timer peripheral base address
+ * param channel  Quad Timer channel number
+ * param config   Pointer to user's Quad Timer config structure
+ */
 void QTMR_Init(TMR_Type *base, qtmr_channel_selection_t channel, const qtmr_config_t *config)
 {
     assert(config);
@@ -91,21 +73,29 @@ void QTMR_Init(TMR_Type *base, qtmr_channel_selection_t channel, const qtmr_conf
     /* Enable the module clock */
     CLOCK_EnableClock(s_qtmrClocks[QTMR_GetInstance(base)]);
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
-    
+
     /* Setup the counter sources */
     base->CHANNEL[channel].CTRL = (TMR_CTRL_PCS(config->primarySource) | TMR_CTRL_SCS(config->secondarySource));
 
     /* Setup the master mode operation */
-    base->CHANNEL[channel].SCTRL = (TMR_SCTRL_EEOF(config->enableExternalForce) | TMR_SCTRL_MSTR(config->enableMasterMode));
+    base->CHANNEL[channel].SCTRL =
+        (TMR_SCTRL_EEOF(config->enableExternalForce) | TMR_SCTRL_MSTR(config->enableMasterMode));
 
     /* Setup debug mode */
     base->CHANNEL[channel].CSCTRL = TMR_CSCTRL_DBG_EN(config->debugMode);
-    
-    base->CHANNEL[channel].FILT &= ~( TMR_FILT_FILT_CNT_MASK | TMR_FILT_FILT_PER_MASK);
+
+    base->CHANNEL[channel].FILT &= ~(TMR_FILT_FILT_CNT_MASK | TMR_FILT_FILT_PER_MASK);
     /* Setup input filter */
-    base->CHANNEL[channel].FILT = (TMR_FILT_FILT_CNT(config->faultFilterCount) | TMR_FILT_FILT_PER(config->faultFilterPeriod));
+    base->CHANNEL[channel].FILT =
+        (TMR_FILT_FILT_CNT(config->faultFilterCount) | TMR_FILT_FILT_PER(config->faultFilterPeriod));
 }
 
+/*!
+ * brief Stops the counter and gates the Quad Timer clock
+ *
+ * param base     Quad Timer peripheral base address
+ * param channel  Quad Timer channel number
+ */
 void QTMR_Deinit(TMR_Type *base, qtmr_channel_selection_t channel)
 {
     /* Stop the counter */
@@ -117,10 +107,28 @@ void QTMR_Deinit(TMR_Type *base, qtmr_channel_selection_t channel)
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }
 
+/*!
+ * brief  Fill in the Quad Timer config struct with the default settings
+ *
+ * The default values are:
+ * code
+ *    config->debugMode = kQTMR_RunNormalInDebug;
+ *    config->enableExternalForce = false;
+ *    config->enableMasterMode = false;
+ *    config->faultFilterCount = 0;
+ *    config->faultFilterPeriod = 0;
+ *    config->primarySource = kQTMR_ClockDivide_2;
+ *    config->secondarySource = kQTMR_Counter0InputPin;
+ * endcode
+ * param config Pointer to user's Quad Timer config structure.
+ */
 void QTMR_GetDefaultConfig(qtmr_config_t *config)
 {
     assert(config);
 
+    /* Initializes the configure structure to zero. */
+    memset(config, 0, sizeof(*config));
+
     /* Halt counter during debug mode */
     config->debugMode = kQTMR_RunNormalInDebug;
     /* Another counter cannot force state of OFLAG signal */
@@ -137,8 +145,29 @@ void QTMR_GetDefaultConfig(qtmr_config_t *config)
     config->secondarySource = kQTMR_Counter0InputPin;
 }
 
-status_t QTMR_SetupPwm(
-    TMR_Type *base, qtmr_channel_selection_t channel, uint32_t pwmFreqHz, uint8_t dutyCyclePercent, bool outputPolarity, uint32_t srcClock_Hz)
+/*!
+ * brief Sets up Quad timer module for PWM signal output.
+ *
+ * The function initializes the timer module according to the parameters passed in by the user. The
+ * function also sets up the value compare registers to match the PWM signal requirements.
+ *
+ * param base             Quad Timer peripheral base address
+ * param channel          Quad Timer channel number
+ * param pwmFreqHz        PWM signal frequency in Hz
+ * param dutyCyclePercent PWM pulse width, value should be between 0 to 100
+ *                         0=inactive signal(0% duty cycle)...
+ *                         100=active signal (100% duty cycle)
+ * param outputPolarity   true: invert polarity of the output signal, false: no inversion
+ * param srcClock_Hz      Main counter clock in Hz.
+ *
+ * return Returns an error if there was error setting up the signal.
+ */
+status_t QTMR_SetupPwm(TMR_Type *base,
+                       qtmr_channel_selection_t channel,
+                       uint32_t pwmFreqHz,
+                       uint8_t dutyCyclePercent,
+                       bool outputPolarity,
+                       uint32_t srcClock_Hz)
 {
     uint32_t periodCount, highCount, lowCount, reg;
 
@@ -153,8 +182,8 @@ status_t QTMR_SetupPwm(
 
     /* Counter values to generate a PWM signal */
     periodCount = (srcClock_Hz / pwmFreqHz);
-    highCount = (periodCount * dutyCyclePercent) / 100;
-    lowCount = periodCount - highCount;
+    highCount   = (periodCount * dutyCyclePercent) / 100;
+    lowCount    = periodCount - highCount;
 
     /* Setup the compare registers for PWM output */
     base->CHANNEL[channel].COMP1 = lowCount;
@@ -190,10 +219,22 @@ status_t QTMR_SetupPwm(
      */
     reg |= (TMR_CTRL_LENGTH_MASK | TMR_CTRL_OUTMODE(kQTMR_ToggleOnAltCompareReg));
     base->CHANNEL[channel].CTRL = reg;
-   
+
     return kStatus_Success;
 }
 
+/*!
+ * brief Allows the user to count the source clock cycles until a capture event arrives.
+ *
+ * The count is stored in the capture register.
+ *
+ * param base            Quad Timer peripheral base address
+ * param channel         Quad Timer channel number
+ * param capturePin      Pin through which we receive the input signal to trigger the capture
+ * param inputPolarity   true: invert polarity of the input signal, false: no inversion
+ * param reloadOnCapture true: reload the counter when an input capture occurs, false: no reload
+ * param captureMode     Specifies which edge of the input signal  triggers a capture
+ */
 void QTMR_SetupInputCapture(TMR_Type *base,
                             qtmr_channel_selection_t channel,
                             qtmr_input_source_t capturePin,
@@ -227,6 +268,14 @@ void QTMR_SetupInputCapture(TMR_Type *base,
     }
 }
 
+/*!
+ * brief Enables the selected Quad Timer interrupts
+ *
+ * param base      Quad Timer peripheral base address
+ * param channel   Quad Timer channel number
+ * param mask      The interrupts to enable. This is a logical OR of members of the
+ *                  enumeration ::qtmr_interrupt_enable_t
+ */
 void QTMR_EnableInterrupts(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t mask)
 {
     uint16_t reg;
@@ -265,6 +314,14 @@ void QTMR_EnableInterrupts(TMR_Type *base, qtmr_channel_selection_t channel, uin
     base->CHANNEL[channel].CSCTRL = reg;
 }
 
+/*!
+ * brief Disables the selected Quad Timer interrupts
+ *
+ * param base     Quad Timer peripheral base addres
+ * param channel  Quad Timer channel number
+ * param mask The interrupts to enable. This is a logical OR of members of the
+ *             enumeration ::qtmr_interrupt_enable_t
+ */
 void QTMR_DisableInterrupts(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t mask)
 {
     uint16_t reg;
@@ -301,6 +358,15 @@ void QTMR_DisableInterrupts(TMR_Type *base, qtmr_channel_selection_t channel, ui
     base->CHANNEL[channel].CSCTRL = reg;
 }
 
+/*!
+ * brief Gets the enabled Quad Timer interrupts
+ *
+ * param base    Quad Timer peripheral base address
+ * param channel Quad Timer channel number
+ *
+ * return The enabled interrupts. This is the logical OR of members of the
+ *         enumeration ::qtmr_interrupt_enable_t
+ */
 uint32_t QTMR_GetEnabledInterrupts(TMR_Type *base, qtmr_channel_selection_t channel)
 {
     uint32_t enabledInterrupts = 0;
@@ -338,6 +404,15 @@ uint32_t QTMR_GetEnabledInterrupts(TMR_Type *base, qtmr_channel_selection_t chan
     return enabledInterrupts;
 }
 
+/*!
+ * brief Gets the Quad Timer status flags
+ *
+ * param base     Quad Timer peripheral base address
+ * param channel  Quad Timer channel number
+ *
+ * return The status flags. This is the logical OR of members of the
+ *         enumeration ::qtmr_status_flags_t
+ */
 uint32_t QTMR_GetStatus(TMR_Type *base, qtmr_channel_selection_t channel)
 {
     uint32_t statusFlags = 0;
@@ -375,6 +450,14 @@ uint32_t QTMR_GetStatus(TMR_Type *base, qtmr_channel_selection_t channel)
     return statusFlags;
 }
 
+/*!
+ * brief Clears the Quad Timer status flags.
+ *
+ * param base     Quad Timer peripheral base address
+ * param channel  Quad Timer channel number
+ * param mask The status flags to clear. This is a logical OR of members of the
+ *             enumeration ::qtmr_status_flags_t
+ */
 void QTMR_ClearStatusFlags(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t mask)
 {
     uint16_t reg;
@@ -411,6 +494,22 @@ void QTMR_ClearStatusFlags(TMR_Type *base, qtmr_channel_selection_t channel, uin
     base->CHANNEL[channel].CSCTRL = reg;
 }
 
+/*!
+ * brief Sets the timer period in ticks.
+ *
+ * Timers counts from initial value till it equals the count value set here. The counter
+ * will then reinitialize to the value specified in the Load register.
+ *
+ * note
+ * 1. This function will write the time period in ticks to COMP1 or COMP2 register
+ *    depending on the count direction
+ * 2. User can call the utility macros provided in fsl_common.h to convert to ticks
+ * 3. This function supports cases, providing only primary source clock without secondary source clock.
+ *
+ * param base     Quad Timer peripheral base address
+ * param channel  Quad Timer channel number
+ * param ticks Timer period in units of ticks
+ */
 void QTMR_SetTimerPeriod(TMR_Type *base, qtmr_channel_selection_t channel, uint16_t ticks)
 {
     /* Set the length bit to reinitialize the counters on a match */
@@ -428,6 +527,14 @@ void QTMR_SetTimerPeriod(TMR_Type *base, qtmr_channel_selection_t channel, uint1
     }
 }
 
+/*!
+ * brief Enable the Quad Timer DMA.
+ *
+ * param base     Quad Timer peripheral base address
+ * param channel  Quad Timer channel number
+ * param mask     The DMA to enable. This is a logical OR of members of the
+ *                  enumeration ::qtmr_dma_enable_t
+ */
 void QTMR_EnableDma(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t mask)
 {
     uint16_t reg;
@@ -436,7 +543,7 @@ void QTMR_EnableDma(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t m
     /* Input Edge Flag DMA Enable */
     if (mask & kQTMR_InputEdgeFlagDmaEnable)
     {
-       /* Restriction: Do not set both DMA[IEFDE] and SCTRL[IEFIE] */
+        /* Restriction: Do not set both DMA[IEFDE] and SCTRL[IEFIE] */
         base->CHANNEL[channel].SCTRL &= ~TMR_SCTRL_IEFIE_MASK;
         reg |= TMR_DMA_IEFDE_MASK;
     }
@@ -453,6 +560,14 @@ void QTMR_EnableDma(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t m
     base->CHANNEL[channel].DMA = reg;
 }
 
+/*!
+ * brief Disable the Quad Timer DMA.
+ *
+ * param base     Quad Timer peripheral base address
+ * param channel  Quad Timer channel number
+ * param mask     The DMA to enable. This is a logical OR of members of the
+ *                  enumeration ::qtmr_dma_enable_t
+ */
 void QTMR_DisableDma(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t mask)
 {
     uint16_t reg;
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_qtmr.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_qtmr.h
index ee23b4cca81..26d1204ebb2 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_qtmr.h
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_qtmr.h
@@ -1,34 +1,8 @@
 /*
- * The Clear BSD License
  * Copyright 2017 NXP
  * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
  *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 #ifndef _FSL_QTMR_H_
 #define _FSL_QTMR_H_
@@ -40,7 +14,6 @@
  * @{
  */
 
-
 /*******************************************************************************
  * Definitions
  ******************************************************************************/
@@ -135,21 +108,21 @@ typedef enum _qtmr_debug_action
 /*! @brief List of Quad Timer interrupts */
 typedef enum _qtmr_interrupt_enable
 {
-    kQTMR_CompareInterruptEnable = (1U << 0),  /*!< Compare interrupt.*/
+    kQTMR_CompareInterruptEnable  = (1U << 0), /*!< Compare interrupt.*/
     kQTMR_Compare1InterruptEnable = (1U << 1), /*!< Compare 1 interrupt.*/
     kQTMR_Compare2InterruptEnable = (1U << 2), /*!< Compare 2 interrupt.*/
     kQTMR_OverflowInterruptEnable = (1U << 3), /*!< Timer overflow interrupt.*/
-    kQTMR_EdgeInterruptEnable = (1U << 4)      /*!< Input edge interrupt.*/
+    kQTMR_EdgeInterruptEnable     = (1U << 4)  /*!< Input edge interrupt.*/
 } qtmr_interrupt_enable_t;
 
 /*! @brief List of Quad Timer flags */
 typedef enum _qtmr_status_flags
 {
-    kQTMR_CompareFlag = (1U << 0),  /*!< Compare flag */
+    kQTMR_CompareFlag  = (1U << 0), /*!< Compare flag */
     kQTMR_Compare1Flag = (1U << 1), /*!< Compare 1 flag */
     kQTMR_Compare2Flag = (1U << 2), /*!< Compare 2 flag */
     kQTMR_OverflowFlag = (1U << 3), /*!< Timer overflow flag */
-    kQTMR_EdgeFlag = (1U << 4)      /*!< Input edge flag */
+    kQTMR_EdgeFlag     = (1U << 4)  /*!< Input edge flag */
 } qtmr_status_flags_t;
 
 /*! @brief List of channel selection */
@@ -164,7 +137,7 @@ typedef enum _qtmr_channel_selection
 /*! @brief List of Quad Timer DMA enable */
 typedef enum _qtmr_dma_enable
 {
-    kQTMR_InputEdgeFlagDmaEnable = (1U << 0),      /*!< Input Edge Flag DMA Enable.*/
+    kQTMR_InputEdgeFlagDmaEnable      = (1U << 0), /*!< Input Edge Flag DMA Enable.*/
     kQTMR_ComparatorPreload1DmaEnable = (1U << 1), /*!< Comparator Preload Register 1 DMA Enable.*/
     kQTMR_ComparatorPreload2DmaEnable = (1U << 2), /*!< Comparator Preload Register 2 DMA Enable.*/
 } qtmr_dma_enable_t;
@@ -259,8 +232,12 @@ void QTMR_GetDefaultConfig(qtmr_config_t *config);
  *
  * @return Returns an error if there was error setting up the signal.
  */
-status_t QTMR_SetupPwm(
-    TMR_Type *base, qtmr_channel_selection_t channel, uint32_t pwmFreqHz, uint8_t dutyCyclePercent, bool outputPolarity, uint32_t srcClock_Hz);
+status_t QTMR_SetupPwm(TMR_Type *base,
+                       qtmr_channel_selection_t channel,
+                       uint32_t pwmFreqHz,
+                       uint8_t dutyCyclePercent,
+                       bool outputPolarity,
+                       uint32_t srcClock_Hz);
 
 /*!
  * @brief Allows the user to count the source clock cycles until a capture event arrives.
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_rtwdog.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_rtwdog.c
index 54f2717a6fe..9a32bd8064e 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_rtwdog.c
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_rtwdog.c
@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
+ * Copyright 2016-2018 NXP
  * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
  *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include "fsl_rtwdog.h"
@@ -39,11 +13,24 @@
 #define FSL_COMPONENT_ID "platform.drivers.rtwdog"
 #endif
 
-
 /*******************************************************************************
  * Code
  ******************************************************************************/
 
+/*!
+ * brief Clears the RTWDOG flag.
+ *
+ * This function clears the RTWDOG status flag.
+ *
+ * Example to clear an interrupt flag:
+ * code
+ *   RTWDOG_ClearStatusFlags(wdog_base,kRTWDOG_InterruptFlag);
+ * endcode
+ * param base        RTWDOG peripheral base address.
+ * param mask        The status flags to clear.
+ *                    The parameter can be any combination of the following values:
+ *                    arg kRTWDOG_InterruptFlag
+ */
 void RTWDOG_ClearStatusFlags(RTWDOG_Type *base, uint32_t mask)
 {
     if (mask & kRTWDOG_InterruptFlag)
@@ -52,47 +39,103 @@ void RTWDOG_ClearStatusFlags(RTWDOG_Type *base, uint32_t mask)
     }
 }
 
+/*!
+ * brief Initializes the RTWDOG configuration structure.
+ *
+ * This function initializes the RTWDOG configuration structure to default values. The default
+ * values are:
+ * code
+ *   rtwdogConfig->enableRtwdog = true;
+ *   rtwdogConfig->clockSource = kRTWDOG_ClockSource1;
+ *   rtwdogConfig->prescaler = kRTWDOG_ClockPrescalerDivide1;
+ *   rtwdogConfig->workMode.enableWait = true;
+ *   rtwdogConfig->workMode.enableStop = false;
+ *   rtwdogConfig->workMode.enableDebug = false;
+ *   rtwdogConfig->testMode = kRTWDOG_TestModeDisabled;
+ *   rtwdogConfig->enableUpdate = true;
+ *   rtwdogConfig->enableInterrupt = false;
+ *   rtwdogConfig->enableWindowMode = false;
+ *   rtwdogConfig->windowValue = 0U;
+ *   rtwdogConfig->timeoutValue = 0xFFFFU;
+ * endcode
+ *
+ * param config Pointer to the RTWDOG configuration structure.
+ * see rtwdog_config_t
+ */
 void RTWDOG_GetDefaultConfig(rtwdog_config_t *config)
 {
     assert(config);
 
-    config->enableRtwdog = true;
-    config->clockSource = kRTWDOG_ClockSource1;
-    config->prescaler = kRTWDOG_ClockPrescalerDivide1;
-    config->workMode.enableWait = true;
-    config->workMode.enableStop = false;
+    /* Initializes the configure structure to zero. */
+    memset(config, 0, sizeof(*config));
+
+    config->enableRtwdog         = true;
+    config->clockSource          = kRTWDOG_ClockSource1;
+    config->prescaler            = kRTWDOG_ClockPrescalerDivide1;
+    config->workMode.enableWait  = true;
+    config->workMode.enableStop  = false;
     config->workMode.enableDebug = false;
-    config->testMode = kRTWDOG_TestModeDisabled;
-    config->enableUpdate = true;
-    config->enableInterrupt = false;
-    config->enableWindowMode = false;
-    config->windowValue = 0U;
-    config->timeoutValue = 0xFFFFU;
+    config->testMode             = kRTWDOG_TestModeDisabled;
+    config->enableUpdate         = true;
+    config->enableInterrupt      = false;
+    config->enableWindowMode     = false;
+    config->windowValue          = 0U;
+    config->timeoutValue         = 0xFFFFU;
 }
 
+/*!
+ * brief Initializes the RTWDOG module.
+ *
+ * This function initializes the RTWDOG.
+ * To reconfigure the RTWDOG without forcing a reset first, enableUpdate must be set to true
+ * in the configuration.
+ *
+ * Example:
+ * code
+ *   rtwdog_config_t config;
+ *   RTWDOG_GetDefaultConfig(&config);
+ *   config.timeoutValue = 0x7ffU;
+ *   config.enableUpdate = true;
+ *   RTWDOG_Init(wdog_base,&config);
+ * endcode
+ *
+ * param base   RTWDOG peripheral base address.
+ * param config The configuration of the RTWDOG.
+ */
 void RTWDOG_Init(RTWDOG_Type *base, const rtwdog_config_t *config)
 {
     assert(config);
 
-    uint32_t value = 0U;
+    uint32_t value        = 0U;
     uint32_t primaskValue = 0U;
- 
-    value = RTWDOG_CS_EN(config->enableRtwdog) | RTWDOG_CS_CLK(config->clockSource) | RTWDOG_CS_INT(config->enableInterrupt) |
-            RTWDOG_CS_WIN(config->enableWindowMode) | RTWDOG_CS_UPDATE(config->enableUpdate) |
-            RTWDOG_CS_DBG(config->workMode.enableDebug) | RTWDOG_CS_STOP(config->workMode.enableStop) |
-            RTWDOG_CS_WAIT(config->workMode.enableWait) | RTWDOG_CS_PRES(config->prescaler) | RTWDOG_CS_CMD32EN(true) |
-            RTWDOG_CS_TST(config->testMode);
+
+    value = RTWDOG_CS_EN(config->enableRtwdog) | RTWDOG_CS_CLK(config->clockSource) |
+            RTWDOG_CS_INT(config->enableInterrupt) | RTWDOG_CS_WIN(config->enableWindowMode) |
+            RTWDOG_CS_UPDATE(config->enableUpdate) | RTWDOG_CS_DBG(config->workMode.enableDebug) |
+            RTWDOG_CS_STOP(config->workMode.enableStop) | RTWDOG_CS_WAIT(config->workMode.enableWait) |
+            RTWDOG_CS_PRES(config->prescaler) | RTWDOG_CS_CMD32EN(true) | RTWDOG_CS_TST(config->testMode);
 
     /* Disable the global interrupts. Otherwise, an interrupt could effectively invalidate the unlock sequence
      * and the WCT may expire. After the configuration finishes, re-enable the global interrupts. */
     primaskValue = DisableGlobalIRQ();
     RTWDOG_Unlock(base);
-    base->WIN = config->windowValue;
+    base->WIN   = config->windowValue;
     base->TOVAL = config->timeoutValue;
-    base->CS = value;
+    base->CS    = value;
+    while ((base->CS & RTWDOG_CS_RCS_MASK) == 0)
+    {
+    }
     EnableGlobalIRQ(primaskValue);
 }
 
+/*!
+ * brief De-initializes the RTWDOG module.
+ *
+ * This function shuts down the RTWDOG.
+ * Ensure that the WDOG_CS.UPDATE is 1, which means that the register update is enabled.
+ *
+ * param base   RTWDOG peripheral base address.
+ */
 void RTWDOG_Deinit(RTWDOG_Type *base)
 {
     uint32_t primaskValue = 0U;
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_rtwdog.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_rtwdog.h
index 76ba5b3b03f..b1a708fc80c 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_rtwdog.h
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_rtwdog.h
@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
+ * Copyright 2016-2018 NXP
  * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 #ifndef _FSL_RTWDOG_H_
 #define _FSL_RTWDOG_H_
@@ -41,25 +15,24 @@
  * @{
  */
 
-
 /*******************************************************************************
  * Definitions
  *******************************************************************************/
 /*! @name Unlock sequence */
 /*@{*/
-#define WDOG_FIRST_WORD_OF_UNLOCK (RTWDOG_UPDATE_KEY & 0xFFFFU)  /*!< First word of unlock sequence */
-#define WDOG_SECOND_WORD_OF_UNLOCK ((RTWDOG_UPDATE_KEY >> 16U)& 0xFFFFU) /*!< Second word of unlock sequence */
+#define WDOG_FIRST_WORD_OF_UNLOCK (RTWDOG_UPDATE_KEY & 0xFFFFU)           /*!< First word of unlock sequence */
+#define WDOG_SECOND_WORD_OF_UNLOCK ((RTWDOG_UPDATE_KEY >> 16U) & 0xFFFFU) /*!< Second word of unlock sequence */
 /*@}*/
 
 /*! @name Refresh sequence */
 /*@{*/
-#define WDOG_FIRST_WORD_OF_REFRESH (RTWDOG_REFRESH_KEY & 0xFFFFU)  /*!< First word of refresh sequence */
-#define WDOG_SECOND_WORD_OF_REFRESH ((RTWDOG_REFRESH_KEY >> 16U)& 0xFFFFU) /*!< Second word of refresh sequence */
+#define WDOG_FIRST_WORD_OF_REFRESH (RTWDOG_REFRESH_KEY & 0xFFFFU)           /*!< First word of refresh sequence */
+#define WDOG_SECOND_WORD_OF_REFRESH ((RTWDOG_REFRESH_KEY >> 16U) & 0xFFFFU) /*!< Second word of refresh sequence */
 /*@}*/
 /*! @name Driver version */
 /*@{*/
-/*! @brief RTWDOG driver version 2.0.0. */
-#define FSL_RTWDOG_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*! @brief RTWDOG driver version 2.1.0. */
+#define FSL_RTWDOG_DRIVER_VERSION (MAKE_VERSION(2, 1, 0))
 /*@}*/
 
 /*! @brief Describes RTWDOG clock source. */
@@ -74,7 +47,7 @@ typedef enum _rtwdog_clock_source
 /*! @brief Describes the selection of the clock prescaler. */
 typedef enum _rtwdog_clock_prescaler
 {
-    kRTWDOG_ClockPrescalerDivide1 = 0x0U,   /*!< Divided by 1 */
+    kRTWDOG_ClockPrescalerDivide1   = 0x0U, /*!< Divided by 1 */
     kRTWDOG_ClockPrescalerDivide256 = 0x1U, /*!< Divided by 256 */
 } rtwdog_clock_prescaler_t;
 
@@ -90,9 +63,9 @@ typedef struct _rtwdog_work_mode
 typedef enum _rtwdog_test_mode
 {
     kRTWDOG_TestModeDisabled = 0U, /*!< Test Mode disabled */
-    kRTWDOG_UserModeEnabled = 1U,  /*!< User Mode enabled */
-    kRTWDOG_LowByteTest = 2U,      /*!< Test Mode enabled, only low byte is used */
-    kRTWDOG_HighByteTest = 3U,     /*!< Test Mode enabled, only high byte is used */
+    kRTWDOG_UserModeEnabled  = 1U, /*!< User Mode enabled */
+    kRTWDOG_LowByteTest      = 2U, /*!< Test Mode enabled, only low byte is used */
+    kRTWDOG_HighByteTest     = 3U, /*!< Test Mode enabled, only high byte is used */
 } rtwdog_test_mode_t;
 
 /*! @brief Describes RTWDOG configuration structure. */
@@ -127,7 +100,7 @@ enum _rtwdog_interrupt_enable_t
  */
 enum _rtwdog_status_flags_t
 {
-    kRTWDOG_RunningFlag = RTWDOG_CS_EN_MASK,    /*!< Running flag, set when RTWDOG is enabled */
+    kRTWDOG_RunningFlag   = RTWDOG_CS_EN_MASK,  /*!< Running flag, set when RTWDOG is enabled */
     kRTWDOG_InterruptFlag = RTWDOG_CS_FLG_MASK, /*!< Interrupt flag, set when interrupt occurs */
 };
 
@@ -188,7 +161,7 @@ void RTWDOG_GetDefaultConfig(rtwdog_config_t *config);
  * @param base   RTWDOG peripheral base address.
  * @param config The configuration of the RTWDOG.
  */
-void RTWDOG_Init(RTWDOG_Type *base, const rtwdog_config_t *config);
+AT_QUICKACCESS_SECTION_CODE(void RTWDOG_Init(RTWDOG_Type *base, const rtwdog_config_t *config));
 
 /*!
  * @brief De-initializes the RTWDOG module.
@@ -289,6 +262,43 @@ static inline uint32_t RTWDOG_GetStatusFlags(RTWDOG_Type *base)
     return (base->CS & (RTWDOG_CS_EN_MASK | RTWDOG_CS_FLG_MASK));
 }
 
+/*!
+ * @brief Enables/disables the window mode.
+ *
+ * @param base   RTWDOG peripheral base address.
+ * @param enable Enables(true) or disables(false) the feature.
+ */
+static inline void RTWDOG_EnableWindowMode(RTWDOG_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->CS |= RTWDOG_CS_WIN_MASK;
+    }
+    else
+    {
+        base->CS &= ~RTWDOG_CS_WIN_MASK;
+    }
+}
+
+/*!
+ * @brief Converts raw count value to millisecond.
+ *
+ * Note that if the clock frequency is too high the timeout period can be less than 1 ms.
+ * In this case this api will return 0 value.
+ *
+ * @param base          RTWDOG peripheral base address.
+ * @param count         Raw count value.
+ # @param clockFreqInHz The frequency of the clock source RTWDOG uses.
+ */
+static inline uint32_t RTWDOG_CountToMesec(RTWDOG_Type *base, uint32_t count, uint32_t clockFreqInHz)
+{
+    if ((base->CS & RTWDOG_CS_PRES_MASK) >> RTWDOG_CS_PRES_SHIFT)
+    {
+        clockFreqInHz /= 256;
+    }
+    return count * 1000U / clockFreqInHz;
+}
+
 /*!
  * @brief Clears the RTWDOG flag.
  *
@@ -357,6 +367,9 @@ static inline void RTWDOG_Unlock(RTWDOG_Type *base)
         base->CNT = WDOG_FIRST_WORD_OF_UNLOCK;
         base->CNT = WDOG_SECOND_WORD_OF_UNLOCK;
     }
+    while ((base->CS & RTWDOG_CS_ULK_MASK) == 0)
+    {
+    }
 }
 
 /*!
@@ -369,6 +382,8 @@ static inline void RTWDOG_Unlock(RTWDOG_Type *base)
  */
 static inline void RTWDOG_Refresh(RTWDOG_Type *base)
 {
+    uint32_t primaskValue = 0U;
+    primaskValue          = DisableGlobalIRQ();
     if ((base->CS) & RTWDOG_CS_CMD32EN_MASK)
     {
         base->CNT = RTWDOG_REFRESH_KEY;
@@ -378,6 +393,7 @@ static inline void RTWDOG_Refresh(RTWDOG_Type *base)
         base->CNT = WDOG_FIRST_WORD_OF_REFRESH;
         base->CNT = WDOG_SECOND_WORD_OF_REFRESH;
     }
+    EnableGlobalIRQ(primaskValue);
 }
 
 /*!
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_sai.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_sai.c
index db5d26a2634..9bf4c59ba2b 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_sai.c
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_sai.c
@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2016, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
  * All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include "fsl_sai.h"
@@ -46,7 +20,7 @@ enum _sai_transfer_state
 {
     kSAI_Busy = 0x0U, /*!< SAI is busy */
     kSAI_Idle,        /*!< Transfer is done. */
-    kSAI_Error        /*!< Transfer error occured. */
+    kSAI_Error        /*!< Transfer error occurred. */
 };
 
 /*! @brief Typedef for sai tx interrupt handler. */
@@ -58,7 +32,8 @@ typedef void (*sai_rx_isr_t)(I2S_Type *base, sai_handle_t *saiHandle);
 /*******************************************************************************
  * Prototypes
  ******************************************************************************/
-#if defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER)
+#if ((defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER)) || \
+     (defined(FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV) && (FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV)))
 
 /*!
  * @brief Set the master clock divider.
@@ -84,23 +59,52 @@ static uint32_t SAI_GetInstance(I2S_Type *base);
  * @brief sends a piece of data in non-blocking way.
  *
  * @param base SAI base pointer
- * @param channel Data channel used.
+ * @param channel start channel number.
+ * @param channelMask enabled channels mask.
+ * @param endChannel end channel numbers.
  * @param bitWidth How many bits in a audio word, usually 8/16/24/32 bits.
  * @param buffer Pointer to the data to be written.
  * @param size Bytes to be written.
  */
-static void SAI_WriteNonBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size);
+static void SAI_WriteNonBlocking(I2S_Type *base,
+                                 uint32_t channel,
+                                 uint32_t channelMask,
+                                 uint32_t endChannel,
+                                 uint32_t bitWidth,
+                                 uint8_t *buffer,
+                                 uint32_t size);
 
 /*!
  * @brief Receive a piece of data in non-blocking way.
  *
  * @param base SAI base pointer
- * @param channel Data channel used.
+ * @param channel start channel number.
+ * @param channelMask enabled channels mask.
+ * @param endChannel end channel numbers.
  * @param bitWidth How many bits in a audio word, usually 8/16/24/32 bits.
  * @param buffer Pointer to the data to be read.
  * @param size Bytes to be read.
  */
-static void SAI_ReadNonBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size);
+static void SAI_ReadNonBlocking(I2S_Type *base,
+                                uint32_t channel,
+                                uint32_t channelMask,
+                                uint32_t endChannel,
+                                uint32_t bitWidth,
+                                uint8_t *buffer,
+                                uint32_t size);
+
+/*!
+ * @brief Get classic I2S mode configurations.
+ *
+ * @param config transceiver configurations
+ * @param bitWidth audio data bitWidth.
+ * @param mode audio data channel
+ * @param saiChannelMask channel mask value to enable
+ */
+static void SAI_GetCommonConfig(sai_transceiver_t *config,
+                                sai_word_width_t bitWidth,
+                                sai_mono_stereo_t mode,
+                                uint32_t saiChannelMask);
 /*******************************************************************************
  * Variables
  ******************************************************************************/
@@ -123,24 +127,39 @@ static sai_rx_isr_t s_saiRxIsr;
 /*******************************************************************************
  * Code
  ******************************************************************************/
-#if defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER)
+#if ((defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER)) || \
+     (defined(FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV) && (FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV)))
 static void SAI_SetMasterClockDivider(I2S_Type *base, uint32_t mclk_Hz, uint32_t mclkSrcClock_Hz)
 {
-    uint32_t freq = mclkSrcClock_Hz;
+    assert(mclk_Hz <= mclkSrcClock_Hz);
+
+    uint32_t sourceFreq = mclkSrcClock_Hz / 100U; /*In order to prevent overflow */
+    uint32_t targetFreq = mclk_Hz / 100U;         /*In order to prevent overflow */
+
+#if FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV
+    uint32_t postDivider = sourceFreq / targetFreq;
+
+    /* if source equal to target, then disable divider */
+    if (postDivider == 1U)
+    {
+        base->MCR &= ~I2S_MCR_DIVEN_MASK;
+    }
+    else
+    {
+        base->MCR = (base->MCR & (~I2S_MCR_DIV_MASK)) | I2S_MCR_DIV(postDivider / 2U - 1U) | I2S_MCR_DIVEN_MASK;
+    }
+#endif
+#if FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER
     uint16_t fract, divide;
-    uint32_t remaind = 0;
+    uint32_t remaind           = 0;
     uint32_t current_remainder = 0xFFFFFFFFU;
-    uint16_t current_fract = 0;
-    uint16_t current_divide = 0;
-    uint32_t mul_freq = 0;
-    uint32_t max_fract = 256;
-
-    /*In order to prevent overflow */
-    freq /= 100;
-    mclk_Hz /= 100;
+    uint16_t current_fract     = 0;
+    uint16_t current_divide    = 0;
+    uint32_t mul_freq          = 0;
+    uint32_t max_fract         = 256;
 
     /* Compute the max fract number */
-    max_fract = mclk_Hz * 4096 / freq + 1;
+    max_fract = targetFreq * 4096 / sourceFreq + 1;
     if (max_fract > 256)
     {
         max_fract = 256;
@@ -149,30 +168,30 @@ static void SAI_SetMasterClockDivider(I2S_Type *base, uint32_t mclk_Hz, uint32_t
     /* Looking for the closet frequency */
     for (fract = 1; fract < max_fract; fract++)
     {
-        mul_freq = freq * fract;
-        remaind = mul_freq % mclk_Hz;
-        divide = mul_freq / mclk_Hz;
+        mul_freq = sourceFreq * fract;
+        remaind  = mul_freq % targetFreq;
+        divide   = mul_freq / targetFreq;
 
         /* Find the exactly frequency */
         if (remaind == 0)
         {
-            current_fract = fract;
-            current_divide = mul_freq / mclk_Hz;
+            current_fract  = fract;
+            current_divide = mul_freq / targetFreq;
             break;
         }
 
         /* Closer to next one, set the closest to next data */
         if (remaind > mclk_Hz / 2)
         {
-            remaind = mclk_Hz - remaind;
+            remaind = targetFreq - remaind;
             divide += 1;
         }
 
         /* Update the closest div and fract */
         if (remaind < current_remainder)
         {
-            current_fract = fract;
-            current_divide = divide;
+            current_fract     = fract;
+            current_divide    = divide;
             current_remainder = remaind;
         }
     }
@@ -184,6 +203,7 @@ static void SAI_SetMasterClockDivider(I2S_Type *base, uint32_t mclk_Hz, uint32_t
     while (base->MCR & I2S_MCR_DUF_MASK)
     {
     }
+#endif
 }
 #endif /* FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER */
 
@@ -205,45 +225,138 @@ static uint32_t SAI_GetInstance(I2S_Type *base)
     return instance;
 }
 
-static void SAI_WriteNonBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size)
+static void SAI_WriteNonBlocking(I2S_Type *base,
+                                 uint32_t channel,
+                                 uint32_t channelMask,
+                                 uint32_t endChannel,
+                                 uint32_t bitWidth,
+                                 uint8_t *buffer,
+                                 uint32_t size)
 {
     uint32_t i = 0;
-    uint8_t j = 0;
+    uint8_t j = 0, m = 0;
     uint8_t bytesPerWord = bitWidth / 8U;
-    uint32_t data = 0;
-    uint32_t temp = 0;
+    uint32_t data        = 0;
+    uint32_t temp        = 0;
 
     for (i = 0; i < size / bytesPerWord; i++)
     {
-        for (j = 0; j < bytesPerWord; j++)
+        for (j = channel; j <= endChannel; j++)
         {
-            temp = (uint32_t)(*buffer);
-            data |= (temp << (8U * j));
-            buffer++;
+            if ((1U << j) & channelMask)
+            {
+                for (m = 0; m < bytesPerWord; m++)
+                {
+                    temp = (uint32_t)(*buffer);
+                    data |= (temp << (8U * m));
+                    buffer++;
+                }
+                base->TDR[j] = data;
+                data         = 0;
+            }
         }
-        base->TDR[channel] = data;
-        data = 0;
     }
 }
 
-static void SAI_ReadNonBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size)
+static void SAI_ReadNonBlocking(I2S_Type *base,
+                                uint32_t channel,
+                                uint32_t channelMask,
+                                uint32_t endChannel,
+                                uint32_t bitWidth,
+                                uint8_t *buffer,
+                                uint32_t size)
 {
     uint32_t i = 0;
-    uint8_t j = 0;
+    uint8_t j = 0, m = 0;
     uint8_t bytesPerWord = bitWidth / 8U;
-    uint32_t data = 0;
+    uint32_t data        = 0;
 
     for (i = 0; i < size / bytesPerWord; i++)
     {
-        data = base->RDR[channel];
-        for (j = 0; j < bytesPerWord; j++)
+        for (j = channel; j <= endChannel; j++)
         {
-            *buffer = (data >> (8U * j)) & 0xFF;
-            buffer++;
+            if ((1U << j) & channelMask)
+            {
+                data = base->RDR[j];
+                for (m = 0; m < bytesPerWord; m++)
+                {
+                    *buffer = (data >> (8U * m)) & 0xFF;
+                    buffer++;
+                }
+            }
         }
     }
 }
 
+static void SAI_GetCommonConfig(sai_transceiver_t *config,
+                                sai_word_width_t bitWidth,
+                                sai_mono_stereo_t mode,
+                                uint32_t saiChannelMask)
+{
+    assert(NULL != config);
+    assert(saiChannelMask != 0U);
+
+    memset(config, 0U, sizeof(sai_transceiver_t));
+
+    config->channelMask = saiChannelMask;
+    /* sync mode default configurations */
+    config->syncMode = kSAI_ModeAsync;
+
+    /* master mode default */
+    config->masterSlave = kSAI_Master;
+
+    /* bit default configurations */
+    config->bitClock.bclkSrcSwap    = false;
+    config->bitClock.bclkInputDelay = false;
+    config->bitClock.bclkPolarity   = kSAI_SampleOnRisingEdge;
+    config->bitClock.bclkSource     = kSAI_BclkSourceMclkDiv;
+
+    /* frame sync default configurations */
+    config->frameSync.frameSyncWidth = bitWidth;
+    config->frameSync.frameSyncEarly = true;
+#if defined(FSL_FEATURE_SAI_HAS_FRAME_SYNC_ON_DEMAND) && FSL_FEATURE_SAI_HAS_FRAME_SYNC_ON_DEMAND
+    config->frameSync.frameSyncGenerateOnDemand = false;
+#endif
+    config->frameSync.frameSyncPolarity = kSAI_PolarityActiveLow;
+
+    /* serial data default configurations */
+#if defined(FSL_FEATURE_SAI_HAS_CHANNEL_MODE) && FSL_FEATURE_SAI_HAS_CHANNEL_MODE
+    config->serialData.dataMode = kSAI_DataPinStateOutputZero;
+#endif
+    config->serialData.dataOrder           = kSAI_DataMSB;
+    config->serialData.dataWord0Length     = bitWidth;
+    config->serialData.dataWordLength      = bitWidth;
+    config->serialData.dataWordNLength     = bitWidth;
+    config->serialData.dataFirstBitShifted = bitWidth;
+    config->serialData.dataWordNum         = 2U;
+    config->serialData.dataMaskedWord      = mode;
+
+#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1)
+    /* fifo configurations */
+    config->fifo.fifoWatermark = FSL_FEATURE_SAI_FIFO_COUNT / 2U;
+#endif
+
+#if defined(FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR) && FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR
+    config->fifo.fifoContinueOneError = true;
+#endif
+}
+
+/*!
+ * brief Initializes the SAI Tx peripheral.
+ *
+ * deprecated Do not use this function.  It has been superceded by @ref SAI_Init
+ *
+ * Ungates the SAI clock, resets the module, and configures SAI Tx with a configuration structure.
+ * The configuration structure can be custom filled or set with default values by
+ * SAI_TxGetDefaultConfig().
+ *
+ * note  This API should be called at the beginning of the application to use
+ * the SAI driver. Otherwise, accessing the SAIM module can cause a hard fault
+ * because the clock is not enabled.
+ *
+ * param base SAI base pointer
+ * param config SAI configuration structure.
+ */
 void SAI_TxInit(I2S_Type *base, const sai_config_t *config)
 {
     uint32_t val = 0;
@@ -254,12 +367,14 @@ void SAI_TxInit(I2S_Type *base, const sai_config_t *config)
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
 #if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR)
+#if !(defined(FSL_FEATURE_SAI_HAS_NO_MCR_MICS) && (FSL_FEATURE_SAI_HAS_NO_MCR_MICS))
     /* Master clock source setting */
-    val = (base->MCR & ~I2S_MCR_MICS_MASK);
+    val       = (base->MCR & ~I2S_MCR_MICS_MASK);
     base->MCR = (val | I2S_MCR_MICS(config->mclkSource));
+#endif
 
     /* Configure Master clock output enable */
-    val = (base->MCR & ~I2S_MCR_MOE_MASK);
+    val       = (base->MCR & ~I2S_MCR_MOE_MASK);
     base->MCR = (val | I2S_MCR_MOE(config->mclkOutputEnable));
 #endif /* FSL_FEATURE_SAI_HAS_MCR */
 
@@ -309,7 +424,7 @@ void SAI_TxInit(I2S_Type *base, const sai_config_t *config)
         base->TCR4 |= I2S_TCR4_FSD_MASK;
 
         /* Bit clock source setting */
-        val = base->TCR2 & (~I2S_TCR2_MSEL_MASK);
+        val        = base->TCR2 & (~I2S_TCR2_MSEL_MASK);
         base->TCR2 = (val | I2S_TCR2_MSEL(config->bclkSource));
     }
     else
@@ -335,6 +450,7 @@ void SAI_TxInit(I2S_Type *base, const sai_config_t *config)
             val &= ~I2S_RCR2_SYNC_MASK;
             base->RCR2 = (val | I2S_RCR2_SYNC(0U));
             break;
+#if defined(FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI) && (FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI)
         case kSAI_ModeSyncWithOtherTx:
             val = base->TCR2;
             val &= ~I2S_TCR2_SYNC_MASK;
@@ -345,6 +461,7 @@ void SAI_TxInit(I2S_Type *base, const sai_config_t *config)
             val &= ~I2S_TCR2_SYNC_MASK;
             base->TCR2 = (val | I2S_TCR2_SYNC(3U));
             break;
+#endif /* FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI */
         default:
             break;
     }
@@ -354,6 +471,22 @@ void SAI_TxInit(I2S_Type *base, const sai_config_t *config)
 #endif /* FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR */
 }
 
+/*!
+ * brief Initializes the SAI Rx peripheral.
+ *
+ * deprecated Do not use this function.  It has been superceded by @ref SAI_Init
+ *
+ * Ungates the SAI clock, resets the module, and configures the SAI Rx with a configuration structure.
+ * The configuration structure can be custom filled or set with default values by
+ * SAI_RxGetDefaultConfig().
+ *
+ * note  This API should be called at the beginning of the application to use
+ * the SAI driver. Otherwise, accessing the SAI module can cause a hard fault
+ * because the clock is not enabled.
+ *
+ * param base SAI base pointer
+ * param config SAI configuration structure.
+ */
 void SAI_RxInit(I2S_Type *base, const sai_config_t *config)
 {
     uint32_t val = 0;
@@ -364,12 +497,14 @@ void SAI_RxInit(I2S_Type *base, const sai_config_t *config)
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
 #if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR)
+#if !(defined(FSL_FEATURE_SAI_HAS_NO_MCR_MICS) && (FSL_FEATURE_SAI_HAS_NO_MCR_MICS))
     /* Master clock source setting */
-    val = (base->MCR & ~I2S_MCR_MICS_MASK);
+    val       = (base->MCR & ~I2S_MCR_MICS_MASK);
     base->MCR = (val | I2S_MCR_MICS(config->mclkSource));
+#endif
 
     /* Configure Master clock output enable */
-    val = (base->MCR & ~I2S_MCR_MOE_MASK);
+    val       = (base->MCR & ~I2S_MCR_MOE_MASK);
     base->MCR = (val | I2S_MCR_MOE(config->mclkOutputEnable));
 #endif /* FSL_FEATURE_SAI_HAS_MCR */
 
@@ -419,7 +554,7 @@ void SAI_RxInit(I2S_Type *base, const sai_config_t *config)
         base->RCR4 |= I2S_RCR4_FSD_MASK;
 
         /* Bit clock source setting */
-        val = base->RCR2 & (~I2S_RCR2_MSEL_MASK);
+        val        = base->RCR2 & (~I2S_RCR2_MSEL_MASK);
         base->RCR2 = (val | I2S_RCR2_MSEL(config->bclkSource));
     }
     else
@@ -445,6 +580,7 @@ void SAI_RxInit(I2S_Type *base, const sai_config_t *config)
             val &= ~I2S_TCR2_SYNC_MASK;
             base->TCR2 = (val | I2S_TCR2_SYNC(0U));
             break;
+#if defined(FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI) && (FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI)
         case kSAI_ModeSyncWithOtherTx:
             val = base->RCR2;
             val &= ~I2S_RCR2_SYNC_MASK;
@@ -455,6 +591,7 @@ void SAI_RxInit(I2S_Type *base, const sai_config_t *config)
             val &= ~I2S_RCR2_SYNC_MASK;
             base->RCR2 = (val | I2S_RCR2_SYNC(3U));
             break;
+#endif /* FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI */
         default:
             break;
     }
@@ -464,6 +601,29 @@ void SAI_RxInit(I2S_Type *base, const sai_config_t *config)
 #endif /* FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR */
 }
 
+/*!
+ * brief Initializes the SAI peripheral.
+ *
+ * This API gates the SAI clock. The SAI module can't operate unless SAI_Init is called to enable the clock.
+ *
+ * param base SAI base pointer
+ */
+void SAI_Init(I2S_Type *base)
+{
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Enable the SAI clock */
+    CLOCK_EnableClock(s_saiClock[SAI_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}
+
+/*!
+ * brief De-initializes the SAI peripheral.
+ *
+ * This API gates the SAI clock. The SAI module can't operate unless SAI_TxInit
+ * or SAI_RxInit is called to enable the clock.
+ *
+ * param base SAI base pointer
+ */
 void SAI_Deinit(I2S_Type *base)
 {
     SAI_TxEnable(base, false);
@@ -473,30 +633,81 @@ void SAI_Deinit(I2S_Type *base)
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }
 
+/*!
+ * brief  Sets the SAI Tx configuration structure to default values.
+ *
+ * deprecated Do not use this function.  It has been superceded by @ref
+ * SAI_GetClassicI2SConfig/SAI_GetLeftJustifiedConfig/SAI_GetRightJustifiedConfig/SAI_GetDSPConfig/SAI_GetTDMConfig
+ *
+ * This API initializes the configuration structure for use in SAI_TxConfig().
+ * The initialized structure can remain unchanged in SAI_TxConfig(), or it can be modified
+ *  before calling SAI_TxConfig().
+ * This is an example.
+   code
+   sai_config_t config;
+   SAI_TxGetDefaultConfig(&config);
+   endcode
+ *
+ * param config pointer to master configuration structure
+ */
 void SAI_TxGetDefaultConfig(sai_config_t *config)
 {
-    config->bclkSource = kSAI_BclkSourceMclkDiv;
+    /* Initializes the configure structure to zero. */
+    memset(config, 0, sizeof(*config));
+
+    config->bclkSource  = kSAI_BclkSourceMclkDiv;
     config->masterSlave = kSAI_Master;
-    config->mclkSource = kSAI_MclkSourceSysclk;
-    config->protocol = kSAI_BusI2S;
-    config->syncMode = kSAI_ModeAsync;
 #if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR)
     config->mclkOutputEnable = true;
+#if !(defined(FSL_FEATURE_SAI_HAS_NO_MCR_MICS) && (FSL_FEATURE_SAI_HAS_NO_MCR_MICS))
+    config->mclkSource = kSAI_MclkSourceSysclk;
+#endif
 #endif /* FSL_FEATURE_SAI_HAS_MCR */
+    config->protocol = kSAI_BusI2S;
+    config->syncMode = kSAI_ModeAsync;
 }
 
+/*!
+ * brief  Sets the SAI Rx configuration structure to default values.
+ *
+ * deprecated Do not use this function.  It has been superceded by @ref
+ * SAI_GetClassicI2SConfig/SAI_GetLeftJustifiedConfig/SAI_GetRightJustifiedConfig/SAI_GetDSPConfig/SAI_GetTDMConfig
+ *
+ * This API initializes the configuration structure for use in SAI_RxConfig().
+ * The initialized structure can remain unchanged in SAI_RxConfig() or it can be modified
+ *  before calling SAI_RxConfig().
+ * This is an example.
+   code
+   sai_config_t config;
+   SAI_RxGetDefaultConfig(&config);
+   endcode
+ *
+ * param config pointer to master configuration structure
+ */
 void SAI_RxGetDefaultConfig(sai_config_t *config)
 {
-    config->bclkSource = kSAI_BclkSourceMclkDiv;
+    /* Initializes the configure structure to zero. */
+    memset(config, 0, sizeof(*config));
+
+    config->bclkSource  = kSAI_BclkSourceMclkDiv;
     config->masterSlave = kSAI_Master;
-    config->mclkSource = kSAI_MclkSourceSysclk;
-    config->protocol = kSAI_BusI2S;
-    config->syncMode = kSAI_ModeSync;
 #if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR)
     config->mclkOutputEnable = true;
+#if !(defined(FSL_FEATURE_SAI_HAS_NO_MCR_MICS) && (FSL_FEATURE_SAI_HAS_NO_MCR_MICS))
+    config->mclkSource = kSAI_MclkSourceSysclk;
+#endif
 #endif /* FSL_FEATURE_SAI_HAS_MCR */
+    config->protocol = kSAI_BusI2S;
+    config->syncMode = kSAI_ModeSync;
 }
 
+/*!
+ * brief Resets the SAI Tx.
+ *
+ * This function enables the software reset and FIFO reset of SAI Tx. After reset, clear the reset bit.
+ *
+ * param base SAI base pointer
+ */
 void SAI_TxReset(I2S_Type *base)
 {
     /* Set the software reset and FIFO reset to clear internal state */
@@ -510,9 +721,16 @@ void SAI_TxReset(I2S_Type *base)
     base->TCR3 = 0;
     base->TCR4 = 0;
     base->TCR5 = 0;
-    base->TMR = 0;
+    base->TMR  = 0;
 }
 
+/*!
+ * brief Resets the SAI Rx.
+ *
+ * This function enables the software reset and FIFO reset of SAI Rx. After reset, clear the reset bit.
+ *
+ * param base SAI base pointer
+ */
 void SAI_RxReset(I2S_Type *base)
 {
     /* Set the software reset and FIFO reset to clear internal state */
@@ -526,9 +744,15 @@ void SAI_RxReset(I2S_Type *base)
     base->RCR3 = 0;
     base->RCR4 = 0;
     base->RCR5 = 0;
-    base->RMR = 0;
+    base->RMR  = 0;
 }
 
+/*!
+ * brief Enables/disables the SAI Tx.
+ *
+ * param base SAI base pointer
+ * param enable True means enable SAI Tx, false means disable.
+ */
 void SAI_TxEnable(I2S_Type *base, bool enable)
 {
     if (enable)
@@ -553,6 +777,12 @@ void SAI_TxEnable(I2S_Type *base, bool enable)
     }
 }
 
+/*!
+ * brief Enables/disables the SAI Rx.
+ *
+ * param base SAI base pointer
+ * param enable True means enable SAI Rx, false means disable.
+ */
 void SAI_RxEnable(I2S_Type *base, bool enable)
 {
     if (enable)
@@ -576,6 +806,17 @@ void SAI_RxEnable(I2S_Type *base, bool enable)
     }
 }
 
+/*!
+ * brief Do software reset or FIFO reset .
+ *
+ * FIFO reset means clear all the data in the FIFO, and make the FIFO pointer both to 0.
+ * Software reset means clear the Tx internal logic, including the bit clock, frame count etc. But software
+ * reset will not clear any configuration registers like TCR1~TCR5.
+ * This function will also clear all the error flags such as FIFO error, sync error etc.
+ *
+ * param base SAI base pointer
+ * param type Reset type, FIFO reset or software reset
+ */
 void SAI_TxSoftwareReset(I2S_Type *base, sai_reset_type_t type)
 {
     base->TCSR |= (uint32_t)type;
@@ -584,6 +825,17 @@ void SAI_TxSoftwareReset(I2S_Type *base, sai_reset_type_t type)
     base->TCSR &= ~I2S_TCSR_SR_MASK;
 }
 
+/*!
+ * brief Do software reset or FIFO reset .
+ *
+ * FIFO reset means clear all the data in the FIFO, and make the FIFO pointer both to 0.
+ * Software reset means clear the Rx internal logic, including the bit clock, frame count etc. But software
+ * reset will not clear any configuration registers like RCR1~RCR5.
+ * This function will also clear all the error flags such as FIFO error, sync error etc.
+ *
+ * param base SAI base pointer
+ * param type Reset type, FIFO reset or software reset
+ */
 void SAI_RxSoftwareReset(I2S_Type *base, sai_reset_type_t type)
 {
     base->RCSR |= (uint32_t)type;
@@ -592,18 +844,38 @@ void SAI_RxSoftwareReset(I2S_Type *base, sai_reset_type_t type)
     base->RCSR &= ~I2S_RCSR_SR_MASK;
 }
 
+/*!
+ * brief Set the Tx channel FIFO enable mask.
+ *
+ * param base SAI base pointer
+ * param mask Channel enable mask, 0 means all channel FIFO disabled, 1 means channel 0 enabled,
+ * 3 means both channel 0 and channel 1 enabled.
+ */
 void SAI_TxSetChannelFIFOMask(I2S_Type *base, uint8_t mask)
 {
     base->TCR3 &= ~I2S_TCR3_TCE_MASK;
     base->TCR3 |= I2S_TCR3_TCE(mask);
 }
 
+/*!
+ * brief Set the Rx channel FIFO enable mask.
+ *
+ * param base SAI base pointer
+ * param mask Channel enable mask, 0 means all channel FIFO disabled, 1 means channel 0 enabled,
+ * 3 means both channel 0 and channel 1 enabled.
+ */
 void SAI_RxSetChannelFIFOMask(I2S_Type *base, uint8_t mask)
 {
     base->RCR3 &= ~I2S_RCR3_RCE_MASK;
     base->RCR3 |= I2S_RCR3_RCE(mask);
 }
 
+/*!
+ * brief Set the Tx data order.
+ *
+ * param base SAI base pointer
+ * param order Data order MSB or LSB
+ */
 void SAI_TxSetDataOrder(I2S_Type *base, sai_data_order_t order)
 {
     uint32_t val = (base->TCR4) & (~I2S_TCR4_MF_MASK);
@@ -612,6 +884,12 @@ void SAI_TxSetDataOrder(I2S_Type *base, sai_data_order_t order)
     base->TCR4 = val;
 }
 
+/*!
+ * brief Set the Rx data order.
+ *
+ * param base SAI base pointer
+ * param order Data order MSB or LSB
+ */
 void SAI_RxSetDataOrder(I2S_Type *base, sai_data_order_t order)
 {
     uint32_t val = (base->RCR4) & (~I2S_RCR4_MF_MASK);
@@ -620,6 +898,12 @@ void SAI_RxSetDataOrder(I2S_Type *base, sai_data_order_t order)
     base->RCR4 = val;
 }
 
+/*!
+ * brief Set the Tx data order.
+ *
+ * param base SAI base pointer
+ * param order Data order MSB or LSB
+ */
 void SAI_TxSetBitClockPolarity(I2S_Type *base, sai_clock_polarity_t polarity)
 {
     uint32_t val = (base->TCR2) & (~I2S_TCR2_BCP_MASK);
@@ -628,6 +912,12 @@ void SAI_TxSetBitClockPolarity(I2S_Type *base, sai_clock_polarity_t polarity)
     base->TCR2 = val;
 }
 
+/*!
+ * brief Set the Rx data order.
+ *
+ * param base SAI base pointer
+ * param order Data order MSB or LSB
+ */
 void SAI_RxSetBitClockPolarity(I2S_Type *base, sai_clock_polarity_t polarity)
 {
     uint32_t val = (base->RCR2) & (~I2S_RCR2_BCP_MASK);
@@ -636,6 +926,12 @@ void SAI_RxSetBitClockPolarity(I2S_Type *base, sai_clock_polarity_t polarity)
     base->RCR2 = val;
 }
 
+/*!
+ * brief Set the Tx data order.
+ *
+ * param base SAI base pointer
+ * param order Data order MSB or LSB
+ */
 void SAI_TxSetFrameSyncPolarity(I2S_Type *base, sai_clock_polarity_t polarity)
 {
     uint32_t val = (base->TCR4) & (~I2S_TCR4_FSP_MASK);
@@ -644,6 +940,12 @@ void SAI_TxSetFrameSyncPolarity(I2S_Type *base, sai_clock_polarity_t polarity)
     base->TCR4 = val;
 }
 
+/*!
+ * brief Set the Rx data order.
+ *
+ * param base SAI base pointer
+ * param order Data order MSB or LSB
+ */
 void SAI_RxSetFrameSyncPolarity(I2S_Type *base, sai_clock_polarity_t polarity)
 {
     uint32_t val = (base->RCR4) & (~I2S_RCR4_FSP_MASK);
@@ -653,6 +955,12 @@ void SAI_RxSetFrameSyncPolarity(I2S_Type *base, sai_clock_polarity_t polarity)
 }
 
 #if defined(FSL_FEATURE_SAI_HAS_FIFO_PACKING) && FSL_FEATURE_SAI_HAS_FIFO_PACKING
+/*!
+ * brief Set Tx FIFO packing feature.
+ *
+ * param base SAI base pointer.
+ * param pack FIFO pack type. It is element of sai_fifo_packing_t.
+ */
 void SAI_TxSetFIFOPacking(I2S_Type *base, sai_fifo_packing_t pack)
 {
     uint32_t val = base->TCR4;
@@ -662,6 +970,12 @@ void SAI_TxSetFIFOPacking(I2S_Type *base, sai_fifo_packing_t pack)
     base->TCR4 = val;
 }
 
+/*!
+ * brief Set Rx FIFO packing feature.
+ *
+ * param base SAI base pointer.
+ * param pack FIFO pack type. It is element of sai_fifo_packing_t.
+ */
 void SAI_RxSetFIFOPacking(I2S_Type *base, sai_fifo_packing_t pack)
 {
     uint32_t val = base->RCR4;
@@ -672,167 +986,1129 @@ void SAI_RxSetFIFOPacking(I2S_Type *base, sai_fifo_packing_t pack)
 }
 #endif /* FSL_FEATURE_SAI_HAS_FIFO_PACKING */
 
-void SAI_TxSetFormat(I2S_Type *base,
-                     sai_transfer_format_t *format,
-                     uint32_t mclkSourceClockHz,
-                     uint32_t bclkSourceClockHz)
+/*!
+ * brief Transmitter bit clock rate configurations.
+ *
+ * param base SAI base pointer.
+ * param sourceClockHz, bit clock source frequency.
+ * param sampleRate audio data sample rate.
+ * param bitWidth, audio data bitWidth.
+ * param channelNumbers, audio channel numbers.
+ */
+void SAI_TxSetBitClockRate(
+    I2S_Type *base, uint32_t sourceClockHz, uint32_t sampleRate, uint32_t bitWidth, uint32_t channelNumbers)
 {
-    uint32_t bclk = 0;
-    uint32_t val = 0;
-    uint32_t channels = 2U;
+    uint32_t tcr2         = base->TCR2;
+    uint32_t bitClockDiv  = 0;
+    uint32_t bitClockFreq = sampleRate * bitWidth * channelNumbers;
+
+    assert(sourceClockHz >= bitClockFreq);
 
-    if (format->stereo != kSAI_Stereo)
+    tcr2 &= ~I2S_TCR2_DIV_MASK;
+    /* need to check the divided bclk, if bigger than target, then divider need to re-calculate. */
+    bitClockDiv = sourceClockHz / bitClockFreq;
+    /* for the condition where the source clock is smaller than target bclk */
+    if (bitClockDiv == 0U)
     {
-        channels = 1U;
+        bitClockDiv++;
+    }
+    /* recheck the divider if properly or not, to make sure output blck not bigger than target*/
+    if ((sourceClockHz / bitClockDiv) > bitClockFreq)
+    {
+        bitClockDiv++;
     }
 
-    if (format->isFrameSyncCompact)
+#if defined(FSL_FEATURE_SAI_HAS_BCLK_BYPASS) && (FSL_FEATURE_SAI_HAS_BCLK_BYPASS)
+    /* if bclk same with MCLK, bypass the divider */
+    if (bitClockDiv == 1U)
     {
-        bclk = format->sampleRate_Hz * format->bitWidth * channels;
-        val = (base->TCR4 & (~I2S_TCR4_SYWD_MASK));
-        val |= I2S_TCR4_SYWD(format->bitWidth - 1U);
-        base->TCR4 = val;
+        tcr2 |= I2S_TCR2_BYP_MASK;
     }
     else
+#endif
     {
-        bclk = format->sampleRate_Hz * 32U * 2U;
+        tcr2 |= I2S_TCR2_DIV(bitClockDiv / 2U - 1U);
     }
 
-/* Compute the mclk */
-#if defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER)
-    /* Check if master clock divider enabled, then set master clock divider */
-    if (base->MCR & I2S_MCR_MOE_MASK)
+    base->TCR2 = tcr2;
+}
+
+/*!
+ * brief Receiver bit clock rate configurations.
+ *
+ * param base SAI base pointer.
+ * param sourceClockHz, bit clock source frequency.
+ * param sampleRate audio data sample rate.
+ * param bitWidth, audio data bitWidth.
+ * param channelNumbers, audio channel numbers.
+ */
+void SAI_RxSetBitClockRate(
+    I2S_Type *base, uint32_t sourceClockHz, uint32_t sampleRate, uint32_t bitWidth, uint32_t channelNumbers)
+{
+    uint32_t rcr2         = base->RCR2;
+    uint32_t bitClockDiv  = 0;
+    uint32_t bitClockFreq = sampleRate * bitWidth * channelNumbers;
+
+    assert(sourceClockHz >= bitClockFreq);
+
+    rcr2 &= ~I2S_RCR2_DIV_MASK;
+    /* need to check the divided bclk, if bigger than target, then divider need to re-calculate. */
+    bitClockDiv = sourceClockHz / bitClockFreq;
+    /* for the condition where the source clock is smaller than target bclk */
+    if (bitClockDiv == 0U)
     {
-        SAI_SetMasterClockDivider(base, format->masterClockHz, mclkSourceClockHz);
+        bitClockDiv++;
     }
-#endif /* FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER */
-
-    /* Set bclk if needed */
-    if (base->TCR2 & I2S_TCR2_BCD_MASK)
+    /* recheck the divider if properly or not, to make sure output blck not bigger than target*/
+    if ((sourceClockHz / bitClockDiv) > bitClockFreq)
     {
-        base->TCR2 &= ~I2S_TCR2_DIV_MASK;
-        base->TCR2 |= I2S_TCR2_DIV((bclkSourceClockHz / bclk) / 2U - 1U);
+        bitClockDiv++;
     }
 
-    /* Set bitWidth */
-    val = (format->isFrameSyncCompact) ? (format->bitWidth - 1) : 31U;
-    if (format->protocol == kSAI_BusRightJustified)
+#if defined(FSL_FEATURE_SAI_HAS_BCLK_BYPASS) && (FSL_FEATURE_SAI_HAS_BCLK_BYPASS)
+    /* if bclk same with MCLK, bypass the divider */
+    if (bitClockDiv == 1U)
     {
-        base->TCR5 = I2S_TCR5_WNW(val) | I2S_TCR5_W0W(val) | I2S_TCR5_FBT(val);
+        rcr2 |= I2S_RCR2_BYP_MASK;
     }
     else
+#endif
     {
-        if (base->TCR4 & I2S_TCR4_MF_MASK)
-        {
-            base->TCR5 = I2S_TCR5_WNW(val) | I2S_TCR5_W0W(val) | I2S_TCR5_FBT(format->bitWidth - 1);
-        }
-        else
-        {
-            base->TCR5 = I2S_TCR5_WNW(val) | I2S_TCR5_W0W(val) | I2S_TCR5_FBT(0);
-        }
+        rcr2 |= I2S_RCR2_DIV(bitClockDiv / 2U - 1U);
     }
 
-    /* Set mono or stereo */
-    base->TMR = (uint32_t)format->stereo;
-
-    /* Set data channel */
-    base->TCR3 &= ~I2S_TCR3_TCE_MASK;
-    base->TCR3 |= I2S_TCR3_TCE(1U << format->channel);
-
-#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1)
-    /* Set watermark */
-    base->TCR1 = format->watermark;
-#endif /* FSL_FEATURE_SAI_FIFO_COUNT  */
+    base->RCR2 = rcr2;
 }
 
-void SAI_RxSetFormat(I2S_Type *base,
-                     sai_transfer_format_t *format,
-                     uint32_t mclkSourceClockHz,
-                     uint32_t bclkSourceClockHz)
+/*!
+ * brief Transmitter Bit clock configurations.
+ *
+ * param base SAI base pointer.
+ * param masterSlave master or slave.
+ * param config bit clock other configurations, can be NULL in slave mode.
+ */
+void SAI_TxSetBitclockConfig(I2S_Type *base, sai_master_slave_t masterSlave, sai_bit_clock_t *config)
 {
-    uint32_t bclk = 0;
-    uint32_t val = 0;
-    uint32_t channels = 2U;
+    uint32_t tcr2 = base->TCR2;
 
-    if (format->stereo != kSAI_Stereo)
+    if ((masterSlave == kSAI_Master) || (masterSlave == kSAI_Bclk_Master_FrameSync_Slave))
     {
-        channels = 1U;
-    }
+        assert(config != NULL);
 
-    if (format->isFrameSyncCompact)
-    {
-        bclk = format->sampleRate_Hz * format->bitWidth * channels;
-        val = (base->RCR4 & (~I2S_RCR4_SYWD_MASK));
-        val |= I2S_RCR4_SYWD(format->bitWidth - 1U);
-        base->RCR4 = val;
+        tcr2 &= ~(I2S_TCR2_BCD_MASK | I2S_TCR2_BCP_MASK | I2S_TCR2_BCI_MASK | I2S_TCR2_BCS_MASK | I2S_TCR2_MSEL_MASK);
+        tcr2 |= I2S_TCR2_BCD(1U) | I2S_TCR2_BCP(config->bclkPolarity) | I2S_TCR2_BCI(config->bclkInputDelay) |
+                I2S_TCR2_BCS(config->bclkSrcSwap) | I2S_TCR2_MSEL(config->bclkSource);
     }
     else
     {
-        bclk = format->sampleRate_Hz * 32U * 2U;
+        tcr2 &= ~(I2S_TCR2_BCD_MASK);
     }
 
-/* Compute the mclk */
-#if defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER)
-    /* Check if master clock divider enabled */
-    if (base->MCR & I2S_MCR_MOE_MASK)
-    {
-        SAI_SetMasterClockDivider(base, format->masterClockHz, mclkSourceClockHz);
-    }
-#endif /* FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER */
+    base->TCR2 = tcr2;
+}
 
-    /* Set bclk if needed */
-    if (base->RCR2 & I2S_RCR2_BCD_MASK)
-    {
-        base->RCR2 &= ~I2S_RCR2_DIV_MASK;
-        base->RCR2 |= I2S_RCR2_DIV((bclkSourceClockHz / bclk) / 2U - 1U);
-    }
+/*!
+ * brief Receiver Bit clock configurations.
+ *
+ * param base SAI base pointer.
+ * param masterSlave master or slave.
+ * param config bit clock other configurations, can be NULL in slave mode.
+ */
+void SAI_RxSetBitclockConfig(I2S_Type *base, sai_master_slave_t masterSlave, sai_bit_clock_t *config)
+{
+    uint32_t rcr2 = base->RCR2;
 
-    /* Set bitWidth */
-    val = (format->isFrameSyncCompact) ? (format->bitWidth - 1) : 31U;
-    if (format->protocol == kSAI_BusRightJustified)
+    if ((masterSlave == kSAI_Master) || (masterSlave == kSAI_Bclk_Master_FrameSync_Slave))
     {
-        base->RCR5 = I2S_RCR5_WNW(val) | I2S_RCR5_W0W(val) | I2S_RCR5_FBT(val);
+        assert(config != NULL);
+
+        rcr2 &= ~(I2S_RCR2_BCD_MASK | I2S_RCR2_BCP_MASK | I2S_RCR2_BCI_MASK | I2S_RCR2_BCS_MASK | I2S_RCR2_MSEL_MASK);
+        rcr2 |= I2S_RCR2_BCD(1U) | I2S_RCR2_BCP(config->bclkPolarity) | I2S_RCR2_BCI(config->bclkInputDelay) |
+                I2S_RCR2_BCS(config->bclkSrcSwap) | I2S_RCR2_MSEL(config->bclkSource);
     }
     else
     {
-        if (base->RCR4 & I2S_RCR4_MF_MASK)
-        {
-            base->RCR5 = I2S_RCR5_WNW(val) | I2S_RCR5_W0W(val) | I2S_RCR5_FBT(format->bitWidth - 1);
-        }
-        else
-        {
-            base->RCR5 = I2S_RCR5_WNW(val) | I2S_RCR5_W0W(val) | I2S_RCR5_FBT(0);
-        }
+        rcr2 &= ~(I2S_RCR2_BCD_MASK);
     }
 
-    /* Set mono or stereo */
-    base->RMR = (uint32_t)format->stereo;
-
-    /* Set data channel */
-    base->RCR3 &= ~I2S_RCR3_RCE_MASK;
-    base->RCR3 |= I2S_RCR3_RCE(1U << format->channel);
+    base->RCR2 = rcr2;
+}
 
-#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1)
+#if (defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR)) || \
+    (defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER))
+/*!
+ * brief Master clock configurations.
+ *
+ * param base SAI base pointer.
+ * param config master clock configurations.
+ */
+void SAI_SetMasterClockConfig(I2S_Type *base, sai_master_clock_t *config)
+{
+    assert(config != NULL);
+
+#if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR)
+    uint32_t val = 0;
+#if !(defined(FSL_FEATURE_SAI_HAS_NO_MCR_MICS) && (FSL_FEATURE_SAI_HAS_NO_MCR_MICS))
+    /* Master clock source setting */
+    val       = (base->MCR & ~I2S_MCR_MICS_MASK);
+    base->MCR = (val | I2S_MCR_MICS(config->mclkSource));
+#endif
+
+    /* Configure Master clock output enable */
+    val       = (base->MCR & ~I2S_MCR_MOE_MASK);
+    base->MCR = (val | I2S_MCR_MOE(config->mclkOutputEnable));
+#endif /* FSL_FEATURE_SAI_HAS_MCR */
+
+#if ((defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER)) || \
+     (defined(FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV) && (FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV)))
+    /* Check if master clock divider enabled, then set master clock divider */
+    if (config->mclkOutputEnable)
+    {
+        SAI_SetMasterClockDivider(base, config->mclkHz, config->mclkSourceClkHz);
+    }
+#endif /* FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER */
+}
+#endif
+
+/*!
+ * brief SAI transmitter fifo configurations.
+ *
+ * param base SAI base pointer.
+ * param config fifo configurations.
+ */
+void SAI_TxSetFifoConfig(I2S_Type *base, sai_fifo_t *config)
+{
+    assert(config != NULL);
+#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1)
+    assert(config->fifoWatermark <= (I2S_TCR1_TFW_MASK >> I2S_TCR1_TFW_SHIFT));
+#endif
+
+    uint32_t tcr4 = base->TCR4;
+
+#if defined(FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_COMBINE) && FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_COMBINE
+    tcr4 &= ~I2S_TCR4_FCOMB_MASK;
+    tcr4 |= I2S_TCR4_FCOMB(config->fifoCombine);
+#endif
+
+#if defined(FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR) && FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR
+    tcr4 &= ~I2S_TCR4_FCONT_MASK;
+    /* ERR05144: not set FCONT = 1 when TMR > 0, the transmit shift register may not load correctly that will cause TX
+     * not work */
+    if (base->TMR == 0U)
+    {
+        tcr4 |= I2S_TCR4_FCONT(config->fifoContinueOneError);
+    }
+#endif
+
+#if defined(FSL_FEATURE_SAI_HAS_FIFO_PACKING) && FSL_FEATURE_SAI_HAS_FIFO_PACKING
+    tcr4 &= ~I2S_TCR4_FPACK_MASK;
+    tcr4 |= I2S_TCR4_FPACK(config->fifoPacking);
+#endif
+
+    base->TCR4 = tcr4;
+
+#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1)
+    base->TCR1 = (base->TCR1 & (~I2S_TCR1_TFW_MASK)) | I2S_TCR1_TFW(config->fifoWatermark);
+#endif
+}
+
+/*!
+ * brief SAI receiver fifo configurations.
+ *
+ * param base SAI base pointer.
+ * param config fifo configurations.
+ */
+void SAI_RxSetFifoConfig(I2S_Type *base, sai_fifo_t *config)
+{
+    assert(config != NULL);
+#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1)
+    assert(config->fifoWatermark <= (I2S_TCR1_TFW_MASK >> I2S_TCR1_TFW_SHIFT));
+#endif
+    uint32_t rcr4 = base->RCR4;
+
+#if defined(FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_COMBINE) && FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_COMBINE
+    rcr4 &= ~I2S_RCR4_FCOMB_MASK;
+    rcr4 |= I2S_RCR4_FCOMB(config->fifoCombine);
+#endif
+
+#if defined(FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR) && FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR
+    rcr4 &= ~I2S_RCR4_FCONT_MASK;
+    rcr4 |= I2S_RCR4_FCONT(config->fifoContinueOneError);
+#endif
+
+#if defined(FSL_FEATURE_SAI_HAS_FIFO_PACKING) && FSL_FEATURE_SAI_HAS_FIFO_PACKING
+    rcr4 &= ~I2S_RCR4_FPACK_MASK;
+    rcr4 |= I2S_RCR4_FPACK(config->fifoPacking);
+#endif
+
+    base->RCR4 = rcr4;
+
+#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1)
+    base->RCR1 = (base->RCR1 & (~I2S_RCR1_RFW_MASK)) | I2S_RCR1_RFW(config->fifoWatermark);
+#endif
+}
+
+/*!
+ * brief SAI transmitter Frame sync configurations.
+ *
+ * param base SAI base pointer.
+ * param masterSlave master or slave.
+ * param config frame sync configurations, can be NULL in slave mode.
+ */
+void SAI_TxSetFrameSyncConfig(I2S_Type *base, sai_master_slave_t masterSlave, sai_frame_sync_t *config)
+{
+    uint32_t tcr4 = base->TCR4;
+
+    if ((masterSlave == kSAI_Master) || (masterSlave == kSAI_Bclk_Slave_FrameSync_Master))
+    {
+        assert(config != NULL);
+        assert((config->frameSyncWidth - 1U) <= (I2S_TCR4_SYWD_MASK >> I2S_TCR4_SYWD_SHIFT));
+
+        tcr4 &= ~(I2S_TCR4_FSE_MASK | I2S_TCR4_FSP_MASK | I2S_TCR4_FSD_MASK | I2S_TCR4_SYWD_MASK);
+
+#if defined(FSL_FEATURE_SAI_HAS_FRAME_SYNC_ON_DEMAND) && FSL_FEATURE_SAI_HAS_FRAME_SYNC_ON_DEMAND
+        tcr4 &= ~I2S_TCR4_ONDEM_MASK;
+        tcr4 |= I2S_TCR4_ONDEM(config->frameSyncGenerateOnDemand);
+#endif
+
+        tcr4 |= I2S_TCR4_FSE(config->frameSyncEarly) | I2S_TCR4_FSP(config->frameSyncPolarity) | I2S_TCR4_FSD(1U) |
+                I2S_TCR4_SYWD(config->frameSyncWidth - 1U);
+    }
+    else
+    {
+        tcr4 &= ~I2S_TCR4_FSD_MASK;
+    }
+
+    base->TCR4 = tcr4;
+}
+
+/*!
+ * brief SAI receiver Frame sync configurations.
+ *
+ * param base SAI base pointer.
+ * param masterSlave master or slave.
+ * param config frame sync configurations, can be NULL in slave mode.
+ */
+void SAI_RxSetFrameSyncConfig(I2S_Type *base, sai_master_slave_t masterSlave, sai_frame_sync_t *config)
+{
+    uint32_t rcr4 = base->RCR4;
+
+    if ((masterSlave == kSAI_Master) || (masterSlave == kSAI_Bclk_Slave_FrameSync_Master))
+    {
+        assert(config != NULL);
+        assert((config->frameSyncWidth - 1U) <= (I2S_RCR4_SYWD_MASK >> I2S_RCR4_SYWD_SHIFT));
+
+        rcr4 &= ~(I2S_RCR4_FSE_MASK | I2S_RCR4_FSP_MASK | I2S_RCR4_FSD_MASK | I2S_RCR4_SYWD_MASK);
+
+#if defined(FSL_FEATURE_SAI_HAS_FRAME_SYNC_ON_DEMAND) && FSL_FEATURE_SAI_HAS_FRAME_SYNC_ON_DEMAND
+        rcr4 &= ~I2S_RCR4_ONDEM_MASK;
+        rcr4 |= I2S_RCR4_ONDEM(config->frameSyncGenerateOnDemand);
+#endif
+
+        rcr4 |= I2S_RCR4_FSE(config->frameSyncEarly) | I2S_RCR4_FSP(config->frameSyncPolarity) | I2S_RCR4_FSD(1U) |
+                I2S_RCR4_SYWD(config->frameSyncWidth - 1U);
+    }
+    else
+    {
+        rcr4 &= ~I2S_RCR4_FSD_MASK;
+    }
+
+    base->RCR4 = rcr4;
+}
+
+/*!
+ * brief SAI transmitter Serial data configurations.
+ *
+ * param base SAI base pointer.
+ * param config serial data configurations.
+ */
+void SAI_TxSetSerialDataConfig(I2S_Type *base, sai_serial_data_t *config)
+{
+    assert(config != NULL);
+
+    uint32_t tcr4 = base->TCR4;
+
+    base->TCR5 = I2S_TCR5_WNW(config->dataWordNLength - 1U) | I2S_TCR5_W0W(config->dataWord0Length - 1U) |
+                 I2S_TCR5_FBT(config->dataFirstBitShifted - 1U);
+    base->TMR = config->dataMaskedWord;
+#if defined(FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR) && FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR
+    /* ERR05144: not set FCONT = 1 when TMR > 0, the transmit shift register may not load correctly that will cause TX
+     * not work */
+    if (config->dataMaskedWord > 0U)
+    {
+        tcr4 &= ~I2S_TCR4_FCONT_MASK;
+    }
+#endif
+    tcr4 &= ~(I2S_TCR4_FRSZ_MASK | I2S_TCR4_MF_MASK);
+    tcr4 |= I2S_TCR4_FRSZ(config->dataWordNum - 1U) | I2S_TCR4_MF(config->dataOrder);
+
+#if defined(FSL_FEATURE_SAI_HAS_CHANNEL_MODE) && FSL_FEATURE_SAI_HAS_CHANNEL_MODE
+    tcr4 &= ~I2S_TCR4_CHMOD_MASK;
+    tcr4 |= I2S_TCR4_CHMOD(config->dataMode);
+#endif
+
+    base->TCR4 = tcr4;
+}
+
+/*!
+ * @brief SAI receiver Serial data configurations.
+ *
+ * @param base SAI base pointer.
+ * @param config serial data configurations.
+ */
+void SAI_RxSetSerialDataConfig(I2S_Type *base, sai_serial_data_t *config)
+{
+    assert(config != NULL);
+
+    uint32_t rcr4 = base->RCR4;
+
+    base->RCR5 = I2S_RCR5_WNW(config->dataWordNLength - 1U) | I2S_RCR5_W0W(config->dataWord0Length - 1U) |
+                 I2S_RCR5_FBT(config->dataFirstBitShifted - 1U);
+    base->RMR = config->dataMaskedWord;
+
+    rcr4 &= ~(I2S_RCR4_FRSZ_MASK | I2S_RCR4_MF_MASK);
+    rcr4 |= I2S_RCR4_FRSZ(config->dataWordNum - 1u) | I2S_RCR4_MF(config->dataOrder);
+
+    base->RCR4 = rcr4;
+}
+
+/*!
+ * brief SAI transmitter configurations.
+ *
+ * param base SAI base pointer.
+ * param config transmitter configurations.
+ */
+void SAI_TxSetConfig(I2S_Type *base, sai_transceiver_t *config)
+{
+    assert(config != NULL);
+    assert(FSL_FEATURE_SAI_CHANNEL_COUNTn(base) != -1);
+
+    uint32_t val = 0U, i = 0U;
+    uint32_t channelNums = 0U;
+    /* reset transmitter */
+    SAI_TxReset(base);
+
+    /* if channel mask is not set, then format->channel must be set,
+     use it to get channel mask value */
+    if (config->channelMask == 0U)
+    {
+        config->channelMask = 1U << config->startChannel;
+    }
+
+    for (i = 0U; i < FSL_FEATURE_SAI_CHANNEL_COUNTn(base); i++)
+    {
+        if (((uint32_t)1 << i) & config->channelMask)
+        {
+            /* get start channel number when channelNums = 0 only */
+            if (channelNums == 0U)
+            {
+                config->startChannel = i;
+            }
+            channelNums++;
+            config->endChannel = i;
+        }
+    }
+    assert(channelNums <= FSL_FEATURE_SAI_CHANNEL_COUNTn(base));
+    config->channelNums = channelNums;
+#if defined(FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE) && (FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE)
+    /* make sure combine mode disabled while multipe channel is used */
+    if (config->channelNums > 1U)
+    {
+        base->TCR4 &= ~I2S_TCR4_FCOMB_MASK;
+    }
+#endif
+
+    /* Set data channel */
+    base->TCR3 &= ~I2S_TCR3_TCE_MASK;
+    base->TCR3 |= I2S_TCR3_TCE(config->channelMask);
+
+    /* Set Sync mode */
+    switch (config->syncMode)
+    {
+        case kSAI_ModeAsync:
+            val = base->TCR2;
+            val &= ~I2S_TCR2_SYNC_MASK;
+            base->TCR2 = (val | I2S_TCR2_SYNC(0U));
+            break;
+        case kSAI_ModeSync:
+            val = base->TCR2;
+            val &= ~I2S_TCR2_SYNC_MASK;
+            base->TCR2 = (val | I2S_TCR2_SYNC(1U));
+            /* If sync with Rx, should set Rx to async mode */
+            val = base->RCR2;
+            val &= ~I2S_RCR2_SYNC_MASK;
+            base->RCR2 = (val | I2S_RCR2_SYNC(0U));
+            break;
+#if defined(FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI) && (FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI)
+        case kSAI_ModeSyncWithOtherTx:
+            val = base->TCR2;
+            val &= ~I2S_TCR2_SYNC_MASK;
+            base->TCR2 = (val | I2S_TCR2_SYNC(2U));
+            break;
+        case kSAI_ModeSyncWithOtherRx:
+            val = base->TCR2;
+            val &= ~I2S_TCR2_SYNC_MASK;
+            base->TCR2 = (val | I2S_TCR2_SYNC(3U));
+            break;
+#endif /* FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI */
+        default:
+            break;
+    }
+
+    /* bit clock configurations */
+    SAI_TxSetBitclockConfig(base, config->masterSlave, &config->bitClock);
+    /* serial data configurations */
+    SAI_TxSetSerialDataConfig(base, &config->serialData);
+    /* frame sync configurations */
+    SAI_TxSetFrameSyncConfig(base, config->masterSlave, &config->frameSync);
+    /* fifo configurations */
+    SAI_TxSetFifoConfig(base, &config->fifo);
+}
+
+/*!
+ * brief SAI transmitter transfer configurations.
+ *
+ * This function initializes the TX, include bit clock, frame sync, master clock, serial data and fifo configurations.
+ *
+ * param base SAI base pointer.
+ * param handle SAI handle pointer.
+ * param config tranmitter configurations.
+ */
+void SAI_TransferTxSetConfig(I2S_Type *base, sai_handle_t *handle, sai_transceiver_t *config)
+{
+    assert(handle != NULL);
+    assert(config != NULL);
+
+    handle->bitWidth = config->frameSync.frameSyncWidth;
+#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1)
+    handle->watermark = config->fifo.fifoWatermark;
+#endif
+
+    /* transmitter configurations */
+    SAI_TxSetConfig(base, config);
+
+    handle->channel = config->startChannel;
+    /* used for multi channel */
+    handle->channelMask = config->channelMask;
+    handle->channelNums = config->channelNums;
+    handle->endChannel  = config->endChannel;
+}
+
+/*!
+ * brief SAI receiver configurations.
+ *
+ * param base SAI base pointer.
+ * param config transmitter configurations.
+ */
+void SAI_RxSetConfig(I2S_Type *base, sai_transceiver_t *config)
+{
+    assert(config != NULL);
+    assert(FSL_FEATURE_SAI_CHANNEL_COUNTn(base) != -1);
+
+    uint32_t val = 0U, i = 0U;
+    uint32_t channelNums = 0U;
+
+    /* reset receiver */
+    SAI_RxReset(base);
+
+    /* if channel mask is not set, then format->channel must be set,
+     use it to get channel mask value */
+    if (config->channelMask == 0U)
+    {
+        config->channelMask = 1U << config->startChannel;
+    }
+
+    for (i = 0U; i < FSL_FEATURE_SAI_CHANNEL_COUNTn(base); i++)
+    {
+        if (((uint32_t)1 << i) & config->channelMask)
+        {
+            /* get start channel number when channelNums = 0 only */
+            if (channelNums == 0U)
+            {
+                config->startChannel = i;
+            }
+            channelNums++;
+            config->endChannel = i;
+        }
+    }
+    assert(channelNums <= FSL_FEATURE_SAI_CHANNEL_COUNTn(base));
+    config->channelNums = channelNums;
+#if defined(FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE) && (FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE)
+    /* make sure combine mode disabled while multipe channel is used */
+    if (config->channelNums > 1U)
+    {
+        base->RCR4 &= ~I2S_RCR4_FCOMB_MASK;
+    }
+#endif
+
+    /* Set data channel */
+    base->RCR3 &= ~I2S_RCR3_RCE_MASK;
+    base->RCR3 |= I2S_RCR3_RCE(config->channelMask);
+
+    /* Set Sync mode */
+    switch (config->syncMode)
+    {
+        case kSAI_ModeAsync:
+            val = base->RCR2;
+            val &= ~I2S_RCR2_SYNC_MASK;
+            base->RCR2 = (val | I2S_RCR2_SYNC(0U));
+            break;
+        case kSAI_ModeSync:
+            val = base->RCR2;
+            val &= ~I2S_RCR2_SYNC_MASK;
+            base->RCR2 = (val | I2S_RCR2_SYNC(1U));
+            /* If sync with Tx, should set Tx to async mode */
+            val = base->TCR2;
+            val &= ~I2S_TCR2_SYNC_MASK;
+            base->TCR2 = (val | I2S_TCR2_SYNC(0U));
+            break;
+#if defined(FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI) && (FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI)
+        case kSAI_ModeSyncWithOtherTx:
+            val = base->RCR2;
+            val &= ~I2S_RCR2_SYNC_MASK;
+            base->RCR2 = (val | I2S_RCR2_SYNC(2U));
+            break;
+        case kSAI_ModeSyncWithOtherRx:
+            val = base->RCR2;
+            val &= ~I2S_RCR2_SYNC_MASK;
+            base->RCR2 = (val | I2S_RCR2_SYNC(3U));
+            break;
+#endif /* FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI */
+        default:
+            break;
+    }
+
+    /* bit clock configurations */
+    SAI_RxSetBitclockConfig(base, config->masterSlave, &config->bitClock);
+    /* serial data configurations */
+    SAI_RxSetSerialDataConfig(base, &config->serialData);
+    /* frame sync configurations */
+    SAI_RxSetFrameSyncConfig(base, config->masterSlave, &config->frameSync);
+    /* fifo configurations */
+    SAI_RxSetFifoConfig(base, &config->fifo);
+}
+
+/*!
+ * brief SAI receiver transfer configurations.
+ *
+ * This function initializes the TX, include bit clock, frame sync, master clock, serial data and fifo configurations.
+ *
+ * param base SAI base pointer.
+ * param handle SAI handle pointer.
+ * param config tranmitter configurations.
+ */
+void SAI_TransferRxSetConfig(I2S_Type *base, sai_handle_t *handle, sai_transceiver_t *config)
+{
+    assert(handle != NULL);
+    assert(config != NULL);
+
+    handle->bitWidth = config->frameSync.frameSyncWidth;
+#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1)
+    handle->watermark = config->fifo.fifoWatermark;
+#endif
+
+    /* receiver configurations */
+    SAI_RxSetConfig(base, config);
+
+    handle->channel = config->startChannel;
+    /* used for multi channel */
+    handle->channelMask = config->channelMask;
+    handle->channelNums = config->channelNums;
+    handle->endChannel  = config->endChannel;
+}
+
+/*!
+ * brief Get classic I2S mode configurations.
+ *
+ * param config transceiver configurations.
+ * param bitWidth audio data bitWidth.
+ * param mode audio data channel.
+ * param saiChannelMask channel mask value to enable.
+ */
+void SAI_GetClassicI2SConfig(sai_transceiver_t *config,
+                             sai_word_width_t bitWidth,
+                             sai_mono_stereo_t mode,
+                             uint32_t saiChannelMask)
+{
+    SAI_GetCommonConfig(config, bitWidth, mode, saiChannelMask);
+}
+
+/*!
+ * brief Get left justified mode configurations.
+ *
+ * param config transceiver configurations.
+ * param bitWidth audio data bitWidth.
+ * param mode audio data channel.
+ * param saiChannelMask channel mask value to enable.
+ */
+void SAI_GetLeftJustifiedConfig(sai_transceiver_t *config,
+                                sai_word_width_t bitWidth,
+                                sai_mono_stereo_t mode,
+                                uint32_t saiChannelMask)
+{
+    assert(NULL != config);
+    assert(saiChannelMask != 0U);
+
+    SAI_GetCommonConfig(config, bitWidth, mode, saiChannelMask);
+
+    config->frameSync.frameSyncEarly    = false;
+    config->frameSync.frameSyncPolarity = kSAI_PolarityActiveHigh;
+}
+
+/*!
+ * brief Get right justified mode configurations.
+ *
+ * param config transceiver configurations.
+ * param bitWidth audio data bitWidth.
+ * param mode audio data channel.
+ * param saiChannelMask channel mask value to enable.
+ */
+void SAI_GetRightJustifiedConfig(sai_transceiver_t *config,
+                                 sai_word_width_t bitWidth,
+                                 sai_mono_stereo_t mode,
+                                 uint32_t saiChannelMask)
+{
+    assert(NULL != config);
+    assert(saiChannelMask != 0U);
+
+    SAI_GetCommonConfig(config, bitWidth, mode, saiChannelMask);
+
+    config->frameSync.frameSyncEarly    = false;
+    config->frameSync.frameSyncPolarity = kSAI_PolarityActiveHigh;
+}
+
+/*!
+ * brief Get DSP mode configurations.
+ *
+ * param config transceiver configurations.
+ * param bitWidth audio data bitWidth.
+ * param mode audio data channel.
+ * param saiChannelMask channel mask value to enable.
+ */
+void SAI_GetDSPConfig(sai_transceiver_t *config,
+                      sai_frame_sync_len_t frameSyncWidth,
+                      sai_word_width_t bitWidth,
+                      sai_mono_stereo_t mode,
+                      uint32_t saiChannelMask)
+{
+    assert(NULL != config);
+    assert(saiChannelMask != 0U);
+
+    SAI_GetCommonConfig(config, bitWidth, mode, saiChannelMask);
+
+    /* frame sync default configurations */
+    switch (frameSyncWidth)
+    {
+        case kSAI_FrameSyncLenOneBitClk:
+            config->frameSync.frameSyncWidth = 1U;
+            break;
+        default:
+            assert(false);
+    }
+    config->frameSync.frameSyncEarly    = false;
+    config->frameSync.frameSyncPolarity = kSAI_PolarityActiveHigh;
+}
+
+/*!
+ * brief Get TDM mode configurations.
+ *
+ * param config transceiver configurations.
+ * param bitWidth audio data bitWidth.
+ * param mode audio data channel.
+ * param saiChannelMask channel mask value to enable.
+ */
+void SAI_GetTDMConfig(sai_transceiver_t *config,
+                      sai_frame_sync_len_t frameSyncWidth,
+                      sai_word_width_t bitWidth,
+                      uint32_t dataWordNum,
+                      uint32_t saiChannelMask)
+{
+    assert(NULL != config);
+    assert(saiChannelMask != 0U);
+    assert(dataWordNum <= 32U);
+
+    SAI_GetCommonConfig(config, bitWidth, kSAI_Stereo, saiChannelMask);
+
+    /* frame sync default configurations */
+    switch (frameSyncWidth)
+    {
+        case kSAI_FrameSyncLenOneBitClk:
+            config->frameSync.frameSyncWidth = 1U;
+            break;
+        case kSAI_FrameSyncLenPerWordWidth:
+            break;
+        default:
+            assert(false);
+    }
+    config->frameSync.frameSyncEarly    = false;
+    config->frameSync.frameSyncPolarity = kSAI_PolarityActiveHigh;
+    config->serialData.dataWordNum      = dataWordNum;
+}
+
+/*!
+ * brief Configures the SAI Tx audio format.
+ *
+ * deprecated Do not use this function.  It has been superceded by @ref SAI_TxSetConfig
+ *
+ * The audio format can be changed at run-time. This function configures the sample rate and audio data
+ * format to be transferred.
+ *
+ * param base SAI base pointer.
+ * param format Pointer to the SAI audio data format structure.
+ * param mclkSourceClockHz SAI master clock source frequency in Hz.
+ * param bclkSourceClockHz SAI bit clock source frequency in Hz. If the bit clock source is a master
+ * clock, this value should equal the masterClockHz.
+ */
+void SAI_TxSetFormat(I2S_Type *base,
+                     sai_transfer_format_t *format,
+                     uint32_t mclkSourceClockHz,
+                     uint32_t bclkSourceClockHz)
+{
+    assert(FSL_FEATURE_SAI_CHANNEL_COUNTn(base) != -1);
+
+    uint32_t bclk    = 0;
+    uint32_t val     = 0;
+    uint32_t i       = 0U;
+    uint32_t divider = 0U, channelNums = 0U;
+
+    if (format->isFrameSyncCompact)
+    {
+        bclk = format->sampleRate_Hz * format->bitWidth * (format->stereo == kSAI_Stereo ? 2U : 1U);
+        val  = (base->TCR4 & (~I2S_TCR4_SYWD_MASK));
+        val |= I2S_TCR4_SYWD(format->bitWidth - 1U);
+        base->TCR4 = val;
+    }
+    else
+    {
+        bclk = format->sampleRate_Hz * 32U * 2U;
+    }
+
+/* Compute the mclk */
+#if defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER)
+    /* Check if master clock divider enabled, then set master clock divider */
+    if (base->MCR & I2S_MCR_MOE_MASK)
+    {
+        SAI_SetMasterClockDivider(base, format->masterClockHz, mclkSourceClockHz);
+    }
+#endif /* FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER */
+
+    /* Set bclk if needed */
+    if (base->TCR2 & I2S_TCR2_BCD_MASK)
+    {
+        base->TCR2 &= ~I2S_TCR2_DIV_MASK;
+        /* need to check the divided bclk, if bigger than target, then divider need to re-calculate. */
+        divider = bclkSourceClockHz / bclk;
+        /* for the condition where the source clock is smaller than target bclk */
+        if (divider == 0U)
+        {
+            divider++;
+        }
+        /* recheck the divider if properly or not, to make sure output blck not bigger than target*/
+        if ((bclkSourceClockHz / divider) > bclk)
+        {
+            divider++;
+        }
+
+#if defined(FSL_FEATURE_SAI_HAS_BCLK_BYPASS) && (FSL_FEATURE_SAI_HAS_BCLK_BYPASS)
+        /* if bclk same with MCLK, bypass the divider */
+        if (divider == 1U)
+        {
+            base->TCR2 |= I2S_TCR2_BYP_MASK;
+        }
+        else
+#endif
+        {
+            base->TCR2 |= I2S_TCR2_DIV(divider / 2U - 1U);
+        }
+    }
+
+    /* Set bitWidth */
+    val = (format->isFrameSyncCompact) ? (format->bitWidth - 1) : 31U;
+    if (format->protocol == kSAI_BusRightJustified)
+    {
+        base->TCR5 = I2S_TCR5_WNW(val) | I2S_TCR5_W0W(val) | I2S_TCR5_FBT(val);
+    }
+    else
+    {
+        if (base->TCR4 & I2S_TCR4_MF_MASK)
+        {
+            base->TCR5 = I2S_TCR5_WNW(val) | I2S_TCR5_W0W(val) | I2S_TCR5_FBT(format->bitWidth - 1);
+        }
+        else
+        {
+            base->TCR5 = I2S_TCR5_WNW(val) | I2S_TCR5_W0W(val) | I2S_TCR5_FBT(0);
+        }
+    }
+
+    /* Set mono or stereo */
+    base->TMR = (uint32_t)format->stereo;
+
+    /* if channel mask is not set, then format->channel must be set,
+     use it to get channel mask value */
+    if (format->channelMask == 0U)
+    {
+        format->channelMask = 1U << format->channel;
+    }
+
+    /* if channel nums is not set, calculate it here according to channelMask*/
+    for (i = 0U; i < FSL_FEATURE_SAI_CHANNEL_COUNTn(base); i++)
+    {
+        if (((uint32_t)1 << i) & format->channelMask)
+        {
+            /* geet start channel number when channelNums = 0 only */
+            if (channelNums == 0U)
+            {
+                format->channel = i;
+            }
+            channelNums++;
+            format->endChannel = i;
+        }
+    }
+    format->channelNums = channelNums;
+    assert(format->channelNums <= FSL_FEATURE_SAI_CHANNEL_COUNTn(base));
+
+#if defined(FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE) && (FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE)
+    /* make sure combine mode disabled while multipe channel is used */
+    if (format->channelNums > 1U)
+    {
+        base->TCR4 &= ~I2S_TCR4_FCOMB_MASK;
+    }
+#endif
+
+    /* Set data channel */
+    base->TCR3 &= ~I2S_TCR3_TCE_MASK;
+    base->TCR3 |= I2S_TCR3_TCE(format->channelMask);
+
+#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1)
+    /* Set watermark */
+    base->TCR1 = format->watermark;
+#endif /* FSL_FEATURE_SAI_FIFO_COUNT  */
+}
+
+/*!
+ * brief Configures the SAI Rx audio format.
+ *
+ * deprecated Do not use this function.  It has been superceded by @ref SAI_RxSetConfig
+ *
+ * The audio format can be changed at run-time. This function configures the sample rate and audio data
+ * format to be transferred.
+ *
+ * param base SAI base pointer.
+ * param format Pointer to the SAI audio data format structure.
+ * param mclkSourceClockHz SAI master clock source frequency in Hz.
+ * param bclkSourceClockHz SAI bit clock source frequency in Hz. If the bit clock source is a master
+ * clock, this value should equal the masterClockHz.
+ */
+void SAI_RxSetFormat(I2S_Type *base,
+                     sai_transfer_format_t *format,
+                     uint32_t mclkSourceClockHz,
+                     uint32_t bclkSourceClockHz)
+{
+    assert(FSL_FEATURE_SAI_CHANNEL_COUNTn(base) != -1);
+
+    uint32_t bclk    = 0;
+    uint32_t val     = 0;
+    uint32_t i       = 0U;
+    uint32_t divider = 0U, channelNums = 0U;
+
+    if (format->isFrameSyncCompact)
+    {
+        bclk = format->sampleRate_Hz * format->bitWidth * (format->stereo == kSAI_Stereo ? 2U : 1U);
+        val  = (base->RCR4 & (~I2S_RCR4_SYWD_MASK));
+        val |= I2S_RCR4_SYWD(format->bitWidth - 1U);
+        base->RCR4 = val;
+    }
+    else
+    {
+        bclk = format->sampleRate_Hz * 32U * 2U;
+    }
+
+/* Compute the mclk */
+#if defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER)
+    /* Check if master clock divider enabled */
+    if (base->MCR & I2S_MCR_MOE_MASK)
+    {
+        SAI_SetMasterClockDivider(base, format->masterClockHz, mclkSourceClockHz);
+    }
+#endif /* FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER */
+
+    /* Set bclk if needed */
+    if (base->RCR2 & I2S_RCR2_BCD_MASK)
+    {
+        base->RCR2 &= ~I2S_RCR2_DIV_MASK;
+        /* need to check the divided bclk, if bigger than target, then divider need to re-calculate. */
+        divider = bclkSourceClockHz / bclk;
+        /* for the condition where the source clock is smaller than target bclk */
+        if (divider == 0U)
+        {
+            divider++;
+        }
+        /* recheck the divider if properly or not, to make sure output blck not bigger than target*/
+        if ((bclkSourceClockHz / divider) > bclk)
+        {
+            divider++;
+        }
+#if defined(FSL_FEATURE_SAI_HAS_BCLK_BYPASS) && (FSL_FEATURE_SAI_HAS_BCLK_BYPASS)
+        /* if bclk same with MCLK, bypass the divider */
+        if (divider == 1U)
+        {
+            base->RCR2 |= I2S_RCR2_BYP_MASK;
+        }
+        else
+#endif
+        {
+            base->RCR2 |= I2S_RCR2_DIV(divider / 2U - 1U);
+        }
+    }
+
+    /* Set bitWidth */
+    val = (format->isFrameSyncCompact) ? (format->bitWidth - 1) : 31U;
+    if (format->protocol == kSAI_BusRightJustified)
+    {
+        base->RCR5 = I2S_RCR5_WNW(val) | I2S_RCR5_W0W(val) | I2S_RCR5_FBT(val);
+    }
+    else
+    {
+        if (base->RCR4 & I2S_RCR4_MF_MASK)
+        {
+            base->RCR5 = I2S_RCR5_WNW(val) | I2S_RCR5_W0W(val) | I2S_RCR5_FBT(format->bitWidth - 1);
+        }
+        else
+        {
+            base->RCR5 = I2S_RCR5_WNW(val) | I2S_RCR5_W0W(val) | I2S_RCR5_FBT(0);
+        }
+    }
+
+    /* Set mono or stereo */
+    base->RMR = (uint32_t)format->stereo;
+
+    /* if channel mask is not set, then format->channel must be set,
+     use it to get channel mask value */
+    if (format->channelMask == 0U)
+    {
+        format->channelMask = 1U << format->channel;
+    }
+
+    /* if channel nums is not set, calculate it here according to channelMask*/
+    for (i = 0U; i < FSL_FEATURE_SAI_CHANNEL_COUNTn(base); i++)
+    {
+        if (((uint32_t)1 << i) & format->channelMask)
+        {
+            /* geet start channel number when channelNums = 0 only */
+            if (channelNums == 0U)
+            {
+                format->channel = i;
+            }
+            channelNums++;
+            format->endChannel = i;
+        }
+    }
+    format->channelNums = channelNums;
+    assert(format->channelNums <= FSL_FEATURE_SAI_CHANNEL_COUNTn(base));
+
+#if defined(FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE) && (FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE)
+    /* make sure combine mode disabled while multipe channel is used */
+    if (format->channelNums > 1U)
+    {
+        base->RCR4 &= ~I2S_RCR4_FCOMB_MASK;
+    }
+#endif
+
+    /* Set data channel */
+    base->RCR3 &= ~I2S_RCR3_RCE_MASK;
+    /* enable all the channel */
+    base->RCR3 |= I2S_RCR3_RCE(format->channelMask);
+
+#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1)
     /* Set watermark */
     base->RCR1 = format->watermark;
 #endif /* FSL_FEATURE_SAI_FIFO_COUNT  */
 }
 
+/*!
+ * brief Sends data using a blocking method.
+ *
+ * note This function blocks by polling until data is ready to be sent.
+ *
+ * param base SAI base pointer.
+ * param channel Data channel used.
+ * param bitWidth How many bits in an audio word; usually 8/16/24/32 bits.
+ * param buffer Pointer to the data to be written.
+ * param size Bytes to be written.
+ */
 void SAI_WriteBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size)
 {
-    uint32_t i = 0;
+    uint32_t i           = 0;
+    uint8_t bytesPerWord = bitWidth / 8U;
+#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1)
+    bytesPerWord = (size_t)((FSL_FEATURE_SAI_FIFO_COUNT - base->TCR1) * bytesPerWord);
+#endif
+
+    while (i < size)
+    {
+        /* Wait until it can write data */
+        while (!(base->TCSR & I2S_TCSR_FWF_MASK))
+        {
+        }
+
+        SAI_WriteNonBlocking(base, channel, 1U << channel, channel, bitWidth, buffer, bytesPerWord);
+        buffer += bytesPerWord;
+        i += bytesPerWord;
+    }
+
+    /* Wait until the last data is sent */
+    while (!(base->TCSR & I2S_TCSR_FWF_MASK))
+    {
+    }
+}
+
+/*!
+ * brief Sends data to multi channel using a blocking method.
+ *
+ * note This function blocks by polling until data is ready to be sent.
+ *
+ * param base SAI base pointer.
+ * param channel Data channel used.
+ * param channelMask channel mask.
+ * param bitWidth How many bits in an audio word; usually 8/16/24/32 bits.
+ * param buffer Pointer to the data to be written.
+ * param size Bytes to be written.
+ */
+void SAI_WriteMultiChannelBlocking(
+    I2S_Type *base, uint32_t channel, uint32_t channelMask, uint32_t bitWidth, uint8_t *buffer, uint32_t size)
+{
+    assert(FSL_FEATURE_SAI_CHANNEL_COUNTn(base) != -1);
+
+    uint32_t i = 0, j = 0;
     uint8_t bytesPerWord = bitWidth / 8U;
+    uint32_t channelNums = 0U, endChannel = 0U;
 
-    while (i < size)
+#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1)
+    bytesPerWord = (size_t)((FSL_FEATURE_SAI_FIFO_COUNT - base->TCR1) * bytesPerWord);
+#endif
+
+    for (i = 0U; (i < FSL_FEATURE_SAI_CHANNEL_COUNTn(base)); i++)
+    {
+        if ((1U << i) & (channelMask))
+        {
+            channelNums++;
+            endChannel = i;
+        }
+    }
+
+    assert(channelNums <= FSL_FEATURE_SAI_CHANNEL_COUNTn(base));
+    bytesPerWord *= channelNums;
+
+    while (j < size)
     {
         /* Wait until it can write data */
         while (!(base->TCSR & I2S_TCSR_FWF_MASK))
         {
         }
 
-        SAI_WriteNonBlocking(base, channel, bitWidth, buffer, bytesPerWord);
+        SAI_WriteNonBlocking(base, channel, channelMask, endChannel, bitWidth, buffer, bytesPerWord);
         buffer += bytesPerWord;
-        i += bytesPerWord;
+        j += bytesPerWord;
     }
 
     /* Wait until the last data is sent */
@@ -841,10 +2117,72 @@ void SAI_WriteBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint
     }
 }
 
+/*!
+ * brief Receives multi channel data using a blocking method.
+ *
+ * note This function blocks by polling until data is ready to be sent.
+ *
+ * param base SAI base pointer.
+ * param channel Data channel used.
+ * param channelMask channel mask.
+ * param bitWidth How many bits in an audio word; usually 8/16/24/32 bits.
+ * param buffer Pointer to the data to be read.
+ * param size Bytes to be read.
+ */
+void SAI_ReadMultiChannelBlocking(
+    I2S_Type *base, uint32_t channel, uint32_t channelMask, uint32_t bitWidth, uint8_t *buffer, uint32_t size)
+{
+    assert(FSL_FEATURE_SAI_CHANNEL_COUNTn(base) != -1);
+
+    uint32_t i = 0, j = 0;
+    uint8_t bytesPerWord = bitWidth / 8U;
+    uint32_t channelNums = 0U, endChannel = 0U;
+#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1)
+    bytesPerWord = (size_t)(base->RCR1 * bytesPerWord);
+#endif
+    for (i = 0U; (i < FSL_FEATURE_SAI_CHANNEL_COUNTn(base)); i++)
+    {
+        if ((1U << i) & (channelMask))
+        {
+            channelNums++;
+            endChannel = i;
+        }
+    }
+
+    assert(channelNums <= FSL_FEATURE_SAI_CHANNEL_COUNTn(base));
+    bytesPerWord *= channelNums;
+
+    while (j < size)
+    {
+        /* Wait until data is received */
+        while (!(base->RCSR & I2S_RCSR_FWF_MASK))
+        {
+        }
+
+        SAI_ReadNonBlocking(base, channel, channelMask, endChannel, bitWidth, buffer, bytesPerWord);
+        buffer += bytesPerWord;
+        j += bytesPerWord;
+    }
+}
+
+/*!
+ * brief Receives data using a blocking method.
+ *
+ * note This function blocks by polling until data is ready to be sent.
+ *
+ * param base SAI base pointer.
+ * param channel Data channel used.
+ * param bitWidth How many bits in an audio word; usually 8/16/24/32 bits.
+ * param buffer Pointer to the data to be read.
+ * param size Bytes to be read.
+ */
 void SAI_ReadBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size)
 {
-    uint32_t i = 0;
+    uint32_t i           = 0;
     uint8_t bytesPerWord = bitWidth / 8U;
+#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1)
+    bytesPerWord = (size_t)(base->RCR1 * bytesPerWord);
+#endif
 
     while (i < size)
     {
@@ -853,12 +2191,23 @@ void SAI_ReadBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8
         {
         }
 
-        SAI_ReadNonBlocking(base, channel, bitWidth, buffer, bytesPerWord);
+        SAI_ReadNonBlocking(base, channel, 1U << channel, channel, bitWidth, buffer, bytesPerWord);
         buffer += bytesPerWord;
         i += bytesPerWord;
     }
 }
 
+/*!
+ * brief Initializes the SAI Tx handle.
+ *
+ * This function initializes the Tx handle for the SAI Tx transactional APIs. Call
+ * this function once to get the handle initialized.
+ *
+ * param base SAI base pointer
+ * param handle SAI handle pointer.
+ * param callback Pointer to the user callback function.
+ * param userData User parameter passed to the callback function
+ */
 void SAI_TransferTxCreateHandle(I2S_Type *base, sai_handle_t *handle, sai_transfer_callback_t callback, void *userData)
 {
     assert(handle);
@@ -870,6 +2219,7 @@ void SAI_TransferTxCreateHandle(I2S_Type *base, sai_handle_t *handle, sai_transf
 
     handle->callback = callback;
     handle->userData = userData;
+    handle->base     = base;
 
     /* Set the isr pointer */
     s_saiTxIsr = SAI_TransferTxHandleIRQ;
@@ -878,6 +2228,17 @@ void SAI_TransferTxCreateHandle(I2S_Type *base, sai_handle_t *handle, sai_transf
     EnableIRQ(s_saiTxIRQ[SAI_GetInstance(base)]);
 }
 
+/*!
+ * brief Initializes the SAI Rx handle.
+ *
+ * This function initializes the Rx handle for the SAI Rx transactional APIs. Call
+ * this function once to get the handle initialized.
+ *
+ * param base SAI base pointer.
+ * param handle SAI handle pointer.
+ * param callback Pointer to the user callback function.
+ * param userData User parameter passed to the callback function.
+ */
 void SAI_TransferRxCreateHandle(I2S_Type *base, sai_handle_t *handle, sai_transfer_callback_t callback, void *userData)
 {
     assert(handle);
@@ -889,6 +2250,7 @@ void SAI_TransferRxCreateHandle(I2S_Type *base, sai_handle_t *handle, sai_transf
 
     handle->callback = callback;
     handle->userData = userData;
+    handle->base     = base;
 
     /* Set the isr pointer */
     s_saiRxIsr = SAI_TransferRxHandleIRQ;
@@ -897,6 +2259,22 @@ void SAI_TransferRxCreateHandle(I2S_Type *base, sai_handle_t *handle, sai_transf
     EnableIRQ(s_saiRxIRQ[SAI_GetInstance(base)]);
 }
 
+/*!
+ * brief Configures the SAI Tx audio format.
+ *
+ * deprecated Do not use this function.  It has been superceded by @ref SAI_TxSetTransferConfig
+ *
+ * The audio format can be changed at run-time. This function configures the sample rate and audio data
+ * format to be transferred.
+ *
+ * param base SAI base pointer.
+ * param handle SAI handle pointer.
+ * param format Pointer to the SAI audio data format structure.
+ * param mclkSourceClockHz SAI master clock source frequency in Hz.
+ * param bclkSourceClockHz SAI bit clock source frequency in Hz. If a bit clock source is a master
+ * clock, this value should equal the masterClockHz in format.
+ * return Status of this function. Return value is the status_t.
+ */
 status_t SAI_TransferTxSetFormat(I2S_Type *base,
                                  sai_handle_t *handle,
                                  sai_transfer_format_t *format,
@@ -905,7 +2283,11 @@ status_t SAI_TransferTxSetFormat(I2S_Type *base,
 {
     assert(handle);
 
-    if ((mclkSourceClockHz < format->sampleRate_Hz) || (bclkSourceClockHz < format->sampleRate_Hz))
+    if ((bclkSourceClockHz < format->sampleRate_Hz)
+#if defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER)
+        || (mclkSourceClockHz < format->sampleRate_Hz)
+#endif
+    )
     {
         return kStatus_InvalidArgument;
     }
@@ -915,13 +2297,34 @@ status_t SAI_TransferTxSetFormat(I2S_Type *base,
 #if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1)
     handle->watermark = format->watermark;
 #endif
-    handle->channel = format->channel;
 
     SAI_TxSetFormat(base, format, mclkSourceClockHz, bclkSourceClockHz);
 
+    handle->channel = format->channel;
+    /* used for multi channel */
+    handle->channelMask = format->channelMask;
+    handle->channelNums = format->channelNums;
+    handle->endChannel  = format->endChannel;
+
     return kStatus_Success;
 }
 
+/*!
+ * brief Configures the SAI Rx audio format.
+ *
+ * deprecated Do not use this function.  It has been superceded by @ref SAI_RxSetTransferConfig
+ *
+ * The audio format can be changed at run-time. This function configures the sample rate and audio data
+ * format to be transferred.
+ *
+ * param base SAI base pointer.
+ * param handle SAI handle pointer.
+ * param format Pointer to the SAI audio data format structure.
+ * param mclkSourceClockHz SAI master clock source frequency in Hz.
+ * param bclkSourceClockHz SAI bit clock source frequency in Hz. If a bit clock source is a master
+ * clock, this value should equal the masterClockHz in format.
+ * return Status of this function. Return value is one of status_t.
+ */
 status_t SAI_TransferRxSetFormat(I2S_Type *base,
                                  sai_handle_t *handle,
                                  sai_transfer_format_t *format,
@@ -930,7 +2333,11 @@ status_t SAI_TransferRxSetFormat(I2S_Type *base,
 {
     assert(handle);
 
-    if ((mclkSourceClockHz < format->sampleRate_Hz) || (bclkSourceClockHz < format->sampleRate_Hz))
+    if ((bclkSourceClockHz < format->sampleRate_Hz)
+#if defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER)
+        || (mclkSourceClockHz < format->sampleRate_Hz)
+#endif
+    )
     {
         return kStatus_InvalidArgument;
     }
@@ -940,13 +2347,33 @@ status_t SAI_TransferRxSetFormat(I2S_Type *base,
 #if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1)
     handle->watermark = format->watermark;
 #endif
-    handle->channel = format->channel;
 
     SAI_RxSetFormat(base, format, mclkSourceClockHz, bclkSourceClockHz);
 
+    handle->channel = format->channel;
+    /* used for multi channel */
+    handle->channelMask = format->channelMask;
+    handle->channelNums = format->channelNums;
+    handle->endChannel  = format->endChannel;
+
     return kStatus_Success;
 }
 
+/*!
+ * brief Performs an interrupt non-blocking send transfer on SAI.
+ *
+ * note This API returns immediately after the transfer initiates.
+ * Call the SAI_TxGetTransferStatusIRQ to poll the transfer status and check whether
+ * the transfer is finished. If the return status is not kStatus_SAI_Busy, the transfer
+ * is finished.
+ *
+ * param base SAI base pointer.
+ * param handle Pointer to the sai_handle_t structure which stores the transfer state.
+ * param xfer Pointer to the sai_transfer_t structure.
+ * retval kStatus_Success Successfully started the data receive.
+ * retval kStatus_SAI_TxBusy Previous receive still not finished.
+ * retval kStatus_InvalidArgument The input parameter is invalid.
+ */
 status_t SAI_TransferSendNonBlocking(I2S_Type *base, sai_handle_t *handle, sai_transfer_t *xfer)
 {
     assert(handle);
@@ -958,15 +2385,15 @@ status_t SAI_TransferSendNonBlocking(I2S_Type *base, sai_handle_t *handle, sai_t
     }
 
     /* Add into queue */
-    handle->transferSize[handle->queueUser] = xfer->dataSize;
-    handle->saiQueue[handle->queueUser].data = xfer->data;
+    handle->transferSize[handle->queueUser]      = xfer->dataSize;
+    handle->saiQueue[handle->queueUser].data     = xfer->data;
     handle->saiQueue[handle->queueUser].dataSize = xfer->dataSize;
-    handle->queueUser = (handle->queueUser + 1) % SAI_XFER_QUEUE_SIZE;
+    handle->queueUser                            = (handle->queueUser + 1) % SAI_XFER_QUEUE_SIZE;
 
     /* Set the state to busy */
     handle->state = kSAI_Busy;
 
-/* Enable interrupt */
+    /* Enable interrupt */
 #if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1)
     /* Use FIFO request interrupt and fifo error*/
     SAI_TxEnableInterrupts(base, kSAI_FIFOErrorInterruptEnable | kSAI_FIFORequestInterruptEnable);
@@ -980,6 +2407,21 @@ status_t SAI_TransferSendNonBlocking(I2S_Type *base, sai_handle_t *handle, sai_t
     return kStatus_Success;
 }
 
+/*!
+ * brief Performs an interrupt non-blocking receive transfer on SAI.
+ *
+ * note This API returns immediately after the transfer initiates.
+ * Call the SAI_RxGetTransferStatusIRQ to poll the transfer status and check whether
+ * the transfer is finished. If the return status is not kStatus_SAI_Busy, the transfer
+ * is finished.
+ *
+ * param base SAI base pointer
+ * param handle Pointer to the sai_handle_t structure which stores the transfer state.
+ * param xfer Pointer to the sai_transfer_t structure.
+ * retval kStatus_Success Successfully started the data receive.
+ * retval kStatus_SAI_RxBusy Previous receive still not finished.
+ * retval kStatus_InvalidArgument The input parameter is invalid.
+ */
 status_t SAI_TransferReceiveNonBlocking(I2S_Type *base, sai_handle_t *handle, sai_transfer_t *xfer)
 {
     assert(handle);
@@ -991,10 +2433,10 @@ status_t SAI_TransferReceiveNonBlocking(I2S_Type *base, sai_handle_t *handle, sa
     }
 
     /* Add into queue */
-    handle->transferSize[handle->queueUser] = xfer->dataSize;
-    handle->saiQueue[handle->queueUser].data = xfer->data;
+    handle->transferSize[handle->queueUser]      = xfer->dataSize;
+    handle->saiQueue[handle->queueUser].data     = xfer->data;
     handle->saiQueue[handle->queueUser].dataSize = xfer->dataSize;
-    handle->queueUser = (handle->queueUser + 1) % SAI_XFER_QUEUE_SIZE;
+    handle->queueUser                            = (handle->queueUser + 1) % SAI_XFER_QUEUE_SIZE;
 
     /* Set state to busy */
     handle->state = kSAI_Busy;
@@ -1013,6 +2455,15 @@ status_t SAI_TransferReceiveNonBlocking(I2S_Type *base, sai_handle_t *handle, sa
     return kStatus_Success;
 }
 
+/*!
+ * brief Gets a set byte count.
+ *
+ * param base SAI base pointer.
+ * param handle Pointer to the sai_handle_t structure which stores the transfer state.
+ * param count Bytes count sent.
+ * retval kStatus_Success Succeed get the transfer count.
+ * retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress.
+ */
 status_t SAI_TransferGetSendCount(I2S_Type *base, sai_handle_t *handle, size_t *count)
 {
     assert(handle);
@@ -1031,6 +2482,15 @@ status_t SAI_TransferGetSendCount(I2S_Type *base, sai_handle_t *handle, size_t *
     return status;
 }
 
+/*!
+ * brief Gets a received byte count.
+ *
+ * param base SAI base pointer.
+ * param handle Pointer to the sai_handle_t structure which stores the transfer state.
+ * param count Bytes count received.
+ * retval kStatus_Success Succeed get the transfer count.
+ * retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress.
+ */
 status_t SAI_TransferGetReceiveCount(I2S_Type *base, sai_handle_t *handle, size_t *count)
 {
     assert(handle);
@@ -1049,6 +2509,15 @@ status_t SAI_TransferGetReceiveCount(I2S_Type *base, sai_handle_t *handle, size_
     return status;
 }
 
+/*!
+ * brief Aborts the current send.
+ *
+ * note This API can be called any time when an interrupt non-blocking transfer initiates
+ * to abort the transfer early.
+ *
+ * param base SAI base pointer.
+ * param handle Pointer to the sai_handle_t structure which stores the transfer state.
+ */
 void SAI_TransferAbortSend(I2S_Type *base, sai_handle_t *handle)
 {
     assert(handle);
@@ -1067,9 +2536,18 @@ void SAI_TransferAbortSend(I2S_Type *base, sai_handle_t *handle)
     /* Clear the queue */
     memset(handle->saiQueue, 0, sizeof(sai_transfer_t) * SAI_XFER_QUEUE_SIZE);
     handle->queueDriver = 0;
-    handle->queueUser = 0;
+    handle->queueUser   = 0;
 }
 
+/*!
+ * brief Aborts the current IRQ receive.
+ *
+ * note This API can be called when an interrupt non-blocking transfer initiates
+ * to abort the transfer early.
+ *
+ * param base SAI base pointer
+ * param handle Pointer to the sai_handle_t structure which stores the transfer state.
+ */
 void SAI_TransferAbortReceive(I2S_Type *base, sai_handle_t *handle)
 {
     assert(handle);
@@ -1088,9 +2566,18 @@ void SAI_TransferAbortReceive(I2S_Type *base, sai_handle_t *handle)
     /* Clear the queue */
     memset(handle->saiQueue, 0, sizeof(sai_transfer_t) * SAI_XFER_QUEUE_SIZE);
     handle->queueDriver = 0;
-    handle->queueUser = 0;
+    handle->queueUser   = 0;
 }
 
+/*!
+ * brief Terminate all SAI send.
+ *
+ * This function will clear all transfer slots buffered in the sai queue. If users only want to abort the
+ * current transfer slot, please call SAI_TransferAbortSend.
+ *
+ * param base SAI base pointer.
+ * param handle SAI eDMA handle pointer.
+ */
 void SAI_TransferTerminateSend(I2S_Type *base, sai_handle_t *handle)
 {
     assert(handle);
@@ -1101,10 +2588,19 @@ void SAI_TransferTerminateSend(I2S_Type *base, sai_handle_t *handle)
     /* Clear all the internal information */
     memset(handle->saiQueue, 0U, sizeof(handle->saiQueue));
     memset(handle->transferSize, 0U, sizeof(handle->transferSize));
-    handle->queueUser = 0U;
+    handle->queueUser   = 0U;
     handle->queueDriver = 0U;
 }
 
+/*!
+ * brief Terminate all SAI receive.
+ *
+ * This function will clear all transfer slots buffered in the sai queue. If users only want to abort the
+ * current transfer slot, please call SAI_TransferAbortReceive.
+ *
+ * param base SAI base pointer.
+ * param handle SAI eDMA handle pointer.
+ */
 void SAI_TransferTerminateReceive(I2S_Type *base, sai_handle_t *handle)
 {
     assert(handle);
@@ -1115,16 +2611,22 @@ void SAI_TransferTerminateReceive(I2S_Type *base, sai_handle_t *handle)
     /* Clear all the internal information */
     memset(handle->saiQueue, 0U, sizeof(handle->saiQueue));
     memset(handle->transferSize, 0U, sizeof(handle->transferSize));
-    handle->queueUser = 0U;
+    handle->queueUser   = 0U;
     handle->queueDriver = 0U;
 }
 
+/*!
+ * brief Tx interrupt handler.
+ *
+ * param base SAI base pointer.
+ * param handle Pointer to the sai_handle_t structure.
+ */
 void SAI_TransferTxHandleIRQ(I2S_Type *base, sai_handle_t *handle)
 {
     assert(handle);
 
-    uint8_t *buffer = handle->saiQueue[handle->queueDriver].data;
-    uint8_t dataSize = handle->bitWidth / 8U;
+    uint8_t *buffer  = handle->saiQueue[handle->queueDriver].data;
+    uint8_t dataSize = (handle->bitWidth / 8U) * handle->channelNums;
 
     /* Handle Error */
     if (base->TCSR & I2S_TCSR_FEF_MASK)
@@ -1151,7 +2653,8 @@ void SAI_TransferTxHandleIRQ(I2S_Type *base, sai_handle_t *handle)
                            (size_t)((FSL_FEATURE_SAI_FIFO_COUNT - handle->watermark) * dataSize));
 
         /* Copy the data from sai buffer to FIFO */
-        SAI_WriteNonBlocking(base, handle->channel, handle->bitWidth, buffer, size);
+        SAI_WriteNonBlocking(base, handle->channel, handle->channelMask, handle->endChannel, handle->bitWidth, buffer,
+                             size);
 
         /* Update the internal counter */
         handle->saiQueue[handle->queueDriver].dataSize -= size;
@@ -1162,7 +2665,8 @@ void SAI_TransferTxHandleIRQ(I2S_Type *base, sai_handle_t *handle)
     {
         uint8_t size = MIN((handle->saiQueue[handle->queueDriver].dataSize), dataSize);
 
-        SAI_WriteNonBlocking(base, handle->channel, handle->bitWidth, buffer, size);
+        SAI_WriteNonBlocking(base, handle->channel, handle->channelMask, handle->endChannel, handle->bitWidth, buffer,
+                             size);
 
         /* Update internal counter */
         handle->saiQueue[handle->queueDriver].dataSize -= size;
@@ -1170,7 +2674,7 @@ void SAI_TransferTxHandleIRQ(I2S_Type *base, sai_handle_t *handle)
     }
 #endif /* FSL_FEATURE_SAI_FIFO_COUNT */
 
-    /* If finished a blcok, call the callback function */
+    /* If finished a block, call the callback function */
     if (handle->saiQueue[handle->queueDriver].dataSize == 0U)
     {
         memset(&handle->saiQueue[handle->queueDriver], 0, sizeof(sai_transfer_t));
@@ -1188,12 +2692,18 @@ void SAI_TransferTxHandleIRQ(I2S_Type *base, sai_handle_t *handle)
     }
 }
 
+/*!
+ * brief Tx interrupt handler.
+ *
+ * param base SAI base pointer.
+ * param handle Pointer to the sai_handle_t structure.
+ */
 void SAI_TransferRxHandleIRQ(I2S_Type *base, sai_handle_t *handle)
 {
     assert(handle);
 
-    uint8_t *buffer = handle->saiQueue[handle->queueDriver].data;
-    uint8_t dataSize = handle->bitWidth / 8U;
+    uint8_t *buffer  = handle->saiQueue[handle->queueDriver].data;
+    uint8_t dataSize = (handle->bitWidth / 8U) * handle->channelNums;
 
     /* Handle Error */
     if (base->RCSR & I2S_RCSR_FEF_MASK)
@@ -1219,7 +2729,8 @@ void SAI_TransferRxHandleIRQ(I2S_Type *base, sai_handle_t *handle)
         uint8_t size = MIN((handle->saiQueue[handle->queueDriver].dataSize), (handle->watermark * dataSize));
 
         /* Copy the data from sai buffer to FIFO */
-        SAI_ReadNonBlocking(base, handle->channel, handle->bitWidth, buffer, size);
+        SAI_ReadNonBlocking(base, handle->channel, handle->channelMask, handle->endChannel, handle->bitWidth, buffer,
+                            size);
 
         /* Update the internal counter */
         handle->saiQueue[handle->queueDriver].dataSize -= size;
@@ -1230,7 +2741,8 @@ void SAI_TransferRxHandleIRQ(I2S_Type *base, sai_handle_t *handle)
     {
         uint8_t size = MIN((handle->saiQueue[handle->queueDriver].dataSize), dataSize);
 
-        SAI_ReadNonBlocking(base, handle->channel, handle->bitWidth, buffer, size);
+        SAI_ReadNonBlocking(base, handle->channel, handle->channelMask, handle->endChannel, handle->bitWidth, buffer,
+                            size);
 
         /* Update internal state */
         handle->saiQueue[handle->queueDriver].dataSize -= size;
@@ -1238,7 +2750,7 @@ void SAI_TransferRxHandleIRQ(I2S_Type *base, sai_handle_t *handle)
     }
 #endif /* FSL_FEATURE_SAI_FIFO_COUNT */
 
-    /* If finished a blcok, call the callback function */
+    /* If finished a block, call the callback function */
     if (handle->saiQueue[handle->queueDriver].dataSize == 0U)
     {
         memset(&handle->saiQueue[handle->queueDriver], 0, sizeof(sai_transfer_t));
@@ -1468,6 +2980,227 @@ void I2S3_Rx_DriverIRQHandler(void)
 }
 #endif /* I2S3*/
 
+#if defined(I2S4)
+void I2S4_DriverIRQHandler(void)
+{
+#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1)
+    if ((s_saiHandle[4][1]) && ((I2S4->RCSR & kSAI_FIFORequestFlag) || (I2S4->RCSR & kSAI_FIFOErrorFlag)) &&
+        ((I2S4->RCSR & kSAI_FIFORequestInterruptEnable) || (I2S4->RCSR & kSAI_FIFOErrorInterruptEnable)))
+#else
+    if ((s_saiHandle[4][1]) && ((I2S4->RCSR & kSAI_FIFOWarningFlag) || (I2S4->RCSR & kSAI_FIFOErrorFlag)) &&
+        ((I2S4->RCSR & kSAI_FIFOWarningInterruptEnable) || (I2S4->RCSR & kSAI_FIFOErrorInterruptEnable)))
+#endif
+    {
+        s_saiRxIsr(I2S4, s_saiHandle[4][1]);
+    }
+#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1)
+    if ((s_saiHandle[4][0]) && ((I2S4->TCSR & kSAI_FIFORequestFlag) || (I2S4->TCSR & kSAI_FIFOErrorFlag)) &&
+        ((I2S4->TCSR & kSAI_FIFORequestInterruptEnable) || (I2S4->TCSR & kSAI_FIFOErrorInterruptEnable)))
+#else
+    if ((s_saiHandle[4][0]) && ((I2S4->TCSR & kSAI_FIFOWarningFlag) || (I2S4->TCSR & kSAI_FIFOErrorFlag)) &&
+        ((I2S4->TCSR & kSAI_FIFOWarningInterruptEnable) || (I2S4->TCSR & kSAI_FIFOErrorInterruptEnable)))
+#endif
+    {
+        s_saiTxIsr(I2S4, s_saiHandle[4][0]);
+    }
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+    __DSB();
+#endif
+}
+
+void I2S4_Tx_DriverIRQHandler(void)
+{
+    assert(s_saiHandle[4][0]);
+    s_saiTxIsr(I2S4, s_saiHandle[4][0]);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+    __DSB();
+#endif
+}
+
+void I2S4_Rx_DriverIRQHandler(void)
+{
+    assert(s_saiHandle[4][1]);
+    s_saiRxIsr(I2S4, s_saiHandle[4][1]);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+    __DSB();
+#endif
+}
+#endif
+
+#if defined(FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ) && (FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ) && defined(I2S5) && \
+    defined(I2S6)
+void I2S56_DriverIRQHandler(void)
+{
+    /* use index 5 to get handle when I2S5 & I2S6 share IRQ NUMBER */
+    I2S_Type *base = s_saiHandle[5][1]->base;
+#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1)
+    if ((s_saiHandle[5][1]) && base && ((base->RCSR & kSAI_FIFORequestFlag) || (base->RCSR & kSAI_FIFOErrorFlag)) &&
+        ((base->RCSR & kSAI_FIFORequestInterruptEnable) || (base->RCSR & kSAI_FIFOErrorInterruptEnable)))
+#else
+    if ((s_saiHandle[5][1]) && base && ((base->RCSR & kSAI_FIFOWarningFlag) || (base->RCSR & kSAI_FIFOErrorFlag)) &&
+        ((base->RCSR & kSAI_FIFOWarningInterruptEnable) || (base->RCSR & kSAI_FIFOErrorInterruptEnable)))
+#endif
+    {
+        s_saiRxIsr(base, s_saiHandle[5][1]);
+    }
+
+    base = s_saiHandle[5][0]->base;
+#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1)
+    if ((s_saiHandle[5][0]) && base && ((base->TCSR & kSAI_FIFORequestFlag) || (base->TCSR & kSAI_FIFOErrorFlag)) &&
+        ((base->TCSR & kSAI_FIFORequestInterruptEnable) || (base->TCSR & kSAI_FIFOErrorInterruptEnable)))
+#else
+    if ((s_saiHandle[5][0]) && base && ((base->TCSR & kSAI_FIFOWarningFlag) || (base->TCSR & kSAI_FIFOErrorFlag)) &&
+        ((base->TCSR & kSAI_FIFOWarningInterruptEnable) || (base->TCSR & kSAI_FIFOErrorInterruptEnable)))
+#endif
+    {
+        s_saiTxIsr(base, s_saiHandle[5][0]);
+    }
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+    __DSB();
+#endif
+}
+
+void I2S56_Tx_DriverIRQHandler(void)
+{
+    /* use index 5 to get handle when I2S5 & I2S6 share IRQ NUMBER */
+    assert(s_saiHandle[5][0]);
+    s_saiTxIsr(s_saiHandle[5][0]->base, s_saiHandle[5][0]);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+    __DSB();
+#endif
+}
+
+void I2S56_Rx_DriverIRQHandler(void)
+{
+    /* use index 5 to get handle when I2S5 & I2S6 share IRQ NUMBER */
+    assert(s_saiHandle[5][1]);
+    s_saiRxIsr(s_saiHandle[5][1]->base, s_saiHandle[5][1]);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+    __DSB();
+#endif
+}
+
+#else
+
+#if defined(I2S5)
+void I2S5_DriverIRQHandler(void)
+{
+#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1)
+    if ((s_saiHandle[5][1]) && ((I2S5->RCSR & kSAI_FIFORequestFlag) || (I2S5->RCSR & kSAI_FIFOErrorFlag)) &&
+        ((I2S5->RCSR & kSAI_FIFORequestInterruptEnable) || (I2S5->RCSR & kSAI_FIFOErrorInterruptEnable)))
+#else
+    if ((s_saiHandle[5][1]) && ((I2S5->RCSR & kSAI_FIFOWarningFlag) || (I2S5->RCSR & kSAI_FIFOErrorFlag)) &&
+        ((I2S5->RCSR & kSAI_FIFOWarningInterruptEnable) || (I2S5->RCSR & kSAI_FIFOErrorInterruptEnable)))
+#endif
+    {
+        s_saiRxIsr(I2S5, s_saiHandle[5][1]);
+    }
+#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1)
+    if ((s_saiHandle[5][0]) && ((I2S5->TCSR & kSAI_FIFORequestFlag) || (I2S5->TCSR & kSAI_FIFOErrorFlag)) &&
+        ((I2S5->TCSR & kSAI_FIFORequestInterruptEnable) || (I2S5->TCSR & kSAI_FIFOErrorInterruptEnable)))
+#else
+    if ((s_saiHandle[5][0]) && ((I2S5->TCSR & kSAI_FIFOWarningFlag) || (I2S5->TCSR & kSAI_FIFOErrorFlag)) &&
+        ((I2S5->TCSR & kSAI_FIFOWarningInterruptEnable) || (I2S5->TCSR & kSAI_FIFOErrorInterruptEnable)))
+#endif
+    {
+        s_saiTxIsr(I2S5, s_saiHandle[5][0]);
+    }
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+    __DSB();
+#endif
+}
+
+void I2S5_Tx_DriverIRQHandler(void)
+{
+    assert(s_saiHandle[5][0]);
+    s_saiTxIsr(I2S5, s_saiHandle[5][0]);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+    __DSB();
+#endif
+}
+
+void I2S5_Rx_DriverIRQHandler(void)
+{
+    assert(s_saiHandle[5][1]);
+    s_saiRxIsr(I2S5, s_saiHandle[5][1]);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+    __DSB();
+#endif
+}
+#endif
+
+#if defined(I2S6)
+void I2S6_DriverIRQHandler(void)
+{
+#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1)
+    if ((s_saiHandle[6][1]) && ((I2S6->RCSR & kSAI_FIFORequestFlag) || (I2S6->RCSR & kSAI_FIFOErrorFlag)) &&
+        ((I2S6->RCSR & kSAI_FIFORequestInterruptEnable) || (I2S6->RCSR & kSAI_FIFOErrorInterruptEnable)))
+#else
+    if ((s_saiHandle[6][1]) && ((I2S6->RCSR & kSAI_FIFOWarningFlag) || (I2S6->RCSR & kSAI_FIFOErrorFlag)) &&
+        ((I2S6->RCSR & kSAI_FIFOWarningInterruptEnable) || (I2S6->RCSR & kSAI_FIFOErrorInterruptEnable)))
+#endif
+    {
+        s_saiRxIsr(I2S6, s_saiHandle[6][1]);
+    }
+#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1)
+    if ((s_saiHandle[6][0]) && ((I2S6->TCSR & kSAI_FIFORequestFlag) || (I2S6->TCSR & kSAI_FIFOErrorFlag)) &&
+        ((I2S6->TCSR & kSAI_FIFORequestInterruptEnable) || (I2S6->TCSR & kSAI_FIFOErrorInterruptEnable)))
+#else
+    if ((s_saiHandle[6][0]) && ((I2S6->TCSR & kSAI_FIFOWarningFlag) || (I2S6->TCSR & kSAI_FIFOErrorFlag)) &&
+        ((I2S6->TCSR & kSAI_FIFOWarningInterruptEnable) || (I2S6->TCSR & kSAI_FIFOErrorInterruptEnable)))
+#endif
+    {
+        s_saiTxIsr(I2S6, s_saiHandle[6][0]);
+    }
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+    __DSB();
+#endif
+}
+
+void I2S6_Tx_DriverIRQHandler(void)
+{
+    assert(s_saiHandle[6][0]);
+    s_saiTxIsr(I2S6, s_saiHandle[6][0]);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+    __DSB();
+#endif
+}
+
+void I2S6_Rx_DriverIRQHandler(void)
+{
+    assert(s_saiHandle[6][1]);
+    s_saiRxIsr(I2S6, s_saiHandle[6][1]);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+    __DSB();
+#endif
+}
+#endif
+#endif
+
 #if defined(AUDIO__SAI0)
 void AUDIO_SAI0_INT_DriverIRQHandler(void)
 {
@@ -1987,7 +3720,7 @@ void SAI3_DriverIRQHandler(void)
 #endif
 }
 
-void SAI3_Tx_DriverIRQHandler(void)
+void SAI3_TX_DriverIRQHandler(void)
 {
     assert(s_saiHandle[3][0]);
     s_saiTxIsr(SAI3, s_saiHandle[3][0]);
@@ -1998,7 +3731,7 @@ void SAI3_Tx_DriverIRQHandler(void)
 #endif
 }
 
-void SAI3_Rx_DriverIRQHandler(void)
+void SAI3_RX_DriverIRQHandler(void)
 {
     assert(s_saiHandle[3][1]);
     s_saiRxIsr(SAI3, s_saiHandle[3][1]);
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_sai.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_sai.h
index 82dd26bfa62..6a9c8355f0c 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_sai.h
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_sai.h
@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
  * All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #ifndef _FSL_SAI_H_
@@ -38,7 +12,7 @@
 #include "fsl_common.h"
 
 /*!
- * @addtogroup sai
+ * @addtogroup sai_driver
  * @{
  */
 
@@ -48,19 +22,32 @@
 
 /*! @name Driver version */
 /*@{*/
-#define FSL_SAI_DRIVER_VERSION (MAKE_VERSION(2, 1, 4)) /*!< Version 2.1.4 */
+#define FSL_SAI_DRIVER_VERSION (MAKE_VERSION(2, 2, 1)) /*!< Version 2.2.1 */
 /*@}*/
 
 /*! @brief SAI return status*/
 enum _sai_status_t
 {
-    kStatus_SAI_TxBusy = MAKE_STATUS(kStatusGroup_SAI, 0),    /*!< SAI Tx is busy. */
-    kStatus_SAI_RxBusy = MAKE_STATUS(kStatusGroup_SAI, 1),    /*!< SAI Rx is busy. */
-    kStatus_SAI_TxError = MAKE_STATUS(kStatusGroup_SAI, 2),   /*!< SAI Tx FIFO error. */
-    kStatus_SAI_RxError = MAKE_STATUS(kStatusGroup_SAI, 3),   /*!< SAI Rx FIFO error. */
+    kStatus_SAI_TxBusy    = MAKE_STATUS(kStatusGroup_SAI, 0), /*!< SAI Tx is busy. */
+    kStatus_SAI_RxBusy    = MAKE_STATUS(kStatusGroup_SAI, 1), /*!< SAI Rx is busy. */
+    kStatus_SAI_TxError   = MAKE_STATUS(kStatusGroup_SAI, 2), /*!< SAI Tx FIFO error. */
+    kStatus_SAI_RxError   = MAKE_STATUS(kStatusGroup_SAI, 3), /*!< SAI Rx FIFO error. */
     kStatus_SAI_QueueFull = MAKE_STATUS(kStatusGroup_SAI, 4), /*!< SAI transfer queue is full. */
-    kStatus_SAI_TxIdle = MAKE_STATUS(kStatusGroup_SAI, 5),    /*!< SAI Tx is idle */
-    kStatus_SAI_RxIdle = MAKE_STATUS(kStatusGroup_SAI, 6)     /*!< SAI Rx is idle */
+    kStatus_SAI_TxIdle    = MAKE_STATUS(kStatusGroup_SAI, 5), /*!< SAI Tx is idle */
+    kStatus_SAI_RxIdle    = MAKE_STATUS(kStatusGroup_SAI, 6)  /*!< SAI Rx is idle */
+};
+
+/*< sai channel mask value, actual channel numbers is depend soc specific */
+enum _sai_channel_mask
+{
+    kSAI_Channel0Mask = 1 << 0U, /*!< channel 0 mask value */
+    kSAI_Channel1Mask = 1 << 1U, /*!< channel 1 mask value */
+    kSAI_Channel2Mask = 1 << 2U, /*!< channel 2 mask value */
+    kSAI_Channel3Mask = 1 << 3U, /*!< channel 3 mask value */
+    kSAI_Channel4Mask = 1 << 4U, /*!< channel 4 mask value */
+    kSAI_Channel5Mask = 1 << 5U, /*!< channel 5 mask value */
+    kSAI_Channel6Mask = 1 << 6U, /*!< channel 6 mask value */
+    kSAI_Channel7Mask = 1 << 7U, /*!< channel 7 mask value */
 };
 
 /*! @brief Define the SAI bus type */
@@ -76,8 +63,10 @@ typedef enum _sai_protocol
 /*! @brief Master or slave mode */
 typedef enum _sai_master_slave
 {
-    kSAI_Master = 0x0U, /*!< Master mode */
-    kSAI_Slave = 0x1U   /*!< Slave mode */
+    kSAI_Master                      = 0x0U, /*!< Master mode include bclk and frame sync */
+    kSAI_Slave                       = 0x1U, /*!< Slave mode  include bclk and frame sync */
+    kSAI_Bclk_Master_FrameSync_Slave = 0x2U, /*!< bclk in master mode, frame sync in slave mode */
+    kSAI_Bclk_Slave_FrameSync_Master = 0x3U, /*!< bclk in slave mode, frame sync in master mode */
 } sai_master_slave_t;
 
 /*! @brief Mono or stereo audio format */
@@ -98,19 +87,24 @@ typedef enum _sai_data_order
 /*! @brief SAI clock polarity, active high or low */
 typedef enum _sai_clock_polarity
 {
-    kSAI_PolarityActiveHigh = 0x0U, /*!< Clock active high */
-    kSAI_PolarityActiveLow          /*!< Clock active low */
+    kSAI_PolarityActiveHigh = 0x0U,  /*!< Drive outputs on rising edge */
+    kSAI_PolarityActiveLow,          /*!< Drive outputs on falling edge */
+    kSAI_SampleOnFallingEdge = 0x0U, /*!< Sample inputs on falling edge */
+    kSAI_SampleOnRisingEdge          /*!< Sample inputs on rising edge */
 } sai_clock_polarity_t;
 
 /*! @brief Synchronous or asynchronous mode */
 typedef enum _sai_sync_mode
 {
-    kSAI_ModeAsync = 0x0U,    /*!< Asynchronous mode */
-    kSAI_ModeSync,            /*!< Synchronous mode (with receiver or transmit) */
+    kSAI_ModeAsync = 0x0U, /*!< Asynchronous mode */
+    kSAI_ModeSync,         /*!< Synchronous mode (with receiver or transmit) */
+#if defined(FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI) && (FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI)
     kSAI_ModeSyncWithOtherTx, /*!< Synchronous with another SAI transmit */
     kSAI_ModeSyncWithOtherRx  /*!< Synchronous with another SAI receiver */
+#endif                        /* FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI */
 } sai_sync_mode_t;
 
+#if !(defined(FSL_FEATURE_SAI_HAS_NO_MCR_MICS) && (FSL_FEATURE_SAI_HAS_NO_MCR_MICS))
 /*! @brief Mater clock source */
 typedef enum _sai_mclk_source
 {
@@ -119,14 +113,20 @@ typedef enum _sai_mclk_source
     kSAI_MclkSourceSelect2,       /*!< Master clock from source 2 */
     kSAI_MclkSourceSelect3        /*!< Master clock from source 3 */
 } sai_mclk_source_t;
+#endif
 
 /*! @brief Bit clock source */
 typedef enum _sai_bclk_source
 {
     kSAI_BclkSourceBusclk = 0x0U, /*!< Bit clock using bus clock */
-    kSAI_BclkSourceMclkDiv,       /*!< Bit clock using master clock divider */
-    kSAI_BclkSourceOtherSai0,     /*!< Bit clock from other SAI device  */
-    kSAI_BclkSourceOtherSai1      /*!< Bit clock from other SAI device */
+    /* General device bit source definition */
+    kSAI_BclkSourceMclkOption1 = 0x1U, /*!< Bit clock MCLK option 1 */
+    kSAI_BclkSourceMclkOption2 = 0x2U, /*!< Bit clock MCLK option2  */
+    kSAI_BclkSourceMclkOption3 = 0x3U, /*!< Bit clock MCLK option3 */
+    /* Kinetis device bit clock source definition */
+    kSAI_BclkSourceMclkDiv   = 0x1U, /*!< Bit clock using master clock divider */
+    kSAI_BclkSourceOtherSai0 = 0x2U, /*!< Bit clock from other SAI device  */
+    kSAI_BclkSourceOtherSai1 = 0x3U  /*!< Bit clock from other SAI device */
 } sai_bclk_source_t;
 
 /*! @brief The SAI interrupt enable flag */
@@ -134,9 +134,9 @@ enum _sai_interrupt_enable_t
 {
     kSAI_WordStartInterruptEnable =
         I2S_TCSR_WSIE_MASK, /*!< Word start flag, means the first word in a frame detected */
-    kSAI_SyncErrorInterruptEnable = I2S_TCSR_SEIE_MASK,   /*!< Sync error flag, means the sync error is detected */
+    kSAI_SyncErrorInterruptEnable   = I2S_TCSR_SEIE_MASK, /*!< Sync error flag, means the sync error is detected */
     kSAI_FIFOWarningInterruptEnable = I2S_TCSR_FWIE_MASK, /*!< FIFO warning flag, means the FIFO is empty */
-    kSAI_FIFOErrorInterruptEnable = I2S_TCSR_FEIE_MASK,   /*!< FIFO error flag */
+    kSAI_FIFOErrorInterruptEnable   = I2S_TCSR_FEIE_MASK, /*!< FIFO error flag */
 #if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1)
     kSAI_FIFORequestInterruptEnable = I2S_TCSR_FRIE_MASK, /*!< FIFO request, means reached watermark */
 #endif                                                    /* FSL_FEATURE_SAI_FIFO_COUNT */
@@ -166,9 +166,9 @@ enum _sai_flags
 /*! @brief The reset type */
 typedef enum _sai_reset_type
 {
-    kSAI_ResetTypeSoftware = I2S_TCSR_SR_MASK,          /*!< Software reset, reset the logic state */
-    kSAI_ResetTypeFIFO = I2S_TCSR_FR_MASK,              /*!< FIFO reset, reset the FIFO read and write pointer */
-    kSAI_ResetAll = I2S_TCSR_SR_MASK | I2S_TCSR_FR_MASK /*!< All reset. */
+    kSAI_ResetTypeSoftware = I2S_TCSR_SR_MASK, /*!< Software reset, reset the logic state */
+    kSAI_ResetTypeFIFO     = I2S_TCSR_FR_MASK, /*!< FIFO reset, reset the FIFO read and write pointer */
+    kSAI_ResetAll          = I2S_TCSR_SR_MASK | I2S_TCSR_FR_MASK /*!< All reset. */
 } sai_reset_type_t;
 
 #if defined(FSL_FEATURE_SAI_HAS_FIFO_PACKING) && FSL_FEATURE_SAI_HAS_FIFO_PACKING
@@ -179,8 +179,8 @@ typedef enum _sai_reset_type
 typedef enum _sai_fifo_packing
 {
     kSAI_FifoPackingDisabled = 0x0U, /*!< Packing disabled */
-    kSAI_FifoPacking8bit = 0x2U,     /*!< 8 bit packing enabled */
-    kSAI_FifoPacking16bit = 0x3U     /*!< 16bit packing enabled */
+    kSAI_FifoPacking8bit     = 0x2U, /*!< 8 bit packing enabled */
+    kSAI_FifoPacking16bit    = 0x3U  /*!< 16bit packing enabled */
 } sai_fifo_packing_t;
 #endif /* FSL_FEATURE_SAI_HAS_FIFO_PACKING */
 
@@ -190,56 +190,213 @@ typedef struct _sai_config
     sai_protocol_t protocol;  /*!< Audio bus protocol in SAI */
     sai_sync_mode_t syncMode; /*!< SAI sync mode, control Tx/Rx clock sync */
 #if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR)
-    bool mclkOutputEnable;          /*!< Master clock output enable, true means master clock divider enabled */
-#endif                              /* FSL_FEATURE_SAI_HAS_MCR */
-    sai_mclk_source_t mclkSource;   /*!< Master Clock source */
+    bool mclkOutputEnable; /*!< Master clock output enable, true means master clock divider enabled */
+#if !(defined(FSL_FEATURE_SAI_HAS_NO_MCR_MICS) && (FSL_FEATURE_SAI_HAS_NO_MCR_MICS))
+    sai_mclk_source_t mclkSource; /*!< Master Clock source */
+#endif                            /* FSL_FEATURE_SAI_HAS_MCR */
+#endif
     sai_bclk_source_t bclkSource;   /*!< Bit Clock source */
     sai_master_slave_t masterSlave; /*!< Master or slave */
 } sai_config_t;
 
+#ifndef SAI_XFER_QUEUE_SIZE
 /*!@brief SAI transfer queue size, user can refine it according to use case. */
 #define SAI_XFER_QUEUE_SIZE (4)
+#endif
 
 /*! @brief Audio sample rate */
 typedef enum _sai_sample_rate
 {
-    kSAI_SampleRate8KHz = 8000U,     /*!< Sample rate 8000 Hz */
-    kSAI_SampleRate11025Hz = 11025U, /*!< Sample rate 11025 Hz */
-    kSAI_SampleRate12KHz = 12000U,   /*!< Sample rate 12000 Hz */
-    kSAI_SampleRate16KHz = 16000U,   /*!< Sample rate 16000 Hz */
-    kSAI_SampleRate22050Hz = 22050U, /*!< Sample rate 22050 Hz */
-    kSAI_SampleRate24KHz = 24000U,   /*!< Sample rate 24000 Hz */
-    kSAI_SampleRate32KHz = 32000U,   /*!< Sample rate 32000 Hz */
-    kSAI_SampleRate44100Hz = 44100U, /*!< Sample rate 44100 Hz */
-    kSAI_SampleRate48KHz = 48000U,   /*!< Sample rate 48000 Hz */
-    kSAI_SampleRate96KHz = 96000U    /*!< Sample rate 96000 Hz */
+    kSAI_SampleRate8KHz    = 8000U,   /*!< Sample rate 8000 Hz */
+    kSAI_SampleRate11025Hz = 11025U,  /*!< Sample rate 11025 Hz */
+    kSAI_SampleRate12KHz   = 12000U,  /*!< Sample rate 12000 Hz */
+    kSAI_SampleRate16KHz   = 16000U,  /*!< Sample rate 16000 Hz */
+    kSAI_SampleRate22050Hz = 22050U,  /*!< Sample rate 22050 Hz */
+    kSAI_SampleRate24KHz   = 24000U,  /*!< Sample rate 24000 Hz */
+    kSAI_SampleRate32KHz   = 32000U,  /*!< Sample rate 32000 Hz */
+    kSAI_SampleRate44100Hz = 44100U,  /*!< Sample rate 44100 Hz */
+    kSAI_SampleRate48KHz   = 48000U,  /*!< Sample rate 48000 Hz */
+    kSAI_SampleRate96KHz   = 96000U,  /*!< Sample rate 96000 Hz */
+    kSAI_SampleRate192KHz  = 192000U, /*!< Sample rate 192000 Hz */
+    kSAI_SampleRate384KHz  = 384000U, /*!< Sample rate 384000 Hz */
 } sai_sample_rate_t;
 
 /*! @brief Audio word width */
 typedef enum _sai_word_width
 {
-    kSAI_WordWidth8bits = 8U,   /*!< Audio data width 8 bits */
+    kSAI_WordWidth8bits  = 8U,  /*!< Audio data width 8 bits */
     kSAI_WordWidth16bits = 16U, /*!< Audio data width 16 bits */
     kSAI_WordWidth24bits = 24U, /*!< Audio data width 24 bits */
     kSAI_WordWidth32bits = 32U  /*!< Audio data width 32 bits */
 } sai_word_width_t;
 
+#if defined(FSL_FEATURE_SAI_HAS_CHANNEL_MODE) && FSL_FEATURE_SAI_HAS_CHANNEL_MODE
+/*! @brief sai data pin state definition */
+typedef enum _sai_data_pin_state
+{
+    kSAI_DataPinStateTriState =
+        0U, /*!< transmit data pins are tri-stated when slots are masked or channels are disabled */
+    kSAI_DataPinStateOutputZero = 1U, /*!< transmit data pins are never tri-stated and will output zero when slots
+                                             are masked or channel disabled */
+} sai_data_pin_state_t;
+#endif
+
+#if defined(FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_COMBINE) && FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_COMBINE
+/*! @brief sai fifo combine mode definition */
+typedef enum _sai_fifo_combine
+{
+    kSAI_FifoCombineDisabled = 0U,          /*!< sai fifo combine mode disabled */
+    kSAI_FifoCombineModeEnabledOnRead,      /*!< sai fifo combine mode enabled on FIFO reads */
+    kSAI_FifoCombineModeEnabledOnWrite,     /*!< sai fifo combine mode enabled on FIFO write */
+    kSAI_FifoCombineModeEnabledOnReadWrite, /*!< sai fifo combined mode enabled on FIFO read/writes */
+} sai_fifo_combine_t;
+#endif
+
+/*! @brief sai transceiver type */
+typedef enum _sai_transceiver_type
+{
+    kSAI_Transmitter = 0U, /*!< sai transmitter */
+    kSAI_Receiver    = 1U, /*!< sai receiver */
+} sai_transceiver_type_t;
+
+/*! @brief sai frame sync len */
+typedef enum _sai_frame_sync_len
+{
+    kSAI_FrameSyncLenOneBitClk    = 0U, /*!< 1 bit clock frame sync len for DSP mode */
+    kSAI_FrameSyncLenPerWordWidth = 1U, /*!< Frame sync length decided by word width */
+} sai_frame_sync_len_t;
+
 /*! @brief sai transfer format */
 typedef struct _sai_transfer_format
 {
     uint32_t sampleRate_Hz;   /*!< Sample rate of audio data */
     uint32_t bitWidth;        /*!< Data length of audio data, usually 8/16/24/32 bits */
     sai_mono_stereo_t stereo; /*!< Mono or stereo */
-    uint32_t masterClockHz;   /*!< Master clock frequency in Hz */
+#if defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER)
+    uint32_t masterClockHz; /*!< Master clock frequency in Hz */
+#endif                      /* FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER */
 #if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1)
-    uint8_t watermark;       /*!< Watermark value */
-#endif                       /* FSL_FEATURE_SAI_FIFO_COUNT */
-    uint8_t channel;         /*!< Data channel used in transfer.*/
+    uint8_t watermark; /*!< Watermark value */
+#endif                 /* FSL_FEATURE_SAI_FIFO_COUNT */
+
+    /* for the multi channel usage, user can provide channelMask Oonly, then sai driver will handle
+     * other parameter carefully, such as
+     * channelMask = kSAI_Channel0Mask | kSAI_Channel1Mask | kSAI_Channel4Mask
+     * then in SAI_RxSetFormat/SAI_TxSetFormat function, channel/endChannel/channelNums will be calculated.
+     * for the single channel usage, user can provide channel or channel mask only, such as,
+     * channel = 0 or channelMask = kSAI_Channel0Mask.
+     */
+    uint8_t channel;     /*!< Transfer start channel */
+    uint8_t channelMask; /*!< enabled channel mask value, reference _sai_channel_mask */
+    uint8_t endChannel;  /*!< end channel number */
+    uint8_t channelNums; /*!< Total enabled channel numbers */
+
     sai_protocol_t protocol; /*!< Which audio protocol used */
     bool isFrameSyncCompact; /*!< True means Frame sync length is configurable according to bitWidth, false means frame
                                 sync length is 64 times of bit clock. */
 } sai_transfer_format_t;
 
+#if (defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR)) || \
+    (defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER))
+/*! @brief master clock configurations */
+typedef struct _sai_master_clock
+{
+#if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR)
+    bool mclkOutputEnable; /*!< master clock output enable */
+#if !(defined(FSL_FEATURE_SAI_HAS_NO_MCR_MICS) && (FSL_FEATURE_SAI_HAS_NO_MCR_MICS))
+    sai_mclk_source_t mclkSource; /*!< Master Clock source */
+#endif
+#endif
+
+#if (defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR)) || \
+    (defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER))
+    uint32_t mclkHz;          /*!< target mclk frequency */
+    uint32_t mclkSourceClkHz; /*!< mclk source frequency*/
+#endif
+} sai_master_clock_t;
+#endif
+
+/*! @brief sai fifo configurations */
+typedef struct _sai_fifo
+{
+#if defined(FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR) && FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR
+    bool fifoContinueOneError; /*!< fifo continues when error occur */
+#endif
+
+#if defined(FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_COMBINE) && FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_COMBINE
+    sai_fifo_combine_t fifoCombine; /*!< fifo combine mode */
+#endif
+
+#if defined(FSL_FEATURE_SAI_HAS_FIFO_PACKING) && FSL_FEATURE_SAI_HAS_FIFO_PACKING
+    sai_fifo_packing_t fifoPacking; /*!< fifo packing mode */
+#endif
+#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1)
+    uint8_t fifoWatermark; /*!< fifo watermark */
+#endif
+} sai_fifo_t;
+
+/*! @brief sai bit clock configurations */
+typedef struct _sai_bit_clock
+{
+    bool bclkSrcSwap;    /*!< bit clock source swap */
+    bool bclkInputDelay; /*!< bit clock actually used by the transmitter is delayed by the pad output delay,
+                           this has effect of decreasing the data input setup time, but increasing the data output valid
+                           time .*/
+    sai_clock_polarity_t bclkPolarity; /*!< bit clock polarity */
+    sai_bclk_source_t bclkSource;      /*!< bit Clock source */
+} sai_bit_clock_t;
+
+/*! @brief sai frame sync configurations */
+typedef struct _sai_frame_sync
+{
+    uint8_t frameSyncWidth; /*!< frame sync width in number of bit clocks */
+    bool frameSyncEarly;    /*!< TRUE is frame sync assert one bit before the first bit of frame
+                                FALSE is frame sync assert with the first bit of the frame */
+
+#if defined(FSL_FEATURE_SAI_HAS_FRAME_SYNC_ON_DEMAND) && FSL_FEATURE_SAI_HAS_FRAME_SYNC_ON_DEMAND
+    bool frameSyncGenerateOnDemand; /*!< internal frame sync is generated when FIFO waring flag is clear */
+#endif
+
+    sai_clock_polarity_t frameSyncPolarity; /*!< frame sync polarity */
+
+} sai_frame_sync_t;
+
+/*! @brief sai serial data configurations */
+typedef struct _sai_serial_data
+{
+#if defined(FSL_FEATURE_SAI_HAS_CHANNEL_MODE) && FSL_FEATURE_SAI_HAS_CHANNEL_MODE
+    sai_data_pin_state_t dataMode; /*!< sai data pin state when slots masked or channel disabled */
+#endif
+
+    sai_data_order_t dataOrder; /*!< configure whether the LSB or MSB is transmitted first */
+    uint8_t dataWord0Length;    /*!< configure the number of bits in the first word in each frame */
+    uint8_t dataWordNLength; /*!< configure the number of bits in the each word in each frame, except the first word */
+    uint8_t dataWordLength;  /*!< used to record the data length for dma transfer */
+    uint8_t
+        dataFirstBitShifted; /*!< Configure the bit index for the first bit transmitted for each word in the frame */
+    uint8_t dataWordNum;     /*!< configure the number of words in each frame */
+    uint32_t dataMaskedWord; /*!< configure whether the transmit word is masked */
+} sai_serial_data_t;
+
+/*! @brief sai transceiver configurations */
+typedef struct _sai_transceiver
+{
+    sai_serial_data_t serialData; /*!< serial data configurations */
+    sai_frame_sync_t frameSync;   /*!< ws configurations */
+    sai_bit_clock_t bitClock;     /*!< bit clock configurations */
+    sai_fifo_t fifo;              /*!< fifo configurations */
+
+    sai_master_slave_t masterSlave; /*!< transceiver is master or slave */
+
+    sai_sync_mode_t syncMode; /*!< transceiver sync mode */
+
+    uint8_t startChannel; /*!< Transfer start channel */
+    uint8_t channelMask;  /*!< enabled channel mask value, reference _sai_channel_mask */
+    uint8_t endChannel;   /*!< end channel number */
+    uint8_t channelNums;  /*!< Total enabled channel numbers */
+
+} sai_transceiver_t;
+
 /*! @brief SAI transfer structure */
 typedef struct _sai_transfer
 {
@@ -255,11 +412,25 @@ typedef void (*sai_transfer_callback_t)(I2S_Type *base, sai_handle_t *handle, st
 /*! @brief SAI handle structure */
 struct _sai_handle
 {
-    uint32_t state;                               /*!< Transfer status */
-    sai_transfer_callback_t callback;             /*!< Callback function called at transfer event*/
-    void *userData;                               /*!< Callback parameter passed to callback function*/
-    uint8_t bitWidth;                             /*!< Bit width for transfer, 8/16/24/32 bits */
-    uint8_t channel;                              /*!< Transfer channel */
+    I2S_Type *base; /*!< base address */
+
+    uint32_t state;                   /*!< Transfer status */
+    sai_transfer_callback_t callback; /*!< Callback function called at transfer event*/
+    void *userData;                   /*!< Callback parameter passed to callback function*/
+    uint8_t bitWidth;                 /*!< Bit width for transfer, 8/16/24/32 bits */
+
+    /* for the multi channel usage, user can provide channelMask Oonly, then sai driver will handle
+     * other parameter carefully, such as
+     * channelMask = kSAI_Channel0Mask | kSAI_Channel1Mask | kSAI_Channel4Mask
+     * then in SAI_RxSetFormat/SAI_TxSetFormat function, channel/endChannel/channelNums will be calculated.
+     * for the single channel usage, user can provide channel or channel mask only, such as,
+     * channel = 0 or channelMask = kSAI_Channel0Mask.
+     */
+    uint8_t channel;     /*!< Transfer start channel */
+    uint8_t channelMask; /*!< enabled channel mask value, refernece _sai_channel_mask */
+    uint8_t endChannel;  /*!< end channel number */
+    uint8_t channelNums; /*!< Total enabled channel numbers */
+
     sai_transfer_t saiQueue[SAI_XFER_QUEUE_SIZE]; /*!< Transfer queue storing queued transfer */
     size_t transferSize[SAI_XFER_QUEUE_SIZE];     /*!< Data bytes need to transfer */
     volatile uint8_t queueUser;                   /*!< Index for user to queue transfer */
@@ -284,6 +455,7 @@ extern "C" {
 
 /*!
  * @brief Initializes the SAI Tx peripheral.
+ * @deprecated Do not use this function.  It has been superceded by @ref SAI_Init
  *
  * Ungates the SAI clock, resets the module, and configures SAI Tx with a configuration structure.
  * The configuration structure can be custom filled or set with default values by
@@ -295,11 +467,12 @@ extern "C" {
  *
  * @param base SAI base pointer
  * @param config SAI configuration structure.
-*/
+ */
 void SAI_TxInit(I2S_Type *base, const sai_config_t *config);
 
 /*!
  * @brief Initializes the SAI Rx peripheral.
+ * @deprecated Do not use this function.  It has been superceded by @ref SAI_Init
  *
  * Ungates the SAI clock, resets the module, and configures the SAI Rx with a configuration structure.
  * The configuration structure can be custom filled or set with default values by
@@ -316,6 +489,8 @@ void SAI_RxInit(I2S_Type *base, const sai_config_t *config);
 
 /*!
  * @brief  Sets the SAI Tx configuration structure to default values.
+ * @deprecated Do not use this function.  It has been superceded by @ref
+ * SAI_GetClassicI2SConfig/SAI_GetLeftJustifiedConfig/SAI_GetRightJustifiedConfig/SAI_GetDSPConfig/SAI_GetTDMConfig
  *
  * This API initializes the configuration structure for use in SAI_TxConfig().
  * The initialized structure can remain unchanged in SAI_TxConfig(), or it can be modified
@@ -332,6 +507,8 @@ void SAI_TxGetDefaultConfig(sai_config_t *config);
 
 /*!
  * @brief  Sets the SAI Rx configuration structure to default values.
+ * @deprecated Do not use this function.  It has been superceded by @ref
+ * SAI_GetClassicI2SConfig/SAI_GetLeftJustifiedConfig/SAI_GetRightJustifiedConfig/SAI_GetDSPConfig/SAI_GetTDMConfig
  *
  * This API initializes the configuration structure for use in SAI_RxConfig().
  * The initialized structure can remain unchanged in SAI_RxConfig() or it can be modified
@@ -346,14 +523,23 @@ void SAI_TxGetDefaultConfig(sai_config_t *config);
  */
 void SAI_RxGetDefaultConfig(sai_config_t *config);
 
+/*!
+ * @brief Initializes the SAI peripheral.
+ *
+ * This API gates the SAI clock. The SAI module can't operate unless SAI_Init is called to enable the clock.
+ *
+ * @param base SAI base pointer.
+ */
+void SAI_Init(I2S_Type *base);
+
 /*!
  * @brief De-initializes the SAI peripheral.
  *
  * This API gates the SAI clock. The SAI module can't operate unless SAI_TxInit
  * or SAI_RxInit is called to enable the clock.
  *
- * @param base SAI base pointer
-*/
+ * @param base SAI base pointer.
+ */
 void SAI_Deinit(I2S_Type *base);
 
 /*!
@@ -377,7 +563,7 @@ void SAI_RxReset(I2S_Type *base);
 /*!
  * @brief Enables/disables the SAI Tx.
  *
- * @param base SAI base pointer
+ * @param base SAI base pointer.
  * @param enable True means enable SAI Tx, false means disable.
  */
 void SAI_TxEnable(I2S_Type *base, bool enable);
@@ -385,11 +571,278 @@ void SAI_TxEnable(I2S_Type *base, bool enable);
 /*!
  * @brief Enables/disables the SAI Rx.
  *
- * @param base SAI base pointer
+ * @param base SAI base pointer.
  * @param enable True means enable SAI Rx, false means disable.
  */
 void SAI_RxEnable(I2S_Type *base, bool enable);
 
+/*!
+ * @brief Set Rx bit clock direction.
+ *
+ * Select bit clock direction, master or slave.
+ *
+ * @param base SAI base pointer.
+ * @param masterSlave reference sai_master_slave_t.
+ */
+static inline void SAI_TxSetBitClockDirection(I2S_Type *base, sai_master_slave_t masterSlave)
+{
+    if (masterSlave == kSAI_Master)
+    {
+        base->TCR2 |= I2S_TCR2_BCD_MASK;
+    }
+    else
+    {
+        base->TCR2 &= ~I2S_TCR2_BCD_MASK;
+    }
+}
+
+/*!
+ * @brief Set Rx bit clock direction.
+ *
+ * Select bit clock direction, master or slave.
+ *
+ * @param base SAI base pointer.
+ * @param masterSlave reference sai_master_slave_t.
+ */
+static inline void SAI_RxSetBitClockDirection(I2S_Type *base, sai_master_slave_t masterSlave)
+{
+    if (masterSlave == kSAI_Master)
+    {
+        base->RCR2 |= I2S_RCR2_BCD_MASK;
+    }
+    else
+    {
+        base->RCR2 &= ~I2S_RCR2_BCD_MASK;
+    }
+}
+
+/*!
+ * @brief Set Rx frame sync direction.
+ *
+ * Select frame sync direction, master or slave.
+ *
+ * @param base SAI base pointer.
+ * @param masterSlave reference sai_master_slave_t.
+ */
+static inline void SAI_RxSetFrameSyncDirection(I2S_Type *base, sai_master_slave_t masterSlave)
+{
+    if (masterSlave == kSAI_Master)
+    {
+        base->RCR4 |= I2S_RCR4_FSD_MASK;
+    }
+    else
+    {
+        base->RCR4 &= ~I2S_RCR4_FSD_MASK;
+    }
+}
+
+/*!
+ * @brief Set Tx frame sync direction.
+ *
+ * Select frame sync direction, master or slave.
+ *
+ * @param base SAI base pointer.
+ * @param masterSlave reference sai_master_slave_t.
+ */
+static inline void SAI_TxSetFrameSyncDirection(I2S_Type *base, sai_master_slave_t masterSlave)
+{
+    if (masterSlave == kSAI_Master)
+    {
+        base->TCR4 |= I2S_TCR4_FSD_MASK;
+    }
+    else
+    {
+        base->TCR4 &= ~I2S_TCR4_FSD_MASK;
+    }
+}
+
+/*!
+ * @brief Transmitter bit clock rate configurations.
+ *
+ * @param base SAI base pointer.
+ * @param sourceClockHz, bit clock source frequency.
+ * @param sampleRate audio data sample rate.
+ * @param bitWidth, audio data bitWidth.
+ * @param channelNumbers, audio channel numbers.
+ */
+void SAI_TxSetBitClockRate(
+    I2S_Type *base, uint32_t sourceClockHz, uint32_t sampleRate, uint32_t bitWidth, uint32_t channelNumbers);
+
+/*!
+ * @brief Receiver bit clock rate configurations.
+ *
+ * @param base SAI base pointer.
+ * @param sourceClockHz, bit clock source frequency.
+ * @param sampleRate audio data sample rate.
+ * @param bitWidth, audio data bitWidth.
+ * @param channelNumbers, audio channel numbers.
+ */
+void SAI_RxSetBitClockRate(
+    I2S_Type *base, uint32_t sourceClockHz, uint32_t sampleRate, uint32_t bitWidth, uint32_t channelNumbers);
+
+/*!
+ * @brief Transmitter Bit clock configurations.
+ *
+ * @param base SAI base pointer.
+ * @param masterSlave master or slave.
+ * @param config bit clock other configurations, can be NULL in slave mode.
+ */
+void SAI_TxSetBitclockConfig(I2S_Type *base, sai_master_slave_t masterSlave, sai_bit_clock_t *config);
+
+/*!
+ * @brief Receiver Bit clock configurations.
+ *
+ * @param base SAI base pointer.
+ * @param masterSlave master or slave.
+ * @param config bit clock other configurations, can be NULL in slave mode.
+ */
+void SAI_RxSetBitclockConfig(I2S_Type *base, sai_master_slave_t masterSlave, sai_bit_clock_t *config);
+
+#if (defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR)) || \
+    (defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER))
+/*!
+ * @brief Master clock configurations.
+ *
+ * @param base SAI base pointer.
+ * @param config master clock configurations.
+ */
+void SAI_SetMasterClockConfig(I2S_Type *base, sai_master_clock_t *config);
+#endif
+
+/*!
+ * @brief SAI transmitter fifo configurations.
+ *
+ * @param base SAI base pointer.
+ * @param config fifo configurations.
+ */
+void SAI_TxSetFifoConfig(I2S_Type *base, sai_fifo_t *config);
+
+/*!
+ * @brief SAI receiver fifo configurations.
+ *
+ * @param base SAI base pointer.
+ * @param config fifo configurations.
+ */
+void SAI_RxSetFifoConfig(I2S_Type *base, sai_fifo_t *config);
+
+/*!
+ * @brief SAI transmitter Frame sync configurations.
+ *
+ * @param base SAI base pointer.
+ * @param masterSlave master or slave.
+ * @param config frame sync configurations, can be NULL in slave mode.
+ */
+void SAI_TxSetFrameSyncConfig(I2S_Type *base, sai_master_slave_t masterSlave, sai_frame_sync_t *config);
+
+/*!
+ * @brief SAI receiver Frame sync configurations.
+ *
+ * @param base SAI base pointer.
+ * @param masterSlave master or slave.
+ * @param config frame sync configurations, can be NULL in slave mode.
+ */
+void SAI_RxSetFrameSyncConfig(I2S_Type *base, sai_master_slave_t masterSlave, sai_frame_sync_t *config);
+
+/*!
+ * @brief SAI transmitter Serial data configurations.
+ *
+ * @param base SAI base pointer.
+ * @param config serial data configurations.
+ */
+void SAI_TxSetSerialDataConfig(I2S_Type *base, sai_serial_data_t *config);
+
+/*!
+ * @brief SAI receiver Serial data configurations.
+ *
+ * @param base SAI base pointer.
+ * @param config serial data configurations.
+ */
+void SAI_RxSetSerialDataConfig(I2S_Type *base, sai_serial_data_t *config);
+
+/*!
+ * @brief SAI transmitter configurations.
+ *
+ * @param base SAI base pointer.
+ * @param config transmitter configurations.
+ */
+void SAI_TxSetConfig(I2S_Type *base, sai_transceiver_t *config);
+
+/*!
+ * @brief SAI receiver configurations.
+ *
+ * @param base SAI base pointer.
+ * @param config receiver configurations.
+ */
+void SAI_RxSetConfig(I2S_Type *base, sai_transceiver_t *config);
+
+/*!
+ * @brief Get classic I2S mode configurations.
+ *
+ * @param config transceiver configurations.
+ * @param bitWidth audio data bitWidth.
+ * @param mode audio data channel.
+ * @param saiChannelMask mask value of the channel to be enable.
+ */
+void SAI_GetClassicI2SConfig(sai_transceiver_t *config,
+                             sai_word_width_t bitWidth,
+                             sai_mono_stereo_t mode,
+                             uint32_t saiChannelMask);
+
+/*!
+ * @brief Get left justified mode configurations.
+ *
+ * @param config transceiver configurations.
+ * @param bitWidth audio data bitWidth.
+ * @param mode audio data channel.
+ * @param saiChannelMask mask value of the channel to be enable.
+ */
+void SAI_GetLeftJustifiedConfig(sai_transceiver_t *config,
+                                sai_word_width_t bitWidth,
+                                sai_mono_stereo_t mode,
+                                uint32_t saiChannelMask);
+
+/*!
+ * @brief Get right justified mode configurations.
+ *
+ * @param config transceiver configurations.
+ * @param bitWidth audio data bitWidth.
+ * @param mode audio data channel.
+ * @param saiChannelMask mask value of the channel to be enable.
+ */
+void SAI_GetRightJustifiedConfig(sai_transceiver_t *config,
+                                 sai_word_width_t bitWidth,
+                                 sai_mono_stereo_t mode,
+                                 uint32_t saiChannelMask);
+
+/*!
+ * @brief Get TDM mode configurations.
+ *
+ * @param config transceiver configurations.
+ * @param frameSyncWidth length of frame sync.
+ * @param bitWidth audio data word width.
+ * @param dataWordNum word number in one frame.
+ * @param saiChannelMask mask value of the channel to be enable.
+ */
+void SAI_GetTDMConfig(sai_transceiver_t *config,
+                      sai_frame_sync_len_t frameSyncWidth,
+                      sai_word_width_t bitWidth,
+                      uint32_t dataWordNum,
+                      uint32_t saiChannelMask);
+
+/*!
+ * @brief Get DSP mode configurations.
+ *
+ * @param config transceiver configurations.
+ * @param frameSyncWidth length of frame sync.
+ * @param bitWidth audio data bitWidth.
+ * @param mode audio data channel.
+ * @param saiChannelMask mask value of the channel to enable.
+ */
+void SAI_GetDSPConfig(sai_transceiver_t *config,
+                      sai_frame_sync_len_t frameSyncWidth,
+                      sai_word_width_t bitWidth,
+                      sai_mono_stereo_t mode,
+                      uint32_t saiChannelMask);
 /*! @} */
 
 /*!
@@ -451,7 +904,7 @@ static inline void SAI_RxClearStatusFlags(I2S_Type *base, uint32_t mask)
  * @brief Do software reset or FIFO reset .
  *
  * FIFO reset means clear all the data in the FIFO, and make the FIFO pointer both to 0.
- * Software reset means claer the Tx internal logic, including the bit clock, frame count etc. But software
+ * Software reset means clear the Tx internal logic, including the bit clock, frame count etc. But software
  * reset will not clear any configuration registers like TCR1~TCR5.
  * This function will also clear all the error flags such as FIFO error, sync error etc.
  *
@@ -464,7 +917,7 @@ void SAI_TxSoftwareReset(I2S_Type *base, sai_reset_type_t type);
  * @brief Do software reset or FIFO reset .
  *
  * FIFO reset means clear all the data in the FIFO, and make the FIFO pointer both to 0.
- * Software reset means claer the Rx internal logic, including the bit clock, frame count etc. But software
+ * Software reset means clear the Rx internal logic, including the bit clock, frame count etc. But software
  * reset will not clear any configuration registers like RCR1~RCR5.
  * This function will also clear all the error flags such as FIFO error, sync error etc.
  *
@@ -549,24 +1002,24 @@ void SAI_RxSetFrameSyncPolarity(I2S_Type *base, sai_clock_polarity_t polarity);
 void SAI_TxSetFIFOPacking(I2S_Type *base, sai_fifo_packing_t pack);
 
 /*!
-* @brief Set Rx FIFO packing feature.
-*
-* @param base SAI base pointer.
-* @param pack FIFO pack type. It is element of sai_fifo_packing_t.
-*/
+ * @brief Set Rx FIFO packing feature.
+ *
+ * @param base SAI base pointer.
+ * @param pack FIFO pack type. It is element of sai_fifo_packing_t.
+ */
 void SAI_RxSetFIFOPacking(I2S_Type *base, sai_fifo_packing_t pack);
 #endif /* FSL_FEATURE_SAI_HAS_FIFO_PACKING */
 
 #if defined(FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR) && FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR
 /*!
-* @brief Set Tx FIFO error continue.
-*
-* FIFO error continue mode means SAI will keep running while FIFO error occured. If this feature
-* not enabled, SAI will hang and users need to clear FEF flag in TCSR register.
-*
-* @param base SAI base pointer.
-* @param isEnabled Is FIFO error continue enabled, true means enable, false means disable.
-*/
+ * @brief Set Tx FIFO error continue.
+ *
+ * FIFO error continue mode means SAI will keep running while FIFO error occurred. If this feature
+ * not enabled, SAI will hang and users need to clear FEF flag in TCSR register.
+ *
+ * @param base SAI base pointer.
+ * @param isEnabled Is FIFO error continue enabled, true means enable, false means disable.
+ */
 static inline void SAI_TxSetFIFOErrorContinue(I2S_Type *base, bool isEnabled)
 {
     if (isEnabled)
@@ -580,14 +1033,14 @@ static inline void SAI_TxSetFIFOErrorContinue(I2S_Type *base, bool isEnabled)
 }
 
 /*!
-* @brief Set Rx FIFO error continue.
-*
-* FIFO error continue mode means SAI will keep running while FIFO error occured. If this feature
-* not enabled, SAI will hang and users need to clear FEF flag in RCSR register.
-*
-* @param base SAI base pointer.
-* @param isEnabled Is FIFO error continue enabled, true means enable, false means disable.
-*/
+ * @brief Set Rx FIFO error continue.
+ *
+ * FIFO error continue mode means SAI will keep running while FIFO error occurred. If this feature
+ * not enabled, SAI will hang and users need to clear FEF flag in RCSR register.
+ *
+ * @param base SAI base pointer.
+ * @param isEnabled Is FIFO error continue enabled, true means enable, false means disable.
+ */
 static inline void SAI_RxSetFIFOErrorContinue(I2S_Type *base, bool isEnabled)
 {
     if (isEnabled)
@@ -600,6 +1053,7 @@ static inline void SAI_RxSetFIFOErrorContinue(I2S_Type *base, bool isEnabled)
     }
 }
 #endif
+
 /*! @} */
 
 /*!
@@ -761,6 +1215,7 @@ static inline uint32_t SAI_RxGetDataRegisterAddress(I2S_Type *base, uint32_t cha
 
 /*!
  * @brief Configures the SAI Tx audio format.
+ * @deprecated Do not use this function.  It has been superceded by @ref SAI_TxSetConfig
  *
  * The audio format can be changed at run-time. This function configures the sample rate and audio data
  * format to be transferred.
@@ -770,7 +1225,7 @@ static inline uint32_t SAI_RxGetDataRegisterAddress(I2S_Type *base, uint32_t cha
  * @param mclkSourceClockHz SAI master clock source frequency in Hz.
  * @param bclkSourceClockHz SAI bit clock source frequency in Hz. If the bit clock source is a master
  * clock, this value should equal the masterClockHz.
-*/
+ */
 void SAI_TxSetFormat(I2S_Type *base,
                      sai_transfer_format_t *format,
                      uint32_t mclkSourceClockHz,
@@ -778,6 +1233,7 @@ void SAI_TxSetFormat(I2S_Type *base,
 
 /*!
  * @brief Configures the SAI Rx audio format.
+ * @deprecated Do not use this function.  It has been superceded by @ref SAI_RxSetConfig
  *
  * The audio format can be changed at run-time. This function configures the sample rate and audio data
  * format to be transferred.
@@ -787,7 +1243,7 @@ void SAI_TxSetFormat(I2S_Type *base,
  * @param mclkSourceClockHz SAI master clock source frequency in Hz.
  * @param bclkSourceClockHz SAI bit clock source frequency in Hz. If the bit clock source is a master
  * clock, this value should equal the masterClockHz.
-*/
+ */
 void SAI_RxSetFormat(I2S_Type *base,
                      sai_transfer_format_t *format,
                      uint32_t mclkSourceClockHz,
@@ -806,6 +1262,21 @@ void SAI_RxSetFormat(I2S_Type *base,
  */
 void SAI_WriteBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size);
 
+/*!
+ * @brief Sends data to multi channel using a blocking method.
+ *
+ * @note This function blocks by polling until data is ready to be sent.
+ *
+ * @param base SAI base pointer.
+ * @param channel Data channel used.
+ * @param channelMask channel mask.
+ * @param bitWidth How many bits in an audio word; usually 8/16/24/32 bits.
+ * @param buffer Pointer to the data to be written.
+ * @param size Bytes to be written.
+ */
+void SAI_WriteMultiChannelBlocking(
+    I2S_Type *base, uint32_t channel, uint32_t channelMask, uint32_t bitWidth, uint8_t *buffer, uint32_t size);
+
 /*!
  * @brief Writes data into SAI FIFO.
  *
@@ -831,6 +1302,21 @@ static inline void SAI_WriteData(I2S_Type *base, uint32_t channel, uint32_t data
  */
 void SAI_ReadBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size);
 
+/*!
+ * @brief Receives multi channel data using a blocking method.
+ *
+ * @note This function blocks by polling until data is ready to be sent.
+ *
+ * @param base SAI base pointer.
+ * @param channel Data channel used.
+ * @param channelMask channel mask.
+ * @param bitWidth How many bits in an audio word; usually 8/16/24/32 bits.
+ * @param buffer Pointer to the data to be read.
+ * @param size Bytes to be read.
+ */
+void SAI_ReadMultiChannelBlocking(
+    I2S_Type *base, uint32_t channel, uint32_t channelMask, uint32_t bitWidth, uint8_t *buffer, uint32_t size);
+
 /*!
  * @brief Reads data from the SAI FIFO.
  *
@@ -876,8 +1362,33 @@ void SAI_TransferTxCreateHandle(I2S_Type *base, sai_handle_t *handle, sai_transf
  */
 void SAI_TransferRxCreateHandle(I2S_Type *base, sai_handle_t *handle, sai_transfer_callback_t callback, void *userData);
 
+/*!
+ * @brief SAI transmitter transfer configurations.
+ *
+ * This function initializes the Tx, include bit clock, frame sync, master clock, serial data and fifo
+ * configurations.
+ *
+ * @param base SAI base pointer.
+ * @param handle SAI handle pointer.
+ * @param config tranmitter configurations.
+ */
+void SAI_TransferTxSetConfig(I2S_Type *base, sai_handle_t *handle, sai_transceiver_t *config);
+
+/*!
+ * @brief SAI receiver transfer configurations.
+ *
+ * This function initializes the Rx, include bit clock, frame sync, master clock, serial data and fifo
+ * configurations.
+ *
+ * @param base SAI base pointer.
+ * @param handle SAI handle pointer.
+ * @param config receiver configurations.
+ */
+void SAI_TransferRxSetConfig(I2S_Type *base, sai_handle_t *handle, sai_transceiver_t *config);
+
 /*!
  * @brief Configures the SAI Tx audio format.
+ * @deprecated Do not use this function.  It has been superceded by @ref SAI_TxSetTransferConfig
  *
  * The audio format can be changed at run-time. This function configures the sample rate and audio data
  * format to be transferred.
@@ -889,7 +1400,7 @@ void SAI_TransferRxCreateHandle(I2S_Type *base, sai_handle_t *handle, sai_transf
  * @param bclkSourceClockHz SAI bit clock source frequency in Hz. If a bit clock source is a master
  * clock, this value should equal the masterClockHz in format.
  * @return Status of this function. Return value is the status_t.
-*/
+ */
 status_t SAI_TransferTxSetFormat(I2S_Type *base,
                                  sai_handle_t *handle,
                                  sai_transfer_format_t *format,
@@ -898,6 +1409,7 @@ status_t SAI_TransferTxSetFormat(I2S_Type *base,
 
 /*!
  * @brief Configures the SAI Rx audio format.
+ * @deprecated Do not use this function.  It has been superceded by @ref SAI_RxSetTransferConfig
  *
  * The audio format can be changed at run-time. This function configures the sample rate and audio data
  * format to be transferred.
@@ -909,7 +1421,7 @@ status_t SAI_TransferTxSetFormat(I2S_Type *base,
  * @param bclkSourceClockHz SAI bit clock source frequency in Hz. If a bit clock source is a master
  * clock, this value should equal the masterClockHz in format.
  * @return Status of this function. Return value is one of status_t.
-*/
+ */
 status_t SAI_TransferRxSetFormat(I2S_Type *base,
                                  sai_handle_t *handle,
                                  sai_transfer_format_t *format,
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_sai_edma.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_sai_edma.c
index 11bdae301b7..6fb16e06f20 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_sai_edma.c
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_sai_edma.c
@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
  * All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include "fsl_sai_edma.h"
@@ -94,8 +68,8 @@ static void SAI_TxEDMACallback(edma_handle_t *handle, void *userData, bool done,
 static void SAI_RxEDMACallback(edma_handle_t *handle, void *userData, bool done, uint32_t tcds);
 
 /*******************************************************************************
-* Code
-******************************************************************************/
+ * Code
+ ******************************************************************************/
 static uint32_t SAI_GetInstance(I2S_Type *base)
 {
     uint32_t instance;
@@ -117,9 +91,9 @@ static uint32_t SAI_GetInstance(I2S_Type *base)
 static void SAI_TxEDMACallback(edma_handle_t *handle, void *userData, bool done, uint32_t tcds)
 {
     sai_edma_private_handle_t *privHandle = (sai_edma_private_handle_t *)userData;
-    sai_edma_handle_t *saiHandle = privHandle->handle;
+    sai_edma_handle_t *saiHandle          = privHandle->handle;
 
-    /* If finished a blcok, call the callback function */
+    /* If finished a block, call the callback function */
     memset(&saiHandle->saiQueue[saiHandle->queueDriver], 0, sizeof(sai_transfer_t));
     saiHandle->queueDriver = (saiHandle->queueDriver + 1) % SAI_XFER_QUEUE_SIZE;
     if (saiHandle->callback)
@@ -139,9 +113,9 @@ static void SAI_TxEDMACallback(edma_handle_t *handle, void *userData, bool done,
 static void SAI_RxEDMACallback(edma_handle_t *handle, void *userData, bool done, uint32_t tcds)
 {
     sai_edma_private_handle_t *privHandle = (sai_edma_private_handle_t *)userData;
-    sai_edma_handle_t *saiHandle = privHandle->handle;
+    sai_edma_handle_t *saiHandle          = privHandle->handle;
 
-    /* If finished a blcok, call the callback function */
+    /* If finished a block, call the callback function */
     memset(&saiHandle->saiQueue[saiHandle->queueDriver], 0, sizeof(sai_transfer_t));
     saiHandle->queueDriver = (saiHandle->queueDriver + 1) % SAI_XFER_QUEUE_SIZE;
     if (saiHandle->callback)
@@ -158,6 +132,19 @@ static void SAI_RxEDMACallback(edma_handle_t *handle, void *userData, bool done,
     }
 }
 
+/*!
+ * brief Initializes the SAI eDMA handle.
+ *
+ * This function initializes the SAI master DMA handle, which can be used for other SAI master transactional APIs.
+ * Usually, for a specified SAI instance, call this API once to get the initialized handle.
+ *
+ * param base SAI base pointer.
+ * param handle SAI eDMA handle pointer.
+ * param base SAI peripheral base address.
+ * param callback Pointer to user callback function.
+ * param userData User parameter passed to the callback function.
+ * param dmaHandle eDMA handle pointer, this handle shall be static allocated by users.
+ */
 void SAI_TransferTxCreateHandleEDMA(
     I2S_Type *base, sai_edma_handle_t *handle, sai_edma_callback_t callback, void *userData, edma_handle_t *dmaHandle)
 {
@@ -170,13 +157,13 @@ void SAI_TransferTxCreateHandleEDMA(
 
     /* Set sai base to handle */
     handle->dmaHandle = dmaHandle;
-    handle->callback = callback;
-    handle->userData = userData;
+    handle->callback  = callback;
+    handle->userData  = userData;
 
     /* Set SAI state to idle */
     handle->state = kSAI_Idle;
 
-    s_edmaPrivateHandle[instance][0].base = base;
+    s_edmaPrivateHandle[instance][0].base   = base;
     s_edmaPrivateHandle[instance][0].handle = handle;
 
     /* Need to use scatter gather */
@@ -186,6 +173,19 @@ void SAI_TransferTxCreateHandleEDMA(
     EDMA_SetCallback(dmaHandle, SAI_TxEDMACallback, &s_edmaPrivateHandle[instance][0]);
 }
 
+/*!
+ * brief Initializes the SAI Rx eDMA handle.
+ *
+ * This function initializes the SAI slave DMA handle, which can be used for other SAI master transactional APIs.
+ * Usually, for a specified SAI instance, call this API once to get the initialized handle.
+ *
+ * param base SAI base pointer.
+ * param handle SAI eDMA handle pointer.
+ * param base SAI peripheral base address.
+ * param callback Pointer to user callback function.
+ * param userData User parameter passed to the callback function.
+ * param dmaHandle eDMA handle pointer, this handle shall be static allocated by users.
+ */
 void SAI_TransferRxCreateHandleEDMA(
     I2S_Type *base, sai_edma_handle_t *handle, sai_edma_callback_t callback, void *userData, edma_handle_t *dmaHandle)
 {
@@ -198,13 +198,13 @@ void SAI_TransferRxCreateHandleEDMA(
 
     /* Set sai base to handle */
     handle->dmaHandle = dmaHandle;
-    handle->callback = callback;
-    handle->userData = userData;
+    handle->callback  = callback;
+    handle->userData  = userData;
 
     /* Set SAI state to idle */
     handle->state = kSAI_Idle;
 
-    s_edmaPrivateHandle[instance][1].base = base;
+    s_edmaPrivateHandle[instance][1].base   = base;
     s_edmaPrivateHandle[instance][1].handle = handle;
 
     /* Need to use scatter gather */
@@ -214,6 +214,21 @@ void SAI_TransferRxCreateHandleEDMA(
     EDMA_SetCallback(dmaHandle, SAI_RxEDMACallback, &s_edmaPrivateHandle[instance][1]);
 }
 
+/*!
+ * brief Configures the SAI Tx audio format.
+ *
+ * The audio format can be changed at run-time. This function configures the sample rate and audio data
+ * format to be transferred. This function also sets the eDMA parameter according to formatting requirements.
+ *
+ * param base SAI base pointer.
+ * param handle SAI eDMA handle pointer.
+ * param format Pointer to SAI audio data format structure.
+ * param mclkSourceClockHz SAI master clock source frequency in Hz.
+ * param bclkSourceClockHz SAI bit clock source frequency in Hz. If bit clock source is master
+ * clock, this value should equals to masterClockHz in format.
+ * retval kStatus_Success Audio format set successfully.
+ * retval kStatus_InvalidArgument The input argument is invalid.
+ */
 void SAI_TransferTxSetFormatEDMA(I2S_Type *base,
                                  sai_edma_handle_t *handle,
                                  sai_transfer_format_t *format,
@@ -225,7 +240,7 @@ void SAI_TransferTxSetFormatEDMA(I2S_Type *base,
     /* Configure the audio format to SAI registers */
     SAI_TxSetFormat(base, format, mclkSourceClockHz, bclkSourceClockHz);
 
-    /* Get the tranfer size from format, this should be used in EDMA configuration */
+    /* Get the transfer size from format, this should be used in EDMA configuration */
     if (format->bitWidth == 24U)
     {
         handle->bytesPerFrame = 4U;
@@ -238,7 +253,7 @@ void SAI_TransferTxSetFormatEDMA(I2S_Type *base,
     /* Update the data channel SAI used */
     handle->channel = format->channel;
 
-    /* Clear the channel enable bits unitl do a send/receive */
+    /* Clear the channel enable bits until do a send/receive */
     base->TCR3 &= ~I2S_TCR3_TCE_MASK;
 #if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1)
     handle->count = FSL_FEATURE_SAI_FIFO_COUNT - format->watermark;
@@ -247,6 +262,57 @@ void SAI_TransferTxSetFormatEDMA(I2S_Type *base,
 #endif /* FSL_FEATURE_SAI_FIFO_COUNT */
 }
 
+/*!
+ * @brief Configures the SAI Tx.
+ *
+ *
+ * @param base SAI base pointer.
+ * @param handle SAI eDMA handle pointer.
+ * @param saiConfig sai configurations.
+ */
+void SAI_TransferTxSetConfigEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_transceiver_t *saiConfig)
+{
+    assert(handle && saiConfig);
+
+    /* Configure the audio format to SAI registers */
+    SAI_TxSetConfig(base, saiConfig);
+
+    /* Get the transfer size from format, this should be used in EDMA configuration */
+    if (saiConfig->serialData.dataWordLength == 24U)
+    {
+        handle->bytesPerFrame = 4U;
+    }
+    else
+    {
+        handle->bytesPerFrame = saiConfig->serialData.dataWordLength / 8U;
+    }
+    /* Update the data channel SAI used */
+    handle->channel = saiConfig->startChannel;
+
+    /* Clear the channel enable bits until do a send/receive */
+    base->TCR3 &= ~I2S_TCR3_TCE_MASK;
+#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1)
+    handle->count = FSL_FEATURE_SAI_FIFO_COUNT - saiConfig->fifo.fifoWatermark;
+#else
+    handle->count = 1U;
+#endif /* FSL_FEATURE_SAI_FIFO_COUNT */
+}
+
+/*!
+ * brief Configures the SAI Rx audio format.
+ *
+ * The audio format can be changed at run-time. This function configures the sample rate and audio data
+ * format to be transferred. This function also sets the eDMA parameter according to formatting requirements.
+ *
+ * param base SAI base pointer.
+ * param handle SAI eDMA handle pointer.
+ * param format Pointer to SAI audio data format structure.
+ * param mclkSourceClockHz SAI master clock source frequency in Hz.
+ * param bclkSourceClockHz SAI bit clock source frequency in Hz. If a bit clock source is the master
+ * clock, this value should equal to masterClockHz in format.
+ * retval kStatus_Success Audio format set successfully.
+ * retval kStatus_InvalidArgument The input argument is invalid.
+ */
 void SAI_TransferRxSetFormatEDMA(I2S_Type *base,
                                  sai_edma_handle_t *handle,
                                  sai_transfer_format_t *format,
@@ -258,7 +324,7 @@ void SAI_TransferRxSetFormatEDMA(I2S_Type *base,
     /* Configure the audio format to SAI registers */
     SAI_RxSetFormat(base, format, mclkSourceClockHz, bclkSourceClockHz);
 
-    /* Get the tranfer size from format, this should be used in EDMA configuration */
+    /* Get the transfer size from format, this should be used in EDMA configuration */
     if (format->bitWidth == 24U)
     {
         handle->bytesPerFrame = 4U;
@@ -271,7 +337,7 @@ void SAI_TransferRxSetFormatEDMA(I2S_Type *base,
     /* Update the data channel SAI used */
     handle->channel = format->channel;
 
-    /* Clear the channel enable bits unitl do a send/receive */
+    /* Clear the channel enable bits until do a send/receive */
     base->RCR3 &= ~I2S_RCR3_RCE_MASK;
 #if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1)
     handle->count = format->watermark;
@@ -280,12 +346,62 @@ void SAI_TransferRxSetFormatEDMA(I2S_Type *base,
 #endif /* FSL_FEATURE_SAI_FIFO_COUNT */
 }
 
+/*!
+ * @brief Configures the SAI Rx.
+ *
+ *
+ * @param base SAI base pointer.
+ * @param handle SAI eDMA handle pointer.
+ * @param saiConfig sai configurations.
+ */
+void SAI_TransferRxSetConfigEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_transceiver_t *saiConfig)
+{
+    assert(handle && saiConfig);
+
+    /* Configure the audio format to SAI registers */
+    SAI_RxSetConfig(base, saiConfig);
+
+    /* Get the transfer size from format, this should be used in EDMA configuration */
+    if (saiConfig->serialData.dataWordLength == 24U)
+    {
+        handle->bytesPerFrame = 4U;
+    }
+    else
+    {
+        handle->bytesPerFrame = saiConfig->serialData.dataWordLength / 8U;
+    }
+
+    /* Update the data channel SAI used */
+    handle->channel = saiConfig->startChannel;
+
+    /* Clear the channel enable bits until do a send/receive */
+    base->RCR3 &= ~I2S_RCR3_RCE_MASK;
+#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1)
+    handle->count = saiConfig->fifo.fifoWatermark;
+#else
+    handle->count = 1U;
+#endif /* FSL_FEATURE_SAI_FIFO_COUNT */
+}
+
+/*!
+ * brief Performs a non-blocking SAI transfer using DMA.
+ *
+ * note This interface returns immediately after the transfer initiates. Call
+ * SAI_GetTransferStatus to poll the transfer status and check whether the SAI transfer is finished.
+ *
+ * param base SAI base pointer.
+ * param handle SAI eDMA handle pointer.
+ * param xfer Pointer to the DMA transfer structure.
+ * retval kStatus_Success Start a SAI eDMA send successfully.
+ * retval kStatus_InvalidArgument The input argument is invalid.
+ * retval kStatus_TxBusy SAI is busy sending data.
+ */
 status_t SAI_TransferSendEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_transfer_t *xfer)
 {
     assert(handle && xfer);
 
     edma_transfer_config_t config = {0};
-    uint32_t destAddr = SAI_TxGetDataRegisterAddress(base, handle->channel);
+    uint32_t destAddr             = SAI_TxGetDataRegisterAddress(base, handle->channel);
 
     /* Check if input parameter invalid */
     if ((xfer->data == NULL) || (xfer->dataSize == 0U))
@@ -302,10 +418,10 @@ status_t SAI_TransferSendEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_tra
     handle->state = kSAI_Busy;
 
     /* Update the queue state */
-    handle->transferSize[handle->queueUser] = xfer->dataSize;
-    handle->saiQueue[handle->queueUser].data = xfer->data;
+    handle->transferSize[handle->queueUser]      = xfer->dataSize;
+    handle->saiQueue[handle->queueUser].data     = xfer->data;
     handle->saiQueue[handle->queueUser].dataSize = xfer->dataSize;
-    handle->queueUser = (handle->queueUser + 1) % SAI_XFER_QUEUE_SIZE;
+    handle->queueUser                            = (handle->queueUser + 1) % SAI_XFER_QUEUE_SIZE;
 
     /* Prepare edma configure */
     EDMA_PrepareTransfer(&config, xfer->data, handle->bytesPerFrame, (void *)destAddr, handle->bytesPerFrame,
@@ -331,12 +447,25 @@ status_t SAI_TransferSendEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_tra
     return kStatus_Success;
 }
 
+/*!
+ * brief Performs a non-blocking SAI receive using eDMA.
+ *
+ * note This interface returns immediately after the transfer initiates. Call
+ * the SAI_GetReceiveRemainingBytes to poll the transfer status and check whether the SAI transfer is finished.
+ *
+ * param base SAI base pointer
+ * param handle SAI eDMA handle pointer.
+ * param xfer Pointer to DMA transfer structure.
+ * retval kStatus_Success Start a SAI eDMA receive successfully.
+ * retval kStatus_InvalidArgument The input argument is invalid.
+ * retval kStatus_RxBusy SAI is busy receiving data.
+ */
 status_t SAI_TransferReceiveEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_transfer_t *xfer)
 {
     assert(handle && xfer);
 
     edma_transfer_config_t config = {0};
-    uint32_t srcAddr = SAI_RxGetDataRegisterAddress(base, handle->channel);
+    uint32_t srcAddr              = SAI_RxGetDataRegisterAddress(base, handle->channel);
 
     /* Check if input parameter invalid */
     if ((xfer->data == NULL) || (xfer->dataSize == 0U))
@@ -353,10 +482,10 @@ status_t SAI_TransferReceiveEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_
     handle->state = kSAI_Busy;
 
     /* Update queue state  */
-    handle->transferSize[handle->queueUser] = xfer->dataSize;
-    handle->saiQueue[handle->queueUser].data = xfer->data;
+    handle->transferSize[handle->queueUser]      = xfer->dataSize;
+    handle->saiQueue[handle->queueUser].data     = xfer->data;
     handle->saiQueue[handle->queueUser].dataSize = xfer->dataSize;
-    handle->queueUser = (handle->queueUser + 1) % SAI_XFER_QUEUE_SIZE;
+    handle->queueUser                            = (handle->queueUser + 1) % SAI_XFER_QUEUE_SIZE;
 
     /* Prepare edma configure */
     EDMA_PrepareTransfer(&config, (void *)srcAddr, handle->bytesPerFrame, xfer->data, handle->bytesPerFrame,
@@ -382,6 +511,15 @@ status_t SAI_TransferReceiveEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_
     return kStatus_Success;
 }
 
+/*!
+ * brief Aborts a SAI transfer using eDMA.
+ *
+ * This function only aborts the current transfer slots, the other transfer slots' information still kept
+ * in the handler. If users want to terminate all transfer slots, just call SAI_TransferTerminateSendEDMA.
+ *
+ * param base SAI base pointer.
+ * param handle SAI eDMA handle pointer.
+ */
 void SAI_TransferAbortSendEDMA(I2S_Type *base, sai_edma_handle_t *handle)
 {
     assert(handle);
@@ -410,6 +548,15 @@ void SAI_TransferAbortSendEDMA(I2S_Type *base, sai_edma_handle_t *handle)
     handle->state = kSAI_Idle;
 }
 
+/*!
+ * brief Aborts a SAI receive using eDMA.
+ *
+ * This function only aborts the current transfer slots, the other transfer slots' information still kept
+ * in the handler. If users want to terminate all transfer slots, just call SAI_TransferTerminateReceiveEDMA.
+ *
+ * param base SAI base pointer
+ * param handle SAI eDMA handle pointer.
+ */
 void SAI_TransferAbortReceiveEDMA(I2S_Type *base, sai_edma_handle_t *handle)
 {
     assert(handle);
@@ -438,6 +585,15 @@ void SAI_TransferAbortReceiveEDMA(I2S_Type *base, sai_edma_handle_t *handle)
     handle->state = kSAI_Idle;
 }
 
+/*!
+ * brief Terminate all SAI send.
+ *
+ * This function will clear all transfer slots buffered in the sai queue. If users only want to abort the
+ * current transfer slot, please call SAI_TransferAbortSendEDMA.
+ *
+ * param base SAI base pointer.
+ * param handle SAI eDMA handle pointer.
+ */
 void SAI_TransferTerminateSendEDMA(I2S_Type *base, sai_edma_handle_t *handle)
 {
     assert(handle);
@@ -449,10 +605,19 @@ void SAI_TransferTerminateSendEDMA(I2S_Type *base, sai_edma_handle_t *handle)
     memset(handle->tcd, 0U, sizeof(handle->tcd));
     memset(handle->saiQueue, 0U, sizeof(handle->saiQueue));
     memset(handle->transferSize, 0U, sizeof(handle->transferSize));
-    handle->queueUser = 0U;
+    handle->queueUser   = 0U;
     handle->queueDriver = 0U;
 }
 
+/*!
+ * brief Terminate all SAI receive.
+ *
+ * This function will clear all transfer slots buffered in the sai queue. If users only want to abort the
+ * current transfer slot, please call SAI_TransferAbortReceiveEDMA.
+ *
+ * param base SAI base pointer.
+ * param handle SAI eDMA handle pointer.
+ */
 void SAI_TransferTerminateReceiveEDMA(I2S_Type *base, sai_edma_handle_t *handle)
 {
     assert(handle);
@@ -464,10 +629,19 @@ void SAI_TransferTerminateReceiveEDMA(I2S_Type *base, sai_edma_handle_t *handle)
     memset(handle->tcd, 0U, sizeof(handle->tcd));
     memset(handle->saiQueue, 0U, sizeof(handle->saiQueue));
     memset(handle->transferSize, 0U, sizeof(handle->transferSize));
-    handle->queueUser = 0U;
+    handle->queueUser   = 0U;
     handle->queueDriver = 0U;
 }
 
+/*!
+ * brief Gets byte count sent by SAI.
+ *
+ * param base SAI base pointer.
+ * param handle SAI eDMA handle pointer.
+ * param count Bytes count sent by SAI.
+ * retval kStatus_Success Succeed get the transfer count.
+ * retval kStatus_NoTransferInProgress There is no non-blocking transaction in progress.
+ */
 status_t SAI_TransferGetSendCountEDMA(I2S_Type *base, sai_edma_handle_t *handle, size_t *count)
 {
     assert(handle);
@@ -488,6 +662,15 @@ status_t SAI_TransferGetSendCountEDMA(I2S_Type *base, sai_edma_handle_t *handle,
     return status;
 }
 
+/*!
+ * brief Gets byte count received by SAI.
+ *
+ * param base SAI base pointer
+ * param handle SAI eDMA handle pointer.
+ * param count Bytes count received by SAI.
+ * retval kStatus_Success Succeed get the transfer count.
+ * retval kStatus_NoTransferInProgress There is no non-blocking transaction in progress.
+ */
 status_t SAI_TransferGetReceiveCountEDMA(I2S_Type *base, sai_edma_handle_t *handle, size_t *count)
 {
     assert(handle);
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_sai_edma.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_sai_edma.h
index 0b806d246bb..71305fd4485 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_sai_edma.h
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_sai_edma.h
@@ -1,41 +1,15 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
  * All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 #ifndef _FSL_SAI_EDMA_H_
 #define _FSL_SAI_EDMA_H_
 
-#include "fsl_sai.h"
 #include "fsl_edma.h"
+#include "fsl_sai.h"
 
 /*!
  * @addtogroup sai_edma
@@ -48,7 +22,7 @@
 
 /*! @name Driver version */
 /*@{*/
-#define FSL_SAI_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 1, 4)) /*!< Version 2.1.4 */
+#define FSL_SAI_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 2, 0)) /*!< Version 2.2.0 */
 /*@}*/
 
 typedef struct _sai_edma_handle sai_edma_handle_t;
@@ -132,7 +106,7 @@ void SAI_TransferRxCreateHandleEDMA(
  * clock, this value should equals to masterClockHz in format.
  * @retval kStatus_Success Audio format set successfully.
  * @retval kStatus_InvalidArgument The input argument is invalid.
-*/
+ */
 void SAI_TransferTxSetFormatEDMA(I2S_Type *base,
                                  sai_edma_handle_t *handle,
                                  sai_transfer_format_t *format,
@@ -153,13 +127,33 @@ void SAI_TransferTxSetFormatEDMA(I2S_Type *base,
  * clock, this value should equal to masterClockHz in format.
  * @retval kStatus_Success Audio format set successfully.
  * @retval kStatus_InvalidArgument The input argument is invalid.
-*/
+ */
 void SAI_TransferRxSetFormatEDMA(I2S_Type *base,
                                  sai_edma_handle_t *handle,
                                  sai_transfer_format_t *format,
                                  uint32_t mclkSourceClockHz,
                                  uint32_t bclkSourceClockHz);
 
+/*!
+ * @brief Configures the SAI Tx.
+ *
+ *
+ * @param base SAI base pointer.
+ * @param handle SAI eDMA handle pointer.
+ * @param saiConfig sai configurations.
+ */
+void SAI_TransferTxSetConfigEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_transceiver_t *saiConfig);
+
+/*!
+ * @brief Configures the SAI Rx.
+ *
+ *
+ * @param base SAI base pointer.
+ * @param handle SAI eDMA handle pointer.
+ * @param saiConfig sai configurations.
+ */
+void SAI_TransferRxSetConfigEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_transceiver_t *saiConfig);
+
 /*!
  * @brief Performs a non-blocking SAI transfer using DMA.
  *
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_semc.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_semc.c
index 31dbe764958..68a517c3eb6 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_semc.c
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_semc.c
@@ -1,34 +1,8 @@
 /*
- * The Clear BSD License
- * Copyright 2017 NXP
+ * Copyright 2017-2018 NXP
  * All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include "fsl_semc.h"
@@ -42,7 +16,6 @@
 #define FSL_COMPONENT_ID "platform.drivers.semc"
 #endif
 
-
 /*! @brief Define macros for SEMC driver. */
 #define SEMC_IPCOMMANDDATASIZEBYTEMAX (4U)
 #define SEMC_IPCOMMANDMAGICKEY (0xA55A)
@@ -125,7 +98,7 @@ static status_t SEMC_IsIPCommandDone(SEMC_Type *base);
 
 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
 /*! @brief Pointers to SEMC clocks for each instance. */
-static const clock_ip_name_t s_semcClock[FSL_FEATURE_SOC_SEMC_COUNT] = SEMC_CLOCKS;
+static const clock_ip_name_t s_semcClock[FSL_FEATURE_SOC_SEMC_COUNT]    = SEMC_CLOCKS;
 static const clock_ip_name_t s_semcExtClock[FSL_FEATURE_SOC_SEMC_COUNT] = SEMC_EXSC_CLOCKS;
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
@@ -163,7 +136,7 @@ static status_t SEMC_CovertMemorySize(SEMC_Type *base, uint32_t size_kbytes, uin
     }
 
     *sizeConverted = 0;
-    memsize = size_kbytes / 8;
+    memsize        = size_kbytes / 8;
     while (memsize)
     {
         memsize >>= 1;
@@ -242,36 +215,54 @@ static status_t SEMC_IsIPCommandDone(SEMC_Type *base)
     return kStatus_Success;
 }
 
+/*!
+ * brief Gets the SEMC default basic configuration structure.
+ *
+ * The purpose of this API is to get the default SEMC
+ * configure structure for SEMC_Init(). User may use the initialized
+ * structure unchanged in SEMC_Init(), or modify some fields of the
+ * structure before calling SEMC_Init().
+ * Example:
+   code
+   semc_config_t config;
+   SEMC_GetDefaultConfig(&config);
+   endcode
+ * param config The SEMC configuration structure pointer.
+ */
 void SEMC_GetDefaultConfig(semc_config_t *config)
 {
     assert(config);
 
-    semc_axi_queueweight_t queueWeight; /*!< AXI queue weight. */
-    semc_queuea_weight_t queueaWeight;
-    semc_queueb_weight_t queuebWeight;
+    /* Initializes the configure structure to zero. */
+    memset(config, 0, sizeof(*config));
+
+    semc_queuea_weight_struct_t *queueaWeight = &(config->queueWeight.queueaWeight.queueaConfig);
+    semc_queueb_weight_struct_t *queuebWeight = &(config->queueWeight.queuebWeight.queuebConfig);
 
     /* Get default settings. */
-    config->dqsMode = kSEMC_Loopbackinternal;
+    config->dqsMode          = kSEMC_Loopbackinternal;
     config->cmdTimeoutCycles = 0;
     config->busTimeoutCycles = 0x1F;
 
-    /* Set a typical weight settings. */
-    memset((void *)&queueWeight, 0, sizeof(semc_axi_queueweight_t));
-
-    queueaWeight.qos = SEMC_BMCR0_TYPICAL_WQOS;
-    queueaWeight.aging = SEMC_BMCR0_TYPICAL_WAGE;
-    queueaWeight.slaveHitSwith = SEMC_BMCR0_TYPICAL_WSH;
-    queueaWeight.slaveHitNoswitch = SEMC_BMCR0_TYPICAL_WRWS;
-    queuebWeight.qos = SEMC_BMCR1_TYPICAL_WQOS;
-    queuebWeight.aging = SEMC_BMCR1_TYPICAL_WAGE;
-    queuebWeight.slaveHitSwith = SEMC_BMCR1_TYPICAL_WRWS;
-    queuebWeight.weightPagehit = SEMC_BMCR1_TYPICAL_WPH;
-    queuebWeight.bankRotation = SEMC_BMCR1_TYPICAL_WBR;
-
-    config->queueWeight.queueaWeight = &queueaWeight;
-    config->queueWeight.queuebWeight = &queuebWeight;
+    queueaWeight->qos              = SEMC_BMCR0_TYPICAL_WQOS;
+    queueaWeight->aging            = SEMC_BMCR0_TYPICAL_WAGE;
+    queueaWeight->slaveHitSwith    = SEMC_BMCR0_TYPICAL_WSH;
+    queueaWeight->slaveHitNoswitch = SEMC_BMCR0_TYPICAL_WRWS;
+    queuebWeight->qos              = SEMC_BMCR1_TYPICAL_WQOS;
+    queuebWeight->aging            = SEMC_BMCR1_TYPICAL_WAGE;
+    queuebWeight->slaveHitSwith    = SEMC_BMCR1_TYPICAL_WRWS;
+    queuebWeight->weightPagehit    = SEMC_BMCR1_TYPICAL_WPH;
+    queuebWeight->bankRotation     = SEMC_BMCR1_TYPICAL_WBR;
 }
 
+/*!
+ * brief Initializes SEMC.
+ * This function ungates the SEMC clock and initializes SEMC.
+ * This function must be called before calling any other SEMC driver functions.
+ *
+ * param base SEMC peripheral base address.
+ * param configure The SEMC configuration structure pointer.
+ */
 void SEMC_Init(SEMC_Type *base, semc_config_t *configure)
 {
     assert(configure);
@@ -301,18 +292,20 @@ void SEMC_Init(SEMC_Type *base, semc_config_t *configure)
                  SEMC_MCR_CTO(configure->cmdTimeoutCycles) | SEMC_MCR_DQSMD(configure->dqsMode);
 
     /* Configure Queue 0/1 for AXI bus. */
-    if (configure->queueWeight.queueaWeight)
-    {
-        base->BMCR0 = (uint32_t)(configure->queueWeight.queueaWeight);
-    }
-    if (configure->queueWeight.queuebWeight)
-    {
-        base->BMCR1 = (uint32_t)(configure->queueWeight.queuebWeight);
-    }
+    base->BMCR0 = (uint32_t)(configure->queueWeight.queueaWeight.queueaValue);
+    base->BMCR1 = (uint32_t)(configure->queueWeight.queuebWeight.queuebValue);
+
     /* Enable SEMC. */
     base->MCR &= ~SEMC_MCR_MDIS_MASK;
 }
 
+/*!
+ * brief Deinitializes the SEMC module and gates the clock.
+ * This function gates the SEMC clock. As a result, the SEMC
+ * module doesn't work after calling this function.
+ *
+ * param base SEMC peripheral base address.
+ */
 void SEMC_Deinit(SEMC_Type *base)
 {
     /* Disable module.  Check there is no pending command before disable module.  */
@@ -330,6 +323,14 @@ void SEMC_Deinit(SEMC_Type *base)
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }
 
+/*!
+ * brief Configures SDRAM controller in SEMC.
+ *
+ * param base SEMC peripheral base address.
+ * param cs The chip selection.
+ * param config The sdram configuration.
+ * param clkSrc_Hz The SEMC clock frequency.
+ */
 status_t SEMC_ConfigureSDRAM(SEMC_Type *base, semc_sdram_cs_t cs, semc_sdram_config_t *config, uint32_t clkSrc_Hz)
 {
     assert(config);
@@ -337,7 +338,7 @@ status_t SEMC_ConfigureSDRAM(SEMC_Type *base, semc_sdram_cs_t cs, semc_sdram_con
     assert(config->refreshBurstLen);
 
     uint8_t memsize;
-    status_t result = kStatus_Success;
+    status_t result   = kStatus_Success;
     uint16_t prescale = config->tPrescalePeriod_Ns / 16 / (1000000000 / clkSrc_Hz);
     uint16_t refresh;
     uint16_t urgentRef;
@@ -359,9 +360,9 @@ status_t SEMC_ConfigureSDRAM(SEMC_Type *base, semc_sdram_cs_t cs, semc_sdram_con
         return kStatus_SEMC_InvalidTimerSetting;
     }
 
-    refresh = config->refreshPeriod_nsPerRow / config->tPrescalePeriod_Ns;
+    refresh   = config->refreshPeriod_nsPerRow / config->tPrescalePeriod_Ns;
     urgentRef = config->refreshUrgThreshold / config->tPrescalePeriod_Ns;
-    idle = config->tIdleTimeout_Ns / config->tPrescalePeriod_Ns;
+    idle      = config->tIdleTimeout_Ns / config->tPrescalePeriod_Ns;
 
     uint32_t iocReg = base->IOCR & ~(SEMC_IOCR_PINMUXBITWIDTH << config->csxPinMux);
 
@@ -372,7 +373,7 @@ status_t SEMC_ConfigureSDRAM(SEMC_Type *base, semc_sdram_cs_t cs, semc_sdram_con
         return result;
     }
 
-    base->BR[cs] = (config->address & SEMC_BR_BA_MASK) | SEMC_BR_MS(memsize) | SEMC_BR_VLD_MASK;
+    base->BR[cs]   = (config->address & SEMC_BR_BA_MASK) | SEMC_BR_MS(memsize) | SEMC_BR_VLD_MASK;
     base->SDRAMCR0 = SEMC_SDRAMCR0_PS(config->portSize) | SEMC_SDRAMCR0_BL(config->burstLen) |
                      SEMC_SDRAMCR0_COL(config->columnAddrBitNum) | SEMC_SDRAMCR0_CL(config->casLatency);
     /* IOMUX setting. */
@@ -419,7 +420,7 @@ status_t SEMC_ConfigureSDRAM(SEMC_Type *base, semc_sdram_cs_t cs, semc_sdram_con
         return result;
     }
     /* Mode setting value. */
-    mode = (uint16_t)config->burstLen | (uint16_t)(config->casLatency << SEMC_SDRAM_MODESETCAL_OFFSET);
+    mode   = (uint16_t)config->burstLen | (uint16_t)(config->casLatency << SEMC_SDRAM_MODESETCAL_OFFSET);
     result = SEMC_SendIPCommand(base, kSEMC_MemType_SDRAM, config->address, kSEMC_SDRAMCM_Modeset, mode, NULL);
     if (result != kStatus_Success)
     {
@@ -431,6 +432,13 @@ status_t SEMC_ConfigureSDRAM(SEMC_Type *base, semc_sdram_cs_t cs, semc_sdram_con
     return kStatus_Success;
 }
 
+/*!
+ * brief Configures NAND controller in SEMC.
+ *
+ * param base SEMC peripheral base address.
+ * param config The nand configuration.
+ * param clkSrc_Hz The SEMC clock frequency.
+ */
 status_t SEMC_ConfigureNAND(SEMC_Type *base, semc_nand_config_t *config, uint32_t clkSrc_Hz)
 {
     assert(config);
@@ -505,6 +513,13 @@ status_t SEMC_ConfigureNAND(SEMC_Type *base, semc_nand_config_t *config, uint32_
     return kStatus_Success;
 }
 
+/*!
+ * brief Configures NOR controller in SEMC.
+ *
+ * param base SEMC peripheral base address.
+ * param config The nor configuration.
+ * param clkSrc_Hz The SEMC clock frequency.
+ */
 status_t SEMC_ConfigureNOR(SEMC_Type *base, semc_nor_config_t *config, uint32_t clkSrc_Hz)
 {
     assert(config);
@@ -518,7 +533,7 @@ status_t SEMC_ConfigureNOR(SEMC_Type *base, semc_nor_config_t *config, uint32_t
     }
 
     uint32_t iocReg = base->IOCR & ~(SEMC_IOCR_PINMUXBITWIDTH << config->cePinMux);
-    uint32_t muxCe = (config->cePinMux == kSEMC_MUXRDY) ?
+    uint32_t muxCe  = (config->cePinMux == kSEMC_MUXRDY) ?
                          SEMC_IOCR_NOR_CE - 1 :
                          ((config->cePinMux == kSEMC_MUXA8) ? SEMC_IOCR_NOR_CE_A8 : SEMC_IOCR_NOR_CE);
 
@@ -594,7 +609,7 @@ status_t SEMC_ConfigureNOR(SEMC_Type *base, semc_nor_config_t *config, uint32_t
     {
         return result;
     }
-    base->BR[5] = (config->address & SEMC_BR_BA_MASK) | SEMC_BR_MS(memsize) | SEMC_BR_VLD_MASK;
+    base->BR[5]  = (config->address & SEMC_BR_BA_MASK) | SEMC_BR_MS(memsize) | SEMC_BR_VLD_MASK;
     base->NORCR0 = SEMC_NORCR0_PS(config->portSize) | SEMC_NORCR0_BL(config->burstLen) |
                    SEMC_NORCR0_AM(config->addrMode) | SEMC_NORCR0_ADVP(config->advActivePolarity) |
                    SEMC_NORCR0_COL(config->columnAddrBitNum);
@@ -608,16 +623,28 @@ status_t SEMC_ConfigureNOR(SEMC_Type *base, semc_nor_config_t *config, uint32_t
                    SEMC_NORCR1_WEH(SEMC_ConvertTiming(config->tWeHigh_Ns, clkSrc_Hz)) |
                    SEMC_NORCR1_REL(SEMC_ConvertTiming(config->tReLow_Ns, clkSrc_Hz)) |
                    SEMC_NORCR1_REH(SEMC_ConvertTiming(config->tReHigh_Ns, clkSrc_Hz));
-    base->NORCR2 = SEMC_NORCR2_WDS(SEMC_ConvertTiming(config->tWriteSetup_Ns, clkSrc_Hz)) |
-                   SEMC_NORCR2_WDH(SEMC_ConvertTiming(config->tWriteHold_Ns, clkSrc_Hz)) |
-                   SEMC_NORCR2_TA(SEMC_ConvertTiming(config->tTurnAround_Ns, clkSrc_Hz)) |
-                   SEMC_NORCR2_AWDH(SEMC_ConvertTiming(config->tAddr2WriteHold_Ns, clkSrc_Hz) + 1) |
-                   SEMC_NORCR2_LC(config->latencyCount) | SEMC_NORCR2_RD(config->readCycle) |
-                   SEMC_NORCR2_CEITV(SEMC_ConvertTiming(config->tCeInterval_Ns, clkSrc_Hz));
+    base->NORCR2 =
+#if defined(FSL_FEATURE_SEMC_HAS_NOR_WDS_TIME) && (FSL_FEATURE_SEMC_HAS_NOR_WDS_TIME)
+        SEMC_NORCR2_WDS(SEMC_ConvertTiming(config->tWriteSetup_Ns, clkSrc_Hz)) |
+#endif /* FSL_FEATURE_SEMC_HAS_NOR_WDS_TIME */
+#if defined(FSL_FEATURE_SEMC_HAS_NOR_WDH_TIME) && (FSL_FEATURE_SEMC_HAS_NOR_WDH_TIME)
+        SEMC_NORCR2_WDH(SEMC_ConvertTiming(config->tWriteHold_Ns, clkSrc_Hz)) |
+#endif /* FSL_FEATURE_SEMC_HAS_NOR_WDH_TIME */
+        SEMC_NORCR2_TA(SEMC_ConvertTiming(config->tTurnAround_Ns, clkSrc_Hz)) |
+        SEMC_NORCR2_AWDH(SEMC_ConvertTiming(config->tAddr2WriteHold_Ns, clkSrc_Hz) + 1) |
+        SEMC_NORCR2_LC(config->latencyCount) | SEMC_NORCR2_RD(config->readCycle) |
+        SEMC_NORCR2_CEITV(SEMC_ConvertTiming(config->tCeInterval_Ns, clkSrc_Hz));
 
     return SEMC_ConfigureIPCommand(base, (config->portSize + 1));
 }
 
+/*!
+ * brief Configures SRAM controller in SEMC.
+ *
+ * param base SEMC peripheral base address.
+ * param config The sram configuration.
+ * param clkSrc_Hz The SEMC clock frequency.
+ */
 status_t SEMC_ConfigureSRAM(SEMC_Type *base, semc_sram_config_t *config, uint32_t clkSrc_Hz)
 {
     assert(config);
@@ -631,7 +658,7 @@ status_t SEMC_ConfigureSRAM(SEMC_Type *base, semc_sram_config_t *config, uint32_
     }
 
     uint32_t iocReg = base->IOCR & ~(SEMC_IOCR_PINMUXBITWIDTH << config->cePinMux);
-    uint32_t muxCe = (config->cePinMux == kSEMC_MUXRDY) ?
+    uint32_t muxCe  = (config->cePinMux == kSEMC_MUXRDY) ?
                          SEMC_IOCR_PSRAM_CE - 1 :
                          ((config->cePinMux == kSEMC_MUXA8) ? SEMC_IOCR_PSRAM_CE_A8 : SEMC_IOCR_PSRAM_CE);
 
@@ -699,7 +726,7 @@ status_t SEMC_ConfigureSRAM(SEMC_Type *base, semc_sram_config_t *config, uint32_
     {
         return result;
     }
-    base->BR[6] = (config->address & SEMC_BR_BA_MASK) | SEMC_BR_MS(memsize) | SEMC_BR_VLD_MASK;
+    base->BR[6]   = (config->address & SEMC_BR_BA_MASK) | SEMC_BR_MS(memsize) | SEMC_BR_VLD_MASK;
     base->SRAMCR0 = SEMC_SRAMCR0_PS(config->portSize) | SEMC_SRAMCR0_BL(config->burstLen) |
                     SEMC_SRAMCR0_AM(config->addrMode) | SEMC_SRAMCR0_ADVP(config->advActivePolarity) |
                     SEMC_SRAMCR0_COL_MASK;
@@ -724,6 +751,13 @@ status_t SEMC_ConfigureSRAM(SEMC_Type *base, semc_sram_config_t *config, uint32_
     return result;
 }
 
+/*!
+ * brief Configures DBI controller in SEMC.
+ *
+ * param base SEMC peripheral base address.
+ * param config The dbi configuration.
+ * param clkSrc_Hz The SEMC clock frequency.
+ */
 status_t SEMC_ConfigureDBI(SEMC_Type *base, semc_dbi_config_t *config, uint32_t clkSrc_Hz)
 {
     assert(config);
@@ -754,21 +788,35 @@ status_t SEMC_ConfigureDBI(SEMC_Type *base, semc_dbi_config_t *config, uint32_t
         SEMC_DBICR0_PS(config->portSize) | SEMC_DBICR0_BL(config->burstLen) | SEMC_DBICR0_COL(config->columnAddrBitNum);
 
     /* Timing setting. */
-    base->DBICR1 = SEMC_DBICR1_CES(SEMC_ConvertTiming(config->tCsxSetup_Ns, clkSrc_Hz)) |
-                   SEMC_DBICR1_CEH(SEMC_ConvertTiming(config->tCsxHold_Ns, clkSrc_Hz)) |
-                   SEMC_DBICR1_WEL(SEMC_ConvertTiming(config->tWexLow_Ns, clkSrc_Hz)) |
-                   SEMC_DBICR1_WEH(SEMC_ConvertTiming(config->tWexHigh_Ns, clkSrc_Hz)) |
-                   SEMC_DBICR1_REL(SEMC_ConvertTiming(config->tRdxLow_Ns, clkSrc_Hz)) |
-                   SEMC_DBICR1_REH(SEMC_ConvertTiming(config->tRdxHigh_Ns, clkSrc_Hz)) |
-                   SEMC_DBICR1_CEITV(SEMC_ConvertTiming(config->tCsxInterval_Ns, clkSrc_Hz));
+    base->DBICR1 = SEMC_DBICR1_CES(SEMC_ConvertTiming(config->tCsxSetup_Ns, clkSrc_Hz) - 1) |
+                   SEMC_DBICR1_CEH(SEMC_ConvertTiming(config->tCsxHold_Ns, clkSrc_Hz) - 1) |
+                   SEMC_DBICR1_WEL(SEMC_ConvertTiming(config->tWexLow_Ns, clkSrc_Hz) - 1) |
+                   SEMC_DBICR1_WEH(SEMC_ConvertTiming(config->tWexHigh_Ns, clkSrc_Hz) - 1) |
+                   SEMC_DBICR1_REL(SEMC_ConvertTiming(config->tRdxLow_Ns, clkSrc_Hz) - 1) |
+                   SEMC_DBICR1_REH(SEMC_ConvertTiming(config->tRdxHigh_Ns, clkSrc_Hz) - 1) |
+                   SEMC_DBICR1_CEITV(SEMC_ConvertTiming(config->tCsxInterval_Ns, clkSrc_Hz) - 1);
     return SEMC_ConfigureIPCommand(base, (config->portSize + 1));
 }
 
+/*!
+ * brief SEMC IP command access.
+ *
+ * param base  SEMC peripheral base address.
+ * param type  SEMC memory type. refer to "semc_mem_type_t"
+ * param address  SEMC device address.
+ * param command  SEMC IP command.
+ * For NAND device, we should use the SEMC_BuildNandIPCommand to get the right nand command.
+ * For NOR/DBI device, take refer to "semc_ipcmd_nor_dbi_t".
+ * For SRAM device, take refer to "semc_ipcmd_sram_t".
+ * For SDRAM device, take refer to "semc_ipcmd_sdram_t".
+ * param write  Data for write access.
+ * param read   Data pointer for read data out.
+ */
 status_t SEMC_SendIPCommand(
     SEMC_Type *base, semc_mem_type_t type, uint32_t address, uint16_t command, uint32_t write, uint32_t *read)
 {
     uint32_t cmdMode;
-    bool readCmd = 0;
+    bool readCmd  = 0;
     bool writeCmd = 0;
     status_t result;
 
@@ -782,22 +830,22 @@ status_t SEMC_SendIPCommand(
     switch (type)
     {
         case kSEMC_MemType_NAND:
-            readCmd = (cmdMode == kSEMC_NANDCM_CommandAddressRead) ||
-                      (cmdMode == kSEMC_NANDCM_CommandRead) || (cmdMode == kSEMC_NANDCM_Read);
-            writeCmd = (cmdMode == kSEMC_NANDCM_CommandAddressWrite) ||
-                       (cmdMode == kSEMC_NANDCM_CommandWrite) || (cmdMode == kSEMC_NANDCM_Write);
+            readCmd = (cmdMode == kSEMC_NANDCM_CommandAddressRead) || (cmdMode == kSEMC_NANDCM_CommandRead) ||
+                      (cmdMode == kSEMC_NANDCM_Read);
+            writeCmd = (cmdMode == kSEMC_NANDCM_CommandAddressWrite) || (cmdMode == kSEMC_NANDCM_CommandWrite) ||
+                       (cmdMode == kSEMC_NANDCM_Write);
             break;
         case kSEMC_MemType_NOR:
         case kSEMC_MemType_8080:
-            readCmd = (cmdMode == kSEMC_NORDBICM_Read);
+            readCmd  = (cmdMode == kSEMC_NORDBICM_Read);
             writeCmd = (cmdMode == kSEMC_NORDBICM_Write);
             break;
         case kSEMC_MemType_SRAM:
-            readCmd = (cmdMode == kSEMC_SRAMCM_ArrayRead) || (cmdMode == kSEMC_SRAMCM_RegRead);
+            readCmd  = (cmdMode == kSEMC_SRAMCM_ArrayRead) || (cmdMode == kSEMC_SRAMCM_RegRead);
             writeCmd = (cmdMode == kSEMC_SRAMCM_ArrayWrite) || (cmdMode == kSEMC_SRAMCM_RegWrite);
             break;
         case kSEMC_MemType_SDRAM:
-            readCmd = (cmdMode == kSEMC_SDRAMCM_Read);
+            readCmd  = (cmdMode == kSEMC_SDRAMCM_Read);
             writeCmd = (cmdMode == kSEMC_SDRAMCM_Write) || (cmdMode == kSEMC_SDRAMCM_Modeset);
             break;
         default:
@@ -828,6 +876,14 @@ status_t SEMC_SendIPCommand(
     return kStatus_Success;
 }
 
+/*!
+ * brief SEMC NAND device memory write through IP command.
+ *
+ * param base  SEMC peripheral base address.
+ * param address  SEMC NAND device address.
+ * param data  Data for write access.
+ * param size_bytes   Data length.
+ */
 status_t SEMC_IPCommandNandWrite(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes)
 {
     assert(data);
@@ -868,6 +924,14 @@ status_t SEMC_IPCommandNandWrite(SEMC_Type *base, uint32_t address, uint8_t *dat
     return result;
 }
 
+/*!
+ * brief SEMC NAND device memory read through IP command.
+ *
+ * param base  SEMC peripheral base address.
+ * param address  SEMC NAND device address.
+ * param data  Data pointer for data read out.
+ * param size_bytes   Data length.
+ */
 status_t SEMC_IPCommandNandRead(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes)
 {
     assert(data);
@@ -908,13 +972,21 @@ status_t SEMC_IPCommandNandRead(SEMC_Type *base, uint32_t address, uint8_t *data
     return result;
 }
 
+/*!
+ * brief SEMC NOR device memory read through IP command.
+ *
+ * param base  SEMC peripheral base address.
+ * param address  SEMC NOR device address.
+ * param data  Data pointer for data read out.
+ * param size_bytes   Data length.
+ */
 status_t SEMC_IPCommandNorRead(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes)
 {
     assert(data);
 
     uint32_t tempData = 0;
-    status_t result = kStatus_Success;
-    uint8_t dataSize = base->NORCR0 & SEMC_NORCR0_PS_MASK;
+    status_t result   = kStatus_Success;
+    uint8_t dataSize  = base->NORCR0 & SEMC_NORCR0_PS_MASK;
 
     /* Configure IP command data size. */
     SEMC_ConfigureIPCommand(base, SEMC_IPCOMMANDDATASIZEBYTEMAX);
@@ -946,13 +1018,21 @@ status_t SEMC_IPCommandNorRead(SEMC_Type *base, uint32_t address, uint8_t *data,
     return result;
 }
 
+/*!
+ * brief SEMC NOR device memory write through IP command.
+ *
+ * param base  SEMC peripheral base address.
+ * param address  SEMC NOR device address.
+ * param data  Data for write access.
+ * param size_bytes   Data length.
+ */
 status_t SEMC_IPCommandNorWrite(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes)
 {
     assert(data);
 
     uint32_t tempData = 0;
-    status_t result = kStatus_Success;
-    uint8_t dataSize = base->NORCR0 & SEMC_NORCR0_PS_MASK;
+    status_t result   = kStatus_Success;
+    uint8_t dataSize  = base->NORCR0 & SEMC_NORCR0_PS_MASK;
 
     /* Write command built */
     while (size_bytes >= SEMC_IPCOMMANDDATASIZEBYTEMAX)
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_semc.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_semc.h
index a6937e12eee..41ad2b2362d 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_semc.h
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_semc.h
@@ -1,34 +1,8 @@
 /*
- * The Clear BSD License
- * Copyright 2017 NXP
+ * Copyright 2017-2018 NXP
  * All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- * that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 #ifndef _FSL_SEMC_H_
 #define _FSL_SEMC_H_
@@ -46,29 +20,30 @@
 
 /*! @name Driver version */
 /*@{*/
-/*! @brief SEMC driver version 2.0.1. */
-#define FSL_SEMC_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
+/*! @brief SEMC driver version 2.0.4. */
+#define FSL_SEMC_DRIVER_VERSION (MAKE_VERSION(2, 0, 4))
 /*@}*/
 
 /*! @brief SEMC status. */
 enum _semc_status
 {
-    kStatus_SEMC_InvalidDeviceType = MAKE_STATUS(kStatusGroup_SEMC, 0),
-    kStatus_SEMC_IpCommandExecutionError = MAKE_STATUS(kStatusGroup_SEMC, 1),
-    kStatus_SEMC_AxiCommandExecutionError = MAKE_STATUS(kStatusGroup_SEMC, 2),
-    kStatus_SEMC_InvalidMemorySize = MAKE_STATUS(kStatusGroup_SEMC, 3),
-    kStatus_SEMC_InvalidIpcmdDataSize = MAKE_STATUS(kStatusGroup_SEMC, 4),
-    kStatus_SEMC_InvalidAddressPortWidth = MAKE_STATUS(kStatusGroup_SEMC, 5),
-    kStatus_SEMC_InvalidDataPortWidth = MAKE_STATUS(kStatusGroup_SEMC, 6),
-    kStatus_SEMC_InvalidSwPinmuxSelection = MAKE_STATUS(kStatusGroup_SEMC, 7),
-    kStatus_SEMC_InvalidBurstLength = MAKE_STATUS(kStatusGroup_SEMC, 8),
+    kStatus_SEMC_InvalidDeviceType            = MAKE_STATUS(kStatusGroup_SEMC, 0),
+    kStatus_SEMC_IpCommandExecutionError      = MAKE_STATUS(kStatusGroup_SEMC, 1),
+    kStatus_SEMC_AxiCommandExecutionError     = MAKE_STATUS(kStatusGroup_SEMC, 2),
+    kStatus_SEMC_InvalidMemorySize            = MAKE_STATUS(kStatusGroup_SEMC, 3),
+    kStatus_SEMC_InvalidIpcmdDataSize         = MAKE_STATUS(kStatusGroup_SEMC, 4),
+    kStatus_SEMC_InvalidAddressPortWidth      = MAKE_STATUS(kStatusGroup_SEMC, 5),
+    kStatus_SEMC_InvalidDataPortWidth         = MAKE_STATUS(kStatusGroup_SEMC, 6),
+    kStatus_SEMC_InvalidSwPinmuxSelection     = MAKE_STATUS(kStatusGroup_SEMC, 7),
+    kStatus_SEMC_InvalidBurstLength           = MAKE_STATUS(kStatusGroup_SEMC, 8),
     kStatus_SEMC_InvalidColumnAddressBitWidth = MAKE_STATUS(kStatusGroup_SEMC, 9),
-    kStatus_SEMC_InvalidBaseAddress = MAKE_STATUS(kStatusGroup_SEMC, 10),
-    kStatus_SEMC_InvalidTimerSetting = MAKE_STATUS(kStatusGroup_SEMC, 11),
+    kStatus_SEMC_InvalidBaseAddress           = MAKE_STATUS(kStatusGroup_SEMC, 10),
+    kStatus_SEMC_InvalidTimerSetting          = MAKE_STATUS(kStatusGroup_SEMC, 11),
 };
 
 /*! @brief SEMC memory device type. */
-typedef enum _semc_mem_type {
+typedef enum _semc_mem_type
+{
     kSEMC_MemType_SDRAM = 0, /*!< SDRAM */
     kSEMC_MemType_SRAM,      /*!< SRAM */
     kSEMC_MemType_NOR,       /*!< NOR */
@@ -77,13 +52,15 @@ typedef enum _semc_mem_type {
 } semc_mem_type_t;
 
 /*! @brief SEMC WAIT/RDY polarity. */
-typedef enum _semc_waitready_polarity {
+typedef enum _semc_waitready_polarity
+{
     kSEMC_LowActive = 0, /*!< Low active. */
     kSEMC_HighActive,    /*!< High active. */
 } semc_waitready_polarity_t;
 
 /*! @brief SEMC SDRAM Chip selection . */
-typedef enum _semc_sdram_cs {
+typedef enum _semc_sdram_cs
+{
     kSEMC_SDRAM_CS0 = 0, /*!< SEMC SDRAM CS0. */
     kSEMC_SDRAM_CS1,     /*!< SEMC SDRAM CS1. */
     kSEMC_SDRAM_CS2,     /*!< SEMC SDRAM CS2. */
@@ -91,21 +68,24 @@ typedef enum _semc_sdram_cs {
 } semc_sdram_cs_t;
 
 /*! @brief SEMC NAND device type. */
-typedef enum _semc_nand_access_type {
+typedef enum _semc_nand_access_type
+{
     kSEMC_NAND_ACCESS_BY_AXI = 0,
     kSEMC_NAND_ACCESS_BY_IPCMD,
 } semc_nand_access_type_t;
 
 /*! @brief SEMC interrupts . */
-typedef enum _semc_interrupt_enable {
+typedef enum _semc_interrupt_enable
+{
     kSEMC_IPCmdDoneInterrupt = SEMC_INTEN_IPCMDDONEEN_MASK, /*!< Ip command done interrupt. */
-    kSEMC_IPCmdErrInterrupt = SEMC_INTEN_IPCMDERREN_MASK,   /*!< Ip command error interrupt. */
+    kSEMC_IPCmdErrInterrupt  = SEMC_INTEN_IPCMDERREN_MASK,  /*!< Ip command error interrupt. */
     kSEMC_AXICmdErrInterrupt = SEMC_INTEN_AXICMDERREN_MASK, /*!< AXI command error interrupt. */
     kSEMC_AXIBusErrInterrupt = SEMC_INTEN_AXIBUSERREN_MASK  /*!< AXI bus error interrupt. */
 } semc_interrupt_enable_t;
 
 /*! @brief SEMC IP command data size in bytes. */
-typedef enum _semc_ipcmd_datasize {
+typedef enum _semc_ipcmd_datasize
+{
     kSEMC_IPcmdDataSize_1bytes = 1, /*!< The IP command data size 1 byte. */
     kSEMC_IPcmdDataSize_2bytes,     /*!< The IP command data size 2 byte. */
     kSEMC_IPcmdDataSize_3bytes,     /*!< The IP command data size 3 byte. */
@@ -113,21 +93,24 @@ typedef enum _semc_ipcmd_datasize {
 } semc_ipcmd_datasize_t;
 
 /*! @brief SEMC auto-refresh timing. */
-typedef enum _semc_refresh_time {
+typedef enum _semc_refresh_time
+{
     kSEMC_RefreshThreeClocks = 0x0U, /*!< The refresh timing with three bus clocks. */
     kSEMC_RefreshSixClocks,          /*!< The refresh timing with six bus clocks. */
     kSEMC_RefreshNineClocks          /*!< The refresh timing with nine bus clocks. */
 } semc_refresh_time_t;
 
 /*! @brief CAS latency */
-typedef enum _semc_caslatency {
+typedef enum _semc_caslatency
+{
     kSEMC_LatencyOne = 1, /*!< Latency  1. */
     kSEMC_LatencyTwo,     /*!< Latency  2. */
     kSEMC_LatencyThree,   /*!< Latency  3. */
 } semc_caslatency_t;
 
 /*! @brief SEMC sdram column address bit number. */
-typedef enum _semc_sdram_column_bit_num {
+typedef enum _semc_sdram_column_bit_num
+{
     kSEMC_SdramColunm_12bit = 0x0U, /*!< 12 bit. */
     kSEMC_SdramColunm_11bit,        /*!< 11 bit. */
     kSEMC_SdramColunm_10bit,        /*!< 10 bit. */
@@ -135,7 +118,8 @@ typedef enum _semc_sdram_column_bit_num {
 } semc_sdram_column_bit_num_t;
 
 /*! @brief SEMC sdram burst length. */
-typedef enum _semc_sdram_burst_len {
+typedef enum _semc_sdram_burst_len
+{
     kSEMC_Sdram_BurstLen1 = 0, /*!< Burst length 1*/
     kSEMC_Sdram_BurstLen2,     /*!< Burst length 2*/
     kSEMC_Sdram_BurstLen4,     /*!< Burst length 4*/
@@ -143,7 +127,8 @@ typedef enum _semc_sdram_burst_len {
 } sem_sdram_burst_len_t;
 
 /*! @brief SEMC nand column address bit number. */
-typedef enum _semc_nand_column_bit_num {
+typedef enum _semc_nand_column_bit_num
+{
     kSEMC_NandColum_16bit = 0x0U, /*!< 16 bit. */
     kSEMC_NandColum_15bit,        /*!< 15 bit. */
     kSEMC_NandColum_14bit,        /*!< 14 bit. */
@@ -155,7 +140,8 @@ typedef enum _semc_nand_column_bit_num {
 } semc_nand_column_bit_num_t;
 
 /*! @brief SEMC nand burst length. */
-typedef enum _semc_nand_burst_len {
+typedef enum _semc_nand_burst_len
+{
     kSEMC_Nand_BurstLen1 = 0, /*!< Burst length 1*/
     kSEMC_Nand_BurstLen2,     /*!< Burst length 2*/
     kSEMC_Nand_BurstLen4,     /*!< Burst length 4*/
@@ -166,7 +152,8 @@ typedef enum _semc_nand_burst_len {
 } sem_nand_burst_len_t;
 
 /*! @brief SEMC nor/sram column address bit number. */
-typedef enum _semc_norsram_column_bit_num {
+typedef enum _semc_norsram_column_bit_num
+{
     kSEMC_NorColum_12bit = 0x0U, /*!< 12 bit. */
     kSEMC_NorColum_11bit,        /*!< 11 bit. */
     kSEMC_NorColum_10bit,        /*!< 10 bit. */
@@ -181,7 +168,8 @@ typedef enum _semc_norsram_column_bit_num {
 } semc_norsram_column_bit_num_t;
 
 /*! @brief SEMC nor/sram burst length. */
-typedef enum _semc_norsram_burst_len {
+typedef enum _semc_norsram_burst_len
+{
     kSEMC_Nor_BurstLen1 = 0, /*!< Burst length 1*/
     kSEMC_Nor_BurstLen2,     /*!< Burst length 2*/
     kSEMC_Nor_BurstLen4,     /*!< Burst length 4*/
@@ -192,7 +180,8 @@ typedef enum _semc_norsram_burst_len {
 } sem_norsram_burst_len_t;
 
 /*! @brief SEMC dbi column address bit number. */
-typedef enum _semc_dbi_column_bit_num {
+typedef enum _semc_dbi_column_bit_num
+{
     kSEMC_Dbi_Colum_12bit = 0x0U, /*!< 12 bit. */
     kSEMC_Dbi_Colum_11bit,        /*!< 11 bit. */
     kSEMC_Dbi_Colum_10bit,        /*!< 10 bit. */
@@ -207,7 +196,8 @@ typedef enum _semc_dbi_column_bit_num {
 } semc_dbi_column_bit_num_t;
 
 /*! @brief SEMC dbi burst length. */
-typedef enum _semc_dbi_burst_len {
+typedef enum _semc_dbi_burst_len
+{
     kSEMC_Dbi_BurstLen1 = 0, /*!< Burst length 1*/
     kSEMC_Dbi_BurstLen2,     /*!< Burst length 2*/
     kSEMC_Dbi_Dbi_BurstLen4, /*!< Burst length 4*/
@@ -218,55 +208,63 @@ typedef enum _semc_dbi_burst_len {
 } sem_dbi_burst_len_t;
 
 /*! @brief SEMC IOMUXC. */
-typedef enum _semc_iomux_pin {
-    kSEMC_MUXA8 = SEMC_IOCR_MUX_A8_SHIFT,     /*!< MUX A8 pin. */
+typedef enum _semc_iomux_pin
+{
+    kSEMC_MUXA8   = SEMC_IOCR_MUX_A8_SHIFT,   /*!< MUX A8 pin. */
     kSEMC_MUXCSX0 = SEMC_IOCR_MUX_CSX0_SHIFT, /*!< MUX CSX0 pin */
     kSEMC_MUXCSX1 = SEMC_IOCR_MUX_CSX1_SHIFT, /*!< MUX CSX1 Pin.*/
     kSEMC_MUXCSX2 = SEMC_IOCR_MUX_CSX2_SHIFT, /*!< MUX CSX2 Pin. */
     kSEMC_MUXCSX3 = SEMC_IOCR_MUX_CSX3_SHIFT, /*!< MUX CSX3 Pin. */
-    kSEMC_MUXRDY = SEMC_IOCR_MUX_RDY_SHIFT    /*!< MUX RDY pin. */
+    kSEMC_MUXRDY  = SEMC_IOCR_MUX_RDY_SHIFT   /*!< MUX RDY pin. */
 } semc_iomux_pin;
 
 /*! @brief SEMC NOR/PSRAM Address bit 27 A27. */
-typedef enum _semc_iomux_nora27_pin {
-    kSEMC_MORA27_NONE = 0,                           /*!< No NOR/SRAM A27 pin. */
+typedef enum _semc_iomux_nora27_pin
+{
+    kSEMC_MORA27_NONE    = 0,                        /*!< No NOR/SRAM A27 pin. */
     kSEMC_NORA27_MUXCSX3 = SEMC_IOCR_MUX_CSX3_SHIFT, /*!< MUX CSX3 Pin. */
-    kSEMC_NORA27_MUXRDY = SEMC_IOCR_MUX_RDY_SHIFT    /*!< MUX RDY pin. */
+    kSEMC_NORA27_MUXRDY  = SEMC_IOCR_MUX_RDY_SHIFT   /*!< MUX RDY pin. */
 } semc_iomux_nora27_pin;
 
 /*! @brief SEMC port size. */
-typedef enum _semc_port_size {
+typedef enum _semc_port_size
+{
     kSEMC_PortSize8Bit = 0, /*!< 8-Bit port size. */
     kSEMC_PortSize16Bit     /*!< 16-Bit port size. */
 } smec_port_size_t;
 
 /*! @brief SEMC address mode. */
-typedef enum _semc_addr_mode {
+typedef enum _semc_addr_mode
+{
     kSEMC_AddrDataMux = 0, /*!< SEMC address/data mux mode. */
     kSEMC_AdvAddrdataMux,  /*!< Advanced address/data mux mode. */
     kSEMC_AddrDataNonMux   /*!< Address/data non-mux mode. */
 } semc_addr_mode_t;
 
 /*! @brief SEMC DQS read strobe mode. */
-typedef enum _semc_dqs_mode {
+typedef enum _semc_dqs_mode
+{
     kSEMC_Loopbackinternal = 0, /*!< Dummy read strobe loopbacked internally. */
     kSEMC_Loopbackdqspad,       /*!< Dummy read strobe loopbacked from DQS pad. */
 } semc_dqs_mode_t;
 
 /*! @brief SEMC ADV signal active polarity. */
-typedef enum _semc_adv_polarity {
+typedef enum _semc_adv_polarity
+{
     kSEMC_AdvActiveLow = 0, /*!< Adv active low. */
     kSEMC_AdvActivehigh,    /*!< Adv active low. */
 } semc_adv_polarity_t;
 
 /*! @brief SEMC RDY signal active polarity. */
-typedef enum _semc_rdy_polarity {
+typedef enum _semc_rdy_polarity
+{
     kSEMC_RdyActiveLow = 0, /*!< Adv active low. */
     kSEMC_RdyActivehigh,    /*!< Adv active low. */
 } semc_rdy_polarity_t;
 
 /*! @brief SEMC IP command for NAND: address mode. */
-typedef enum _semc_ipcmd_nand_addrmode {
+typedef enum _semc_ipcmd_nand_addrmode
+{
     kSEMC_NANDAM_ColumnRow = 0x0U, /*!< Address mode: column and row address(5Byte-CA0/CA1/RA0/RA1/RA2). */
     kSEMC_NANDAM_ColumnCA0,        /*!< Address mode: column address only(1 Byte-CA0).  */
     kSEMC_NANDAM_ColumnCA0CA1,     /*!< Address mode: column address only(2 Byte-CA0/CA1). */
@@ -276,21 +274,23 @@ typedef enum _semc_ipcmd_nand_addrmode {
 } semc_ipcmd_nand_addrmode_t;
 
 /*! @brief SEMC IP command for NAND： command mode. */
-typedef enum _semc_ipcmd_nand_cmdmode {
-    kSEMC_NANDCM_Command = 0x2U,        /*!< command. */
-    kSEMC_NANDCM_CommandHold,           /*!< Command hold. */
-    kSEMC_NANDCM_CommandAddress,        /*!< Command address. */
-    kSEMC_NANDCM_CommandAddressHold,    /*!< Command address hold.  */
-    kSEMC_NANDCM_CommandAddressRead,    /*!< Command address read.  */
-    kSEMC_NANDCM_CommandAddressWrite,   /*!< Command address write.  */
-    kSEMC_NANDCM_CommandRead,           /*!< Command read.  */
-    kSEMC_NANDCM_CommandWrite,          /*!< Command write.  */
-    kSEMC_NANDCM_Read,                  /*!< Read.  */
-    kSEMC_NANDCM_Write                  /*!< Write.  */
+typedef enum _semc_ipcmd_nand_cmdmode
+{
+    kSEMC_NANDCM_Command = 0x2U,      /*!< command. */
+    kSEMC_NANDCM_CommandHold,         /*!< Command hold. */
+    kSEMC_NANDCM_CommandAddress,      /*!< Command address. */
+    kSEMC_NANDCM_CommandAddressHold,  /*!< Command address hold.  */
+    kSEMC_NANDCM_CommandAddressRead,  /*!< Command address read.  */
+    kSEMC_NANDCM_CommandAddressWrite, /*!< Command address write.  */
+    kSEMC_NANDCM_CommandRead,         /*!< Command read.  */
+    kSEMC_NANDCM_CommandWrite,        /*!< Command write.  */
+    kSEMC_NANDCM_Read,                /*!< Read.  */
+    kSEMC_NANDCM_Write                /*!< Write.  */
 } semc_ipcmd_nand_cmdmode_t;
 
 /*! @brief SEMC NAND address option. */
-typedef enum _semc_nand_address_option {
+typedef enum _semc_nand_address_option
+{
     kSEMC_NandAddrOption_5byte_CA2RA3 = 0U, /*!< CA0+CA1+RA0+RA1+RA2 */
     kSEMC_NandAddrOption_4byte_CA2RA2 = 2U, /*!< CA0+CA1+RA0+RA1 */
     kSEMC_NandAddrOption_3byte_CA2RA1 = 4U, /*!< CA0+CA1+RA0 */
@@ -300,13 +300,15 @@ typedef enum _semc_nand_address_option {
 } semc_nand_address_option_t;
 
 /*! @brief SEMC IP command for NOR. */
-typedef enum _semc_ipcmd_nor_dbi {
+typedef enum _semc_ipcmd_nor_dbi
+{
     kSEMC_NORDBICM_Read = 0x2U, /*!< NOR read. */
     kSEMC_NORDBICM_Write        /*!< NOR write.  */
 } semc_ipcmd_nor_dbi_t;
 
 /*! @brief SEMC IP command for SRAM. */
-typedef enum _semc_ipcmd_sram {
+typedef enum _semc_ipcmd_sram
+{
     kSEMC_SRAMCM_ArrayRead = 0x2U, /*!< SRAM memory array read. */
     kSEMC_SRAMCM_ArrayWrite,       /*!< SRAM memory array write. */
     kSEMC_SRAMCM_RegRead,          /*!< SRAM memory register read. */
@@ -314,7 +316,8 @@ typedef enum _semc_ipcmd_sram {
 } semc_ipcmd_sram_t;
 
 /*! @brief SEMC IP command for SDARM. */
-typedef enum _semc_ipcmd_sdram {
+typedef enum _semc_ipcmd_sdram
+{
     kSEMC_SDRAMCM_Read = 0x8U, /*!< SDRAM memory read. */
     kSEMC_SDRAMCM_Write,       /*!< SDRAM memory write. */
     kSEMC_SDRAMCM_Modeset,     /*!< SDRAM MODE SET. */
@@ -362,26 +365,24 @@ typedef struct _semc_sdram_config
     uint8_t refreshBurstLen;         /*!< Refresh burst length. */
 } semc_sdram_config_t;
 
-
 /*! @brief SEMC NAND device timing configuration structure. */
 typedef struct _semc_nand_timing_config
 {
-    uint8_t tCeSetup_Ns;                         /*!< CE setup time: tCS. */
-    uint8_t tCeHold_Ns;                          /*!< CE hold time: tCH. */
-    uint8_t tCeInterval_Ns;                      /*!< CE interval time:tCEITV. */
-    uint8_t tWeLow_Ns;                           /*!< WE low time: tWP. */
-    uint8_t tWeHigh_Ns;                          /*!< WE high time: tWH. */
-    uint8_t tReLow_Ns;                           /*!< RE low time: tRP. */
-    uint8_t tReHigh_Ns;                          /*!< RE high time: tREH. */
-    uint8_t tTurnAround_Ns;                      /*!< Turnaround time for async mode: tTA. */
-    uint8_t tWehigh2Relow_Ns;                    /*!< WE# high to RE# wait time: tWHR. */
-    uint8_t tRehigh2Welow_Ns;                    /*!< RE# high to WE# low wait time: tRHW. */
-    uint8_t tAle2WriteStart_Ns;                  /*!< ALE to write start wait time: tADL. */
-    uint8_t tReady2Relow_Ns;                     /*!< Ready to RE# low min wait time: tRR. */
-    uint8_t tWehigh2Busy_Ns;                     /*!< WE# high to busy wait time: tWB. */    
+    uint8_t tCeSetup_Ns;        /*!< CE setup time: tCS. */
+    uint8_t tCeHold_Ns;         /*!< CE hold time: tCH. */
+    uint8_t tCeInterval_Ns;     /*!< CE interval time:tCEITV. */
+    uint8_t tWeLow_Ns;          /*!< WE low time: tWP. */
+    uint8_t tWeHigh_Ns;         /*!< WE high time: tWH. */
+    uint8_t tReLow_Ns;          /*!< RE low time: tRP. */
+    uint8_t tReHigh_Ns;         /*!< RE high time: tREH. */
+    uint8_t tTurnAround_Ns;     /*!< Turnaround time for async mode: tTA. */
+    uint8_t tWehigh2Relow_Ns;   /*!< WE# high to RE# wait time: tWHR. */
+    uint8_t tRehigh2Welow_Ns;   /*!< RE# high to WE# low wait time: tRHW. */
+    uint8_t tAle2WriteStart_Ns; /*!< ALE to write start wait time: tADL. */
+    uint8_t tReady2Relow_Ns;    /*!< Ready to RE# low min wait time: tRR. */
+    uint8_t tWehigh2Busy_Ns;    /*!< WE# high to busy wait time: tWB. */
 } semc_nand_timing_config_t;
 
-
 /*! @brief SEMC NAND configuration structure. */
 typedef struct _semc_nand_config
 {
@@ -424,10 +425,14 @@ typedef struct _semc_nor_config
     uint8_t tReHigh_Ns;                             /*!< RE high time for async mode. */
     uint8_t tTurnAround_Ns;                         /*!< Turnaround time for async mode. */
     uint8_t tAddr2WriteHold_Ns;                     /*!< Address to write data hold time for async mode. */
-    uint8_t tWriteSetup_Ns;                         /*!< Write data setup time for sync mode.*/
-    uint8_t tWriteHold_Ns;                          /*!< Write hold time for sync mode. */
-    uint8_t latencyCount;                           /*!< Latency count for sync mode. */
-    uint8_t readCycle;                              /*!< Read cycle time for sync mode. */
+#if defined(FSL_FEATURE_SEMC_HAS_NOR_WDS_TIME) && (FSL_FEATURE_SEMC_HAS_NOR_WDS_TIME)
+    uint8_t tWriteSetup_Ns; /*!< Write data setup time for sync mode.*/
+#endif
+#if defined(FSL_FEATURE_SEMC_HAS_NOR_WDH_TIME) && (FSL_FEATURE_SEMC_HAS_NOR_WDH_TIME)
+    uint8_t tWriteHold_Ns; /*!< Write hold time for sync mode. */
+#endif
+    uint8_t latencyCount; /*!< Latency count for sync mode. */
+    uint8_t readCycle;    /*!< Read cycle time for sync mode. */
 } semc_nor_config_t;
 
 /*! @brief SEMC SRAM  configuration structure. */
@@ -477,30 +482,44 @@ typedef struct _semc_dbi_config
     uint8_t tCsxInterval_Ns;                    /*!< Write data setup time.*/
 } semc_dbi_config_t;
 
-/*! @brief SEMC AXI queue a weight setting. */
-typedef struct _semc_queuea_weight
+/*! @brief SEMC AXI queue a weight setting structure. */
+typedef struct _semc_queuea_weight_struct
 {
     uint32_t qos : 4;              /*!< weight of qos for queue 0 . */
     uint32_t aging : 4;            /*!< weight of aging for queue 0.*/
     uint32_t slaveHitSwith : 8;    /*!< weight of read/write switch for queue 0.*/
     uint32_t slaveHitNoswitch : 8; /*!< weight of read/write no switch for queue 0  .*/
+} semc_queuea_weight_struct_t;
+
+/*! @brief SEMC AXI queue a weight setting union. */
+typedef union _semc_queuea_weight
+{
+    semc_queuea_weight_struct_t queueaConfig; /*!< Structure configuration for queueA. */
+    uint32_t queueaValue; /*!< Configuration value for queueA which could directly write to the reg. */
 } semc_queuea_weight_t;
 
-/*! @brief SEMC AXI queue b weight setting. */
-typedef struct _semc_queueb_weight
+/*! @brief SEMC AXI queue b weight setting structure. */
+typedef struct _semc_queueb_weight_struct
 {
     uint32_t qos : 4;           /*!< weight of qos for queue 1. */
     uint32_t aging : 4;         /*!< weight of aging for queue 1.*/
     uint32_t slaveHitSwith : 8; /*!< weight of read/write switch for queue 1.*/
     uint32_t weightPagehit : 8; /*!< weight of page hit for queue 1 only .*/
     uint32_t bankRotation : 8;  /*!< weight of bank rotation for queue 1 only .*/
+} semc_queueb_weight_struct_t;
+
+/*! @brief SEMC AXI queue b weight setting union. */
+typedef union _semc_queueb_weight
+{
+    semc_queueb_weight_struct_t queuebConfig; /*!< Structure configuration for queueB. */
+    uint32_t queuebValue; /*!< Configuration value for queueB which could directly write to the reg. */
 } semc_queueb_weight_t;
 
 /*! @brief SEMC AXI queue weight setting. */
 typedef struct _semc_axi_queueweight
 {
-    semc_queuea_weight_t *queueaWeight; /*!< Weight settings for queue a. */
-    semc_queueb_weight_t *queuebWeight; /*!< Weight settings for queue b. */
+    semc_queuea_weight_t queueaWeight; /*!< Weight settings for queue a. */
+    semc_queueb_weight_t queuebWeight; /*!< Weight settings for queue b. */
 } semc_axi_queueweight_t;
 
 /*!
@@ -560,8 +579,12 @@ void SEMC_Init(SEMC_Type *base, semc_config_t *configure);
 
 /*!
  * @brief Deinitializes the SEMC module and gates the clock.
- * This function gates the SEMC clock. As a result, the SEMC
- * module doesn't work after calling this function.
+ *
+ * This function gates the SEMC clock. As a result, the SEMC module doesn't work after
+ * calling this function, for some IDE, calling this API may cause the next downloading
+ * operation failed. so, please call this API cautiously. Additional, users can
+ * using "#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL (1)" to disable the clock control
+ * operation in drivers.
  *
  * @param base SEMC peripheral base address.
  */
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_snvs_hp.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_snvs_hp.c
index 0e6efab1311..c59e9fc0358 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_snvs_hp.c
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_snvs_hp.c
@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright (c) 2017, NXP
+ * Copyright 2017, NXP
  * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
  *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include "fsl_snvs_hp.h"
@@ -50,9 +24,6 @@
 #define YEAR_RANGE_START (1970U)
 #define YEAR_RANGE_END (2099U)
 
-#if !(defined(SNVS_HPCOMR_SW_SV_MASK))
-#define SNVS_HPCOMR_SW_SV_MASK (0x100U)
-#endif
 #if !(defined(SNVS_HPSR_PI_MASK))
 #define SNVS_HPSR_PI_MASK (0x2U)
 #endif
@@ -210,13 +181,13 @@ static void SNVS_HP_ConvertSecondsToDatetime(uint32_t seconds, snvs_hp_rtc_datet
     secondsRemaining = secondsRemaining % SECONDS_IN_A_DAY;
 
     /* Calculate the datetime hour, minute and second fields */
-    datetime->hour = secondsRemaining / SECONDS_IN_A_HOUR;
+    datetime->hour   = secondsRemaining / SECONDS_IN_A_HOUR;
     secondsRemaining = secondsRemaining % SECONDS_IN_A_HOUR;
     datetime->minute = secondsRemaining / 60U;
     datetime->second = secondsRemaining % SECONDS_IN_A_MINUTE;
 
     /* Calculate year */
-    daysInYear = DAYS_IN_A_YEAR;
+    daysInYear     = DAYS_IN_A_YEAR;
     datetime->year = YEAR_RANGE_START;
     while (days > daysInYear)
     {
@@ -265,6 +236,44 @@ static uint32_t SNVS_HP_GetInstance(SNVS_Type *base)
 }
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
+/*!
+ * brief Initialize the SNVS.
+ *
+ * note This API should be called at the beginning of the application using the SNVS driver.
+ *
+ * param base SNVS peripheral base address
+ */
+void SNVS_HP_Init(SNVS_Type *base)
+{
+#if (!(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && \
+     defined(SNVS_HP_CLOCKS))
+    uint32_t instance = SNVS_HP_GetInstance(base);
+    CLOCK_EnableClock(s_snvsHpClock[instance]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}
+
+/*!
+ * brief Deinitialize the SNVS.
+ *
+ * param base SNVS peripheral base address
+ */
+void SNVS_HP_Deinit(SNVS_Type *base)
+{
+#if (!(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && \
+     defined(SNVS_HP_CLOCKS))
+    uint32_t instance = SNVS_HP_GetInstance(base);
+    CLOCK_DisableClock(s_snvsHpClock[instance]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}
+
+/*!
+ * brief Ungates the SNVS clock and configures the peripheral for basic operation.
+ *
+ * note This API should be called at the beginning of the application using the SNVS driver.
+ *
+ * param base   SNVS peripheral base address
+ * param config Pointer to the user's SNVS configuration structure.
+ */
 void SNVS_HP_RTC_Init(SNVS_Type *base, const snvs_hp_rtc_config_t *config)
 {
     assert(config);
@@ -275,17 +284,22 @@ void SNVS_HP_RTC_Init(SNVS_Type *base, const snvs_hp_rtc_config_t *config)
     CLOCK_EnableClock(s_snvsHpClock[instance]);
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
-    base->HPCOMR |= SNVS_HPCOMR_NPSWA_EN_MASK | SNVS_HPCOMR_SW_SV_MASK;
+    base->HPCOMR |= SNVS_HPCOMR_NPSWA_EN_MASK;
 
     base->HPCR = SNVS_HPCR_PI_FREQ(config->periodicInterruptFreq);
 
     if (config->rtcCalEnable)
     {
-        base->HPCR = SNVS_HPCR_HPCALB_VAL_MASK & (config->rtcCalValue << SNVS_HPCR_HPCALB_VAL_SHIFT);
+        base->HPCR |= SNVS_HPCR_HPCALB_VAL_MASK & (config->rtcCalValue << SNVS_HPCR_HPCALB_VAL_SHIFT);
         base->HPCR |= SNVS_HPCR_HPCALB_EN_MASK;
     }
 }
 
+/*!
+ * brief Stops the RTC and SRTC timers.
+ *
+ * param base SNVS peripheral base address
+ */
 void SNVS_HP_RTC_Deinit(SNVS_Type *base)
 {
     base->HPCR &= ~SNVS_HPCR_RTC_EN_MASK;
@@ -297,36 +311,59 @@ void SNVS_HP_RTC_Deinit(SNVS_Type *base)
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }
 
+/*!
+ * brief Fills in the SNVS config struct with the default settings.
+ *
+ * The default values are as follows.
+ * code
+ *    config->rtccalenable = false;
+ *    config->rtccalvalue = 0U;
+ *    config->PIFreq = 0U;
+ * endcode
+ * param config Pointer to the user's SNVS configuration structure.
+ */
 void SNVS_HP_RTC_GetDefaultConfig(snvs_hp_rtc_config_t *config)
 {
     assert(config);
 
-    config->rtcCalEnable = false;
-    config->rtcCalValue = 0U;
+    /* Initializes the configure structure to zero. */
+    memset(config, 0, sizeof(*config));
+
+    config->rtcCalEnable          = false;
+    config->rtcCalValue           = 0U;
     config->periodicInterruptFreq = 0U;
 }
 
 static uint32_t SNVS_HP_RTC_GetSeconds(SNVS_Type *base)
 {
     uint32_t seconds = 0;
-    uint32_t tmp = 0;
+    uint32_t tmp     = 0;
 
     /* Do consecutive reads until value is correct */
     do
     {
         seconds = tmp;
-        tmp = (base->HPRTCMR << 17U) | (base->HPRTCLR >> 15U);
+        tmp     = (base->HPRTCMR << 17U) | (base->HPRTCLR >> 15U);
     } while (tmp != seconds);
 
     return seconds;
 }
 
+/*!
+ * brief Sets the SNVS RTC date and time according to the given time structure.
+ *
+ * param base     SNVS peripheral base address
+ * param datetime Pointer to the structure where the date and time details are stored.
+ *
+ * return kStatus_Success: Success in setting the time and starting the SNVS RTC
+ *         kStatus_InvalidArgument: Error because the datetime format is incorrect
+ */
 status_t SNVS_HP_RTC_SetDatetime(SNVS_Type *base, const snvs_hp_rtc_datetime_t *datetime)
 {
     assert(datetime);
 
     uint32_t seconds = 0U;
-    uint32_t tmp = base->HPCR;
+    uint32_t tmp     = base->HPCR;
 
     /* disable RTC */
     SNVS_HP_RTC_StopTimer(base);
@@ -352,6 +389,12 @@ status_t SNVS_HP_RTC_SetDatetime(SNVS_Type *base, const snvs_hp_rtc_datetime_t *
     return kStatus_Success;
 }
 
+/*!
+ * brief Gets the SNVS RTC time and stores it in the given time structure.
+ *
+ * param base     SNVS peripheral base address
+ * param datetime Pointer to the structure where the date and time details are stored.
+ */
 void SNVS_HP_RTC_GetDatetime(SNVS_Type *base, snvs_hp_rtc_datetime_t *datetime)
 {
     assert(datetime);
@@ -359,13 +402,27 @@ void SNVS_HP_RTC_GetDatetime(SNVS_Type *base, snvs_hp_rtc_datetime_t *datetime)
     SNVS_HP_ConvertSecondsToDatetime(SNVS_HP_RTC_GetSeconds(base), datetime);
 }
 
+/*!
+ * brief Sets the SNVS RTC alarm time.
+ *
+ * The function sets the RTC alarm. It also checks whether the specified alarm time
+ * is greater than the present time. If not, the function does not set the alarm
+ * and returns an error.
+ *
+ * param base      SNVS peripheral base address
+ * param alarmTime Pointer to the structure where the alarm time is stored.
+ *
+ * return kStatus_Success: success in setting the SNVS RTC alarm
+ *         kStatus_InvalidArgument: Error because the alarm datetime format is incorrect
+ *         kStatus_Fail: Error because the alarm time has already passed
+ */
 status_t SNVS_HP_RTC_SetAlarm(SNVS_Type *base, const snvs_hp_rtc_datetime_t *alarmTime)
 {
     assert(alarmTime);
 
     uint32_t alarmSeconds = 0U;
-    uint32_t currSeconds = 0U;
-    uint32_t tmp = base->HPCR;
+    uint32_t currSeconds  = 0U;
+    uint32_t tmp          = base->HPCR;
 
     /* Return error if the alarm time provided is not valid */
     if (!(SNVS_HP_CheckDatetimeFormat(alarmTime)))
@@ -374,7 +431,7 @@ status_t SNVS_HP_RTC_SetAlarm(SNVS_Type *base, const snvs_hp_rtc_datetime_t *ala
     }
 
     alarmSeconds = SNVS_HP_ConvertDatetimeToSeconds(alarmTime);
-    currSeconds = SNVS_HP_RTC_GetSeconds(base);
+    currSeconds  = SNVS_HP_RTC_GetSeconds(base);
 
     /* Return error if the alarm time has passed */
     if (alarmSeconds < currSeconds)
@@ -398,6 +455,12 @@ status_t SNVS_HP_RTC_SetAlarm(SNVS_Type *base, const snvs_hp_rtc_datetime_t *ala
     return kStatus_Success;
 }
 
+/*!
+ * brief Returns the SNVS RTC alarm time.
+ *
+ * param base     SNVS peripheral base address
+ * param datetime Pointer to the structure where the alarm date and time details are stored.
+ */
 void SNVS_HP_RTC_GetAlarm(SNVS_Type *base, snvs_hp_rtc_datetime_t *datetime)
 {
     assert(datetime);
@@ -411,6 +474,11 @@ void SNVS_HP_RTC_GetAlarm(SNVS_Type *base, snvs_hp_rtc_datetime_t *datetime)
 }
 
 #if (defined(FSL_FEATURE_SNVS_HAS_SRTC) && (FSL_FEATURE_SNVS_HAS_SRTC > 0))
+/*!
+ * brief The function synchronizes RTC counter value with SRTC.
+ *
+ * param base SNVS peripheral base address
+ */
 void SNVS_HP_RTC_TimeSynchronize(SNVS_Type *base)
 {
     uint32_t tmp = base->HPCR;
@@ -428,6 +496,14 @@ void SNVS_HP_RTC_TimeSynchronize(SNVS_Type *base)
 }
 #endif /* FSL_FEATURE_SNVS_HAS_SRTC */
 
+/*!
+ * brief Gets the SNVS status flags.
+ *
+ * param base SNVS peripheral base address
+ *
+ * return The status flags. This is the logical OR of members of the
+ *         enumeration ::snvs_status_flags_t
+ */
 uint32_t SNVS_HP_RTC_GetStatusFlags(SNVS_Type *base)
 {
     uint32_t flags = 0U;
@@ -445,6 +521,14 @@ uint32_t SNVS_HP_RTC_GetStatusFlags(SNVS_Type *base)
     return flags;
 }
 
+/*!
+ * brief Gets the enabled SNVS interrupts.
+ *
+ * param base SNVS peripheral base address
+ *
+ * return The enabled interrupts. This is the logical OR of members of the
+ *         enumeration ::snvs_interrupt_enable_t
+ */
 uint32_t SNVS_HP_RTC_GetEnabledInterrupts(SNVS_Type *base)
 {
     uint32_t val = 0U;
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_snvs_hp.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_snvs_hp.h
index 27bf7e66250..0b86d098506 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_snvs_hp.h
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_snvs_hp.h
@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright (c) 2017, NXP
+ * Copyright 2017-2018, NXP
  * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #ifndef _FSL_SNVS_HP_H_
@@ -48,23 +22,50 @@
 
 /*! @name Driver version */
 /*@{*/
-#define FSL_SNVS_HP_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */
+#define FSL_SNVS_HP_DRIVER_VERSION (MAKE_VERSION(2, 1, 2)) /*!< Version 2.1.2 */
 /*@}*/
 
 /*! @brief List of SNVS interrupts */
 typedef enum _snvs_hp_interrupts
 {
-    kSNVS_RTC_AlarmInterrupt = SNVS_HPCR_HPTA_EN_MASK,  /*!< RTC time alarm */
-    kSNVS_RTC_PeriodicInterrupt = SNVS_HPCR_PI_EN_MASK, /*!< RTC periodic interrupt */
+    kSNVS_RTC_AlarmInterrupt    = SNVS_HPCR_HPTA_EN_MASK, /*!< RTC time alarm */
+    kSNVS_RTC_PeriodicInterrupt = SNVS_HPCR_PI_EN_MASK,   /*!< RTC periodic interrupt */
 } snvs_hp_interrupts_t;
 
 /*! @brief List of SNVS flags */
 typedef enum _snvs_hp_status_flags
 {
-    kSNVS_RTC_AlarmInterruptFlag = SNVS_HPSR_HPTA_MASK,  /*!< RTC time alarm flag */
-    kSNVS_RTC_PeriodicInterruptFlag = SNVS_HPSR_PI_MASK, /*!< RTC periodic interrupt flag */
+    kSNVS_RTC_AlarmInterruptFlag    = SNVS_HPSR_HPTA_MASK,          /*!< RTC time alarm flag */
+    kSNVS_RTC_PeriodicInterruptFlag = SNVS_HPSR_PI_MASK,            /*!< RTC periodic interrupt flag */
+    kSNVS_ZMK_ZeroFlag              = (int)SNVS_HPSR_ZMK_ZERO_MASK, /*!< The ZMK is zero */
+    kSNVS_OTPMK_ZeroFlag            = SNVS_HPSR_OTPMK_ZERO_MASK,    /*!< The OTPMK is zero */
 } snvs_hp_status_flags_t;
 
+/*! @brief List of SNVS security violation flags */
+typedef enum _snvs_hp_sv_status_flags
+{
+    kSNVS_LP_ViolationFlag = SNVS_HPSVSR_SW_LPSV_MASK,           /*!< Low Power section Security Violation */
+    kSNVS_ZMK_EccFailFlag  = SNVS_HPSVSR_ZMK_ECC_FAIL_MASK,      /*!< Zeroizable Master Key Error Correcting Code Check
+                                                                   Failure */
+    kSNVS_LP_SoftwareViolationFlag   = SNVS_HPSVSR_SW_LPSV_MASK, /*!< LP Software Security Violation */
+    kSNVS_FatalSoftwareViolationFlag = SNVS_HPSVSR_SW_FSV_MASK,  /*!< Software Fatal Security Violation */
+    kSNVS_SoftwareViolationFlag      = SNVS_HPSVSR_SW_SV_MASK,   /*!< Software Security Violation */
+    kSNVS_Violation0Flag             = SNVS_HPSVSR_SV0_MASK,     /*!< Security Violation 0 */
+    kSNVS_Violation1Flag             = SNVS_HPSVSR_SV1_MASK,     /*!< Security Violation 1 */
+    kSNVS_Violation2Flag             = SNVS_HPSVSR_SV2_MASK,     /*!< Security Violation 2 */
+    kSNVS_Violation3Flag             = SNVS_HPSVSR_SV3_MASK,     /*!< Security Violation 3 */
+    kSNVS_Violation4Flag             = SNVS_HPSVSR_SV4_MASK,     /*!< Security Violation 4 */
+    kSNVS_Violation5Flag             = SNVS_HPSVSR_SV5_MASK,     /*!< Security Violation 5 */
+} snvs_hp_sv_status_flags_t;
+
+/*!
+ * @brief Macro to make security violation flag
+ *
+ * Macro help to make security violation flag kSNVS_Violation0Flag to kSNVS_Violation5Flag,
+ * For example, SNVS_MAKE_HP_SV_FLAG(0) is kSNVS_Violation0Flag.
+ */
+#define SNVS_MAKE_HP_SV_FLAG(x) (1U << (SNVS_HPSVSR_SV0_SHIFT + (x)))
+
 /*! @brief Structure is used to hold the date and time */
 typedef struct _snvs_hp_rtc_datetime
 {
@@ -95,6 +96,18 @@ typedef struct _snvs_hp_rtc_config
                                          Range from 0 to 15 */
 } snvs_hp_rtc_config_t;
 
+typedef enum _snvs_hp_ssm_state
+{
+    kSNVS_SSMInit      = 0x00, /*!< Init */
+    kSNVS_SSMHardFail  = 0x01, /*!< Hard Fail */
+    kSNVS_SSMSoftFail  = 0x03, /*!< Soft Fail */
+    kSNVS_SSMInitInter = 0x08, /*!< Init Intermediate (transition state between Init and Check) */
+    kSNVS_SSMCheck     = 0x09, /*!< Check */
+    kSNVS_SSMNonSecure = 0x0B, /*!< Non-Secure */
+    kSNVS_SSMTrusted   = 0x0D, /*!< Trusted */
+    kSNVS_SSMSecure    = 0x0F, /*!< Secure */
+} snvs_hp_ssm_state_t;
+
 /*******************************************************************************
  * API
  ******************************************************************************/
@@ -108,6 +121,22 @@ extern "C" {
  * @{
  */
 
+/*!
+ * @brief Initialize the SNVS.
+ *
+ * @note This API should be called at the beginning of the application using the SNVS driver.
+ *
+ * @param base SNVS peripheral base address
+ */
+void SNVS_HP_Init(SNVS_Type *base);
+
+/*!
+ * @brief Deinitialize the SNVS.
+ *
+ * @param base SNVS peripheral base address
+ */
+void SNVS_HP_Deinit(SNVS_Type *base);
+
 /*!
  * @brief Ungates the SNVS clock and configures the peripheral for basic operation.
  *
@@ -300,6 +329,280 @@ static inline void SNVS_HP_RTC_StopTimer(SNVS_Type *base)
     }
 }
 
+/*! @}*/
+
+/*!
+ * @brief Enable or disable master key selection.
+ *
+ * @param base SNVS peripheral base address
+ * @param enable Pass true to enable, false to disable.
+ */
+static inline void SNVS_HP_EnableMasterKeySelection(SNVS_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->HPCOMR |= SNVS_HPCOMR_MKS_EN_MASK;
+    }
+    else
+    {
+        base->HPCOMR &= (~SNVS_HPCOMR_MKS_EN_MASK);
+    }
+}
+
+/*!
+ * @brief Trigger to program Zeroizable Master Key.
+ *
+ * @param base SNVS peripheral base address
+ * @param enable Pass true to enable, false to disable.
+ */
+static inline void SNVS_HP_ProgramZeroizableMasterKey(SNVS_Type *base)
+{
+    base->HPCOMR |= SNVS_HPCOMR_PROG_ZMK_MASK;
+}
+
+/*!
+ * @brief Trigger SSM State Transition
+ *
+ * Trigger state transition of the system security monitor (SSM). It results only
+ * the following transitions of the SSM:
+ *   - Check State -> Non-Secure (when Non-Secure Boot and not in Fab Configuration)
+ *   - Check State --> Trusted (when Secure Boot or in Fab Configuration )
+ *   - Trusted State --> Secure
+ *   - Secure State --> Trusted
+ *   - Soft Fail --> Non-Secure
+ *
+ * @param base SNVS peripheral base address
+ */
+static inline void SNVS_HP_ChangeSSMState(SNVS_Type *base)
+{
+    base->HPCOMR |= SNVS_HPCOMR_SSM_ST_MASK;
+}
+
+/*!
+ * @brief Trigger Software Fatal Security Violation
+ *
+ * The result SSM state transition is:
+ *  - Check State -> Soft Fail
+ *  - Non-Secure State -> Soft Fail
+ *  - Trusted State -> Soft Fail
+ *  - Secure State -> Soft Fail
+ *
+ * @param base SNVS peripheral base address
+ */
+static inline void SNVS_HP_SetSoftwareFatalSecurityViolation(SNVS_Type *base)
+{
+    base->HPCOMR |= SNVS_HPCOMR_SW_FSV_MASK;
+}
+
+/*!
+ * @brief Trigger Software Security Violation
+ *
+ * The result SSM state transition is:
+ *  - Check -> Non-Secure
+ *  - Trusted -> Soft Fail
+ *  - Secure -> Soft Fail
+ *
+ * @param base SNVS peripheral base address
+ */
+static inline void SNVS_HP_SetSoftwareSecurityViolation(SNVS_Type *base)
+{
+    base->HPCOMR |= SNVS_HPCOMR_SW_SV_MASK;
+}
+
+/*!
+ * @brief Get current SSM State
+ *
+ * @param base SNVS peripheral base address
+ * @return Current SSM state
+ */
+static inline snvs_hp_ssm_state_t SNVS_HP_GetSSMState(SNVS_Type *base)
+{
+    return (snvs_hp_ssm_state_t)((base->HPSR & SNVS_HPSR_SSM_STATE_MASK) >> SNVS_HPSR_SSM_STATE_SHIFT);
+}
+
+/*!
+ * @brief Reset the SNVS LP section.
+ *
+ * Reset the LP section except SRTC and Time alarm.
+ *
+ * @param base SNVS peripheral base address
+ */
+static inline void SNVS_HP_ResetLP(SNVS_Type *base)
+{
+    base->HPCOMR |= SNVS_HPCOMR_LP_SWR_MASK;
+}
+
+/*!
+ * @name High Assurance Counter (HAC)
+ * @{
+ */
+
+/*!
+ * @brief Enable or disable the High Assurance Counter (HAC)
+ *
+ * @param base SNVS peripheral base address
+ * @param enable Pass true to enable, false to disable.
+ */
+static inline void SNVS_HP_EnableHighAssuranceCounter(SNVS_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->HPCOMR |= SNVS_HPCOMR_HAC_EN_MASK;
+    }
+    else
+    {
+        base->HPCOMR &= (~SNVS_HPCOMR_HAC_EN_MASK);
+    }
+}
+
+/*!
+ * @brief Start or stop the High Assurance Counter (HAC)
+ *
+ * @param base SNVS peripheral base address
+ * @param start Pass true to start, false to stop.
+ */
+static inline void SNVS_HP_StartHighAssuranceCounter(SNVS_Type *base, bool start)
+{
+    if (start)
+    {
+        base->HPCOMR &= (~SNVS_HPCOMR_HAC_STOP_MASK);
+    }
+    else
+    {
+        base->HPCOMR |= SNVS_HPCOMR_HAC_STOP_MASK;
+    }
+}
+
+/*!
+ * @brief Set the High Assurance Counter (HAC) initialize value.
+ *
+ * @param base SNVS peripheral base address
+ * @param value The initial value to set.
+ */
+static inline void SNVS_HP_SetHighAssuranceCounterInitialValue(SNVS_Type *base, uint32_t value)
+{
+    base->HPHACIVR = value;
+}
+
+/*!
+ * @brief Load the High Assurance Counter (HAC)
+ *
+ * This function loads the HAC initialize value to counter register.
+ *
+ * @param base SNVS peripheral base address
+ */
+static inline void SNVS_HP_LoadHighAssuranceCounter(SNVS_Type *base)
+{
+    base->HPCOMR |= SNVS_HPCOMR_HAC_LOAD_MASK;
+}
+
+/*!
+ * @brief Get the current High Assurance Counter (HAC) value
+ *
+ * @param base SNVS peripheral base address
+ * @return HAC currnet value.
+ */
+static inline uint32_t SNVS_HP_GetHighAssuranceCounter(SNVS_Type *base)
+{
+    return base->HPHACR;
+}
+
+/*!
+ * @brief Clear the High Assurance Counter (HAC)
+ *
+ * This function can be called in a functional or soft fail state. When the HAC
+ * is enabled:
+ *   - If the HAC is cleared in the soft fail state, the SSM transitions to the
+ * hard fail state immediately;
+ *   - If the HAC is cleared in functional state, the SSM will transition to
+ * hard fail immediately after transitioning to soft fail.
+ *
+ * @param base SNVS peripheral base address
+ */
+static inline void SNVS_HP_ClearHighAssuranceCounter(SNVS_Type *base)
+{
+    base->HPCOMR |= SNVS_HPCOMR_HAC_CLEAR_MASK;
+}
+
+/*!
+ * @brief Lock the High Assurance Counter (HAC)
+ *
+ * Once locked, the HAC initialize value could not be changed, the HAC enable
+ * status could not be changed. This could only be unlocked by system reset.
+ *
+ * @param base SNVS peripheral base address
+ */
+static inline void SNVS_HP_LockHighAssuranceCounter(SNVS_Type *base)
+{
+    base->HPLR |= SNVS_HPLR_HAC_L_MASK;
+}
+
+/*! @}*/
+
+/*!
+ * @brief Get the SNVS HP status flags.
+ *
+ * The flags are returned as the OR'ed value of @ref snvs_hp_sgtatus_flags_t.
+ *
+ * @param base SNVS peripheral base address
+ * @return The OR'ed value of status flags.
+ */
+static inline uint32_t SNVS_HP_GetStatusFlags(SNVS_Type *base)
+{
+    return base->HPSR;
+}
+
+/*!
+ * @brief Clear the SNVS HP status flags.
+ *
+ * The flags to clear are passed in as the OR'ed value of @ref snvs_hp_status_flags_t.
+ * Only these flags could be cleared using this API.
+ *  - @ref kSNVS_RTC_PeriodicInterruptFlag
+ *  - @ref kSNVS_RTC_AlarmInterruptFlag
+ *
+ * @param base SNVS peripheral base address
+ * @param mask OR'ed value of the flags to clear.
+ */
+static inline void SNVS_HP_ClearStatusFlags(SNVS_Type *base, uint32_t mask)
+{
+    base->HPSR = mask;
+}
+
+/*!
+ * @brief Get the SNVS HP security violation status flags.
+ *
+ * The flags are returned as the OR'ed value of @ref snvs_hp_sv_status_flags_t.
+ *
+ * @param base SNVS peripheral base address
+ * @return The OR'ed value of security violation status flags.
+ */
+static inline uint32_t SNVS_HP_GetSecurityViolationStatusFlags(SNVS_Type *base)
+{
+    return base->HPSVSR;
+}
+
+/*!
+ * @brief Clear the SNVS HP security violation status flags.
+ *
+ * The flags to clear are passed in as the OR'ed value of @ref snvs_hp_sv_status_flags_t.
+ * Only these flags could be cleared using this API.
+ *
+ *  - @ref kSNVS_ZMK_EccFailFlag
+ *  - @ref kSNVS_Violation0Flag
+ *  - @ref kSNVS_Violation1Flag
+ *  - @ref kSNVS_Violation2Flag
+ *  - @ref kSNVS_Violation3Flag
+ *  - @ref kSNVS_Violation4Flag
+ *  - @ref kSNVS_Violation5Flag
+ *
+ * @param base SNVS peripheral base address
+ * @param mask OR'ed value of the flags to clear.
+ */
+static inline void SNVS_HP_ClearSecurityViolationStatusFlags(SNVS_Type *base, uint32_t mask)
+{
+    base->HPSVSR = mask;
+}
+
 #if defined(__cplusplus)
 }
 #endif
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_snvs_lp.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_snvs_lp.c
index c9f539630e6..96f41cb054f 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_snvs_lp.c
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_snvs_lp.c
@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright (c) 2017, NXP
+ * Copyright 2017, NXP
  * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include "fsl_snvs_lp.h"
@@ -50,6 +24,8 @@
 #define YEAR_RANGE_START (1970U)
 #define YEAR_RANGE_END (2099U)
 
+#define SNVS_DEFAULT_PGD_VALUE (0x41736166U)
+
 /*******************************************************************************
  * Prototypes
  ******************************************************************************/
@@ -200,13 +176,13 @@ static void SNVS_LP_ConvertSecondsToDatetime(uint32_t seconds, snvs_lp_srtc_date
     secondsRemaining = secondsRemaining % SECONDS_IN_A_DAY;
 
     /* Calculate the datetime hour, minute and second fields */
-    datetime->hour = secondsRemaining / SECONDS_IN_A_HOUR;
+    datetime->hour   = secondsRemaining / SECONDS_IN_A_HOUR;
     secondsRemaining = secondsRemaining % SECONDS_IN_A_HOUR;
     datetime->minute = secondsRemaining / 60U;
     datetime->second = secondsRemaining % SECONDS_IN_A_MINUTE;
 
     /* Calculate year */
-    daysInYear = DAYS_IN_A_YEAR;
+    daysInYear     = DAYS_IN_A_YEAR;
     datetime->year = YEAR_RANGE_START;
     while (days > daysInYear)
     {
@@ -255,6 +231,49 @@ static uint32_t SNVS_LP_GetInstance(SNVS_Type *base)
 }
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
+/*!
+ * brief Ungates the SNVS clock and configures the peripheral for basic operation.
+ *
+ * note This API should be called at the beginning of the application using the SNVS driver.
+ *
+ * param base   SNVS peripheral base address
+ * param config Pointer to the user's SNVS configuration structure.
+ */
+void SNVS_LP_Init(SNVS_Type *base)
+{
+#if (!(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && \
+     defined(SNVS_LP_CLOCKS))
+    uint32_t instance = SNVS_LP_GetInstance(base);
+    CLOCK_EnableClock(s_snvsLpClock[instance]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+    /* Power glitch detector: set the PGD value and clear the previous status. */
+    base->LPPGDR = SNVS_DEFAULT_PGD_VALUE;
+    base->LPSR   = SNVS_LPSR_PGD_MASK;
+}
+
+/*!
+ * brief Deinit the SNVS LP section.
+ *
+ * param base SNVS peripheral base address
+ */
+void SNVS_LP_Deinit(SNVS_Type *base)
+{
+#if (!(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && \
+     defined(SNVS_LP_CLOCKS))
+    uint32_t instance = SNVS_LP_GetInstance(base);
+    CLOCK_DisableClock(s_snvsLpClock[instance]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}
+
+/*!
+ * brief Ungates the SNVS clock and configures the peripheral for basic operation.
+ *
+ * note This API should be called at the beginning of the application using the SNVS driver.
+ *
+ * param base   SNVS peripheral base address
+ * param config Pointer to the user's SNVS configuration structure.
+ */
 void SNVS_LP_SRTC_Init(SNVS_Type *base, const snvs_lp_srtc_config_t *config)
 {
     assert(config);
@@ -280,6 +299,11 @@ void SNVS_LP_SRTC_Init(SNVS_Type *base, const snvs_lp_srtc_config_t *config)
     }
 }
 
+/*!
+ * brief Stops the SRTC timer.
+ *
+ * param base SNVS peripheral base address
+ */
 void SNVS_LP_SRTC_Deinit(SNVS_Type *base)
 {
     base->LPCR &= ~SNVS_LPCR_SRTC_ENV_MASK;
@@ -291,35 +315,57 @@ void SNVS_LP_SRTC_Deinit(SNVS_Type *base)
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }
 
+/*!
+ * brief Fills in the SNVS_LP config struct with the default settings.
+ *
+ * The default values are as follows.
+ * code
+ *    config->srtccalenable = false;
+ *    config->srtccalvalue = 0U;
+ * endcode
+ * param config Pointer to the user's SNVS configuration structure.
+ */
 void SNVS_LP_SRTC_GetDefaultConfig(snvs_lp_srtc_config_t *config)
 {
     assert(config);
 
+    /* Initializes the configure structure to zero. */
+    memset(config, 0, sizeof(*config));
+
     config->srtcCalEnable = false;
-    config->srtcCalValue = 0U;
+    config->srtcCalValue  = 0U;
 }
 
 static uint32_t SNVS_LP_SRTC_GetSeconds(SNVS_Type *base)
 {
     uint32_t seconds = 0;
-    uint32_t tmp = 0;
+    uint32_t tmp     = 0;
 
     /* Do consecutive reads until value is correct */
     do
     {
         seconds = tmp;
-        tmp = (base->LPSRTCMR << 17U) | (base->LPSRTCLR >> 15U);
+        tmp     = (base->LPSRTCMR << 17U) | (base->LPSRTCLR >> 15U);
     } while (tmp != seconds);
 
     return seconds;
 }
 
+/*!
+ * brief Sets the SNVS SRTC date and time according to the given time structure.
+ *
+ * param base     SNVS peripheral base address
+ * param datetime Pointer to the structure where the date and time details are stored.
+ *
+ * return kStatus_Success: Success in setting the time and starting the SNVS SRTC
+ *         kStatus_InvalidArgument: Error because the datetime format is incorrect
+ */
 status_t SNVS_LP_SRTC_SetDatetime(SNVS_Type *base, const snvs_lp_srtc_datetime_t *datetime)
 {
     assert(datetime);
 
     uint32_t seconds = 0U;
-    uint32_t tmp = base->LPCR;
+    uint32_t tmp     = base->LPCR;
 
     /* disable RTC */
     SNVS_LP_SRTC_StopTimer(base);
@@ -345,6 +391,12 @@ status_t SNVS_LP_SRTC_SetDatetime(SNVS_Type *base, const snvs_lp_srtc_datetime_t
     return kStatus_Success;
 }
 
+/*!
+ * brief Gets the SNVS SRTC time and stores it in the given time structure.
+ *
+ * param base     SNVS peripheral base address
+ * param datetime Pointer to the structure where the date and time details are stored.
+ */
 void SNVS_LP_SRTC_GetDatetime(SNVS_Type *base, snvs_lp_srtc_datetime_t *datetime)
 {
     assert(datetime);
@@ -352,13 +404,31 @@ void SNVS_LP_SRTC_GetDatetime(SNVS_Type *base, snvs_lp_srtc_datetime_t *datetime
     SNVS_LP_ConvertSecondsToDatetime(SNVS_LP_SRTC_GetSeconds(base), datetime);
 }
 
+/*!
+ * brief Sets the SNVS SRTC alarm time.
+ *
+ * The function sets the SRTC alarm. It also checks whether the specified alarm
+ * time is greater than the present time. If not, the function does not set the alarm
+ * and returns an error.
+ * Please note, that SRTC alarm has limited resolution because only 32 most
+ * significant bits of SRTC counter are compared to SRTC Alarm register.
+ * If the alarm time is beyond SRTC resolution, the function does not set the alarm
+ * and returns an error.
+ *
+ * param base      SNVS peripheral base address
+ * param alarmTime Pointer to the structure where the alarm time is stored.
+ *
+ * return kStatus_Success: success in setting the SNVS SRTC alarm
+ *         kStatus_InvalidArgument: Error because the alarm datetime format is incorrect
+ *         kStatus_Fail: Error because the alarm time has already passed or is beyond resolution
+ */
 status_t SNVS_LP_SRTC_SetAlarm(SNVS_Type *base, const snvs_lp_srtc_datetime_t *alarmTime)
 {
     assert(alarmTime);
 
     uint32_t alarmSeconds = 0U;
-    uint32_t currSeconds = 0U;
-    uint32_t tmp = base->LPCR;
+    uint32_t currSeconds  = 0U;
+    uint32_t tmp          = base->LPCR;
 
     /* Return error if the alarm time provided is not valid */
     if (!(SNVS_LP_CheckDatetimeFormat(alarmTime)))
@@ -367,7 +437,7 @@ status_t SNVS_LP_SRTC_SetAlarm(SNVS_Type *base, const snvs_lp_srtc_datetime_t *a
     }
 
     alarmSeconds = SNVS_LP_ConvertDatetimeToSeconds(alarmTime);
-    currSeconds = SNVS_LP_SRTC_GetSeconds(base);
+    currSeconds  = SNVS_LP_SRTC_GetSeconds(base);
 
     /* Return error if the alarm time has passed */
     if (alarmSeconds <= currSeconds)
@@ -390,6 +460,12 @@ status_t SNVS_LP_SRTC_SetAlarm(SNVS_Type *base, const snvs_lp_srtc_datetime_t *a
     return kStatus_Success;
 }
 
+/*!
+ * brief Returns the SNVS SRTC alarm time.
+ *
+ * param base     SNVS peripheral base address
+ * param datetime Pointer to the structure where the alarm date and time details are stored.
+ */
 void SNVS_LP_SRTC_GetAlarm(SNVS_Type *base, snvs_lp_srtc_datetime_t *datetime)
 {
     assert(datetime);
@@ -402,6 +478,14 @@ void SNVS_LP_SRTC_GetAlarm(SNVS_Type *base, snvs_lp_srtc_datetime_t *datetime)
     SNVS_LP_ConvertSecondsToDatetime(alarmSeconds, datetime);
 }
 
+/*!
+ * brief Gets the SNVS status flags.
+ *
+ * param base SNVS peripheral base address
+ *
+ * return The status flags. This is the logical OR of members of the
+ *         enumeration ::snvs_status_flags_t
+ */
 uint32_t SNVS_LP_SRTC_GetStatusFlags(SNVS_Type *base)
 {
     uint32_t flags = 0U;
@@ -414,6 +498,14 @@ uint32_t SNVS_LP_SRTC_GetStatusFlags(SNVS_Type *base)
     return flags;
 }
 
+/*!
+ * brief Gets the enabled SNVS interrupts.
+ *
+ * param base SNVS peripheral base address
+ *
+ * return The enabled interrupts. This is the logical OR of members of the
+ *         enumeration ::snvs_interrupt_enable_t
+ */
 uint32_t SNVS_LP_SRTC_GetEnabledInterrupts(SNVS_Type *base)
 {
     uint32_t val = 0U;
@@ -426,6 +518,13 @@ uint32_t SNVS_LP_SRTC_GetEnabledInterrupts(SNVS_Type *base)
     return val;
 }
 
+/*!
+ * brief Enables the specified SNVS external tamper.
+ *
+ * param base SNVS peripheral base address
+ * param pin SNVS external tamper pin
+ * param polarity Polarity of external tamper
+ */
 void SNVS_LP_EnableExternalTamper(SNVS_Type *base,
                                   snvs_lp_external_tamper_t pin,
                                   snvs_lp_external_tamper_polarity_t polarity)
@@ -480,6 +579,12 @@ void SNVS_LP_EnableExternalTamper(SNVS_Type *base,
     }
 }
 
+/*!
+ * brief Disables the specified SNVS external tamper.
+ *
+ * param base SNVS peripheral base address
+ * param pin SNVS external tamper pin
+ */
 void SNVS_LP_DisableExternalTamper(SNVS_Type *base, snvs_lp_external_tamper_t pin)
 {
     switch (pin)
@@ -521,6 +626,14 @@ void SNVS_LP_DisableExternalTamper(SNVS_Type *base, snvs_lp_external_tamper_t pi
     }
 }
 
+/*!
+ * brief Returns status of the specified external tamper.
+ *
+ * param base SNVS peripheral base address
+ * param pin SNVS external tamper pin
+ *
+ * return The status flag. This is the enumeration ::snvs_external_tamper_status_t
+ */
 snvs_lp_external_tamper_status_t SNVS_LP_GetExternalTamperStatus(SNVS_Type *base, snvs_lp_external_tamper_t pin)
 {
     snvs_lp_external_tamper_status_t status = kSNVS_TamperNotDetected;
@@ -565,6 +678,12 @@ snvs_lp_external_tamper_status_t SNVS_LP_GetExternalTamperStatus(SNVS_Type *base
     return status;
 }
 
+/*!
+ * brief Clears status of the specified external tamper.
+ *
+ * param base SNVS peripheral base address
+ * param pin SNVS external tamper pin
+ */
 void SNVS_LP_ClearExternalTamperStatus(SNVS_Type *base, snvs_lp_external_tamper_t pin)
 {
     base->LPSR |= SNVS_LPSR_ET1D_MASK;
@@ -607,3 +726,35 @@ void SNVS_LP_ClearExternalTamperStatus(SNVS_Type *base, snvs_lp_external_tamper_
             break;
     }
 }
+
+/*!
+ * brief Get the current Monotonic Counter.
+ *
+ * param base SNVS peripheral base address
+ * return Current Monotonic Counter value.
+ */
+uint64_t SNVS_LP_GetMonotonicCounter(SNVS_Type *base)
+{
+    uint32_t mc_lsb, mc_msb;
+
+    mc_msb = base->LPSMCMR;
+    mc_lsb = base->LPSMCLR;
+
+    return ((uint64_t)mc_msb << 32UL) | (uint64_t)mc_lsb;
+}
+
+/*!
+ * brief Write Zeroizable Master Key (ZMK) to the SNVS registers.
+ *
+ * param base SNVS peripheral base address
+ * param ZMKey The ZMK write to the SNVS register.
+ */
+void SNVS_LP_WriteZeroizableMasterKey(SNVS_Type *base, uint32_t ZMKey[SNVS_ZMK_REG_COUNT])
+{
+    uint8_t i = 0;
+
+    for (i = 0; i < SNVS_ZMK_REG_COUNT; i++)
+    {
+        base->LPZMKR[i] = ZMKey[i];
+    }
+}
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_snvs_lp.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_snvs_lp.h
index bd61d52ddb4..7f012ccd8aa 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_snvs_lp.h
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_snvs_lp.h
@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright (c) 2017, NXP
+ * Copyright 2017, NXP
  * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #ifndef _FSL_SNVS_LP_H_
@@ -48,9 +22,11 @@
 
 /*! @name Driver version */
 /*@{*/
-#define FSL_SNVS_LP_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */
+#define FSL_SNVS_LP_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) /*!< Version 2.1.0 */
 /*@}*/
 
+#define SNVS_ZMK_REG_COUNT 8 /* 8 Zeroizable Master Key registers. */
+
 /*! @brief List of SNVS_LP interrupts */
 typedef enum _snvs_lp_srtc_interrupts
 {
@@ -68,14 +44,14 @@ typedef enum _snvs_lp_external_tamper
 {
     kSNVS_ExternalTamper1 = 1U,
 #if defined(FSL_FEATURE_SNVS_HAS_MULTIPLE_TAMPER) && (FSL_FEATURE_SNVS_HAS_MULTIPLE_TAMPER > 1)
-    kSNVS_ExternalTamper2 = 2U,
-    kSNVS_ExternalTamper3 = 3U,
-    kSNVS_ExternalTamper4 = 4U,
-    kSNVS_ExternalTamper5 = 5U,
-    kSNVS_ExternalTamper6 = 6U,
-    kSNVS_ExternalTamper7 = 7U,
-    kSNVS_ExternalTamper8 = 8U,
-    kSNVS_ExternalTamper9 = 9U,
+    kSNVS_ExternalTamper2  = 2U,
+    kSNVS_ExternalTamper3  = 3U,
+    kSNVS_ExternalTamper4  = 4U,
+    kSNVS_ExternalTamper5  = 5U,
+    kSNVS_ExternalTamper6  = 6U,
+    kSNVS_ExternalTamper7  = 7U,
+    kSNVS_ExternalTamper8  = 8U,
+    kSNVS_ExternalTamper9  = 9U,
     kSNVS_ExternalTamper10 = 10U
 #endif
 } snvs_lp_external_tamper_t;
@@ -91,13 +67,13 @@ typedef enum _snvs_lp_external_tamper
 typedef enum _snvs_lp_external_tamper_status
 {
     kSNVS_TamperNotDetected = 0U,
-    kSNVS_TamperDetected = 1U
+    kSNVS_TamperDetected    = 1U
 } snvs_lp_external_tamper_status_t;
 
 /*! @brief SNVS_LP external tamper polarity */
 typedef enum _snvs_lp_external_tamper_polarity
 {
-    kSNVS_ExternalTamperActiveLow = 0U,
+    kSNVS_ExternalTamperActiveLow  = 0U,
     kSNVS_ExternalTamperActiveHigh = 1U
 } snvs_lp_external_tamper_polarity_t;
 
@@ -129,6 +105,25 @@ typedef struct _snvs_lp_srtc_config
                                 This is a 5-bit 2's complement value, range from -16 to +15 */
 } snvs_lp_srtc_config_t;
 
+/*!
+ * @brief SNVS_LP Zeroizable Master Key programming mode.
+ */
+typedef enum _snvs_lp_zmk_program_mode
+{
+    kSNVS_ZMKSoftwareProgram, /*!< Software programming mode. */
+    kSNVS_ZMKHardwareProgram, /*!< Hardware programming mode. */
+} snvs_lp_zmk_program_mode_t;
+
+/*!
+ * @brief SNVS_LP Master Key mode.
+ */
+typedef enum _snvs_lp_master_key_mode
+{
+    kSNVS_OTPMK = 0, /*!< One Time Programmable Master Key. */
+    kSNVS_ZMK   = 2, /*!< Zeroizable Master Key. */
+    kSNVS_CMK   = 3, /*!< Combined Master Key, it is XOR of OPTMK and ZMK. */
+} snvs_lp_master_key_mode_t;
+
 /*******************************************************************************
  * API
  ******************************************************************************/
@@ -142,6 +137,25 @@ extern "C" {
  * @{
  */
 
+/*!
+ * @brief Ungates the SNVS clock and configures the peripheral for basic operation.
+ *
+ * @note This API should be called at the beginning of the application using the SNVS driver.
+ *
+ * @param base   SNVS peripheral base address
+ * @param config Pointer to the user's SNVS configuration structure.
+ */
+void SNVS_LP_Init(SNVS_Type *base);
+
+/*!
+ * @brief Deinit the SNVS LP section.
+ *
+ * @param base SNVS peripheral base address
+ */
+void SNVS_LP_Deinit(SNVS_Type *base);
+
+/*! @}*/
+
 /*!
  * @brief Ungates the SNVS clock and configures the peripheral for basic operation.
  *
@@ -171,8 +185,6 @@ void SNVS_LP_SRTC_Deinit(SNVS_Type *base);
  */
 void SNVS_LP_SRTC_GetDefaultConfig(snvs_lp_srtc_config_t *config);
 
-/*! @}*/
-
 /*!
  * @name Secure RTC (SRTC) current Time & Alarm
  * @{
@@ -372,6 +384,155 @@ snvs_lp_external_tamper_status_t SNVS_LP_GetExternalTamperStatus(SNVS_Type *base
  */
 void SNVS_LP_ClearExternalTamperStatus(SNVS_Type *base, snvs_lp_external_tamper_t pin);
 
+/*! @}*/
+
+/*!
+ * @name Monotonic Counter (MC)
+ * @{
+ */
+
+/*!
+ * @brief Enable or disable the Monotonic Counter.
+ *
+ * @param base SNVS peripheral base address
+ * @param enable Pass true to enable, false to disable.
+ */
+static inline void SNVS_LP_EnableMonotonicCounter(SNVS_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->LPCR |= SNVS_LPCR_MC_ENV_MASK;
+    }
+    else
+    {
+        base->LPCR &= (~SNVS_LPCR_MC_ENV_MASK);
+    }
+}
+
+/*!
+ * @brief Get the current Monotonic Counter.
+ *
+ * @param base SNVS peripheral base address
+ * @return Current Monotonic Counter value.
+ */
+uint64_t SNVS_LP_GetMonotonicCounter(SNVS_Type *base);
+
+/*!
+ * @brief Increase the Monotonic Counter.
+ *
+ * Increase the Monotonic Counter by 1.
+ *
+ * @param base SNVS peripheral base address
+ */
+static inline void SNVS_LP_IncreaseMonotonicCounter(SNVS_Type *base)
+{
+    /* Write to the LPSMCLR or LPSMCLR, the counter increases. */
+    *((volatile uint32_t *)(&(base->LPSMCLR))) = 0xFFFFFFFFU;
+}
+
+/*! @}*/
+
+/*!
+ * @name Zeroizable Master Key (ZMK)
+ * @{
+ */
+
+/*!
+ * @brief Write Zeroizable Master Key (ZMK) to the SNVS registers.
+ *
+ * @param base SNVS peripheral base address
+ * @param ZMKey The ZMK write to the SNVS register.
+ */
+void SNVS_LP_WriteZeroizableMasterKey(SNVS_Type *base, uint32_t ZMKey[SNVS_ZMK_REG_COUNT]);
+
+/*!
+ * @brief Set Zeroizable Master Key valid.
+ *
+ * This API could only be called when using software programming mode. After writing
+ * ZMK using @ref SNVS_LP_WriteZeroizableMasterKey, call this API to make the ZMK
+ * valid.
+ *
+ * @param base SNVS peripheral base address
+ * @param valid Pass true to set valid, false to set invalid.
+ */
+static inline void SNVS_LP_SetZeroizableMasterKeyValid(SNVS_Type *base, bool valid)
+{
+    if (valid)
+    {
+        base->LPMKCR |= SNVS_LPMKCR_ZMK_VAL_MASK;
+    }
+    else
+    {
+        base->LPMKCR &= (~SNVS_LPMKCR_ZMK_VAL_MASK);
+    }
+}
+
+/*!
+ * @brief Get Zeroizable Master Key valid status.
+ *
+ * In hardware programming mode, call this API to check whether the ZMK is valid.
+ *
+ * @param base SNVS peripheral base address
+ * @return true if valid, false if invalid.
+ */
+static inline bool SNVS_LP_GetZeroizableMasterKeyValid(SNVS_Type *base)
+{
+    return (SNVS_LPMKCR_ZMK_VAL_MASK == (base->LPMKCR & SNVS_LPMKCR_ZMK_VAL_MASK));
+}
+
+/*!
+ * @brief Set Zeroizable Master Key programming mode.
+ *
+ * @param base SNVS peripheral base address
+ * @param mode ZMK programming mode.
+ */
+static inline void SNVS_LP_SetZeroizableMasterKeyProgramMode(SNVS_Type *base, snvs_lp_zmk_program_mode_t mode)
+{
+    if (kSNVS_ZMKSoftwareProgram == mode)
+    {
+        base->LPMKCR &= (~SNVS_LPMKCR_ZMK_HWP_MASK);
+    }
+    else
+    {
+        base->LPMKCR |= SNVS_LPMKCR_ZMK_HWP_MASK;
+    }
+}
+
+/*!
+ * @brief Enable or disable Zeroizable Master Key ECC.
+ *
+ * @param base SNVS peripheral base address
+ * @param enable Pass true to enable, false to disable.
+ */
+static inline void SNVS_LP_EnableZeroizableMasterKeyECC(SNVS_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->LPMKCR |= SNVS_LPMKCR_ZMK_ECC_EN_MASK;
+    }
+    else
+    {
+        base->LPMKCR &= (~SNVS_LPMKCR_ZMK_ECC_EN_MASK);
+    }
+}
+
+/*!
+ * @brief Set SNVS Master Key mode.
+ *
+ * @param base SNVS peripheral base address
+ * @param mode Master Key mode.
+ * @note When @ref kSNVS_ZMK or @ref kSNVS_CMK used, the SNVS_HP must be configured
+ * to enable the master key selection.
+ */
+static inline void SNVS_LP_SetMasterKeyMode(SNVS_Type *base, snvs_lp_master_key_mode_t mode)
+{
+    uint32_t lpmkcr = base->LPMKCR;
+    lpmkcr          = (lpmkcr & (~SNVS_LPMKCR_MASTER_KEY_SEL_MASK)) | SNVS_LPMKCR_MASTER_KEY_SEL(mode);
+    base->LPMKCR    = lpmkcr;
+}
+
+/*! @}*/
+
 #if defined(__cplusplus)
 }
 #endif
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_spdif.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_spdif.c
index 80b3229e200..2431301b5e7 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_spdif.c
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_spdif.c
@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
- * Copyright (c) 2017, NXP Semiconductor, Inc.
+ * Copyright 2017, NXP
  * All rights reserved.
  *
- * 
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include "fsl_spdif.h"
@@ -39,7 +13,6 @@
 #define FSL_COMPONENT_ID "platform.drivers.spdif"
 #endif
 
-
 /*******************************************************************************
  * Definitations
  ******************************************************************************/
@@ -47,7 +20,7 @@ enum _spdif_transfer_state
 {
     kSPDIF_Busy = 0x0U, /*!< SPDIF is busy */
     kSPDIF_Idle,        /*!< Transfer is done. */
-    kSPDIF_Error        /*!< Transfer error occured. */
+    kSPDIF_Error        /*!< Transfer error occurred. */
 };
 
 /*! @brief Typedef for spdif tx interrupt handler. */
@@ -81,7 +54,7 @@ static spdif_isr_t s_spdifTxIsr;
 /*! @brief Pointer to IRQ handler for each instance. */
 static spdif_isr_t s_spdifRxIsr;
 /*! @brief Used for spdif gain */
-static uint8_t s_spdif_gain[8] = {24U, 16U, 12U, 8U, 6U, 4U, 3U, 1U};
+static uint8_t s_spdif_gain[8]         = {24U, 16U, 12U, 8U, 6U, 4U, 3U, 1U};
 static uint8_t s_spdif_tx_watermark[4] = {16, 12, 8, 4};
 static uint8_t s_spdif_rx_watermark[4] = {1, 4, 8, 16};
 
@@ -106,6 +79,20 @@ uint32_t SPDIF_GetInstance(SPDIF_Type *base)
     return instance;
 }
 
+/*!
+ * brief Initializes the SPDIF peripheral.
+ *
+ * Ungates the SPDIF clock, resets the module, and configures SPDIF with a configuration structure.
+ * The configuration structure can be custom filled or set with default values by
+ * SPDIF_GetDefaultConfig().
+ *
+ * note  This API should be called at the beginning of the application to use
+ * the SPDIF driver. Otherwise, accessing the SPDIF module can cause a hard fault
+ * because the clock is not enabled.
+ *
+ * param base SPDIF base pointer
+ * param config SPDIF configuration structure.
+ */
 void SPDIF_Init(SPDIF_Type *base, const spdif_config_t *config)
 {
     uint32_t val = 0;
@@ -138,6 +125,13 @@ void SPDIF_Init(SPDIF_Type *base, const spdif_config_t *config)
     base->STC = val;
 }
 
+/*!
+ * brief De-initializes the SPDIF peripheral.
+ *
+ * This API gates the SPDIF clock. The SPDIF module can't operate unless SPDIF_Init is called to enable the clock.
+ *
+ * param base SPDIF base pointer
+ */
 void SPDIF_Deinit(SPDIF_Type *base)
 {
     SPDIF_TxEnable(base, false);
@@ -147,20 +141,43 @@ void SPDIF_Deinit(SPDIF_Type *base)
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }
 
+/*!
+ * brief  Sets the SPDIF configuration structure to default values.
+ *
+ * This API initializes the configuration structure for use in SPDIF_Init.
+ * The initialized structure can remain unchanged in SPDIF_Init, or it can be modified
+ *  before calling SPDIF_Init.
+ * This is an example.
+   code
+   spdif_config_t config;
+   SPDIF_GetDefaultConfig(&config);
+   endcode
+ *
+ * param config pointer to master configuration structure
+ */
 void SPDIF_GetDefaultConfig(spdif_config_t *config)
 {
-    config->isTxAutoSync = true;
-    config->isRxAutoSync = true;
-    config->DPLLClkSource = 1;
-    config->txClkSource = 1;
-    config->rxFullSelect = kSPDIF_RxFull8Samples;
-    config->txFullSelect = kSPDIF_TxEmpty8Samples;
-    config->uChannelSrc = kSPDIF_UChannelFromTx;
-    config->txSource = kSPDIF_txNormal;
+    /* Initializes the configure structure to zero. */
+    memset(config, 0, sizeof(*config));
+
+    config->isTxAutoSync   = true;
+    config->isRxAutoSync   = true;
+    config->DPLLClkSource  = 1;
+    config->txClkSource    = 1;
+    config->rxFullSelect   = kSPDIF_RxFull8Samples;
+    config->txFullSelect   = kSPDIF_TxEmpty8Samples;
+    config->uChannelSrc    = kSPDIF_UChannelFromTx;
+    config->txSource       = kSPDIF_txNormal;
     config->validityConfig = kSPDIF_validityFlagAlwaysClear;
-    config->gain = kSPDIF_GAIN_8;
+    config->gain           = kSPDIF_GAIN_8;
 }
 
+/*!
+ * brief Enables/disables the SPDIF Tx.
+ *
+ * param base SPDIF base pointer
+ * param enable True means enable SPDIF Tx, false means disable.
+ */
 void SPDIF_TxEnable(SPDIF_Type *base, bool enable)
 {
     uint32_t val = 0;
@@ -182,11 +199,20 @@ void SPDIF_TxEnable(SPDIF_Type *base, bool enable)
     }
 }
 
+/*!
+ * brief Configures the SPDIF Tx sample rate.
+ *
+ * The audio format can be changed at run-time. This function configures the sample rate.
+ *
+ * param base SPDIF base pointer.
+ * param sampleRate_Hz SPDIF sample rate frequency in Hz.
+ * param sourceClockFreq_Hz SPDIF tx clock source frequency in Hz.
+ */
 void SPDIF_TxSetSampleRate(SPDIF_Type *base, uint32_t sampleRate_Hz, uint32_t sourceClockFreq_Hz)
 {
-    uint32_t clkDiv = sourceClockFreq_Hz / (sampleRate_Hz * 64);
-    uint32_t mod = sourceClockFreq_Hz % (sampleRate_Hz * 64);
-    uint32_t val = 0;
+    uint32_t clkDiv     = sourceClockFreq_Hz / (sampleRate_Hz * 64);
+    uint32_t mod        = sourceClockFreq_Hz % (sampleRate_Hz * 64);
+    uint32_t val        = 0;
     uint8_t clockSource = (((base->STC) & SPDIF_STC_TXCLK_SOURCE_MASK) >> SPDIF_STC_TXCLK_SOURCE_SHIFT);
 
     /* Compute the nearest divider */
@@ -220,9 +246,18 @@ void SPDIF_TxSetSampleRate(SPDIF_Type *base, uint32_t sampleRate_Hz, uint32_t so
     }
 }
 
+/*!
+ * brief Configures the SPDIF Rx audio format.
+ *
+ * The audio format can be changed at run-time. This function configures the sample rate and audio data
+ * format to be transferred.
+ *
+ * param base SPDIF base pointer.
+ * param clockSourceFreq_Hz SPDIF system clock frequency in hz.
+ */
 uint32_t SPDIF_GetRxSampleRate(SPDIF_Type *base, uint32_t clockSourceFreq_Hz)
 {
-    uint32_t gain = s_spdif_gain[((base->SRPC & SPDIF_SRPC_GAINSEL_MASK) >> SPDIF_SRPC_GAINSEL_SHIFT)];
+    uint32_t gain    = s_spdif_gain[((base->SRPC & SPDIF_SRPC_GAINSEL_MASK) >> SPDIF_SRPC_GAINSEL_SHIFT)];
     uint32_t measure = 0, sampleRate = 0;
     uint64_t temp = 0;
 
@@ -233,17 +268,26 @@ uint32_t SPDIF_GetRxSampleRate(SPDIF_Type *base, uint32_t clockSourceFreq_Hz)
 
     /* Get the measure value */
     measure = base->SRFM;
-    temp = (uint64_t)measure * (uint64_t)clockSourceFreq_Hz;
+    temp    = (uint64_t)measure * (uint64_t)clockSourceFreq_Hz;
     temp /= (uint64_t)(1024 * 1024 * 128 * gain);
     sampleRate = (uint32_t)temp;
 
     return sampleRate;
 }
 
+/*!
+ * brief Sends data using a blocking method.
+ *
+ * note This function blocks by polling until data is ready to be sent.
+ *
+ * param base SPDIF base pointer.
+ * param buffer Pointer to the data to be written.
+ * param size Bytes to be written.
+ */
 void SPDIF_WriteBlocking(SPDIF_Type *base, uint8_t *buffer, uint32_t size)
 {
     assert(buffer);
-    assert(size / 6U == 0U);
+    assert(size % 6U == 0U);
 
     uint32_t i = 0, j = 0, data = 0;
 
@@ -275,10 +319,19 @@ void SPDIF_WriteBlocking(SPDIF_Type *base, uint8_t *buffer, uint32_t size)
     }
 }
 
+/*!
+ * brief Receives data using a blocking method.
+ *
+ * note This function blocks by polling until data is ready to be sent.
+ *
+ * param base SPDIF base pointer.
+ * param buffer Pointer to the data to be read.
+ * param size Bytes to be read.
+ */
 void SPDIF_ReadBlocking(SPDIF_Type *base, uint8_t *buffer, uint32_t size)
 {
     assert(buffer);
-    assert(size / 6U == 0U);
+    assert(size % 6U == 0U);
 
     uint32_t i = 0, j = 0, data = 0;
 
@@ -309,6 +362,17 @@ void SPDIF_ReadBlocking(SPDIF_Type *base, uint8_t *buffer, uint32_t size)
     }
 }
 
+/*!
+ * brief Initializes the SPDIF Tx handle.
+ *
+ * This function initializes the Tx handle for the SPDIF Tx transactional APIs. Call
+ * this function once to get the handle initialized.
+ *
+ * param base SPDIF base pointer
+ * param handle SPDIF handle pointer.
+ * param callback Pointer to the user callback function.
+ * param userData User parameter passed to the callback function
+ */
 void SPDIF_TransferTxCreateHandle(SPDIF_Type *base,
                                   spdif_handle_t *handle,
                                   spdif_transfer_callback_t callback,
@@ -333,6 +397,17 @@ void SPDIF_TransferTxCreateHandle(SPDIF_Type *base,
     EnableIRQ(s_spdifIRQ[SPDIF_GetInstance(base)]);
 }
 
+/*!
+ * brief Initializes the SPDIF Rx handle.
+ *
+ * This function initializes the Rx handle for the SPDIF Rx transactional APIs. Call
+ * this function once to get the handle initialized.
+ *
+ * param base SPDIF base pointer.
+ * param handle SPDIF handle pointer.
+ * param callback Pointer to the user callback function.
+ * param userData User parameter passed to the callback function.
+ */
 void SPDIF_TransferRxCreateHandle(SPDIF_Type *base,
                                   spdif_handle_t *handle,
                                   spdif_transfer_callback_t callback,
@@ -357,6 +432,21 @@ void SPDIF_TransferRxCreateHandle(SPDIF_Type *base,
     EnableIRQ(s_spdifIRQ[SPDIF_GetInstance(base)]);
 }
 
+/*!
+ * brief Performs an interrupt non-blocking send transfer on SPDIF.
+ *
+ * note This API returns immediately after the transfer initiates.
+ * Call the SPDIF_TxGetTransferStatusIRQ to poll the transfer status and check whether
+ * the transfer is finished. If the return status is not kStatus_SPDIF_Busy, the transfer
+ * is finished.
+ *
+ * param base SPDIF base pointer.
+ * param handle Pointer to the spdif_handle_t structure which stores the transfer state.
+ * param xfer Pointer to the spdif_transfer_t structure.
+ * retval kStatus_Success Successfully started the data receive.
+ * retval kStatus_SPDIF_TxBusy Previous receive still not finished.
+ * retval kStatus_InvalidArgument The input parameter is invalid.
+ */
 status_t SPDIF_TransferSendNonBlocking(SPDIF_Type *base, spdif_handle_t *handle, spdif_transfer_t *xfer)
 {
     assert(handle);
@@ -368,10 +458,10 @@ status_t SPDIF_TransferSendNonBlocking(SPDIF_Type *base, spdif_handle_t *handle,
     }
 
     /* Add into queue */
-    handle->transferSize[handle->queueUser] = xfer->dataSize;
-    handle->spdifQueue[handle->queueUser].data = xfer->data;
+    handle->transferSize[handle->queueUser]        = xfer->dataSize;
+    handle->spdifQueue[handle->queueUser].data     = xfer->data;
     handle->spdifQueue[handle->queueUser].dataSize = xfer->dataSize;
-    handle->queueUser = (handle->queueUser + 1) % SPDIF_XFER_QUEUE_SIZE;
+    handle->queueUser                              = (handle->queueUser + 1) % SPDIF_XFER_QUEUE_SIZE;
 
     /* Set the state to busy */
     handle->state = kSPDIF_Busy;
@@ -385,6 +475,21 @@ status_t SPDIF_TransferSendNonBlocking(SPDIF_Type *base, spdif_handle_t *handle,
     return kStatus_Success;
 }
 
+/*!
+ * brief Performs an interrupt non-blocking receive transfer on SPDIF.
+ *
+ * note This API returns immediately after the transfer initiates.
+ * Call the SPDIF_RxGetTransferStatusIRQ to poll the transfer status and check whether
+ * the transfer is finished. If the return status is not kStatus_SPDIF_Busy, the transfer
+ * is finished.
+ *
+ * param base SPDIF base pointer
+ * param handle Pointer to the spdif_handle_t structure which stores the transfer state.
+ * param xfer Pointer to the spdif_transfer_t structure.
+ * retval kStatus_Success Successfully started the data receive.
+ * retval kStatus_SPDIF_RxBusy Previous receive still not finished.
+ * retval kStatus_InvalidArgument The input parameter is invalid.
+ */
 status_t SPDIF_TransferReceiveNonBlocking(SPDIF_Type *base, spdif_handle_t *handle, spdif_transfer_t *xfer)
 {
     assert(handle);
@@ -396,12 +501,12 @@ status_t SPDIF_TransferReceiveNonBlocking(SPDIF_Type *base, spdif_handle_t *hand
     }
 
     /* Add into queue */
-    handle->transferSize[handle->queueUser] = xfer->dataSize;
-    handle->spdifQueue[handle->queueUser].data = xfer->data;
+    handle->transferSize[handle->queueUser]        = xfer->dataSize;
+    handle->spdifQueue[handle->queueUser].data     = xfer->data;
     handle->spdifQueue[handle->queueUser].dataSize = xfer->dataSize;
-    handle->spdifQueue[handle->queueUser].udata = xfer->udata;
-    handle->spdifQueue[handle->queueUser].qdata = xfer->qdata;
-    handle->queueUser = (handle->queueUser + 1) % SPDIF_XFER_QUEUE_SIZE;
+    handle->spdifQueue[handle->queueUser].udata    = xfer->udata;
+    handle->spdifQueue[handle->queueUser].qdata    = xfer->qdata;
+    handle->queueUser                              = (handle->queueUser + 1) % SPDIF_XFER_QUEUE_SIZE;
 
     /* Set state to busy */
     handle->state = kSPDIF_Busy;
@@ -416,6 +521,15 @@ status_t SPDIF_TransferReceiveNonBlocking(SPDIF_Type *base, spdif_handle_t *hand
     return kStatus_Success;
 }
 
+/*!
+ * brief Gets a set byte count.
+ *
+ * param base SPDIF base pointer.
+ * param handle Pointer to the spdif_handle_t structure which stores the transfer state.
+ * param count Bytes count sent.
+ * retval kStatus_Success Succeed get the transfer count.
+ * retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress.
+ */
 status_t SPDIF_TransferGetSendCount(SPDIF_Type *base, spdif_handle_t *handle, size_t *count)
 {
     assert(handle);
@@ -434,6 +548,15 @@ status_t SPDIF_TransferGetSendCount(SPDIF_Type *base, spdif_handle_t *handle, si
     return status;
 }
 
+/*!
+ * brief Gets a received byte count.
+ *
+ * param base SPDIF base pointer.
+ * param handle Pointer to the spdif_handle_t structure which stores the transfer state.
+ * param count Bytes count received.
+ * retval kStatus_Success Succeed get the transfer count.
+ * retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress.
+ */
 status_t SPDIF_TransferGetReceiveCount(SPDIF_Type *base, spdif_handle_t *handle, size_t *count)
 {
     assert(handle);
@@ -452,6 +575,15 @@ status_t SPDIF_TransferGetReceiveCount(SPDIF_Type *base, spdif_handle_t *handle,
     return status;
 }
 
+/*!
+ * brief Aborts the current send.
+ *
+ * note This API can be called any time when an interrupt non-blocking transfer initiates
+ * to abort the transfer early.
+ *
+ * param base SPDIF base pointer.
+ * param handle Pointer to the spdif_handle_t structure which stores the transfer state.
+ */
 void SPDIF_TransferAbortSend(SPDIF_Type *base, spdif_handle_t *handle)
 {
     assert(handle);
@@ -464,9 +596,18 @@ void SPDIF_TransferAbortSend(SPDIF_Type *base, spdif_handle_t *handle)
     /* Clear the queue */
     memset(handle->spdifQueue, 0, sizeof(spdif_transfer_t) * SPDIF_XFER_QUEUE_SIZE);
     handle->queueDriver = 0;
-    handle->queueUser = 0;
+    handle->queueUser   = 0;
 }
 
+/*!
+ * brief Aborts the current IRQ receive.
+ *
+ * note This API can be called when an interrupt non-blocking transfer initiates
+ * to abort the transfer early.
+ *
+ * param base SPDIF base pointer
+ * param handle Pointer to the spdif_handle_t structure which stores the transfer state.
+ */
 void SPDIF_TransferAbortReceive(SPDIF_Type *base, spdif_handle_t *handle)
 {
     assert(handle);
@@ -480,14 +621,20 @@ void SPDIF_TransferAbortReceive(SPDIF_Type *base, spdif_handle_t *handle)
     /* Clear the queue */
     memset(handle->spdifQueue, 0, sizeof(spdif_transfer_t) * SPDIF_XFER_QUEUE_SIZE);
     handle->queueDriver = 0;
-    handle->queueUser = 0;
+    handle->queueUser   = 0;
 }
 
+/*!
+ * brief Tx interrupt handler.
+ *
+ * param base SPDIF base pointer.
+ * param handle Pointer to the spdif_handle_t structure.
+ */
 void SPDIF_TransferTxHandleIRQ(SPDIF_Type *base, spdif_handle_t *handle)
 {
     assert(handle);
 
-    uint8_t *buffer = handle->spdifQueue[handle->queueDriver].data;
+    uint8_t *buffer  = handle->spdifQueue[handle->queueDriver].data;
     uint8_t dataSize = 0;
     uint32_t i = 0, j = 0, data = 0;
 
@@ -520,7 +667,7 @@ void SPDIF_TransferTxHandleIRQ(SPDIF_Type *base, spdif_handle_t *handle)
         handle->spdifQueue[handle->queueDriver].dataSize -= dataSize * 6U;
         handle->spdifQueue[handle->queueDriver].data += dataSize * 6U;
 
-        /* If finished a blcok, call the callback function */
+        /* If finished a block, call the callback function */
         if (handle->spdifQueue[handle->queueDriver].dataSize == 0U)
         {
             memset(&handle->spdifQueue[handle->queueDriver], 0, sizeof(spdif_transfer_t));
@@ -539,11 +686,17 @@ void SPDIF_TransferTxHandleIRQ(SPDIF_Type *base, spdif_handle_t *handle)
     }
 }
 
+/*!
+ * brief Tx interrupt handler.
+ *
+ * param base SPDIF base pointer.
+ * param handle Pointer to the spdif_handle_t structure.
+ */
 void SPDIF_TransferRxHandleIRQ(SPDIF_Type *base, spdif_handle_t *handle)
 {
     assert(handle);
 
-    uint8_t *buffer = NULL;
+    uint8_t *buffer  = NULL;
     uint8_t dataSize = 0;
     uint32_t i = 0, j = 0, data = 0;
 
@@ -592,8 +745,8 @@ void SPDIF_TransferRxHandleIRQ(SPDIF_Type *base, spdif_handle_t *handle)
     if ((SPDIF_GetStatusFlag(base) & kSPDIF_QChannelReceiveRegisterFull) &&
         (base->SIE & kSPDIF_QChannelReceiveRegisterFull))
     {
-        buffer = handle->spdifQueue[handle->queueDriver].qdata;
-        data = SPDIF_ReadQChannel(base);
+        buffer    = handle->spdifQueue[handle->queueDriver].qdata;
+        data      = SPDIF_ReadQChannel(base);
         buffer[0] = data & 0xFFU;
         buffer[1] = (data >> 8U) & 0xFFU;
         buffer[2] = (data >> 16U) & 0xFFU;
@@ -603,8 +756,8 @@ void SPDIF_TransferRxHandleIRQ(SPDIF_Type *base, spdif_handle_t *handle)
     if ((SPDIF_GetStatusFlag(base) & kSPDIF_UChannelReceiveRegisterFull) &&
         (base->SIE & kSPDIF_UChannelReceiveRegisterFull))
     {
-        buffer = handle->spdifQueue[handle->queueDriver].udata;
-        data = SPDIF_ReadUChannel(base);
+        buffer    = handle->spdifQueue[handle->queueDriver].udata;
+        data      = SPDIF_ReadUChannel(base);
         buffer[0] = data & 0xFFU;
         buffer[1] = (data >> 8U) & 0xFFU;
         buffer[2] = (data >> 16U) & 0xFFU;
@@ -614,7 +767,7 @@ void SPDIF_TransferRxHandleIRQ(SPDIF_Type *base, spdif_handle_t *handle)
     if ((SPDIF_GetStatusFlag(base) & kSPDIF_RxFIFOFull) && (base->SIE & kSPDIF_RxFIFOFull))
     {
         dataSize = handle->watermark;
-        buffer = handle->spdifQueue[handle->queueDriver].data;
+        buffer   = handle->spdifQueue[handle->queueDriver].data;
         while (i < dataSize)
         {
             /* Read left channel data */
@@ -638,7 +791,7 @@ void SPDIF_TransferRxHandleIRQ(SPDIF_Type *base, spdif_handle_t *handle)
         handle->spdifQueue[handle->queueDriver].dataSize -= dataSize * 6U;
         handle->spdifQueue[handle->queueDriver].data += dataSize * 6U;
 
-        /* If finished a blcok, call the callback function */
+        /* If finished a block, call the callback function */
         if (handle->spdifQueue[handle->queueDriver].dataSize == 0U)
         {
             memset(&handle->spdifQueue[handle->queueDriver], 0, sizeof(spdif_transfer_t));
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_spdif.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_spdif.h
index ce852af5445..2b4a23ad184 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_spdif.h
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_spdif.h
@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2016, Freescale Semiconductor, Inc.
  * All rights reserved.
  *
  *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #ifndef _FSL_SPDIF_H_
@@ -48,29 +22,29 @@
 
 /*! @name Driver version */
 /*@{*/
-#define FSL_SPDIF_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */
+#define FSL_SPDIF_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) /*!< Version 2.0.2 */
 /*@}*/
 
 /*! @brief SPDIF return status*/
 enum _spdif_status_t
 {
-    kStatus_SPDIF_RxDPLLLocked = MAKE_STATUS(kStatusGroup_SPDIF, 0),     /*!< SPDIF Rx PLL locked. */
-    kStatus_SPDIF_TxFIFOError = MAKE_STATUS(kStatusGroup_SPDIF, 1),      /*!< SPDIF Tx FIFO error. */
-    kStatus_SPDIF_TxFIFOResync = MAKE_STATUS(kStatusGroup_SPDIF, 2),     /*!< SPDIF Tx left and right FIFO resync. */
-    kStatus_SPDIF_RxCnew = MAKE_STATUS(kStatusGroup_SPDIF, 3),           /*!< SPDIF Rx status channel value updated. */
-    kStatus_SPDIF_ValidatyNoGood = MAKE_STATUS(kStatusGroup_SPDIF, 4),   /*!< SPDIF validaty flag not good. */
-    kStatus_SPDIF_RxIllegalSymbol = MAKE_STATUS(kStatusGroup_SPDIF, 5),  /*!< SPDIF Rx receive illegal symbol. */
+    kStatus_SPDIF_RxDPLLLocked     = MAKE_STATUS(kStatusGroup_SPDIF, 0), /*!< SPDIF Rx PLL locked. */
+    kStatus_SPDIF_TxFIFOError      = MAKE_STATUS(kStatusGroup_SPDIF, 1), /*!< SPDIF Tx FIFO error. */
+    kStatus_SPDIF_TxFIFOResync     = MAKE_STATUS(kStatusGroup_SPDIF, 2), /*!< SPDIF Tx left and right FIFO resync. */
+    kStatus_SPDIF_RxCnew           = MAKE_STATUS(kStatusGroup_SPDIF, 3), /*!< SPDIF Rx status channel value updated. */
+    kStatus_SPDIF_ValidatyNoGood   = MAKE_STATUS(kStatusGroup_SPDIF, 4), /*!< SPDIF validaty flag not good. */
+    kStatus_SPDIF_RxIllegalSymbol  = MAKE_STATUS(kStatusGroup_SPDIF, 5), /*!< SPDIF Rx receive illegal symbol. */
     kStatus_SPDIF_RxParityBitError = MAKE_STATUS(kStatusGroup_SPDIF, 6), /*!< SPDIF Rx parity bit error. */
-    kStatus_SPDIF_UChannelOverrun = MAKE_STATUS(kStatusGroup_SPDIF, 7),  /*!< SPDIF receive U channel overrun. */
-    kStatus_SPDIF_QChannelOverrun = MAKE_STATUS(kStatusGroup_SPDIF, 8),  /*!< SPDIF receive Q channel overrun. */
-    kStatus_SPDIF_UQChannelSync = MAKE_STATUS(kStatusGroup_SPDIF, 9),    /*!< SPDIF U/Q channel sync found. */
+    kStatus_SPDIF_UChannelOverrun  = MAKE_STATUS(kStatusGroup_SPDIF, 7), /*!< SPDIF receive U channel overrun. */
+    kStatus_SPDIF_QChannelOverrun  = MAKE_STATUS(kStatusGroup_SPDIF, 8), /*!< SPDIF receive Q channel overrun. */
+    kStatus_SPDIF_UQChannelSync    = MAKE_STATUS(kStatusGroup_SPDIF, 9), /*!< SPDIF U/Q channel sync found. */
     kStatus_SPDIF_UQChannelFrameError = MAKE_STATUS(kStatusGroup_SPDIF, 10), /*!< SPDIF U/Q channel frame error. */
-    kStatus_SPDIF_RxFIFOError = MAKE_STATUS(kStatusGroup_SPDIF, 11),         /*!< SPDIF Rx FIFO error. */
+    kStatus_SPDIF_RxFIFOError         = MAKE_STATUS(kStatusGroup_SPDIF, 11), /*!< SPDIF Rx FIFO error. */
     kStatus_SPDIF_RxFIFOResync = MAKE_STATUS(kStatusGroup_SPDIF, 12), /*!< SPDIF Rx left and right FIFO resync. */
-    kStatus_SPDIF_LockLoss = MAKE_STATUS(kStatusGroup_SPDIF, 13),     /*!< SPDIF Rx PLL clock lock loss. */
-    kStatus_SPDIF_TxIdle = MAKE_STATUS(kStatusGroup_SPDIF, 14),       /*!< SPDIF Tx is idle */
-    kStatus_SPDIF_RxIdle = MAKE_STATUS(kStatusGroup_SPDIF, 15),       /*!< SPDIF Rx is idle */
-    kStatus_SPDIF_QueueFull = MAKE_STATUS(kStatusGroup_SPDIF, 16)     /*!< SPDIF queue full */
+    kStatus_SPDIF_LockLoss     = MAKE_STATUS(kStatusGroup_SPDIF, 13), /*!< SPDIF Rx PLL clock lock loss. */
+    kStatus_SPDIF_TxIdle       = MAKE_STATUS(kStatusGroup_SPDIF, 14), /*!< SPDIF Tx is idle */
+    kStatus_SPDIF_RxIdle       = MAKE_STATUS(kStatusGroup_SPDIF, 15), /*!< SPDIF Rx is idle */
+    kStatus_SPDIF_QueueFull    = MAKE_STATUS(kStatusGroup_SPDIF, 16)  /*!< SPDIF queue full */
 };
 
 /*! @brief SPDIF Rx FIFO full falg select, it decides when assert the rx full flag */
@@ -94,7 +68,7 @@ typedef enum _spdif_txempty_select
 /*! @brief SPDIF U channel source */
 typedef enum _spdif_uchannel_source
 {
-    kSPDIF_NoUChannel = 0x0U,     /*!< No embedded U channel */
+    kSPDIF_NoUChannel     = 0x0U, /*!< No embedded U channel */
     kSPDIF_UChannelFromRx = 0x1U, /*!< U channel from receiver, it is CD mode */
     kSPDIF_UChannelFromTx = 0x3U, /*!< U channel from on chip tx */
 } spdif_uchannel_source_t;
@@ -115,7 +89,7 @@ typedef enum _spdif_gain_select
 typedef enum _spdif_tx_source
 {
     kSPDIF_txFromReceiver = 0x1U, /*!< Tx data directly through SPDIF receiver */
-    kSPDIF_txNormal = 0x5U,       /*!< Normal operation, data from processor */
+    kSPDIF_txNormal       = 0x5U, /*!< Normal operation, data from processor */
 } spdif_tx_source_t;
 
 /*! @brief SPDIF tx data source */
@@ -128,24 +102,24 @@ typedef enum _spdif_validity_config
 /*! @brief The SPDIF interrupt enable flag */
 enum _spdif_interrupt_enable_t
 {
-    kSPDIF_RxDPLLLocked = SPDIF_SIE_LOCK_MASK,                    /*!< SPDIF DPLL locked */
-    kSPDIF_TxFIFOError = SPDIF_SIE_TXUNOV_MASK,                   /*!< Tx FIFO underrun or overrun */
-    kSPDIF_TxFIFOResync = SPDIF_SIE_TXRESYN_MASK,                 /*!< Tx FIFO left and right channel resync */
-    kSPDIF_RxControlChannelChange = SPDIF_SIE_CNEW_MASK,          /*!< SPDIF Rx control channel value changed */
-    kSPDIF_ValidityFlagNoGood = SPDIF_SIE_VALNOGOOD_MASK,         /*!< SPDIF validity flag no good */
-    kSPDIF_RxIllegalSymbol = SPDIF_SIE_SYMERR_MASK,               /*!< SPDIF receiver found illegal symbol */
-    kSPDIF_RxParityBitError = SPDIF_SIE_BITERR_MASK,              /*!< SPDIF receiver found parity bit error */
-    kSPDIF_UChannelReceiveRegisterFull = SPDIF_SIE_URXFUL_MASK,   /*!< SPDIF U channel revceive register full */
-    kSPDIF_UChannelReceiveRegisterOverrun = SPDIF_SIE_URXOV_MASK, /*!< SPDIF U channel receive register overrun */
-    kSPDIF_QChannelReceiveRegisterFull = SPDIF_SIE_QRXFUL_MASK,   /*!< SPDIF Q channel receive reigster full */
-    kSPDIF_QChannelReceiveRegisterOverrun = SPDIF_SIE_QRXOV_MASK, /*!< SPDIF Q channel receive register overrun */
-    kSPDIF_UQChannelSync = SPDIF_SIE_UQSYNC_MASK,                 /*!< SPDIF U/Q channel sync found */
-    kSPDIF_UQChannelFrameError = SPDIF_SIE_UQERR_MASK,            /*!< SPDIF U/Q channel frame error */
-    kSPDIF_RxFIFOError = SPDIF_SIE_RXFIFOUNOV_MASK,               /*!< SPDIF Rx FIFO underrun/overrun */
-    kSPDIF_RxFIFOResync = SPDIF_SIE_RXFIFORESYN_MASK,             /*!< SPDIF Rx left and right FIFO resync */
-    kSPDIF_LockLoss = SPDIF_SIE_LOCKLOSS_MASK,                    /*!< SPDIF receiver loss of lock */
-    kSPDIF_TxFIFOEmpty = SPDIF_SIE_TXEM_MASK,                     /*!< SPDIF Tx FIFO empty */
-    kSPDIF_RxFIFOFull = SPDIF_SIE_RXFIFOFUL_MASK                  /*!< SPDIF Rx FIFO full */
+    kSPDIF_RxDPLLLocked                   = SPDIF_SIE_LOCK_MASK,        /*!< SPDIF DPLL locked */
+    kSPDIF_TxFIFOError                    = SPDIF_SIE_TXUNOV_MASK,      /*!< Tx FIFO underrun or overrun */
+    kSPDIF_TxFIFOResync                   = SPDIF_SIE_TXRESYN_MASK,     /*!< Tx FIFO left and right channel resync */
+    kSPDIF_RxControlChannelChange         = SPDIF_SIE_CNEW_MASK,        /*!< SPDIF Rx control channel value changed */
+    kSPDIF_ValidityFlagNoGood             = SPDIF_SIE_VALNOGOOD_MASK,   /*!< SPDIF validity flag no good */
+    kSPDIF_RxIllegalSymbol                = SPDIF_SIE_SYMERR_MASK,      /*!< SPDIF receiver found illegal symbol */
+    kSPDIF_RxParityBitError               = SPDIF_SIE_BITERR_MASK,      /*!< SPDIF receiver found parity bit error */
+    kSPDIF_UChannelReceiveRegisterFull    = SPDIF_SIE_URXFUL_MASK,      /*!< SPDIF U channel revceive register full */
+    kSPDIF_UChannelReceiveRegisterOverrun = SPDIF_SIE_URXOV_MASK,       /*!< SPDIF U channel receive register overrun */
+    kSPDIF_QChannelReceiveRegisterFull    = SPDIF_SIE_QRXFUL_MASK,      /*!< SPDIF Q channel receive reigster full */
+    kSPDIF_QChannelReceiveRegisterOverrun = SPDIF_SIE_QRXOV_MASK,       /*!< SPDIF Q channel receive register overrun */
+    kSPDIF_UQChannelSync                  = SPDIF_SIE_UQSYNC_MASK,      /*!< SPDIF U/Q channel sync found */
+    kSPDIF_UQChannelFrameError            = SPDIF_SIE_UQERR_MASK,       /*!< SPDIF U/Q channel frame error */
+    kSPDIF_RxFIFOError                    = SPDIF_SIE_RXFIFOUNOV_MASK,  /*!< SPDIF Rx FIFO underrun/overrun */
+    kSPDIF_RxFIFOResync                   = SPDIF_SIE_RXFIFORESYN_MASK, /*!< SPDIF Rx left and right FIFO resync */
+    kSPDIF_LockLoss                       = SPDIF_SIE_LOCKLOSS_MASK,    /*!< SPDIF receiver loss of lock */
+    kSPDIF_TxFIFOEmpty                    = SPDIF_SIE_TXEM_MASK,        /*!< SPDIF Tx FIFO empty */
+    kSPDIF_RxFIFOFull                     = SPDIF_SIE_RXFIFOFUL_MASK    /*!< SPDIF Rx FIFO full */
 };
 
 /*! @brief The DMA request sources */
@@ -226,7 +200,7 @@ extern "C" {
  *
  * @param base SPDIF base pointer
  * @param config SPDIF configuration structure.
-*/
+ */
 void SPDIF_Init(SPDIF_Type *base, const spdif_config_t *config);
 
 /*!
@@ -251,7 +225,7 @@ void SPDIF_GetDefaultConfig(spdif_config_t *config);
  * This API gates the SPDIF clock. The SPDIF module can't operate unless SPDIF_Init is called to enable the clock.
  *
  * @param base SPDIF base pointer
-*/
+ */
 void SPDIF_Deinit(SPDIF_Type *base);
 
 /*!
@@ -474,7 +448,7 @@ static inline uint32_t SPDIF_RxGetRightDataRegisterAddress(SPDIF_Type *base)
  * @param base SPDIF base pointer.
  * @param sampleRate_Hz SPDIF sample rate frequency in Hz.
  * @param sourceClockFreq_Hz SPDIF tx clock source frequency in Hz.
-*/
+ */
 void SPDIF_TxSetSampleRate(SPDIF_Type *base, uint32_t sampleRate_Hz, uint32_t sourceClockFreq_Hz);
 
 /*!
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_spdif_edma.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_spdif_edma.c
index 79cc2ff05d8..8504a25ec9b 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_spdif_edma.c
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_spdif_edma.c
@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2016, Freescale Semiconductor, Inc.
  * All rights reserved.
  *
- * 
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
  *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include "fsl_spdif_edma.h"
@@ -39,7 +13,6 @@
 #define FSL_COMPONENT_ID "platform.drivers.spdif_edma"
 #endif
 
-
 /*******************************************************************************
  * Definitations
  ******************************************************************************/
@@ -60,7 +33,7 @@ enum _spdif_edma_transfer_state
 };
 
 /*<! Private handle only used for internally. */
-static spdif_edma_private_handle_t s_edmaPrivateHandle[FSL_FEATURE_SOC_I2S_COUNT][2];
+static spdif_edma_private_handle_t s_edmaPrivateHandle[FSL_FEATURE_SOC_SPDIF_COUNT][2];
 static uint8_t s_spdif_tx_watermark[4] = {16, 12, 8, 4};
 static uint8_t s_spdif_rx_watermark[4] = {1, 4, 8, 16};
 
@@ -104,14 +77,14 @@ static void SPDIF_TxEDMACallback(edma_handle_t *handle, void *userData, bool don
 static void SPDIF_RxEDMACallback(edma_handle_t *handle, void *userData, bool done, uint32_t tcds);
 
 /*******************************************************************************
-* Code
-******************************************************************************/
+ * Code
+ ******************************************************************************/
 static void SPDIF_TxEDMACallback(edma_handle_t *handle, void *userData, bool done, uint32_t tcds)
 {
     spdif_edma_private_handle_t *privHandle = (spdif_edma_private_handle_t *)userData;
-    spdif_edma_handle_t *spdifHandle = privHandle->handle;
+    spdif_edma_handle_t *spdifHandle        = privHandle->handle;
 
-    /* If finished a blcok, call the callback function */
+    /* If finished a block, call the callback function */
     memset(&spdifHandle->spdifQueue[spdifHandle->queueDriver], 0, sizeof(spdif_edma_transfer_t));
     spdifHandle->queueDriver = (spdifHandle->queueDriver + 1) % SPDIF_XFER_QUEUE_SIZE;
     if (spdifHandle->callback)
@@ -129,9 +102,9 @@ static void SPDIF_TxEDMACallback(edma_handle_t *handle, void *userData, bool don
 static void SPDIF_RxEDMACallback(edma_handle_t *handle, void *userData, bool done, uint32_t tcds)
 {
     spdif_edma_private_handle_t *privHandle = (spdif_edma_private_handle_t *)userData;
-    spdif_edma_handle_t *spdifHandle = privHandle->handle;
+    spdif_edma_handle_t *spdifHandle        = privHandle->handle;
 
-    /* If finished a blcok, call the callback function */
+    /* If finished a block, call the callback function */
     memset(&spdifHandle->spdifQueue[spdifHandle->queueDriver], 0, sizeof(spdif_edma_transfer_t));
     spdifHandle->queueDriver = (spdifHandle->queueDriver + 1) % SPDIF_XFER_QUEUE_SIZE;
     if (spdifHandle->callback)
@@ -190,10 +163,10 @@ static status_t SPDIF_SubmitTransfer(edma_handle_t *handle, const edma_transfer_
     if (currentTcd != previousTcd)
     {
         /* Enable scatter/gather feature in the previous TCD block. */
-        csr = (handle->tcdPool[previousTcd].CSR | DMA_CSR_ESG_MASK) & ~DMA_CSR_DREQ_MASK;
+        csr                              = (handle->tcdPool[previousTcd].CSR | DMA_CSR_ESG_MASK) & ~DMA_CSR_DREQ_MASK;
         handle->tcdPool[previousTcd].CSR = csr;
         /*
-            Check if the TCD blcok in the registers is the previous one (points to current TCD block). It
+            Check if the TCD block in the registers is the previous one (points to current TCD block). It
             is used to check if the previous TCD linked has been loaded in TCD register. If so, it need to
             link the TCD register in case link the current TCD with the dead chain when TCD loading occurs
             before link the previous TCD block.
@@ -256,6 +229,20 @@ static status_t SPDIF_SubmitTransfer(edma_handle_t *handle, const edma_transfer_
     return kStatus_Success;
 }
 
+/*!
+ * brief Initializes the SPDIF eDMA handle.
+ *
+ * This function initializes the SPDIF master DMA handle, which can be used for other SPDIF master transactional APIs.
+ * Usually, for a specified SPDIF instance, call this API once to get the initialized handle.
+ *
+ * param base SPDIF base pointer.
+ * param handle SPDIF eDMA handle pointer.
+ * param base SPDIF peripheral base address.
+ * param callback Pointer to user callback function.
+ * param userData User parameter passed to the callback function.
+ * param dmaLeftHandle eDMA handle pointer for left channel, this handle shall be static allocated by users.
+ * param dmaRightHandle eDMA handle pointer for right channel, this handle shall be static allocated by users.
+ */
 void SPDIF_TransferTxCreateHandleEDMA(SPDIF_Type *base,
                                       spdif_edma_handle_t *handle,
                                       spdif_edma_callback_t callback,
@@ -271,17 +258,17 @@ void SPDIF_TransferTxCreateHandleEDMA(SPDIF_Type *base,
     memset(handle, 0, sizeof(*handle));
 
     /* Set spdif base to handle */
-    handle->dmaLeftHandle = dmaLeftHandle;
+    handle->dmaLeftHandle  = dmaLeftHandle;
     handle->dmaRightHandle = dmaRightHandle;
-    handle->callback = callback;
-    handle->userData = userData;
+    handle->callback       = callback;
+    handle->userData       = userData;
     handle->count =
         s_spdif_tx_watermark[(base->SCR & SPDIF_SCR_TXFIFOEMPTY_SEL_MASK) >> SPDIF_SCR_TXFIFOEMPTY_SEL_SHIFT];
 
     /* Set SPDIF state to idle */
     handle->state = kSPDIF_Idle;
 
-    s_edmaPrivateHandle[instance][0].base = base;
+    s_edmaPrivateHandle[instance][0].base   = base;
     s_edmaPrivateHandle[instance][0].handle = handle;
 
     /* Need to use scatter gather */
@@ -292,6 +279,20 @@ void SPDIF_TransferTxCreateHandleEDMA(SPDIF_Type *base,
     EDMA_SetCallback(dmaRightHandle, SPDIF_TxEDMACallback, &s_edmaPrivateHandle[instance][0]);
 }
 
+/*!
+ * brief Initializes the SPDIF Rx eDMA handle.
+ *
+ * This function initializes the SPDIF slave DMA handle, which can be used for other SPDIF master transactional APIs.
+ * Usually, for a specified SPDIF instance, call this API once to get the initialized handle.
+ *
+ * param base SPDIF base pointer.
+ * param handle SPDIF eDMA handle pointer.
+ * param base SPDIF peripheral base address.
+ * param callback Pointer to user callback function.
+ * param userData User parameter passed to the callback function.
+ * param dmaLeftHandle eDMA handle pointer for left channel, this handle shall be static allocated by users.
+ * param dmaRightHandle eDMA handle pointer for right channel, this handle shall be static allocated by users.
+ */
 void SPDIF_TransferRxCreateHandleEDMA(SPDIF_Type *base,
                                       spdif_edma_handle_t *handle,
                                       spdif_edma_callback_t callback,
@@ -307,16 +308,16 @@ void SPDIF_TransferRxCreateHandleEDMA(SPDIF_Type *base,
     memset(handle, 0, sizeof(*handle));
 
     /* Set spdif base to handle */
-    handle->dmaLeftHandle = dmaLeftHandle;
+    handle->dmaLeftHandle  = dmaLeftHandle;
     handle->dmaRightHandle = dmaRightHandle;
-    handle->callback = callback;
-    handle->userData = userData;
+    handle->callback       = callback;
+    handle->userData       = userData;
     handle->count = s_spdif_rx_watermark[(base->SCR & SPDIF_SCR_RXFIFOFULL_SEL_MASK) >> SPDIF_SCR_RXFIFOFULL_SEL_SHIFT];
 
     /* Set SPDIF state to idle */
     handle->state = kSPDIF_Idle;
 
-    s_edmaPrivateHandle[instance][1].base = base;
+    s_edmaPrivateHandle[instance][1].base   = base;
     s_edmaPrivateHandle[instance][1].handle = handle;
 
     /* Need to use scatter gather */
@@ -327,12 +328,25 @@ void SPDIF_TransferRxCreateHandleEDMA(SPDIF_Type *base,
     EDMA_SetCallback(dmaRightHandle, SPDIF_RxEDMACallback, &s_edmaPrivateHandle[instance][1]);
 }
 
+/*!
+ * brief Performs a non-blocking SPDIF transfer using DMA.
+ *
+ * note This interface returns immediately after the transfer initiates. Call
+ * SPDIF_GetTransferStatus to poll the transfer status and check whether the SPDIF transfer is finished.
+ *
+ * param base SPDIF base pointer.
+ * param handle SPDIF eDMA handle pointer.
+ * param xfer Pointer to the DMA transfer structure.
+ * retval kStatus_Success Start a SPDIF eDMA send successfully.
+ * retval kStatus_InvalidArgument The input argument is invalid.
+ * retval kStatus_TxBusy SPDIF is busy sending data.
+ */
 status_t SPDIF_TransferSendEDMA(SPDIF_Type *base, spdif_edma_handle_t *handle, spdif_edma_transfer_t *xfer)
 {
     assert(handle && xfer);
 
     edma_transfer_config_t config = {0};
-    uint32_t destAddr = SPDIF_TxGetLeftDataRegisterAddress(base);
+    uint32_t destAddr             = SPDIF_TxGetLeftDataRegisterAddress(base);
 
     /* Check if input parameter invalid */
     if ((xfer->leftData == NULL) || (xfer->dataSize == 0U) || (xfer->rightData == NULL))
@@ -349,11 +363,11 @@ status_t SPDIF_TransferSendEDMA(SPDIF_Type *base, spdif_edma_handle_t *handle, s
     handle->state = kSPDIF_Busy;
 
     /* Update the queue state */
-    handle->transferSize[handle->queueUser] = xfer->dataSize;
-    handle->spdifQueue[handle->queueUser].leftData = xfer->leftData;
-    handle->spdifQueue[handle->queueUser].dataSize = xfer->dataSize;
+    handle->transferSize[handle->queueUser]         = xfer->dataSize;
+    handle->spdifQueue[handle->queueUser].leftData  = xfer->leftData;
+    handle->spdifQueue[handle->queueUser].dataSize  = xfer->dataSize;
     handle->spdifQueue[handle->queueUser].rightData = xfer->rightData;
-    handle->queueUser = (handle->queueUser + 1) % SPDIF_XFER_QUEUE_SIZE;
+    handle->queueUser                               = (handle->queueUser + 1) % SPDIF_XFER_QUEUE_SIZE;
 
     /* Store the initially configured eDMA minor byte transfer count into the SPDIF handle */
     handle->nbytes = handle->count * 8U;
@@ -382,12 +396,25 @@ status_t SPDIF_TransferSendEDMA(SPDIF_Type *base, spdif_edma_handle_t *handle, s
     return kStatus_Success;
 }
 
+/*!
+ * brief Performs a non-blocking SPDIF receive using eDMA.
+ *
+ * note This interface returns immediately after the transfer initiates. Call
+ * the SPDIF_GetReceiveRemainingBytes to poll the transfer status and check whether the SPDIF transfer is finished.
+ *
+ * param base SPDIF base pointer
+ * param handle SPDIF eDMA handle pointer.
+ * param xfer Pointer to DMA transfer structure.
+ * retval kStatus_Success Start a SPDIF eDMA receive successfully.
+ * retval kStatus_InvalidArgument The input argument is invalid.
+ * retval kStatus_RxBusy SPDIF is busy receiving data.
+ */
 status_t SPDIF_TransferReceiveEDMA(SPDIF_Type *base, spdif_edma_handle_t *handle, spdif_edma_transfer_t *xfer)
 {
     assert(handle && xfer);
 
     edma_transfer_config_t config = {0};
-    uint32_t srcAddr = SPDIF_RxGetLeftDataRegisterAddress(base);
+    uint32_t srcAddr              = SPDIF_RxGetLeftDataRegisterAddress(base);
 
     /* Check if input parameter invalid */
     if ((xfer->leftData == NULL) || (xfer->dataSize == 0U) || (xfer->rightData == NULL))
@@ -404,11 +431,11 @@ status_t SPDIF_TransferReceiveEDMA(SPDIF_Type *base, spdif_edma_handle_t *handle
     handle->state = kSPDIF_Busy;
 
     /* Update the queue state */
-    handle->transferSize[handle->queueUser] = xfer->dataSize;
-    handle->spdifQueue[handle->queueUser].leftData = xfer->leftData;
-    handle->spdifQueue[handle->queueUser].dataSize = xfer->dataSize;
+    handle->transferSize[handle->queueUser]         = xfer->dataSize;
+    handle->spdifQueue[handle->queueUser].leftData  = xfer->leftData;
+    handle->spdifQueue[handle->queueUser].dataSize  = xfer->dataSize;
     handle->spdifQueue[handle->queueUser].rightData = xfer->rightData;
-    handle->queueUser = (handle->queueUser + 1) % SPDIF_XFER_QUEUE_SIZE;
+    handle->queueUser                               = (handle->queueUser + 1) % SPDIF_XFER_QUEUE_SIZE;
 
     /* Store the initially configured eDMA minor byte transfer count into the SPDIF handle */
     handle->nbytes = handle->count * 8U;
@@ -438,6 +465,12 @@ status_t SPDIF_TransferReceiveEDMA(SPDIF_Type *base, spdif_edma_handle_t *handle
     return kStatus_Success;
 }
 
+/*!
+ * brief Aborts a SPDIF transfer using eDMA.
+ *
+ * param base SPDIF base pointer.
+ * param handle SPDIF eDMA handle pointer.
+ */
 void SPDIF_TransferAbortSendEDMA(SPDIF_Type *base, spdif_edma_handle_t *handle)
 {
     assert(handle);
@@ -452,13 +485,19 @@ void SPDIF_TransferAbortSendEDMA(SPDIF_Type *base, spdif_edma_handle_t *handle)
     /* Set internal state */
     memset(handle->spdifQueue, 0U, sizeof(handle->spdifQueue));
     memset(handle->transferSize, 0U, sizeof(handle->transferSize));
-    handle->queueUser = 0U;
+    handle->queueUser   = 0U;
     handle->queueDriver = 0U;
 
     /* Set the handle state */
     handle->state = kSPDIF_Idle;
 }
 
+/*!
+ * brief Aborts a SPDIF receive using eDMA.
+ *
+ * param base SPDIF base pointer
+ * param handle SPDIF eDMA handle pointer.
+ */
 void SPDIF_TransferAbortReceiveEDMA(SPDIF_Type *base, spdif_edma_handle_t *handle)
 {
     assert(handle);
@@ -473,13 +512,22 @@ void SPDIF_TransferAbortReceiveEDMA(SPDIF_Type *base, spdif_edma_handle_t *handl
     /* Set internal state */
     memset(handle->spdifQueue, 0U, sizeof(handle->spdifQueue));
     memset(handle->transferSize, 0U, sizeof(handle->transferSize));
-    handle->queueUser = 0U;
+    handle->queueUser   = 0U;
     handle->queueDriver = 0U;
 
     /* Set the handle state */
     handle->state = kSPDIF_Idle;
 }
 
+/*!
+ * brief Gets byte count sent by SPDIF.
+ *
+ * param base SPDIF base pointer.
+ * param handle SPDIF eDMA handle pointer.
+ * param count Bytes count sent by SPDIF.
+ * retval kStatus_Success Succeed get the transfer count.
+ * retval kStatus_NoTransferInProgress There is no non-blocking transaction in progress.
+ */
 status_t SPDIF_TransferGetSendCountEDMA(SPDIF_Type *base, spdif_edma_handle_t *handle, size_t *count)
 {
     assert(handle);
@@ -500,6 +548,15 @@ status_t SPDIF_TransferGetSendCountEDMA(SPDIF_Type *base, spdif_edma_handle_t *h
     return status;
 }
 
+/*!
+ * brief Gets byte count received by SPDIF.
+ *
+ * param base SPDIF base pointer
+ * param handle SPDIF eDMA handle pointer.
+ * param count Bytes count received by SPDIF.
+ * retval kStatus_Success Succeed get the transfer count.
+ * retval kStatus_NoTransferInProgress There is no non-blocking transaction in progress.
+ */
 status_t SPDIF_TransferGetReceiveCountEDMA(SPDIF_Type *base, spdif_edma_handle_t *handle, size_t *count)
 {
     assert(handle);
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_spdif_edma.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_spdif_edma.h
index 2815616f261..b39c2026711 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_spdif_edma.h
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_spdif_edma.h
@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2016, Freescale Semiconductor, Inc.
  * All rights reserved.
  *
- * 
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
  *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 #ifndef _FSL_SPDIF_EDMA_H_
 #define _FSL_SPDIF_EDMA_H_
@@ -48,7 +22,7 @@
 
 /*! @name Driver version */
 /*@{*/
-#define FSL_SPDIF_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */
+#define FSL_SPDIF_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) /*!< Version 2.0.1 */
 /*@}*/
 
 typedef struct _spdif_edma_handle spdif_edma_handle_t;
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_src.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_src.c
index 7672586d320..10af22893aa 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_src.c
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_src.c
@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2016, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
  * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
  *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include "fsl_src.h"
@@ -39,7 +13,6 @@
 #define FSL_COMPONENT_ID "platform.drivers.src"
 #endif
 
-
 /*******************************************************************************
  * Prototypes
  ******************************************************************************/
@@ -52,6 +25,12 @@
  * Code
  ******************************************************************************/
 
+/*!
+ * brief Clear the status flags of SRC.
+ *
+ * param base SRC peripheral base address.
+ * param Mask value of status flags to be cleared, see to #_src_reset_status_flags.
+ */
 void SRC_ClearResetStatusFlags(SRC_Type *base, uint32_t flags)
 {
     uint32_t tmp32 = base->SRSR;
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_src.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_src.h
index bf255820512..5a8830f69d9 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_src.h
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_src.h
@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2016, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
  * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #ifndef _FSL_SRC_H_
@@ -48,8 +22,8 @@
 
 /*! @name Driver version */
 /*@{*/
-/*! @brief SRC driver version 2.0.0. */
-#define FSL_SRC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*! @brief SRC driver version 2.0.1. */
+#define FSL_SRC_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
 /*@}*/
 
 /*!
@@ -62,25 +36,29 @@ enum _src_reset_status_flags
                                                                driven out on PTE0 pin. */
 #endif                                                    /* FSL_FEATURE_SRC_HAS_SRSR_RESET_OUT */
 #if !(defined(FSL_FEATURE_SRC_HAS_NO_SRSR_WBI) && FSL_FEATURE_SRC_HAS_NO_SRSR_WBI)
-    kSRC_WarmBootIndicationFlag = SRC_SRSR_WBI_MASK,      /*!< WARM boot indication shows that WARM boot
-                                                               was initiated by software. */
-#endif                                                    /* FSL_FEATURE_SRC_HAS_NO_SRSR_WBI */
-    kSRC_TemperatureSensorResetFlag = SRC_SRSR_TSR_MASK,  /*!< Indicates whether the reset was the
-                                                               result of software reset from on-chip
-                                                               Temperature Sensor. Temperature Sensor
-                                                               Interrupt need be served before this
-                                                               bit can be cleaned.*/
+    kSRC_WarmBootIndicationFlag = SRC_SRSR_WBI_MASK,     /*!< WARM boot indication shows that WARM boot
+                                                              was initiated by software. */
+#endif                                                   /* FSL_FEATURE_SRC_HAS_NO_SRSR_WBI */
+    kSRC_TemperatureSensorResetFlag = SRC_SRSR_TSR_MASK, /*!< Indicates whether the reset was the
+                                                              result of software reset from on-chip
+                                                              Temperature Sensor. Temperature Sensor
+                                                              Interrupt needs to be served before this
+                                                              bit can be cleaned.*/
 #if (defined(FSL_FEATURE_SRC_HAS_SRSR_WDOG3_RST_B) && FSL_FEATURE_SRC_HAS_SRSR_WDOG3_RST_B)
     kSRC_Wdog3ResetFlag = SRC_SRSR_WDOG3_RST_B_MASK, /*!< IC Watchdog3 Time-out reset. Indicates
                                                           whether the reset was the result of the
                                                           watchdog3 time-out event. */
 #endif                                               /* FSL_FEATURE_SRC_HAS_SRSR_WDOG3_RST_B */
 #if (defined(FSL_FEATURE_SRC_HAS_SRSR_SW) && FSL_FEATURE_SRC_HAS_SRSR_SW)
-    kSRC_SoftwareResetFlag = SRC_SRSR_SW_MASK,        /*!< Indicates a reset has been caused by software
-                                                           setting of SYSRESETREQ bit in Application
-                                                           Interrupt and Reset Control Register in the
-                                                           ARM core. */
-#endif                                                /* FSL_FEATURE_SRC_HAS_SRSR_SW */
+    kSRC_SoftwareResetFlag = SRC_SRSR_SW_MASK, /*!< Indicates a reset has been caused by software
+                                                    setting of SYSRESETREQ bit in Application
+                                                    Interrupt and Reset Control Register in the
+                                                    ARM core. */
+#endif                                         /* FSL_FEATURE_SRC_HAS_SRSR_SW */
+#if (defined(FSL_FEATURE_SRC_HAS_SRSR_JTAG_SW_RST) && FSL_FEATURE_SRC_HAS_SRSR_JTAG_SW_RST)
+    kSRC_JTAGSystemResetFlag =
+        SRC_SRSR_JTAG_SW_RST_MASK, /*!< Indicates whether the reset was the result of software reset form JTAG */
+#endif                             /* FSL_FEATURE_SRC_HAS_SRSR_JTAG_SW_RST */
     kSRC_JTAGSoftwareResetFlag = SRC_SRSR_SJC_MASK,   /*!< Indicates whether the reset was the result of
                                                       setting SJC_GPCCR bit 31. */
     kSRC_JTAGGeneratedResetFlag = SRC_SRSR_JTAG_MASK, /*!< Indicates a reset has been caused by JTAG
@@ -112,10 +90,11 @@ enum _src_reset_status_flags
                                                     power-on detection logic. */
 #endif                                         /* FSL_FEATURE_SRC_HAS_SRSR_POR */
 #if (defined(FSL_FEATURE_SRC_HAS_SRSR_LOCKUP_SYSRESETREQ) && FSL_FEATURE_SRC_HAS_SRSR_LOCKUP_SYSRESETREQ)
-    kSRC_LockupSysResetFlag = SRC_SRSR_LOCKUP_SYSRESETREQ_MASK, /*!< Indicates a reset has been caused by CPU lockup or software 
-                                                                     setting of SYSRESETREQ bit in Application Interrupt and 
-                                                                     Reset Control Register of the ARM core. */
-#endif                                         /* FSL_FEATURE_SRC_HAS_SRSR_LOCKUP_SYSRESETREQ */
+    kSRC_LockupSysResetFlag =
+        SRC_SRSR_LOCKUP_SYSRESETREQ_MASK, /*!< Indicates a reset has been caused by CPU lockup or software
+                                               setting of SYSRESETREQ bit in Application Interrupt and
+                                               Reset Control Register of the ARM core. */
+#endif                                    /* FSL_FEATURE_SRC_HAS_SRSR_LOCKUP_SYSRESETREQ */
 #if (defined(FSL_FEATURE_SRC_HAS_SRSR_IPP_RESET_B) && FSL_FEATURE_SRC_HAS_SRSR_IPP_RESET_B)
     kSRC_IppResetPinFlag = SRC_SRSR_IPP_RESET_B_MASK, /*!< Indicates whether reset was the result of
                                                            ipp_reset_b pin (Power-up sequence). */
@@ -170,9 +149,9 @@ typedef enum _src_wdog3_reset_option
 typedef enum _src_warm_reset_bypass_count
 {
     kSRC_WarmResetWaitAlways = 0U, /*!< System will wait until MMDC acknowledge is asserted. */
-    kSRC_WarmResetWaitClk16 = 1U,  /*!< Wait 16 32KHz clock cycles before switching the reset. */
-    kSRC_WarmResetWaitClk32 = 2U,  /*!< Wait 32 32KHz clock cycles before switching the reset. */
-    kSRC_WarmResetWaitClk64 = 3U,  /*!< Wait 64 32KHz clock cycles before switching the reset. */
+    kSRC_WarmResetWaitClk16  = 1U, /*!< Wait 16 32KHz clock cycles before switching the reset. */
+    kSRC_WarmResetWaitClk32  = 2U, /*!< Wait 32 32KHz clock cycles before switching the reset. */
+    kSRC_WarmResetWaitClk64  = 3U, /*!< Wait 64 32KHz clock cycles before switching the reset. */
 } src_warm_reset_bypass_count_t;
 
 #if defined(__cplusplus)
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_tempmon.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_tempmon.c
new file mode 100644
index 00000000000..2d110547df6
--- /dev/null
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_tempmon.c
@@ -0,0 +1,185 @@
+/*
+ * Copyright  2018 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_tempmon.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.tempmon"
+#endif
+
+/*! @brief TEMPMON calibration data mask. */
+#define TEMPMON_HOTTEMPMASK 0xFFU
+#define TEMPMON_HOTTEMPSHIFT 0x00U
+#define TEMPMON_HOTCOUNTMASK 0xFFF00U
+#define TEMPMON_HOTCOUNTSHIFT 0X08U
+#define TEMPMON_ROOMCOUNTMASK 0xFFF00000U
+#define TEMPMON_ROOMCOUNTSHIFT 0x14U
+
+/*! @brief the room temperature. */
+#define TEMPMON_ROOMTEMP 25.0
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+static uint32_t s_hotTemp;    /*!< The value of TEMPMON_TEMPSENSE0[TEMP_VALUE] at room temperature .*/
+static uint32_t s_hotCount;   /*!< The value of TEMPMON_TEMPSENSE0[TEMP_VALUE] at the hot temperature.*/
+static float s_hotT_ROOM;     /*!< The value of s_hotTemp minus room temperature(25¡æ).*/
+static uint32_t s_roomC_hotC; /*!< The value of s_roomCount minus s_hotCount.*/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/*!
+ * brief Initializes the TEMPMON module.
+ *
+ * param base TEMPMON base pointer
+ * param config Pointer to configuration structure.
+ */
+void TEMPMON_Init(TEMPMON_Type *base, const tempmon_config_t *config)
+{
+    assert(NULL != config);
+
+    uint32_t calibrationData;
+    uint32_t roomCount;
+
+    /* Power on the temperature sensor*/
+    base->TEMPSENSE0 &= ~TEMPMON_TEMPSENSE0_POWER_DOWN_MASK;
+
+    /* Set temperature monitor frequency */
+    base->TEMPSENSE1 = TEMPMON_TEMPSENSE1_MEASURE_FREQ(config->frequency);
+
+    /* ready to read calibration data */
+    calibrationData = OCOTP->ANA1;
+    s_hotTemp       = (uint32_t)(calibrationData & TEMPMON_HOTTEMPMASK) >> TEMPMON_HOTTEMPSHIFT;
+    s_hotCount      = (uint32_t)(calibrationData & TEMPMON_HOTCOUNTMASK) >> TEMPMON_HOTCOUNTSHIFT;
+    roomCount       = (uint32_t)(calibrationData & TEMPMON_ROOMCOUNTMASK) >> TEMPMON_ROOMCOUNTSHIFT;
+
+    s_hotT_ROOM  = s_hotTemp - TEMPMON_ROOMTEMP;
+    s_roomC_hotC = roomCount - s_hotCount;
+
+    /* Set alarm temperature */
+    TEMPMON_SetTempAlarm(base, config->highAlarmTemp, kTEMPMON_HighAlarmMode);
+    TEMPMON_SetTempAlarm(base, config->panicAlarmTemp, kTEMPMON_PanicAlarmMode);
+    TEMPMON_SetTempAlarm(base, config->lowAlarmTemp, kTEMPMON_LowAlarmMode);
+}
+
+/*!
+ * brief Deinitializes the TEMPMON module.
+ *
+ * param base TEMPMON base pointer
+ */
+void TEMPMON_Deinit(TEMPMON_Type *base)
+{
+    base->TEMPSENSE0 |= TEMPMON_TEMPSENSE0_POWER_DOWN_MASK;
+}
+
+/*!
+ * brief Gets the default configuration structure.
+ *
+ * This function initializes the TEMPMON configuration structure to a default value. The default
+ * values are:
+ *   tempmonConfig->frequency = 0x02U;
+ *   tempmonConfig->highAlarmTemp = 44U;
+ *   tempmonConfig->panicAlarmTemp = 90U;
+ *   tempmonConfig->lowAlarmTemp = 39U;
+ *
+ * param config Pointer to a configuration structure.
+ */
+void TEMPMON_GetDefaultConfig(tempmon_config_t *config)
+{
+    assert(config);
+
+    /* Initializes the configure structure to zero. */
+    memset(config, 0, sizeof(*config));
+
+    /* Default measure frequency */
+    config->frequency = 0x03U;
+    /* Default high alarm temperature */
+    config->highAlarmTemp = 40U;
+    /* Default panic alarm temperature */
+    config->panicAlarmTemp = 90U;
+    /* Default low alarm temperature */
+    config->lowAlarmTemp = 20U;
+}
+
+/*!
+ * brief Get current temperature with the fused temperature calibration data.
+ *
+ * param base TEMPMON base pointer
+ * return current temperature with degrees Celsius.
+ */
+float TEMPMON_GetCurrentTemperature(TEMPMON_Type *base)
+{
+    /* Check arguments */
+    assert(NULL != base);
+
+    uint32_t nmeas;
+    float tmeas;
+
+    while (!(base->TEMPSENSE0 & TEMPMON_TEMPSENSE0_FINISHED_MASK))
+    {
+    }
+
+    /* ready to read temperature code value */
+    nmeas = (base->TEMPSENSE0 & TEMPMON_TEMPSENSE0_TEMP_CNT_MASK) >> TEMPMON_TEMPSENSE0_TEMP_CNT_SHIFT;
+
+    /* Calculate temperature */
+    tmeas = s_hotTemp - (float)((nmeas - s_hotCount) * s_hotT_ROOM / s_roomC_hotC);
+
+    return tmeas;
+}
+
+/*!
+ * brief Set the temperature count (raw sensor output) that will generate an alarm interrupt.
+ *
+ * param base TEMPMON base pointer
+ * param tempVal The alarm temperature with degrees Celsius
+ * param alarmMode The alarm mode.
+ */
+void TEMPMON_SetTempAlarm(TEMPMON_Type *base, uint32_t tempVal, tempmon_alarm_mode alarmMode)
+{
+    /* Check arguments */
+    assert(NULL != base);
+
+    uint32_t tempCodeVal;
+
+    /* Calculate alarm temperature code value */
+    tempCodeVal = (uint32_t)(s_hotCount + (s_hotTemp - tempVal) * s_roomC_hotC / s_hotT_ROOM);
+
+    switch (alarmMode)
+    {
+        case kTEMPMON_HighAlarmMode:
+            /* Set high alarm temperature code value */
+            base->TEMPSENSE0 |= TEMPMON_TEMPSENSE0_ALARM_VALUE(tempCodeVal);
+            break;
+
+        case kTEMPMON_PanicAlarmMode:
+            /* Set panic alarm temperature code value */
+            base->TEMPSENSE2 |= TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE(tempCodeVal);
+            break;
+
+        case kTEMPMON_LowAlarmMode:
+            /* Set low alarm temperature code value */
+            base->TEMPSENSE2 |= TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE(tempCodeVal);
+            break;
+
+        default:
+            assert(false);
+            break;
+    }
+}
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_tempmon.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_tempmon.h
new file mode 100644
index 00000000000..eaa5be67ddd
--- /dev/null
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_tempmon.h
@@ -0,0 +1,126 @@
+/*
+ * Copyright  2018 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _FSL_TEMPMON_H_
+#define _FSL_TEMPMON_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup tempmon
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+#define FSL_TEMPMON_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */
+/*@}*/
+
+/*! @brief TEMPMON temperature structure. */
+typedef struct _tempmon_config
+{
+    uint16_t frequency;      /*!< The temperature measure frequency.*/
+    uint32_t highAlarmTemp;  /*!< The high alarm temperature.*/
+    uint32_t panicAlarmTemp; /*!< The panic alarm temperature.*/
+    uint32_t lowAlarmTemp;   /*!< The low alarm temperature.*/
+} tempmon_config_t;
+
+/*! @brief TEMPMON alarm mode. */
+typedef enum _tempmon_alarm_mode
+{
+    kTEMPMON_HighAlarmMode  = 0U, /*!< The high alarm temperature interrupt mode.*/
+    kTEMPMON_PanicAlarmMode = 1U, /*!< The panic alarm temperature interrupt mode.*/
+    kTEMPMON_LowAlarmMode   = 2U, /*!< The low alarm temperature interrupt mode.*/
+} tempmon_alarm_mode;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Initializes the TEMPMON module.
+ *
+ * @param base TEMPMON base pointer
+ * @param config Pointer to configuration structure.
+ */
+void TEMPMON_Init(TEMPMON_Type *base, const tempmon_config_t *config);
+
+/*!
+ * @brief Deinitializes the TEMPMON module.
+ *
+ * @param base TEMPMON base pointer
+ */
+void TEMPMON_Deinit(TEMPMON_Type *base);
+
+/*!
+ * @brief Gets the default configuration structure.
+ *
+ * This function initializes the TEMPMON configuration structure to a default value. The default
+ * values are:
+ *   tempmonConfig->frequency = 0x02U;
+ *   tempmonConfig->highAlarmTemp = 44U;
+ *   tempmonConfig->panicAlarmTemp = 90U;
+ *   tempmonConfig->lowAlarmTemp = 39U;
+ *
+ * @param config Pointer to a configuration structure.
+ */
+void TEMPMON_GetDefaultConfig(tempmon_config_t *config);
+
+/*!
+ * @brief start the temperature measurement process.
+ *
+ * @param base TEMPMON base pointer.
+ */
+static inline void TEMPMON_StartMeasure(TEMPMON_Type *base)
+{
+    base->TEMPSENSE0 |= TEMPMON_TEMPSENSE0_MEASURE_TEMP_MASK;
+}
+
+/*!
+ * @brief stop the measurement process.
+ *
+ * @param base TEMPMON base pointer
+ */
+static inline void TEMPMON_StopMeasure(TEMPMON_Type *base)
+{
+    base->TEMPSENSE0 &= ~TEMPMON_TEMPSENSE0_MEASURE_TEMP_MASK;
+}
+
+/*!
+ * @brief Get current temperature with the fused temperature calibration data.
+ *
+ * @param base TEMPMON base pointer
+ * @return current temperature with degrees Celsius.
+ */
+float TEMPMON_GetCurrentTemperature(TEMPMON_Type *base);
+
+/*!
+ * @brief Set the temperature count (raw sensor output) that will generate an alarm interrupt.
+ *
+ * @param base TEMPMON base pointer
+ * @param tempVal The alarm temperature with degrees Celsius
+ * @param alarmMode The alarm mode.
+ */
+void TEMPMON_SetTempAlarm(TEMPMON_Type *base, uint32_t tempVal, tempmon_alarm_mode alarmMode);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* _FSL_TEMPMON_H_ */
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_trng.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_trng.c
index 68864316fe1..28e02887dd3 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_trng.c
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_trng.c
@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
  * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 #include "fsl_trng.h"
 
@@ -46,10 +20,11 @@
 
 /* Default values for user configuration structure.*/
 #if (defined(KW40Z4_SERIES) || defined(KW41Z4_SERIES) || defined(KW31Z4_SERIES) || defined(KW21Z4_SERIES) || \
-     defined(MCIMX7U5_M4_SERIES) || defined(KW36Z4_SERIES))
+     defined(MCIMX7U5_M4_SERIES) || defined(KW36Z4_SERIES) || defined(KW37A4_SERIES) || defined(KW37Z4_SERIES) ||\
+     defined(KW38A4_SERIES) || defined(KW38Z4_SERIES) || defined(KW39A4_SERIES))
 #define TRNG_USER_CONFIG_DEFAULT_OSC_DIV kTRNG_RingOscDiv8
-#elif(defined(KV56F24_SERIES) || defined(KV58F24_SERIES) || defined(KL28Z7_SERIES) || defined(KL81Z7_SERIES) || \
-      defined(KL82Z7_SERIES))
+#elif (defined(KV56F24_SERIES) || defined(KV58F24_SERIES) || defined(KL28Z7_SERIES) || defined(KL81Z7_SERIES) || \
+       defined(KL82Z7_SERIES))
 #define TRNG_USER_CONFIG_DEFAULT_OSC_DIV kTRNG_RingOscDiv4
 #elif defined(K81F25615_SERIES)
 #define TRNG_USER_CONFIG_DEFAULT_OSC_DIV kTRNG_RingOscDiv2
@@ -86,8 +61,8 @@
 /*! @brief TRNG work mode */
 typedef enum _trng_work_mode
 {
-    kTRNG_WorkModeRun = 0U,    /*!< Run Mode. */
-    kTRNG_WorkModeProgram = 1U /*!< Program Mode. */
+    kTRNG_WorkModeRun     = 0U, /*!< Run Mode. */
+    kTRNG_WorkModeProgram = 1U  /*!< Program Mode. */
 } trng_work_mode_t;
 
 /*! @brief TRNG statistical check type*/
@@ -1248,40 +1223,78 @@ static uint32_t trng_GetInstance(TRNG_Type *base)
  * Description   :  Initializes user configuration structure to default settings.
  *
  *END*************************************************************************/
+/*!
+ * brief Initializes the user configuration structure to default values.
+ *
+ * This function initializes the configuration structure to default values. The default
+ * values are as follows.
+ * code
+ *     user_config->lock = 0;
+ *     user_config->clockMode = kTRNG_ClockModeRingOscillator;
+ *     user_config->ringOscDiv = kTRNG_RingOscDiv0;  Or  to other kTRNG_RingOscDiv[2|8] depending on the platform.
+ *     user_config->sampleMode = kTRNG_SampleModeRaw;
+ *     user_config->entropyDelay = 3200;
+ *     user_config->sampleSize = 2500;
+ *     user_config->sparseBitLimit = TRNG_USER_CONFIG_DEFAULT_SPARSE_BIT_LIMIT;
+ *     user_config->retryCount = 63;
+ *     user_config->longRunMaxLimit = 34;
+ *     user_config->monobitLimit.maximum = 1384;
+ *     user_config->monobitLimit.minimum = 1116;
+ *     user_config->runBit1Limit.maximum = 405;
+ *     user_config->runBit1Limit.minimum = 227;
+ *     user_config->runBit2Limit.maximum = 220;
+ *     user_config->runBit2Limit.minimum = 98;
+ *     user_config->runBit3Limit.maximum = 125;
+ *     user_config->runBit3Limit.minimum = 37;
+ *     user_config->runBit4Limit.maximum = 75;
+ *     user_config->runBit4Limit.minimum = 11;
+ *     user_config->runBit5Limit.maximum = 47;
+ *     user_config->runBit5Limit.minimum = 1;
+ *     user_config->runBit6PlusLimit.maximum = 47;
+ *     user_config->runBit6PlusLimit.minimum = 1;
+ *     user_config->pokerLimit.maximum = 26912;
+ *     user_config->pokerLimit.minimum = 24445;
+ *     user_config->frequencyCountLimit.maximum = 25600;
+ *     user_config->frequencyCountLimit.minimum = 1600;
+ * endcode
+ *
+ * param user_config   User configuration structure.
+ * return If successful, returns the kStatus_TRNG_Success. Otherwise, it returns an error.
+ */
 status_t TRNG_GetDefaultConfig(trng_config_t *userConfig)
 {
     status_t result;
 
     if (userConfig != NULL)
     {
-        userConfig->lock = TRNG_USER_CONFIG_DEFAULT_LOCK;
-        userConfig->clockMode = kTRNG_ClockModeRingOscillator;
-        userConfig->ringOscDiv = TRNG_USER_CONFIG_DEFAULT_OSC_DIV;
-        userConfig->sampleMode = kTRNG_SampleModeRaw;
-        userConfig->entropyDelay = TRNG_USER_CONFIG_DEFAULT_ENTROPY_DELAY;
-        userConfig->sampleSize = TRNG_USER_CONFIG_DEFAULT_SAMPLE_SIZE;
+        userConfig->lock           = (bool)TRNG_USER_CONFIG_DEFAULT_LOCK;
+        userConfig->clockMode      = kTRNG_ClockModeRingOscillator;
+        userConfig->ringOscDiv     = TRNG_USER_CONFIG_DEFAULT_OSC_DIV;
+        userConfig->sampleMode     = kTRNG_SampleModeRaw;
+        userConfig->entropyDelay   = TRNG_USER_CONFIG_DEFAULT_ENTROPY_DELAY;
+        userConfig->sampleSize     = TRNG_USER_CONFIG_DEFAULT_SAMPLE_SIZE;
         userConfig->sparseBitLimit = TRNG_USER_CONFIG_DEFAULT_SPARSE_BIT_LIMIT;
 
         /* Statistical Check Parameters.*/
-        userConfig->retryCount = TRNG_USER_CONFIG_DEFAULT_RETRY_COUNT;
+        userConfig->retryCount      = TRNG_USER_CONFIG_DEFAULT_RETRY_COUNT;
         userConfig->longRunMaxLimit = TRNG_USER_CONFIG_DEFAULT_RUN_MAX_LIMIT;
 
-        userConfig->monobitLimit.maximum = TRNG_USER_CONFIG_DEFAULT_MONOBIT_MAXIMUM;
-        userConfig->monobitLimit.minimum = TRNG_USER_CONFIG_DEFAULT_MONOBIT_MINIMUM;
-        userConfig->runBit1Limit.maximum = TRNG_USER_CONFIG_DEFAULT_RUNBIT1_MAXIMUM;
-        userConfig->runBit1Limit.minimum = TRNG_USER_CONFIG_DEFAULT_RUNBIT1_MINIMUM;
-        userConfig->runBit2Limit.maximum = TRNG_USER_CONFIG_DEFAULT_RUNBIT2_MAXIMUM;
-        userConfig->runBit2Limit.minimum = TRNG_USER_CONFIG_DEFAULT_RUNBIT2_MINIMUM;
-        userConfig->runBit3Limit.maximum = TRNG_USER_CONFIG_DEFAULT_RUNBIT3_MAXIMUM;
-        userConfig->runBit3Limit.minimum = TRNG_USER_CONFIG_DEFAULT_RUNBIT3_MINIMUM;
-        userConfig->runBit4Limit.maximum = TRNG_USER_CONFIG_DEFAULT_RUNBIT4_MAXIMUM;
-        userConfig->runBit4Limit.minimum = TRNG_USER_CONFIG_DEFAULT_RUNBIT4_MINIMUM;
-        userConfig->runBit5Limit.maximum = TRNG_USER_CONFIG_DEFAULT_RUNBIT5_MAXIMUM;
-        userConfig->runBit5Limit.minimum = TRNG_USER_CONFIG_DEFAULT_RUNBIT5_MINIMUM;
-        userConfig->runBit6PlusLimit.maximum = TRNG_USER_CONFIG_DEFAULT_RUNBIT6PLUS_MAXIMUM;
-        userConfig->runBit6PlusLimit.minimum = TRNG_USER_CONFIG_DEFAULT_RUNBIT6PLUS_MINIMUM;
-        userConfig->pokerLimit.maximum = TRNG_USER_CONFIG_DEFAULT_POKER_MAXIMUM;
-        userConfig->pokerLimit.minimum = TRNG_USER_CONFIG_DEFAULT_POKER_MINIMUM;
+        userConfig->monobitLimit.maximum        = TRNG_USER_CONFIG_DEFAULT_MONOBIT_MAXIMUM;
+        userConfig->monobitLimit.minimum        = TRNG_USER_CONFIG_DEFAULT_MONOBIT_MINIMUM;
+        userConfig->runBit1Limit.maximum        = TRNG_USER_CONFIG_DEFAULT_RUNBIT1_MAXIMUM;
+        userConfig->runBit1Limit.minimum        = TRNG_USER_CONFIG_DEFAULT_RUNBIT1_MINIMUM;
+        userConfig->runBit2Limit.maximum        = TRNG_USER_CONFIG_DEFAULT_RUNBIT2_MAXIMUM;
+        userConfig->runBit2Limit.minimum        = TRNG_USER_CONFIG_DEFAULT_RUNBIT2_MINIMUM;
+        userConfig->runBit3Limit.maximum        = TRNG_USER_CONFIG_DEFAULT_RUNBIT3_MAXIMUM;
+        userConfig->runBit3Limit.minimum        = TRNG_USER_CONFIG_DEFAULT_RUNBIT3_MINIMUM;
+        userConfig->runBit4Limit.maximum        = TRNG_USER_CONFIG_DEFAULT_RUNBIT4_MAXIMUM;
+        userConfig->runBit4Limit.minimum        = TRNG_USER_CONFIG_DEFAULT_RUNBIT4_MINIMUM;
+        userConfig->runBit5Limit.maximum        = TRNG_USER_CONFIG_DEFAULT_RUNBIT5_MAXIMUM;
+        userConfig->runBit5Limit.minimum        = TRNG_USER_CONFIG_DEFAULT_RUNBIT5_MINIMUM;
+        userConfig->runBit6PlusLimit.maximum    = TRNG_USER_CONFIG_DEFAULT_RUNBIT6PLUS_MAXIMUM;
+        userConfig->runBit6PlusLimit.minimum    = TRNG_USER_CONFIG_DEFAULT_RUNBIT6PLUS_MINIMUM;
+        userConfig->pokerLimit.maximum          = TRNG_USER_CONFIG_DEFAULT_POKER_MAXIMUM;
+        userConfig->pokerLimit.minimum          = TRNG_USER_CONFIG_DEFAULT_POKER_MINIMUM;
         userConfig->frequencyCountLimit.maximum = TRNG_USER_CONFIG_DEFAULT_FREQUENCY_MAXIMUM;
         userConfig->frequencyCountLimit.minimum = TRNG_USER_CONFIG_DEFAULT_FREQUENCY_MINIMUM;
 
@@ -1301,7 +1314,7 @@ status_t TRNG_GetDefaultConfig(trng_config_t *userConfig)
  * This function sets the retry counter which defines the number of times a
  * statistical check may fails during the TRNG Entropy Generation before
  * generating an error.
-*/
+ */
 static status_t trng_SetRetryCount(TRNG_Type *base, uint8_t retry_count)
 {
     status_t status;
@@ -1332,123 +1345,132 @@ static status_t trng_SetStatisticalCheckLimit(TRNG_Type *base,
     uint32_t range;
     status_t status = kStatus_Success;
 
-    if (limit && (limit->maximum > limit->minimum))
+    if ((NULL != limit) && (limit->maximum > limit->minimum))
     {
         range = limit->maximum - limit->minimum; /* Registers use range instead of minimum value.*/
 
-        switch (statistical_check)
+        if (statistical_check == kTRNG_StatisticalCheckMonobit) /* Allowable maximum and minimum number of ones/zero
+                                                                   detected during entropy generation. */
+        {
+            if ((range <= 0xffffu) && (limit->maximum <= 0xffffu))
+            {
+                TRNG_WR_SCML_MONO_MAX(base, limit->maximum);
+                TRNG_WR_SCML_MONO_RNG(base, range);
+            }
+            else
+            {
+                status = kStatus_InvalidArgument;
+            }
+        }
+        else if (statistical_check == kTRNG_StatisticalCheckRunBit1) /* Allowable maximum and minimum number of runs of
+                                                                        length 1 detected during entropy generation. */
+        {
+            if ((range <= 0x7fffu) && (limit->maximum <= 0x7fffu))
+            {
+                TRNG_WR_SCR1L_RUN1_MAX(base, limit->maximum);
+                TRNG_WR_SCR1L_RUN1_RNG(base, range);
+            }
+            else
+            {
+                status = kStatus_InvalidArgument;
+            }
+        }
+        else if (statistical_check == kTRNG_StatisticalCheckRunBit2) /* Allowable maximum and minimum number of runs of
+                                                                        length 2 detected during entropy generation. */
+        {
+            if ((range <= 0x3fffu) && (limit->maximum <= 0x3fffu))
+            {
+                TRNG_WR_SCR2L_RUN2_MAX(base, limit->maximum);
+                TRNG_WR_SCR2L_RUN2_RNG(base, range);
+            }
+            else
+            {
+                status = kStatus_InvalidArgument;
+            }
+        }
+        else if (statistical_check == kTRNG_StatisticalCheckRunBit3) /* Allowable maximum and minimum number of runs of
+                                                                        length 3 detected during entropy generation. */
+        {
+            if ((range <= 0x1fffu) && (limit->maximum <= 0x1fffu))
+            {
+                TRNG_WR_SCR3L_RUN3_MAX(base, limit->maximum);
+                TRNG_WR_SCR3L_RUN3_RNG(base, range);
+            }
+            else
+            {
+                status = kStatus_InvalidArgument;
+            }
+        }
+        else if (statistical_check == kTRNG_StatisticalCheckRunBit4) /* Allowable maximum and minimum number of runs of
+                                                                        length 4 detected during entropy generation. */
+        {
+            if ((range <= 0xfffu) && (limit->maximum <= 0xfffu))
+            {
+                TRNG_WR_SCR4L_RUN4_MAX(base, limit->maximum);
+                TRNG_WR_SCR4L_RUN4_RNG(base, range);
+            }
+            else
+            {
+                status = kStatus_InvalidArgument;
+            }
+        }
+        else if (statistical_check == kTRNG_StatisticalCheckRunBit5) /* Allowable maximum and minimum number of runs of
+                                                                        length 5 detected during entropy generation. */
+        {
+            if ((range <= 0x7ffu) && (limit->maximum <= 0x7ffu))
+            {
+                TRNG_WR_SCR5L_RUN5_MAX(base, limit->maximum);
+                TRNG_WR_SCR5L_RUN5_RNG(base, range);
+            }
+            else
+            {
+                status = kStatus_InvalidArgument;
+            }
+        }
+        else if (statistical_check == kTRNG_StatisticalCheckRunBit6Plus) /* Allowable maximum and minimum number of
+                                                                            length 6 or more detected during entropy
+                                                                            generation */
+        {
+            if ((range <= 0x7ffu) && (limit->maximum <= 0x7ffu))
+            {
+                TRNG_WR_SCR6PL_RUN6P_MAX(base, limit->maximum);
+                TRNG_WR_SCR6PL_RUN6P_RNG(base, range);
+            }
+            else
+            {
+                status = kStatus_InvalidArgument;
+            }
+        }
+        else if (statistical_check == kTRNG_StatisticalCheckPoker) /* Allowable maximum and minimum limit of "Poker
+                                                                      Test" detected during entropy generation . */
         {
-            case kTRNG_StatisticalCheckMonobit: /* Allowable maximum and minimum number of ones/zero detected during
-                                                   entropy generation. */
-                if ((range <= 0xffffu) && (limit->maximum <= 0xffffu))
-                {
-                    TRNG_WR_SCML_MONO_MAX(base, limit->maximum);
-                    TRNG_WR_SCML_MONO_RNG(base, range);
-                }
-                else
-                {
-                    status = kStatus_InvalidArgument;
-                }
-                break;
-            case kTRNG_StatisticalCheckRunBit1: /* Allowable maximum and minimum number of runs of length 1 detected
-                                                   during entropy generation. */
-                if ((range <= 0x7fffu) && (limit->maximum <= 0x7fffu))
-                {
-                    TRNG_WR_SCR1L_RUN1_MAX(base, limit->maximum);
-                    TRNG_WR_SCR1L_RUN1_RNG(base, range);
-                }
-                else
-                {
-                    status = kStatus_InvalidArgument;
-                }
-                break;
-            case kTRNG_StatisticalCheckRunBit2: /* Allowable maximum and minimum number of runs of length 2 detected
-                                                   during entropy generation. */
-                if ((range <= 0x3fffu) && (limit->maximum <= 0x3fffu))
-                {
-                    TRNG_WR_SCR2L_RUN2_MAX(base, limit->maximum);
-                    TRNG_WR_SCR2L_RUN2_RNG(base, range);
-                }
-                else
-                {
-                    status = kStatus_InvalidArgument;
-                }
-                break;
-            case kTRNG_StatisticalCheckRunBit3: /* Allowable maximum and minimum number of runs of length 3 detected
-                                                   during entropy generation. */
-                if ((range <= 0x1fffu) && (limit->maximum <= 0x1fffu))
-                {
-                    TRNG_WR_SCR3L_RUN3_MAX(base, limit->maximum);
-                    TRNG_WR_SCR3L_RUN3_RNG(base, range);
-                }
-                else
-                {
-                    status = kStatus_InvalidArgument;
-                }
-                break;
-            case kTRNG_StatisticalCheckRunBit4: /* Allowable maximum and minimum number of runs of length 4 detected
-                                                   during entropy generation. */
-                if ((range <= 0xfffu) && (limit->maximum <= 0xfffu))
-                {
-                    TRNG_WR_SCR4L_RUN4_MAX(base, limit->maximum);
-                    TRNG_WR_SCR4L_RUN4_RNG(base, range);
-                }
-                else
-                {
-                    status = kStatus_InvalidArgument;
-                }
-                break;
-            case kTRNG_StatisticalCheckRunBit5: /* Allowable maximum and minimum number of runs of length 5 detected
-                                                   during entropy generation. */
-                if ((range <= 0x7ffu) && (limit->maximum <= 0x7ffu))
-                {
-                    TRNG_WR_SCR5L_RUN5_MAX(base, limit->maximum);
-                    TRNG_WR_SCR5L_RUN5_RNG(base, range);
-                }
-                else
-                {
-                    status = kStatus_InvalidArgument;
-                }
-                break;
-            case kTRNG_StatisticalCheckRunBit6Plus: /* Allowable maximum and minimum number of length 6 or more detected
-                                                       during entropy generation */
-                if ((range <= 0x7ffu) && (limit->maximum <= 0x7ffu))
-                {
-                    TRNG_WR_SCR6PL_RUN6P_MAX(base, limit->maximum);
-                    TRNG_WR_SCR6PL_RUN6P_RNG(base, range);
-                }
-                else
-                {
-                    status = kStatus_InvalidArgument;
-                }
-                break;
-            case kTRNG_StatisticalCheckPoker: /* Allowable maximum and minimum limit of "Poker Test" detected during
-                                                 entropy generation . */
-                if ((range <= 0xffffu) && (limit->maximum <= 0xffffffu))
-                {
-                    TRNG_WR_PKRMAX_PKR_MAX(base, limit->maximum);
-                    TRNG_WR_PKRRNG_PKR_RNG(base, range);
-                }
-                else
-                {
-                    status = kStatus_InvalidArgument;
-                }
-                break;
-            case kTRNG_StatisticalCheckFrequencyCount: /* Allowable maximum and minimum limit of entropy sample frquency
-                                                          count during entropy generation . */
-                if ((limit->minimum <= 0x3fffffu) && (limit->maximum <= 0x3fffffu))
-                {
-                    TRNG_WR_FRQMAX_FRQ_MAX(base, limit->maximum);
-                    TRNG_WR_FRQMIN_FRQ_MIN(base, limit->minimum);
-                }
-                else
-                {
-                    status = kStatus_InvalidArgument;
-                }
-                break;
-            default:
+            if ((range <= 0xffffu) && (limit->maximum <= 0xffffffu))
+            {
+                TRNG_WR_PKRMAX_PKR_MAX(base, limit->maximum);
+                TRNG_WR_PKRRNG_PKR_RNG(base, range);
+            }
+            else
+            {
                 status = kStatus_InvalidArgument;
-                break;
+            }
+        }
+        else if (statistical_check == kTRNG_StatisticalCheckFrequencyCount) /* Allowable maximum and minimum limit of
+                                                                               entropy sample frquency count during
+                                                                               entropy generation . */
+        {
+            if ((limit->minimum <= 0x3fffffu) && (limit->maximum <= 0x3fffffu))
+            {
+                TRNG_WR_FRQMAX_FRQ_MAX(base, limit->maximum);
+                TRNG_WR_FRQMIN_FRQ_MIN(base, limit->minimum);
+            }
+            else
+            {
+                status = kStatus_InvalidArgument;
+            }
+        }
+        else
+        {
+            status = kStatus_InvalidArgument;
         }
     }
 
@@ -1465,35 +1487,75 @@ static status_t trng_ApplyUserConfig(TRNG_Type *base, const trng_config_t *userC
 {
     status_t status;
 
-    if (((status = trng_SetRetryCount(base, userConfig->retryCount)) == kStatus_Success) &&
-        ((status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckMonobit, &userConfig->monobitLimit)) ==
-         kStatus_Success) &&
-        ((status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckRunBit1, &userConfig->runBit1Limit)) ==
-         kStatus_Success) &&
-        ((status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckRunBit2, &userConfig->runBit2Limit)) ==
-         kStatus_Success) &&
-        ((status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckRunBit3, &userConfig->runBit3Limit)) ==
-         kStatus_Success) &&
-        ((status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckRunBit4, &userConfig->runBit4Limit)) ==
-         kStatus_Success) &&
-        ((status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckRunBit5, &userConfig->runBit5Limit)) ==
-         kStatus_Success) &&
-        ((status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckRunBit6Plus,
-                                                 &userConfig->runBit6PlusLimit)) == kStatus_Success) &&
-        ((status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckPoker, &userConfig->pokerLimit)) ==
-         kStatus_Success) &&
-        ((status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckFrequencyCount,
-                                                 &userConfig->frequencyCountLimit)) == kStatus_Success))
+    status = trng_SetRetryCount(base, userConfig->retryCount);
+    if (kStatus_Success != status)
+    {
+        return status;
+    }
+
+    status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckMonobit, &userConfig->monobitLimit);
+    if (kStatus_Success != status)
     {
-        TRNG_WR_MCTL_FOR_SCLK(base, userConfig->clockMode);
-        TRNG_WR_MCTL_OSC_DIV(base, userConfig->ringOscDiv);
-        TRNG_WR_MCTL_SAMP_MODE(base, userConfig->sampleMode);
-        TRNG_WR_SDCTL_ENT_DLY(base, userConfig->entropyDelay);
-        TRNG_WR_SDCTL_SAMP_SIZE(base, userConfig->sampleSize);
-        TRNG_WR_SBLIM_SB_LIM(base, userConfig->sparseBitLimit);
-        TRNG_WR_SCMISC_LRUN_MAX(base, userConfig->longRunMaxLimit);
+        return status;
     }
 
+    status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckRunBit1, &userConfig->runBit1Limit);
+    if (kStatus_Success != status)
+    {
+        return status;
+    }
+
+    status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckRunBit2, &userConfig->runBit2Limit);
+    if (kStatus_Success != status)
+    {
+        return status;
+    }
+
+    status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckRunBit3, &userConfig->runBit3Limit);
+    if (kStatus_Success != status)
+    {
+        return status;
+    }
+
+    status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckRunBit4, &userConfig->runBit4Limit);
+    if (kStatus_Success != status)
+    {
+        return status;
+    }
+
+    status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckRunBit5, &userConfig->runBit5Limit);
+    if (kStatus_Success != status)
+    {
+        return status;
+    }
+
+    status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckRunBit6Plus, &userConfig->runBit6PlusLimit);
+    if (kStatus_Success != status)
+    {
+        return status;
+    }
+
+    status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckPoker, &userConfig->pokerLimit);
+    if (kStatus_Success != status)
+    {
+        return status;
+    }
+
+    status =
+        trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckFrequencyCount, &userConfig->frequencyCountLimit);
+    if (kStatus_Success != status)
+    {
+        return status;
+    }
+
+    TRNG_WR_MCTL_FOR_SCLK(base, userConfig->clockMode);
+    TRNG_WR_MCTL_OSC_DIV(base, userConfig->ringOscDiv);
+    TRNG_WR_MCTL_SAMP_MODE(base, userConfig->sampleMode);
+    TRNG_WR_SDCTL_ENT_DLY(base, userConfig->entropyDelay);
+    TRNG_WR_SDCTL_SAMP_SIZE(base, userConfig->sampleSize);
+    TRNG_WR_SBLIM_SB_LIM(base, userConfig->sparseBitLimit);
+    TRNG_WR_SCMISC_LRUN_MAX(base, userConfig->longRunMaxLimit);
+
     return status;
 }
 
@@ -1503,7 +1565,7 @@ static status_t trng_ApplyUserConfig(TRNG_Type *base, const trng_config_t *userC
  * This function gets an entropy data from TRNG.
  * Entropy data is spread over TRNG_ENT_COUNT registers.
  * Read register number is defined by index parameter.
-*/
+ */
 static uint32_t trng_ReadEntropy(TRNG_Type *base, uint32_t index)
 {
     uint32_t data;
@@ -1512,7 +1574,7 @@ static uint32_t trng_ReadEntropy(TRNG_Type *base, uint32_t index)
 
     data = TRNG_RD_ENT(base, index);
 
-    if (index == (TRNG_ENT_COUNT - 1))
+    if (index == (TRNG_ENT_COUNT - 1u))
     {
         /* Dummy read. Defect workaround.
          * TRNG could not clear ENT_VAL  flag automatically, application
@@ -1524,6 +1586,16 @@ static uint32_t trng_ReadEntropy(TRNG_Type *base, uint32_t index)
     return data;
 }
 
+/*!
+ * brief Initializes the TRNG.
+ *
+ * This function initializes the TRNG.
+ * When called, the TRNG entropy generation starts immediately.
+ *
+ * param base  TRNG base address
+ * param userConfig    Pointer to the initialization configuration structure.
+ * return If successful, returns the kStatus_TRNG_Success. Otherwise, it returns an error.
+ */
 status_t TRNG_Init(TRNG_Type *base, const trng_config_t *userConfig)
 {
     status_t result;
@@ -1550,11 +1622,13 @@ status_t TRNG_Init(TRNG_Type *base, const trng_config_t *userConfig)
             TRNG_WR_MCTL_PRGM(base, kTRNG_WorkModeRun);
 #if !(defined(FSL_FEATURE_TRNG_HAS_NO_TRNG_ACC) && (FSL_FEATURE_TRNG_HAS_NO_TRNG_ACC > 0))
             /* Enable TRNG Access Mode. To generate an Entropy
-            * value that can be read via the true0-true15 registers.*/
+             * value that can be read via the true0-true15 registers.*/
             TRNG_WR_MCTL_TRNG_ACC(base, 1);
 #endif /* !FSL_FEATURE_TRNG_HAS_NO_TRNG_ACC */
 
-            if (userConfig->lock == 1) /* Disable programmability of TRNG registers. */
+            (void)trng_ReadEntropy(base, (TRNG_ENT_COUNT - 1u));
+
+            if (true == userConfig->lock) /* Disable programmability of TRNG registers. */
             {
                 TRNG_WR_SEC_CFG_NO_PRGM(base, 1);
             }
@@ -1570,10 +1644,17 @@ status_t TRNG_Init(TRNG_Type *base, const trng_config_t *userConfig)
     return result;
 }
 
+/*!
+ * brief Shuts down the TRNG.
+ *
+ * This function shuts down the TRNG.
+ *
+ * param base  TRNG base address.
+ */
 void TRNG_Deinit(TRNG_Type *base)
 {
     /* Check input parameters.*/
-    if (base)
+    if (NULL != base)
     {
         /* Move to program mode. Stop entropy generation.*/
         TRNG_WR_MCTL_PRGM(base, kTRNG_WorkModeProgram);
@@ -1584,7 +1665,7 @@ void TRNG_Deinit(TRNG_Type *base)
          is complete. If the TRNG clock is stopped while the TRNG ring oscillator
          is running, the oscillator continues running though the RNG clock.
          is stopped. */
-        while (TRNG_RD_MCTL_TSTOP_OK(base) == 0)
+        while (TRNG_RD_MCTL_TSTOP_OK(base) == 0u)
         {
         }
 
@@ -1595,6 +1676,16 @@ void TRNG_Deinit(TRNG_Type *base)
     }
 }
 
+/*!
+ * brief Gets random data.
+ *
+ * This function gets random data from the TRNG.
+ *
+ * param base  TRNG base address.
+ * param data  Pointer address used to store random data.
+ * param dataSize  Size of the buffer pointed by the data parameter.
+ * return random data
+ */
 status_t TRNG_GetRandomData(TRNG_Type *base, void *data, size_t dataSize)
 {
     status_t result = kStatus_Success;
@@ -1603,20 +1694,27 @@ status_t TRNG_GetRandomData(TRNG_Type *base, void *data, size_t dataSize)
     uint32_t random_size;
     uint8_t *data_p = (uint8_t *)data;
     uint32_t i;
+    uint32_t tmpValidFlag;
+    uint32_t tmpErrorFlag;
+
     int index = 0;
 
     /* Check input parameters.*/
-    if (base && data && dataSize)
+    if ((NULL != base) && (NULL != data) && (0U != dataSize))
     {
         do
         {
             /* Wait for Valid or Error flag*/
-            while ((TRNG_RD_MCTL_ENT_VAL(base) == 0) && (TRNG_RD_MCTL_ERR(base) == 0))
+            tmpValidFlag = TRNG_RD_MCTL_ENT_VAL(base);
+            tmpErrorFlag = TRNG_RD_MCTL_ERR(base);
+            while (tmpValidFlag == 0u && tmpErrorFlag == 0u)
             {
+                tmpValidFlag = TRNG_RD_MCTL_ENT_VAL(base);
+                tmpErrorFlag = TRNG_RD_MCTL_ERR(base);
             }
 
             /* Check HW error.*/
-            if (TRNG_RD_MCTL_ERR(base))
+            if (0U != TRNG_RD_MCTL_ERR(base))
             {
                 result = kStatus_Fail; /* TRNG module error occurred */
                 /* Clear error.*/
@@ -1625,7 +1723,7 @@ status_t TRNG_GetRandomData(TRNG_Type *base, void *data, size_t dataSize)
             }
 
             /* Read Entropy.*/
-            random_32 = trng_ReadEntropy(base, index++);
+            random_32 = trng_ReadEntropy(base, (uint32_t)index++);
 
             random_p = (uint8_t *)&random_32;
 
@@ -1644,13 +1742,13 @@ status_t TRNG_GetRandomData(TRNG_Type *base, void *data, size_t dataSize)
             }
 
             dataSize -= random_size;
-        } while (dataSize > 0);
+        } while (dataSize > 0u);
 
         /* Start a new entropy generation.
         It is done by reading of the last entropy register.*/
-        if ((index % TRNG_ENT_COUNT) != (TRNG_ENT_COUNT - 1))
+        if (((unsigned)index % TRNG_ENT_COUNT) != (TRNG_ENT_COUNT - 1u))
         {
-            trng_ReadEntropy(base, (TRNG_ENT_COUNT - 1));
+            (void)trng_ReadEntropy(base, (TRNG_ENT_COUNT - 1u));
         }
     }
     else
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_trng.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_trng.h
index de844e892ed..a2c3911428f 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_trng.h
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_trng.h
@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
  * Copyright 2016-2018 NXP
  * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
  *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 #ifndef _FSL_TRNG_DRIVER_H_
 #define _FSL_TRNG_DRIVER_H_
@@ -43,32 +17,35 @@
  * @{
  */
 
-
 /*******************************************************************************
  * Definitions
  *******************************************************************************/
 
 /*! @name Driver version */
 /*@{*/
-/*! @brief TRNG driver version 2.0.2. 
+/*! @brief TRNG driver version 2.0.4.
  *
- * Current version: 2.0.2
+ * Current version: 2.0.4
  *
  * Change log:
+ * - version 2.0.4
+ *   - Fix MISRA-2012 issues.
+ * - Version 2.0.3
+ *   - update TRNG_Init to restart entropy generation
  * - Version 2.0.2
  *   - fix MISRA issues
  * - Version 2.0.1
  *   - add support for KL8x and KL28Z
  *   - update default OSCDIV for K81 to divide by 2
  */
-#define FSL_TRNG_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
+#define FSL_TRNG_DRIVER_VERSION (MAKE_VERSION(2, 0, 4))
 /*@}*/
 
 /*! @brief TRNG sample mode. Used by trng_config_t. */
 typedef enum _trng_sample_mode
 {
     kTRNG_SampleModeVonNeumann = 0U, /*!< Use von Neumann data in both Entropy shifter and Statistical Checker. */
-    kTRNG_SampleModeRaw = 1U,        /*!< Use raw data into both Entropy shifter and Statistical Checker. */
+    kTRNG_SampleModeRaw        = 1U, /*!< Use raw data into both Entropy shifter and Statistical Checker. */
     kTRNG_SampleModeVonNeumannRaw =
         2U /*!< Use von Neumann data in Entropy shifter. Use raw data into Statistical Checker. */
 } trng_sample_mode_t;
@@ -77,7 +54,7 @@ typedef enum _trng_sample_mode
 typedef enum _trng_clock_mode
 {
     kTRNG_ClockModeRingOscillator = 0U, /*!< Ring oscillator is used to operate the TRNG (default). */
-    kTRNG_ClockModeSystem = 1U          /*!< System clock is used to operate the TRNG. This is for test use only, and
+    kTRNG_ClockModeSystem         = 1U  /*!< System clock is used to operate the TRNG. This is for test use only, and
                                            indeterminate results may occur. */
 } trng_clock_mode_t;
 
@@ -114,44 +91,36 @@ typedef struct _trng_user_config
         entropyDelay; /*!< @brief Entropy Delay. Defines the length (in system clocks) of each Entropy sample taken. */
     uint16_t sampleSize; /*!< @brief Sample Size. Defines the total number of Entropy samples that will be taken during
                             Entropy generation. */
-    uint16_t
-        sparseBitLimit; /*!< @brief Sparse Bit Limit which defines the maximum number of
-                        * consecutive samples that may be discarded before an error is generated.
-                        * This limit is used only for during von Neumann sampling (enabled by TRNG_HAL_SetSampleMode()).
-                        * Samples are discarded if two consecutive raw samples are both 0 or both 1. If
-                        * this discarding occurs for a long period of time, it indicates that there is
-                        * insufficient Entropy. */
+    uint16_t sparseBitLimit; /*!< @brief Sparse Bit Limit which defines the maximum number of
+                              * consecutive samples that may be discarded before an error is generated.
+                              * This limit is used only for during von Neumann sampling (enabled by
+                              * TRNG_HAL_SetSampleMode()). Samples are discarded if two consecutive raw samples are both
+                              * 0 or both 1. If this discarding occurs for a long period of time, it indicates that
+                              * there is insufficient Entropy. */
     /* Statistical Check Parameters.*/
     uint8_t retryCount;      /*!< @brief Retry count. It defines the number of times a statistical check may fails
-                             * during the TRNG Entropy Generation before generating an error. */
+                              * during the TRNG Entropy Generation before generating an error. */
     uint8_t longRunMaxLimit; /*!< @brief Largest allowable number of consecutive samples of all 1, or all 0,
-                             * that is allowed during the Entropy generation. */
-    trng_statistical_check_limit_t
-        monobitLimit; /*!< @brief Maximum and minimum limits for statistical check of number of ones/zero detected
-                         during entropy generation. */
-    trng_statistical_check_limit_t
-        runBit1Limit; /*!< @brief Maximum and minimum limits for statistical check of number of runs of length 1
-                         detected during entropy generation. */
-    trng_statistical_check_limit_t
-        runBit2Limit; /*!< @brief Maximum and minimum limits for statistical check of number of runs of length 2
-                         detected during entropy generation. */
-    trng_statistical_check_limit_t
-        runBit3Limit; /*!< @brief Maximum and minimum limits for statistical check of number of runs of length 3
-                         detected during entropy generation. */
-    trng_statistical_check_limit_t
-        runBit4Limit; /*!< @brief Maximum and minimum limits for statistical check of number of runs of length 4
-                         detected during entropy generation. */
-    trng_statistical_check_limit_t
-        runBit5Limit; /*!< @brief Maximum and minimum limits for statistical check of number of runs of length 5
-                         detected during entropy generation. */
+                              * that is allowed during the Entropy generation. */
+    trng_statistical_check_limit_t monobitLimit; /*!< @brief Maximum and minimum limits for statistical check of number
+                                                    of ones/zero detected during entropy generation. */
+    trng_statistical_check_limit_t runBit1Limit; /*!< @brief Maximum and minimum limits for statistical check of number
+                                                    of runs of length 1 detected during entropy generation. */
+    trng_statistical_check_limit_t runBit2Limit; /*!< @brief Maximum and minimum limits for statistical check of number
+                                                    of runs of length 2 detected during entropy generation. */
+    trng_statistical_check_limit_t runBit3Limit; /*!< @brief Maximum and minimum limits for statistical check of number
+                                                    of runs of length 3 detected during entropy generation. */
+    trng_statistical_check_limit_t runBit4Limit; /*!< @brief Maximum and minimum limits for statistical check of number
+                                                    of runs of length 4 detected during entropy generation. */
+    trng_statistical_check_limit_t runBit5Limit; /*!< @brief Maximum and minimum limits for statistical check of number
+                                                    of runs of length 5 detected during entropy generation. */
     trng_statistical_check_limit_t runBit6PlusLimit; /*!< @brief Maximum and minimum limits for statistical check of
                                                         number of runs of length 6 or more detected during entropy
                                                         generation. */
     trng_statistical_check_limit_t
         pokerLimit; /*!< @brief Maximum and minimum limits for statistical check of "Poker Test". */
-    trng_statistical_check_limit_t
-        frequencyCountLimit; /*!< @brief Maximum and minimum limits for statistical check of entropy sample frequency
-                                count. */
+    trng_statistical_check_limit_t frequencyCountLimit; /*!< @brief Maximum and minimum limits for statistical check of
+                                                           entropy sample frequency count. */
 } trng_config_t;
 
 /*******************************************************************************
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_tsc.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_tsc.c
index 75f5c62d217..47f52b3db06 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_tsc.c
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_tsc.c
@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2016, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
  * All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include "fsl_tsc.h"
@@ -39,7 +13,6 @@
 #define FSL_COMPONENT_ID "platform.drivers.tsc"
 #endif
 
-
 /*******************************************************************************
  * Prototypes
  ******************************************************************************/
@@ -56,8 +29,10 @@ static uint32_t TSC_GetInstance(TSC_Type *base);
 /*! @brief Pointers to TSC bases for each instance. */
 static TSC_Type *const s_tscBases[] = TSC_BASE_PTRS;
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
 /*! @brief Pointers to ADC clocks for each instance. */
 static const clock_ip_name_t s_tscClocks[] = TSC_CLOCKS;
+#endif
 
 /*******************************************************************************
  * Code
@@ -80,6 +55,12 @@ static uint32_t TSC_GetInstance(TSC_Type *base)
     return instance;
 }
 
+/*!
+ * brief Initialize the TSC module.
+ *
+ * param base TSC peripheral base address.
+ * param config Pointer to "tsc_config_t" structure.
+ */
 void TSC_Init(TSC_Type *base, const tsc_config_t *config)
 {
     assert(NULL != config);
@@ -103,6 +84,11 @@ void TSC_Init(TSC_Type *base, const tsc_config_t *config)
     base->PRE_CHARGE_TIME = TSC_PRE_CHARGE_TIME_PRE_CHARGE_TIME(config->prechargeTime);
 }
 
+/*!
+ * brief De-initializes the TSC module.
+ *
+ * param base TSC peripheral base address.
+ */
 void TSC_Deinit(TSC_Type *base)
 {
 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
@@ -111,14 +97,40 @@ void TSC_Deinit(TSC_Type *base)
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }
 
+/*!
+ * brief Gets an available pre-defined settings for the controller's configuration.
+ *
+ * This function initializes the converter configuration structure with available settings.
+ * The default values of measureDelayTime and prechargeTime is tested on LCD8000-43T screen and work normally.
+ * The default values are:
+ * code
+ *    config->enableAutoMeausre = false;
+ *    config->measureDelayTime = 0xFFFFU;
+ *    config->prechargeTime = 0xFFFFU;
+ *    config->detectionMode = kTSC_4WireDetectionMode;
+ * endCode
+ * param config Pointer to "tsc_config_t" structure.
+ */
 void TSC_GetDefaultConfig(tsc_config_t *config)
 {
+    /* Initializes the configure structure to zero. */
+    memset(config, 0, sizeof(*config));
+
     config->enableAutoMeasure = false;
-    config->measureDelayTime = 0xFFFFU;
-    config->prechargeTime = 0xFFFFU;
-    config->detectionMode = kTSC_Detection4WireMode;
+    config->measureDelayTime  = 0xFFFFU;
+    config->prechargeTime     = 0xFFFFU;
+    config->detectionMode     = kTSC_Detection4WireMode;
 }
 
+/*!
+ * brief Get Y coordinate value or X coordinate value. The value is an ADC conversion value.
+ *
+ * param base TSC peripheral base address.
+ * param selection Select alternative measure value which is Y coordinate value or X coordinate value.
+ *        See "tsc_corrdinate_value_selection_t".
+ * return If selection is "kTSC_XCoordinateValueSelection", the API returns x-coordinate vlaue.
+ *         If selection is "kTSC_YCoordinateValueSelection", the API returns y-coordinate vlaue.
+ */
 uint32_t TSC_GetMeasureValue(TSC_Type *base, tsc_corrdinate_value_selection_t selection)
 {
     uint32_t tmp32 = 0;
@@ -137,6 +149,15 @@ uint32_t TSC_GetMeasureValue(TSC_Type *base, tsc_corrdinate_value_selection_t se
     return tmp32;
 }
 
+/*!
+ * brief Send hardware trigger signal to ADC in debug mode. The trigger signal must last at least 1 ips clock period.
+ *
+ * param base TSC peripheral base address.
+ * param hwts Hardware trigger select signal, select which channel to start conversion. See "tsc_trigger_signal_t".
+ *             On ADC side, HWTS = 1 << x indicates the x logic channel is selected to start hardware ADC conversion.
+ * param enable Switcher of the trigger signal. "true" means generate trigger signal, "false" means don't generate
+ *               trigger signal.
+ */
 void TSC_DebugTriggerSignalToADC(TSC_Type *base, tsc_trigger_signal_t hwts, bool enable)
 {
     if (enable)
@@ -153,6 +174,13 @@ void TSC_DebugTriggerSignalToADC(TSC_Type *base, tsc_trigger_signal_t hwts, bool
     }
 }
 
+/*!
+ * brief Enable/Disable detection in debug mode.
+ *
+ * param base TSC peripheral base address.
+ * param detectionMode Set detect mode. See "tsc_detection_mode_t"
+ * param enable Switcher of detect enable. "true" means enable detection, "false" means disable detection.
+ */
 void TSC_DebugEnableDetection(TSC_Type *base, tsc_detection_mode_t detectionMode, bool enable)
 {
     if (detectionMode == kTSC_Detection4WireMode)
@@ -182,6 +210,13 @@ void TSC_DebugEnableDetection(TSC_Type *base, tsc_detection_mode_t detectionMode
     }
 }
 
+/*!
+ * brief Set TSC port mode in debug mode.(pull down, pull up and 200k-pull up)
+ *
+ * param base TSC peripheral base address.
+ * param port TSC controller ports.
+ * param mode TSC port mode.(pull down, pull up and 200k-pull up)
+ */
 void TSC_DebugSetPortMode(TSC_Type *base, tsc_port_source_t port, tsc_port_mode_t mode)
 {
     uint32_t tmp32;
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_tsc.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_tsc.h
index 84ea3206339..bb94af43083 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_tsc.h
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_tsc.h
@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
+ * Copyright 2016-2019 NXP
  * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
  *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #ifndef _FSL_TSC_H_
@@ -43,14 +17,14 @@
  */
 
 /*******************************************************************************
-* Definitions
-******************************************************************************/
+ * Definitions
+ ******************************************************************************/
 /*! @brief TSC driver version */
-#define FSL_TSC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */
+#define FSL_TSC_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) /*!< Version 2.0.2. */
 
 /*!
-* @ Controller detection mode.
-*/
+ * @ Controller detection mode.
+ */
 typedef enum _tsc_detection_mode
 {
     kTSC_Detection4WireMode = 0U, /*!< 4-Wire Detection Mode. */
@@ -58,8 +32,8 @@ typedef enum _tsc_detection_mode
 } tsc_detection_mode_t;
 
 /*!
-* @ Coordinate value mask.
-*/
+ * @ Coordinate value mask.
+ */
 typedef enum _tsc_corrdinate_value_selection
 {
     kTSC_XCoordinateValueSelection = 0U, /*!< X coordinate value is selected. */
@@ -67,17 +41,16 @@ typedef enum _tsc_corrdinate_value_selection
 } tsc_corrdinate_value_selection_t;
 
 /*!
-* @ Interrupt signal enable/disable mask.
-*/
+ * @ Interrupt signal enable/disable mask.
+ */
 enum _tsc_interrupt_signal_mask
 {
     kTSC_IdleSoftwareSignalEnable = TSC_INT_SIG_EN_IDLE_SW_SIG_EN_MASK, /*!< Enable the interrupt signal when the
                                                                            controller has return to idle status.
                                                                              The signal is only valid after using
                                                                            TSC_ReturnToIdleStatus API. */
-    kTSC_ValidSignalEnable =
-        TSC_INT_SIG_EN_VALID_SIG_EN_MASK, /*!< Enable the interrupt signal when controller receives a detect signal
-                                             after measurement. */
+    kTSC_ValidSignalEnable = TSC_INT_SIG_EN_VALID_SIG_EN_MASK, /*!< Enable the interrupt signal when controller receives
+                                                                  a detect signal after measurement. */
     kTSC_DetectSignalEnable =
         TSC_INT_SIG_EN_DETECT_SIG_EN_MASK, /*!< Enable the interrupt signal when controller receives a detect signal. */
     kTSC_MeasureSignalEnable = TSC_INT_SIG_EN_MEASURE_SIG_EN_MASK, /*!< Enable the interrupt signal after the touch
@@ -85,8 +58,8 @@ enum _tsc_interrupt_signal_mask
 };
 
 /*!
-* @ Interrupt enable/disable mask.
-*/
+ * @ Interrupt enable/disable mask.
+ */
 enum _tsc_interrupt_mask
 {
     kTSC_IdleSoftwareInterruptEnable =
@@ -99,8 +72,8 @@ enum _tsc_interrupt_mask
 };
 
 /*!
-* @ Interrupt Status flag mask.
-*/
+ * @ Interrupt Status flag mask.
+ */
 enum _tsc_interrupt_status_flag_mask
 {
     kTSC_IdleSoftwareFlag =
@@ -115,20 +88,19 @@ enum _tsc_interrupt_status_flag_mask
 };
 
 /*!
-* @ ADC status flag mask.
-*/
+ * @ ADC status flag mask.
+ */
 enum _tsc_adc_status_flag_mask
 {
     kTSC_ADCCOCOSignalFlag =
         TSC_DEBUG_MODE_ADC_COCO_MASK, /*!< This signal is generated by ADC when a conversion is completed. */
-    kTSC_ADCConversionValueFlag =
-        TSC_DEBUG_MODE_ADC_CONV_VALUE_MASK, /*!< This signal is generated by ADC and indicates the result of an ADC
-                                               conversion. */
+    kTSC_ADCConversionValueFlag = TSC_DEBUG_MODE_ADC_CONV_VALUE_MASK, /*!< This signal is generated by ADC and indicates
+                                                                         the result of an ADC conversion. */
 };
 
 /*!
-* @ TSC status flag mask.
-*/
+ * @ TSC status flag mask.
+ */
 enum _tsc_status_flag_mask
 {
     kTSC_IntermediateStateFlag = TSC_DEBUG_MODE2_INTERMEDIATE_MASK,  /*!< This flag is set if TSC is in intermediate
@@ -164,41 +136,38 @@ enum _tsc_status_flag_mask
 };
 
 /*!
-* @brief TSC state machine. These seven states are TSC complete workflow.
-*/
+ * @brief TSC state machine. These seven states are TSC complete workflow.
+ */
 typedef enum _tsc_state_machine
 {
-    kTSC_IdleState = 0U << TSC_DEBUG_MODE2_STATE_MACHINE_SHIFT,         /*!< Controller is in idle state. */
+    kTSC_IdleState         = 0U << TSC_DEBUG_MODE2_STATE_MACHINE_SHIFT, /*!< Controller is in idle state. */
     kTSC_1stPreChargeState = 1U << TSC_DEBUG_MODE2_STATE_MACHINE_SHIFT, /*!< Controller is in 1st-Pre-charge state. */
-    kTSC_1stDetectState = 2U << TSC_DEBUG_MODE2_STATE_MACHINE_SHIFT,    /*!< Controller is in 1st-detect state. */
-    kTSC_XMeasureState = 3U << TSC_DEBUG_MODE2_STATE_MACHINE_SHIFT,     /*!< Controller is in x-measure state. */
-    kTSC_YMeasureState = 4U << TSC_DEBUG_MODE2_STATE_MACHINE_SHIFT,     /*!< Controller is in y-measure state. */
+    kTSC_1stDetectState    = 2U << TSC_DEBUG_MODE2_STATE_MACHINE_SHIFT, /*!< Controller is in 1st-detect state. */
+    kTSC_XMeasureState     = 3U << TSC_DEBUG_MODE2_STATE_MACHINE_SHIFT, /*!< Controller is in x-measure state. */
+    kTSC_YMeasureState     = 4U << TSC_DEBUG_MODE2_STATE_MACHINE_SHIFT, /*!< Controller is in y-measure state. */
     kTSC_2ndPreChargeState = 5U << TSC_DEBUG_MODE2_STATE_MACHINE_SHIFT, /*!< Controller is in 2nd-Pre-charge state. */
-    kTSC_2ndDetectState = 6U << TSC_DEBUG_MODE2_STATE_MACHINE_SHIFT,    /*!< Controller is in 2nd-detect state. */
+    kTSC_2ndDetectState    = 6U << TSC_DEBUG_MODE2_STATE_MACHINE_SHIFT, /*!< Controller is in 2nd-detect state. */
 } tsc_state_machine_t;
 
 /*!
-* @brief TSC glitch threshold.
-*/
+ * @brief TSC glitch threshold.
+ */
 typedef enum _tsc_glitch_threshold
 {
-    kTSC_glitchThresholdALT0 =
-        0U << TSC_DEBUG_MODE2_DE_GLITCH_SHIFT, /*!< Normal function: 0x1fff ipg clock cycles, Low power mode: 0x9 low
-                                                          power clock cycles. */
-    kTSC_glitchThresholdALT1 =
-        1U << TSC_DEBUG_MODE2_DE_GLITCH_SHIFT, /*!< Normal function: 0xfff ipg clock cycles, Low power mode: :0x7 low
-                                                          power clock cycles. */
-    kTSC_glitchThresholdALT2 =
-        2U << TSC_DEBUG_MODE2_DE_GLITCH_SHIFT, /*!< Normal function: 0x7ff ipg clock cycles, Low power mode: :0x5 low
-                                                          power clock cycles. */
+    kTSC_glitchThresholdALT0 = 0U << TSC_DEBUG_MODE2_DE_GLITCH_SHIFT, /*!< Normal function: 0x1fff ipg clock cycles, Low
+                                                                         power mode: 0x9 low power clock cycles. */
+    kTSC_glitchThresholdALT1 = 1U << TSC_DEBUG_MODE2_DE_GLITCH_SHIFT, /*!< Normal function: 0xfff ipg clock cycles, Low
+                                                                         power mode: :0x7 low power clock cycles. */
+    kTSC_glitchThresholdALT2 = 2U << TSC_DEBUG_MODE2_DE_GLITCH_SHIFT, /*!< Normal function: 0x7ff ipg clock cycles, Low
+                                                                         power mode: :0x5 low power clock cycles. */
     kTSC_glitchThresholdALT3 =
         3U << TSC_DEBUG_MODE2_DE_GLITCH_SHIFT, /*!< Normal function: 0x3 ipg clock cycles, Low
-                                                          power mode: :0x3 low power clock cycles. */
+                                                           power mode: :0x3 low power clock cycles. */
 } tsc_glitch_threshold_t;
 
 /*!
-* @ Hardware trigger select signal, select which ADC channel to start conversion.
-*/
+ * @ Hardware trigger select signal, select which ADC channel to start conversion.
+ */
 typedef enum _tsc_trigger_signal
 {
     kTSC_TriggerToChannel0 = 1U << 0U, /*!< Trigger to ADC channel0. ADC_HC0 register will be used to conversion. */
@@ -209,31 +178,31 @@ typedef enum _tsc_trigger_signal
 } tsc_trigger_signal_t;
 
 /*!
-* @ TSC controller ports.
-*/
+ * @ TSC controller ports.
+ */
 typedef enum _tsc_port_source
 {
     kTSC_WiperPortSource = 0U, /*!< TSC controller wiper port. */
-    kTSC_YnlrPortSource = 1U,  /*!< TSC controller ynlr port. */
-    kTSC_YpllPortSource = 2U,  /*!< TSC controller ypll port. */
-    kTSC_XnurPortSource = 3U,  /*!< TSC controller xnur port. */
-    kTSC_XpulPortSource = 4U,  /*!< TSC controller xpul port. */
+    kTSC_YnlrPortSource  = 1U, /*!< TSC controller ynlr port. */
+    kTSC_YpllPortSource  = 2U, /*!< TSC controller ypll port. */
+    kTSC_XnurPortSource  = 3U, /*!< TSC controller xnur port. */
+    kTSC_XpulPortSource  = 4U, /*!< TSC controller xpul port. */
 } tsc_port_source_t;
 
 /*!
-* @ TSC port mode.
-*/
+ * @ TSC port mode.
+ */
 typedef enum _tsc_port_mode
 {
-    kTSC_PortOffMode = 0U,               /*!< Disable pull up/down mode. */
+    kTSC_PortOffMode         = 0U,       /*!< Disable pull up/down mode. */
     kTSC_Port200k_PullUpMode = 1U << 2U, /*!< 200k-pull up mode. */
-    kTSC_PortPullUpMode = 1U << 1U,      /*!< Pull up mode. */
-    kTSC_PortPullDownMode = 1U << 0U,    /*!< Pull down mode. */
+    kTSC_PortPullUpMode      = 1U << 1U, /*!< Pull up mode. */
+    kTSC_PortPullDownMode    = 1U << 0U, /*!< Pull down mode. */
 } tsc_port_mode_t;
 
 /*!
-* @ Controller configuration.
-*/
+ * @ Controller configuration.
+ */
 typedef struct _tsc_config
 {
     bool enableAutoMeasure;    /*!< Enable the auto-measure. It indicates after detect touch, whether automatic start
@@ -250,49 +219,49 @@ typedef struct _tsc_config
 } tsc_config_t;
 
 /*******************************************************************************
-* API
-******************************************************************************/
+ * API
+ ******************************************************************************/
 #if defined(__cplusplus)
 extern "C" {
 #endif
 
 /*!
-* @brief Initialize the TSC module.
-*
-* @param base TSC peripheral base address.
-* @param config Pointer to "tsc_config_t" structure.
-*/
+ * @brief Initialize the TSC module.
+ *
+ * @param base TSC peripheral base address.
+ * @param config Pointer to "tsc_config_t" structure.
+ */
 void TSC_Init(TSC_Type *base, const tsc_config_t *config);
 
 /*!
-* @brief De-initializes the TSC module.
-*
-* @param base TSC peripheral base address.
-*/
+ * @brief De-initializes the TSC module.
+ *
+ * @param base TSC peripheral base address.
+ */
 void TSC_Deinit(TSC_Type *base);
 
 /*!
-* @brief Gets an available pre-defined settings for the controller's configuration.
-*
-* This function initializes the converter configuration structure with available settings.
-* The default values of measureDelayTime and prechargeTime is tested on LCD8000-43T screen and work normally.
-* The default values are:
-* @code
-*    config->enableAutoMeausre = false;
-*    config->measureDelayTime = 0xFFFFU;
-*    config->prechargeTime = 0xFFFFU;
-*    config->detectionMode = kTSC_4WireDetectionMode;
-* @endCode
-* @param config Pointer to "tsc_config_t" structure.
-*/
+ * @brief Gets an available pre-defined settings for the controller's configuration.
+ *
+ * This function initializes the converter configuration structure with available settings.
+ * The default values of measureDelayTime and prechargeTime is tested on LCD8000-43T screen and work normally.
+ * The default values are:
+ * @code
+ *    config->enableAutoMeausre = false;
+ *    config->measureDelayTime = 0xFFFFU;
+ *    config->prechargeTime = 0xFFFFU;
+ *    config->detectionMode = kTSC_4WireDetectionMode;
+ * @endCode
+ * @param config Pointer to "tsc_config_t" structure.
+ */
 void TSC_GetDefaultConfig(tsc_config_t *config);
 
 /*!
-* @brief Make the TSC module return to idle status after finish the current state operation.
-*        Application could check TSC status to confirm that the controller has return to idle status.
-*
-* @param base TSC peripheral base address.
-*/
+ * @brief Make the TSC module return to idle status after finish the current state operation.
+ *        Application could check TSC status to confirm that the controller has return to idle status.
+ *
+ * @param base TSC peripheral base address.
+ */
 static inline void TSC_ReturnToIdleStatus(TSC_Type *base)
 {
     /* TSC_FLOW_CONTROL_DISABLE_MASK is a HW self-clean bit. */
@@ -300,10 +269,10 @@ static inline void TSC_ReturnToIdleStatus(TSC_Type *base)
 }
 
 /*!
-* @brief Start sense detection and (if work in auto-measure mode) measure after detect a touch.
-*
-* @param base TSC peripheral base address.
-*/
+ * @brief Start sense detection and (if work in auto-measure mode) measure after detect a touch.
+ *
+ * @param base TSC peripheral base address.
+ */
 static inline void TSC_StartSenseDetection(TSC_Type *base)
 {
     /* TSC_FLOW_CONTROL_START_SENSE_MASK is a HW self-clean bit. */
@@ -311,10 +280,10 @@ static inline void TSC_StartSenseDetection(TSC_Type *base)
 }
 
 /*!
-* @brief start measure X/Y coordinate value after detect a touch.
-*
-* @param base TSC peripheral base address.
-*/
+ * @brief start measure X/Y coordinate value after detect a touch.
+ *
+ * @param base TSC peripheral base address.
+ */
 static inline void TSC_StartMeasure(TSC_Type *base)
 {
     /* TSC_FLOW_CONTROL_START_MEASURE_MASK is a HW self-clean bit. */
@@ -322,10 +291,10 @@ static inline void TSC_StartMeasure(TSC_Type *base)
 }
 
 /*!
-* @brief Drop measure X/Y coordinate value after detect a touch and controller return to idle status.
-*
-* @param base TSC peripheral base address.
-*/
+ * @brief Drop measure X/Y coordinate value after detect a touch and controller return to idle status.
+ *
+ * @param base TSC peripheral base address.
+ */
 static inline void TSC_DropMeasure(TSC_Type *base)
 {
     /* TSC_FLOW_CONTROL_DROP_MEASURE_MASK is a HW self-clean bit. */
@@ -333,10 +302,10 @@ static inline void TSC_DropMeasure(TSC_Type *base)
 }
 
 /*!
-* @brief This is a synchronization reset, which resets every register except IPS directly access ones.
-*
-* @param base TSC peripheral base address.
-*/
+ * @brief This is a synchronization reset, which resets every register except IPS directly access ones.
+ *
+ * @param base TSC peripheral base address.
+ */
 static inline void TSC_SoftwareReset(TSC_Type *base)
 {
     /* TSC_FLOW_CONTROL_SW_RST_MASK is a HW self-clean bit. */
@@ -344,106 +313,106 @@ static inline void TSC_SoftwareReset(TSC_Type *base)
 }
 
 /*!
-* @brief Get Y coordinate value or X coordinate value. The value is an ADC conversion value.
-*
-* @param base TSC peripheral base address.
-* @param selection Select alternative measure value which is Y coordinate value or X coordinate value.
-*        See "tsc_corrdinate_value_selection_t".
-* @return If selection is "kTSC_XCoordinateValueSelection", the API returns x-coordinate vlaue.
-*         If selection is "kTSC_YCoordinateValueSelection", the API returns y-coordinate vlaue.
-*/
+ * @brief Get Y coordinate value or X coordinate value. The value is an ADC conversion value.
+ *
+ * @param base TSC peripheral base address.
+ * @param selection Select alternative measure value which is Y coordinate value or X coordinate value.
+ *        See "tsc_corrdinate_value_selection_t".
+ * @return If selection is "kTSC_XCoordinateValueSelection", the API returns x-coordinate vlaue.
+ *         If selection is "kTSC_YCoordinateValueSelection", the API returns y-coordinate vlaue.
+ */
 uint32_t TSC_GetMeasureValue(TSC_Type *base, tsc_corrdinate_value_selection_t selection);
 
 /*!
-* @brief Enable the interrupt signals. Interrupt signal will be set when corresponding event happens.
-*        Specific events point to "_tsc_interrupt_signal_mask" .
-*        Specific interrupt signal point to "_tsc_interrupt_status_flag_mask";
-*
-* @param base TSC peripheral base address.
-* @param mask Interrupt signals mask. See "_tsc_interrupt_signal_mask".
-*/
+ * @brief Enable the interrupt signals. Interrupt signal will be set when corresponding event happens.
+ *        Specific events point to "_tsc_interrupt_signal_mask" .
+ *        Specific interrupt signal point to "_tsc_interrupt_status_flag_mask";
+ *
+ * @param base TSC peripheral base address.
+ * @param mask Interrupt signals mask. See "_tsc_interrupt_signal_mask".
+ */
 static inline void TSC_EnableInterruptSignals(TSC_Type *base, uint32_t mask)
 {
     base->INT_SIG_EN |= mask;
 }
 
 /*!
-* @brief Disable the interrupt signals. Interrupt signal will be set when corresponding event happens.
-*        Specific events point to "_tsc_interrupt_signal_mask".
-*        Specific interrupt signal point to "_tsc_interrupt_status_flag_mask";
-*
-* @param base TSC peripheral base address.
-* @param mask Interrupt signals mask. See "_tsc_interrupt_signal_mask".
-*/
+ * @brief Disable the interrupt signals. Interrupt signal will be set when corresponding event happens.
+ *        Specific events point to "_tsc_interrupt_signal_mask".
+ *        Specific interrupt signal point to "_tsc_interrupt_status_flag_mask";
+ *
+ * @param base TSC peripheral base address.
+ * @param mask Interrupt signals mask. See "_tsc_interrupt_signal_mask".
+ */
 static inline void TSC_DisableInterruptSignals(TSC_Type *base, uint32_t mask)
 {
     base->INT_SIG_EN &= ~mask;
 }
 
 /*!
-* @brief Enable the interrupts. Notice: Only interrupts and signals are all enabled, interrupts
-*        could work normally.
-*
-* @param base TSC peripheral base address.
-* @param mask Interrupts mask. See "_tsc_interrupt_mask".
-*/
+ * @brief Enable the interrupts. Notice: Only interrupts and signals are all enabled, interrupts
+ *        could work normally.
+ *
+ * @param base TSC peripheral base address.
+ * @param mask Interrupts mask. See "_tsc_interrupt_mask".
+ */
 static inline void TSC_EnableInterrupts(TSC_Type *base, uint32_t mask)
 {
     base->INT_EN |= mask;
 }
 
 /*!
-* @brief Disable the interrupts.
-*
-* @param base TSC peripheral base address.
-* @param mask Interrupts mask. See "_tsc_interrupt_mask".
-*/
+ * @brief Disable the interrupts.
+ *
+ * @param base TSC peripheral base address.
+ * @param mask Interrupts mask. See "_tsc_interrupt_mask".
+ */
 static inline void TSC_DisableInterrupts(TSC_Type *base, uint32_t mask)
 {
     base->INT_EN &= ~mask;
 }
 
 /*!
-* @brief Get interrupt status flags. Interrupt status falgs are valid when corresponding
-*        interrupt signals are enabled.
-*
-* @param base TSC peripheral base address.
-* @return Status flags asserted mask. See "_tsc_interrupt_status_flag_mask".
-*/
+ * @brief Get interrupt status flags. Interrupt status falgs are valid when corresponding
+ *        interrupt signals are enabled.
+ *
+ * @param base TSC peripheral base address.
+ * @return Status flags asserted mask. See "_tsc_interrupt_status_flag_mask".
+ */
 static inline uint32_t TSC_GetInterruptStatusFlags(TSC_Type *base)
 {
     return base->INT_STATUS;
 }
 
 /*!
-* @brief Clear interrupt status flags. Interrupt status falgs are valid when corresponding
-*        interrupt signals are enabled.
-*
-* @param base TSC peripheral base address.
-* @param mask Status flags mask. See "_tsc_interrupt_status_flag_mask".
-*/
+ * @brief Clear interrupt status flags. Interrupt status falgs are valid when corresponding
+ *        interrupt signals are enabled.
+ *
+ * @param base TSC peripheral base address.
+ * @param mask Status flags mask. See "_tsc_interrupt_status_flag_mask".
+ */
 static inline void TSC_ClearInterruptStatusFlags(TSC_Type *base, uint32_t mask)
 {
     base->INT_STATUS = mask;
 }
 
 /*!
-* @brief Get the status flags of ADC working with TSC.
-*
-* @param base TSC peripheral base address.
-* @return Status flags asserted mask. See "_tsc_adc_status_flag_mask".
-*/
+ * @brief Get the status flags of ADC working with TSC.
+ *
+ * @param base TSC peripheral base address.
+ * @return Status flags asserted mask. See "_tsc_adc_status_flag_mask".
+ */
 static inline uint32_t TSC_GetADCStatusFlags(TSC_Type *base)
 {
     return base->DEBUG_MODE;
 }
 
 /*!
-* @brief Get the status flags of TSC.
-*
-* @param base TSC peripheral base address.
-* @return Status flags asserted mask. See "_tsc_status_flag_mask".
-*/
+ * @brief Get the status flags of TSC.
+ *
+ * @param base TSC peripheral base address.
+ * @return Status flags asserted mask. See "_tsc_status_flag_mask".
+ */
 static inline uint32_t TSC_GetStatusFlags(TSC_Type *base)
 {
     return base->DEBUG_MODE2;
@@ -458,14 +427,14 @@ static inline uint32_t TSC_GetStatusFlags(TSC_Type *base)
  ******************************************************************************/
 
 /*!
-* @brief Enable/Disable debug mode. Once work in debug mode, then all
-* TSC outputs will be controlled by software. Software can also observe all TSC inputs
-* through debug interface. Furthermore, the debug registers also provides current state
-* machine states. Software can always check the current hardware state.
-*
-* @param base TSC peripheral base address.
-* @param enable Switcher of the debug mode. "true" means debug mode,"false" means non-debug mode.
-*/
+ * @brief Enable/Disable debug mode. Once work in debug mode, then all
+ * TSC outputs will be controlled by software. Software can also observe all TSC inputs
+ * through debug interface. Furthermore, the debug registers also provides current state
+ * machine states. Software can always check the current hardware state.
+ *
+ * @param base TSC peripheral base address.
+ * @param enable Switcher of the debug mode. "true" means debug mode,"false" means non-debug mode.
+ */
 static inline void TSC_EnableDebugMode(TSC_Type *base, bool enable)
 {
     if (enable)
@@ -479,24 +448,24 @@ static inline void TSC_EnableDebugMode(TSC_Type *base, bool enable)
 }
 
 /*!
-* @brief Send hardware trigger signal to ADC in debug mode. The trigger signal must last at least 1 ips clock period.
-*
-* @param base TSC peripheral base address.
-* @param hwts Hardware trigger select signal, select which channel to start conversion. See "tsc_trigger_signal_t".
-*             On ADC side, HWTS = 1 << x indicates the x logic channel is selected to start hardware ADC conversion.
-* @param enable Switcher of the trigger signal. "true" means generate trigger signal, "false" means don't generate
-*               trigger signal.
-*/
+ * @brief Send hardware trigger signal to ADC in debug mode. The trigger signal must last at least 1 ips clock period.
+ *
+ * @param base TSC peripheral base address.
+ * @param hwts Hardware trigger select signal, select which channel to start conversion. See "tsc_trigger_signal_t".
+ *             On ADC side, HWTS = 1 << x indicates the x logic channel is selected to start hardware ADC conversion.
+ * @param enable Switcher of the trigger signal. "true" means generate trigger signal, "false" means don't generate
+ *               trigger signal.
+ */
 void TSC_DebugTriggerSignalToADC(TSC_Type *base, tsc_trigger_signal_t hwts, bool enable);
 
 /*!
-* @brief Enable/Disable hardware generates an ADC COCO clear signal in debug mode.
-*
-* @param base TSC peripheral base address.
-* @param enable Switcher of the function of hardware generating an ADC COCO clear signal.
-*        "true" means prevent TSC from generate ADC COCO clear signal.
-*        "false" means allow TSC hardware generates ADC COCO clear.
-*/
+ * @brief Enable/Disable hardware generates an ADC COCO clear signal in debug mode.
+ *
+ * @param base TSC peripheral base address.
+ * @param enable Switcher of the function of hardware generating an ADC COCO clear signal.
+ *        "true" means prevent TSC from generate ADC COCO clear signal.
+ *        "false" means allow TSC hardware generates ADC COCO clear.
+ */
 static inline void TSC_DebugDisableHWClear(TSC_Type *base, bool enable)
 {
     if (enable)
@@ -510,12 +479,12 @@ static inline void TSC_DebugDisableHWClear(TSC_Type *base, bool enable)
 }
 
 /*!
-* @brief Send clear ADC COCO signal to ADC in debug mode. The signal must hold a while.
-*
-* @param base TSC peripheral base address.
-* @param enable Switcher of the clear signal."true" means generate clear signal, "false" means don't generate
-*               clear signal.
-*/
+ * @brief Send clear ADC COCO signal to ADC in debug mode. The signal must hold a while.
+ *
+ * @param base TSC peripheral base address.
+ * @param enable Switcher of the clear signal."true" means generate clear signal, "false" means don't generate
+ *               clear signal.
+ */
 static inline void TSC_DebugClearSignalToADC(TSC_Type *base, bool enable)
 {
     if (enable)
@@ -529,20 +498,25 @@ static inline void TSC_DebugClearSignalToADC(TSC_Type *base, bool enable)
 }
 
 /*!
-* @brief Enable/Disable detection in debug mode.
-*
-* @param base TSC peripheral base address.
-* @param detectionMode Set detect mode. See "tsc_detection_mode_t"
-* @param enable Switcher of detect enable. "true" means enable detection, "false" means disable detection.
-*/
+ * @brief Enable/Disable detection in debug mode.
+ *
+ * @param base TSC peripheral base address.
+ * @param detectionMode Set detect mode. See "tsc_detection_mode_t"
+ * @param enable Switcher of detect enable. "true" means enable detection, "false" means disable detection.
+ */
 void TSC_DebugEnableDetection(TSC_Type *base, tsc_detection_mode_t detectionMode, bool enable);
 
 /*!
-* @brief Set TSC port mode in debug mode.(pull down, pull up and 200k-pull up)
-*
-* @param base TSC peripheral base address.
-* @param port TSC controller ports.
-* @param mode TSC port mode.(pull down, pull up and 200k-pull up)
-*/
+ * @brief Set TSC port mode in debug mode.(pull down, pull up and 200k-pull up)
+ *
+ * @param base TSC peripheral base address.
+ * @param port TSC controller ports.
+ * @param mode TSC port mode.(pull down, pull up and 200k-pull up)
+ */
 void TSC_DebugSetPortMode(TSC_Type *base, tsc_port_source_t port, tsc_port_mode_t mode);
+
+#if defined(__cplusplus)
+}
+#endif
+
 #endif /* _FSL_TSC_H_ */
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_usdhc.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_usdhc.c
index d5145ff5cfd..7a3015d584b 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_usdhc.c
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_usdhc.c
@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2016, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
  * All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include "fsl_usdhc.h"
@@ -52,6 +26,8 @@
 #define USDHC_MAX_CLKFS ((USDHC_SYS_CTRL_SDCLKFS_MASK >> USDHC_SYS_CTRL_SDCLKFS_SHIFT) + 1U)
 #define USDHC_PREV_DVS(x) ((x) -= 1U)
 #define USDHC_PREV_CLKFS(x, y) ((x) >>= (y))
+/*! @brief USDHC ADMA table address align size */
+#define USDHC_ADMA_TABLE_ADDRESS_ALIGN (4U)
 
 /* Typedef for interrupt handler. */
 typedef void (*usdhc_isr_t)(USDHC_Type *base, usdhc_handle_t *handle);
@@ -82,8 +58,12 @@ static void USDHC_SetTransferInterrupt(USDHC_Type *base, bool usingInterruptSign
  * @param base USDHC peripheral base address.
  * @param data Data to be transferred.
  * @param flag data present flag
+ * @param enDMA DMA enable flag
  */
-static status_t USDHC_SetDataTransferConfig(USDHC_Type *base, usdhc_data_t *data, uint32_t *dataPresentFlag);
+static status_t USDHC_SetDataTransferConfig(USDHC_Type *base,
+                                            usdhc_data_t *data,
+                                            uint32_t *dataPresentFlag,
+                                            bool enDMA);
 
 /*!
  * @brief Receive command response
@@ -189,21 +169,21 @@ static void USDHC_TransferHandleSdioInterrupt(USDHC_Type *base, usdhc_handle_t *
 static void USDHC_TransferHandleBlockGap(USDHC_Type *base, usdhc_handle_t *handle);
 
 /*!
-* @brief Handle retuning
-*
-* @param base USDHC peripheral base address.
-* @param handle USDHC handle.
-* @param interrupt flags
-*/
+ * @brief Handle retuning
+ *
+ * @param base USDHC peripheral base address.
+ * @param handle USDHC handle.
+ * @param interrupt flags
+ */
 static void USDHC_TransferHandleReTuning(USDHC_Type *base, usdhc_handle_t *handle, uint32_t interruptFlags);
 
 /*!
-* @brief wait command done
-*
-* @param base USDHC peripheral base address.
-* @param command configuration
-* @param pollingCmdDone polling command done flag
-*/
+ * @brief wait command done
+ *
+ * @param base USDHC peripheral base address.
+ * @param command configuration
+ * @param pollingCmdDone polling command done flag
+ */
 static status_t USDHC_WaitCommandDone(USDHC_Type *base, usdhc_command_t *command, bool pollingCmdDone);
 
 /*******************************************************************************
@@ -263,7 +243,7 @@ static void USDHC_SetTransferInterrupt(USDHC_Type *base, bool usingInterruptSign
     }
 }
 
-static status_t USDHC_SetDataTransferConfig(USDHC_Type *base, usdhc_data_t *data, uint32_t *dataPresentFlag)
+static status_t USDHC_SetDataTransferConfig(USDHC_Type *base, usdhc_data_t *data, uint32_t *dataPresentFlag, bool enDMA)
 {
     uint32_t mixCtrl = base->MIX_CTRL;
 
@@ -337,12 +317,23 @@ static status_t USDHC_SetDataTransferConfig(USDHC_Type *base, usdhc_data_t *data
 
         /* data present flag */
         *dataPresentFlag |= kUSDHC_DataPresentFlag;
+        /* Disable useless interrupt */
+        if (enDMA)
+        {
+            base->INT_SIGNAL_EN &= ~(kUSDHC_BufferWriteReadyFlag | kUSDHC_BufferReadReadyFlag | kUSDHC_DmaCompleteFlag);
+            base->INT_STATUS_EN &= ~(kUSDHC_BufferWriteReadyFlag | kUSDHC_BufferReadReadyFlag | kUSDHC_DmaCompleteFlag);
+        }
+        else
+        {
+            base->INT_SIGNAL_EN |= kUSDHC_BufferWriteReadyFlag | kUSDHC_BufferReadReadyFlag;
+            base->INT_STATUS_EN |= kUSDHC_BufferWriteReadyFlag | kUSDHC_BufferReadReadyFlag;
+        }
     }
     else
     {
         /* clear data flags */
         mixCtrl &= ~(USDHC_MIX_CTRL_MSBSEL_MASK | USDHC_MIX_CTRL_BCEN_MASK | USDHC_MIX_CTRL_DTDSEL_MASK |
-                     USDHC_MIX_CTRL_AC12EN_MASK);
+                     USDHC_MIX_CTRL_AC12EN_MASK | USDHC_MIX_CTRL_AC23EN_MASK);
 
         if (base->PRES_STATE & kUSDHC_CommandInhibitFlag)
         {
@@ -358,30 +349,22 @@ static status_t USDHC_SetDataTransferConfig(USDHC_Type *base, usdhc_data_t *data
 
 static status_t USDHC_ReceiveCommandResponse(USDHC_Type *base, usdhc_command_t *command)
 {
-    uint32_t i;
+    assert(command != NULL);
 
     if (command->responseType != kCARD_ResponseTypeNone)
     {
         command->response[0U] = base->CMD_RSP0;
         if (command->responseType == kCARD_ResponseTypeR2)
         {
-            command->response[1U] = base->CMD_RSP1;
-            command->response[2U] = base->CMD_RSP2;
-            command->response[3U] = base->CMD_RSP3;
-
-            i = 4U;
             /* R3-R2-R1-R0(lowest 8 bit is invalid bit) has the same format as R2 format in SD specification document
             after removed internal CRC7 and end bit. */
-            do
-            {
-                command->response[i - 1U] <<= 8U;
-                if (i > 1U)
-                {
-                    command->response[i - 1U] |= ((command->response[i - 2U] & 0xFF000000U) >> 24U);
-                }
-            } while (i--);
+            command->response[0U] <<= 8U;
+            command->response[1U] = (base->CMD_RSP1 << 8U) | ((base->CMD_RSP0 & 0xFF000000U) >> 24U);
+            command->response[2U] = (base->CMD_RSP2 << 8U) | ((base->CMD_RSP1 & 0xFF000000U) >> 24U);
+            command->response[3U] = (base->CMD_RSP3 << 8U) | ((base->CMD_RSP2 & 0xFF000000U) >> 24U);
         }
     }
+
     /* check response error flag */
     if ((command->responseErrorFlags != 0U) &&
         ((command->responseType == kCARD_ResponseTypeR1) || (command->responseType == kCARD_ResponseTypeR1b) ||
@@ -407,10 +390,10 @@ static uint32_t USDHC_ReadDataPort(USDHC_Type *base, usdhc_data_t *data, uint32_
     if ((base->MIX_CTRL & USDHC_MIX_CTRL_DMAEN_MASK) == 0U)
     {
         /*
-       * Add non aligned access support ,user need make sure your buffer size is big
-       * enough to hold the data,in other words,user need make sure the buffer size
-       * is 4 byte aligned
-       */
+         * Add non aligned access support ,user need make sure your buffer size is big
+         * enough to hold the data,in other words,user need make sure the buffer size
+         * is 4 byte aligned
+         */
         if (data->blockSize % sizeof(uint32_t) != 0U)
         {
             data->blockSize +=
@@ -456,10 +439,10 @@ static status_t USDHC_ReadByDataPortBlocking(USDHC_Type *base, usdhc_data_t *dat
     status_t error = kStatus_Success;
 
     /*
-       * Add non aligned access support ,user need make sure your buffer size is big
-       * enough to hold the data,in other words,user need make sure the buffer size
-       * is 4 byte aligned
-       */
+     * Add non aligned access support ,user need make sure your buffer size is big
+     * enough to hold the data,in other words,user need make sure the buffer size
+     * is 4 byte aligned
+     */
     if (data->blockSize % sizeof(uint32_t) != 0U)
     {
         data->blockSize +=
@@ -527,10 +510,10 @@ static uint32_t USDHC_WriteDataPort(USDHC_Type *base, usdhc_data_t *data, uint32
     if ((base->MIX_CTRL & USDHC_MIX_CTRL_DMAEN_MASK) == 0U)
     {
         /*
-           * Add non aligned access support ,user need make sure your buffer size is big
-           * enough to hold the data,in other words,user need make sure the buffer size
-           * is 4 byte aligned
-           */
+         * Add non aligned access support ,user need make sure your buffer size is big
+         * enough to hold the data,in other words,user need make sure the buffer size
+         * is 4 byte aligned
+         */
         if (data->blockSize % sizeof(uint32_t) != 0U)
         {
             data->blockSize +=
@@ -576,10 +559,10 @@ static status_t USDHC_WriteByDataPortBlocking(USDHC_Type *base, usdhc_data_t *da
     status_t error = kStatus_Success;
 
     /*
-       * Add non aligned access support ,user need make sure your buffer size is big
-       * enough to hold the data,in other words,user need make sure the buffer size
-       * is 4 byte aligned
-       */
+     * Add non aligned access support ,user need make sure your buffer size is big
+     * enough to hold the data,in other words,user need make sure the buffer size
+     * is 4 byte aligned
+     */
     if (data->blockSize % sizeof(uint32_t) != 0U)
     {
         data->blockSize +=
@@ -641,6 +624,12 @@ static status_t USDHC_WriteByDataPortBlocking(USDHC_Type *base, usdhc_data_t *da
     return error;
 }
 
+/*!
+ * brief send command function
+ *
+ * param base USDHC peripheral base address.
+ * param command configuration
+ */
 void USDHC_SendCommand(USDHC_Type *base, usdhc_command_t *command)
 {
     assert(NULL != command);
@@ -694,7 +683,7 @@ void USDHC_SendCommand(USDHC_Type *base, usdhc_command_t *command)
                          USDHC_CMD_XFR_TYP_RSPTYP_MASK | USDHC_CMD_XFR_TYP_DPSEL_MASK)));
 
         /* config the command xfertype and argument */
-        base->CMD_ARG = command->argument;
+        base->CMD_ARG     = command->argument;
         base->CMD_XFR_TYP = xferType;
     }
 
@@ -709,7 +698,7 @@ static status_t USDHC_WaitCommandDone(USDHC_Type *base, usdhc_command_t *command
 {
     assert(NULL != command);
 
-    status_t error = kStatus_Success;
+    status_t error           = kStatus_Success;
     uint32_t interruptStatus = 0U;
     /* check if need polling command done or not */
     if (pollingCmdDone)
@@ -746,7 +735,7 @@ static status_t USDHC_WaitCommandDone(USDHC_Type *base, usdhc_command_t *command
 
 static status_t USDHC_TransferDataBlocking(USDHC_Type *base, usdhc_data_t *data, bool enDMA)
 {
-    status_t error = kStatus_Success;
+    status_t error           = kStatus_Success;
     uint32_t interruptStatus = 0U;
 
     if (enDMA)
@@ -796,6 +785,26 @@ static status_t USDHC_TransferDataBlocking(USDHC_Type *base, usdhc_data_t *data,
     return error;
 }
 
+/*!
+ * brief USDHC module initialization function.
+ *
+ * Configures the USDHC according to the user configuration.
+ *
+ * Example:
+   code
+   usdhc_config_t config;
+   config.cardDetectDat3 = false;
+   config.endianMode = kUSDHC_EndianModeLittle;
+   config.dmaMode = kUSDHC_DmaModeAdma2;
+   config.readWatermarkLevel = 128U;
+   config.writeWatermarkLevel = 128U;
+   USDHC_Init(USDHC, &config);
+   endcode
+ *
+ * param base USDHC peripheral base address.
+ * param config USDHC configuration information.
+ * retval kStatus_Success Operate successfully.
+ */
 void USDHC_Init(USDHC_Type *base, const usdhc_config_t *config)
 {
     assert(config);
@@ -805,14 +814,16 @@ void USDHC_Init(USDHC_Type *base, const usdhc_config_t *config)
 
     uint32_t proctl, sysctl, wml;
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* Enable USDHC clock. */
     CLOCK_EnableClock(s_usdhcClock[USDHC_GetInstance(base)]);
+#endif
 
     /* Reset USDHC. */
     USDHC_Reset(base, kUSDHC_ResetAll, 100U);
 
     proctl = base->PROT_CTRL;
-    wml = base->WTMK_LVL;
+    wml    = base->WTMK_LVL;
     sysctl = base->SYS_CTRL;
 
     proctl &= ~(USDHC_PROT_CTRL_EMODE_MASK | USDHC_PROT_CTRL_DMASEL_MASK);
@@ -829,8 +840,8 @@ void USDHC_Init(USDHC_Type *base, const usdhc_config_t *config)
     sysctl &= ~USDHC_SYS_CTRL_DTOCV_MASK;
     sysctl |= USDHC_SYS_CTRL_DTOCV(config->dataTimeout);
 
-    base->SYS_CTRL = sysctl;
-    base->WTMK_LVL = wml;
+    base->SYS_CTRL  = sysctl;
+    base->WTMK_LVL  = wml;
     base->PROT_CTRL = proctl;
 
 #if FSL_FEATURE_USDHC_HAS_EXT_DMA
@@ -843,12 +854,28 @@ void USDHC_Init(USDHC_Type *base, const usdhc_config_t *config)
     USDHC_SetTransferInterrupt(base, false);
 }
 
+/*!
+ * brief Deinitializes the USDHC.
+ *
+ * param base USDHC peripheral base address.
+ */
 void USDHC_Deinit(USDHC_Type *base)
 {
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* Disable clock. */
     CLOCK_DisableClock(s_usdhcClock[USDHC_GetInstance(base)]);
+#endif
 }
 
+/*!
+ * brief Resets the USDHC.
+ *
+ * param base USDHC peripheral base address.
+ * param mask The reset type mask(_usdhc_reset).
+ * param timeout Timeout for reset.
+ * retval true Reset successfully.
+ * retval false Reset failed.
+ */
 bool USDHC_Reset(USDHC_Type *base, uint32_t mask, uint32_t timeout)
 {
     base->SYS_CTRL |= (mask & (USDHC_SYS_CTRL_RSTA_MASK | USDHC_SYS_CTRL_RSTC_MASK | USDHC_SYS_CTRL_RSTD_MASK));
@@ -865,6 +892,12 @@ bool USDHC_Reset(USDHC_Type *base, uint32_t mask, uint32_t timeout)
     return ((!timeout) ? false : true);
 }
 
+/*!
+ * brief Gets the capability information.
+ *
+ * param base USDHC peripheral base address.
+ * param capability Structure to save capability information.
+ */
 void USDHC_GetCapability(USDHC_Type *base, usdhc_capability_t *capability)
 {
     assert(capability);
@@ -875,7 +908,7 @@ void USDHC_GetCapability(USDHC_Type *base, usdhc_capability_t *capability)
     htCapability = base->HOST_CTRL_CAP;
 
     /* Get the capability of USDHC. */
-    maxBlockLength = ((htCapability & USDHC_HOST_CTRL_CAP_MBL_MASK) >> USDHC_HOST_CTRL_CAP_MBL_SHIFT);
+    maxBlockLength             = ((htCapability & USDHC_HOST_CTRL_CAP_MBL_MASK) >> USDHC_HOST_CTRL_CAP_MBL_SHIFT);
     capability->maxBlockLength = (512U << maxBlockLength);
     /* Other attributes not in HTCAPBLT register. */
     capability->maxBlockCount = USDHC_MAX_BLOCK_COUNT;
@@ -889,15 +922,24 @@ void USDHC_GetCapability(USDHC_Type *base, usdhc_capability_t *capability)
     capability->flags |= (kUSDHC_Support4BitFlag | kUSDHC_Support8BitFlag);
 }
 
+/*!
+ * brief Sets the SD bus clock frequency.
+ *
+ * param base USDHC peripheral base address.
+ * param srcClock_Hz USDHC source clock frequency united in Hz.
+ * param busClock_Hz SD bus clock frequency united in Hz.
+ *
+ * return The nearest frequency of busClock_Hz configured to SD bus.
+ */
 uint32_t USDHC_SetSdClock(USDHC_Type *base, uint32_t srcClock_Hz, uint32_t busClock_Hz)
 {
     assert(srcClock_Hz != 0U);
     assert((busClock_Hz != 0U) && (busClock_Hz <= srcClock_Hz));
 
-    uint32_t totalDiv = 0U;
-    uint32_t divisor = 0U;
-    uint32_t prescaler = 0U;
-    uint32_t sysctl = 0U;
+    uint32_t totalDiv         = 0U;
+    uint32_t divisor          = 0U;
+    uint32_t prescaler        = 0U;
+    uint32_t sysctl           = 0U;
     uint32_t nearestFrequency = 0U;
 
     /* calucate total divisor first */
@@ -929,34 +971,40 @@ uint32_t USDHC_SetSdClock(USDHC_Type *base, uint32_t srcClock_Hz, uint32_t busCl
             while ((divisor * prescaler) < totalDiv)
             {
                 divisor++;
+                if (divisor > USDHC_MAX_DVS)
+                {
+                    if ((prescaler <<= 1U) > USDHC_MAX_CLKFS)
+                    {
+                        return 0;
+                    }
+                    divisor = totalDiv / prescaler;
+                }
             }
-
-            nearestFrequency = srcClock_Hz / (divisor == 0U ? 1U : divisor) / prescaler;
         }
         else
         {
             /* in this situation , divsior and SDCLKFS can generate same clock
             use SDCLKFS*/
-            if ((USDHC_MAX_DVS % totalDiv) == 0U)
+            if (((totalDiv % 2U) != 0U) & (totalDiv != 1U))
             {
-                divisor = 0U;
-                prescaler = totalDiv;
+                divisor   = totalDiv;
+                prescaler = 1U;
             }
             else
             {
-                divisor = (totalDiv / 2U) + 1U; /* make sure the output frequency not bigger than target value */
-                prescaler = 2U;
+                divisor   = 1U;
+                prescaler = totalDiv;
             }
-            nearestFrequency = srcClock_Hz / totalDiv;
         }
+        nearestFrequency = srcClock_Hz / (divisor == 0U ? 1U : divisor) / prescaler;
     }
     /* in this condition , srcClock_Hz = busClock_Hz, */
     else
     {
         /* in DDR mode , set SDCLKFS to 0, divisor = 0, actually the
         totoal divider = 2U */
-        divisor = 0U;
-        prescaler = 0U;
+        divisor          = 0U;
+        prescaler        = 0U;
         nearestFrequency = srcClock_Hz;
     }
 
@@ -985,6 +1033,17 @@ uint32_t USDHC_SetSdClock(USDHC_Type *base, uint32_t srcClock_Hz, uint32_t busCl
     return nearestFrequency;
 }
 
+/*!
+ * brief Sends 80 clocks to the card to set it to the active state.
+ *
+ * This function must be called each time the card is inserted to ensure that the card can receive the command
+ * correctly.
+ *
+ * param base USDHC peripheral base address.
+ * param timeout Timeout to initialize card.
+ * retval true Set card active successfully.
+ * retval false Set card active failed.
+ */
 bool USDHC_SetCardActive(USDHC_Type *base, uint32_t timeout)
 {
     base->SYS_CTRL |= USDHC_SYS_CTRL_INITA_MASK;
@@ -1001,6 +1060,13 @@ bool USDHC_SetCardActive(USDHC_Type *base, uint32_t timeout)
     return ((!timeout) ? false : true);
 }
 
+/*!
+ * brief the enable/disable DDR mode
+ *
+ * param base USDHC peripheral base address.
+ * param enable/disable flag
+ * param nibble position
+ */
 void USDHC_EnableDDRMode(USDHC_Type *base, bool enable, uint32_t nibblePos)
 {
     uint32_t prescaler = (base->SYS_CTRL & USDHC_SYS_CTRL_SDCLKFS_MASK) >> USDHC_SYS_CTRL_SDCLKFS_SHIFT;
@@ -1028,6 +1094,24 @@ void USDHC_EnableDDRMode(USDHC_Type *base, bool enable, uint32_t nibblePos)
     base->SYS_CTRL = (base->SYS_CTRL & (~USDHC_SYS_CTRL_SDCLKFS_MASK)) | USDHC_SYS_CTRL_SDCLKFS(prescaler);
 }
 
+/*!
+ * brief Configures the MMC boot feature.
+ *
+ * Example:
+   code
+   usdhc_boot_config_t config;
+   config.ackTimeoutCount = 4;
+   config.bootMode = kUSDHC_BootModeNormal;
+   config.blockCount = 5;
+   config.enableBootAck = true;
+   config.enableBoot = true;
+   config.enableAutoStopAtBlockGap = true;
+   USDHC_SetMmcBootConfig(USDHC, &config);
+   endcode
+ *
+ * param base USDHC peripheral base address.
+ * param config The MMC boot configuration information.
+ */
 void USDHC_SetMmcBootConfig(USDHC_Type *base, const usdhc_boot_config_t *config)
 {
     assert(config);
@@ -1060,6 +1144,18 @@ void USDHC_SetMmcBootConfig(USDHC_Type *base, const usdhc_boot_config_t *config)
     base->MMC_BOOT = mmcboot;
 }
 
+/*!
+ * brief Sets the ADMA1 descriptor table configuration.
+ *
+ * param admaTable Adma table address.
+ * param admaTableWords Adma table length.
+ * param dataBufferAddr Data buffer address.
+ * param dataBytes Data length.
+ * param flags ADAM descriptor flag, used to indicate to create multiple or single descriptor, please
+ *  reference _usdhc_adma_flag.
+ * retval kStatus_OutOfRange ADMA descriptor table length isn't enough to describe data.
+ * retval kStatus_Success Operate successfully.
+ */
 status_t USDHC_SetADMA1Descriptor(
     uint32_t *admaTable, uint32_t admaTableWords, const uint32_t *dataBufferAddr, uint32_t dataBytes, uint32_t flags)
 {
@@ -1082,10 +1178,10 @@ status_t USDHC_SetADMA1Descriptor(
         return kStatus_USDHC_NotSupport;
     }
     /*
-    * Add non aligned access support ,user need make sure your buffer size is big
-    * enough to hold the data,in other words,user need make sure the buffer size
-    * is 4 byte aligned
-    */
+     * Add non aligned access support ,user need make sure your buffer size is big
+     * enough to hold the data,in other words,user need make sure the buffer size
+     * is 4 byte aligned
+     */
     if (dataBytes % sizeof(uint32_t) != 0U)
     {
         /* make the data length as word-aligned */
@@ -1134,6 +1230,18 @@ status_t USDHC_SetADMA1Descriptor(
     return kStatus_Success;
 }
 
+/*!
+ * brief Sets the ADMA2 descriptor table configuration.
+ *
+ * param admaTable Adma table address.
+ * param admaTableWords Adma table length.
+ * param dataBufferAddr Data buffer address.
+ * param dataBytes Data Data length.
+ * param flags ADAM descriptor flag, used to indicate to create multiple or single descriptor, please
+ *  reference _usdhc_adma_flag.
+ * retval kStatus_OutOfRange ADMA descriptor table length isn't enough to describe data.
+ * retval kStatus_Success Operate successfully.
+ */
 status_t USDHC_SetADMA2Descriptor(
     uint32_t *admaTable, uint32_t admaTableWords, const uint32_t *dataBufferAddr, uint32_t dataBytes, uint32_t flags)
 {
@@ -1151,10 +1259,10 @@ status_t USDHC_SetADMA2Descriptor(
         return kStatus_USDHC_DMADataAddrNotAlign;
     }
     /*
-    * Add non aligned access support ,user need make sure your buffer size is big
-    * enough to hold the data,in other words,user need make sure the buffer size
-    * is 4 byte aligned
-    */
+     * Add non aligned access support ,user need make sure your buffer size is big
+     * enough to hold the data,in other words,user need make sure the buffer size
+     * is 4 byte aligned
+     */
     if (dataBytes % sizeof(uint32_t) != 0U)
     {
         /* make the data length as word-aligned */
@@ -1204,7 +1312,7 @@ status_t USDHC_SetADMA2Descriptor(
         }
 
         /* Each descriptor for ADMA2 is 64-bit in length */
-        adma2EntryAddress[i].address = (dataBytes == 0U) ? &s_usdhcBootDummy : data;
+        adma2EntryAddress[i].address   = (dataBytes == 0U) ? &s_usdhcBootDummy : data;
         adma2EntryAddress[i].attribute = (dmaBufferLen << USDHC_ADMA2_DESCRIPTOR_LENGTH_SHIFT);
         adma2EntryAddress[i].attribute |=
             (dataBytes == 0U) ? 0U : (kUSDHC_Adma2DescriptorTypeTransfer | kUSDHC_Adma2DescriptorInterruptFlag);
@@ -1232,6 +1340,17 @@ status_t USDHC_SetADMA2Descriptor(
     return kStatus_Success;
 }
 
+/*!
+ * brief Internal DMA configuration.
+ * This function is used to config the USDHC DMA related registers.
+ * param base USDHC peripheral base address.
+ * param adma configuration
+ * param dataAddr transfer data address, a simple DMA parameter, if ADMA is used, leave it to NULL.
+ * param enAutoCmd23 flag to indicate Auto CMD23 is enable or not, a simple DMA parameter,if ADMA is used, leave it to
+ * false.
+ * retval kStatus_OutOfRange ADMA descriptor table length isn't enough to describe data.
+ * retval kStatus_Success Operate successfully.
+ */
 status_t USDHC_SetInternalDmaConfig(USDHC_Type *base,
                                     usdhc_adma_config_t *dmaConfig,
                                     const uint32_t *dataAddr,
@@ -1239,6 +1358,8 @@ status_t USDHC_SetInternalDmaConfig(USDHC_Type *base,
 {
     assert(dmaConfig);
     assert(dataAddr);
+    assert((NULL != dmaConfig->admaTable) &&
+           (((USDHC_ADMA_TABLE_ADDRESS_ALIGN - 1U) & (uint32_t)dmaConfig->admaTable) == 0U));
 
 #if FSL_FEATURE_USDHC_HAS_EXT_DMA
     /* disable the external DMA if support */
@@ -1266,7 +1387,7 @@ status_t USDHC_SetInternalDmaConfig(USDHC_Type *base,
     else
     {
         /* When use ADMA, disable simple DMA */
-        base->DS_ADDR = 0U;
+        base->DS_ADDR       = 0U;
         base->ADMA_SYS_ADDR = (uint32_t)(dmaConfig->admaTable);
     }
 
@@ -1279,16 +1400,28 @@ status_t USDHC_SetInternalDmaConfig(USDHC_Type *base,
     return kStatus_Success;
 }
 
+/*!
+ * brief Sets the DMA descriptor table configuration.
+ * A high level DMA descriptor configuration function.
+ * param base USDHC peripheral base address.
+ * param adma configuration
+ * param data Data descriptor
+ * param flags ADAM descriptor flag, used to indicate to create multiple or single descriptor, please
+ *  reference _usdhc_adma_flag
+ * retval kStatus_OutOfRange ADMA descriptor table length isn't enough to describe data.
+ * retval kStatus_Success Operate successfully.
+ */
 status_t USDHC_SetAdmaTableConfig(USDHC_Type *base,
                                   usdhc_adma_config_t *dmaConfig,
                                   usdhc_data_t *dataConfig,
                                   uint32_t flags)
 {
     assert(NULL != dmaConfig);
-    assert(NULL != dmaConfig->admaTable);
+    assert((NULL != dmaConfig->admaTable) &&
+           (((USDHC_ADMA_TABLE_ADDRESS_ALIGN - 1U) & (uint32_t)dmaConfig->admaTable) == 0U));
     assert(NULL != dataConfig);
 
-    status_t error = kStatus_Fail;
+    status_t error           = kStatus_Fail;
     uint32_t bootDummyOffset = dataConfig->dataType == kUSDHC_TransferDataBootcontinous ? sizeof(uint32_t) : 0U;
     const uint32_t *data =
         (const uint32_t *)((uint32_t)((dataConfig->rxData == NULL) ? dataConfig->txData : dataConfig->rxData) +
@@ -1329,15 +1462,35 @@ status_t USDHC_SetAdmaTableConfig(USDHC_Type *base,
     return error;
 }
 
+/*!
+ * brief Transfers the command/data using a blocking method.
+ *
+ * This function waits until the command response/data is received or the USDHC encounters an error by polling the
+ * status
+ * flag.
+ * The application must not call this API in multiple threads at the same time. Because of that this API doesn't support
+ * the re-entry mechanism.
+ *
+ * note There is no need to call the API 'USDHC_TransferCreateHandle' when calling this API.
+ *
+ * param base USDHC peripheral base address.
+ * param adma configuration
+ * param transfer Transfer content.
+ * retval kStatus_InvalidArgument Argument is invalid.
+ * retval kStatus_USDHC_PrepareAdmaDescriptorFailed Prepare ADMA descriptor failed.
+ * retval kStatus_USDHC_SendCommandFailed Send command failed.
+ * retval kStatus_USDHC_TransferDataFailed Transfer data failed.
+ * retval kStatus_Success Operate successfully.
+ */
 status_t USDHC_TransferBlocking(USDHC_Type *base, usdhc_adma_config_t *dmaConfig, usdhc_transfer_t *transfer)
 {
     assert(transfer);
 
-    status_t error = kStatus_Fail;
+    status_t error           = kStatus_Fail;
     usdhc_command_t *command = transfer->command;
-    usdhc_data_t *data = transfer->data;
-    bool enDMA = true;
-    bool executeTuning = ((data == NULL) ? false : data->dataType == kUSDHC_TransferDataTuning);
+    usdhc_data_t *data       = transfer->data;
+    bool enDMA               = true;
+    bool executeTuning       = ((data == NULL) ? false : data->dataType == kUSDHC_TransferDataTuning);
 
     /*check re-tuning request*/
     if ((USDHC_GetInterruptStatusFlags(base) & kUSDHC_ReTuningEventFlag) != 0U)
@@ -1349,9 +1502,10 @@ status_t USDHC_TransferBlocking(USDHC_Type *base, usdhc_adma_config_t *dmaConfig
     /* Update ADMA descriptor table according to different DMA mode(no DMA, ADMA1, ADMA2).*/
     if ((data != NULL) && (dmaConfig != NULL) && (!executeTuning))
     {
-        error = USDHC_SetAdmaTableConfig(base, dmaConfig, data, (data->dataType & kUSDHC_TransferDataBoot) ?
-                                                                    kUSDHC_AdmaDescriptorMultipleFlag :
-                                                                    kUSDHC_AdmaDescriptorSingleFlag);
+        error =
+            USDHC_SetAdmaTableConfig(base, dmaConfig, data,
+                                     (data->dataType & kUSDHC_TransferDataBoot) ? kUSDHC_AdmaDescriptorMultipleFlag :
+                                                                                  kUSDHC_AdmaDescriptorSingleFlag);
     }
 
     /* if the DMA desciptor configure fail or not needed , disable it */
@@ -1378,7 +1532,7 @@ status_t USDHC_TransferBlocking(USDHC_Type *base, usdhc_adma_config_t *dmaConfig
 #endif
 
     /* config the data transfer parameter */
-    error = USDHC_SetDataTransferConfig(base, data, &(command->flags));
+    error = USDHC_SetDataTransferConfig(base, data, &(command->flags), enDMA);
     if (kStatus_Success != error)
     {
         return error;
@@ -1397,6 +1551,25 @@ status_t USDHC_TransferBlocking(USDHC_Type *base, usdhc_adma_config_t *dmaConfig
     return error;
 }
 
+/*!
+ * brief Transfers the command/data using an interrupt and an asynchronous method.
+ *
+ * This function sends a command and data and returns immediately. It doesn't wait the transfer complete or encounter an
+ * error.
+ * The application must not call this API in multiple threads at the same time. Because of that this API doesn't support
+ * the re-entry mechanism.
+ *
+ * note Call the API 'USDHC_TransferCreateHandle' when calling this API.
+ *
+ * param base USDHC peripheral base address.
+ * param handle USDHC handle.
+ * param adma configuration.
+ * param transfer Transfer content.
+ * retval kStatus_InvalidArgument Argument is invalid.
+ * retval kStatus_USDHC_BusyTransferring Busy transferring.
+ * retval kStatus_USDHC_PrepareAdmaDescriptorFailed Prepare ADMA descriptor failed.
+ * retval kStatus_Success Operate successfully.
+ */
 status_t USDHC_TransferNonBlocking(USDHC_Type *base,
                                    usdhc_handle_t *handle,
                                    usdhc_adma_config_t *dmaConfig,
@@ -1405,10 +1578,11 @@ status_t USDHC_TransferNonBlocking(USDHC_Type *base,
     assert(handle);
     assert(transfer);
 
-    status_t error = kStatus_Fail;
+    status_t error           = kStatus_Fail;
     usdhc_command_t *command = transfer->command;
-    usdhc_data_t *data = transfer->data;
-    bool executeTuning = ((data == NULL) ? false : data->dataType == kUSDHC_TransferDataTuning);
+    usdhc_data_t *data       = transfer->data;
+    bool executeTuning       = ((data == NULL) ? false : data->dataType == kUSDHC_TransferDataTuning);
+    bool enDMA               = true;
 
     /*check re-tuning request*/
     if ((USDHC_GetInterruptStatusFlags(base) & (kUSDHC_ReTuningEventFlag)) != 0U)
@@ -1418,18 +1592,19 @@ status_t USDHC_TransferNonBlocking(USDHC_Type *base,
     }
 
     /* Save command and data into handle before transferring. */
+
     handle->command = command;
-    handle->data = data;
-    handle->interruptFlags = 0U;
+    handle->data    = data;
     /* transferredWords will only be updated in ISR when transfer way is DATAPORT. */
     handle->transferredWords = 0U;
 
     /* Update ADMA descriptor table according to different DMA mode(no DMA, ADMA1, ADMA2).*/
     if ((data != NULL) && (dmaConfig != NULL) && (!executeTuning))
     {
-        error = USDHC_SetAdmaTableConfig(base, dmaConfig, data, (data->dataType & kUSDHC_TransferDataBoot) ?
-                                                                    kUSDHC_AdmaDescriptorMultipleFlag :
-                                                                    kUSDHC_AdmaDescriptorSingleFlag);
+        error =
+            USDHC_SetAdmaTableConfig(base, dmaConfig, data,
+                                     (data->dataType & kUSDHC_TransferDataBoot) ? kUSDHC_AdmaDescriptorMultipleFlag :
+                                                                                  kUSDHC_AdmaDescriptorSingleFlag);
     }
 
     /* if the DMA desciptor configure fail or not needed , disable it */
@@ -1437,6 +1612,7 @@ status_t USDHC_TransferNonBlocking(USDHC_Type *base,
     {
         /* disable DMA, using polling mode in this situation */
         USDHC_EnableInternalDMA(base, false);
+        enDMA = false;
     }
 #if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL
     else
@@ -1454,7 +1630,7 @@ status_t USDHC_TransferNonBlocking(USDHC_Type *base,
     }
 #endif
 
-    error = USDHC_SetDataTransferConfig(base, data, &(command->flags));
+    error = USDHC_SetDataTransferConfig(base, data, &(command->flags), enDMA);
     if (kStatus_Success != error)
     {
         return error;
@@ -1467,6 +1643,14 @@ status_t USDHC_TransferNonBlocking(USDHC_Type *base,
 }
 
 #if defined(FSL_FEATURE_USDHC_HAS_SDR50_MODE) && (FSL_FEATURE_USDHC_HAS_SDR50_MODE)
+/*!
+ * brief manual tuning trigger or abort
+ * User should handle the tuning cmd and find the boundary of the delay
+ * then calucate a average value which will be config to the CLK_TUNE_CTRL_STATUS
+ * This function should called before USDHC_AdjustDelayforSDR104 function
+ * param base USDHC peripheral base address.
+ * param tuning enable flag
+ */
 void USDHC_EnableManualTuning(USDHC_Type *base, bool enable)
 {
     if (enable)
@@ -1485,6 +1669,14 @@ void USDHC_EnableManualTuning(USDHC_Type *base, bool enable)
     }
 }
 
+/*!
+ * brief the SDR104 mode delay setting adjust
+ * This function should called after USDHC_ManualTuningForSDR104
+ * param base USDHC peripheral base address.
+ * param delay setting configuration
+ * retval kStatus_Fail config the delay setting fail
+ * retval kStatus_Success config the delay setting success
+ */
 status_t USDHC_AdjustDelayForManualTuning(USDHC_Type *base, uint32_t delay)
 {
     uint32_t clkTuneCtrl = 0U;
@@ -1507,6 +1699,16 @@ status_t USDHC_AdjustDelayForManualTuning(USDHC_Type *base, uint32_t delay)
     return kStatus_Success;
 }
 
+/*!
+ * brief the enable standard tuning function
+ * The standard tuning window and tuning counter use the default config
+ * tuning cmd is send by the software, user need to check the tuning result
+ * can be used for SDR50,SDR104,HS200 mode tuning
+ * param base USDHC peripheral base address.
+ * param tuning start tap
+ * param tuning step
+ * param enable/disable flag
+ */
 void USDHC_EnableStandardTuning(USDHC_Type *base, uint32_t tuningStartTap, uint32_t step, bool enable)
 {
     uint32_t tuningCtrl = 0U;
@@ -1536,6 +1738,11 @@ void USDHC_EnableStandardTuning(USDHC_Type *base, uint32_t tuningStartTap, uint3
     }
 }
 
+/*!
+ * brief the auto tuning enbale for CMD/DATA line
+ *
+ * param base USDHC peripheral base address.
+ */
 void USDHC_EnableAutoTuningForCmdAndData(USDHC_Type *base)
 {
     uint32_t busWidth = 0U;
@@ -1585,7 +1792,7 @@ static void USDHC_TransferHandleCommand(USDHC_Type *base, usdhc_handle_t *handle
 {
     assert(handle->command);
 
-    if ((interruptFlags & kUSDHC_CommandErrorFlag) && (!(handle->data)))
+    if (interruptFlags & kUSDHC_CommandErrorFlag)
     {
         if (handle->callback.TransferComplete)
         {
@@ -1689,6 +1896,14 @@ static void USDHC_TransferHandleBlockGap(USDHC_Type *base, usdhc_handle_t *handl
     }
 }
 
+/*!
+ * brief Creates the USDHC handle.
+ *
+ * param base USDHC peripheral base address.
+ * param handle USDHC handle pointer.
+ * param callback Structure pointer to contain all callback functions.
+ * param userData Callback function parameter.
+ */
 void USDHC_TransferCreateHandle(USDHC_Type *base,
                                 usdhc_handle_t *handle,
                                 const usdhc_transfer_callback_t *callback,
@@ -1701,35 +1916,40 @@ void USDHC_TransferCreateHandle(USDHC_Type *base,
     memset(handle, 0, sizeof(*handle));
 
     /* Set the callback. */
-    handle->callback.CardInserted = callback->CardInserted;
-    handle->callback.CardRemoved = callback->CardRemoved;
-    handle->callback.SdioInterrupt = callback->SdioInterrupt;
-    handle->callback.BlockGap = callback->BlockGap;
+    handle->callback.CardInserted     = callback->CardInserted;
+    handle->callback.CardRemoved      = callback->CardRemoved;
+    handle->callback.SdioInterrupt    = callback->SdioInterrupt;
+    handle->callback.BlockGap         = callback->BlockGap;
     handle->callback.TransferComplete = callback->TransferComplete;
-    handle->callback.ReTuning = callback->ReTuning;
-    handle->userData = userData;
+    handle->callback.ReTuning         = callback->ReTuning;
+    handle->userData                  = userData;
 
     /* Save the handle in global variables to support the double weak mechanism. */
     s_usdhcHandle[USDHC_GetInstance(base)] = handle;
 
     /* Enable interrupt in NVIC. */
     USDHC_SetTransferInterrupt(base, true);
-    /* disable the tuning pass interrupt */
-    USDHC_DisableInterruptSignal(base, kUSDHC_TuningPassFlag | kUSDHC_ReTuningEventFlag);
     /* save IRQ handler */
     s_usdhcIsr = USDHC_TransferHandleIRQ;
 
     EnableIRQ(s_usdhcIRQ[USDHC_GetInstance(base)]);
 }
 
+/*!
+ * brief IRQ handler for the USDHC.
+ *
+ * This function deals with the IRQs on the given host controller.
+ *
+ * param base USDHC peripheral base address.
+ * param handle USDHC handle.
+ */
 void USDHC_TransferHandleIRQ(USDHC_Type *base, usdhc_handle_t *handle)
 {
     assert(handle);
 
     uint32_t interruptFlags;
 
-    interruptFlags = USDHC_GetInterruptStatusFlags(base);
-    handle->interruptFlags = interruptFlags;
+    interruptFlags = USDHC_GetEnabledInterruptStatusFlags(base);
 
     if (interruptFlags & kUSDHC_CardDetectFlag)
     {
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_usdhc.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_usdhc.h
index 4139dfd8bd3..acf33a1f0b0 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_usdhc.h
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_usdhc.h
@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2016, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
  * All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 #ifndef _FSL_USDHC_H_
 #define _FSL_USDHC_H_
@@ -47,8 +21,8 @@
 
 /*! @name Driver version */
 /*@{*/
-/*! @brief Driver version 2.2.3. */
-#define FSL_USDHC_DRIVER_VERSION (MAKE_VERSION(2U, 2U, 3U))
+/*! @brief Driver version 2.2.8. */
+#define FSL_USDHC_DRIVER_VERSION (MAKE_VERSION(2U, 2U, 8U))
 /*@}*/
 
 /*! @brief Maximum block count can be set one time */
@@ -57,26 +31,26 @@
 /*! @brief USDHC status */
 enum _usdhc_status
 {
-    kStatus_USDHC_BusyTransferring = MAKE_STATUS(kStatusGroup_USDHC, 0U),            /*!< Transfer is on-going */
+    kStatus_USDHC_BusyTransferring            = MAKE_STATUS(kStatusGroup_USDHC, 0U), /*!< Transfer is on-going */
     kStatus_USDHC_PrepareAdmaDescriptorFailed = MAKE_STATUS(kStatusGroup_USDHC, 1U), /*!< Set DMA descriptor failed */
-    kStatus_USDHC_SendCommandFailed = MAKE_STATUS(kStatusGroup_USDHC, 2U),           /*!< Send command failed */
-    kStatus_USDHC_TransferDataFailed = MAKE_STATUS(kStatusGroup_USDHC, 3U),          /*!< Transfer data failed */
-    kStatus_USDHC_DMADataAddrNotAlign = MAKE_STATUS(kStatusGroup_USDHC, 4U),         /*!< data address not align */
-    kStatus_USDHC_ReTuningRequest = MAKE_STATUS(kStatusGroup_USDHC, 5U),             /*!< re-tuning request */
-    kStatus_USDHC_TuningError = MAKE_STATUS(kStatusGroup_USDHC, 6U),                 /*!< tuning error */
-    kStatus_USDHC_NotSupport = MAKE_STATUS(kStatusGroup_USDHC, 7U),                  /*!< not support */
+    kStatus_USDHC_SendCommandFailed           = MAKE_STATUS(kStatusGroup_USDHC, 2U), /*!< Send command failed */
+    kStatus_USDHC_TransferDataFailed          = MAKE_STATUS(kStatusGroup_USDHC, 3U), /*!< Transfer data failed */
+    kStatus_USDHC_DMADataAddrNotAlign         = MAKE_STATUS(kStatusGroup_USDHC, 4U), /*!< data address not align */
+    kStatus_USDHC_ReTuningRequest             = MAKE_STATUS(kStatusGroup_USDHC, 5U), /*!< re-tuning request */
+    kStatus_USDHC_TuningError                 = MAKE_STATUS(kStatusGroup_USDHC, 6U), /*!< tuning error */
+    kStatus_USDHC_NotSupport                  = MAKE_STATUS(kStatusGroup_USDHC, 7U), /*!< not support */
 };
 
 /*! @brief Host controller capabilities flag mask */
 enum _usdhc_capability_flag
 {
-    kUSDHC_SupportAdmaFlag = USDHC_HOST_CTRL_CAP_ADMAS_MASK,        /*!< Support ADMA */
-    kUSDHC_SupportHighSpeedFlag = USDHC_HOST_CTRL_CAP_HSS_MASK,     /*!< Support high-speed */
-    kUSDHC_SupportDmaFlag = USDHC_HOST_CTRL_CAP_DMAS_MASK,          /*!< Support DMA */
-    kUSDHC_SupportSuspendResumeFlag = USDHC_HOST_CTRL_CAP_SRS_MASK, /*!< Support suspend/resume */
-    kUSDHC_SupportV330Flag = USDHC_HOST_CTRL_CAP_VS33_MASK,         /*!< Support voltage 3.3V */
-    kUSDHC_SupportV300Flag = USDHC_HOST_CTRL_CAP_VS30_MASK,         /*!< Support voltage 3.0V */
-    kUSDHC_SupportV180Flag = USDHC_HOST_CTRL_CAP_VS18_MASK,         /*!< Support voltage 1.8V */
+    kUSDHC_SupportAdmaFlag          = USDHC_HOST_CTRL_CAP_ADMAS_MASK, /*!< Support ADMA */
+    kUSDHC_SupportHighSpeedFlag     = USDHC_HOST_CTRL_CAP_HSS_MASK,   /*!< Support high-speed */
+    kUSDHC_SupportDmaFlag           = USDHC_HOST_CTRL_CAP_DMAS_MASK,  /*!< Support DMA */
+    kUSDHC_SupportSuspendResumeFlag = USDHC_HOST_CTRL_CAP_SRS_MASK,   /*!< Support suspend/resume */
+    kUSDHC_SupportV330Flag          = USDHC_HOST_CTRL_CAP_VS33_MASK,  /*!< Support voltage 3.3V */
+    kUSDHC_SupportV300Flag          = USDHC_HOST_CTRL_CAP_VS30_MASK,  /*!< Support voltage 3.0V */
+    kUSDHC_SupportV180Flag          = USDHC_HOST_CTRL_CAP_VS18_MASK,  /*!< Support voltage 1.8V */
     /* Put additional two flags in HTCAPBLT_MBL's position. */
     kUSDHC_Support4BitFlag = (USDHC_HOST_CTRL_CAP_MBL_SHIFT << 0U), /*!< Support 4 bit mode */
     kUSDHC_Support8BitFlag = (USDHC_HOST_CTRL_CAP_MBL_SHIFT << 1U), /*!< Support 8 bit mode */
@@ -86,19 +60,19 @@ enum _usdhc_capability_flag
 #if defined(FSL_FEATURE_USDHC_HAS_SDR104_MODE) && (!FSL_FEATURE_USDHC_HAS_SDR104_MODE)
     kUSDHC_SupportSDR104Flag = 0, /*!< not support SDR104 mode */
 #else
-    kUSDHC_SupportSDR104Flag = USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK, /*!< support SDR104 mode */
+    kUSDHC_SupportSDR104Flag   = USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK, /*!< support SDR104 mode */
 #endif
 #if defined(FSL_FEATURE_USDHC_HAS_SDR50_MODE) && (!FSL_FEATURE_USDHC_HAS_SDR50_MODE)
     kUSDHC_SupportSDR50Flag = 0U, /*!< not support SDR50 mode */
 #else
-    kUSDHC_SupportSDR50Flag = USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK,   /*!< support SDR50 mode */
+    kUSDHC_SupportSDR50Flag    = USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK,  /*!< support SDR50 mode */
 #endif
 };
 
 /*! @brief Wakeup event mask */
 enum _usdhc_wakeup_event
 {
-    kUSDHC_WakeupEventOnCardInt = USDHC_PROT_CTRL_WECINT_MASK,    /*!< Wakeup on card interrupt */
+    kUSDHC_WakeupEventOnCardInt    = USDHC_PROT_CTRL_WECINT_MASK, /*!< Wakeup on card interrupt */
     kUSDHC_WakeupEventOnCardInsert = USDHC_PROT_CTRL_WECINS_MASK, /*!< Wakeup on card insertion */
     kUSDHC_WakeupEventOnCardRemove = USDHC_PROT_CTRL_WECRM_MASK,  /*!< Wakeup on card removal */
 
@@ -109,14 +83,14 @@ enum _usdhc_wakeup_event
 /*! @brief Reset type mask */
 enum _usdhc_reset
 {
-    kUSDHC_ResetAll = USDHC_SYS_CTRL_RSTA_MASK,     /*!< Reset all except card detection */
+    kUSDHC_ResetAll     = USDHC_SYS_CTRL_RSTA_MASK, /*!< Reset all except card detection */
     kUSDHC_ResetCommand = USDHC_SYS_CTRL_RSTC_MASK, /*!< Reset command line */
-    kUSDHC_ResetData = USDHC_SYS_CTRL_RSTD_MASK,    /*!< Reset data line */
+    kUSDHC_ResetData    = USDHC_SYS_CTRL_RSTD_MASK, /*!< Reset data line */
 
 #if defined(FSL_FEATURE_USDHC_HAS_SDR50_MODE) && (!FSL_FEATURE_USDHC_HAS_SDR50_MODE)
     kUSDHC_ResetTuning = 0U, /*!< no reset tuning circuit bit */
 #else
-    kUSDHC_ResetTuning = USDHC_SYS_CTRL_RSTT_MASK,                      /*!< reset tuning circuit */
+    kUSDHC_ResetTuning         = USDHC_SYS_CTRL_RSTT_MASK,                /*!< reset tuning circuit */
 #endif
 
     kUSDHC_ResetsAll =
@@ -129,99 +103,99 @@ enum _usdhc_transfer_flag
     kUSDHC_EnableDmaFlag = USDHC_MIX_CTRL_DMAEN_MASK, /*!< Enable DMA */
 
     kUSDHC_CommandTypeSuspendFlag = (USDHC_CMD_XFR_TYP_CMDTYP(1U)), /*!< Suspend command */
-    kUSDHC_CommandTypeResumeFlag = (USDHC_CMD_XFR_TYP_CMDTYP(2U)),  /*!< Resume command */
-    kUSDHC_CommandTypeAbortFlag = (USDHC_CMD_XFR_TYP_CMDTYP(3U)),   /*!< Abort command */
+    kUSDHC_CommandTypeResumeFlag  = (USDHC_CMD_XFR_TYP_CMDTYP(2U)), /*!< Resume command */
+    kUSDHC_CommandTypeAbortFlag   = (USDHC_CMD_XFR_TYP_CMDTYP(3U)), /*!< Abort command */
 
-    kUSDHC_EnableBlockCountFlag = USDHC_MIX_CTRL_BCEN_MASK,      /*!< Enable block count */
+    kUSDHC_EnableBlockCountFlag    = USDHC_MIX_CTRL_BCEN_MASK,   /*!< Enable block count */
     kUSDHC_EnableAutoCommand12Flag = USDHC_MIX_CTRL_AC12EN_MASK, /*!< Enable auto CMD12 */
-    kUSDHC_DataReadFlag = USDHC_MIX_CTRL_DTDSEL_MASK,            /*!< Enable data read */
-    kUSDHC_MultipleBlockFlag = USDHC_MIX_CTRL_MSBSEL_MASK,       /*!< Multiple block data read/write */
+    kUSDHC_DataReadFlag            = USDHC_MIX_CTRL_DTDSEL_MASK, /*!< Enable data read */
+    kUSDHC_MultipleBlockFlag       = USDHC_MIX_CTRL_MSBSEL_MASK, /*!< Multiple block data read/write */
     kUSDHC_EnableAutoCommand23Flag = USDHC_MIX_CTRL_AC23EN_MASK, /*!< Enable auto CMD23 */
 
-    kUSDHC_ResponseLength136Flag = USDHC_CMD_XFR_TYP_RSPTYP(1U),    /*!< 136 bit response length */
-    kUSDHC_ResponseLength48Flag = USDHC_CMD_XFR_TYP_RSPTYP(2U),     /*!< 48 bit response length */
+    kUSDHC_ResponseLength136Flag    = USDHC_CMD_XFR_TYP_RSPTYP(1U), /*!< 136 bit response length */
+    kUSDHC_ResponseLength48Flag     = USDHC_CMD_XFR_TYP_RSPTYP(2U), /*!< 48 bit response length */
     kUSDHC_ResponseLength48BusyFlag = USDHC_CMD_XFR_TYP_RSPTYP(3U), /*!< 48 bit response length with busy status */
 
-    kUSDHC_EnableCrcCheckFlag = USDHC_CMD_XFR_TYP_CCCEN_MASK,   /*!< Enable CRC check */
+    kUSDHC_EnableCrcCheckFlag   = USDHC_CMD_XFR_TYP_CCCEN_MASK, /*!< Enable CRC check */
     kUSDHC_EnableIndexCheckFlag = USDHC_CMD_XFR_TYP_CICEN_MASK, /*!< Enable index check */
-    kUSDHC_DataPresentFlag = USDHC_CMD_XFR_TYP_DPSEL_MASK,      /*!< Data present flag */
+    kUSDHC_DataPresentFlag      = USDHC_CMD_XFR_TYP_DPSEL_MASK, /*!< Data present flag */
 };
 
 /*! @brief Present status flag mask */
 enum _usdhc_present_status_flag
 {
-    kUSDHC_CommandInhibitFlag = USDHC_PRES_STATE_CIHB_MASK,     /*!< Command inhibit */
-    kUSDHC_DataInhibitFlag = USDHC_PRES_STATE_CDIHB_MASK,       /*!< Data inhibit */
-    kUSDHC_DataLineActiveFlag = USDHC_PRES_STATE_DLA_MASK,      /*!< Data line active */
-    kUSDHC_SdClockStableFlag = USDHC_PRES_STATE_SDSTB_MASK,     /*!< SD bus clock stable */
-    kUSDHC_WriteTransferActiveFlag = USDHC_PRES_STATE_WTA_MASK, /*!< Write transfer active */
-    kUSDHC_ReadTransferActiveFlag = USDHC_PRES_STATE_RTA_MASK,  /*!< Read transfer active */
-    kUSDHC_BufferWriteEnableFlag = USDHC_PRES_STATE_BWEN_MASK,  /*!< Buffer write enable */
-    kUSDHC_BufferReadEnableFlag = USDHC_PRES_STATE_BREN_MASK,   /*!< Buffer read enable */
+    kUSDHC_CommandInhibitFlag      = USDHC_PRES_STATE_CIHB_MASK,  /*!< Command inhibit */
+    kUSDHC_DataInhibitFlag         = USDHC_PRES_STATE_CDIHB_MASK, /*!< Data inhibit */
+    kUSDHC_DataLineActiveFlag      = USDHC_PRES_STATE_DLA_MASK,   /*!< Data line active */
+    kUSDHC_SdClockStableFlag       = USDHC_PRES_STATE_SDSTB_MASK, /*!< SD bus clock stable */
+    kUSDHC_WriteTransferActiveFlag = USDHC_PRES_STATE_WTA_MASK,   /*!< Write transfer active */
+    kUSDHC_ReadTransferActiveFlag  = USDHC_PRES_STATE_RTA_MASK,   /*!< Read transfer active */
+    kUSDHC_BufferWriteEnableFlag   = USDHC_PRES_STATE_BWEN_MASK,  /*!< Buffer write enable */
+    kUSDHC_BufferReadEnableFlag    = USDHC_PRES_STATE_BREN_MASK,  /*!< Buffer read enable */
 
 #if defined(FSL_FEATURE_USDHC_HAS_SDR50_MODE) && (!FSL_FEATURE_USDHC_HAS_SDR50_MODE)
     kUSDHC_DelaySettingFinishedFlag = 0U, /*!< not support */
-    kUSDHC_ReTuningRequestFlag = 0U,      /*!< not support */
+    kUSDHC_ReTuningRequestFlag      = 0U, /*!< not support */
 #else
     kUSDHC_ReTuningRequestFlag = USDHC_PRES_STATE_RTR_MASK, /*!< re-tuning request flag ,only used for SDR104 mode */
     kUSDHC_DelaySettingFinishedFlag = USDHC_PRES_STATE_TSCD_MASK, /*!< delay setting finished flag */
 #endif
 
-    kUSDHC_CardInsertedFlag = USDHC_PRES_STATE_CINST_MASK,    /*!< Card inserted */
-    kUSDHC_CommandLineLevelFlag = USDHC_PRES_STATE_CLSL_MASK, /*!< Command line signal level */
-
-    kUSDHC_Data0LineLevelFlag = (1U << USDHC_PRES_STATE_DLSL_SHIFT),        /*!< Data0 line signal level */
-    kUSDHC_Data1LineLevelFlag = (1U << (USDHC_PRES_STATE_DLSL_SHIFT + 1U)), /*!< Data1 line signal level */
-    kUSDHC_Data2LineLevelFlag = (1U << (USDHC_PRES_STATE_DLSL_SHIFT + 2U)), /*!< Data2 line signal level */
-    kUSDHC_Data3LineLevelFlag = (1U << (USDHC_PRES_STATE_DLSL_SHIFT + 3U)), /*!< Data3 line signal level */
-    kUSDHC_Data4LineLevelFlag = (1U << (USDHC_PRES_STATE_DLSL_SHIFT + 4U)), /*!< Data4 line signal level */
-    kUSDHC_Data5LineLevelFlag = (1U << (USDHC_PRES_STATE_DLSL_SHIFT + 5U)), /*!< Data5 line signal level */
-    kUSDHC_Data6LineLevelFlag = (1U << (USDHC_PRES_STATE_DLSL_SHIFT + 6U)), /*!< Data6 line signal level */
-    kUSDHC_Data7LineLevelFlag = (1U << (USDHC_PRES_STATE_DLSL_SHIFT + 7U)), /*!< Data7 line signal level */
+    kUSDHC_CardInsertedFlag     = USDHC_PRES_STATE_CINST_MASK, /*!< Card inserted */
+    kUSDHC_CommandLineLevelFlag = USDHC_PRES_STATE_CLSL_MASK,  /*!< Command line signal level */
+
+    kUSDHC_Data0LineLevelFlag = 1U << USDHC_PRES_STATE_DLSL_SHIFT,               /*!< Data0 line signal level */
+    kUSDHC_Data1LineLevelFlag = 1U << (USDHC_PRES_STATE_DLSL_SHIFT + 1U),        /*!< Data1 line signal level */
+    kUSDHC_Data2LineLevelFlag = 1U << (USDHC_PRES_STATE_DLSL_SHIFT + 2U),        /*!< Data2 line signal level */
+    kUSDHC_Data3LineLevelFlag = 1U << (USDHC_PRES_STATE_DLSL_SHIFT + 3U),        /*!< Data3 line signal level */
+    kUSDHC_Data4LineLevelFlag = 1U << (USDHC_PRES_STATE_DLSL_SHIFT + 4U),        /*!< Data4 line signal level */
+    kUSDHC_Data5LineLevelFlag = 1U << (USDHC_PRES_STATE_DLSL_SHIFT + 5U),        /*!< Data5 line signal level */
+    kUSDHC_Data6LineLevelFlag = 1U << (USDHC_PRES_STATE_DLSL_SHIFT + 6U),        /*!< Data6 line signal level */
+    kUSDHC_Data7LineLevelFlag = (int)(1U << (USDHC_PRES_STATE_DLSL_SHIFT + 7U)), /*!< Data7 line signal level */
 };
 
 /*! @brief Interrupt status flag mask */
 enum _usdhc_interrupt_status_flag
 {
-    kUSDHC_CommandCompleteFlag = USDHC_INT_STATUS_CC_MASK,   /*!< Command complete */
-    kUSDHC_DataCompleteFlag = USDHC_INT_STATUS_TC_MASK,      /*!< Data complete */
-    kUSDHC_BlockGapEventFlag = USDHC_INT_STATUS_BGE_MASK,    /*!< Block gap event */
-    kUSDHC_DmaCompleteFlag = USDHC_INT_STATUS_DINT_MASK,     /*!< DMA interrupt */
-    kUSDHC_BufferWriteReadyFlag = USDHC_INT_STATUS_BWR_MASK, /*!< Buffer write ready */
-    kUSDHC_BufferReadReadyFlag = USDHC_INT_STATUS_BRR_MASK,  /*!< Buffer read ready */
-    kUSDHC_CardInsertionFlag = USDHC_INT_STATUS_CINS_MASK,   /*!< Card inserted */
-    kUSDHC_CardRemovalFlag = USDHC_INT_STATUS_CRM_MASK,      /*!< Card removed */
-    kUSDHC_CardInterruptFlag = USDHC_INT_STATUS_CINT_MASK,   /*!< Card interrupt */
+    kUSDHC_CommandCompleteFlag  = USDHC_INT_STATUS_CC_MASK,   /*!< Command complete */
+    kUSDHC_DataCompleteFlag     = USDHC_INT_STATUS_TC_MASK,   /*!< Data complete */
+    kUSDHC_BlockGapEventFlag    = USDHC_INT_STATUS_BGE_MASK,  /*!< Block gap event */
+    kUSDHC_DmaCompleteFlag      = USDHC_INT_STATUS_DINT_MASK, /*!< DMA interrupt */
+    kUSDHC_BufferWriteReadyFlag = USDHC_INT_STATUS_BWR_MASK,  /*!< Buffer write ready */
+    kUSDHC_BufferReadReadyFlag  = USDHC_INT_STATUS_BRR_MASK,  /*!< Buffer read ready */
+    kUSDHC_CardInsertionFlag    = USDHC_INT_STATUS_CINS_MASK, /*!< Card inserted */
+    kUSDHC_CardRemovalFlag      = USDHC_INT_STATUS_CRM_MASK,  /*!< Card removed */
+    kUSDHC_CardInterruptFlag    = USDHC_INT_STATUS_CINT_MASK, /*!< Card interrupt */
 
 #if defined(FSL_FEATURE_USDHC_HAS_SDR50_MODE) && (!FSL_FEATURE_USDHC_HAS_SDR50_MODE)
     kUSDHC_ReTuningEventFlag = 0U, /*!< Re-Tuning event,only for SD3.0 SDR104 mode */
-    kUSDHC_TuningPassFlag = 0U,    /*!< SDR104 mode tuning pass flag */
-    kUSDHC_TuningErrorFlag = 0U,   /*!< SDR104 tuning error flag */
+    kUSDHC_TuningPassFlag    = 0U, /*!< SDR104 mode tuning pass flag */
+    kUSDHC_TuningErrorFlag   = 0U, /*!< SDR104 tuning error flag */
 #else
-    kUSDHC_ReTuningEventFlag = USDHC_INT_STATUS_RTE_MASK,         /*!< Re-Tuning event,only for SD3.0 SDR104 mode */
-    kUSDHC_TuningPassFlag = USDHC_INT_STATUS_TP_MASK,             /*!< SDR104 mode tuning pass flag */
-    kUSDHC_TuningErrorFlag = USDHC_INT_STATUS_TNE_MASK,           /*!< SDR104 tuning error flag */
+    kUSDHC_ReTuningEventFlag        = USDHC_INT_STATUS_RTE_MASK,  /*!< Re-Tuning event,only for SD3.0 SDR104 mode */
+    kUSDHC_TuningPassFlag           = USDHC_INT_STATUS_TP_MASK,   /*!< SDR104 mode tuning pass flag */
+    kUSDHC_TuningErrorFlag          = USDHC_INT_STATUS_TNE_MASK,  /*!< SDR104 tuning error flag */
 #endif
 
-    kUSDHC_CommandTimeoutFlag = USDHC_INT_STATUS_CTOE_MASK,      /*!< Command timeout error */
-    kUSDHC_CommandCrcErrorFlag = USDHC_INT_STATUS_CCE_MASK,      /*!< Command CRC error */
+    kUSDHC_CommandTimeoutFlag     = USDHC_INT_STATUS_CTOE_MASK,  /*!< Command timeout error */
+    kUSDHC_CommandCrcErrorFlag    = USDHC_INT_STATUS_CCE_MASK,   /*!< Command CRC error */
     kUSDHC_CommandEndBitErrorFlag = USDHC_INT_STATUS_CEBE_MASK,  /*!< Command end bit error */
-    kUSDHC_CommandIndexErrorFlag = USDHC_INT_STATUS_CIE_MASK,    /*!< Command index error */
-    kUSDHC_DataTimeoutFlag = USDHC_INT_STATUS_DTOE_MASK,         /*!< Data timeout error */
-    kUSDHC_DataCrcErrorFlag = USDHC_INT_STATUS_DCE_MASK,         /*!< Data CRC error */
-    kUSDHC_DataEndBitErrorFlag = USDHC_INT_STATUS_DEBE_MASK,     /*!< Data end bit error */
+    kUSDHC_CommandIndexErrorFlag  = USDHC_INT_STATUS_CIE_MASK,   /*!< Command index error */
+    kUSDHC_DataTimeoutFlag        = USDHC_INT_STATUS_DTOE_MASK,  /*!< Data timeout error */
+    kUSDHC_DataCrcErrorFlag       = USDHC_INT_STATUS_DCE_MASK,   /*!< Data CRC error */
+    kUSDHC_DataEndBitErrorFlag    = USDHC_INT_STATUS_DEBE_MASK,  /*!< Data end bit error */
     kUSDHC_AutoCommand12ErrorFlag = USDHC_INT_STATUS_AC12E_MASK, /*!< Auto CMD12 error */
-    kUSDHC_DmaErrorFlag = USDHC_INT_STATUS_DMAE_MASK,            /*!< DMA error */
+    kUSDHC_DmaErrorFlag           = USDHC_INT_STATUS_DMAE_MASK,  /*!< DMA error */
 
     kUSDHC_CommandErrorFlag = (kUSDHC_CommandTimeoutFlag | kUSDHC_CommandCrcErrorFlag | kUSDHC_CommandEndBitErrorFlag |
                                kUSDHC_CommandIndexErrorFlag), /*!< Command error */
-    kUSDHC_DataErrorFlag = (kUSDHC_DataTimeoutFlag | kUSDHC_DataCrcErrorFlag | kUSDHC_DataEndBitErrorFlag |
-                            kUSDHC_AutoCommand12ErrorFlag),                                    /*!< Data error */
-    kUSDHC_ErrorFlag = (kUSDHC_CommandErrorFlag | kUSDHC_DataErrorFlag | kUSDHC_DmaErrorFlag), /*!< All error */
-    kUSDHC_DataFlag = (kUSDHC_DataCompleteFlag | kUSDHC_DmaCompleteFlag | kUSDHC_BufferWriteReadyFlag |
+    kUSDHC_DataErrorFlag    = (kUSDHC_DataTimeoutFlag | kUSDHC_DataCrcErrorFlag | kUSDHC_DataEndBitErrorFlag |
+                            kUSDHC_AutoCommand12ErrorFlag),                                        /*!< Data error */
+    kUSDHC_ErrorFlag        = (kUSDHC_CommandErrorFlag | kUSDHC_DataErrorFlag | kUSDHC_DmaErrorFlag), /*!< All error */
+    kUSDHC_DataFlag         = (kUSDHC_DataCompleteFlag | kUSDHC_DmaCompleteFlag | kUSDHC_BufferWriteReadyFlag |
                        kUSDHC_BufferReadReadyFlag | kUSDHC_DataErrorFlag | kUSDHC_DmaErrorFlag), /*!< Data interrupts */
-    kUSDHC_CommandFlag = (kUSDHC_CommandErrorFlag | kUSDHC_CommandCompleteFlag), /*!< Command interrupts */
-    kUSDHC_CardDetectFlag = (kUSDHC_CardInsertionFlag | kUSDHC_CardRemovalFlag), /*!< Card detection interrupts */
+    kUSDHC_CommandFlag      = (kUSDHC_CommandErrorFlag | kUSDHC_CommandCompleteFlag), /*!< Command interrupts */
+    kUSDHC_CardDetectFlag   = (kUSDHC_CardInsertionFlag | kUSDHC_CardRemovalFlag),    /*!< Card detection interrupts */
     kUSDHC_SDR104TuningFlag = (kUSDHC_TuningErrorFlag | kUSDHC_TuningPassFlag | kUSDHC_ReTuningEventFlag),
 
     kUSDHC_AllInterruptFlags = (kUSDHC_BlockGapEventFlag | kUSDHC_CardInterruptFlag | kUSDHC_CommandFlag |
@@ -231,32 +205,31 @@ enum _usdhc_interrupt_status_flag
 /*! @brief Auto CMD12 error status flag mask */
 enum _usdhc_auto_command12_error_status_flag
 {
-    kUSDHC_AutoCommand12NotExecutedFlag = USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK,  /*!< Not executed error */
-    kUSDHC_AutoCommand12TimeoutFlag = USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK,     /*!< Timeout error */
-    kUSDHC_AutoCommand12EndBitErrorFlag = USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK, /*!< End bit error */
-    kUSDHC_AutoCommand12CrcErrorFlag = USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK,     /*!< CRC error */
-    kUSDHC_AutoCommand12IndexErrorFlag = USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK,   /*!< Index error */
-    kUSDHC_AutoCommand12NotIssuedFlag = USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK, /*!< Not issued error */
+    kUSDHC_AutoCommand12NotExecutedFlag = USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK,    /*!< Not executed error */
+    kUSDHC_AutoCommand12TimeoutFlag     = USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK,   /*!< Timeout error */
+    kUSDHC_AutoCommand12EndBitErrorFlag = USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK,   /*!< End bit error */
+    kUSDHC_AutoCommand12CrcErrorFlag    = USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK,    /*!< CRC error */
+    kUSDHC_AutoCommand12IndexErrorFlag  = USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK,    /*!< Index error */
+    kUSDHC_AutoCommand12NotIssuedFlag   = USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK, /*!< Not issued error */
 };
 
 /*! @brief standard tuning flag */
 enum _usdhc_standard_tuning
 {
 #if defined(FSL_FEATURE_USDHC_HAS_SDR50_MODE) && (!FSL_FEATURE_USDHC_HAS_SDR50_MODE)
-    kUSDHC_ExecuteTuning = 0U,        /*!< not support */
+    kUSDHC_ExecuteTuning        = 0U, /*!< not support */
     kUSDHC_TuningSampleClockSel = 0U, /*!< not support */
 #else
-    kUSDHC_ExecuteTuning = USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK, /*!< used to start tuning procedure */
-    kUSDHC_TuningSampleClockSel =
-        USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK,               /*!< when std_tuning_en bit is set, this bit is used
-                                                                    select sampleing clock */
+    kUSDHC_ExecuteTuning        = USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK, /*!< used to start tuning procedure */
+    kUSDHC_TuningSampleClockSel = USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK, /*!< when std_tuning_en bit is set, this
+                                                                                bit is used select sampleing clock */
 #endif
 };
 
 /*! @brief ADMA error status flag mask */
 enum _usdhc_adma_error_status_flag
 {
-    kUSDHC_AdmaLenghMismatchFlag = USDHC_ADMA_ERR_STATUS_ADMALME_MASK,   /*!< Length mismatch error */
+    kUSDHC_AdmaLenghMismatchFlag   = USDHC_ADMA_ERR_STATUS_ADMALME_MASK, /*!< Length mismatch error */
     kUSDHC_AdmaDescriptorErrorFlag = USDHC_ADMA_ERR_STATUS_ADMADCE_MASK, /*!< Descriptor error */
 };
 
@@ -271,48 +244,49 @@ enum _usdhc_adma_error_state
         0x00U, /*!< Stop DMA, previous location set in the ADMA system address is error address */
     kUSDHC_AdmaErrorStateFetchDescriptor =
         0x01U, /*!< Fetch descriptor, current location set in the ADMA system address is error address */
-    kUSDHC_AdmaErrorStateChangeAddress = 0x02U, /*!< Change address, no DMA error is occured */
+    kUSDHC_AdmaErrorStateChangeAddress = 0x02U, /*!< Change address, no DMA error is occurred */
     kUSDHC_AdmaErrorStateTransferData =
         0x03U, /*!< Transfer data, previous location set in the ADMA system address is error address */
-    kUSDHC_AdmaErrorStateInvalidLength = 0x04U,     /*!< Invalid length in ADMA descriptor */
+    kUSDHC_AdmaErrorStateInvalidLength     = 0x04U, /*!< Invalid length in ADMA descriptor */
     kUSDHC_AdmaErrorStateInvalidDescriptor = 0x08U, /*!< Invalid descriptor fetched by ADMA */
 
     kUSDHC_AdmaErrorState = kUSDHC_AdmaErrorStateInvalidLength | kUSDHC_AdmaErrorStateInvalidDescriptor |
                             kUSDHC_AdmaErrorStateFetchDescriptor, /*!< ADMA error state */
 };
 
-/*! @brief Force event mask */
+/*! @brief Force event bit position */
 enum _usdhc_force_event
 {
     kUSDHC_ForceEventAutoCommand12NotExecuted = USDHC_FORCE_EVENT_FEVTAC12NE_MASK, /*!< Auto CMD12 not executed error */
-    kUSDHC_ForceEventAutoCommand12Timeout = USDHC_FORCE_EVENT_FEVTAC12TOE_MASK,    /*!< Auto CMD12 timeout error */
-    kUSDHC_ForceEventAutoCommand12CrcError = USDHC_FORCE_EVENT_FEVTAC12CE_MASK,    /*!< Auto CMD12 CRC error */
-    kUSDHC_ForceEventEndBitError = USDHC_FORCE_EVENT_FEVTAC12EBE_MASK,             /*!< Auto CMD12 end bit error */
-    kUSDHC_ForceEventAutoCommand12IndexError = USDHC_FORCE_EVENT_FEVTAC12IE_MASK,  /*!< Auto CMD12 index error */
+    kUSDHC_ForceEventAutoCommand12Timeout     = USDHC_FORCE_EVENT_FEVTAC12TOE_MASK, /*!< Auto CMD12 timeout error */
+    kUSDHC_ForceEventAutoCommand12CrcError    = USDHC_FORCE_EVENT_FEVTAC12CE_MASK,  /*!< Auto CMD12 CRC error */
+    kUSDHC_ForceEventEndBitError              = USDHC_FORCE_EVENT_FEVTAC12EBE_MASK, /*!< Auto CMD12 end bit error */
+    kUSDHC_ForceEventAutoCommand12IndexError  = USDHC_FORCE_EVENT_FEVTAC12IE_MASK,  /*!< Auto CMD12 index error */
     kUSDHC_ForceEventAutoCommand12NotIssued = USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK, /*!< Auto CMD12 not issued error */
-    kUSDHC_ForceEventCommandTimeout = USDHC_FORCE_EVENT_FEVTCTOE_MASK,              /*!< Command timeout error */
-    kUSDHC_ForceEventCommandCrcError = USDHC_FORCE_EVENT_FEVTCCE_MASK,              /*!< Command CRC error */
-    kUSDHC_ForceEventCommandEndBitError = USDHC_FORCE_EVENT_FEVTCEBE_MASK,          /*!< Command end bit error */
-    kUSDHC_ForceEventCommandIndexError = USDHC_FORCE_EVENT_FEVTCIE_MASK,            /*!< Command index error */
-    kUSDHC_ForceEventDataTimeout = USDHC_FORCE_EVENT_FEVTDTOE_MASK,                 /*!< Data timeout error */
-    kUSDHC_ForceEventDataCrcError = USDHC_FORCE_EVENT_FEVTDCE_MASK,                 /*!< Data CRC error */
-    kUSDHC_ForceEventDataEndBitError = USDHC_FORCE_EVENT_FEVTDEBE_MASK,             /*!< Data end bit error */
-    kUSDHC_ForceEventAutoCommand12Error = USDHC_FORCE_EVENT_FEVTAC12E_MASK,         /*!< Auto CMD12 error */
-    kUSDHC_ForceEventCardInt = USDHC_FORCE_EVENT_FEVTCINT_MASK,                     /*!< Card interrupt */
-    kUSDHC_ForceEventDmaError = USDHC_FORCE_EVENT_FEVTDMAE_MASK,                    /*!< Dma error */
+    kUSDHC_ForceEventCommandTimeout         = USDHC_FORCE_EVENT_FEVTCTOE_MASK,      /*!< Command timeout error */
+    kUSDHC_ForceEventCommandCrcError        = USDHC_FORCE_EVENT_FEVTCCE_MASK,       /*!< Command CRC error */
+    kUSDHC_ForceEventCommandEndBitError     = USDHC_FORCE_EVENT_FEVTCEBE_MASK,      /*!< Command end bit error */
+    kUSDHC_ForceEventCommandIndexError      = USDHC_FORCE_EVENT_FEVTCIE_MASK,       /*!< Command index error */
+    kUSDHC_ForceEventDataTimeout            = USDHC_FORCE_EVENT_FEVTDTOE_MASK,      /*!< Data timeout error */
+    kUSDHC_ForceEventDataCrcError           = USDHC_FORCE_EVENT_FEVTDCE_MASK,       /*!< Data CRC error */
+    kUSDHC_ForceEventDataEndBitError        = USDHC_FORCE_EVENT_FEVTDEBE_MASK,      /*!< Data end bit error */
+    kUSDHC_ForceEventAutoCommand12Error     = USDHC_FORCE_EVENT_FEVTAC12E_MASK,     /*!< Auto CMD12 error */
+    kUSDHC_ForceEventCardInt                = (int)USDHC_FORCE_EVENT_FEVTCINT_MASK, /*!< Card interrupt */
+    kUSDHC_ForceEventDmaError               = USDHC_FORCE_EVENT_FEVTDMAE_MASK,      /*!< Dma error */
 #if defined(FSL_FEATURE_USDHC_HAS_SDR50_MODE) && (!FSL_FEATURE_USDHC_HAS_SDR50_MODE)
     kUSDHC_ForceEventTuningError = 0U, /*!< not support */
 #else
-    kUSDHC_ForceEventTuningError = USDHC_FORCE_EVENT_FEVTTNE_MASK, /*!< Tuning error */
+    kUSDHC_ForceEventTuningError = USDHC_FORCE_EVENT_FEVTTNE_MASK,             /*!< Tuning error */
 #endif
+
     kUSDHC_ForceEventsAll =
-        (kUSDHC_ForceEventAutoCommand12NotExecuted | kUSDHC_ForceEventAutoCommand12Timeout |
-         kUSDHC_ForceEventAutoCommand12CrcError | kUSDHC_ForceEventEndBitError |
-         kUSDHC_ForceEventAutoCommand12IndexError | kUSDHC_ForceEventAutoCommand12NotIssued |
-         kUSDHC_ForceEventCommandTimeout | kUSDHC_ForceEventCommandCrcError | kUSDHC_ForceEventCommandEndBitError |
-         kUSDHC_ForceEventCommandIndexError | kUSDHC_ForceEventDataTimeout | kUSDHC_ForceEventDataCrcError |
-         kUSDHC_ForceEventDataEndBitError | kUSDHC_ForceEventAutoCommand12Error | kUSDHC_ForceEventCardInt |
-         kUSDHC_ForceEventDmaError | kUSDHC_ForceEventTuningError), /*!< All force event flags mask */
+        (int)(USDHC_FORCE_EVENT_FEVTAC12NE_MASK | USDHC_FORCE_EVENT_FEVTAC12TOE_MASK |
+              USDHC_FORCE_EVENT_FEVTAC12CE_MASK | USDHC_FORCE_EVENT_FEVTAC12EBE_MASK |
+              USDHC_FORCE_EVENT_FEVTAC12IE_MASK | USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK |
+              USDHC_FORCE_EVENT_FEVTCTOE_MASK | USDHC_FORCE_EVENT_FEVTCCE_MASK | USDHC_FORCE_EVENT_FEVTCEBE_MASK |
+              USDHC_FORCE_EVENT_FEVTCIE_MASK | USDHC_FORCE_EVENT_FEVTDTOE_MASK | USDHC_FORCE_EVENT_FEVTDCE_MASK |
+              USDHC_FORCE_EVENT_FEVTDEBE_MASK | USDHC_FORCE_EVENT_FEVTAC12E_MASK | USDHC_FORCE_EVENT_FEVTCINT_MASK |
+              USDHC_FORCE_EVENT_FEVTDMAE_MASK | kUSDHC_ForceEventTuningError), /*!< All force event flags mask */
 };
 
 /*! @brief Data transfer width */
@@ -326,45 +300,45 @@ typedef enum _usdhc_data_bus_width
 /*! @brief Endian mode */
 typedef enum _usdhc_endian_mode
 {
-    kUSDHC_EndianModeBig = 0U,         /*!< Big endian mode */
+    kUSDHC_EndianModeBig         = 0U, /*!< Big endian mode */
     kUSDHC_EndianModeHalfWordBig = 1U, /*!< Half word big endian mode */
-    kUSDHC_EndianModeLittle = 2U,      /*!< Little endian mode */
+    kUSDHC_EndianModeLittle      = 2U, /*!< Little endian mode */
 } usdhc_endian_mode_t;
 
 /*! @brief DMA mode */
 typedef enum _usdhc_dma_mode
 {
     kUSDHC_DmaModeSimple = 0U, /*!< external DMA */
-    kUSDHC_DmaModeAdma1 = 1U,  /*!< ADMA1 is selected */
-    kUSDHC_DmaModeAdma2 = 2U,  /*!< ADMA2 is selected */
-    kUSDHC_ExternalDMA = 3U,   /*!< external dma mode select */
+    kUSDHC_DmaModeAdma1  = 1U, /*!< ADMA1 is selected */
+    kUSDHC_DmaModeAdma2  = 2U, /*!< ADMA2 is selected */
+    kUSDHC_ExternalDMA   = 3U, /*!< external dma mode select */
 } usdhc_dma_mode_t;
 
 /*! @brief SDIO control flag mask */
 enum _usdhc_sdio_control_flag
 {
-    kUSDHC_StopAtBlockGapFlag = USDHC_PROT_CTRL_SABGREQ_MASK,     /*!< Stop at block gap */
-    kUSDHC_ReadWaitControlFlag = USDHC_PROT_CTRL_RWCTL_MASK,      /*!< Read wait control */
-    kUSDHC_InterruptAtBlockGapFlag = USDHC_PROT_CTRL_IABG_MASK,   /*!< Interrupt at block gap */
-    kUSDHC_ReadDoneNo8CLK = USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK, /*!< read done without 8 clk for block gap */
+    kUSDHC_StopAtBlockGapFlag      = USDHC_PROT_CTRL_SABGREQ_MASK,         /*!< Stop at block gap */
+    kUSDHC_ReadWaitControlFlag     = USDHC_PROT_CTRL_RWCTL_MASK,           /*!< Read wait control */
+    kUSDHC_InterruptAtBlockGapFlag = USDHC_PROT_CTRL_IABG_MASK,            /*!< Interrupt at block gap */
+    kUSDHC_ReadDoneNo8CLK          = USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK, /*!< read done without 8 clk for block gap */
     kUSDHC_ExactBlockNumberReadFlag = USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK, /*!< Exact block number read */
 };
 
 /*! @brief MMC card boot mode */
 typedef enum _usdhc_boot_mode
 {
-    kUSDHC_BootModeNormal = 0U,      /*!< Normal boot */
+    kUSDHC_BootModeNormal      = 0U, /*!< Normal boot */
     kUSDHC_BootModeAlternative = 1U, /*!< Alternative boot */
 } usdhc_boot_mode_t;
 
 /*! @brief The command type */
 typedef enum _usdhc_card_command_type
 {
-    kCARD_CommandTypeNormal = 0U,  /*!< Normal command */
+    kCARD_CommandTypeNormal  = 0U, /*!< Normal command */
     kCARD_CommandTypeSuspend = 1U, /*!< Suspend command */
-    kCARD_CommandTypeResume = 2U,  /*!< Resume command */
-    kCARD_CommandTypeAbort = 3U,   /*!< Abort command */
-    kCARD_CommandTypeEmpty = 4U,   /*!< Empty command */
+    kCARD_CommandTypeResume  = 2U, /*!< Resume command */
+    kCARD_CommandTypeAbort   = 3U, /*!< Abort command */
+    kCARD_CommandTypeEmpty   = 4U, /*!< Empty command */
 } usdhc_card_command_type_t;
 
 /*!
@@ -375,15 +349,15 @@ typedef enum _usdhc_card_command_type
 typedef enum _usdhc_card_response_type
 {
     kCARD_ResponseTypeNone = 0U, /*!< Response type: none */
-    kCARD_ResponseTypeR1 = 1U,   /*!< Response type: R1 */
-    kCARD_ResponseTypeR1b = 2U,  /*!< Response type: R1b */
-    kCARD_ResponseTypeR2 = 3U,   /*!< Response type: R2 */
-    kCARD_ResponseTypeR3 = 4U,   /*!< Response type: R3 */
-    kCARD_ResponseTypeR4 = 5U,   /*!< Response type: R4 */
-    kCARD_ResponseTypeR5 = 6U,   /*!< Response type: R5 */
-    kCARD_ResponseTypeR5b = 7U,  /*!< Response type: R5b */
-    kCARD_ResponseTypeR6 = 8U,   /*!< Response type: R6 */
-    kCARD_ResponseTypeR7 = 9U,   /*!< Response type: R7 */
+    kCARD_ResponseTypeR1   = 1U, /*!< Response type: R1 */
+    kCARD_ResponseTypeR1b  = 2U, /*!< Response type: R1b */
+    kCARD_ResponseTypeR2   = 3U, /*!< Response type: R2 */
+    kCARD_ResponseTypeR3   = 4U, /*!< Response type: R3 */
+    kCARD_ResponseTypeR4   = 5U, /*!< Response type: R4 */
+    kCARD_ResponseTypeR5   = 6U, /*!< Response type: R5 */
+    kCARD_ResponseTypeR5b  = 7U, /*!< Response type: R5b */
+    kCARD_ResponseTypeR6   = 8U, /*!< Response type: R6 */
+    kCARD_ResponseTypeR7   = 9U, /*!< Response type: R7 */
 } usdhc_card_response_type_t;
 
 /*! @brief The alignment size for ADDRESS filed in ADMA1's descriptor */
@@ -425,18 +399,23 @@ typedef enum _usdhc_card_response_type
 #define USDHC_ADMA1_DESCRIPTOR_LENGTH_SHIFT (12U)
 /*! @brief The mask for LENGTH field in ADMA1's descriptor */
 #define USDHC_ADMA1_DESCRIPTOR_LENGTH_MASK (0xFFFFU)
-/*! @brief The maximum value of LENGTH filed in ADMA1's descriptor */
-#define USDHC_ADMA1_DESCRIPTOR_MAX_LENGTH_PER_ENTRY (USDHC_ADMA1_DESCRIPTOR_LENGTH_MASK - 3U)
+/*! @brief The maximum value of LENGTH filed in ADMA1's descriptor
+ * Since the ADMA1 support max transfer size is 65535 which is not divisible by
+ * 4096, so to make sure a large data load transfer(>64KB) continuously(require the data
+ * address should be alwawys align with 4096), software will set the maximum data length
+ * for ADMA1 to (64 - 4)KB.
+ */
+#define USDHC_ADMA1_DESCRIPTOR_MAX_LENGTH_PER_ENTRY (USDHC_ADMA1_DESCRIPTOR_LENGTH_MASK + 1U - 4096U)
 
 /*! @brief The mask for the control/status field in ADMA1 descriptor */
 enum _usdhc_adma1_descriptor_flag
 {
-    kUSDHC_Adma1DescriptorValidFlag = (1U << 0U),                      /*!< Valid flag */
-    kUSDHC_Adma1DescriptorEndFlag = (1U << 1U),                        /*!< End flag */
-    kUSDHC_Adma1DescriptorInterrupFlag = (1U << 2U),                   /*!< Interrupt flag */
-    kUSDHC_Adma1DescriptorActivity1Flag = (1U << 4U),                  /*!< Activity 1 flag */
-    kUSDHC_Adma1DescriptorActivity2Flag = (1U << 5U),                  /*!< Activity 2 flag */
-    kUSDHC_Adma1DescriptorTypeNop = (kUSDHC_Adma1DescriptorValidFlag), /*!< No operation */
+    kUSDHC_Adma1DescriptorValidFlag     = (1U << 0U),                        /*!< Valid flag */
+    kUSDHC_Adma1DescriptorEndFlag       = (1U << 1U),                        /*!< End flag */
+    kUSDHC_Adma1DescriptorInterrupFlag  = (1U << 2U),                        /*!< Interrupt flag */
+    kUSDHC_Adma1DescriptorActivity1Flag = (1U << 4U),                        /*!< Activity 1 flag */
+    kUSDHC_Adma1DescriptorActivity2Flag = (1U << 5U),                        /*!< Activity 2 flag */
+    kUSDHC_Adma1DescriptorTypeNop       = (kUSDHC_Adma1DescriptorValidFlag), /*!< No operation */
     kUSDHC_Adma1DescriptorTypeTransfer =
         (kUSDHC_Adma1DescriptorActivity2Flag | kUSDHC_Adma1DescriptorValidFlag), /*!< Transfer data */
     kUSDHC_Adma1DescriptorTypeLink = (kUSDHC_Adma1DescriptorActivity1Flag | kUSDHC_Adma1DescriptorActivity2Flag |
@@ -476,8 +455,8 @@ enum _usdhc_adma1_descriptor_flag
 /*! @brief ADMA1 descriptor control and status mask */
 enum _usdhc_adma2_descriptor_flag
 {
-    kUSDHC_Adma2DescriptorValidFlag = (1U << 0U),     /*!< Valid flag */
-    kUSDHC_Adma2DescriptorEndFlag = (1U << 1U),       /*!< End flag */
+    kUSDHC_Adma2DescriptorValidFlag     = (1U << 0U), /*!< Valid flag */
+    kUSDHC_Adma2DescriptorEndFlag       = (1U << 1U), /*!< End flag */
     kUSDHC_Adma2DescriptorInterruptFlag = (1U << 2U), /*!< Interrupt flag */
     kUSDHC_Adma2DescriptorActivity1Flag = (1U << 4U), /*!< Activity 1 mask */
     kUSDHC_Adma2DescriptorActivity2Flag = (1U << 5U), /*!< Activity 2 mask */
@@ -506,17 +485,17 @@ enum _usdhc_adma_flag
 /*! @brief dma transfer burst len config. */
 typedef enum _usdhc_burst_len
 {
-    kUSDHC_EnBurstLenForINCR = 0x01U,         /*!< enable burst len for INCR */
-    kUSDHC_EnBurstLenForINCR4816 = 0x02U,     /*!< enable burst len for INCR4/INCR8/INCR16 */
+    kUSDHC_EnBurstLenForINCR         = 0x01U, /*!< enable burst len for INCR */
+    kUSDHC_EnBurstLenForINCR4816     = 0x02U, /*!< enable burst len for INCR4/INCR8/INCR16 */
     kUSDHC_EnBurstLenForINCR4816WRAP = 0x04U, /*!< enable burst len for INCR4/8/16 WRAP */
 } usdhc_burst_len_t;
 
 /*! @brief transfer data type definition. */
 enum _usdhc_transfer_data_type
 {
-    kUSDHC_TransferDataNormal = 0U,        /*!< transfer normal read/write data */
-    kUSDHC_TransferDataTuning = 1U,        /*!< transfer tuning data */
-    kUSDHC_TransferDataBoot = 2U,          /*!< transfer boot data */
+    kUSDHC_TransferDataNormal        = 0U, /*!< transfer normal read/write data */
+    kUSDHC_TransferDataTuning        = 1U, /*!< transfer tuning data */
+    kUSDHC_TransferDataBoot          = 2U, /*!< transfer boot data */
     kUSDHC_TransferDataBootcontinous = 3U, /*!< transfer boot data continous */
 };
 
@@ -655,7 +634,6 @@ struct _usdhc_handle
     usdhc_command_t *volatile command; /*!< Command to send */
 
     /* Transfer status */
-    volatile uint32_t interruptFlags;   /*!< Interrupt flags of last transaction */
     volatile uint32_t transferredWords; /*!< Words transferred by DATAPORT way */
 
     /* Callback functions */
@@ -756,9 +734,9 @@ status_t USDHC_SetAdmaTableConfig(USDHC_Type *base,
  * This function is used to config the USDHC DMA related registers.
  * @param base USDHC peripheral base address.
  * @param adma configuration
- * @param dataAddr tranfer data address, a simple DMA parameter, if ADMA is used, leave it to NULL.
- * @param enAutoCmd23 flag to indicate Auto CMD23 is enable or not, a simple DMA parameter,if ADMA is used, leave it to
- * false.
+ * @param dataAddr transfer data address, a simple DMA parameter, if ADMA is used, leave it to NULL.
+ * @param enAutoCmd23 flag to indicate Auto CMD23 is enable or not, a simple DMA parameter,if ADMA is used, leave it
+ * to false.
  * @retval kStatus_OutOfRange ADMA descriptor table length isn't enough to describe data.
  * @retval kStatus_Success Operate successfully.
  */
@@ -874,6 +852,17 @@ static inline void USDHC_DisableInterruptSignal(USDHC_Type *base, uint32_t mask)
  * @{
  */
 
+/*!
+ * @brief Gets the enabled interrupt status.
+ *
+ * @param base USDHC peripheral base address.
+ * @return Current interrupt status flags mask(_usdhc_interrupt_status_flag).
+ */
+static inline uint32_t USDHC_GetEnabledInterruptStatusFlags(USDHC_Type *base)
+{
+    return (base->INT_STATUS) & (base->INT_SIGNAL_EN);
+}
+
 /*!
  * @brief Gets the current interrupt status.
  *
@@ -1044,11 +1033,11 @@ static inline uint32_t USDHC_ReadData(USDHC_Type *base)
 }
 
 /*!
-* @brief send command function
-*
-* @param base USDHC peripheral base address.
-* @param command configuration
-*/
+ * @brief send command function
+ *
+ * @param base USDHC peripheral base address.
+ * @param command configuration
+ */
 void USDHC_SendCommand(USDHC_Type *base, usdhc_command_t *command);
 
 /*!
@@ -1187,7 +1176,7 @@ static inline void USDHC_EnableMmcBoot(USDHC_Type *base, bool enable)
  * @brief Forces generating events according to the given mask.
  *
  * @param base USDHC peripheral base address.
- * @param mask The force events mask(_usdhc_force_event).
+ * @param mask The force events bit posistion (_usdhc_force_event).
  */
 static inline void USDHC_SetForceEvent(USDHC_Type *base, uint32_t mask)
 {
@@ -1214,10 +1203,10 @@ static inline void UDSHC_SelectVoltage(USDHC_Type *base, bool en18v)
 
 #if defined(FSL_FEATURE_USDHC_HAS_SDR50_MODE) && (FSL_FEATURE_USDHC_HAS_SDR50_MODE)
 /*!
-* @brief check the SDR50 mode request tuning bit
-* When this bit set, user should call USDHC_StandardTuning function
-* @param base USDHC peripheral base address.
-*/
+ * @brief check the SDR50 mode request tuning bit
+ * When this bit set, user should call USDHC_StandardTuning function
+ * @param base USDHC peripheral base address.
+ */
 static inline bool USDHC_RequestTuningForSDR50(USDHC_Type *base)
 {
     return base->HOST_CTRL_CAP & USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK ? true : false;
@@ -1432,8 +1421,8 @@ static inline uint32_t USDHC_GetStrobeDLLStatus(USDHC_Type *base)
  * This function waits until the command response/data is received or the USDHC encounters an error by polling the
  * status
  * flag.
- * The application must not call this API in multiple threads at the same time. Because of that this API doesn't support
- * the re-entry mechanism.
+ * The application must not call this API in multiple threads at the same time. Because of that this API doesn't
+ * support the re-entry mechanism.
  *
  * @note There is no need to call the API 'USDHC_TransferCreateHandle' when calling this API.
  *
@@ -1464,10 +1453,9 @@ void USDHC_TransferCreateHandle(USDHC_Type *base,
 /*!
  * @brief Transfers the command/data using an interrupt and an asynchronous method.
  *
- * This function sends a command and data and returns immediately. It doesn't wait the transfer complete or encounter an
- * error.
- * The application must not call this API in multiple threads at the same time. Because of that this API doesn't support
- * the re-entry mechanism.
+ * This function sends a command and data and returns immediately. It doesn't wait the transfer complete or
+ * encounter an error. The application must not call this API in multiple threads at the same time. Because of that
+ * this API doesn't support the re-entry mechanism.
  *
  * @note Call the API 'USDHC_TransferCreateHandle' when calling this API.
  *
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_wdog.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_wdog.c
index b1cc4eb1fbd..54ee7e61943 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_wdog.c
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_wdog.c
@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
+ * Copyright 2016-2018 NXP
  * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
  *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include "fsl_wdog.h"
@@ -39,7 +13,6 @@
 #define FSL_COMPONENT_ID "platform.drivers.wdog01"
 #endif
 
-
 /*******************************************************************************
  * Variables
  ******************************************************************************/
@@ -49,6 +22,8 @@ static WDOG_Type *const s_wdogBases[] = WDOG_BASE_PTRS;
 static const clock_ip_name_t s_wdogClock[] = WDOG_CLOCKS;
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
+static const IRQn_Type s_wdogIRQ[] = WDOG_IRQS;
+
 /*******************************************************************************
  * Code
  ******************************************************************************/
@@ -70,23 +45,62 @@ static uint32_t WDOG_GetInstance(WDOG_Type *base)
     return instance;
 }
 
+/*!
+ * brief Initializes the WDOG configuration structure.
+ *
+ * This function initializes the WDOG configuration structure to default values. The default
+ * values are as follows.
+ * code
+ *   wdogConfig->enableWdog = true;
+ *   wdogConfig->workMode.enableWait = true;
+ *   wdogConfig->workMode.enableStop = false;
+ *   wdogConfig->workMode.enableDebug = false;
+ *   wdogConfig->enableInterrupt = false;
+ *   wdogConfig->enablePowerdown = false;
+ *   wdogConfig->resetExtension = flase;
+ *   wdogConfig->timeoutValue = 0xFFU;
+ *   wdogConfig->interruptTimeValue = 0x04u;
+ * endcode
+ *
+ * param config Pointer to the WDOG configuration structure.
+ * see wdog_config_t
+ */
 void WDOG_GetDefaultConfig(wdog_config_t *config)
 {
     assert(config);
 
-    config->enableWdog = true;
-    config->workMode.enableWait = false;
-    config->workMode.enableStop = false;
-    config->workMode.enableDebug = false;
-    config->enableInterrupt = false;
+    /* Initializes the configure structure to zero. */
+    memset(config, 0, sizeof(*config));
+
+    config->enableWdog             = true;
+    config->workMode.enableWait    = false;
+    config->workMode.enableStop    = false;
+    config->workMode.enableDebug   = false;
+    config->enableInterrupt        = false;
     config->softwareResetExtension = false;
-    config->enablePowerDown = false;
-    config->softwareAssertion= true;
-    config->softwareResetSignal = true;
-    config->timeoutValue = 0xffu;
-    config->interruptTimeValue = 0x04u;
+    config->enablePowerDown        = false;
+    config->timeoutValue           = 0xffu;
+    config->interruptTimeValue     = 0x04u;
+    config->enableTimeOutAssert    = false;
 }
 
+/*!
+ * brief Initializes the WDOG.
+ *
+ * This function initializes the WDOG. When called, the WDOG runs according to the configuration.
+ *
+ * This is an example.
+ * code
+ *   wdog_config_t config;
+ *   WDOG_GetDefaultConfig(&config);
+ *   config.timeoutValue = 0xffU;
+ *   config->interruptTimeValue = 0x04u;
+ *   WDOG_Init(wdog_base,&config);
+ * endcode
+ *
+ * param base   WDOG peripheral base address
+ * param config The configuration of WDOG
+ */
 void WDOG_Init(WDOG_Type *base, const wdog_config_t *config)
 {
     assert(config);
@@ -96,15 +110,30 @@ void WDOG_Init(WDOG_Type *base, const wdog_config_t *config)
     value = WDOG_WCR_WDE(config->enableWdog) | WDOG_WCR_WDW(config->workMode.enableWait) |
             WDOG_WCR_WDZST(config->workMode.enableStop) | WDOG_WCR_WDBG(config->workMode.enableDebug) |
             WDOG_WCR_SRE(config->softwareResetExtension) | WDOG_WCR_WT(config->timeoutValue) |
-            WDOG_WCR_WDA(config->softwareAssertion) | WDOG_WCR_SRS(config->softwareResetSignal);
+            WDOG_WCR_WDT(config->enableTimeOutAssert) | WDOG_WCR_SRS_MASK | WDOG_WCR_WDA_MASK;
 
-    /* Set configruation */
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Set configuration */
     CLOCK_EnableClock(s_wdogClock[WDOG_GetInstance(base)]);
+#endif
+
     base->WICR = WDOG_WICR_WICT(config->interruptTimeValue) | WDOG_WICR_WIE(config->enableInterrupt);
     base->WMCR = WDOG_WMCR_PDE(config->enablePowerDown);
-    base->WCR = value;
+    base->WCR  = value;
+    if (config->enableInterrupt)
+    {
+        EnableIRQ(s_wdogIRQ[WDOG_GetInstance(base)]);
+    }
 }
 
+/*!
+ * brief Shuts down the WDOG.
+ *
+ * This function shuts down the WDOG.
+ * Watchdog Enable bit is a write one once only bit. It is not
+ * possible to clear this bit by a software write, once the bit is set.
+ * This bit(WDE) can be set/reset only in debug mode(exception).
+ */
 void WDOG_Deinit(WDOG_Type *base)
 {
     if (base->WCR & WDOG_WCR_WDBG_MASK)
@@ -113,6 +142,20 @@ void WDOG_Deinit(WDOG_Type *base)
     }
 }
 
+/*!
+ * brief Gets the WDOG all reset status flags.
+ *
+ * This function gets all reset status flags.
+ *
+ * code
+ * uint16_t status;
+ * status = WDOG_GetStatusFlags (wdog_base);
+ * endcode
+ * param base        WDOG peripheral base address
+ * return            State of the status flag: asserted (true) or not-asserted (false).see _wdog_status_flags
+ *                    - true: a related status flag has been set.
+ *                    - false: a related status flag is not set.
+ */
 uint16_t WDOG_GetStatusFlags(WDOG_Type *base)
 {
     uint16_t status_flag = 0U;
@@ -126,6 +169,20 @@ uint16_t WDOG_GetStatusFlags(WDOG_Type *base)
     return status_flag;
 }
 
+/*!
+ * brief Clears the WDOG flag.
+ *
+ * This function clears the WDOG status flag.
+ *
+ * This is an example for clearing the interrupt flag.
+ * code
+ *   WDOG_ClearStatusFlags(wdog_base,KWDOG_InterruptFlag);
+ * endcode
+ * param base        WDOG peripheral base address
+ * param mask        The status flags to clear.
+ *                    The parameter could be any combination of the following values.
+ *                    kWDOG_TimeoutFlag
+ */
 void WDOG_ClearInterruptStatus(WDOG_Type *base, uint16_t mask)
 {
     if (mask & kWDOG_InterruptFlag)
@@ -134,6 +191,14 @@ void WDOG_ClearInterruptStatus(WDOG_Type *base, uint16_t mask)
     }
 }
 
+/*!
+ * brief Refreshes the WDOG timer.
+ *
+ * This function feeds the WDOG.
+ * This function should be called before the WDOG timer is in timeout. Otherwise, a reset is asserted.
+ *
+ * param base WDOG peripheral base address
+ */
 void WDOG_Refresh(WDOG_Type *base)
 {
     base->WSR = WDOG_REFRESH_KEY & 0xFFFFU;
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_wdog.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_wdog.h
index 508714bbe10..d8e0628a3ec 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_wdog.h
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_wdog.h
@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
+ * Copyright 2016-2018 NXP
  * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
  *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 #ifndef _FSL_WDOG_H_
 #define _FSL_WDOG_H_
@@ -47,11 +21,11 @@
 /*! @name Driver version */
 /*@{*/
 /*! @brief Defines WDOG driver version */
-#define FSL_WDOG_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+#define FSL_WDOG_DRIVER_VERSION (MAKE_VERSION(2, 1, 0))
 /*@}*/
 /*! @name Refresh sequence */
 /*@{*/
-#define WDOG_REFRESH_KEY                         (0xAAAA5555U)
+#define WDOG_REFRESH_KEY (0xAAAA5555U)
 /*@}*/
 
 /*! @brief Defines WDOG work mode. */
@@ -72,8 +46,7 @@ typedef struct _wdog_config
     uint16_t interruptTimeValue; /*!< Interrupt count timeout value */
     bool softwareResetExtension; /*!< software reset extension */
     bool enablePowerDown;        /*!< power down enable bit */
-    bool softwareAssertion;      /*!< software assertion bit*/
-    bool softwareResetSignal;    /*!< software reset signalbit*/
+    bool enableTimeOutAssert;    /*!< Enable WDOG_B timeout assertion. */
 } wdog_config_t;
 
 /*!
@@ -93,11 +66,11 @@ enum _wdog_interrupt_enable
  */
 enum _wdog_status_flags
 {
-    kWDOG_RunningFlag = WDOG_WCR_WDE_MASK,         /*!< Running flag, set when WDOG is enabled*/
-    kWDOG_PowerOnResetFlag = WDOG_WRSR_POR_MASK,   /*!< Power On flag, set when reset is the result of a powerOnReset*/
-    kWDOG_TimeoutResetFlag = WDOG_WRSR_TOUT_MASK,  /*!< Timeout flag, set when reset is the result of a timeout*/
+    kWDOG_RunningFlag       = WDOG_WCR_WDE_MASK,   /*!< Running flag, set when WDOG is enabled*/
+    kWDOG_PowerOnResetFlag  = WDOG_WRSR_POR_MASK,  /*!< Power On flag, set when reset is the result of a powerOnReset*/
+    kWDOG_TimeoutResetFlag  = WDOG_WRSR_TOUT_MASK, /*!< Timeout flag, set when reset is the result of a timeout*/
     kWDOG_SoftwareResetFlag = WDOG_WRSR_SFTW_MASK, /*!< Software flag, set when reset is the result of a software*/
-    kWDOG_InterruptFlag = WDOG_WICR_WTIS_MASK      /*!< interrupt flag,whether interrupt has occurred or not*/
+    kWDOG_InterruptFlag     = WDOG_WICR_WTIS_MASK  /*!< interrupt flag,whether interrupt has occurred or not*/
 };
 
 /*******************************************************************************
@@ -114,7 +87,7 @@ extern "C" {
  */
 
 /*!
- * @brief Initializes the WDOG configuration sturcture.
+ * @brief Initializes the WDOG configuration structure.
  *
  * This function initializes the WDOG configuration structure to default values. The default
  * values are as follows.
@@ -190,6 +163,36 @@ static inline void WDOG_Disable(WDOG_Type *base)
     base->WCR &= ~WDOG_WCR_WDE_MASK;
 }
 
+/*!
+ * @brief Trigger the system software reset.
+ *
+ * This function will write to the WCR[SRS] bit to trigger a software system reset.
+ * This bit will automatically resets to "1" after it has been asserted to "0".
+ * Note: Calling this API will reset the system right now, please using it with more attention.
+ *
+ * @param base WDOG peripheral base address
+ */
+static inline void WDOG_TriggerSystemSoftwareReset(WDOG_Type *base)
+{
+    base->WCR &= ~WDOG_WCR_SRS_MASK;
+}
+
+/*!
+ * @brief Trigger an output assertion.
+ *
+ * This function will write to the WCR[WDA] bit to trigger WDOG_B signal assertion.
+ * The WDOG_B signal can be routed to external pin of the chip, the output pin will turn to
+ * assertion along with WDOG_B signal.
+ * Note: The WDOG_B signal will remain assert until a power on reset occurred, so, please
+ * take more attention while calling it.
+ *
+ * @param base WDOG peripheral base address
+ */
+static inline void WDOG_TriggerSoftwareSignal(WDOG_Type *base)
+{
+    base->WCR &= ~WDOG_WCR_WDA_MASK;
+}
+
 /*!
  * @brief Enables the WDOG interrupt.
  *
@@ -291,7 +294,6 @@ static inline void WDOG_DisablePowerDownEnable(WDOG_Type *base)
  * @param base WDOG peripheral base address
  */
 void WDOG_Refresh(WDOG_Type *base);
-
 /*@}*/
 
 #if defined(__cplusplus)
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_xbara.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_xbara.c
index 3a8d9035658..ab39eb738fe 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_xbara.c
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_xbara.c
@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
  * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
  *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include "fsl_xbara.h"
@@ -43,6 +17,8 @@
 #define FSL_COMPONENT_ID "platform.drivers.xbara"
 #endif
 
+/* Macros for entire XBARA_CTRL register.  */
+#define XBARA_CTRLx(base, index) ((&(base->CTRL0))[index])
 
 /*******************************************************************************
  * Prototypes
@@ -90,6 +66,13 @@ static uint32_t XBARA_GetInstance(XBARA_Type *base)
     return instance;
 }
 
+/*!
+ * brief Initializes the XBARA module.
+ *
+ * This function un-gates the XBARA clock.
+ *
+ * param base XBARA peripheral address.
+ */
 void XBARA_Init(XBARA_Type *base)
 {
 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
@@ -98,6 +81,13 @@ void XBARA_Init(XBARA_Type *base)
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }
 
+/*!
+ * brief Shuts down the XBARA module.
+ *
+ * This function disables XBARA clock.
+ *
+ * param base XBARA peripheral address.
+ */
 void XBARA_Deinit(XBARA_Type *base)
 {
 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
@@ -106,11 +96,39 @@ void XBARA_Deinit(XBARA_Type *base)
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }
 
+/*!
+ * brief Sets a connection between the selected XBARA_IN[*] input and the XBARA_OUT[*] output signal.
+ *
+ * This function connects the XBARA input to the selected XBARA output.
+ * If more than one XBARA module is available, only the inputs and outputs from the same module
+ * can be connected.
+ *
+ * Example:
+   code
+   XBARA_SetSignalsConnection(XBARA, kXBARA_InputPIT_TRG0, kXBARA_OutputDMAMUX18);
+   endcode
+ *
+ * param base XBARA peripheral address.
+ * param input XBARA input signal.
+ * param output XBARA output signal.
+ */
 void XBARA_SetSignalsConnection(XBARA_Type *base, xbar_input_signal_t input, xbar_output_signal_t output)
 {
     XBARA_WR_SELx_SELx(base, (((uint16_t)input) & 0xFFU), (((uint16_t)output) & 0xFFU));
 }
 
+/*!
+ * brief Gets the active edge detection status.
+ *
+ * This function gets the active edge detect status of all XBARA_OUTs. If the
+ * active edge occurs, the return value is asserted. When the interrupt or the DMA
+ * functionality is enabled for the XBARA_OUTx, this field is 1 when the interrupt
+ * or DMA request is asserted and 0 when the interrupt or DMA request has been
+ * cleared.
+ *
+ * param base XBARA peripheral address.
+ * return the mask of these status flag bits.
+ */
 uint32_t XBARA_GetStatusFlags(XBARA_Type *base)
 {
     uint32_t status_flag;
@@ -121,6 +139,12 @@ uint32_t XBARA_GetStatusFlags(XBARA_Type *base)
     return status_flag;
 }
 
+/*!
+ * brief Clears the edge detection status flags of relative mask.
+ *
+ * param base XBARA peripheral address.
+ * param mask the status flags to clear.
+ */
 void XBARA_ClearStatusFlags(XBARA_Type *base, uint32_t mask)
 {
     uint16_t regVal;
@@ -144,79 +168,55 @@ void XBARA_ClearStatusFlags(XBARA_Type *base, uint32_t mask)
     base->CTRL1 = regVal;
 }
 
+/*!
+ * brief Configures the XBARA control register.
+ *
+ * This function configures an XBARA control register. The active edge detection
+ * and the DMA/IRQ function on the corresponding XBARA output can be set.
+ *
+ * Example:
+   code
+   xbara_control_config_t userConfig;
+   userConfig.activeEdge = kXBARA_EdgeRising;
+   userConfig.requestType = kXBARA_RequestInterruptEnalbe;
+   XBARA_SetOutputSignalConfig(XBARA, kXBARA_OutputDMAMUX18, &userConfig);
+   endcode
+ *
+ * param base XBARA peripheral address.
+ * param output XBARA output number.
+ * param controlConfig Pointer to structure that keeps configuration of control register.
+ */
 void XBARA_SetOutputSignalConfig(XBARA_Type *base,
                                  xbar_output_signal_t output,
                                  const xbara_control_config_t *controlConfig)
 {
     uint16_t regVal;
-    /* Set active edge for edge detection, set interrupt or DMA function. */
-    switch ((uint16_t)output)
+    uint8_t outputIndex = (uint8_t)output & 0xFFU;
+    uint8_t regIndex;
+    uint8_t shiftInReg;
+
+    assert(outputIndex < FSL_FEATURE_XBARA_INTERRUPT_COUNT);
+
+    regIndex = outputIndex / 2;
+
+    if ((outputIndex & 0x01U) != 0U)
     {
-#if defined(FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_30) && FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_30 
-        case kXBARA1_OutputDmaChMuxReq30:
-#else
-        case kXBARA_OutputDmamux18:
-#endif
-            /* Assign regVal to CTRL0 register's value */
-            regVal = (base->CTRL0);
-            /* Perform this command to avoid writing 1 into interrupt flag bits and clears bit DEN0, IEN0 */
-            regVal &= (uint16_t)(
-                ~(XBARA_CTRL0_STS0_MASK | XBARA_CTRL0_STS1_MASK | XBARA_CTRL0_DEN0_MASK | XBARA_CTRL0_IEN0_MASK));
-            /* Configure edge and request type */
-            regVal |= (uint16_t)(XBARA_CTRL0_EDGE0(controlConfig->activeEdge) |
-                                 ((controlConfig->requestType) << XBARA_CTRL0_DEN0_SHIFT));
-            /* Write regVal value into CTRL0 register */
-            base->CTRL0 = regVal;
-            break;
-#if defined(FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_31) && FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_31 
-        case kXBARA1_OutputDmaChMuxReq31:
-#else
-        case kXBARA_OutputDmamux19:
-#endif
-            /* Assign regVal to CTRL0 register's value */
-            regVal = (base->CTRL0);
-            /* Perform this command to avoid writing 1 into interrupt flag bits and clears bit DEN1, IEN1 */
-            regVal &= (uint16_t)(
-                ~(XBARA_CTRL0_STS0_MASK | XBARA_CTRL0_STS1_MASK | XBARA_CTRL0_DEN1_MASK | XBARA_CTRL0_IEN1_MASK));
-            /* Configure edge and request type */
-            regVal |= (uint16_t)(XBARA_CTRL0_EDGE1(controlConfig->activeEdge) |
-                                 ((controlConfig->requestType) << XBARA_CTRL0_DEN1_SHIFT));
-            /* Write regVal value into CTRL0 register */
-            base->CTRL0 = regVal;
-            break;
-#if defined(FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_94) && FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_94 
-        case kXBARA1_OutputDmaChMuxReq94:
-#else
-        case kXBARA_OutputDmamux20:
-#endif
-            /* Assign regVal to CTRL1 register's value */
-            regVal = (base->CTRL1);
-            /* Perform this command to avoid writing 1 into interrupt flag bits and clears bit DEN2, IEN2 */
-            regVal &= (uint16_t)(
-                ~(XBARA_CTRL1_STS2_MASK | XBARA_CTRL1_STS3_MASK | XBARA_CTRL1_DEN2_MASK | XBARA_CTRL1_IEN2_MASK));
-            /* Configure edge and request type */
-            regVal |= (uint16_t)(XBARA_CTRL1_EDGE2(controlConfig->activeEdge) |
-                                 ((controlConfig->requestType) << XBARA_CTRL1_DEN2_SHIFT));
-            /* Write regVal value into CTRL1 register */
-            base->CTRL1 = regVal;
-            break;
-#if defined(FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_95) && FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_95 
-        case kXBARA1_OutputDmaChMuxReq95:
-#else
-             case kXBARA_OutputDmamux21:
-#endif
-            /* Assign regVal to CTRL1 register's value */
-            regVal = (base->CTRL1);
-            /* Perform this command to avoid writing 1 into interrupt flag bits and clears bit DEN3, IEN3 */
-            regVal &= (uint16_t)(
-                ~(XBARA_CTRL1_STS2_MASK | XBARA_CTRL1_STS3_MASK | XBARA_CTRL1_DEN3_MASK | XBARA_CTRL1_IEN3_MASK));
-            /* Configure edge and request type */
-            regVal |= (uint16_t)(XBARA_CTRL1_EDGE3(controlConfig->activeEdge) |
-                                 ((controlConfig->requestType) << XBARA_CTRL1_DEN3_SHIFT));
-            /* Write regVal value into CTRL1 register */
-            base->CTRL1 = regVal;
-            break;
-        default:
-            break;
+        shiftInReg = 8;
+    }
+    else
+    {
+        shiftInReg = 0;
     }
+
+    regVal = XBARA_CTRLx(base, regIndex);
+
+    /* Don't clear the status flags. */
+    regVal &= (uint16_t)(~(XBARA_CTRL0_STS0_MASK | XBARA_CTRL0_STS1_MASK));
+
+    regVal &= (uint16_t)(~((XBARA_CTRL0_DEN0_MASK | XBARA_CTRL0_IEN0_MASK | XBARA_CTRL0_EDGE0_MASK) << shiftInReg));
+    regVal |= (uint16_t)(
+        (XBARA_CTRL0_EDGE0(controlConfig->activeEdge) | ((controlConfig->requestType) << XBARA_CTRL0_DEN0_SHIFT))
+        << shiftInReg);
+
+    XBARA_CTRLx(base, regIndex) = regVal;
 }
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_xbara.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_xbara.h
index 98410a198b9..5fd69456007 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_xbara.h
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_xbara.h
@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
+ * Copyright 2016-2019 NXP
  * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #ifndef _FSL_XBARA_H_
@@ -46,7 +20,7 @@
  * Definitions
  ******************************************************************************/
 
-#define FSL_XBARA_DRIVER_VERSION (MAKE_VERSION(2, 0, 3)) /*!< Version 2.0.3. */
+#define FSL_XBARA_DRIVER_VERSION (MAKE_VERSION(2, 0, 4)) /*!< Version 2.0.4. */
 
 /* Macros for entire XBARA_SELx register.  */
 #define XBARA_SELx(base, output) (*(volatile uint16_t *)((uintptr_t) & (base->SEL0) + ((output) / 2U) * 2U))
@@ -61,10 +35,10 @@
  */
 typedef enum _xbara_active_edge
 {
-    kXBARA_EdgeNone = 0U,            /*!< Edge detection status bit never asserts. */
-    kXBARA_EdgeRising = 1U,          /*!< Edge detection status bit asserts on rising edges. */
-    kXBARA_EdgeFalling = 2U,         /*!< Edge detection status bit asserts on falling edges. */
-    kXBARA_EdgeRisingAndFalling = 3U /*!< Edge detection status bit asserts on rising and falling edges. */
+    kXBARA_EdgeNone             = 0U, /*!< Edge detection status bit never asserts. */
+    kXBARA_EdgeRising           = 1U, /*!< Edge detection status bit asserts on rising edges. */
+    kXBARA_EdgeFalling          = 2U, /*!< Edge detection status bit asserts on falling edges. */
+    kXBARA_EdgeRisingAndFalling = 3U  /*!< Edge detection status bit asserts on rising and falling edges. */
 } xbara_active_edge_t;
 
 /*!
@@ -72,9 +46,9 @@ typedef enum _xbara_active_edge
  */
 typedef enum _xbar_request
 {
-    kXBARA_RequestDisable = 0U,        /*!< Interrupt and DMA are disabled. */
-    kXBARA_RequestDMAEnable = 1U,      /*!< DMA enabled, interrupt disabled. */
-    kXBARA_RequestInterruptEnalbe = 2U /*!< Interrupt enabled, DMA disabled. */
+    kXBARA_RequestDisable         = 0U, /*!< Interrupt and DMA are disabled. */
+    kXBARA_RequestDMAEnable       = 1U, /*!< DMA enabled, interrupt disabled. */
+    kXBARA_RequestInterruptEnalbe = 2U  /*!< Interrupt enabled, DMA disabled. */
 } xbara_request_t;
 
 /*!
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_xbarb.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_xbarb.c
index 627b0ab91fa..ec8c05f1a5a 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_xbarb.c
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_xbarb.c
@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
  * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
  *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include "fsl_xbarb.h"
@@ -43,7 +17,6 @@
 #define FSL_COMPONENT_ID "platform.drivers.xbarb"
 #endif
 
-
 /*******************************************************************************
  * Prototypes
  ******************************************************************************/
@@ -90,6 +63,13 @@ static uint32_t XBARB_GetInstance(XBARB_Type *base)
     return instance;
 }
 
+/*!
+ * brief Initializes the XBARB module.
+ *
+ * This function un-gates the XBARB clock.
+ *
+ * param base XBARB peripheral address.
+ */
 void XBARB_Init(XBARB_Type *base)
 {
 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
@@ -98,6 +78,13 @@ void XBARB_Init(XBARB_Type *base)
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }
 
+/*!
+ * brief Shuts down the XBARB module.
+ *
+ * This function disables XBARB clock.
+ *
+ * param base XBARB peripheral address.
+ */
 void XBARB_Deinit(XBARB_Type *base)
 {
 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
@@ -106,6 +93,17 @@ void XBARB_Deinit(XBARB_Type *base)
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }
 
+/*!
+ * brief Configures a connection between the selected XBARB_IN[*] input and the XBARB_OUT[*] output signal.
+ *
+ * This function configures which XBARB input is connected to the selected XBARB output.
+ * If more than one XBARB module is available, only the inputs and outputs from the same module
+ * can be connected.
+ *
+ * param base XBARB peripheral address.
+ * param input XBARB input signal.
+ * param output XBARB output signal.
+ */
 void XBARB_SetSignalsConnection(XBARB_Type *base, xbar_input_signal_t input, xbar_output_signal_t output)
 {
     XBARB_WR_SELx_SELx(base, (((uint16_t)input) & 0xFFU), (((uint16_t)output) & 0xFFU));
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_xbarb.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_xbarb.h
index 38e687fb062..b4598806058 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_xbarb.h
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_xbarb.h
@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
  * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
  *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #ifndef _FSL_XBARB_H_
diff --git a/targets/targets.json b/targets/targets.json
index 1f78c6da88a..63b636cc384 100644
--- a/targets/targets.json
+++ b/targets/targets.json
@@ -1914,11 +1914,18 @@
             "XIP_BOOT_HEADER_ENABLE=1",
             "XIP_EXTERNAL_FLASH=1",
             "XIP_BOOT_HEADER_DCD_ENABLE=1",
+            "HYPERFLASH_BOOT",
+            "FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE=1",
             "SKIP_SYSCLK_INIT",
             "FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE",
+            "__STARTUP_INITIALIZE_RAMFUNCTION",
+            "__STARTUP_INITIALIZE_NONCACHEDATA",
             "MBED_MPU_CUSTOM",
             "MBED_TICKLESS"
         ],
+        "components_add": [
+            "FLASHIAP"
+        ],
         "inherits": ["Target"],
         "detect_code": ["0227"],
         "device_has": [
@@ -1940,12 +1947,16 @@
             "SPI",
             "SPISLAVE",
             "STDIO_MESSAGES",
-            "TRNG"
+            "TRNG",
+            "WATCHDOG",
+            "FLASH"
         ],
         "release_versions": ["2", "5"],
         "features": ["LWIP"],
         "device_name": "MIMXRT1052",
+        "bootloader_supported": true,
         "overrides": {
+            "deep-sleep-latency": 10,
             "network-default-interface-type": "ETHERNET"
         }
     },