fix(NetworkModule): fix CLK delta delay problem in TX path

Author: jakubcabal

core/comp/eth/network_mod/comp/network_mod_core/network_mod_core_cmac.vhd

@@ -564,6 +564,8 @@ architecture CMAC of NETWORK_MOD_CORE is
     signal cmac_tx_lbus_sop        : std_logic_vector(4-1 downto 0);
     signal cmac_tx_lbus_rdy        : std_logic;
 
+    signal mfb2lbus_rx_mfb_dst_rdy : std_logic;
+
     signal adap_tx_mfb_data        : slv_array_t(ETH_PORT_CHAN-1 downto 0)(REGIONS*REGION_SIZE*BLOCK_SIZE*ITEM_WIDTH-1 downto 0);
     signal adap_tx_mfb_crc_err     : slv_array_t(ETH_PORT_CHAN-1 downto 0)(REGIONS-1 downto 0);
     signal adap_tx_mfb_sof_pos     : slv_array_t(ETH_PORT_CHAN-1 downto 0)(REGIONS*max(1,log2(REGION_SIZE))-1 downto 0);
@@ -1449,6 +1451,10 @@ begin
     --  ADAPTERS
     -- =========================================================================
 
+    -- JC: This dump assignment/renaming is necessary here to synchronize
+    -- the delta delay (for simulators) between the clock and data signals!
+    RX_MFB_DST_RDY(0) <= mfb2lbus_rx_mfb_dst_rdy;
+
     mfb2lbus_i : entity work.TX_MAC_LITE_ADAPTER_LBUS
     generic map(
         DEVICE => DEVICE
@@ -1463,7 +1469,7 @@ begin
         IN_MFB_SOF     => RX_MFB_SOF(0),
         IN_MFB_EOF     => RX_MFB_EOF(0),
         IN_MFB_SRC_RDY => RX_MFB_SRC_RDY(0),
-        IN_MFB_DST_RDY => RX_MFB_DST_RDY(0),
+        IN_MFB_DST_RDY => mfb2lbus_rx_mfb_dst_rdy,
 
         OUT_LBUS_DATA  => cmac_tx_lbus_data,
         OUT_LBUS_MTY   => cmac_tx_lbus_mty,

core/comp/eth/network_mod/comp/network_mod_core/network_mod_core_etile.vhd

@@ -523,6 +523,8 @@ architecture ETILE of NETWORK_MOD_CORE is
     signal rx_avst_empty     : std_logic_vector(ETH_PORT_CHAN*AVST_EMPTY_WIDTH   -1 downto 0);
     signal rx_avst_error     : std_logic_vector(ETH_PORT_CHAN*RX_AVST_ERROR_WIDTH-1 downto 0);
 
+    signal mfb2avst_rx_mfb_dst_rdy : std_logic_vector(ETH_PORT_CHAN-1 downto 0);
+
     signal tx_adap_mfb_clk     : std_logic_vector(ETH_PORT_CHAN-1 downto 0) := (others => '0');
     signal tx_adap_mfb_data    : slv_array_t(ETH_PORT_CHAN-1 downto 0)(REGIONS*REGION_SIZE*BLOCK_SIZE*ITEM_WIDTH-1 downto 0);
     signal tx_adap_mfb_crc_err : slv_array_t(ETH_PORT_CHAN-1 downto 0)(REGIONS-1 downto 0);
@@ -1377,6 +1379,10 @@ begin
             mfb2avst_rx_mfb_eof <= RX_MFB_EOF(IT);
         end process;
 
+        -- JC: This assignment/renaming is necessary here to synchronize
+        -- the delta delay (for simulators) between the clock and data signals!
+        RX_MFB_DST_RDY(IT) <= mfb2avst_rx_mfb_dst_rdy(IT);
+
         -- TX adaption
         mfb2avst_i : entity work.TX_MAC_LITE_ADAPTER_AVST_100G
         generic map(
@@ -1394,7 +1400,7 @@ begin
             RX_MFB_EOF     => mfb2avst_rx_mfb_eof,
             RX_MFB_EOF_POS => RX_MFB_EOF_POS(IT),
             RX_MFB_SRC_RDY => RX_MFB_SRC_RDY(IT),
-            RX_MFB_DST_RDY => RX_MFB_DST_RDY(IT),
+            RX_MFB_DST_RDY => mfb2avst_rx_mfb_dst_rdy(IT),
 
             TX_AVST_DATA   => tx_ad_avst_data,
             TX_AVST_SOP    => tx_ad_avst_sop,

core/comp/eth/network_mod/comp/network_mod_core/network_mod_core_ftile.vhd

@@ -212,6 +212,8 @@ architecture FULL of NETWORK_MOD_CORE is
     signal adap_tx_mfb_eof        : slv_array_t(ETH_PORT_CHAN-1 downto 0)(REGIONS-1 downto 0);
     signal adap_tx_mfb_src_rdy    : std_logic_vector(ETH_PORT_CHAN-1 downto 0);
 
+    signal adap_rx_mfb_dst_rdy    : std_logic_vector(ETH_PORT_CHAN-1 downto 0);
+
     begin
 
         mi_splitter_i : entity work.MI_SPLITTER_PLUS_GEN
@@ -820,13 +822,18 @@ architecture FULL of NETWORK_MOD_CORE is
             IN_MFB_EOF_POS    => RX_MFB_EOF_POS(i),
             IN_MFB_ERROR      => (others => '0'),
             IN_MFB_SRC_RDY    => RX_MFB_SRC_RDY(i),
-            IN_MFB_DST_RDY    => RX_MFB_DST_RDY(i),
+            IN_MFB_DST_RDY    => adap_rx_mfb_dst_rdy(i),
             OUT_MAC_DATA      => ftile_tx_adapt_data(i),
             OUT_MAC_INFRAME   => ftile_tx_adapt_inframe(i),
             OUT_MAC_EOP_EMPTY => ftile_tx_adapt_eop_empty(i),
             OUT_MAC_ERROR     => ftile_tx_adapt_error(i),
             OUT_MAC_VALID     => ftile_tx_adapt_valid(i),
             OUT_MAC_READY     => ftile_tx_mac_ready(i)
         );
+
+        -- JC: This dump assignment/renaming is necessary here to synchronize
+        -- the delta delay (for simulators) between the clock and data signals!
+        RX_MFB_DST_RDY(i) <= adap_rx_mfb_dst_rdy(i);
+
     end generate;
 end architecture;

core/comp/eth/network_mod/network_mod.vhd

@@ -174,6 +174,8 @@ architecture FULL of NETWORK_MOD is
     signal tx_mfb_src_rdy_i : slv_array_t   (ETH_PORTS-1 downto 0)(ETH_CHANNELS-1 downto 0);
     signal tx_mfb_dst_rdy_i : slv_array_t   (ETH_PORTS-1 downto 0)(ETH_CHANNELS-1 downto 0);
 
+    signal core_rx_mfb_dst_rdy : slv_array_t   (ETH_PORTS-1 downto 0)(ETH_CHANNELS-1 downto 0);
+
     -- Control/Status signals
     signal sig_activity_rx : slv_array_t(ETH_PORTS-1 downto 0)(ETH_CHANNELS-1 downto 0);
     signal sig_activity_tx : slv_array_t(ETH_PORTS-1 downto 0)(ETH_CHANNELS-1 downto 0);
@@ -510,7 +512,7 @@ begin
             RX_MFB_SOF      => tx_mfb_sof_i    (p),
             RX_MFB_EOF      => tx_mfb_eof_i    (p),
             RX_MFB_SRC_RDY  => tx_mfb_src_rdy_i(p),
-            RX_MFB_DST_RDY  => tx_mfb_dst_rdy_i(p),
+            RX_MFB_DST_RDY  => core_rx_mfb_dst_rdy(p),
 
             RX_MVB_CHANNEL   => mvb_ch (p),
             RX_MVB_TIMESTAMP => mvb_ts (p),
@@ -574,6 +576,10 @@ begin
         rx_mfb_crc_err_i <= core_tx_mfb_crc_err;
         rx_mfb_src_rdy_i <= core_tx_mfb_src_rdy;
 
+        -- JC: This assignment/renaming is necessary here to synchronize
+        -- the delta delay (for simulators) between the clock and data signals!
+        tx_mfb_dst_rdy_i <= core_rx_mfb_dst_rdy;
+
         -- =====================================================================
         -- TIMESTAMP synchronization
         -- =====================================================================