Merge branch 'marushchenko-feat-netmod-add_better_bcast_support' into 'devel'

jakubcabal · jakubcabal · commit b30d8960faf0 · 2025-05-14T06:03:59.000Z
A larger set of generated frames from the Hard IP side + fixes

See merge request ndk/ndk-fpga!208
diff --git a/comp/nic/mac_lite/rx_mac_lite/comp/mac_check/mac_check.vhd b/comp/nic/mac_lite/rx_mac_lite/comp/mac_check/mac_check.vhd
@@ -224,7 +224,7 @@ begin
 
     mac_cast_err_g : for r in 0 to REGIONS-1 generate
         -- Possible multicast error occurence
-        s_multicast_err(r) <= not s_ext_mac_arr(r)(0);
+        s_multicast_err(r) <= (not s_ext_mac_arr(r)(0)) or not s_broadcast_err(r);
         -- Possible broadcast error occurence
         s_broadcast_err(r) <= nand s_ext_mac_arr(r);
     end generate;
diff --git a/comp/nic/mac_lite/rx_mac_lite/comp/stat_unit/rx_stat_unit.vhd b/comp/nic/mac_lite/rx_mac_lite/comp/stat_unit/rx_stat_unit.vhd
@@ -237,8 +237,8 @@ begin
             s_reg_in_rfc_below_min <= IN_LEN_BELOW_MIN;
             s_reg_in_rfc_over_mtu  <= IN_LEN_OVER_MTU;
             s_reg_in_rfc_mac_err   <= IN_MAC_ERROR;
-            s_reg_in_rfc_mac_mcast <= IN_MAC_BCAST;
-            s_reg_in_rfc_mac_bcast <= IN_MAC_MCAST and not IN_MAC_BCAST;
+            s_reg_in_rfc_mac_mcast <= IN_MAC_MCAST;
+            s_reg_in_rfc_mac_bcast <= IN_MAC_BCAST;
             s_reg_in_rfc_fragment  <= IN_CRC_ERROR and s_frame_below_64;
             s_reg_in_rfc_jabber    <= IN_CRC_ERROR and s_frame_over_1518;
             s_reg_in_frame_len     <= s_fixed_frame_len;
diff --git a/comp/uvm/packet_generators/sequence_flowtest.sv b/comp/uvm/packet_generators/sequence_flowtest.sv
@@ -40,6 +40,8 @@ class sequence_flowtest #(int unsigned ITEM_WIDTH) extends uvm_common::sequence_
     int unsigned mac_mask_min = 24;
     int unsigned mac_mask_max = 48;
 
+    bit mac_broadcast = 1;
+
     // Generator options
     bit generated_config = 1;
     bit generated_profile = 1;
@@ -117,6 +119,9 @@ class sequence_flowtest #(int unsigned ITEM_WIDTH) extends uvm_common::sequence_
             mac[i].mask inside { [mac_mask_min : mac_mask_max] };
         }
     }
+    constraint c_mac_broadcast {
+        mac_broadcast -> (mac.sum with (item.address == '1) == 1);
+    }
 
     rand int unsigned seed;
 
@@ -172,6 +177,25 @@ class sequence_flowtest #(int unsigned ITEM_WIDTH) extends uvm_common::sequence_
         ipv4 = ipv4.unique() with (item.address);
         ipv6 = ipv6.unique() with (item.address);
         mac  = mac .unique() with (item.address);
+
+        // Tool doesnt support less address that 2
+        while (ipv4.size() < 2) begin
+            ipv4 = new[ipv4.size()+1](ipv4);
+            std::randomize(ipv4[ipv4.size()-1].address);
+            std::randomize(ipv4[ipv4.size()-1].mask) with { ipv4[ipv4.size()-1].mask <= 32;};
+        end
+
+        while (ipv6.size() < 2) begin
+            ipv6 = new[ipv6.size()+1](ipv6);
+            std::randomize(ipv6[ipv6.size()-1].address);
+            std::randomize(ipv6[ipv6.size()-1].mask) with { ipv6[ipv6.size()-1].mask <= 128;};
+        end
+
+        while (mac.size() < 2) begin
+            mac = new[mac.size()+1](mac);
+            std::randomize(mac[mac.size()-1].address);
+            std::randomize(mac[mac.size()-1].mask) with { mac[mac.size()-1].mask <= 128;};
+        end
     endfunction
 
     function string get_ipv4_addresses();
diff --git a/core/comp/eth/network_mod/comp/network_mod_core/network_mod_core_cmac.vhd b/core/comp/eth/network_mod/comp/network_mod_core/network_mod_core_cmac.vhd
@@ -564,6 +564,8 @@ architecture CMAC of NETWORK_MOD_CORE is
     signal cmac_tx_lbus_sop        : std_logic_vector(4-1 downto 0);
     signal cmac_tx_lbus_rdy        : std_logic;
 
+    signal mfb2lbus_rx_mfb_dst_rdy : std_logic;
+
     signal adap_tx_mfb_data        : slv_array_t(ETH_PORT_CHAN-1 downto 0)(REGIONS*REGION_SIZE*BLOCK_SIZE*ITEM_WIDTH-1 downto 0);
     signal adap_tx_mfb_crc_err     : slv_array_t(ETH_PORT_CHAN-1 downto 0)(REGIONS-1 downto 0);
     signal adap_tx_mfb_sof_pos     : slv_array_t(ETH_PORT_CHAN-1 downto 0)(REGIONS*max(1,log2(REGION_SIZE))-1 downto 0);
@@ -1449,6 +1451,10 @@ begin
     --  ADAPTERS
     -- =========================================================================
 
+    -- JC: This dump assignment/renaming is necessary here to synchronize
+    -- the delta delay (for simulators) between the clock and data signals!
+    RX_MFB_DST_RDY(0) <= mfb2lbus_rx_mfb_dst_rdy;
+
     mfb2lbus_i : entity work.TX_MAC_LITE_ADAPTER_LBUS
     generic map(
         DEVICE => DEVICE
@@ -1463,7 +1469,7 @@ begin
         IN_MFB_SOF     => RX_MFB_SOF(0),
         IN_MFB_EOF     => RX_MFB_EOF(0),
         IN_MFB_SRC_RDY => RX_MFB_SRC_RDY(0),
-        IN_MFB_DST_RDY => RX_MFB_DST_RDY(0),
+        IN_MFB_DST_RDY => mfb2lbus_rx_mfb_dst_rdy,
 
         OUT_LBUS_DATA  => cmac_tx_lbus_data,
         OUT_LBUS_MTY   => cmac_tx_lbus_mty,
diff --git a/core/comp/eth/network_mod/comp/network_mod_core/network_mod_core_etile.vhd b/core/comp/eth/network_mod/comp/network_mod_core/network_mod_core_etile.vhd
@@ -523,6 +523,8 @@ architecture ETILE of NETWORK_MOD_CORE is
     signal rx_avst_empty     : std_logic_vector(ETH_PORT_CHAN*AVST_EMPTY_WIDTH   -1 downto 0);
     signal rx_avst_error     : std_logic_vector(ETH_PORT_CHAN*RX_AVST_ERROR_WIDTH-1 downto 0);
 
+    signal mfb2avst_rx_mfb_dst_rdy : std_logic_vector(ETH_PORT_CHAN-1 downto 0);
+
     signal tx_adap_mfb_clk     : std_logic_vector(ETH_PORT_CHAN-1 downto 0) := (others => '0');
     signal tx_adap_mfb_data    : slv_array_t(ETH_PORT_CHAN-1 downto 0)(REGIONS*REGION_SIZE*BLOCK_SIZE*ITEM_WIDTH-1 downto 0);
     signal tx_adap_mfb_crc_err : slv_array_t(ETH_PORT_CHAN-1 downto 0)(REGIONS-1 downto 0);
@@ -1377,6 +1379,10 @@ begin
             mfb2avst_rx_mfb_eof <= RX_MFB_EOF(IT);
         end process;
 
+        -- JC: This assignment/renaming is necessary here to synchronize
+        -- the delta delay (for simulators) between the clock and data signals!
+        RX_MFB_DST_RDY(IT) <= mfb2avst_rx_mfb_dst_rdy(IT);
+
         -- TX adaption
         mfb2avst_i : entity work.TX_MAC_LITE_ADAPTER_AVST_100G
         generic map(
@@ -1394,7 +1400,7 @@ begin
             RX_MFB_EOF     => mfb2avst_rx_mfb_eof,
             RX_MFB_EOF_POS => RX_MFB_EOF_POS(IT),
             RX_MFB_SRC_RDY => RX_MFB_SRC_RDY(IT),
-            RX_MFB_DST_RDY => RX_MFB_DST_RDY(IT),
+            RX_MFB_DST_RDY => mfb2avst_rx_mfb_dst_rdy(IT),
 
             TX_AVST_DATA   => tx_ad_avst_data,
             TX_AVST_SOP    => tx_ad_avst_sop,
diff --git a/core/comp/eth/network_mod/comp/network_mod_core/network_mod_core_ftile.vhd b/core/comp/eth/network_mod/comp/network_mod_core/network_mod_core_ftile.vhd
@@ -212,6 +212,8 @@ architecture FULL of NETWORK_MOD_CORE is
     signal adap_tx_mfb_eof        : slv_array_t(ETH_PORT_CHAN-1 downto 0)(REGIONS-1 downto 0);
     signal adap_tx_mfb_src_rdy    : std_logic_vector(ETH_PORT_CHAN-1 downto 0);
 
+    signal adap_rx_mfb_dst_rdy    : std_logic_vector(ETH_PORT_CHAN-1 downto 0);
+
     begin
 
         mi_splitter_i : entity work.MI_SPLITTER_PLUS_GEN
@@ -820,13 +822,18 @@ architecture FULL of NETWORK_MOD_CORE is
             IN_MFB_EOF_POS    => RX_MFB_EOF_POS(i),
             IN_MFB_ERROR      => (others => '0'),
             IN_MFB_SRC_RDY    => RX_MFB_SRC_RDY(i),
-            IN_MFB_DST_RDY    => RX_MFB_DST_RDY(i),
+            IN_MFB_DST_RDY    => adap_rx_mfb_dst_rdy(i),
             OUT_MAC_DATA      => ftile_tx_adapt_data(i),
             OUT_MAC_INFRAME   => ftile_tx_adapt_inframe(i),
             OUT_MAC_EOP_EMPTY => ftile_tx_adapt_eop_empty(i),
             OUT_MAC_ERROR     => ftile_tx_adapt_error(i),
             OUT_MAC_VALID     => ftile_tx_adapt_valid(i),
             OUT_MAC_READY     => ftile_tx_mac_ready(i)
         );
+
+        -- JC: This dump assignment/renaming is necessary here to synchronize
+        -- the delta delay (for simulators) between the clock and data signals!
+        RX_MFB_DST_RDY(i) <= adap_rx_mfb_dst_rdy(i);
+
     end generate;
 end architecture;
diff --git a/core/comp/eth/network_mod/network_mod.vhd b/core/comp/eth/network_mod/network_mod.vhd
@@ -174,6 +174,8 @@ architecture FULL of NETWORK_MOD is
     signal tx_mfb_src_rdy_i : slv_array_t   (ETH_PORTS-1 downto 0)(ETH_CHANNELS-1 downto 0);
     signal tx_mfb_dst_rdy_i : slv_array_t   (ETH_PORTS-1 downto 0)(ETH_CHANNELS-1 downto 0);
 
+    signal core_rx_mfb_dst_rdy : slv_array_t   (ETH_PORTS-1 downto 0)(ETH_CHANNELS-1 downto 0);
+
     -- Control/Status signals
     signal sig_activity_rx : slv_array_t(ETH_PORTS-1 downto 0)(ETH_CHANNELS-1 downto 0);
     signal sig_activity_tx : slv_array_t(ETH_PORTS-1 downto 0)(ETH_CHANNELS-1 downto 0);
@@ -510,7 +512,7 @@ begin
             RX_MFB_SOF      => tx_mfb_sof_i    (p),
             RX_MFB_EOF      => tx_mfb_eof_i    (p),
             RX_MFB_SRC_RDY  => tx_mfb_src_rdy_i(p),
-            RX_MFB_DST_RDY  => tx_mfb_dst_rdy_i(p),
+            RX_MFB_DST_RDY  => core_rx_mfb_dst_rdy(p),
 
             RX_MVB_CHANNEL   => mvb_ch (p),
             RX_MVB_TIMESTAMP => mvb_ts (p),
@@ -574,6 +576,10 @@ begin
         rx_mfb_crc_err_i <= core_tx_mfb_crc_err;
         rx_mfb_src_rdy_i <= core_tx_mfb_src_rdy;
 
+        -- JC: This assignment/renaming is necessary here to synchronize
+        -- the delta delay (for simulators) between the clock and data signals!
+        tx_mfb_dst_rdy_i <= core_rx_mfb_dst_rdy;
+
         -- =====================================================================
         -- TIMESTAMP synchronization
         -- =====================================================================
diff --git a/core/comp/eth/network_mod/uvm/tbench/base/env/model.sv b/core/comp/eth/network_mod/uvm/tbench/base/env/model.sv
@@ -190,9 +190,9 @@ class model #(string ETH_CORE_ARCH, int unsigned ETH_PORTS, int unsigned ETH_POR
             drop |= error_frame | error_min_tu | error_max_tu | error_crc | error_mac;
 
             case (get_mac_check_mode(index))
-                2'h1: drop |= ~mac_hit_vld;               // ONLY_VALID
-                2'h2: drop |= ~(mac_hit_vld | broadcast); // VALID_AND_BCAST
-                2'h3: drop |= ~(mac_hit_vld | multicast); // VALID_AND_MCAST
+                2'h1: drop |= ~mac_hit_vld;                           // ONLY_VALID
+                2'h2: drop |= ~(mac_hit_vld | broadcast);             // VALID_AND_BCAST
+                2'h3: drop |= ~(mac_hit_vld | broadcast | multicast); // VALID_AND_BCAST_AND_MCAST
             endcase
 
             msg = $sformatf("\n\thdr input time %s", hdr.time2string());
diff --git a/core/comp/eth/network_mod/uvm/tbench/base/env/sequence_mac_check_configuration.sv b/core/comp/eth/network_mod/uvm/tbench/base/env/sequence_mac_check_configuration.sv
@@ -12,10 +12,10 @@ class sequence_mac_check_configuration #(ETH_TX_HDR_WIDTH, ETH_RX_HDR_WIDTH, ITE
     localparam int unsigned RX_MAC_COUNT = 16;
 
     typedef enum bit[2-1 : 0] {
-        ALL_PASS        = 2'h0,
-        ONLY_VALID      = 2'h1,
-        VALID_AND_BCAST = 2'h2,
-        VALID_AND_MCAST = 2'h3
+        ALL_PASS                  = 2'h0,
+        ONLY_VALID                = 2'h1,
+        VALID_AND_BCAST           = 2'h2,
+        VALID_AND_BCAST_AND_MCAST = 2'h3
     } mode_e;
 
     rand mode_e         mode;
