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radek-isaradek-isa
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Merge branch 'marushchenko-feat-uvm-network_module-support_min_and_max_frame_size_configuration' into 'devel'
Add min & max frame size configuration support to the NETWORK MODULE verification See merge request ndk/ndk-fpga!206
2 parents 4d1e169 + 0fdcc54 commit d272d11

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8 files changed

+75
-4
lines changed

8 files changed

+75
-4
lines changed

‎comp/nic/mac_lite/rx_mac_lite/uvm/registers.sv

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -184,7 +184,7 @@ class reg_mtu extends uvm_reg;
184184

185185
//Configure
186186
//rsvd.configure( this, 8, 24, "RW", 0, 8'h00, 1, 1, 0);
187-
length.configure(this, 32, 0, "RW", 0, def_value, 1, 0, 0);
187+
length.configure(this, 16, 0, "RW", 0, def_value, 1, 0, 0);
188188
endfunction
189189
endclass
190190

‎core/comp/eth/network_mod/uvm/tbench/base/env/model.sv

Lines changed: 10 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -172,8 +172,8 @@ class model #(string ETH_CORE_ARCH, int unsigned ETH_PORTS, int unsigned ETH_POR
172172
{dst_mac, src_mac, eth_type} = {>>{data.data[0: (48+48+16)/ITEM_WIDTH-1]}};
173173

174174
error_frame = !is_frame_valid(hdr.data);
175-
error_min_tu = length < 60;
176-
error_max_tu = length > 1526;
175+
error_min_tu = length < get_frame_length_minimum(index);
176+
error_max_tu = length > get_frame_length_maximum(index);
177177
error_crc = 0;
178178
error_mac = 0;
179179
error = error_frame | error_min_tu | error_max_tu | error_crc | error_mac;
@@ -324,4 +324,12 @@ class model #(string ETH_CORE_ARCH, int unsigned ETH_PORTS, int unsigned ETH_POR
324324
return m_rx_mac_regmodel[port_index].channel[0].rx_mac.mac_check.get();
325325
endfunction
326326

327+
function int unsigned get_frame_length_minimum(int unsigned port_index);
328+
return m_rx_mac_regmodel[port_index].channel[0].rx_mac.min.get() - 4; // Substract the CRC
329+
endfunction
330+
331+
function int unsigned get_frame_length_maximum(int unsigned port_index);
332+
return m_rx_mac_regmodel[port_index].channel[0].rx_mac.max.get() - 4; // Substract the CRC
333+
endfunction
334+
327335
endclass

‎core/comp/eth/network_mod/uvm/tbench/base/env/pkg.sv

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -26,6 +26,7 @@ package uvm_network_mod_env;
2626
`include "sequence_eth.sv"
2727
`include "sequence_timestamp.sv"
2828
`include "sequence_mac_check_configuration.sv"
29+
`include "sequence_frame_length_configuration.sv"
2930
`include "sequence.sv"
3031
endpackage
3132
`endif

‎core/comp/eth/network_mod/uvm/tbench/base/env/sequence.sv

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -22,7 +22,8 @@ class virt_sequence_port#(ETH_TX_HDR_WIDTH, ETH_RX_HDR_WIDTH, ITEM_WIDTH, REGION
2222

2323
protected uvm_logic_vector_array::config_sequence usr_rx_seq_cfg;
2424

25-
uvm_network_mod_env::sequence_mac_check_configuration #(ETH_TX_HDR_WIDTH, ETH_RX_HDR_WIDTH, ITEM_WIDTH, REGIONS, REGION_SIZE, BLOCK_SIZE, ETH_PORT_CHAN, MI_DATA_WIDTH, MI_ADDR_WIDTH) m_sequence_mac_check_configuration;
25+
uvm_network_mod_env::sequence_mac_check_configuration #(ETH_TX_HDR_WIDTH, ETH_RX_HDR_WIDTH, ITEM_WIDTH, REGIONS, REGION_SIZE, BLOCK_SIZE, ETH_PORT_CHAN, MI_DATA_WIDTH, MI_ADDR_WIDTH) m_sequence_mac_check_configuration;
26+
uvm_network_mod_env::sequence_frame_length_configuration #(ETH_TX_HDR_WIDTH, ETH_RX_HDR_WIDTH, ITEM_WIDTH, REGIONS, REGION_SIZE, BLOCK_SIZE, ETH_PORT_CHAN, MI_DATA_WIDTH, MI_ADDR_WIDTH) m_sequence_frame_length_configuration;
2627

2728
rand int unsigned transactions_approx;
2829
constraint c_transactions {
@@ -102,6 +103,8 @@ class virt_sequence_port#(ETH_TX_HDR_WIDTH, ETH_RX_HDR_WIDTH, ITEM_WIDTH, REGION
102103

103104
// MAC Check configuration
104105
m_sequence_mac_check_configuration = uvm_network_mod_env::sequence_mac_check_configuration #(ETH_TX_HDR_WIDTH, ETH_RX_HDR_WIDTH, ITEM_WIDTH, REGIONS, REGION_SIZE, BLOCK_SIZE, ETH_PORT_CHAN, MI_DATA_WIDTH, MI_ADDR_WIDTH)::type_id::create("m_sequence_mac_check_configuration");
106+
// Frame lengths configuration
107+
m_sequence_frame_length_configuration = uvm_network_mod_env::sequence_frame_length_configuration #(ETH_TX_HDR_WIDTH, ETH_RX_HDR_WIDTH, ITEM_WIDTH, REGIONS, REGION_SIZE, BLOCK_SIZE, ETH_PORT_CHAN, MI_DATA_WIDTH, MI_ADDR_WIDTH)::type_id::create("m_sequence_frame_length_configuration");
105108

106109
usr_rx_data = lib_usr_rx_data;
107110
usr_rx_meta = lib_usr_rx_meta;

‎core/comp/eth/network_mod/uvm/tbench/base/env/sequence_frame_length_configuration.sv

Lines changed: 50 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,50 @@
1+
// sequence_frame_length_configuration.sv: Configuration sequence for the frame lengths in RX MAC Lite
2+
// Copyright (C) 2025 CESNET z. s. p. o.
3+
// Author(s): Yaroslav Marushchenko <[email protected]>
4+
// SPDX-License-Identifier: BSD-3-Clause
5+
6+
// TODO: Multi-channel support
7+
8+
class sequence_frame_length_configuration #(ETH_TX_HDR_WIDTH, ETH_RX_HDR_WIDTH, ITEM_WIDTH, REGIONS, REGION_SIZE, BLOCK_SIZE, ETH_PORT_CHAN, MI_DATA_WIDTH, MI_ADDR_WIDTH) extends uvm_sequence;
9+
`uvm_object_param_utils(uvm_network_mod_env::sequence_frame_length_configuration #(ETH_TX_HDR_WIDTH, ETH_RX_HDR_WIDTH, ITEM_WIDTH, REGIONS, REGION_SIZE, BLOCK_SIZE, ETH_PORT_CHAN, MI_DATA_WIDTH, MI_ADDR_WIDTH))
10+
`uvm_declare_p_sequencer(uvm_network_mod_env::sequencer_port #(ETH_TX_HDR_WIDTH, ETH_RX_HDR_WIDTH, ITEM_WIDTH, REGIONS, REGION_SIZE, BLOCK_SIZE, ETH_PORT_CHAN, MI_DATA_WIDTH, MI_ADDR_WIDTH))
11+
12+
int unsigned minimum_length_max = 256;
13+
int unsigned minimum_length_min = 60;
14+
15+
rand int unsigned minimum_length;
16+
constraint c_minimum_length {
17+
minimum_length_min <= minimum_length;
18+
minimum_length <= minimum_length_max;
19+
}
20+
21+
int unsigned maximum_length_max = 16384;
22+
int unsigned maximum_length_min = 1500;
23+
24+
rand int unsigned maximum_length;
25+
constraint c_maximum_length {
26+
maximum_length_min <= maximum_length;
27+
maximum_length <= maximum_length_max;
28+
}
29+
30+
// Constructor
31+
function new(string name = "sequence_frame_length_configuration");
32+
super.new(name);
33+
endfunction
34+
35+
task body;
36+
configure_minimum_length();
37+
configure_maximum_length();
38+
endtask
39+
40+
protected virtual task configure_minimum_length();
41+
uvm_status_e status;
42+
p_sequencer.regmodel.channel[0].rx_mac.min.write(status, minimum_length);
43+
endtask
44+
45+
protected virtual task configure_maximum_length();
46+
uvm_status_e status;
47+
p_sequencer.regmodel.channel[0].rx_mac.max.write(status, maximum_length);
48+
endtask
49+
50+
endclass

‎core/comp/eth/network_mod/uvm/tbench/cmac/env/sequence.sv

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -98,6 +98,9 @@ class virt_sequence_port #(
9898
assert(m_sequence_mac_check_configuration.randomize());
9999
m_sequence_mac_check_configuration.start(p_sequencer);
100100

101+
assert(m_sequence_frame_length_configuration.randomize());
102+
m_sequence_frame_length_configuration.start(p_sequencer);
103+
101104
fork
102105
p_sequencer.regmodel.channel[it].rx_mac.enable.write(status, 1'h1);
103106
p_sequencer.regmodel.channel[it].tx_mac.enable.write(status, 1'h1);

‎core/comp/eth/network_mod/uvm/tbench/e-tile/env/sequence.sv

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -85,6 +85,9 @@ class virt_sequence_port #(ETH_TX_HDR_WIDTH, ETH_RX_HDR_WIDTH, ITEM_WIDTH, REGIO
8585
assert(m_sequence_mac_check_configuration.randomize());
8686
m_sequence_mac_check_configuration.start(p_sequencer);
8787

88+
assert(m_sequence_frame_length_configuration.randomize());
89+
m_sequence_frame_length_configuration.start(p_sequencer);
90+
8891
fork
8992
p_sequencer.regmodel.channel[it].rx_mac.enable.write(status, 1'h1);
9093
p_sequencer.regmodel.channel[it].tx_mac.enable.write(status, 1'h1);

‎core/comp/eth/network_mod/uvm/tbench/f-tile/env/sequence.sv

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -96,6 +96,9 @@ class virt_sequence_port #(
9696
assert(m_sequence_mac_check_configuration.randomize());
9797
m_sequence_mac_check_configuration.start(p_sequencer);
9898

99+
assert(m_sequence_frame_length_configuration.randomize());
100+
m_sequence_frame_length_configuration.start(p_sequencer);
101+
99102
fork
100103
p_sequencer.regmodel.channel[it].rx_mac.enable.write(status, 1'h1);
101104
p_sequencer.regmodel.channel[it].tx_mac.enable.write(status, 1'h1);

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