fix: update Makefile / Modules.tcl paths

martinspinler · martinspinler · commit d72fd6754b94 · 2025-07-18T14:41:13.000+02:00
diff --git a/cards/silicom/n6010/src/comp/pmci/synth/Makefile b/cards/silicom/n6010/src/comp/pmci/synth/Makefile
@@ -11,4 +11,4 @@ DEVICE=AGILEX
 .PHONY: all
 all: comp
 
-include ../../../../../../../conf/Makefile
+include ../../../../../../../build/Makefile
diff --git a/comp/base/fifo/asfifo_bram_datamux/dma_fifo_2to1/Modules.tcl b/comp/base/fifo/asfifo_bram_datamux/dma_fifo_2to1/Modules.tcl
@@ -5,11 +5,13 @@
 # SPDX-License-Identifier: BSD-3-Clause
 
 # Base directories
-set ASFIFO_BASE 		"$OFM_PATH/comp/base/fifo/asfifox"
-set PACKAGES            "$OFM_PATH/comp/base/pkg/math_pack.vhd"
+set ASFIFO_BASE     "$OFM_PATH/comp/base/fifo/asfifox"
+lappend PACKAGES    "$OFM_PATH/comp/base/pkg/math_pack.vhd"
+lappend PACKAGES    "$OFM_PATH/comp/base/pkg/dma_bus_pack.vhd"
+
 # List of components
 set COMPONENTS [list \
-                [list "ASFIFO"  $ASFIFO_BASE "FULL"] \
-                ]
+    [list "ASFIFO"  $ASFIFO_BASE "FULL"] \
+]
 set MOD "$MOD $ENTITY_BASE/dma_fifo_2to1_ent.vhd"
 set MOD "$MOD $ENTITY_BASE/dma_fifo_2to1_arch.vhd"
diff --git a/comp/base/logic/sr_sync_latch/synth/Makefile b/comp/base/logic/sr_sync_latch/synth/Makefile
@@ -6,9 +6,7 @@
 
 TOP_LEVEL_ENT=SR_SYNC_LATCH
 
-SYNTH=vivado
 export CLK_PERIOD=2.64
-export DEVICE=ULTRASCALE
 
 all: comp
 include ../../../../../build/Makefile
diff --git a/comp/base/mem/lvt_mem/Modules.tcl b/comp/base/mem/lvt_mem/Modules.tcl
@@ -6,14 +6,15 @@
 
 set GEN_REG_ARRAY_BASE  "$OFM_PATH/comp/base/mem/gen_reg_array"
 set GEN_LUTRAM_BASE     "$OFM_PATH/comp/base/mem/gen_lutram"
-set GEN_LUTRAM_BASE     "$OFM_PATH/comp/base/mem/sdp_bram"
+set GEN_SDP_BRAM_BASE   "$OFM_PATH/comp/base/mem/sdp_bram"
 set GEN_MUX_BASE        "$OFM_PATH/comp/base/logic/mux"
 
-lappend PACKAGES  "$OFM_PATH/comp/base/pkg/type_pack.vhd"
 lappend PACKAGES  "$OFM_PATH/comp/base/pkg/math_pack.vhd"
+lappend PACKAGES  "$OFM_PATH/comp/base/pkg/type_pack.vhd"
 
 lappend COMPONENTS  [list   "GEN_REG_ARRAY"     $GEN_REG_ARRAY_BASE     "FULL"]
 lappend COMPONENTS  [list   "GEN_LUTRAM"        $GEN_LUTRAM_BASE        "FULL"]
+lappend COMPONENTS  [list   "SDP_BRAM"          $GEN_SDP_BRAM_BASE      "FULL"]
 lappend COMPONENTS  [list   "GEN_MUX"           $GEN_MUX_BASE           "FULL"]
 
 lappend MOD "$ENTITY_BASE/lvt_mem.vhd"
diff --git a/comp/base/misc/frequency_meter/synth/Makefile b/comp/base/misc/frequency_meter/synth/Makefile
@@ -4,7 +4,7 @@
 #
 # SPDX-License-Identifier: BSD-3-Clause
 
-TOP_LEVEL_ENT=FREQUENCY_COUNTER
+TOP_LEVEL_ENT=FREQUENCY_METER
 SYNTH=quartus
 
 all: comp
diff --git a/comp/base/misc/pulse_short/synth/Makefile b/comp/base/misc/pulse_short/synth/Makefile
@@ -6,12 +6,8 @@
 
 TOP_LEVEL_ENT=PULSE_SHORT
 
-SYNTH=vivado
 export CLK_PERIOD=2.56
-export DEVICE=ULTRASCALE
-
 
 all: comp
-# the way: ndk/common/build/Makefile
 include ../../../../../build/Makefile
 .PHONY: all
diff --git a/comp/debug/mem_tester/synth/Makefile b/comp/debug/mem_tester/synth/Makefile
@@ -8,5 +8,5 @@ TOP_LEVEL_ENT=MEM_TESTER
 SYNTH=quartus
 
 all: comp
-include ../../../../../ofm/build/Makefile
+include ../../../../build/Makefile
 .PHONY: all
diff --git a/comp/dma/dma_calypte/comp/rx/comp/software_manager/synth/Makefile b/comp/dma/dma_calypte/comp/rx/comp/software_manager/synth/Makefile
@@ -15,4 +15,4 @@ CLK_PERIOD=4.000
 .PHONY: all
 all: comp
 
-include ../../../../../../../../../build/Makefile
+include ../../../../../../../../build/Makefile
diff --git a/comp/dma/dma_calypte/comp/test_core/comp/tx_debug_core/Modules.tcl b/comp/dma/dma_calypte/comp/test_core/comp/tx_debug_core/Modules.tcl
@@ -7,14 +7,18 @@ lappend PACKAGES "$OFM_PATH/comp/base/pkg/math_pack.vhd"
 lappend PACKAGES "$OFM_PATH/comp/base/pkg/type_pack.vhd"
 
 set MFB_FRAME_LNG_BASE  "$OFM_PATH/comp/mfb_tools/logic/frame_lng"
+set MFB_MERGER_BASE     "$OFM_PATH/comp/mfb_tools/flow/merger_simple"
 set MI_ASYNC_BASE       "$OFM_PATH/comp/mi_tools/async"
+set MI_SPLITTER_BASE    "$OFM_PATH/comp/mi_tools/splitter_plus_gen"
 set NP_LUTRAM_BASE      "$OFM_PATH/comp/base/mem/np_lutram"
 set MEMX_COUNTER_BASE   "$OFM_PATH/comp/base/logic/cnt_multi_memx"
 set AUX_SIGNALS_BASE    "$OFM_PATH/comp/mfb_tools/logic/auxiliary_signals"
 set MFB_GENERATOR_BASE  "$OFM_PATH/comp/mfb_tools/debug/generator"
 
 lappend COMPONENTS [ list "MFB_FRAME_LNG"         $MFB_FRAME_LNG_BASE   "FULL" ]
+lappend COMPONENTS [ list "MFB_MERGER_SIMPLE"     "$MFB_MERGER_BASE"    "FULL" ]
 lappend COMPONENTS [ list "MI_ASYNC"              "$MI_ASYNC_BASE"      "FULL" ]
+lappend COMPONENTS [ list "MI_SPLITTER"           "$MI_SPLITTER_BASE"   "FULL" ]
 lappend COMPONENTS [ list "NP_LUTRAM"             "$NP_LUTRAM_BASE"     "FULL" ]
 lappend COMPONENTS [ list "CNT_MULTI_MEMX"        "$MEMX_COUNTER_BASE"  "FULL" ]
 lappend COMPONENTS [ list "MFB_AUXILIARY_SIGNALS" "$AUX_SIGNALS_BASE"   "FULL" ]
diff --git a/comp/mfb_tools/edit/frame_extender/synth/Makefile b/comp/mfb_tools/edit/frame_extender/synth/Makefile
@@ -10,5 +10,5 @@ SYNTH=quartus
 export DEVICE=AGILEX
 
 all: comp
-include ../../../../../../ofm/build/Makefile
+include ../../../../../build/Makefile
 .PHONY: all
diff --git a/comp/mfb_tools/edit/frame_trimmer/synth/Makefile b/comp/mfb_tools/edit/frame_trimmer/synth/Makefile
@@ -10,5 +10,5 @@ SYNTH=quartus
 export DEVICE=AGILEX
 
 all: comp
-include ../../../../../../ofm/build/Makefile
+include ../../../../../build/Makefile
 .PHONY: all
diff --git a/comp/mfb_tools/flow/crossbarx_stream2/synth/Makefile b/comp/mfb_tools/flow/crossbarx_stream2/synth/Makefile
@@ -10,5 +10,5 @@ SYNTH=quartus
 #export DEVICE=AGILEX
 
 all: comp
-include ../../../../../../ofm/build/Makefile
+include ../../../../../build/Makefile
 .PHONY: all
diff --git a/comp/mfb_tools/flow/rate_limiter/synth/Makefile b/comp/mfb_tools/flow/rate_limiter/synth/Makefile
@@ -11,6 +11,6 @@ SYNTH=quartus
 # export DEVICE=AGILEX
 
 all: comp
-include ../../../../../../ofm/build/Makefile
+include ../../../../../build/Makefile
 .PHONY: all
 
diff --git a/comp/mvb_tools/flow/demux/synth/Makefile b/comp/mvb_tools/flow/demux/synth/Makefile
@@ -12,6 +12,6 @@ export DEVICE=STRATIX10
 
 all: comp
 
-include ../../../../../../ofm/build/Makefile
+include ../../../../../build/Makefile
 
 .PHONY: all
diff --git a/comp/mvb_tools/flow/mux/synth/Makefile b/comp/mvb_tools/flow/mux/synth/Makefile
@@ -12,6 +12,6 @@ export DEVICE=STRATIX10
 
 all: comp
 
-include ../../../../../../ofm/build/Makefile
+include ../../../../../build/Makefile
 
 .PHONY: all
diff --git a/comp/pcie/others/hdr_gen/Modules.tcl b/comp/pcie/others/hdr_gen/Modules.tcl
@@ -5,7 +5,8 @@
 # SPDX-License-Identifier: BSD-3-Clause
 
 # Source files for implemented component
-lappend MOD "$ENTITY_BASE/rq_hdr_gen/rq_hdr_gen.vhd"
-lappend MOD "$ENTITY_BASE/cc_hdr_gen/cc_hdr_gen.vhd"
-lappend MOD "$ENTITY_BASE/cq_hdr_deparser/cq_hdr_deparser.vhd"
-lappend MOD "$ENTITY_BASE/rc_hdr_deparser/rc_hdr_deparser.vhd"
+
+lappend COMPONENTS [list "RQ_HDR_GEN"       $ENTITY_BASE/rq_hdr_gen "FULL"]
+lappend COMPONENTS [list "CC_HDR_GEN"       $ENTITY_BASE/cc_hdr_gen "FULL"]
+lappend COMPONENTS [list "CQ_HDR_DEPARSER"  $ENTITY_BASE/cq_hdr_deparser "FULL"]
+lappend COMPONENTS [list "RC_HDR_DEPARSER"  $ENTITY_BASE/rc_hdr_deparser "FULL"]
diff --git a/comp/pcie/others/hdr_gen/cc_hdr_gen/Modules.tcl b/comp/pcie/others/hdr_gen/cc_hdr_gen/Modules.tcl
@@ -0,0 +1,8 @@
+# Modules.tcl: Components include script
+# Copyright (C) 2022 CESNET z. s. p. o.
+# Author(s): Daniel Kriz <xkrizd01@vutbr.cz>
+#
+# SPDX-License-Identifier: BSD-3-Clause
+
+# Source files for implemented component
+lappend MOD "$ENTITY_BASE/cc_hdr_gen.vhd"
diff --git a/comp/pcie/others/hdr_gen/cc_hdr_gen/synth/Makefile b/comp/pcie/others/hdr_gen/cc_hdr_gen/synth/Makefile
@@ -9,4 +9,4 @@ TOP_LEVEL_ENT=PCIE_CC_HDR_GEN
 .PHONY: all
 all: comp
 
-include ../../../../../build/Makefile
+include ../../../../../../build/Makefile
diff --git a/comp/pcie/others/hdr_gen/cq_hdr_deparser/Modules.tcl b/comp/pcie/others/hdr_gen/cq_hdr_deparser/Modules.tcl
@@ -0,0 +1,9 @@
+# Modules.tcl: Components include script
+# Copyright (C) 2022 CESNET z. s. p. o.
+# Author(s): Daniel Kriz <xkrizd01@vutbr.cz>
+#
+# SPDX-License-Identifier: BSD-3-Clause
+
+# Source files for implemented component
+#
+lappend MOD "$ENTITY_BASE/cq_hdr_deparser.vhd"
diff --git a/comp/pcie/others/hdr_gen/cq_hdr_deparser/synth/Makefile b/comp/pcie/others/hdr_gen/cq_hdr_deparser/synth/Makefile
@@ -9,4 +9,4 @@ TOP_LEVEL_ENT=PCIE_CQ_HDR_DEPARSER
 .PHONY: all
 all: comp
 
-include ../../../../../build/Makefile
+include ../../../../../../build/Makefile
diff --git a/comp/pcie/others/hdr_gen/rc_hdr_deparser/Modules.tcl b/comp/pcie/others/hdr_gen/rc_hdr_deparser/Modules.tcl
@@ -0,0 +1,10 @@
+# Modules.tcl: Components include script
+# Copyright (C) 2022 CESNET z. s. p. o.
+# Author(s): Daniel Kriz <xkrizd01@vutbr.cz>
+#
+# SPDX-License-Identifier: BSD-3-Clause
+
+# Source files for implemented component
+
+lappend PACKAGES "$COMP_BASE/base/pkg/math_pack.vhd"
+lappend MOD "$ENTITY_BASE/rc_hdr_deparser.vhd"
diff --git a/comp/pcie/others/hdr_gen/rc_hdr_deparser/synth/Makefile b/comp/pcie/others/hdr_gen/rc_hdr_deparser/synth/Makefile
@@ -9,4 +9,4 @@ TOP_LEVEL_ENT=PCIE_RC_HDR_DEPARSER
 .PHONY: all
 all: comp
 
-include ../../../../../build/Makefile
+include ../../../../../../build/Makefile
diff --git a/comp/pcie/others/hdr_gen/rq_hdr_gen/Modules.tcl b/comp/pcie/others/hdr_gen/rq_hdr_gen/Modules.tcl
@@ -0,0 +1,8 @@
+# Modules.tcl: Components include script
+# Copyright (C) 2022 CESNET z. s. p. o.
+# Author(s): Daniel Kriz <xkrizd01@vutbr.cz>
+#
+# SPDX-License-Identifier: BSD-3-Clause
+
+# Source files for implemented component
+lappend MOD "$ENTITY_BASE/rq_hdr_gen.vhd"
diff --git a/comp/pcie/others/hdr_gen/rq_hdr_gen/synth/Makefile b/comp/pcie/others/hdr_gen/rq_hdr_gen/synth/Makefile
@@ -9,4 +9,4 @@ TOP_LEVEL_ENT=PCIE_RQ_HDR_GEN
 .PHONY: all
 all: comp
 
-include ../../../../../build/Makefile
+include ../../../../../../build/Makefile
diff --git a/core/comp/app/biflow_simple/synth/Makefile b/core/comp/app/biflow_simple/synth/Makefile
@@ -10,5 +10,5 @@ SYNTH=quartus
 #export DEVICE=AGILEX
 
 all: comp
-include ../../../../../../../ofm/build/Makefile
+include ../../../../../build/Makefile
 .PHONY: all
diff --git a/core/comp/app/dma_chan_mod/synth/Makefile b/core/comp/app/dma_chan_mod/synth/Makefile
@@ -10,5 +10,5 @@ SYNTH=quartus
 #export DEVICE=AGILEX
 
 all: comp
-include ../../../../../../../ofm/build/Makefile
+include ../../../../../build/Makefile
 .PHONY: all
diff --git a/core/comp/app/dma_streams_merger/synth/Makefile b/core/comp/app/dma_streams_merger/synth/Makefile
@@ -10,5 +10,5 @@ SYNTH=quartus
 #export DEVICE=AGILEX
 
 all: comp
-include ../../../../../../../ofm/build/Makefile
+include ../../../../../build/Makefile
 .PHONY: all
diff --git a/core/comp/eth/network_mod/comp/network_mod_core/synth/Makefile b/core/comp/eth/network_mod/comp/network_mod_core/synth/Makefile
@@ -11,5 +11,5 @@ SYNTH=quartus
 #export DEVICE=AGILEX
 
 all: comp
-include ../../../../../../../../ofm/build/Makefile
+include ../../../../../../../build/Makefile
 .PHONY: all
diff --git a/core/comp/eth/network_mod/comp/network_mod_logic/synth/Makefile b/core/comp/eth/network_mod/comp/network_mod_logic/synth/Makefile
@@ -10,5 +10,5 @@ SYNTH=quartus
 #export DEVICE=AGILEX
 
 all: comp
-include ../../../../../../../../ofm/build/Makefile
+include ../../../../../../../build/Makefile
 .PHONY: all
diff --git a/core/comp/eth/network_mod/synth/Makefile b/core/comp/eth/network_mod/synth/Makefile
@@ -11,5 +11,5 @@ SYNTH=quartus
 # export DEVICE=AGILEX
 
 all: comp
-include ../../../../../../ofm/build/Makefile
+include ../../../../../build/Makefile
 .PHONY: all
diff --git a/core/comp/pcie/pcie_mod/comp/pcie_adapter/synth/Makefile b/core/comp/pcie/pcie_mod/comp/pcie_adapter/synth/Makefile
@@ -9,4 +9,4 @@ TOP_LEVEL_ENT=PCIE_ADAPTER
 .PHONY: all
 all: comp
 
-include ../../../../../../../../../conf/Makefile
+include ../../../../../../../build/Makefile
diff --git a/core/comp/pcie/pcie_mod/comp/pcie_ctrl/synth/Makefile b/core/comp/pcie/pcie_mod/comp/pcie_ctrl/synth/Makefile
@@ -9,4 +9,4 @@ TOP_LEVEL_ENT=PCIE_CTRL
 .PHONY: all
 all: comp
 
-include ../../../../../../../../../conf/Makefile
+include ../../../../../../../build/Makefile

Original file line number	Diff line number	Diff line change
`@@ -4,7 +4,7 @@`
`4`	`4`	`#`
`5`	`5`	`# SPDX-License-Identifier: BSD-3-Clause`
`6`	`6`
`7`		`-TOP_LEVEL_ENT=FREQUENCY_COUNTER`
	`7`	`+TOP_LEVEL_ENT=FREQUENCY_METER`
`8`	`8`	`SYNTH=quartus`
`9`	`9`
`10`	`10`	`all: comp`