Update the README.md with information about changes made for CHERIoT

support.

Author: Colin

README.md

@@ -1,12 +1,16 @@
-[![Build Status](https://travis-ci.com/pulp-platform/riscv-dbg.svg?branch=master)](https://travis-ci.com/pulp-platform/riscv-dbg)
 
-# RISC-V Debug Support for PULP Cores
+# RISC-V Debug Support for CHERIoT Ibex
 
 This module is an implementation of a debug unit compliant with the [RISC-V
 debug specification](https://github.com/riscv/riscv-debug-spec) v0.13.1. It is
-used in the [Ariane](https://github.com/pulp-platform/ariane) and
+a fork of the PULP Platform debug module which is used for the 
+[Ariane](https://github.com/pulp-platform/ariane) and
 [RI5CY](https://github.com/pulp-platform/riscv) cores.
 
+To be compatible with the CHERIoT Ibex core the debug ROM and abstract command
+implementation have been modified to replace the RV32I ISA instructions with
+thier CHERIoT ISA equivilents. This work was done by SCI Semicondcutor.
+
 ## Implementation
 We use an execution-based technique, also described in the specification, where
 the core is running in a "park loop". Depending on the request made to the debug
@@ -19,6 +23,7 @@ debugging.
 The following features are currently supported
 
 * Parametrizable buswidth for `XLEN=32` `XLEN=64` cores
+  Note: CHERIoT is XLEN=32 only.
 * Accessing registers over abstract command
 * Program buffer
 * System bus access (only `XLEN`)