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ca0132_dsp_functions.c
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/*
* ca0132_dsp_functions.c:
* Contains basic functions for DSP program assembly/disassembly, and
* definitions for DSP opcode values.
*/
#include "ca0132_defs.h"
static const char *dsp_reg_str[] =
{
/* Main registers, or 'local_hw_reg'. */
"R00", "R01", "R02", "R03",
"R04", "R05", "R06", "R07",
"R08", "R09", "R10", "R11",
"R12", "R13", "R14", "R15",
/*
* Address registers.
*/
"A_R0", "A_R1", "A_R2", "A_R3",
"A_R4", "A_R5", "A_R6", "A_R7",
"A_R0_MDFR", "A_R1_MDFR", "A_R2_MDFR", "A_R3_MDFR",
"A_R4_MDFR", "A_R5_MDFR", "A_R6_MDFR", "A_R7_MDFR",
/*
* Constant value registers. Some of
* these are shared with the emu10k1's
* constant registers.
*/
"CR_0x00000000", "CR_0x00000001", "CR_0x00000002", "CR_0x00000003",
"CR_0x00000004", "CR_0x00000008", "CR_0x00000010", "CR_0x00000020",
"CR_0x00000100", "CR_0x00010000", "CR_0x00000800", "CR_0x10000000",
"CR_0x20000000", "CR_F_2", "CR_0x80000000", "CR_0x7fffffff",
"CR_0xffffffff", "CR_0xfffffffe", "CR_0xc0000000", "CR_0x4f1bbcdc",
"CR_0x5a7ef9db", "CR_0x00100000", "CR_0x2d413ccd", "CR_0x80000001",
"CR_0x08000000", "CR_0x02000000", "CR_0x00800000", "CR_0x00200000",
"CR_0x00080000", "CR_0x0000001f", "CR_0x0000000f", "CR_0x00000007",
/*
* These are floating point based
* constants.
*/
"CR_0x00000006", "CR_0x00000005", "CR_F_PI", "CR_F_PI_DIV_2",
"CR_F_PI_DIV_4", "CR_F_1_DIV_PI", "CR_F_1_DIV_2PI", "CR_F_0.5",
"CR_F_1", "CR_F_NEG_1", "CR_F_3", "CR_F_SQRT_0.5",
"CR_DSP_ID", "CR_B1_13", "CR_B1_14", "CR_B1_15",
"CR_B1_16", "CR_B1_17", "CR_B1_18", "CR_B1_19",
"CR_B1_20", "CR_B1_21", "CR_B1_22", "CR_B1_23",
"TIME0_PER_ENB", "TIME0_COUNTER", "TIME1_PER_ENB", "TIME1_COUNTER",
"TIME2_PER_ENB", "TIME2_COUNTER", "TIME3_PER_ENB", "TIME3_COUNTER",
/*
* Indirect address register r/w
* registers.
*/
"@A_R0_X_REG", "@A_R0_Y_REG", "@A_R1_X_REG", "@A_R1_Y_REG",
"@A_R2_X_REG", "@A_R2_Y_REG", "@A_R3_X_REG", "@A_R3_Y_REG",
"@A_R4_X_REG", "@A_R4_Y_REG", "@A_R5_X_REG", "@A_R5_Y_REG",
"@A_R6_X_REG", "@A_R6_Y_REG", "@A_R7_X_REG", "@A_R7_Y_REG",
"@A_R0_X_INC_REG", "@A_R0_Y_INC_REG", "@A_R1_X_INC_REG", "@A_R1_Y_INC_REG",
"@A_R2_X_INC_REG", "@A_R2_Y_INC_REG", "@A_R3_X_INC_REG", "@A_R3_Y_INC_REG",
"@A_R4_X_INC_REG", "@A_R4_Y_INC_REG", "@A_R5_X_INC_REG", "@A_R5_Y_INC_REG",
"@A_R6_X_INC_REG", "@A_R6_Y_INC_REG", "@A_R7_X_INC_REG", "@A_R7_Y_INC_REG",
/*
* First bank of 32 DSP status related
* registers.
* 128.
*/
"COND_REG", "STACK_FLAG_REG", "PC_STK_PTR", "SR_B0_04_UNK",
"CUR_LOOP_ADR_REG", "CUR_LOOP_CNT_REG", "TOP_LOOP_CNT_ST_REG", "TOP_LOOP_COUNT_ADR_REG",
"LOOP_STACK_PTR", "STA_S_STACK_DATA", "STA_S_STACK_PTR", "PROG_CNT_REG",
"SR_B0_12_UNK", "SR_B0_13_UNK", "SR_B0_14_UNK", "SR_B0_15_UNK",
"SR_B0_16_UNK", "SR_B0_17_UNK", "SR_B0_18_UNK", "SR_B0_19_UNK",
"SR_B0_20_UNK", "SR_B0_21_UNK", "SR_B0_22_UNK", "SR_B0_23_UNK",
"SR_B0_24_UNK", "SR_B0_25_UNK", "SR_B0_26_UNK", "SR_B0_27_UNK",
"SR_B0_28_UNK", "SR_B0_29_UNK", "SR_B0_30_UNK", "SR_B0_31_UNK",
/*
* Bank 1. Includes xyram_ag_index/gpio
* registers.
*/
"SR_B1_00_UNK", "SR_B1_01_UNK", "SR_B1_02_UNK", "SR_B1_03_UNK",
"SR_B1_04_UNK", "SR_B1_05_UNK", "SR_B1_06_UNK", "SR_B1_07_UNK",
"A_R0_BASE", "A_R1_BASE", "A_R2_BASE", "A_R3_BASE",
"A_R4_BASE", "A_R5_BASE", "A_R6_BASE", "A_R7_BASE",
"A_R0_LENG", "A_R1_LENG", "A_R2_LENG", "A_R3_LENG",
"A_R4_LENG", "A_R5_LENG", "A_R6_LENG", "A_R7_LENG",
"SEMAPHORE_G_REG", "INT_CONT_MASK_REG", "INT_CONT_PEND_REG", "INT_CONT_SERV_REG",
"SR_B1_28_UNK", "SR_B1_29_UNK", "SR_B1_30_UNK", "GPIO_REG",
/*
* Bank 2. DSP DMA Registers. On ca0132
* these are mapped to HIC addresses
* 0x110000-0x111000.
*/
"DMACFG_0_REG", "DMA_ADR_OFS_0_REG", "DMA_XFR_CNT_0_REG", "DMA_IRQ_CNT_0_REG",
"DMACFG_1_REG", "DMA_ADR_OFS_1_REG", "DMA_XFR_CNT_1_REG", "DMA_IRQ_CNT_1_REG",
"DMACFG_2_REG", "DMA_ADR_OFS_2_REG", "DMA_XFR_CNT_2_REG", "DMA_IRQ_CNT_2_REG",
"DMACFG_3_REG", "DMA_ADR_OFS_3_REG", "DMA_XFR_CNT_3_REG", "DMA_IRQ_CNT_3_REG",
"DMACFG_4_REG", "DMA_ADR_OFS_4_REG", "DMA_XFR_CNT_4_REG", "DMA_IRQ_CNT_4_REG",
"DMACFG_5_REG", "DMA_ADR_OFS_5_REG", "DMA_XFR_CNT_5_REG", "DMA_IRQ_CNT_5_REG",
"DMACFG_6_REG", "DMA_ADR_OFS_6_REG", "DMA_XFR_CNT_6_REG", "DMA_IRQ_CNT_6_REG",
"DMACFG_7_REG", "DMA_ADR_OFS_7_REG", "DMA_XFR_CNT_7_REG", "DMA_IRQ_CNT_7_REG",
/*
* Bank 3. Continuation of DSP DMA
* registers.
*/
"DMACFG_8_REG", "DMA_ADR_OFS_8_REG", "DMA_XFR_CNT_8_REG", "DMA_IRQ_CNT_8_REG",
"DMACFG_9_REG", "DMA_ADR_OFS_9_REG", "DMA_XFR_CNT_9_REG", "DMA_IRQ_CNT_9_REG",
"DMACFG_A_REG", "DMA_ADR_OFS_A_REG", "DMA_XFR_CNT_A_REG", "DMA_IRQ_CNT_A_REG",
"DMACFG_B_REG", "DMA_ADR_OFS_B_REG", "DMA_XFR_CNT_B_REG", "DMA_IRQ_CNT_B_REG",
"DMACFG_CH_SEL_0_REG", "DMACFG_CH_SEL_1_REG", "DMACFG_CH_SEL_2_REG", "DMACFG_CH_SEL_3_REG",
"DMACFG_CH_SEL_4_REG", "DMACFG_CH_SEL_5_REG", "DMACFG_CH_SEL_6_REG", "DMACFG_CH_SEL_7_REG",
"DMACFG_CH_SEL_8_REG", "DMACFG_CH_SEL_9_REG", "DMACFG_CH_SEL_A_REG", "DMACFG_CH_SEL_B_REG",
"DMACFG_CH_START_REG", "DMACFG_CH_STAT_REG", "DMACFG_CH_PROP_REG", "DMACFG_ACTIVE_REG",
};
const char *get_dsp_operand_str(uint32_t reg_val)
{
return dsp_reg_str[reg_val];
}
/*
* Check the DSP register strings for a match, and if one is found,
* return the value.
*/
uint32_t get_dsp_operand_str_val(char *operand, uint32_t *val)
{
uint32_t i;
for (i = 0; i < ARRAY_SIZE(dsp_reg_str); i++) {
if (!strcmp(dsp_reg_str[i], operand)) {
*val = i;
return 1;
}
}
return 0;
}
static const op_operand_layout p_operand_layouts[] = {
/*
* P_OP_LAYOUT_MOV_2:
*/
{ .loc_layouts = {
{ .layout_val_loc = {
.part1_bit_start = 0,
.part1_bits = 0 },
.layout_val = 0x00,
.operand_cnt = 2,
.operand_loc = {
{ .part1_bit_start = 23,
.part1_bits = 4,
.operand_type = OP_OPERAND_REG_4,
.operand_dir = OPERAND_DIR_DST, },
{ .part1_bit_start = 17,
.part1_bits = 4,
.operand_type = OP_OPERAND_REG_4,
.operand_dir = OPERAND_DIR_SRC, } },
.bitmask = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, } } },
.loc_layout_cnt = 1, },
/*
* P_OP_LAYOUT_MOVX_2:
*/
{ .loc_layouts = {
{ .layout_val_loc = {
.part1_bit_start = 16,
.part1_bits = 1 },
.layout_val = 0x00,
.operand_cnt = 2,
.operand_loc = {
{ .part1_bit_start = 17,
.part1_bits = 4,
.operand_type = OP_OPERAND_REG_4,
.operand_dir = OPERAND_DIR_DST, },
{ .part1_bit_start = 15,
.part1_bits = 1,
.part2_bit_start = 21,
.part2_bits = 3,
.operand_type = OP_OPERAND_A_REG,
.operand_dir = OPERAND_DIR_SRC, } },
.bitmask = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, } },
{ .layout_val_loc = {
.part1_bit_start = 16,
.part1_bits = 1 },
.layout_val = 0x1,
.operand_cnt = 2,
.operand_loc = {
{ .part1_bit_start = 17,
.part1_bits = 4,
.operand_type = OP_OPERAND_REG_4,
.operand_dir = OPERAND_DIR_DST, },
{ .part1_bit_start = 15,
.part1_bits = 1,
.part2_bit_start = 21,
.part2_bits = 6,
.operand_type = OP_OPERAND_A_REG_PLUS_MDFR,
.operand_dir = OPERAND_DIR_SRC, } },
.bitmask = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, } } },
.loc_layout_cnt = 2, },
/*
* P_OP_LAYOUT_MOVX_DUAL_READ_2:
*/
{ .loc_layouts = {
{ .layout_val_loc = {
.part1_bit_start = 16,
.part1_bits = 1 },
.layout_val = 0x00,
.operand_cnt = 4,
.operand_loc = {
{ .part1_bit_start = 20,
.part1_bits = 4,
.operand_type = OP_OPERAND_REG_4,
.operand_dir = OPERAND_DIR_DST, },
{ .part1_bit_start = 13,
.part1_bits = 3,
.operand_type = OP_OPERAND_A_REG_X,
.operand_dir = OPERAND_DIR_SRC,
.parallel_end = 1, },
{ .part1_bit_start = 24,
.part1_bits = 4,
.operand_type = OP_OPERAND_REG_4,
.operand_dir = OPERAND_DIR_DST, },
{ .part1_bit_start = 17,
.part1_bits = 3,
.operand_type = OP_OPERAND_A_REG_Y,
.operand_dir = OPERAND_DIR_SRC, } },
.bitmask = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, } },
{ .layout_val_loc = {
.part1_bit_start = 16,
.part1_bits = 1 },
.layout_val = 0x1,
.operand_cnt = 4,
.operand_loc = {
{ .part1_bit_start = 20,
.part1_bits = 4,
.operand_type = OP_OPERAND_REG_4,
.operand_dir = OPERAND_DIR_DST, },
{ .part1_bit_start = 13,
.part1_bits = 3,
.operand_type = OP_OPERAND_A_REG_X_INC,
.operand_dir = OPERAND_DIR_SRC,
.parallel_end = 1, },
{ .part1_bit_start = 24,
.part1_bits = 4,
.operand_type = OP_OPERAND_REG_4,
.operand_dir = OPERAND_DIR_DST, },
{ .part1_bit_start = 17,
.part1_bits = 3,
.operand_type = OP_OPERAND_A_REG_Y_INC,
.operand_dir = OPERAND_DIR_SRC, } },
.bitmask = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, } } },
.loc_layout_cnt = 2, },
/*
* P_OP_LAYOUT_MOVX_DUAL_WRITE_2:
*/
{ .loc_layouts = {
{ .layout_val_loc = {
.part1_bit_start = 24,
.part1_bits = 1 },
.layout_val = 0x00,
.operand_cnt = 4,
.operand_loc = {
{ .part1_bit_start = 21,
.part1_bits = 3,
.operand_type = OP_OPERAND_A_REG_X,
.operand_dir = OPERAND_DIR_DST, },
{ .part1_bit_start = 12,
.part1_bits = 4,
.operand_type = OP_OPERAND_REG_4,
.operand_dir = OPERAND_DIR_SRC,
.parallel_end = 1, },
{ .part1_bit_start = 25,
.part1_bits = 3,
.operand_type = OP_OPERAND_A_REG_Y,
.operand_dir = OPERAND_DIR_DST, },
{ .part1_bit_start = 16,
.part1_bits = 4,
.operand_type = OP_OPERAND_REG_4,
.operand_dir = OPERAND_DIR_SRC, } },
.bitmask = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, } },
{ .layout_val_loc = {
.part1_bit_start = 24,
.part1_bits = 1 },
.layout_val = 0x1,
.operand_cnt = 4,
.operand_loc = {
{ .part1_bit_start = 21,
.part1_bits = 3,
.operand_type = OP_OPERAND_A_REG_X_INC,
.operand_dir = OPERAND_DIR_DST, },
{ .part1_bit_start = 12,
.part1_bits = 4,
.operand_type = OP_OPERAND_REG_4,
.operand_dir = OPERAND_DIR_SRC,
.parallel_end = 1, },
{ .part1_bit_start = 25,
.part1_bits = 3,
.operand_type = OP_OPERAND_A_REG_Y_INC,
.operand_dir = OPERAND_DIR_DST, },
{ .part1_bit_start = 16,
.part1_bits = 4,
.operand_type = OP_OPERAND_REG_4,
.operand_dir = OPERAND_DIR_SRC, } },
.bitmask = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, } } },
.loc_layout_cnt = 2, },
/*
* P_OP_LAYOUT_EXECUTE_COND_2:
*/
{ .loc_layouts = {
{ .layout_val_loc = {
.part1_bit_start = 16,
.part1_bits = 0 },
.layout_val = 0x00,
.operand_cnt = 1,
.operand_loc = {
{ .part1_bit_start = 20,
.part1_bits = 8,
.operand_type = OP_OPERAND_LITERAL_8,
.operand_dir = OPERAND_DIR_NONE, } },
.supports_opt_args = 0,
.bitmask = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, } } },
.loc_layout_cnt = 1, },
/*
* P_OP_LAYOUT_MOV_4:
*/
{ .loc_layouts = {
{ .layout_val_loc = {
.part1_bit_start = 0,
.part1_bits = 0 },
.layout_val = 0x00,
.operand_cnt = 2,
.operand_loc = {
{ .part1_bit_start = 24,
.part1_bits = 4,
.operand_type = OP_OPERAND_REG_4,
.operand_dir = OPERAND_DIR_DST, },
{ .part1_bit_start = 18,
.part1_bits = 4,
.operand_type = OP_OPERAND_REG_4,
.operand_dir = OPERAND_DIR_SRC, } },
.bitmask = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, } } },
.loc_layout_cnt = 1, },
/*
* P_OP_LAYOUT_MOV_DUAL_4:
*/
{ .loc_layouts = {
{ .layout_val_loc = {
.part1_bit_start = 0,
.part1_bits = 0 },
.layout_val = 0x00,
.operand_cnt = 4,
.operand_loc = {
{ .part1_bit_start = 26,
.part1_bits = 4,
.operand_type = OP_OPERAND_REG_4,
.operand_dir = OPERAND_DIR_DST, },
{ .part1_bit_start = 16,
.part1_bits = 4,
.operand_type = OP_OPERAND_REG_4,
.operand_dir = OPERAND_DIR_SRC,
.parallel_end = 1, },
{ .part1_bit_start = 32,
.part1_bits = 4,
.operand_type = OP_OPERAND_REG_4,
.operand_dir = OPERAND_DIR_DST, },
{ .part1_bit_start = 20,
.part1_bits = 4,
.operand_type = OP_OPERAND_REG_4,
.operand_dir = OPERAND_DIR_SRC, } },
.bitmask = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, } } },
.loc_layout_cnt = 1, },
/*
* P_OP_LAYOUT_MOVX_4:
*/
{ .loc_layouts = {
{ .layout_val_loc = {
.part1_bit_start = 17,
.part1_bits = 1 },
.layout_val = 0x00,
.operand_cnt = 2,
.operand_loc = {
{ .part1_bit_start = 18,
.part1_bits = 4,
.operand_type = OP_OPERAND_REG_4,
.operand_dir = OPERAND_DIR_DST, },
{ .part1_bit_start = 16,
.part1_bits = 1,
.part2_bit_start = 22,
.part2_bits = 3,
.operand_type = OP_OPERAND_A_REG,
.operand_dir = OPERAND_DIR_SRC, } },
.bitmask = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, } },
{ .layout_val_loc = {
.part1_bit_start = 17,
.part1_bits = 1 },
.layout_val = 0x1,
.operand_cnt = 2,
.operand_loc = {
{ .part1_bit_start = 18,
.part1_bits = 4,
.operand_type = OP_OPERAND_REG_4,
.operand_dir = OPERAND_DIR_DST, },
{ .part1_bit_start = 16,
.part1_bits = 1,
.part2_bit_start = 22,
.part2_bits = 6,
.operand_type = OP_OPERAND_A_REG_PLUS_MDFR,
.operand_dir = OPERAND_DIR_SRC, } },
.bitmask = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, } } },
.loc_layout_cnt = 2, },
/*
* P_OP_LAYOUT_MOVX_DUAL_4:
*/
{ .loc_layouts = {
{ .layout_val_loc = {
.part1_bit_start = 15,
.part1_bits = 1 },
.layout_val = 0x00,
.operand_cnt = 4,
.operand_loc = {
{ .part1_bit_start = 16,
.part1_bits = 4,
.operand_type = OP_OPERAND_REG_4,
.operand_dir = OPERAND_DIR_DST, },
{ .part1_bit_start = 24,
.part1_bits = 3,
.operand_type = OP_OPERAND_A_REG_X,
.operand_dir = OPERAND_DIR_SRC,
.parallel_end = 1, },
{ .part1_bit_start = 20,
.part1_bits = 4,
.operand_type = OP_OPERAND_REG_4,
.operand_dir = OPERAND_DIR_DST, },
{ .part1_bit_start = 30,
.part1_bits = 3,
.operand_type = OP_OPERAND_A_REG_Y,
.operand_dir = OPERAND_DIR_SRC, } },
.bitmask = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, } },
{ .layout_val_loc = {
.part1_bit_start = 15,
.part1_bits = 1 },
.layout_val = 0x1,
.operand_cnt = 4,
.operand_loc = {
{ .part1_bit_start = 16,
.part1_bits = 4,
.operand_type = OP_OPERAND_REG_4,
.operand_dir = OPERAND_DIR_DST, },
{ .part1_bit_start = 24,
.part1_bits = 6,
.operand_type = OP_OPERAND_A_REG_X_PLUS_MDFR,
.operand_dir = OPERAND_DIR_SRC,
.parallel_end = 1, },
{ .part1_bit_start = 20,
.part1_bits = 4,
.operand_type = OP_OPERAND_REG_4,
.operand_dir = OPERAND_DIR_DST, },
{ .part1_bit_start = 30,
.part1_bits = 6,
.operand_type = OP_OPERAND_A_REG_Y_PLUS_MDFR,
.operand_dir = OPERAND_DIR_SRC, } },
.bitmask = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, } } },
.loc_layout_cnt = 2, },
/*
* P_OP_LAYOUT_MOVX_READ_X_WRITE_Y_4:
*/
{ .loc_layouts = {
{ .layout_val_loc = {
.part1_bit_start = 15,
.part1_bits = 1 },
.layout_val = 0x00,
.operand_cnt = 4,
.operand_loc = {
{ .part1_bit_start = 16,
.part1_bits = 4,
.operand_type = OP_OPERAND_REG_4,
.operand_dir = OPERAND_DIR_DST, },
{ .part1_bit_start = 24,
.part1_bits = 3,
.operand_type = OP_OPERAND_A_REG_X,
.operand_dir = OPERAND_DIR_SRC,
.parallel_end = 1, },
{ .part1_bit_start = 30,
.part1_bits = 3,
.operand_type = OP_OPERAND_A_REG_Y,
.operand_dir = OPERAND_DIR_DST, },
{ .part1_bit_start = 20,
.part1_bits = 4,
.operand_type = OP_OPERAND_REG_4,
.operand_dir = OPERAND_DIR_SRC, } },
.bitmask = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, } },
{ .layout_val_loc = {
.part1_bit_start = 15,
.part1_bits = 1 },
.layout_val = 0x1,
.operand_cnt = 4,
.operand_loc = {
{ .part1_bit_start = 16,
.part1_bits = 4,
.operand_type = OP_OPERAND_REG_4,
.operand_dir = OPERAND_DIR_DST, },
{ .part1_bit_start = 24,
.part1_bits = 6,
.operand_type = OP_OPERAND_A_REG_X_PLUS_MDFR,
.operand_dir = OPERAND_DIR_SRC,
.parallel_end = 1, },
{ .part1_bit_start = 30,
.part1_bits = 6,
.operand_type = OP_OPERAND_A_REG_Y_PLUS_MDFR,
.operand_dir = OPERAND_DIR_DST, },
{ .part1_bit_start = 20,
.part1_bits = 4,
.operand_type = OP_OPERAND_REG_4,
.operand_dir = OPERAND_DIR_SRC, } },
.bitmask = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, } } },
.loc_layout_cnt = 2, },
/*
* P_OP_LAYOUT_EXECUTE_COND_4:
*/
{ .loc_layouts = {
{ .layout_val_loc = {
.part1_bit_start = 16,
.part1_bits = 2, },
.layout_val = 0x02,
.operand_cnt = 2,
.operand_loc = {
{ .part1_bit_start = 28,
.part1_bits = 8,
.operand_type = OP_OPERAND_LITERAL_8,
.operand_dir = OPERAND_DIR_NONE,
.parallel_end = 1, },
{ .part1_bit_start = 20,
.part1_bits = 8,
.operand_type = OP_OPERAND_LITERAL_8,
.operand_dir = OPERAND_DIR_NONE, } },
.supports_opt_args = 1,
.bitmask = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, } } },
.loc_layout_cnt = 1, },
};
const op_operand_layout *get_p_op_layout(uint32_t layout_id)
{
if (layout_id < ARRAY_SIZE(p_operand_layouts))
return &p_operand_layouts[layout_id];
else
return NULL;
}
static const dsp_op_info parallel_2_asm_ops[] = {
{ .op_str = "MOVX_P",
.op = 0x10,
.layout_id = { P_OP_LAYOUT_MOVX_DUAL_READ_2 },
.mdfr_bit = 12,
.mdfr_bit_type = OP_MDFR_BIT_TYPE_USE_ALT_STR,
.alt_op_str = "MOVX_T1_P",
},
{ .op_str = "MOVX_T1_P",
.op = 0x20,
.layout_id = { P_OP_LAYOUT_MOVX_DUAL_WRITE_2 },
.mdfr_bit = 20,
.alt_op_str = "MOVX_P",
.mdfr_bit_type = OP_MDFR_BIT_TYPE_USE_ALT_STR,
},
{ .op_str = "MOV_T1_P",
.op = 0x30,
.layout_id = { P_OP_LAYOUT_MOV_2 },
.mdfr_bit = 16,
.alt_op_str = "MOV_P",
.mdfr_bit_type = OP_MDFR_BIT_TYPE_USE_ALT_STR,
},
{ .op_str = "MOVX_P",
.op = 0x32,
.layout_id = { P_OP_LAYOUT_MOVX_2 },
},
{ .op_str = "MOVX_P",
.op = 0x33,
.layout_id = { P_OP_LAYOUT_MOVX_2 },
},
{ .op_str = "MOVX_T1_P",
.op = 0x34,
.layout_id = { P_OP_LAYOUT_MOVX_2 },
},
{ .op_str = "MOVX_T1_P",
.op = 0x35,
.layout_id = { P_OP_LAYOUT_MOVX_2 },
},
{ .op_str = "MOVX_P",
.op = 0x3a,
.layout_id = { P_OP_LAYOUT_MOVX_2 },
.src_dst_swap = 1,
},
{ .op_str = "MOVX_P",
.op = 0x3b,
.layout_id = { P_OP_LAYOUT_MOVX_2 },
.src_dst_swap = 1,
},
{ .op_str = "MOVX_T1_P",
.op = 0x3c,
.layout_id = { P_OP_LAYOUT_MOVX_2 },
.src_dst_swap = 1,
},
{ .op_str = "MOVX_T1_P",
.op = 0x3d,
.layout_id = { P_OP_LAYOUT_MOVX_2 },
.src_dst_swap = 1,
},
{ .op_str = "EXEC_COND_P",
.op = 0x3f,
.layout_id = { P_OP_LAYOUT_EXECUTE_COND_2 },
},
};
static const dsp_op_info parallel_4_asm_ops[] = {
{ .op_str = "MOV_P",
.op = 0x20,
.layout_id = { P_OP_LAYOUT_MOV_DUAL_4 },
.src_dst_swap = 0,
},
/* 0x00c9 move behavior. */
{ .op_str = "MOVX_T1_P",
.op = 0x24,
.layout_id = { P_OP_LAYOUT_MOVX_READ_X_WRITE_Y_4 },
.src_dst_swap = 0,
},
{ .op_str = "MOVX_T1_P",
.op = 0x25,
.layout_id = { P_OP_LAYOUT_MOVX_READ_X_WRITE_Y_4 },
.src_dst_swap = 0,
},
/* 0x00c8 move behavior. */
{ .op_str = "MOVX_P",
.op = 0x26,
.layout_id = { P_OP_LAYOUT_MOVX_READ_X_WRITE_Y_4 },
.src_dst_swap = 0,
},
{ .op_str = "MOVX_P",
.op = 0x27,
.layout_id = { P_OP_LAYOUT_MOVX_READ_X_WRITE_Y_4 },
.src_dst_swap = 0,
},
/* No increment. */
{ .op_str = "MOVX_T1_P",
.op = 0x28,
.layout_id = { P_OP_LAYOUT_MOVX_DUAL_4 },
.src_dst_swap = 0,
},
/* Increment, but 0x00c9 type reg read. */
{ .op_str = "MOVX_T1_P",
.op = 0x29,
.layout_id = { P_OP_LAYOUT_MOVX_DUAL_4 },
.src_dst_swap = 0,
},
/* Increment, with regular 0x00c8 reg read. */
{ .op_str = "MOVX_P",
.op = 0x2b,
.layout_id = { P_OP_LAYOUT_MOVX_DUAL_4 },
.src_dst_swap = 0,
},
/* 0x00c9 move behavior. */
{ .op_str = "MOVX_T1_P",
.op = 0x2c,
.layout_id = { P_OP_LAYOUT_MOVX_READ_X_WRITE_Y_4 },
.src_dst_swap = 1,
},
{ .op_str = "MOVX_T1_P",
.op = 0x2d,
.layout_id = { P_OP_LAYOUT_MOVX_READ_X_WRITE_Y_4 },
.src_dst_swap = 1,
},
/* 0x00c8 move behavior. */
{ .op_str = "MOVX_P",
.op = 0x2e,
.layout_id = { P_OP_LAYOUT_MOVX_READ_X_WRITE_Y_4 },
.src_dst_swap = 1,
},
{ .op_str = "MOVX_P",
.op = 0x2f,
.layout_id = { P_OP_LAYOUT_MOVX_READ_X_WRITE_Y_4 },
.src_dst_swap = 1,
},
/* 0x00c9 type read, with no inc and increment. */
{ .op_str = "MOVX_T1_P",
.op = 0x30,
.layout_id = { P_OP_LAYOUT_MOVX_DUAL_4 },
.src_dst_swap = 1,
},
{ .op_str = "MOVX_T1_P",
.op = 0x31,
.layout_id = { P_OP_LAYOUT_MOVX_DUAL_4 },
.src_dst_swap = 1,
},
/* Regular reg read, with no inc and increment. */
{ .op_str = "MOVX_P",
.op = 0x32,
.layout_id = { P_OP_LAYOUT_MOVX_DUAL_4 },
.src_dst_swap = 1,
},
{ .op_str = "MOVX_P",
.op = 0x33,
.layout_id = { P_OP_LAYOUT_MOVX_DUAL_4 },
.src_dst_swap = 1,
},
{ .op_str = "MOV_T1_P",
.op = 0x38,
.layout_id = { P_OP_LAYOUT_MOV_4 },
.src_dst_swap = 0,
.mdfr_bit = 17,
.mdfr_bit_type = OP_MDFR_BIT_TYPE_USE_ALT_STR,
.alt_op_str = "MOV_P",
},
/* Regular 0x00c8 reg read. */
{ .op_str = "MOVX_P",
.op = 0x39,
.layout_id = { P_OP_LAYOUT_MOVX_4 },
.src_dst_swap = 0,
},
/* 0x00c9 type read. */
{ .op_str = "MOVX_T1_P",
.op = 0x3a,
.layout_id = { P_OP_LAYOUT_MOVX_4 },
.src_dst_swap = 0,
},
/* Regular 0x00c8 reg read. */
{ .op_str = "MOVX_P",
.op = 0x3d,
.layout_id = { P_OP_LAYOUT_MOVX_4 },
.src_dst_swap = 1,
},
/* 0x00c9 type read. */
{ .op_str = "MOVX_T1_P",
.op = 0x3e,
.layout_id = { P_OP_LAYOUT_MOVX_4 },
.src_dst_swap = 1,
},
/* Conditional execution. */
{ .op_str = "EXEC_COND_P",
.op = 0x3f,
.layout_id = { P_OP_LAYOUT_EXECUTE_COND_4 },
},
};
const dsp_op_info *get_dsp_p_op_info(uint32_t opcode, uint32_t op_len)
{
const dsp_op_info *p_ops;
uint32_t i, p_ops_cnt;
if (op_len == 2) {
p_ops = parallel_2_asm_ops;
p_ops_cnt = ARRAY_SIZE(parallel_2_asm_ops);
} else {
p_ops = parallel_4_asm_ops;
p_ops_cnt = ARRAY_SIZE(parallel_4_asm_ops);
}
for (i = 0; i < p_ops_cnt; i++) {
if (p_ops[i].op == opcode)
return &p_ops[i];
}
return NULL;
}
static const op_operand_layout operand_layouts[] = {
/*
* OP_LAYOUT_MOV_1:
*/
{ .loc_layouts = {
{ .layout_val_loc = {
.part1_bit_start = 16,
.part1_bits = 1 },
.layout_val = 0x00,
.operand_cnt = 2,
.operand_loc = {
{ .part1_bit_start = 9,
.part1_bits = 7,
.operand_type = OP_OPERAND_REG_7,
.operand_dir = OPERAND_DIR_DST, },
{ .part1_bit_start = 18,
.part1_bits = 7,
.operand_type = OP_OPERAND_REG_7,
.operand_dir = OPERAND_DIR_SRC, } },
.bitmask = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, } },
{ .layout_val_loc = {
.part1_bit_start = 16,
.part1_bits = 1 },
.layout_val = 0x1,
.operand_cnt = 4,
.operand_loc = {
{ .part1_bit_start = 17,
.part1_bits = 4,
.operand_type = OP_OPERAND_REG_4,
.operand_dir = OPERAND_DIR_DST, },
{ .part1_bit_start = 21,
.part1_bits = 3,
.operand_type = OP_OPERAND_REG_3,
.operand_dir = OPERAND_DIR_SRC,
.parallel_end = 1, },
{ .part1_bit_start = 9,
.part1_bits = 4,
.operand_type = OP_OPERAND_REG_4,
.operand_dir = OPERAND_DIR_DST, },
{ .part1_bit_start = 13,
.part1_bits = 3,
.operand_type = OP_OPERAND_REG_3_8,
.operand_dir = OPERAND_DIR_SRC, } },
.bitmask = { 0x00000001, 0x00000000, 0x00000000, 0x00000000, } } },
.loc_layout_cnt = 2, },
/*
* OP_LAYOUT_MOVX_MDFR_OFFSET_1:
*/
{ .loc_layouts = {
{ .layout_val_loc = {
.part1_bit_start = 21,
.part1_bits = 1 },
.layout_val = 0x01,
.operand_cnt = 2,
.operand_loc = {
{ .part1_bit_start = 16,
.part1_bits = 5,
.operand_type = OP_OPERAND_REG_5,
.operand_dir = OPERAND_DIR_DST, },
{ .part1_bit_start = 13,
.part1_bits = 3,
.part2_bit_start = 22,
.part2_bits = 3,
.operand_type = OP_OPERAND_A_REG_Y_MDFR_OFFSET,
.operand_dir = OPERAND_DIR_SRC, } },
.bitmask = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, } },
{ .layout_val_loc = {
.part1_bit_start = 0,
.part1_bits = 0 },
.layout_val = 0x00,
.operand_cnt = 2,
.operand_loc = {
{ .part1_bit_start = 16,
.part1_bits = 5,
.operand_type = OP_OPERAND_REG_5,
.operand_dir = OPERAND_DIR_DST, },
{ .part1_bit_start = 13,
.part1_bits = 3,
.part2_bit_start = 22,
.part2_bits = 3,
.operand_type = OP_OPERAND_A_REG_X_MDFR_OFFSET,
.operand_dir = OPERAND_DIR_SRC, } },
.bitmask = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, } } },
.loc_layout_cnt = 2, },
/*
* OP_LAYOUT_MOVX_LIT_OFFSET_1:
*/
{ .loc_layouts = {
{ .layout_val_loc = {
.part1_bit_start = 0,
.part1_bits = 0 },
.layout_val = 0x00,
.operand_cnt = 2,
.operand_loc = {
{ .part1_bit_start = 16,
.part1_bits = 5,
.operand_type = OP_OPERAND_REG_5,
.operand_dir = OPERAND_DIR_DST, },
{ .part1_bit_start = 9,
.part1_bits = 7,
.part2_bit_start = 21,
.part2_bits = 4,
.operand_type = OP_OPERAND_A_REG_INT_7_OFFSET,
.operand_dir = OPERAND_DIR_SRC, } },
.bitmask = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, } } },
.loc_layout_cnt = 1, },
/*
* OP_LAYOUT_R_X_Y_1:
*/
{ .loc_layouts = {
{ .layout_val_loc = {
.part1_bit_start = 16,
.part1_bits = 1 },
.layout_val = 0x00,
.operand_cnt = 3,
.operand_loc = {
{ .part1_bit_start = 9,
.part1_bits = 5,
.operand_type = OP_OPERAND_REG_5,
.operand_dir = OPERAND_DIR_DST, },
{ .part1_bit_start = 20,
.part1_bits = 5,
.operand_type = OP_OPERAND_REG_5,
.operand_dir = OPERAND_DIR_X, },
{ .part1_bit_start = 15,
.part1_bits = 1,
.part2_bit_start = 17,
.part2_bits = 3,
.operand_type = OP_OPERAND_REG_4,
.operand_dir = OPERAND_DIR_Y, } },
.bitmask = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, } },
{ .layout_val_loc = {
.part1_bit_start = 16,
.part1_bits = 1 },
.layout_val = 0x01,
.operand_cnt = 6,
.operand_loc = {
{ .part1_bit_start = 17,
.part1_bits = 3,
.operand_type = OP_OPERAND_REG_3_ACC,
.operand_dir = OPERAND_DIR_DST, },
{ .part1_bit_start = 22,
.part1_bits = 2,
.operand_type = OP_OPERAND_REG_2_T2,
.operand_dir = OPERAND_DIR_X, },
{ .part1_bit_start = 20,
.part1_bits = 2,
.operand_type = OP_OPERAND_REG_2,
.operand_dir = OPERAND_DIR_Y,
.parallel_end = 1, },
{ .part1_bit_start = 9,
.part1_bits = 3,
.operand_type = OP_OPERAND_REG_3_ACC,
.operand_dir = OPERAND_DIR_DST, },
{ .part1_bit_start = 14,
.part1_bits = 2,
.operand_type = OP_OPERAND_REG_2_T1,
.operand_dir = OPERAND_DIR_X, },
{ .part1_bit_start = 12,
.part1_bits = 2,
.operand_type = OP_OPERAND_REG_2_8,
.operand_dir = OPERAND_DIR_Y, } },
.bitmask = { 0x00000001, 0x00000000, 0x00000000, 0x00000000, } } },
.loc_layout_cnt = 2, },
/*
* OP_LAYOUT_R_X_Y_A_1:
*/
{ .loc_layouts = {
{ .layout_val_loc = {
.part1_bit_start = 0,
.part1_bits = 0 },
.layout_val = 0x00,
.operand_cnt = 4,
.operand_loc = {
{ .part1_bit_start = 9,
.part1_bits = 3,
.operand_type = OP_OPERAND_REG_3_FMA,
.operand_dir = OPERAND_DIR_DST, },
{ .part1_bit_start = 17,
.part1_bits = 4,
.operand_type = OP_OPERAND_REG_4,
.operand_dir = OPERAND_DIR_X, },
{ .part1_bit_start = 12,
.part1_bits = 4,
.operand_type = OP_OPERAND_REG_4,
.operand_dir = OPERAND_DIR_Y, },
{ .part1_bit_start = 21,
.part1_bits = 4,
.operand_type = OP_OPERAND_REG_4,
.operand_dir = OPERAND_DIR_A, } },
.bitmask = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, } } },
.loc_layout_cnt = 1, },
/*
* OP_LAYOUT_R_X_LIT_8_Y_1:
*/
{ .loc_layouts = {
{ .layout_val_loc = {
.part1_bit_start = 0,
.part1_bits = 0 },
.layout_val = 0x00,
.operand_cnt = 3,
.operand_loc = {
{ .part1_bit_start = 21,
.part1_bits = 4,
.operand_type = OP_OPERAND_REG_4,
.operand_dir = OPERAND_DIR_DST, },
{ .part1_bit_start = 17,
.part1_bits = 4,
.operand_type = OP_OPERAND_REG_4,
.operand_dir = OPERAND_DIR_X, },
{ .part1_bit_start = 9,
.part1_bits = 8,
.operand_type = OP_OPERAND_LITERAL_8_INT,
.operand_dir = OPERAND_DIR_Y, } },
.bitmask = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, } } },
.loc_layout_cnt = 1, },
/*
* OP_LAYOUT_PC_OFFSET_1:
*/
{ .loc_layouts = {
{ .layout_val_loc = {
.part1_bit_start = 0,
.part1_bits = 0 },
.layout_val = 0x00,
.operand_cnt = 2,
.operand_loc = {
{ .part1_bit_start = 9,
.part1_bits = 8,
.operand_type = OP_OPERAND_LITERAL_8,
.operand_dir = OPERAND_DIR_NONE, },
{ .part1_bit_start = 17,
.part1_bits = 8,
.operand_type = OP_OPERAND_LITERAL_8_INT_PC_OFFSET,
.operand_dir = OPERAND_DIR_NONE, } },
.bitmask = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, } } },
.loc_layout_cnt = 1, },
/*
* OP_LAYOUT_LOOP_PC_OFFSET_REG_CNT_1:
*/
{ .loc_layouts = {
{ .layout_val_loc = {
.part1_bit_start = 0,
.part1_bits = 0 },