@@ -13,7 +13,7 @@ Reporting (AER) driver and provides information on how to use it, as
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well as how to enable the drivers of endpoint devices to conform with
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PCI Express AER driver.
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- 1.2 Copyright © Intel Corporation 2006.
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+ 1.2 Copyright (C) Intel Corporation 2006.
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1.3 What is the PCI Express AER Driver?
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@@ -71,15 +71,11 @@ console. If it's a correctable error, it is outputed as a warning.
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Otherwise , it is printed as an error. So users could choose different
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log level to filter out correctable error messages.
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- Below shows an example.
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- +------ PCI-Express Device Error -----+
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- Error Severity : Uncorrected (Fatal)
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- PCIE Bus Error type : Transaction Layer
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- Unsupported Request : First
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- Requester ID : 0500
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- VendorID=8086h , DeviceID=0329h , Bus=05h , Device=00h , Function=00h
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- TLB Header:
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- 04000001 00200a03 05010000 00050100
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+ Below shows an example:
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+ 0000:50:00.0: PCIe Bus Error: severity=Uncorrected (Fatal) , type=Transaction Layer , id=0500(Requester ID)
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+ 0000:50:00.0: device [8086:0329] error status/mask=00100000/00000000
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+ 0000:50:00.0: [20] Unsupported Request (First)
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+ 0000:50:00.0: TLP Header: 04000001 00200a03 05010000 00050100
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In the example , 'Requester ID' means the ID of the device who sends
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the error message to root port. Pls. refer to pci express specs for
@@ -112,7 +108,7 @@ but the PCI Express link itself is fully functional. Fatal errors, on
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the other hand , cause the link to be unreliable.
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When AER is enabled , a PCI Express device will automatically send an
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- error message to the PCIE root port above it when the device captures
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+ error message to the PCIe root port above it when the device captures
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an error. The Root Port , upon receiving an error reporting message ,
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internally processes and logs the error message in its PCI Express
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capability structure. Error information being logged includes storing
@@ -198,8 +194,9 @@ to reset link, AER port service driver is required to provide the
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function to reset link. Firstly , kernel looks for if the upstream
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component has an aer driver. If it has , kernel uses the reset_link
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callback of the aer driver. If the upstream component has no aer driver
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- and the port is downstream port , we will use the aer driver of the
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- root port who reports the AER error. As for upstream ports ,
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+ and the port is downstream port , we will perform a hot reset as the
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+ default by setting the Secondary Bus Reset bit of the Bridge Control
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+ register associated with the downstream port. As for upstream ports ,
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they should provide their own aer service drivers with reset_link
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function. If error_detected returns PCI_ERS_RESULT_CAN_RECOVER and
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reset_link returns PCI_ERS_RESULT_RECOVERED , the error handling goes
@@ -253,11 +250,11 @@ cleanup uncorrectable status register. Pls. refer to section 3.3.
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4. Software error injection
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- Debugging PCIE AER error recovery code is quite difficult because it
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+ Debugging PCIe AER error recovery code is quite difficult because it
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is hard to trigger real hardware errors. Software based error
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- injection can be used to fake various kinds of PCIE errors.
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+ injection can be used to fake various kinds of PCIe errors.
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- First you should enable PCIE AER software error injection in kernel
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+ First you should enable PCIe AER software error injection in kernel
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configuration , that is , following item should be in your .config.
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CONFIG_PCIEAER_INJECT=y or CONFIG_PCIEAER_INJECT=m
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