RTL vs Verification system verilog code

[amichai-bd]

RTL Design Constructs

Module

Interface

Package

Function

Macro (define)

Generate Block (generate/endgenerate)

Always Block (always, always_comb, always_ff, always_latch)

Continuous Assignment (assign)

Parameter

Localparam

Typedef

Enum

Struct

Union

Not for RTL Design (With Explanation)

1. Program - Used for testbench synchronization and is not synthesizable.

2. Class - Object-oriented construct used for verification and simulation purposes.

3. Covergroup - Used for functional coverage in verification and is not part of synthesizable design.

4. Coverpoint - Defines specific conditions for coverage collection, only relevant in verification.

5. Cross - Used to analyze the correlation of multiple coverpoints for verification.

6. Clocking Block - Designed for testbench timing synchronization and is not synthesizable.

7. Assertion (assert, assume, cover) - Used for simulation checks and formal verification, not synthesizable.

8. Interface Class - Used in UVM for verification and simulation, not related to hardware design.

9. Constraint - Applies randomization rules in verification and cannot be synthesized.

10. Initial Block - Executes once during simulation and is not synthesizable, so it's not for RTL design.

11. Task - While tasks can be synthesizable if they don't contain timing controls, their use in RTL design is generally discouraged in favor of functions for better code clarity and maintainability.

[amichai-bd]

@roman012285 @abdkeb

[roman012285]

thanks!