From 2984e19d284a19faf5d1d2a7a4b33ca293d79db7 Mon Sep 17 00:00:00 2001 From: roman022285 Date: Mon, 12 Feb 2024 12:34:58 +0200 Subject: [PATCH 1/5] add timer interrupt and illegal instruction exception --- sidebars.js | 2 ++ 1 file changed, 2 insertions(+) diff --git a/sidebars.js b/sidebars.js index 39f31a5d..80da86e7 100644 --- a/sidebars.js +++ b/sidebars.js @@ -306,6 +306,8 @@ RISCV_Cores:[ 'rvc/big_core/csr_registers', 'rvc/big_core/cr_mem', 'rvc/big_core/pmon', + 'rvc/big_core/illegal_instruction_exception', + 'rvc/big_core/timer_interrupt_exception', ], }, { From 5957610c0a0ba7b9995d2e6b1e43a9b28cdb4da5 Mon Sep 17 00:00:00 2001 From: roman022285 Date: Mon, 12 Feb 2024 12:35:19 +0200 Subject: [PATCH 2/5] apdate pmon.md documentation --- docs/rvc/big_core/pmon.md | 1 + 1 file changed, 1 insertion(+) diff --git a/docs/rvc/big_core/pmon.md b/docs/rvc/big_core/pmon.md index e12de137..b9e989b8 100644 --- a/docs/rvc/big_core/pmon.md +++ b/docs/rvc/big_core/pmon.md @@ -10,6 +10,7 @@ - To do that we are going to use two csr counters: - `instret` - counts the number of instructions retired(executed completely). - `cycle` - counts the number of clock cycles. + - Those Csr's are read only. They sample the machine mode csr's `mcycle` and `minstret`. Those hard wired counters have a size of 32 bits. Its important to say that RV32 spec allows us to extend their size to 64 bits by using two more counters: `instreth` and `cycleh`. - In our design, we name `cycle` and `cycleh` as `CSR_CYCLE_LOW` and `CSR_CYCLE_HIGH` respectively. From 7c0a42a82f339ccc4c41fd5339811badc0d4e00e Mon Sep 17 00:00:00 2001 From: roman022285 Date: Mon, 12 Feb 2024 12:36:03 +0200 Subject: [PATCH 3/5] add custom csrs to csr documentation --- docs/rvc/big_core/csr_registers.md | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/docs/rvc/big_core/csr_registers.md b/docs/rvc/big_core/csr_registers.md index 149581e0..e0da29e3 100644 --- a/docs/rvc/big_core/csr_registers.md +++ b/docs/rvc/big_core/csr_registers.md @@ -169,4 +169,16 @@ assign CsrInstQ101H.csr_imm_bit = InstructionQ101H[14]; - CSR unit located in `Q102H` execution stage because we need to forward data to rd if necessary. - CSR register defined in the core package file under `t_csr_addr` enumerator which includes all the CSR addresses used in the core and the registers them self in the `t_csr` struct +### PMON measurments +note: The following csr's defined in `source/core_rrv` core. +- Please refer to [pmon link](/docs/rvc/big_core/pmon.md). + +### Custom CSR's +note: The following csr's defined in `source/core_rrv` core. +- timer interrupt exception csr's: + - `csr_custom_mtime` - Used to measure time of our system. This csr is read only from software and can be updated only in HW. Each clock it decrements by one. Used only in machine mode. + - `csr_cutome_mtimecmp` - This csr is RW csr and used for comparison with `custom_mtime`. We use it in Timer interrupt exception. + See [Timer_interrupt_exception](/docs/rvc/big_core/timer_interrupt_exception.md) + - `csr_custom_LFSR` - Used for generating pseudo random numbers. The algorithm is based on LFSR algorithm. For biggest cycle we used the following Polynom: `x^32 + x^22 + x^2 + x^1 + 1`. That Csr is RO and can be updated by HW for seed value update. + From c9a17b5eee54743723e48a802441e16bb4695647 Mon Sep 17 00:00:00 2001 From: roman022285 Date: Mon, 12 Feb 2024 12:36:20 +0200 Subject: [PATCH 4/5] add illegal instruction documentation flow --- .../big_core/illegal_instruction_exception.md | 84 +++++++++++++++++++ 1 file changed, 84 insertions(+) create mode 100644 docs/rvc/big_core/illegal_instruction_exception.md diff --git a/docs/rvc/big_core/illegal_instruction_exception.md b/docs/rvc/big_core/illegal_instruction_exception.md new file mode 100644 index 00000000..8820a081 --- /dev/null +++ b/docs/rvc/big_core/illegal_instruction_exception.md @@ -0,0 +1,84 @@ +# Illegal Instruction Exception +Illegal instruction is a synchronous exception because its origin comes from the software flow. +### Causes of illegal instructions +- Un familiar instruction that belongs to a specific RISCV extension that not supported bt the core. +- Hw errors while fetching the instruction from the memory. +- Custom instructions that not supported by RISCV spec (In most of the cases the compiler will not compile that). +- Compiler errors (very rare but possible). + +### Cases in our core +For more details, please refer to `/source/core_rrv/illegal_instruction.vh` +- Some of the `Funct7` fields in R-type instructions do not zero +- `Funct3` do not match the instruction. For example we try to execute S-type instruction and `Funct3 = 111`. +- Un recognized OpCode that not supported by the core or not allowed by the spec. + +### Illegal Instruction Generation +- We use the test `/verif/core_rrv/alive_illegal.c`. +- We try to create an instruction with illegal `FUCT7`, we generate `slli` with funct7 = 0x7f instead of 0x0 +``` + // This instruction is trying to generate slli instruction with illegal FUNCT7. + asm(".word 0xfff79793" : /* outputs / : / inputs / : / clobbers */); +``` +- This is a code snippet from the `elf.txt` file +``` + 1660: fd010113 addi sp,sp,-48 + . + . + . + 1674: 00200793 li a5,2 + 1678: fef42423 sw a5,-24(s0) + 167c: fff79793 0xfff79793 + 1680: fec42703 lw a4,-20(s0) + . + . + . + 16b0: 00008067 ret +``` +### Illegal Instruction Mechanism +1. Detection if illegal instruction inside the controller : +`assign IllegalInstructionQ101H = (PreIllegalInstructionQ101H) && ! (flushQ102H || flushQ103H);` +- In case of illegal instruction and flush, we do not start the the interrupt routine because the instruction will be flushed anyway. +- When the illegal instruction is a part of the instruction flow than we erase that instruction by inserting `NOP` and jumps to the interrupt routine. +2. Csr update +Once we decide to take the exception we start to update and read csr's. T +- We update the cause of the exception by modifying the `csr_mcause` csr by assign the `32'h00000002`. +- Update `csr_mepc` with the return value PC of the illegal instruction. We will use it as return address from the interrupt routine. +- Update `csr_mtval` with the illegal instruction machine code. In our case it will be `fff79793` +- Set the `CSR_MSTATUS[MIE]` to the current value of `CSR_MSTATUS[MIE]` to store the previous machine interrupt enable mode. +- Disable `CSR_MSTATUS[MIE]` when taking an exception to avoid nested interrupts. +3. Jumps to Interrupt routine +- Store the values of the registers +- Perform the routine +Jump to `csr_mtvec` value that keeps the address pf the routine. +4. Return from interrupt routine +- Restore the registers +- update `CSR_MSTATUS[MIE]` with `CSR_MSTATUS[MIE]`. +### crt0.s_boot_trap.s file +``` +csr_init: + li t0, 0x100 # Load the immediate value 0x100 of trap handler address + csrw mtvec, t0 # Write the value in t0 to the mtvec CSR +``` + +- The address of the interrupt routine is `0x100` +- Inside that file we store and restore the registers before jumping to the routine inside `interrupt_handler.h`. +Please see `/app/crt0/crt0_boot_trap.S` and `/app/defines/interrupt_handler.h` + +### Interrupt_handler.h +``` + if ((mcause & 0xFFF) == ILLEGAL_INSTRUCTION_EXCEPTION) { + csr_mepc = read_mepc(); + csr_mtval = read_mtval(); + rvc_printf("ILGL INST\n"); + rvc_printf("MEPC:"); + rvc_print_unsigned_int_hex(csr_mepc); + rvc_printf("\n"); + rvc_printf("MTVAL:"); + rvc_print_unsigned_int_hex(csr_mtval); + rvc_printf("\n"); + } +``` + + + + From b7f1a04f1a9b13b7bede779e49bb2158ac40e003 Mon Sep 17 00:00:00 2001 From: roman022285 Date: Mon, 12 Feb 2024 12:41:09 +0200 Subject: [PATCH 5/5] add timer interrupt.md --- docs/rvc/big_core/timer_interrupt_exception.md | 0 1 file changed, 0 insertions(+), 0 deletions(-) create mode 100644 docs/rvc/big_core/timer_interrupt_exception.md diff --git a/docs/rvc/big_core/timer_interrupt_exception.md b/docs/rvc/big_core/timer_interrupt_exception.md new file mode 100644 index 00000000..e69de29b