added first version of the fabric verification including fifo_arb,mini_core,fabric and fabric_mini_cores.

Author: actions-user

docs/fabric/verification/verification_fabric.md

@@ -0,0 +1,145 @@
+## Strategy
+In order to create a good env for the fabric we seperated the fabric into two conceptual components, the first one is the traffic, this part only checks if the data is moving as expected inside the fabric.
+the second part will be a mini_cores_fabric which include also the mini_cores, so the fabric_mini_cores_tb is an extension of the fabric_tb.
+- we also have trackers that it is a log that including all the transactions and the time of the transaction sample.
+### Code
+## fabric_tb
+The fabric_tb is created from 3 main parts. 
+1. Interface - the interface is where we connect from the software to the hardware, we are not using UVM so everything is a bit different then normal. the fabric is a 3x3 mini_core_tile that created using generate inside the fabric. This fact make it very difficult to get a signal in a generic way like signal[col][row] because of the generate. so we created those signals (i.e. interface) using generate.
+```systemverilog
+genvar row, col;
+generate
+  for (col = 1; col <= V_COL; col = col + 1) begin : gen_col
+    for (row = 1; row <= V_ROW; row = row + 1) begin : gen_row
+    // fabric to if 
+      assign fabric.col[col].row[row].mini_core_tile_ins.mini_core_top.mini_mem_wrap.C2F_ReqValidQ103H = valid_tile[col][row]; // input to req_fifo 
+      assign fabric.col[col].row[row].mini_core_tile_ins.mini_core_top.mini_mem_wrap.C2F_ReqQ103H = origin_trans[col][row];     
+    // if to fabric
+      assign origin_trans_fab[col][row] = fabric.col[col].row[row].mini_core_tile_ins.mini_core_top.mini_mem_wrap.C2F_ReqQ103H;   // input_data to req_fifo    
+      assign tile_rsp_trans[col][row] = fabric.col[col].row[row].mini_core_tile_ins.mini_core_top.mini_mem_wrap.F2C_OutFabricQ504H;// input_data to rd_rsp fifo
+      assign valid_tile_rsp[col][row] = fabric.col[col].row[row].mini_core_tile_ins.mini_core_top.mini_mem_wrap.F2C_OutFabricValidQ504H;// valid input_data to rd_rsp fifo
+      assign valid_local[col][row] = fabric.col[col].row[row].mini_core_tile_ins.out_local_req_valid;
+      assign target_trans[col][row] = fabric.col[col].row[row].mini_core_tile_ins.out_local_req;
+      assign requestor_id_ref[col][row] = fabric.col[col].row[row].mini_core_tile_ins.pre_in_local_req.requestor_id;
+      assign tile_ready[col][row] = fabric.col[col].row[row].mini_core_tile_ins.out_local_ready;
+    end
+  end
+endgenerate
+```
+We created for each signal a 2D array that is connected to its relevant tile.
+
+2. sequence - the sequence is creating the traffic for the fabric, collect the data from each tile and then actiate a DI checker.
+- traffic - The data is random but it has more fields, we randomize the source tile and the target tile while making sure that it is not the same tile. then we are randomize the opcode if it is WR or RD. we can read only after write.
+
+- data collection - the data collectors are created like this:
+```systemverilog
+static t_tile_trans_v monitor_source_trans [V_ROW:1] [V_COL:1] [$];
+```
+this is a V_ROWxV_COL queue array from t_tile_trans type. each element is collecting the data for a specific tile, in this case as a source tile.
+```systemverilog
+task automatic fabric_get_source_from_tile();
+t_tile_trans_v [V_COL:1][V_ROW:1] temp_trans_req;
+t_tile_trans_v [V_COL:1][V_ROW:1] temp_trans_rsp;
+  for(int i = 1; i<= V_COL; i++) begin
+    for(int j = 1; j<= V_ROW; j++) begin
+      automatic int col = i;
+      automatic int row = j;
+      fork forever begin
+        t_tile_id source_id;
+        wait(valid_tile[col][row] == 1'b1);
+        source_id[7:4] = col;
+        source_id[3:0] = row;
+        #0;
+        temp_trans_req[col][row].trans.data                  = origin_trans_fab[col][row].data;
+        temp_trans_req[col][row].trans.opcode                = origin_trans_fab[col][row].opcode;
+        temp_trans_req[col][row].trans.address               = origin_trans_fab[col][row].address;
+        temp_trans_req[col][row].trans.next_tile_fifo_arb_id = NULL_CARDINAL;
+        temp_trans_req[col][row].trans.requestor_id = '0;
+        temp_trans_req[col][row].source = source_id;
+        temp_trans_req[col][row].target = origin_trans_fab[col][row].address[31:24];
+        monitor_source_trans[col][row].push_back(temp_trans_req[col][row]);
+        cnt_trans_source = cnt_trans_source + 1;
+        wait(valid_tile[col][row] == 1'b0);
+      end forever begin // RD_RSP
+       t_tile_id source_id_rsp;
+       wait(valid_tile_rsp[col][row] == 1'b1);
+        source_id_rsp[7:4] = col;
+        source_id_rsp[3:0] = row;
+        #0;
+        temp_trans_rsp[col][row].trans.data = '0;
+        temp_trans_rsp[col][row].trans.address = '0;
+        temp_trans_rsp[col][row].trans.opcode  = tile_rsp_trans[col][row].opcode; // input to fifo of RD_RSP in mem_wrap
+        temp_trans_rsp[col][row].trans.requestor_id = '0;
+        temp_trans_rsp[col][row].trans.next_tile_fifo_arb_id = NULL_CARDINAL;
+        temp_trans_rsp[col][row].source = source_id_rsp;
+        temp_trans_rsp[col][row].target = tile_rsp_trans[col][row].address[31:24];
+        monitor_source_trans_rsp[col][row].push_back(temp_trans_rsp[col][row]);
+        cnt_trans_source_rsp = cnt_trans_source_rsp + 1;
+        wait(valid_tile_rsp[col][row] == 1'b0);
+      end
+      join_none
+    end
+  end
+```
+we have 2 collectors in this env:
+- the source collector that collect the data from the source tile it can be a regular data or RD_RSP which is the data that is the data that coming back to the source tile after a read request.
+- the target collector is collecting the data that finish its traffic through the fabric.
+The collectors wait for the relevant signals to be valid and then collect the data into a queue.
+at the end we are activating a DI_checker that checks the data.
+
+3. Tests:
+```systemverilog
+task run_fabric_test(input string test);
+  if (test == "fabric_alive") begin
+     `include "fabric_alive.sv"
+  end else if(test == "fabric_all_tiles") begin
+     `include "fabric_all_tiles.sv"
+  end else if(test == "fabric_wr_rd_data") begin
+     `include "fabric_wr_rd_data.sv"
+  end else if(test == "fabric_BP_test") begin
+     `include "fabric_BP_test.sv"
+  end else begin
+    $error(" [ERROR] : test %s not found",test);
+  end
+endtask
+```
+The 2 main tests are the fabric_all_tiles_test and fabric_BP_test.
+The fabric_all_tiles_test is activating all tiles in parallel, it ensure that the fabric is reliable when it has all kind of traffic like stress or very low traffic.
+the fabrc_BP_test is a test that creating a lot of pressure on each tile, we fill all the fifo of all tiles in transactions and we want to see how the fabric is handling the pressure, if he decline new transactions or if after the release of the pressure the fabric is handling it correctley.
+
+## fabric_mini_cores_tb
+This tb is taking the fabric_tb that test the fabric traffic alone and adding to it the actual mini_cores.
+in this part we compile a C program that can run on each one of our mini cores. the traffic is verified like before but now we are checking if the program do what it suppose to. 
+to do it we created 9 IRAM and DRAM kike this:
+```systemverilog
+logic  [7:0] IMem  [V_ROW:1] [V_COL:1]   [I_MEM_SIZE_MINI + I_MEM_OFFSET_MINI - 1 : I_MEM_OFFSET_MINI];
+logic  [7:0] DMem  [V_ROW:1] [V_COL:1]   [D_MEM_SIZE_MINI + D_MEM_OFFSET_MINI - 1 : D_MEM_OFFSET_MINI];
+```
+In order to connect them to the design we assigned them by generate like before and then load each one of the core seperatly like this:
+```systemverilog
+`MAFIA_DFF(IMem, IMem, clk)
+task load_mem(input int col, input int row);
+    $readmemh({"../../../target/fabric/tests/",test_name,"/gcc_files/inst_mem.sv"} , IMem[col][row]);
+    ...
+```
+this task is reading the i_mem that created from the linker after compiliation.
+next we loaded each imem into the relevant mini core like this:
+```systemverilog
+    ...
+    for(int i = 1; i<= V_COL; i++) begin
+      for(int j = 1; j<= V_ROW; j++) begin
+        automatic int col = i;
+        automatic int row = j;
+        fork begin 
+          load_mem(col,row);
+          $display("time is %0t for tile [%0d,%0d]",$time,col,row);
+        end join
+        ...
+        end
+        end
+```
+In this way we can load for each tile a different program to run in parallel to the other tiles.
+
+
+
+# TODO - add DRAM explanation and add c tests explanation. 

docs/fabric/verification/verification_fifo_arb.md

@@ -0,0 +1,213 @@
+## Strategy
+We devided our goal into 3 main topics.
+1. Creating meaningful sequences that will assure that our design is robust and can handle pressure.
+2. Creating reliable checkers.
+3. Creatung a lot of robust tests that will push the design to his limits.
+Note - we made here an assamption that if the FIFO_arb will be good then the FIFO and the Arbiter will be good as well. 
+
+### Code
+Our FIFO_arb verification created with the least amount of pre assumptions like size of FIFO, depth of FIFO and even the amount of FIFO's in the FIFO_arb (even though it was not in our design, we wnated to ensure the most robust DUT).
+The module of the TB called "router_tb" and it is also contains one basic test for the router.
+The important signals and parameters in the TB are:
+```systemverilog
+parameter V_REQUESTS   = 10;
+parameter V_FIFO_DEPTH = 4;
+parameter V_NUM_FIFO   = 4;  // number of fifos to exercise in the test (HW is always 4, simulation may stimuli only some of them)
+parameter V_NO_BACK_PRESSURE = 0; // used to disable back pressure in the test which will cause a failure in the test
+parameter V_MAX_DELAY  = 5; // max delay in the test
+parameter V_BACK_PRESURE = 10;
+logic              clk;
+logic              rst;
+static t_tile_trans ref_fifo_Q [3:0][$];
+static t_tile_trans ref_outputs_Q [$];  
+```
+We created the fifo_arb inputs and outputs, the inputs are 4 FIFO's (can be less then 4) that are creatd in software (to be used as RM), they are type of dynamic array in SV that called queue.The output is the winner of each transaction. the type of the FIFO's is t_tile_trans.
+we also created some parameters that can change by user definition.
+The main sequence is:
+``` systemverilog
+  fork 
+      run_fifo_arb_test(test_name);
+      fifo_arb_get_inputs();
+      fifo_arb_get_outputs();
+  join
+```
+We are activating three tasks in parallel, run the test and two collectors that will collect the input and the output of the FIFO_arb (for each FIFO obviousley).
+
+ - run_fifo_arb_test(test_name);
+ ```systemverilog
+ task run_fifo_arb_test(input string test);
+  delay(30);
+  // ====================
+  // fifo_arb tests:
+  // ====================
+  if (test == "fifo_arb_simple") begin
+     `include "fifo_arb_simple.sv"
+  end else if(test == "fifo_arb_single_fifo_full_BW")begin
+    `include "fifo_arb_single_fifo_full_BW.sv"
+  end else if(test == "fifo_arb_all_fifo_full_BW")begin
+    `include "fifo_arb_all_fifo_full_BW.sv"
+  end else if(test == "fifo_arb_Assertion_test")begin
+    `include "fifo_arb_Assertion_test.sv"
+  end else if(test == "fifo_arb_back_pressure")begin
+    `include "fifo_arb_back_pressure.sv"
+  end else begin
+    $error(" [ERROR] : test %s not found",test);
+  end
+endtask
+
+ ```
+ This task is running the relevant test that was chosen by the user. 
+
+ - fifo_arb_get_inputs();
+ ```systemverilog
+ task automatic fifo_arb_get_inputs();
+ for(int i = 0; i<4; i++) begin
+  automatic int index = i;
+  fork begin
+    forever begin
+      wait(valid_alloc_req[index] == 1'b1);
+      #0;
+      cnt_in = cnt_in + 1;
+      $display("input of fifo number %0d and CNT_IN = %0d",index,cnt_in);
+      ref_fifo_Q[index].push_back(alloc_req[index]);
+      wait(valid_alloc_req[index] == 1'b0);  
+    end
+  end 
+  forever begin
+    wait(fifo_arb_ins.arb.winner_dec_id[index] == 1'b1);
+    if(winner_req_valid == 1'b0) $display("problem in fifo %0d at time %0t",index,$time);
+    cnt_fifo_pop = cnt_fifo_pop + 1;
+    $display("cnt_fifo_pop = %0d in fifo %0d at time %0t winner_valid is %0b and fifo_pop is %4b",cnt_fifo_pop,index,$time,winner_req_valid,fifo_arb_ins.arb.winner_dec_id);
+    wait(fifo_arb_ins.arb.winner_dec_id[index] == 1'b0);
+  end
+  join_none
+end
+endtask
+ ```
+ This task is using a technique that creating all the fifo's at the same time in parallel, we are using fork - join_none to put the process in the background so the code will continue to run. in this way we created a for loop that generates 4 software fifo's in parallel.
+ Each FIFO is getting a thread of his own that including two sub threds that runs in parallel as well.The first sub thread is collecting all the transaction inputs of the relevant FIFO, the second sub thread is collecting the output of each FIFO, this way we can know where was an issue in a more specific way.
+
+ - fifo_arb_get_outputs();
+ ```systemverilog
+ task automatic fifo_arb_get_outputs();
+int fifo_pop_cnt = 0;
+fork
+forever begin
+  @(winner_req);
+  #0;
+  if(winner_req_valid == 1'b1)begin
+  cnt_out = cnt_out + 1;
+  ref_outputs_Q.push_back(winner_req);
+  $display("CNT OUT = %0d",cnt_out);
+  end
+end
+join_none
+endtask
+ ```
+ This task, also run's in the bacground, simply collect all the output transactions from the fifo_arb and save them in a queue for post process.
+
+ - Post process.
+ The last part of the verification is the DI_checker (Data Integrity).
+after the sequence is finished we are activating a checker that will compare the data from the inputs and the  output.
+
+```systemverilog
+task fifo_arb_DI_checker(); // pseudo SB
+automatic bit check = 0;
+repeat(5000)begin
+  foreach(ref_fifo_Q[i,j])begin
+    foreach(ref_outputs_Q[k])begin
+      if(ref_fifo_Q[i][j] == ref_outputs_Q[k])begin
+        ref_fifo_Q[i].delete(j);
+        ref_outputs_Q.delete(k);
+      end
+     end
+    end
+   end
+  if(ref_outputs_Q.size()!= 0)begin
+    $error("output list not empty ,data is and size %0d",ref_outputs_Q.size());
+    check = 1'b1;
+  end
+  for(int i=0;i<4;i++)begin
+    if(ref_fifo_Q[i].size() != 0)begin
+      check = 1'b1;
+       $error("input list not empty for fifo %0d , and size %0d",i,ref_fifo_Q[i].size());
+    end   
+  end
+  if(check == 1'b0)
+    $display("DI CHECKER: DATA IS CORRECT");
+endtask
+```
+This task is simply checks if all the inputs did got out from the fifo_arb. it iterates all the arrays and compare the input array to the output array, if there is a mismatch then the checker will allert in which fifo and whuch transaction we had this issue.
+
+# Tests 
+We wanted to create the strongest tests that will push our design to its limits. 
+We have 5 tests that can be paramtrize. 
+1. fifo_arb_simple.
+2. fifo_arb_single_fifo_full_BW.
+3. fifo_arb_all_fifo_full_BW.
+4. fifo_arb_Assertion_test.
+5. fifo_arb_back_pressure.
+
+Tests 1 and 2 are very simple and created as first step just to see the flow of the design.
+
+Test 3 is a very powerfull test, it activating all fifo's in the same time and pushes random data in random times to each one of them.
+```systemverilog
+int cycle_delay;
+int cycle_delay_arb;
+int delay_test;
+static int fifo_finish;
+for(int i = 0; i<V_NUM_FIFO; i++) begin
+  automatic int fifo = i;
+  fork begin 
+    $display("this is fifo %d at time %t",fifo,$time);
+    for(int j = 0; j < V_REQUESTS; j++)begin
+        wait(fifo_arb_ins.full[fifo] == '0);
+        cycle_delay = $urandom_range(0, V_MAX_DELAY);
+        delay(cycle_delay);  
+        $display("fifo %d and request %0d at time: %0t and full[%0d] is %0b and full is %4b",fifo,j,$time,fifo,fifo_arb_ins.full[fifo],fifo_arb_ins.full );
+        fifo_arb_gen_trans(fifo);
+    end
+  fifo_finish = fifo_finish + 1;
+  $display("############# this is FIFO_FINISH %0d in fifo %0d at time %t",fifo_finish,fifo,$time);
+
+  end 
+  join_none
+end
+fork : in_ready_arb_fifo_fork
+    begin
+    forever begin
+    cycle_delay_arb = $urandom_range(2, V_MAX_DELAY + 15);
+    rand_in_ready = $urandom_range(0,15);
+    delay(cycle_delay_arb);
+    in_ready_arb_fifo = {5{rand_in_ready}};
+    end
+  end
+  begin
+    delay_test = V_REQUESTS/V_NUM_FIFO;
+    delay(delay_test);
+  end
+join_any
+disable in_ready_arb_fifo_fork;
+in_ready_arb_fifo = 5'b11111;
+wait(fifo_finish == (V_NUM_FIFO));
+$display("############# this is empty %4b at time %t befote wait",fifo_arb_ins.empty,$time);
+wait(fifo_arb_ins.empty == 4'b1111);
+$display("############# after wait FIFO_FINISH %0d at time %0t",fifo_finish,$time);
+$display("############# this is empty %4b at time %t after wait",fifo_arb_ins.empty,$time);
+```
+This test is activating all FIFO's using fork - join_none and randomize the data and the delay.
+the number of transaction is defined by the user as long as the number of FIFO's and the depth of each FIFO. We created a lot of tests that changes those parameters.
+
+The assertion_test is not in the GK, it is only a test that will violate the rule of our assertion so we can verify that out assertions are correct.
+
+and the last test is a back_pressure_test. In this test we wanted to check a real scenario that the fifo_arb will need to handle with. in this case we fill the fifo_arb completley and we didnt allow the transaction to get out of the fifo_arb. we expect that the fifo_arb wont take any new request until the pressure is down. we did it by blocking (using XMR) the ready signal that get into the fifo_arb so the transactions wont be able to get out. 
+
+# Conclusion
+- our sequence is a generic one that all our tests are using it.
+- our DI checker is a simple yet a powerfull one, we found a lot of issues that were fixed and it assure us a reliable GK.
+In order to verify smaller parts or protocols we added assertions and not a checkers, for instanse we use an assertion that checks if we are trying to read from an empty FIFO, our assertion_test verify that.
+- Those tests are very robust and we changed the parameter to get into lot of corners in our design.
+- All in all this env helped us to find a lot of bugs and issues that were in the origin design and it gave us some confident about the reliability of our design.
+
+
+ 

docs/fabric/verification/verification_intro.md

@@ -2,5 +2,17 @@
 sidebar_position: 1
 ---
 
-# Fabric Intro
+# Fabric Verification Intro
+This chapter will describe the verification agenda of the Fabric.
+ - In the fabric we have verified three main components - FIFO_arb, Fabric and Mini_core_tile.
+ - Each one of those components have its own uniqe enviroment that include TB, flow tasks, verification tasks and test lists.
+
+ ## Terms that will be used.
+  -  sequence - a sequence is a flow of activating a DUT.
+  -  test - a test is a scenario that we want to check, a test can contain more then one sequence.
+  - TB - test bench - will activate our DUT and will connect it to the verification enviroment.
+  - Checkers - objects or components that will ensure the reliabilty of our design like data integrity checker and protocol checkers etc.
+  - RM - reference model - a software object that will calculate the expected output of a DUT for each transaction that the DUT is getting.
+  - fork join/join_any/join_none - a fork will create a number of threads that will run in parallel. The ending can be join i.e exit the fork only when all of the threads are over. join_any i.e exit the fork when one or more threads done. join_none - exit the fork even if no thred is done.
+