Merge pull request #87 from FPGA-MAFIA/roman_branch

rename core_rrv to big_core

Author: roman012285

docs/IPs/vga.md

@@ -100,8 +100,8 @@ unsigned int ASCII_BOTTOM[97] = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
 
 
 ### Running simple vga test
-- We will run it on `core_rrv` core. You can run it on any core that have VGA support. 
-- Open or add the following test to your core `/verif/core_rrv/tests/alive_vga.c`. 
+- We will run it on `big_core` core. You can run it on any core that have VGA support. 
+- Open or add the following test to your core `/verif/big_core/tests/alive_vga.c`. 
 ```
 
 #include "big_core_defines.h"
@@ -121,11 +121,11 @@ int main()  {
 ```
 
 - Please make sure to add `print_vga_screen task` to print the screen.    
-You can use the `/verif/core_rrv/tb/core_rrv_vga_tb.sv` test as a template. 
-Do not forget to change the link to new TB in `/verif/core_rrv/tb/core_rrv_verif_list.f` file.   
+You can use the `/verif/big_core/tb/big_core_vga_tb.sv` test as a template. 
+Do not forget to change the link to new TB in `/verif/big_core/tb/big_core_verif_list.f` file.   
 
-- run `/.build -dut core_rrv -test alive_vga -app -sim -gui`.
-- You should see the output in `/target/core_rrv/test/alive_vga/screen.log` file. 
+- run `/.build -dut big_core -test alive_vga -app -sim -gui`.
+- You should see the output in `/target/big_core/test/alive_vga/screen.log` file. 
 - The content of that file will be: 
 ![vga_screen_shot.png](/snapshots/vga_screen_shot.png)
 

docs/build_script/mafia_scripts.md

@@ -15,16 +15,16 @@ The `-yml` flag is used to specify the name of the test file. In this case, it i
 - This script is used to generate a list of parameters for a specific core inside `verif/<core_name>` directory. The list of the parameters will be located in `/target` directory.
 For example:
 ```
-./scripts/gen_parameter_list.py core_rrv
+./scripts/gen_parameter_list.py big_core
 ``` 
-Will generate file name `core_rrv_parameter_list.csv` in `/target`
+Will generate file name `big_core_parameter_list.csv` in `/target`
 
 ### ovrd_params.py
 - This script overrides the default parameters of a specific core. The override parameters will be located in `/verif/<core_name>` directory.
 - The list of the parameters we wish to override and their new values will be located in `/scriprs/ovrd_params` directory.
-For example, assume we would like to override the default parameters of `core_rrv` core. We will need to create a file named `new_params_list.csv` in `/scripts/ovrd_params` directory. The file will contain the list of the parameters we wish to override and their new values and then run the command
+For example, assume we would like to override the default parameters of `big_core` core. We will need to create a file named `new_params_list.csv` in `/scripts/ovrd_params` directory. The file will contain the list of the parameters we wish to override and their new values and then run the command
 ```
-./scripts/ovrd_params.py -dut core_rrv -ovrd_file new_params_list
+./scripts/ovrd_params.py -dut big_core -ovrd_file new_params_list
 ```
 - Suppose we want to override `RF_NUM_MSB` parameter, then the format of `new_params_list.csv` file will be:
 ```

docs/rvc/big_core/csr_registers.md

@@ -150,7 +150,7 @@ For more information about the CSR read/write only instructions, refer to the un
 - In our implementation we are using the CSR register `scratchpad_csr` which address is equal to 0x009. The compiler change its name to `vxsat` as described in the privileged spec, chapter 2. Please do not worry about the names of the CSR registers, you may play with those addresses as you wish and examine `_elf.txt` file to see the changes.
 Make sure to supply the correct address of the CSR as defined in `t_csr_addr` enumerator in the big core package file. 
 
-- **For more instructions using asm volatile, please go to `/verif/core_rrv/test/alive_csr.c`, We suggest to compile the file and look at the `_elf.txt` file to see the generated instructions.** 
+- **For more instructions using asm volatile, please go to `/verif/big_core/test/alive_csr.c`, We suggest to compile the file and look at the `_elf.txt` file to see the generated instructions.** 
 
 ### CSR instructions implemented in the big core
 - CSR control signals are generated in the control unit of the big core. The following code snippet shows the CSR control signals generation. 
@@ -170,11 +170,11 @@ assign CsrInstQ101H.csr_imm_bit  = InstructionQ101H[14];
 - CSR register defined in the core package file under `t_csr_addr` enumerator which includes all the CSR addresses used in the core and the registers them self in the `t_csr` struct
 
 ### PMON measurments
-note: The following csr's defined in `source/core_rrv` core.
+note: The following csr's defined in `source/big_core` core.
 - Please refer to [pmon link](/docs/rvc/big_core/pmon.md).
 
 ### Custom CSR's  
-note: The following csr's defined in `source/core_rrv` core.
+note: The following csr's defined in `source/big_core` core.
 - timer interrupt exception csr's:
   - `csr_custom_mtime` - Used to measure time of our system. This csr is read only from software and can be updated only in HW. Each clock it decrements by one. Used only in machine mode.
   - `csr_cutome_mtimecmp` - This csr is RW csr and used for comparison with `custom_mtime`. We use it in Timer interrupt exception.

docs/rvc/big_core/exceptions.md

@@ -31,13 +31,13 @@ Illegal instruction is a synchronous exception because its origin comes from the
 - Compiler errors (very rare but possible).
 
 ### Cases in our core
-For more details, please refer to `/source/core_rrv/illegal_instruction.vh`
+For more details, please refer to `/source/big_core/illegal_instruction.vh`
 - Some of the `Funct7` fields in R-type instructions do not zero
 - `Funct3` do not match the instruction. For example we try to execute S-type instruction and `Funct3  = 111`.
 - Un recognized OpCode that not supported by the core or not allowed by the spec.
 
 ### Illegal Instruction Generation
-- We use the test `/verif/core_rrv/alive_illegal.c`.
+- We use the test `/verif/big_core/alive_illegal.c`.
 - We try to create an instruction with illegal `FUCT7`, we generate `slli` with funct7 = 0x7f instead of 0x0
 ```
    // This instruction is trying to generate slli instruction with illegal FUNCT7.

docs/rvc/big_core/pmon.md

@@ -23,8 +23,8 @@ The same goes for `instret` and `instreth` which are named `CSR_INSTRET_LOW` and
 - After we calculate the number of valid instructions and clock cycles, we can calculate the CPI and IPC. The CPI is calculated by dividing the number of clock cycles by the number of instructions. The IPC is calculated by dividing the number of instructions by the number of clock cycles.
 
 ### realistic example
-- The task that calculates the CPI and IPC is located at the `verif/core_rrv/tb` folder[^2] 
-- We run the following test named `alive.c` on the core_rrv with 6 pipeline stages:
+- The task that calculates the CPI and IPC is located at the `verif/big_core/tb` folder[^2] 
+- We run the following test named `alive.c` on the big_core with 6 pipeline stages:
 ```
 int sum(int x, int y){
     return x + y;

docs/rvc/core_verification/checker_tasks.md

@@ -73,40 +73,40 @@ The tasks in this file keep a record of all the information stored in the regist
 # rf_write_history size     = 45
 #  >> rf_write_history[0] Mismatch!!
 # ** Error: ERROR: rf_write_history mismatch
-#    Time: 730 ps  Scope: big_core_rrv_tb.di_register_write File: ../../../verif/big_core_rrv/tb/mini_core_tasks.vh Line: 84
+#    Time: 730 ps  Scope: big_big_core_tb.di_register_write File: ../../../verif/big_big_core/tb/mini_core_tasks.vh Line: 84
 #       ref_rf_write_history[0] =   {time: 150, Pc: 00000014, RegDst:  1, Data: 00000000}
 #       rf_write_history    [0] =   {time: 200, Pc: 00000014, RegDst:  1, Data: 00000001}
 #  >> rf_write_history[1] Mismatch!!
 # ** Error: ERROR: rf_write_history mismatch
-#    Time: 730 ps  Scope: big_core_rrv_tb.di_register_write File: ../../../verif/big_core_rrv/tb/mini_core_tasks.vh Line: 84
+#    Time: 730 ps  Scope: big_big_core_tb.di_register_write File: ../../../verif/big_big_core/tb/mini_core_tasks.vh Line: 84
 #       ref_rf_write_history[1] =   {time: 160, Pc: 00000018, RegDst:  2, Data: 00000000}
 #       rf_write_history    [1] =   {time: 210, Pc: 00000018, RegDst:  2, Data: 00000002}
 #  >> rf_write_history[2] Mismatch!!
 # ** Error: ERROR: rf_write_history mismatch
-#    Time: 730 ps  Scope: big_core_rrv_tb.di_register_write File: ../../../verif/big_core_rrv/tb/mini_core_tasks.vh Line: 84
+#    Time: 730 ps  Scope: big_big_core_tb.di_register_write File: ../../../verif/big_big_core/tb/mini_core_tasks.vh Line: 84
 #       ref_rf_write_history[2] =   {time: 170, Pc: 0000001c, RegDst:  3, Data: 00000000}
 #       rf_write_history    [2] =   {time: 220, Pc: 0000001c, RegDst:  3, Data: 00000002}
 #  >> rf_write_history[3] Mismatch!!
 # ** Error: ERROR: rf_write_history mismatch
-#    Time: 730 ps  Scope: big_core_rrv_tb.di_register_write File: ../../../verif/big_core_rrv/tb/mini_core_tasks.vh Line: 84
+#    Time: 730 ps  Scope: big_big_core_tb.di_register_write File: ../../../verif/big_big_core/tb/mini_core_tasks.vh Line: 84
 #       ref_rf_write_history[3] =   {time: 180, Pc: 00000020, RegDst:  4, Data: 00000000}
 #       rf_write_history    [3] =   {time: 230, Pc: 00000020, RegDst:  4, Data: 00000002}
 #  >> rf_write_history[4] Mismatch!!
 # ** Error: ERROR: rf_write_history mismatch
-#    Time: 730 ps  Scope: big_core_rrv_tb.di_register_write File: ../../../verif/big_core_rrv/tb/mini_core_tasks.vh Line: 84
+#    Time: 730 ps  Scope: big_big_core_tb.di_register_write File: ../../../verif/big_big_core/tb/mini_core_tasks.vh Line: 84
 #       ref_rf_write_history[4] =   {time: 190, Pc: 00000024, RegDst:  5, Data: 00000000}
 #       rf_write_history    [4] =   {time: 240, Pc: 00000024, RegDst:  5, Data: 00000002}
 #  >> rf_write_history[5] Mismatch!!
 # ** Error: ERROR: rf_write_history mismatch
-#    Time: 730 ps  Scope: big_core_rrv_tb.di_register_write File: ../../../verif/big_core_rrv/tb/mini_core_tasks.vh Line: 84
+#    Time: 730 ps  Scope: big_big_core_tb.di_register_write File: ../../../verif/big_big_core/tb/mini_core_tasks.vh Line: 84
 #       ref_rf_write_history[5] =   {time: 200, Pc: 00000028, RegDst:  6, Data: 00000000}
 #       rf_write_history    [5] =   {time: 250, Pc: 00000028, RegDst:  6, Data: 00000002}
 .
 .
 .
 #  >> rf_write_history[44] Mismatch!!
 # ** Error: ERROR: rf_write_history mismatch
-#    Time: 730 ps  Scope: big_core_rrv_tb.di_register_write File: ../../../verif/big_core_rrv/tb/mini_core_tasks.vh Line: 84
+#    Time: 730 ps  Scope: big_big_core_tb.di_register_write File: ../../../verif/big_big_core/tb/mini_core_tasks.vh Line: 84
 #       ref_rf_write_history[44] =   {time: 630, Pc: 00000188, RegDst:  2, Data: 0001f000}
 #       rf_write_history    [44] =   {time: 720, Pc: 00000189, RegDst:  2, Data: 0001f004}
 # rf_write_history size match