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i2c_master.c
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/* Copyright 2013 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/* I2C cross-platform code for Chrome EC */
#include "battery.h"
#include "clock.h"
#include "charge_state.h"
#include "console.h"
#include "crc8.h"
#include "host_command.h"
#include "gpio.h"
#include "i2c.h"
#include "i2c_bitbang.h"
#include "i2c_private.h"
#include "system.h"
#include "task.h"
#include "usb_pd.h"
#include "usb_pd_tcpm.h"
#include "util.h"
#include "watchdog.h"
#include "virtual_battery.h"
/* Delay for bitbanging i2c corresponds roughly to 100kHz. */
#define I2C_BITBANG_DELAY_US 5
/* Number of attempts to unwedge each pin. */
#define UNWEDGE_SCL_ATTEMPTS 10
#define UNWEDGE_SDA_ATTEMPTS 3
#define CPUTS(outstr) cputs(CC_I2C, outstr)
#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args)
#define CPRINTF(format, args...) cprintf(CC_I2C, format, ## args)
/* Only chips with multi-port controllers will define I2C_CONTROLLER_COUNT */
#ifndef I2C_CONTROLLER_COUNT
#define I2C_CONTROLLER_COUNT I2C_PORT_COUNT
#endif
#ifndef CONFIG_I2C_BITBANG
#define I2C_BITBANG_PORT_COUNT 0
#endif
static struct mutex port_mutex[I2C_CONTROLLER_COUNT + I2C_BITBANG_PORT_COUNT];
/* A bitmap of the controllers which are currently servicing a request. */
static uint32_t i2c_port_active_list;
BUILD_ASSERT(ARRAY_SIZE(port_mutex) < 32);
static uint8_t port_protected[I2C_PORT_COUNT + I2C_BITBANG_PORT_COUNT];
/**
* Non-deterministically test the lock status of the port. If another task
* has locked the port and the caller is accessing it illegally, then this test
* will incorrectly return true. However, callers which failed to statically
* lock the port will fail quickly.
*/
static int i2c_port_is_locked(int port)
{
#ifdef CONFIG_I2C_MULTI_PORT_CONTROLLER
/* Test the controller, not the port */
port = i2c_port_to_controller(port);
#endif
/* can't lock a non-existing port */
if (port < 0)
return 0;
return (i2c_port_active_list >> port) & 1;
}
const struct i2c_port_t *get_i2c_port(const int port)
{
int i;
/* Find the matching port in i2c_ports[] table. */
for (i = 0; i < i2c_ports_used; i++) {
if (i2c_ports[i].port == port)
return &i2c_ports[i];
}
if (IS_ENABLED(CONFIG_I2C_BITBANG)) {
for (i = 0; i < i2c_bitbang_ports_used; i++) {
if (i2c_bitbang_ports[i].port == port)
return &i2c_bitbang_ports[i];
}
}
return NULL;
}
static int chip_i2c_xfer_with_notify(const int port,
const uint16_t slave_addr_flags,
const uint8_t *out, int out_size,
uint8_t *in, int in_size, int flags)
{
int ret;
uint16_t addr_flags = slave_addr_flags;
const struct i2c_port_t *i2c_port = get_i2c_port(port);
ASSERT(i2c_port);
if (IS_ENABLED(CONFIG_I2C_XFER_BOARD_CALLBACK))
i2c_start_xfer_notify(port, slave_addr_flags);
if (IS_ENABLED(CONFIG_SMBUS_PEC))
/*
* Since we've done PEC processing here,
* remove the flag so it won't confuse chip driver.
*/
addr_flags &= ~I2C_FLAG_PEC;
if (i2c_port->drv)
ret = i2c_port->drv->xfer(i2c_port, addr_flags,
out, out_size, in, in_size, flags);
else
ret = chip_i2c_xfer(port, addr_flags,
out, out_size, in, in_size, flags);
if (IS_ENABLED(CONFIG_I2C_XFER_BOARD_CALLBACK))
i2c_end_xfer_notify(port, slave_addr_flags);
if (IS_ENABLED(CONFIG_I2C_DEBUG)) {
i2c_trace_notify(port, slave_addr_flags, out, out_size,
in, in_size);
}
return ret;
}
#ifdef CONFIG_I2C_XFER_LARGE_READ
/*
* Internal function that splits reading into multiple chip_i2c_xfer() calls
* if in_size exceeds CONFIG_I2C_CHIP_MAX_READ_SIZE.
*/
static int i2c_xfer_no_retry(const int port,
const uint16_t slave_addr_flags,
const uint8_t *out, int out_size,
uint8_t *in, int in_size, int flags)
{
int ret;
int out_flags = flags & I2C_XFER_START;
int in_chunk_size = MIN(in_size, CONFIG_I2C_CHIP_MAX_READ_SIZE);
in_size -= in_chunk_size;
out_flags |= !in_size ? (flags & I2C_XFER_STOP) : 0;
ret = chip_i2c_xfer_with_notify(port, slave_addr_flags,
out, out_size, in,
in_chunk_size, out_flags);
in += in_chunk_size;
while (in_size && ret == EC_SUCCESS) {
in_chunk_size = MIN(in_size, CONFIG_I2C_CHIP_MAX_READ_SIZE);
in_size -= in_chunk_size;
ret = chip_i2c_xfer_with_notify(port, slave_addr_flags,
NULL, 0, in,
in_chunk_size, !in_size ? (flags & I2C_XFER_STOP) : 0);
in += in_chunk_size;
}
return ret;
}
#endif /* CONFIG_I2C_XFER_LARGE_READ */
int i2c_xfer_unlocked(const int port,
const uint16_t slave_addr_flags,
const uint8_t *out, int out_size,
uint8_t *in, int in_size, int flags)
{
int i;
int ret = EC_SUCCESS;
uint16_t addr_flags = slave_addr_flags & ~I2C_FLAG_PEC;
if (!i2c_port_is_locked(port)) {
CPUTS("Access I2C without lock!");
return EC_ERROR_INVAL;
}
for (i = 0; i <= CONFIG_I2C_NACK_RETRY_COUNT; i++) {
#ifdef CONFIG_I2C_XFER_LARGE_READ
ret = i2c_xfer_no_retry(port, addr_flags,
out, out_size, in,
in_size, flags);
#else
ret = chip_i2c_xfer_with_notify(port, addr_flags,
out, out_size,
in, in_size, flags);
#endif /* CONFIG_I2C_XFER_LARGE_READ */
if (ret != EC_ERROR_BUSY)
break;
}
return ret;
}
int i2c_xfer(const int port,
const uint16_t slave_addr_flags,
const uint8_t *out, int out_size,
uint8_t *in, int in_size)
{
int rv;
i2c_lock(port, 1);
rv = i2c_xfer_unlocked(port, slave_addr_flags,
out, out_size, in, in_size,
I2C_XFER_SINGLE);
i2c_lock(port, 0);
return rv;
}
void i2c_lock(int port, int lock)
{
#ifdef CONFIG_I2C_MULTI_PORT_CONTROLLER
/* Lock the controller, not the port */
port = i2c_port_to_controller(port);
#endif
if (port < 0)
return;
if (lock) {
mutex_lock(port_mutex + port);
/* Disable interrupt during changing counter for preemption. */
interrupt_disable();
i2c_port_active_list |= 1 << port;
/* Ec cannot enter sleep if there's any i2c port active. */
disable_sleep(SLEEP_MASK_I2C_MASTER);
interrupt_enable();
} else {
interrupt_disable();
i2c_port_active_list &= ~BIT(port);
/* Once there is no i2c port active, enable sleep bit of i2c. */
if (!i2c_port_active_list)
enable_sleep(SLEEP_MASK_I2C_MASTER);
interrupt_enable();
mutex_unlock(port_mutex + port);
}
}
void i2c_prepare_sysjump(void)
{
int i;
/* Lock all i2c controllers */
for (i = 0; i < ARRAY_SIZE(port_mutex); ++i)
mutex_lock(port_mutex + i);
}
/* i2c_readN with optional error checking */
static int i2c_read(const int port, const uint16_t slave_addr_flags,
uint8_t reg, uint8_t *in, int in_size)
{
if (!IS_ENABLED(CONFIG_SMBUS_PEC) && I2C_USE_PEC(slave_addr_flags))
return EC_ERROR_UNIMPLEMENTED;
if (IS_ENABLED(CONFIG_SMBUS_PEC) && I2C_USE_PEC(slave_addr_flags)) {
int i, rv;
/* addr_8bit = 7 bit addr_flags + 1 bit r/w */
uint8_t addr_8bit = I2C_GET_ADDR(slave_addr_flags) << 1;
uint8_t out[3] = {addr_8bit, reg, addr_8bit | 1};
uint8_t pec_local = 0, pec_remote;
i2c_lock(port, 1);
for (i = 0; i <= CONFIG_I2C_NACK_RETRY_COUNT; i++) {
rv = i2c_xfer_unlocked(port, slave_addr_flags, ®, 1,
in, in_size, I2C_XFER_START);
if (rv)
continue;
rv = i2c_xfer_unlocked(port, slave_addr_flags, NULL, 0,
&pec_remote, 1, I2C_XFER_STOP);
if (rv)
continue;
pec_local = crc8(out, ARRAY_SIZE(out));
pec_local = crc8_arg(in, in_size, pec_local);
if (pec_local == pec_remote)
break;
rv = EC_ERROR_CRC;
}
i2c_lock(port, 0);
return rv;
}
return i2c_xfer(port, slave_addr_flags, ®, 1, in, in_size);
}
/* i2c_writeN with optional error checking */
static int i2c_write(const int port, const uint16_t slave_addr_flags,
const uint8_t *out, int out_size)
{
if (!IS_ENABLED(CONFIG_SMBUS_PEC) && I2C_USE_PEC(slave_addr_flags))
return EC_ERROR_UNIMPLEMENTED;
if (IS_ENABLED(CONFIG_SMBUS_PEC) && I2C_USE_PEC(slave_addr_flags)) {
int i, rv;
uint8_t addr_8bit = I2C_GET_ADDR(slave_addr_flags) << 1;
uint8_t pec;
pec = crc8(&addr_8bit, 1);
pec = crc8_arg(out, out_size, pec);
i2c_lock(port, 1);
for (i = 0; i <= CONFIG_I2C_NACK_RETRY_COUNT; i++) {
rv = i2c_xfer_unlocked(port, slave_addr_flags,
out, out_size, NULL, 0,
I2C_XFER_START);
if (rv)
continue;
rv = i2c_xfer_unlocked(port, slave_addr_flags,
&pec, 1, NULL, 0,
I2C_XFER_STOP);
if (!rv)
break;
}
i2c_lock(port, 0);
return rv;
}
return i2c_xfer(port, slave_addr_flags, out, out_size, NULL, 0);
}
int i2c_read32(const int port,
const uint16_t slave_addr_flags,
int offset, int *data)
{
int rv;
uint8_t reg, buf[sizeof(uint32_t)];
reg = offset & 0xff;
/* I2C read 32-bit word: transmit 8-bit offset, and read 32bits */
rv = i2c_read(port, slave_addr_flags, reg, buf, sizeof(uint32_t));
if (rv)
return rv;
if (I2C_IS_BIG_ENDIAN(slave_addr_flags))
*data = ((int)buf[0] << 24) | ((int)buf[1] << 16) |
((int)buf[0] << 8) | buf[1];
else
*data = ((int)buf[3] << 24) | ((int)buf[2] << 16) |
((int)buf[1] << 8) | buf[0];
return EC_SUCCESS;
}
int i2c_write32(const int port,
const uint16_t slave_addr_flags,
int offset, int data)
{
uint8_t buf[1 + sizeof(uint32_t)];
buf[0] = offset & 0xff;
if (I2C_IS_BIG_ENDIAN(slave_addr_flags)) {
buf[1] = (data >> 24) & 0xff;
buf[2] = (data >> 16) & 0xff;
buf[3] = (data >> 8) & 0xff;
buf[4] = data & 0xff;
} else {
buf[1] = data & 0xff;
buf[2] = (data >> 8) & 0xff;
buf[3] = (data >> 16) & 0xff;
buf[4] = (data >> 24) & 0xff;
}
return i2c_write(port, slave_addr_flags, buf, sizeof(uint32_t) + 1);
}
int i2c_read16(const int port,
const uint16_t slave_addr_flags,
int offset, int *data)
{
int rv;
uint8_t reg, buf[sizeof(uint16_t)];
reg = offset & 0xff;
/* I2C read 16-bit word: transmit 8-bit offset, and read 16bits */
rv = i2c_read(port, slave_addr_flags, reg, buf, sizeof(uint16_t));
if (rv)
return rv;
if (I2C_IS_BIG_ENDIAN(slave_addr_flags))
*data = ((int)buf[0] << 8) | buf[1];
else
*data = ((int)buf[1] << 8) | buf[0];
return EC_SUCCESS;
}
int i2c_write16(const int port,
const uint16_t slave_addr_flags,
int offset, int data)
{
uint8_t buf[1 + sizeof(uint16_t)];
buf[0] = offset & 0xff;
if (I2C_IS_BIG_ENDIAN(slave_addr_flags)) {
buf[1] = (data >> 8) & 0xff;
buf[2] = data & 0xff;
} else {
buf[1] = data & 0xff;
buf[2] = (data >> 8) & 0xff;
}
return i2c_write(port, slave_addr_flags, buf, 1 + sizeof(uint16_t));
}
int i2c_read8(const int port,
const uint16_t slave_addr_flags,
int offset, int *data)
{
int rv;
uint8_t reg = offset;
uint8_t buf;
reg = offset;
rv = i2c_read(port, slave_addr_flags, reg, &buf, sizeof(uint8_t));
if (!rv)
*data = buf;
return rv;
}
int i2c_write8(const int port,
const uint16_t slave_addr_flags,
int offset, int data)
{
uint8_t buf[2];
buf[0] = offset;
buf[1] = data;
return i2c_write(port, slave_addr_flags, buf, sizeof(buf));
}
int i2c_update8(const int port,
const uint16_t slave_addr_flags,
const int offset,
const uint8_t mask,
const enum mask_update_action action)
{
int rv;
int read_val;
int write_val;
rv = i2c_read8(port, slave_addr_flags, offset, &read_val);
if (rv)
return rv;
write_val = (action == MASK_SET) ? (read_val | mask)
: (read_val & ~mask);
if (IS_ENABLED(CONFIG_I2C_UPDATE_IF_CHANGED) && write_val == read_val)
return EC_SUCCESS;
return i2c_write8(port, slave_addr_flags, offset, write_val);
}
int i2c_update16(const int port,
const uint16_t slave_addr_flags,
const int offset,
const uint16_t mask,
const enum mask_update_action action)
{
int rv;
int read_val;
int write_val;
rv = i2c_read16(port, slave_addr_flags, offset, &read_val);
if (rv)
return rv;
write_val = (action == MASK_SET) ? (read_val | mask)
: (read_val & ~mask);
if (IS_ENABLED(CONFIG_I2C_UPDATE_IF_CHANGED) && write_val == read_val)
return EC_SUCCESS;
return i2c_write16(port, slave_addr_flags, offset, write_val);
}
int i2c_field_update8(const int port,
const uint16_t slave_addr_flags,
const int offset,
const uint8_t field_mask,
const uint8_t set_value)
{
int rv;
int read_val;
int write_val;
rv = i2c_read8(port, slave_addr_flags, offset, &read_val);
if (rv)
return rv;
write_val = (read_val & (~field_mask)) | set_value;
if (IS_ENABLED(CONFIG_I2C_UPDATE_IF_CHANGED) && write_val == read_val)
return EC_SUCCESS;
return i2c_write8(port, slave_addr_flags, offset, write_val);
}
int i2c_field_update16(const int port,
const uint16_t slave_addr_flags,
const int offset,
const uint16_t field_mask,
const uint16_t set_value)
{
int rv;
int read_val;
int write_val;
rv = i2c_read16(port, slave_addr_flags, offset, &read_val);
if (rv)
return rv;
write_val = (read_val & (~field_mask)) | set_value;
if (IS_ENABLED(CONFIG_I2C_UPDATE_IF_CHANGED) && write_val == read_val)
return EC_SUCCESS;
return i2c_write16(port, slave_addr_flags, offset, write_val);
}
int i2c_read_offset16(const int port,
const uint16_t slave_addr_flags,
uint16_t offset, int *data, int len)
{
int rv;
uint8_t buf[sizeof(uint16_t)], addr[sizeof(uint16_t)];
if (len < 0 || len > 2)
return EC_ERROR_INVAL;
if (I2C_IS_ADDR16_LITTLE_ENDIAN(slave_addr_flags)) {
addr[0] = offset & 0xff;
addr[1] = (offset >> 8) & 0xff;
} else {
addr[0] = (offset >> 8) & 0xff;
addr[1] = offset & 0xff;
}
/* I2C read 16-bit word: transmit 16-bit offset, and read buffer */
rv = i2c_xfer(port, slave_addr_flags, addr, 2, buf, len);
if (rv)
return rv;
if (len == 1) {
*data = buf[0];
} else {
if (I2C_IS_BIG_ENDIAN(slave_addr_flags))
*data = ((int)buf[0] << 8) | buf[1];
else
*data = ((int)buf[1] << 8) | buf[0];
}
return EC_SUCCESS;
}
int i2c_write_offset16(const int port,
const uint16_t slave_addr_flags,
uint16_t offset, int data, int len)
{
uint8_t buf[2 + sizeof(uint16_t)];
if (len < 0 || len > 2)
return EC_ERROR_INVAL;
if (I2C_IS_ADDR16_LITTLE_ENDIAN(slave_addr_flags)) {
buf[0] = offset & 0xff;
buf[1] = (offset >> 8) & 0xff;
} else {
buf[0] = (offset >> 8) & 0xff;
buf[1] = offset & 0xff;
}
if (len == 1) {
buf[2] = data & 0xff;
} else {
if (I2C_IS_BIG_ENDIAN(slave_addr_flags)) {
buf[2] = (data >> 8) & 0xff;
buf[3] = data & 0xff;
} else {
buf[2] = data & 0xff;
buf[3] = (data >> 8) & 0xff;
}
}
return i2c_xfer(port, slave_addr_flags, buf, 2 + len, NULL, 0);
}
int i2c_read_offset16_block(const int port,
const uint16_t slave_addr_flags,
uint16_t offset, uint8_t *data, int len)
{
uint8_t addr[sizeof(uint16_t)];
if (I2C_IS_ADDR16_LITTLE_ENDIAN(slave_addr_flags)) {
addr[0] = offset & 0xff;
addr[1] = (offset >> 8) & 0xff;
} else {
addr[0] = (offset >> 8) & 0xff;
addr[1] = offset & 0xff;
}
return i2c_xfer(port, slave_addr_flags, addr, 2, data, len);
}
int i2c_write_offset16_block(const int port,
const uint16_t slave_addr_flags,
uint16_t offset, const uint8_t *data, int len)
{
int rv;
uint8_t addr[sizeof(uint16_t)];
if (I2C_IS_ADDR16_LITTLE_ENDIAN(slave_addr_flags)) {
addr[0] = offset & 0xff;
addr[1] = (offset >> 8) & 0xff;
} else {
addr[0] = (offset >> 8) & 0xff;
addr[1] = offset & 0xff;
}
/*
* Split into two transactions to avoid the stack space consumption of
* appending the destination address with the data array.
*/
i2c_lock(port, 1);
rv = i2c_xfer_unlocked(port, slave_addr_flags, addr, 2, NULL, 0,
I2C_XFER_START);
if (!rv)
rv = i2c_xfer_unlocked(port, slave_addr_flags,
data, len, NULL, 0, I2C_XFER_STOP);
i2c_lock(port, 0);
return rv;
}
int i2c_read_string(const int port,
const uint16_t slave_addr_flags,
int offset, uint8_t *data, int len)
{
int i, rv;
uint8_t reg, block_length;
if (!IS_ENABLED(CONFIG_SMBUS_PEC) && I2C_USE_PEC(slave_addr_flags))
return EC_ERROR_UNIMPLEMENTED;
reg = offset;
i2c_lock(port, 1);
for (i = 0; i <= CONFIG_I2C_NACK_RETRY_COUNT; i++) {
int data_length;
/*
* Send device reg space offset, and read back block length.
* Keep this session open without a stop.
*/
rv = i2c_xfer_unlocked(port, slave_addr_flags,
®, 1, &block_length, 1,
I2C_XFER_START);
if (rv)
continue;
if (len && block_length > (len - 1))
data_length = len - 1;
else
data_length = block_length;
if (IS_ENABLED(CONFIG_SMBUS_PEC) &&
I2C_USE_PEC(slave_addr_flags)) {
uint8_t addr_8bit = I2C_GET_ADDR(slave_addr_flags) << 1;
uint8_t out[3] = {addr_8bit, reg, addr_8bit | 1};
uint8_t pec, pec_remote;
rv = i2c_xfer_unlocked(port, slave_addr_flags,
0, 0, data, data_length, 0);
data[data_length] = 0;
if (rv)
continue;
pec = crc8(out, sizeof(out));
pec = crc8_arg(&block_length, 1, pec);
pec = crc8_arg(data, data_length, pec);
/* read all remaining bytes */
block_length -= data_length;
while (block_length) {
uint8_t byte;
rv = i2c_xfer_unlocked(port, slave_addr_flags,
NULL, 0, &byte, 1, 0);
if (rv)
break;
pec = crc8_arg(&byte, 1, pec);
--block_length;
}
if (rv)
continue;
rv = i2c_xfer_unlocked(port, slave_addr_flags, NULL, 0,
&pec_remote, 1, I2C_XFER_STOP);
if (rv)
continue;
if (pec != pec_remote)
rv = EC_ERROR_CRC;
} else {
rv = i2c_xfer_unlocked(port, slave_addr_flags,
0, 0, data, data_length,
I2C_XFER_STOP);
data[data_length] = 0;
if (rv)
continue;
}
/* execution reaches here implies rv=0, so we can exit now */
break;
}
i2c_lock(port, 0);
return rv;
}
int i2c_read_block(const int port,
const uint16_t slave_addr_flags,
int offset, uint8_t *data, int len)
{
int rv;
uint8_t reg_address = offset;
rv = i2c_xfer(port, slave_addr_flags, ®_address, 1, data, len);
return rv;
}
int i2c_write_block(const int port,
const uint16_t slave_addr_flags,
int offset, const uint8_t *data, int len)
{
int i, rv;
uint8_t reg_address = offset, pec = 0;
if (!IS_ENABLED(CONFIG_SMBUS_PEC) && I2C_USE_PEC(slave_addr_flags))
return EC_ERROR_UNIMPLEMENTED;
if (IS_ENABLED(CONFIG_SMBUS_PEC) && I2C_USE_PEC(slave_addr_flags)) {
uint8_t addr_8bit = I2C_GET_ADDR(slave_addr_flags) << 1;
pec = crc8(&addr_8bit, sizeof(uint8_t));
pec = crc8_arg(data, len, pec);
}
/*
* Split into two transactions to avoid the stack space consumption of
* appending the destination address with the data array.
*/
i2c_lock(port, 1);
for (i = 0; i <= CONFIG_I2C_NACK_RETRY_COUNT; i++) {
rv = i2c_xfer_unlocked(port, slave_addr_flags,
®_address, 1, NULL, 0,
I2C_XFER_START);
if (rv)
continue;
if (I2C_USE_PEC(slave_addr_flags)) {
rv = i2c_xfer_unlocked(port, slave_addr_flags,
data, len, NULL, 0, 0);
if (rv)
continue;
rv = i2c_xfer_unlocked(port, slave_addr_flags,
&pec, sizeof(uint8_t), NULL, 0,
I2C_XFER_STOP);
if (rv)
continue;
} else {
rv = i2c_xfer_unlocked(port, slave_addr_flags,
data, len, NULL, 0,
I2C_XFER_STOP);
if (rv)
continue;
}
/* execution reaches here implies rv=0, so we can exit now */
break;
}
i2c_lock(port, 0);
return rv;
}
int get_sda_from_i2c_port(int port, enum gpio_signal *sda)
{
const struct i2c_port_t *i2c_port = get_i2c_port(port);
/* Crash if the port given is not in the i2c_ports[] table. */
ASSERT(i2c_port);
/* Check if the SCL and SDA pins have been defined for this port. */
if (i2c_port->scl == 0 && i2c_port->sda == 0)
return EC_ERROR_INVAL;
*sda = i2c_port->sda;
return EC_SUCCESS;
}
int get_scl_from_i2c_port(int port, enum gpio_signal *scl)
{
const struct i2c_port_t *i2c_port = get_i2c_port(port);
/* Crash if the port given is not in the i2c_ports[] table. */
ASSERT(i2c_port);
/* Check if the SCL and SDA pins have been defined for this port. */
if (i2c_port->scl == 0 && i2c_port->sda == 0)
return EC_ERROR_INVAL;
*scl = i2c_port->scl;
return EC_SUCCESS;
}
void i2c_raw_set_scl(int port, int level)
{
enum gpio_signal g;
if (get_scl_from_i2c_port(port, &g) == EC_SUCCESS)
gpio_set_level(g, level);
}
void i2c_raw_set_sda(int port, int level)
{
enum gpio_signal g;
if (get_sda_from_i2c_port(port, &g) == EC_SUCCESS)
gpio_set_level(g, level);
}
int i2c_raw_mode(int port, int enable)
{
enum gpio_signal sda, scl;
int ret_sda, ret_scl;
/* Get the SDA and SCL pins for this port. If none, then return. */
if (get_sda_from_i2c_port(port, &sda) != EC_SUCCESS)
return EC_ERROR_INVAL;
if (get_scl_from_i2c_port(port, &scl) != EC_SUCCESS)
return EC_ERROR_INVAL;
if (enable) {
int raw_gpio_mode_flags = GPIO_ODR_HIGH;
/* If the CLK line is 1.8V, then ensure we set 1.8V mode */
if ((gpio_list + scl)->flags & GPIO_SEL_1P8V)
raw_gpio_mode_flags |= GPIO_SEL_1P8V;
/*
* To enable raw mode, take out of alternate function mode and
* set the flags to open drain output.
*/
ret_sda = gpio_config_pin(MODULE_I2C, sda, 0);
ret_scl = gpio_config_pin(MODULE_I2C, scl, 0);
gpio_set_flags(scl, raw_gpio_mode_flags);
gpio_set_flags(sda, raw_gpio_mode_flags);
} else {
/*
* Configure the I2C pins to exit raw mode and return
* to normal mode.
*/
ret_sda = gpio_config_pin(MODULE_I2C, sda, 1);
ret_scl = gpio_config_pin(MODULE_I2C, scl, 1);
}
return ret_sda == EC_SUCCESS ? ret_scl : ret_sda;
}
/*
* Unwedge the i2c bus for the given port.
*
* Some devices on our i2c busses keep power even if we get a reset. That
* means that they could be part way through a transaction and could be
* driving the bus in a way that makes it hard for us to talk on the bus.
* ...or they might listen to the next transaction and interpret it in a
* weird way.
*
* Note that devices could be in one of several states:
* - If a device got interrupted in a write transaction it will be watching
* for additional data to finish its write. It will probably be looking to
* ack the data (drive the data line low) after it gets everything.
* - If a device got interrupted while responding to a register read, it will
* be watching for clocks and will drive data out when it sees clocks. At
* the moment it might be trying to send out a 1 (so both clock and data
* may be high) or it might be trying to send out a 0 (so it's driving data
* low).
*
* We attempt to unwedge the bus by doing:
* - If SCL is being held low, then a slave is clock extending. The only
* thing we can do is try to wait until the slave stops clock extending.
* - Otherwise, we will toggle the clock until the slave releases the SDA line.
* Once the SDA line is released, try to send a STOP bit. Rinse and repeat
* until either the bus is normal, or we run out of attempts.
*
* Note this should work for most devices, but depending on the slaves i2c
* state machine, it may not be possible to unwedge the bus.
*/
int i2c_unwedge(int port)
{
int i, j;
int ret = EC_SUCCESS;
#ifdef CONFIG_I2C_BUS_MAY_BE_UNPOWERED
/*
* Don't try to unwedge the port if we know it's unpowered; it's futile.
*/
if (!board_is_i2c_port_powered(port)) {
CPRINTS("Skipping i2c unwedge, bus not powered.");
return EC_ERROR_NOT_POWERED;
}
#endif /* CONFIG_I2C_BUS_MAY_BE_UNPOWERED */
/* Try to put port in to raw bit bang mode. */
if (i2c_raw_mode(port, 1) != EC_SUCCESS)
return EC_ERROR_UNKNOWN;
/*
* If clock is low, wait for a while in case of clock stretched
* by a slave.
*/
if (!i2c_raw_get_scl(port)) {
for (i = 0;; i++) {
if (i >= UNWEDGE_SCL_ATTEMPTS) {
/*
* If we get here, a slave is holding the clock
* low and there is nothing we can do.
*/
CPRINTS("I2C%d unwedge failed, "
"SCL is held low", port);
ret = EC_ERROR_UNKNOWN;
goto unwedge_done;
}
udelay(I2C_BITBANG_DELAY_US);
if (i2c_raw_get_scl(port))
break;
}
}
if (i2c_raw_get_sda(port))
goto unwedge_done;
CPRINTS("I2C%d unwedge called with SDA held low", port);
/* Keep trying to unwedge the SDA line until we run out of attempts. */
for (i = 0; i < UNWEDGE_SDA_ATTEMPTS; i++) {
/* Drive the clock high. */
i2c_raw_set_scl(port, 1);
udelay(I2C_BITBANG_DELAY_US);
/*
* Clock through the problem by clocking out 9 bits. If slave
* releases the SDA line, then we can stop clocking bits and
* send a STOP.
*/
for (j = 0; j < 9; j++) {
if (i2c_raw_get_sda(port))
break;
i2c_raw_set_scl(port, 0);
udelay(I2C_BITBANG_DELAY_US);
i2c_raw_set_scl(port, 1);
udelay(I2C_BITBANG_DELAY_US);
}
/* Take control of SDA line and issue a STOP command. */
i2c_raw_set_sda(port, 0);
udelay(I2C_BITBANG_DELAY_US);
i2c_raw_set_sda(port, 1);
udelay(I2C_BITBANG_DELAY_US);
/* Check if the bus is unwedged. */
if (i2c_raw_get_sda(port) && i2c_raw_get_scl(port))
break;
}
if (!i2c_raw_get_sda(port)) {
CPRINTS("I2C%d unwedge failed, SDA still low", port);
ret = EC_ERROR_UNKNOWN;
}
if (!i2c_raw_get_scl(port)) {
CPRINTS("I2C%d unwedge failed, SCL still low", port);