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Zynq7000 demo w/SMP and single core support (#21)
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‎CORTEX_A9_Zynq7000_GCC/.gitignore‎

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*.o
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*.d

‎CORTEX_A9_Zynq7000_GCC/FreeRTOSDemo/CMakeLists.txt‎

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# Copyright (C) 2023 - 2024 Advanced Micro Devices, Inc. All rights reserved.
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# SPDX-License-Identifier: MIT
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cmake_minimum_required(VERSION 3.16)
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include(${CMAKE_CURRENT_SOURCE_DIR}/Hello_worldExample.cmake)
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include(${CMAKE_CURRENT_SOURCE_DIR}/UserConfig.cmake)
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set(APP_NAME hello_world)
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project(${APP_NAME})
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enable_language(C ASM CXX)
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find_package(common)
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collect(PROJECT_LIB_DEPS xilstandalone)
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collect(PROJECT_LIB_DEPS xil)
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collect(PROJECT_LIB_DEPS gcc)
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collect(PROJECT_LIB_DEPS c)
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collect (PROJECT_LIB_SOURCES platform.c)
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collect (PROJECT_LIB_SOURCES helloworld.c)
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collector_list (_sources PROJECT_LIB_SOURCES)
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foreach (source ${_sources})
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get_filename_component(ext ${source} EXT)
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list(APPEND src_ext ${ext})
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endforeach()
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find_project_type ("${src_ext}" PROJECT_TYPE)
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if("${PROJECT_TYPE}" STREQUAL "c++")
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collect(PROJECT_LIB_DEPS stdc++)
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endif()
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collector_list (_deps PROJECT_LIB_DEPS)
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list (APPEND _deps ${USER_LINK_LIBRARIES})
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if("${PROJECT_TYPE}" STREQUAL "c++")
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string (REPLACE ";" ",-l" _deps "${_deps}")
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endif()
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if(CMAKE_EXPORT_COMPILE_COMMANDS)
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set(CMAKE_CXX_STANDARD_INCLUDE_DIRECTORIES ${CMAKE_CXX_IMPLICIT_INCLUDE_DIRECTORIES})
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set(CMAKE_C_STANDARD_INCLUDE_DIRECTORIES ${CMAKE_C_IMPLICIT_INCLUDE_DIRECTORIES})
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endif()
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linker_gen("${CMAKE_CURRENT_SOURCE_DIR}/linker_files/")
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string(APPEND CMAKE_C_FLAGS ${USER_COMPILE_OPTIONS})
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string(APPEND CMAKE_CXX_FLAGS ${USER_COMPILE_OPTIONS})
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string(APPEND CMAKE_C_LINK_FLAGS ${USER_LINK_OPTIONS})
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string(APPEND CMAKE_CXX_LINK_FLAGS ${USER_LINK_OPTIONS})
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add_dependency_on_bsp(_sources)
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add_executable(${APP_NAME}.elf ${_sources})
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set_target_properties(${APP_NAME}.elf PROPERTIES LINK_DEPENDS ${USER_LINKER_SCRIPT})
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target_link_libraries(${APP_NAME}.elf -Wl,-T -Wl,\"${USER_LINKER_SCRIPT}\" -L\"${CMAKE_SOURCE_DIR}/\" -L\"${CMAKE_LIBRARY_PATH}/\" -L\"${USER_LINK_DIRECTORIES}/\" -Wl,--start-group,-l${_deps} -Wl,--end-group)
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target_compile_definitions(${APP_NAME}.elf PUBLIC ${USER_COMPILE_DEFINITIONS})
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target_include_directories(${APP_NAME}.elf PUBLIC ${USER_INCLUDE_DIRECTORIES})
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print_elf_size(CMAKE_SIZE ${APP_NAME})

‎CORTEX_A9_Zynq7000_GCC/FreeRTOSDemo/Demo/FreeRTOSConfig.h‎

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‎CORTEX_A9_Zynq7000_GCC/FreeRTOSDemo/Demo/IntQueueTimer.c‎

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/*
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* FreeRTOS V202212.00
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* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy of
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* this software and associated documentation files (the "Software"), to deal in
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* the Software without restriction, including without limitation the rights to
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* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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* the Software, and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* https://www.FreeRTOS.org
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* https://github.com/FreeRTOS
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*
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*/
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/*
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* This file initialises three timers as follows:
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*
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* Timer 0 and Timer 1 provide the interrupts that are used with the IntQ
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* standard demo tasks, which test interrupt nesting and using queues from
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* interrupts. Both these interrupts operate below the maximum syscall
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* interrupt priority.
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*
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* Timer 2 is a much higher frequency timer that tests the nesting of interrupts
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* that execute above the maximum syscall interrupt priority.
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*
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* All the timers can nest with the tick interrupt - creating a maximum
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* interrupt nesting depth of 4.
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*/
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/* Scheduler includes. */
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#include "FreeRTOS.h"
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/* Demo includes. */
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#include "IntQueueTimer.h"
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#include "IntQueue.h"
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/* Xilinx includes. */
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#include "xttcps.h"
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#include "xscugic.h"
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/* The frequencies at which the first two timers expire are slightly offset to
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ensure they don't remain synchronised. The frequency of the interrupt that
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operates above the max syscall interrupt priority is 10 times faster so really
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hammers the interrupt entry and exit code. */
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#define tmrTIMERS_USED 3
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#define tmrTIMER_0_FREQUENCY ( 2000UL )
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#define tmrTIMER_1_FREQUENCY ( 2001UL )
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#define tmrTIMER_2_FREQUENCY ( 20000UL )
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#if ( configNUMBER_OF_CORES > 1)
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/* NOTE: vInitialiseTimerForIntQueueTest is executed on one of the
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available cores because it is called, after the scheduler is initialized,
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inside one of the tasks created in IntQueue.c.
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The timers used to generate the interrupts are SPIs so every core
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can configure the interrupts for the core that should handle them.
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*/
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/* Core that handles the interrupts in multi-core. */
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#ifndef configINTERRUPT_QUEUE_TIMER_CORE
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#define tmrCORE portCORE0
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#else
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#if ( configINTERRUPT_QUEUE_TIMER_CORE < 0 || configINTERRUPT_QUEUE_TIMER_CORE >= configNUMBER_OF_CORES )
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#error Invalid core ID, accepted values must be 0 <= xCoreID < configNUMBER_OF_CORES.
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#endif
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#define tmrCORE configINTERRUPT_QUEUE_TIMER_CORE
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#endif
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#endif
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/*-----------------------------------------------------------*/
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/*
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* The single interrupt service routines that is used to service all three
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* timers.
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*/
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static void prvTimerHandler( void *CallBackRef );
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/*-----------------------------------------------------------*/
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/* Timer configuration settings. */
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typedef struct
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{
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uint32_t OutputHz; /* Output frequency. */
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uint16_t Interval; /* Interval value. */
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uint8_t Prescaler; /* Prescaler value. */
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uint16_t Options; /* Option settings. */
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} TmrCntrSetup;
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/* Hardware constants. */
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static const BaseType_t xDeviceIDs[ tmrTIMERS_USED ] = { XPAR_XTTCPS_0_DEVICE_ID, XPAR_XTTCPS_1_DEVICE_ID, XPAR_XTTCPS_2_DEVICE_ID };
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static const BaseType_t xInterruptIDs[ tmrTIMERS_USED ] = { XPAR_XTTCPS_0_INTR, XPAR_XTTCPS_1_INTR, XPAR_XTTCPS_2_INTR };
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/* Timer configuration settings. */
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static TmrCntrSetup xTimerSettings[ tmrTIMERS_USED ] =
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{
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{ tmrTIMER_0_FREQUENCY, 0, 0, XTTCPS_OPTION_INTERVAL_MODE | XTTCPS_OPTION_WAVE_DISABLE },
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{ tmrTIMER_1_FREQUENCY, 0, 0, XTTCPS_OPTION_INTERVAL_MODE | XTTCPS_OPTION_WAVE_DISABLE },
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{ tmrTIMER_2_FREQUENCY, 0, 0, XTTCPS_OPTION_INTERVAL_MODE | XTTCPS_OPTION_WAVE_DISABLE }
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};
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/* Lower priority number means higher logical priority, so
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configMAX_API_CALL_INTERRUPT_PRIORITY - 1 is above the maximum system call
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interrupt priority. */
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static const UBaseType_t uxInterruptPriorities[ tmrTIMERS_USED ] =
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{
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configMAX_API_CALL_INTERRUPT_PRIORITY + 1,
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configMAX_API_CALL_INTERRUPT_PRIORITY,
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configMAX_API_CALL_INTERRUPT_PRIORITY - 1
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};
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static XTtcPs xTimerInstances[ tmrTIMERS_USED ];
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/* Used to provide a means of ensuring the intended interrupt nesting depth is
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actually being reached. */
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#if ( configNUMBER_OF_CORES == 1 )
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extern volatile uint32_t ulPortInterruptNesting;
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#else
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extern volatile uint32_t ulPortInterruptNesting[ configNUMBER_OF_CORES ];
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#endif
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static uint32_t ulMaxRecordedNesting = 0;
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/* Used to ensure the high frequency timer is running at the expected
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frequency. */
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static volatile uint32_t ulHighFrequencyTimerCounts = 0;
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/*-----------------------------------------------------------*/
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#if ( configNUMBER_OF_CORES == 1 )
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void vInitialiseTimerForIntQueueTest( void )
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{
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BaseType_t xStatus;
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TmrCntrSetup *pxTimerSettings;
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extern XScuGic xInterruptController;
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BaseType_t xTimer;
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XTtcPs *pxTimerInstance;
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XTtcPs_Config *pxTimerConfiguration;
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const uint8_t ucHighLevel = 1;
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for( xTimer = 0; xTimer < tmrTIMERS_USED; xTimer++ )
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{
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/* Look up the timer's configuration. */
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pxTimerInstance = &( xTimerInstances[ xTimer ] );
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pxTimerConfiguration = XTtcPs_LookupConfig( xDeviceIDs[ xTimer ] );
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configASSERT( pxTimerConfiguration );
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pxTimerSettings = &( xTimerSettings[ xTimer ] );
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/* Initialise the device. */
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xStatus = XTtcPs_CfgInitialize( pxTimerInstance, pxTimerConfiguration, pxTimerConfiguration->BaseAddress );
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if( xStatus != XST_SUCCESS )
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{
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/* Not sure how to do this before XTtcPs_CfgInitialize is called
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as pxTimerInstance is set within XTtcPs_CfgInitialize(). */
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XTtcPs_Stop( pxTimerInstance );
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xStatus = XTtcPs_CfgInitialize( pxTimerInstance, pxTimerConfiguration, pxTimerConfiguration->BaseAddress );
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configASSERT( xStatus == XST_SUCCESS );
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}
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/* Set the options. */
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XTtcPs_SetOptions( pxTimerInstance, pxTimerSettings->Options );
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/* The timer frequency is preset in the pxTimerSettings structure.
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Derive the values for the other structure members. */
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XTtcPs_CalcIntervalFromFreq( pxTimerInstance, pxTimerSettings->OutputHz, &( pxTimerSettings->Interval ), &( pxTimerSettings->Prescaler ) );
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/* Set the interval and prescale. */
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XTtcPs_SetInterval( pxTimerInstance, pxTimerSettings->Interval );
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XTtcPs_SetPrescaler( pxTimerInstance, pxTimerSettings->Prescaler );
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/* The priority must be the lowest possible. */
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XScuGic_SetPriorityTriggerType( &xInterruptController, xInterruptIDs[ xTimer ], uxInterruptPriorities[ xTimer ] << portPRIORITY_SHIFT, ucHighLevel );
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/* Connect to the interrupt controller. */
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xStatus = XScuGic_Connect( &xInterruptController, xInterruptIDs[ xTimer ], ( Xil_InterruptHandler ) prvTimerHandler, ( void * ) pxTimerInstance );
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configASSERT( xStatus == XST_SUCCESS);
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/* Enable the interrupt in the GIC. */
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XScuGic_Enable( &xInterruptController, xInterruptIDs[ xTimer ] );
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/* Enable the interrupts in the timer. */
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XTtcPs_EnableInterrupts( pxTimerInstance, XTTCPS_IXR_INTERVAL_MASK );
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/* Start the timer. */
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XTtcPs_Start( pxTimerInstance );
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}
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}
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#else /* #if ( configNUMBER_OF_CORES == 1 ) */
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/* This function is also used to test the interrupt management
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APIs provided in the port layer for the applications. */
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void vInitialiseTimerForIntQueueTest( void )
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{
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BaseType_t xStatus;
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TmrCntrSetup *pxTimerSettings;
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BaseType_t xTimer;
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XTtcPs *pxTimerInstance;
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XTtcPs_Config *pxTimerConfiguration;
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const uint8_t ucHighLevel = 1;
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for( xTimer = 0; xTimer < tmrTIMERS_USED; xTimer++ )
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{
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/* Look up the timer's configuration. */
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pxTimerInstance = &( xTimerInstances[ xTimer ] );
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pxTimerConfiguration = XTtcPs_LookupConfig( xDeviceIDs[ xTimer ] );
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configASSERT( pxTimerConfiguration );
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pxTimerSettings = &( xTimerSettings[ xTimer ] );
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/* Initialise the device. */
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xStatus = XTtcPs_CfgInitialize( pxTimerInstance, pxTimerConfiguration, pxTimerConfiguration->BaseAddress );
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if( xStatus != XST_SUCCESS )
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{
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/* Not sure how to do this before XTtcPs_CfgInitialize is called
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as pxTimerInstance is set within XTtcPs_CfgInitialize(). */
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XTtcPs_Stop( pxTimerInstance );
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xStatus = XTtcPs_CfgInitialize( pxTimerInstance, pxTimerConfiguration, pxTimerConfiguration->BaseAddress );
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configASSERT( xStatus == XST_SUCCESS );
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}
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/* Set the options. */
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XTtcPs_SetOptions( pxTimerInstance, pxTimerSettings->Options );
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/* The timer frequency is preset in the pxTimerSettings structure.
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Derive the values for the other structure members. */
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XTtcPs_CalcIntervalFromFreq( pxTimerInstance, pxTimerSettings->OutputHz, &( pxTimerSettings->Interval ), &( pxTimerSettings->Prescaler ) );
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/* Set the interval and prescale. */
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XTtcPs_SetInterval( pxTimerInstance, pxTimerSettings->Interval );
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XTtcPs_SetPrescaler( pxTimerInstance, pxTimerSettings->Prescaler );
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/* The priority must be the lowest possible. */
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vPortConfigureInterrupt( xInterruptIDs[ xTimer ], uxInterruptPriorities[ xTimer ] << portPRIORITY_SHIFT, ucHighLevel);
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/* Connect to the interrupt controller. */
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vPortInstallInterruptHandler( xInterruptIDs[ xTimer ], ( Xil_InterruptHandler ) prvTimerHandler, ( void * ) pxTimerInstance );
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/* Enable the interrupt in the GIC for the selected core. */
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vPortEnableInterrupt( xInterruptIDs[ xTimer ], tmrCORE );
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/* Enable the interrupts in the timer. */
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XTtcPs_EnableInterrupts( pxTimerInstance, XTTCPS_IXR_INTERVAL_MASK );
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/* Start the timer. */
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XTtcPs_Start( pxTimerInstance );
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}
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}
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#endif /* #if ( configNUMBER_OF_CORES == 1 ) */
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/*-----------------------------------------------------------*/
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static void prvTimerHandler( void *pvCallBackRef )
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{
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uint32_t ulInterruptStatus;
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XTtcPs *pxTimer = ( XTtcPs * ) pvCallBackRef;
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BaseType_t xYieldRequired;
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/* Read the interrupt status to clear the interrupt. */
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ulInterruptStatus = XTtcPs_GetInterruptStatus( pxTimer );
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__asm volatile ("DSB SY");
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__asm volatile ("ISB SY");
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/* Only one interrupt event type is expected. */
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configASSERT( ( XTTCPS_IXR_INTERVAL_MASK & ulInterruptStatus ) != 0 );
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( void ) ulInterruptStatus; /* Prevent compiler warning when configASSERT() is not defined. */
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/* Check the device ID to know which IntQueue demo to call. */
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if( pxTimer->Config.DeviceId == xDeviceIDs[ 0 ] )
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{
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xYieldRequired = xFirstTimerHandler();
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}
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else if( pxTimer->Config.DeviceId == xDeviceIDs[ 1 ] )
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{
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xYieldRequired = xSecondTimerHandler();
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}
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else
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{
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/* Used to check the timer is running at the expected frequency. */
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ulHighFrequencyTimerCounts++;
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xYieldRequired = pdFALSE;
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}
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#if ( configNUMBER_OF_CORES == 1 )
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/* Latch the highest interrupt nesting count detected. */
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if( ulPortInterruptNesting > ulMaxRecordedNesting )
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{
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ulMaxRecordedNesting = ulPortInterruptNesting;
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}
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#else
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/* Latch the highest interrupt nesting count detected. */
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if( ulPortInterruptNesting[ tmrCORE ] > ulMaxRecordedNesting )
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{
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ulMaxRecordedNesting = ulPortInterruptNesting[ tmrCORE ];
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}
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/* Check that we are on the correct core. */
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configASSERT( portGET_CORE_ID() == tmrCORE );
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#endif
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/* If xYieldRequired is not pdFALSE then calling either xFirstTimerHandler()
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or xSecondTimerHandler() resulted in a task leaving the blocked state and
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the task that left the blocked state had a priority higher than the currently
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running task (the task this interrupt interrupted) - so a context switch
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should be performed so the interrupt returns directly to the higher priority
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task. xYieldRequired is tested inside the following macro. */
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portYIELD_FROM_ISR( xYieldRequired );
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}
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