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‎board/gameduino.brd

61 KB
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‎board/gameduino.sch

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‎doc/Gameduino_Reference_Manual_v0.pdf

1.74 MB
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‎fpga/ck_div.v

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module ck_div(
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input ck_in,
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output ck_out,
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input sys_rst_i
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//output locked;
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);
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parameter DIV_BY = 1;
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parameter MULT_BY = 1;
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wire ck_fb;
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//DCM #(
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// .CLKDV_DIVIDE(DIV_BY),
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// .DFS_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for frequency synthesis
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// .DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE
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// .STARTUP_WAIT("TRUE") // Delay configuration DONE until DCM LOCK, TRUE/FALSE
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//) DCM_inst (
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// .CLK0(ck_fb),
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// .CLKDV(ck_out),
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// .CLKFB(ck_fb), // DCM clock feedback
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// .CLKIN(ck_in), // Clock input (from IBUFG, BUFG or DCM)
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// .RST(0)
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//);
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DCM #(
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.CLKFX_MULTIPLY(MULT_BY),
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.CLKFX_DIVIDE(DIV_BY),
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.DFS_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for frequency synthesis
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.DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE
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.STARTUP_WAIT("TRUE") // Delay configuration DONE until DCM LOCK, TRUE/FALSE
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) DCM_inst (
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.CLK0(ck_fb),
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.CLKFX(ck_out),
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.CLKFB(ck_fb), // DCM clock feedback
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.CLKIN(ck_in), // Clock input (from IBUFG, BUFG or DCM)
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.RST(0)
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);
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//BUFG BUFG_inst(.I(ck_int), .O(ck_out));
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endmodule

‎fpga/ck_div.vhd

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module ck_div(
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input ck_in,
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output ck_out,
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input sys_rst_i
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//output locked;
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);
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parameter DIV_BY = 1;
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parameter MULT_BY = 1;
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wire ck_fb;
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//DCM #(
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// .CLKDV_DIVIDE(DIV_BY),
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// .DFS_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for frequency synthesis
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// .DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE
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// .STARTUP_WAIT("TRUE") // Delay configuration DONE until DCM LOCK, TRUE/FALSE
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//) DCM_inst (
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// .CLK0(ck_fb),
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// .CLKDV(ck_out),
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// .CLKFB(ck_fb), // DCM clock feedback
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// .CLKIN(ck_in), // Clock input (from IBUFG, BUFG or DCM)
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// .RST(0)
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//);
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DCM #(
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.CLKFX_MULTIPLY(MULT_BY),
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.CLKFX_DIVIDE(DIV_BY),
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.DFS_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for frequency synthesis
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.DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE
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.STARTUP_WAIT("TRUE") // Delay configuration DONE until DCM LOCK, TRUE/FALSE
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) DCM_inst (
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.CLK0(ck_fb),
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.CLKFX(ck_out),
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.CLKFB(ck_fb), // DCM clock feedback
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.CLKIN(ck_in), // Clock input (from IBUFG, BUFG or DCM)
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.RST(0)
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);
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//BUFG BUFG_inst(.I(ck_int), .O(ck_out));
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endmodule

‎fpga/fifo.v

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module fifo ( clk, datain, wr, dataout, rd, fullness);
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parameter WIDTH = 1;
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input clk;
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input [WIDTH-1:0] datain;
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input wr;
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output [WIDTH-1:0] dataout;
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input rd;
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output reg [4:0] fullness;
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always @(posedge clk)
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begin
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fullness <= (fullness + wr - rd);
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end
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wire [3:0] readaddr = (fullness - 1);
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genvar i;
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generate
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for (i = 0; i < WIDTH; i=i+1) begin : srl16
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SRL16E fifo16(
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.CLK(clk),
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.CE(wr),
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.D(datain[i]),
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.A0(readaddr[0]),
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.A1(readaddr[1]),
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.A2(readaddr[2]),
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.A3(readaddr[3]),
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.Q(dataout[i]));
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end
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endgenerate
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endmodule

‎fpga/generated.v

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‎fpga/j0.v

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// J0 is a stripped-down J1.
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// Major changes:
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// stacks are only 16 deep
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// program counter is only 7 bits (128 instructions)
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// DEPTH and LSHIFT instructions removed
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// multiply and swab instructions added
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module j0(
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input sys_clk_i, input sys_rst_i,
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output [6:0] insn_addr,
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input [15:0] insn,
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output mem_rd,
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output mem_wr,
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output [15:0] mem_addr,
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output [15:0] mem_dout,
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input [15:0] mem_din,
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input pause
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);
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wire [15:0] immediate = { 1'b0, insn[14:0] };
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wire [15:0] ramrd;
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reg [4:0] dsp; // Data stack pointer
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reg [4:0] _dsp;
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reg [15:0] st0; // Top of data stack
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reg [15:0] _st0;
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wire dstkW; // D stack write
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reg [6:0] pc;
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reg [6:0] _pc;
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reg [4:0] rsp;
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reg [4:0] _rsp;
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reg rstkW; // R stack write
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reg [15:0] rstkD; // R stack write value
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wire [6:0] pc_plus_1 = pc + 1;
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// The D and R stacks
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reg [15:0] dstack[0:31];
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reg [15:0] rstack[0:31];
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wire [15:0] st1 = dstack[dsp];
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wire [15:0] rst0 = rstack[rsp];
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// st0sel is the ALU operation. For branch and call the operation
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// is T, for 0branch it is N. For ALU ops it is loaded from the instruction
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// field.
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reg [4:0] st0sel;
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always @*
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begin
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case (insn[14:13])
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2'b00: st0sel <= 0; // ubranch
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2'b10: st0sel <= 0; // call
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2'b01: st0sel <= 1; // 0branch
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2'b11: st0sel <= {insn[4], insn[11:8]}; // ALU
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default: st0sel <= 4'bxxxx;
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endcase
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// Compute the new value of T.
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if (insn[15])
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_st0 <= immediate;
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else
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case (st0sel)
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5'b00000: _st0 <= st0;
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5'b00001: _st0 <= st1;
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5'b00010: _st0 <= st0 + st1;
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5'b00011: _st0 <= st0 & st1;
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5'b00100: _st0 <= st0 | st1;
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5'b00101: _st0 <= st0 ^ st1;
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5'b00110: _st0 <= ~st0;
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5'b00111: _st0 <= {16{(st1 == st0)}};
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5'b01000: _st0 <= {16{($signed(st1) < $signed(st0))}};
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5'b01001: _st0 <= st1 >> st0[3:0];
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5'b01010: _st0 <= st0 - 1;
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5'b01011: _st0 <= rst0;
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5'b01100: _st0 <= mem_din;
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5'b01101: _st0 <= st1 * st0;
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5'b01110: _st0 <= {st0[7:0], st0[15:8]};
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5'b01111: _st0 <= {16{(st1 < st0)}};
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default: _st0 <= 16'hxxxx;
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endcase
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end
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wire is_alu = (insn[15:13] == 3'b011);
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wire is_lit = (insn[15]);
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// assign mem_rd = (is_alu & (insn[11:8] == 4'hc));
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assign mem_rd = (st0sel == 5'hc);
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assign mem_wr = is_alu & insn[5];
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assign mem_addr = st0;
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assign mem_dout = st1;
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assign dstkW = is_lit | (is_alu & insn[7]);
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wire [1:0] dd = insn[1:0]; // D stack delta
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wire [1:0] rd = insn[3:2]; // R stack delta
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always @*
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begin
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if (is_lit) begin // literal
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_dsp = dsp + 1;
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_rsp = rsp;
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rstkW = 0;
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rstkD = _pc;
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end else if (is_alu) begin // ALU
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_dsp = dsp + {dd[1], dd[1], dd[1], dd};
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_rsp = rsp + {rd[1], rd[1], rd[1], rd};
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rstkW = insn[6];
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rstkD = st0;
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end else begin // jump/call
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// predicated jump is like DROP
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if (insn[15:13] == 3'b001) begin
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_dsp = dsp - 1;
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end else begin
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_dsp = dsp;
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end
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if (insn[15:13] == 3'b010) begin // call
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_rsp = rsp + 1;
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rstkW = 1;
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rstkD = {pc_plus_1, 1'b0};
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end else begin
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_rsp = rsp;
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rstkW = 0;
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rstkD = _pc;
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end
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end
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if (sys_rst_i)
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_pc = pc;
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else
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if ((insn[15:13] == 3'b000) |
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((insn[15:13] == 3'b001) & (|st0 == 0)) |
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(insn[15:13] == 3'b010))
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_pc = insn[6:0];
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else if (is_alu & insn[12])
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_pc = rst0[7:1];
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else
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_pc = pc_plus_1;
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end
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assign insn_addr = pause ? pc : _pc;
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always @(posedge sys_clk_i)
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begin
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if (sys_rst_i) begin
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pc <= 0;
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dsp <= 0;
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st0 <= 0;
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rsp <= 0;
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end else if (!pause) begin
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pc <= _pc;
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dsp <= _dsp;
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st0 <= _st0;
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rsp <= _rsp;
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if (dstkW)
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dstack[_dsp] = st0;
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if (rstkW)
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rstack[_rsp] = rstkD;
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end
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end
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endmodule // j1

‎fpga/revision.v

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`define REVISION 8'h11

‎fpga/testtop.v

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module top(
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input SCK, // arduino 13
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input MOSI, // arduino 11
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inout MISO, // arduino 12
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input SSEL, // arduino 9
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output flashMOSI,
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input flashMISO,
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output flashSCK,
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output flashSSEL
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);
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assign flashMOSI = MOSI;
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assign MISO = flashMISO;
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assign flashSCK = SCK;
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assign flashSSEL = SSEL;
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endmodule // top

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