feat: init - modular and elliptic curve arithmetic operations

Author: Jakub Jaksik

HDL/eddsa/eddsa.sv

@@ -0,0 +1,15 @@
+package parameters_pkg;
+parameter int DATA_WIDTH = 448;
+// p = 2^448 - 2^224 - 1
+parameter logic [DATA_WIDTH-1:0] MODULUS = 448'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF;
+parameter logic [DATA_WIDTH-1:0] MODULUS_INV = 448'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF00000000000000000000000000000000000000000000000000000001;
+// R = 2^448
+parameter logic [DATA_WIDTH:0] R = 449'h10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
+parameter logic [DATA_WIDTH-1:0] R_MOD_P = 448'h100000000000000000000000000000000000000000000000000000001;
+parameter logic [DATA_WIDTH-1:0] R_INV = 448'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE00000000000000000000000000000000000000000000000000000001;
+parameter logic [DATA_WIDTH-1:0] R2_MOD_P = 448'h0000000000000000000000000000000000000000000000000000000300000000000000000000000000000000000000000000000000000002;
+
+// d = -39081
+// D = d*R Montgomery representation
+parameter logic [DATA_WIDTH-1:0] D = 448'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF6755FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF6756;
+endpackage

HDL/parameters_pkg.sv

@@ -0,0 +1,71 @@
+/*
+    Module: add
+
+    Description:
+    This module performs staged addition of two large inputs (a and b) with a bit width specified by 
+    the parameter SIZE. The width of SIZE must be divisible by 2. The module is designed 
+    with a typical input size of 448 bits in mind.
+
+    Parameters:
+    - SIZE: Bit width of the inputs, must be divisible by 2.
+
+    Inputs:
+    - clk   : Clock signal.
+    - rst   : Synchronous reset signal.
+    - start : Initiates the addition process.
+    - a, b  : Input operands with width SIZE.
+
+    Outputs:
+    - result   : Result of a + b, with a width of SIZE + 1 to accommodate any carry.
+    - done  : Asserted high when the addition is complete.
+
+    Operation:
+    - On `start`, the module begins adding `a` and `b` in 2 stages, each handling half of the bits.
+      The FSM controls the addition process across IDLE and STAGE1 states, with the 
+      final result in `result` once `done` is asserted.
+*/
+
+module add_2_parts #(
+    parameter int SIZE = 224 // Default bit width, must be divisible by 2
+)(
+    input  logic clk,
+    input  logic rst,
+    input  logic start,
+    input  [SIZE-1:0] a,       
+    input  [SIZE-1:0] b,       
+    output logic [SIZE:0] result,
+    output logic done
+);
+    typedef enum logic [1:0] {IDLE, STAGE1} state_t;
+    state_t state = IDLE;
+
+    logic [SIZE/2-1:0] partial_sum1;
+    logic carry;
+
+    always_ff@(posedge clk or posedge rst) begin
+        if (rst) begin
+            state <= IDLE;
+            done <= 1;
+            result <= 0;
+            partial_sum1 <= 0;
+            carry <= 0;
+        end else begin
+            case (state)
+                IDLE: begin
+                    if (start) begin
+                        {carry, partial_sum1} <= a[SIZE/2-1:0] + b[SIZE/2-1:0];
+                        state <= STAGE1;
+                        done <= 0;
+                    end 
+                end
+                STAGE1: begin
+                    result[SIZE:SIZE/2] <= a[SIZE-1:SIZE/2] + b[SIZE-1:SIZE/2] + carry;
+                    result[SIZE/2-1:0] <= partial_sum1;
+                    state <= IDLE;
+                    done <= 1;
+                end
+            endcase
+        end
+    end
+
+endmodule

HDL/primitives/arithmetic/add_2_parts.sv

@@ -0,0 +1,81 @@
+/*
+    Module: add
+
+    Description:
+    This module performs staged addition of two large inputs (a and b) with a bit width specified by 
+    the parameter SIZE. The width of SIZE must be divisible by 4. The module is designed 
+    with a typical input size of 448 bits in mind.
+
+    Parameters:
+    - SIZE: Bit width of the inputs, must be divisible by 4.
+
+    Inputs:
+    - clk   : Clock signal.
+    - rst   : Synchronous reset signal.
+    - start : Initiates the addition process.
+    - a, b  : Input operands with width SIZE.
+
+    Outputs:
+    - result   : Result of a + b, with a width of SIZE + 1 to accommodate any carry.
+    - done  : Asserted high when the addition is complete.
+
+    Operation:
+    - On `start`, the module begins adding `a` and `b` in 4 stages, each handling a quarter of the bits.
+      The FSM controls the addition process across IDLE, STAGE1, STAGE2, and STAGE3 states, with the 
+      final result in `result` once `done` is asserted.
+*/
+
+module add_4_parts #(
+    parameter int SIZE = 896 // Default bit width, must be divisible by 4
+)(
+    input  logic clk,
+    input  logic rst,
+    input  logic start,
+    input  [SIZE-1:0] a,       
+    input  [SIZE-1:0] b,       
+    output logic [SIZE:0] result,
+    output logic done
+);
+    typedef enum logic [1:0] {IDLE, STAGE1, STAGE2, STAGE3} state_t;
+    state_t state = IDLE;
+
+    logic [SIZE/4-1:0] partial_sum1, partial_sum2, partial_sum3;
+    logic carry;
+
+    always_ff@(posedge clk or posedge rst) begin
+        if (rst) begin
+            state <= IDLE;
+            done <= 1;
+            result <= 0;
+            partial_sum1 <= 0;
+            partial_sum2 <= 0;
+            partial_sum3 <= 0;
+            carry <= 0;
+        end else begin
+            case (state)
+                IDLE: begin
+                    if (start) begin
+                        {carry, partial_sum1} <= a[SIZE/4-1:0] + b[SIZE/4-1:0];
+                        state <= STAGE1;
+                        done <= 0;
+                    end 
+                end
+                STAGE1: begin
+                    {carry, partial_sum2} <= a[2*SIZE/4-1:SIZE/4] + b[2*SIZE/4-1:SIZE/4] + carry;
+                    state <= STAGE2;
+                end
+                STAGE2: begin
+                    {carry, partial_sum3} <= a[3*SIZE/4-1:2*SIZE/4] + b[3*SIZE/4-1:2*SIZE/4] + carry;
+                    state <= STAGE3;
+                end
+                STAGE3: begin
+                    result[SIZE:3*SIZE/4] <= a[4*SIZE/4-1:3*SIZE/4] + b[4*SIZE/4-1:3*SIZE/4] + carry;
+                    result[3*SIZE/4-1:0] <= {partial_sum3, partial_sum2, partial_sum1};
+                    state <= IDLE;
+                    done <= 1;
+                end
+            endcase
+        end
+    end
+
+endmodule

HDL/primitives/arithmetic/add_4_parts.sv

@@ -0,0 +1,101 @@
+/*
+    Module: add
+
+    Description:
+    This module performs staged addition of two large inputs (a and b) with a bit width specified by 
+    the parameter SIZE. The width of SIZE must be divisible by 8. The module is designed 
+    with a typical input size of 448 bits in mind.
+
+    Parameters:
+    - SIZE: Bit width of the inputs, must be divisible by 8.
+
+    Inputs:
+    - clk   : Clock signal.
+    - rst   : Synchronous reset signal.
+    - start : Initiates the addition process.
+    - a, b  : Input operands with width SIZE.
+
+    Outputs:
+    - result   : Result of a + b, with a width of SIZE + 1 to accommodate any carry.
+    - done  : Asserted high when the addition is complete.
+
+    Operation:
+    - On `start`, the module begins adding `a` and `b` in 8 stages, each handling an eighth of the bits.
+      The FSM controls the addition process across IDLE, STAGE1 to STAGE7 states, with the 
+      final result in `result` once `done` is asserted.
+*/
+
+module add_8_parts #(
+    parameter int SIZE = 896 // Default bit width, must be divisible by 8
+)(
+    input  logic clk,
+    input  logic rst,
+    input  logic start,
+    input  [SIZE-1:0] a,       
+    input  [SIZE-1:0] b,       
+    output logic [SIZE:0] result,
+    output logic done
+);
+    typedef enum logic [2:0] {IDLE, STAGE1, STAGE2, STAGE3, STAGE4, STAGE5, STAGE6, STAGE7} state_t;
+    state_t state = IDLE;
+
+    logic [SIZE/8-1:0] partial_sum1, partial_sum2, partial_sum3, partial_sum4, partial_sum5, partial_sum6, partial_sum7;
+    logic carry;
+
+    always_ff@(posedge clk or posedge rst) begin
+        if (rst) begin
+            state <= IDLE;
+            done <= 1;
+            result <= 0;
+            partial_sum1 <= 0;
+            partial_sum2 <= 0;
+            partial_sum3 <= 0;
+            partial_sum4 <= 0;
+            partial_sum5 <= 0;
+            partial_sum6 <= 0;
+            partial_sum7 <= 0;
+            carry <= 0;
+        end else begin
+            case (state) 
+                IDLE: begin
+                    if (start) begin
+                        {carry, partial_sum1} <= a[SIZE/8-1:0] + b[SIZE/8-1:0];
+                        state <= STAGE1;
+                        done <= 0;
+                    end 
+                end
+                STAGE1: begin
+                    {carry, partial_sum2} <= a[2*SIZE/8-1:SIZE/8] + b[2*SIZE/8-1:SIZE/8] + carry;
+                    state <= STAGE2;
+                end
+                STAGE2: begin
+                    {carry, partial_sum3} <= a[3*SIZE/8-1:2*SIZE/8] + b[3*SIZE/8-1:2*SIZE/8] + carry;
+                    state <= STAGE3;
+                end
+                STAGE3: begin
+                    {carry, partial_sum4} <= a[4*SIZE/8-1:3*SIZE/8] + b[4*SIZE/8-1:3*SIZE/8] + carry;
+                    state <= STAGE4;
+                end
+                STAGE4: begin
+                    {carry, partial_sum5} <= a[5*SIZE/8-1:4*SIZE/8] + b[5*SIZE/8-1:4*SIZE/8] + carry;
+                    state <= STAGE5;
+                end
+                STAGE5: begin
+                    {carry, partial_sum6} <= a[6*SIZE/8-1:5*SIZE/8] + b[6*SIZE/8-1:5*SIZE/8] + carry;
+                    state <= STAGE6;
+                end
+                STAGE6: begin
+                    {carry, partial_sum7} <= a[7*SIZE/8-1:6*SIZE/8] + b[7*SIZE/8-1:6*SIZE/8] + carry;
+                    state <= STAGE7;
+                end
+                STAGE7: begin
+                    result[SIZE:7*SIZE/8] <= a[8*SIZE/8-1:7*SIZE/8] + b[8*SIZE/8-1:7*SIZE/8] + carry;
+                    result[7*SIZE/8-1:0] <= {partial_sum7, partial_sum6, partial_sum5, partial_sum4, partial_sum3, partial_sum2, partial_sum1};
+                    state <= IDLE;
+                    done <= 1;
+                end
+            endcase
+        end
+    end
+
+endmodule

HDL/primitives/arithmetic/add_8_parts.sv

@@ -0,0 +1,85 @@
+module mul #(
+    parameter int SIZE = 448
+)(
+    input  logic clk,
+    input  logic rst,
+    input  logic start,
+    input  [SIZE-1:0] a,
+    input  [SIZE-1:0] b,
+    output logic [2*SIZE-1:0] result,
+    output logic done
+);
+    typedef enum logic [1:0] {IDLE, STAGE1, STAGE2, FINISH} state_t;
+    state_t state = IDLE;
+    
+    logic add_224_start, add_448_start, add_896_start;
+    logic add_224_done, add_448_done, add_896_done;
+    logic [SIZE/2-1:0] add_224_a, add_224_b,
+    logic [SIZE/2:0] add_224_result;
+    logic [SIZE-1:0] add_448_a, add_448_b,
+    logic [SIZE:0] add_448_result;
+    logic [2*SIZE-1:0] add_896_a, add_896_b,
+    logic [2*SIZE:0] add_896_result;
+
+    logic [2*SIZE-1:0] accumulated_result,
+
+    add_2_parts #(SIZE/2) adder_224 (
+        .clk(clk),
+        .rst(rst),
+        .start(add_224_start),
+        .a(add_224_a),
+        .b(add_224_b),
+        .result(add_224_result),
+        .done(add_224_done)
+    );
+
+    add_4_parts #(SIZE) adder_448 (
+        .clk(clk),
+        .rst(rst),
+        .start(add_448_start),
+        .a(add_448_a),
+        .b(add_448_b),
+        .result(add_448_result),
+        .done(add_448_done)
+    );
+
+    add_8_parts #(2*SIZE) adder_896 (
+        .clk(clk),
+        .rst(rst),
+        .start(add_896_start),
+        .a(add_896_a),
+        .b(add_896_b),
+        .result(add_896_result),
+        .done(add_896_done)
+    );
+
+    always_ff @(posedge clk or posedge rst) begin
+        if (rst) begin
+            state <= IDLE;
+            done <= 0;
+            accumulated_result <= 0;
+            add_224_start <= 0;
+            add_448_start <= 0;
+            add_896_start <= 0;
+        end else begin
+            case (state)
+                IDLE: begin
+                    if (start) begin
+                        state <= STAGE1;
+                        done <= 0;
+                    end
+                end
+                STAGE1: begin
+                    
+                end
+                STAGE2: begin
+                    
+                end
+                FINISH: begin
+
+                end
+            endcase
+        end
+    end
+endmodule
+