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| 1 | +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py |
| 2 | +; RUN: opt < %s -passes=vector-combine -S -mtriple=x86_64-- | FileCheck %s |
| 3 | + |
| 4 | +target datalayout = "e-p:64:64-i64:64-f80:128-n8:16:32:64-S128" |
| 5 | + |
| 6 | +; This would insert before a phi instruction which is invalid IR. |
| 7 | + |
| 8 | +define <4 x double> @PR60649() { |
| 9 | +; CHECK-LABEL: @PR60649( |
| 10 | +; CHECK-NEXT: entry: |
| 11 | +; CHECK-NEXT: br label [[END:%.*]] |
| 12 | +; CHECK: unreachable: |
| 13 | +; CHECK-NEXT: br label [[END]] |
| 14 | +; CHECK: end: |
| 15 | +; CHECK-NEXT: [[T0:%.*]] = phi <4 x double> [ zeroinitializer, [[ENTRY:%.*]] ], [ zeroinitializer, [[UNREACHABLE:%.*]] ] |
| 16 | +; CHECK-NEXT: [[T1:%.*]] = phi <4 x double> [ zeroinitializer, [[ENTRY]] ], [ zeroinitializer, [[UNREACHABLE]] ] |
| 17 | +; CHECK-NEXT: [[TMP0:%.*]] = shufflevector <4 x double> [[T0]], <4 x double> [[T0]], <4 x i32> <i32 2, i32 3, i32 undef, i32 undef> |
| 18 | +; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x double> [[T0]], <4 x double> [[T0]], <4 x i32> <i32 0, i32 1, i32 undef, i32 undef> |
| 19 | +; CHECK-NEXT: [[TMP2:%.*]] = fdiv <4 x double> [[TMP1]], <double 0.000000e+00, double 0.000000e+00, double undef, double undef> |
| 20 | +; CHECK-NEXT: [[TMP3:%.*]] = fmul <4 x double> [[TMP0]], <double 0.000000e+00, double 0.000000e+00, double undef, double undef> |
| 21 | +; CHECK-NEXT: [[T5:%.*]] = shufflevector <4 x double> [[TMP2]], <4 x double> [[TMP3]], <4 x i32> <i32 0, i32 1, i32 4, i32 5> |
| 22 | +; CHECK-NEXT: ret <4 x double> [[T5]] |
| 23 | +; |
| 24 | +entry: |
| 25 | + br label %end |
| 26 | + |
| 27 | +unreachable: |
| 28 | + br label %end |
| 29 | + |
| 30 | +end: |
| 31 | + %t0 = phi <4 x double> [ zeroinitializer, %entry ], [ zeroinitializer, %unreachable ] |
| 32 | + %t1 = phi <4 x double> [ zeroinitializer, %entry ], [ zeroinitializer, %unreachable ] |
| 33 | + %t2 = shufflevector <4 x double> zeroinitializer, <4 x double> zeroinitializer, <4 x i32> <i32 0, i32 0, i32 1, i32 1> |
| 34 | + %t3 = fdiv <4 x double> %t0, %t2 |
| 35 | + %t4 = fmul <4 x double> %t0, %t2 |
| 36 | + %t5 = shufflevector <4 x double> %t3, <4 x double> %t4, <4 x i32> <i32 0, i32 1, i32 6, i32 7> |
| 37 | + ret <4 x double> %t5 |
| 38 | +} |
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