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nefelim4agKevinOConnor
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stm32: h7 spi support reload mode & frequency
Signed-off-by: Timofey Titovets <[email protected]>
1 parent b16cb65 commit fec3e68

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2 files changed

+17
-3
lines changed

2 files changed

+17
-3
lines changed

Diff for: src/stm32/gpio.h

+7-1
Original file line numberDiff line numberDiff line change
@@ -38,7 +38,13 @@ void gpio_adc_cancel_sample(struct gpio_adc g);
3838

3939
struct spi_config {
4040
void *spi;
41-
uint32_t spi_cr1;
41+
union {
42+
uint32_t spi_cr1;
43+
struct {
44+
uint8_t div;
45+
uint8_t mode;
46+
};
47+
};
4248
};
4349
struct spi_config spi_setup(uint32_t bus, uint8_t mode, uint32_t rate);
4450
void spi_prepare(struct spi_config config);

Diff for: src/stm32/stm32h7_spi.c

+10-2
Original file line numberDiff line numberDiff line change
@@ -100,19 +100,27 @@ spi_setup(uint32_t bus, uint8_t mode, uint32_t rate)
100100
while ((pclk >> (div + 1)) > rate && div < 7)
101101
div++;
102102

103-
uint32_t cr1 = SPI_CR1_SPE;
104103
spi->CFG1 |= (div << SPI_CFG1_MBR_Pos) | (7 << SPI_CFG1_DSIZE_Pos);
105104
CLEAR_BIT(spi->CFG1, SPI_CFG1_CRCSIZE);
106105
spi->CFG2 |= ((mode << SPI_CFG2_CPHA_Pos) | SPI_CFG2_MASTER | SPI_CFG2_SSM
107106
| SPI_CFG2_AFCNTR | SPI_CFG2_SSOE);
108107
spi->CR1 |= SPI_CR1_SSI;
109108

110-
return (struct spi_config){ .spi = spi, .spi_cr1 = cr1 };
109+
return (struct spi_config){ .spi = spi, .div = div, .mode = mode };
111110
}
112111

113112
void
114113
spi_prepare(struct spi_config config)
115114
{
115+
uint32_t div = config.div;
116+
uint32_t mode = config.mode;
117+
SPI_TypeDef *spi = config.spi;
118+
// Reload frequency
119+
spi->CFG1 = (spi->CFG1 & ~SPI_CFG1_MBR_Msk);
120+
spi->CFG1 |= (div << SPI_CFG1_MBR_Pos);
121+
// Reload mode
122+
spi->CFG2 = (spi->CFG2 & ~SPI_CFG2_CPHA_Msk);
123+
spi->CFG2 |= (mode << SPI_CFG2_CPHA_Pos);
116124
}
117125

118126
void

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