|
| 1 | +CS35L33 Speaker Amplifier |
| 2 | + |
| 3 | +Required properties: |
| 4 | + |
| 5 | + - compatible : "cirrus,cs35l33" |
| 6 | + |
| 7 | + - reg : the I2C address of the device for I2C |
| 8 | + |
| 9 | + - VA-supply, VP-supply : power supplies for the device, |
| 10 | + as covered in |
| 11 | + Documentation/devicetree/bindings/regulator/regulator.txt. |
| 12 | + |
| 13 | +Optional properties: |
| 14 | + |
| 15 | + - reset-gpios : gpio used to reset the amplifier |
| 16 | + |
| 17 | + - interrupt-parent : Specifies the phandle of the interrupt controller to |
| 18 | + which the IRQs from CS35L33 are delivered to. |
| 19 | + - interrupts : IRQ line info CS35L33. |
| 20 | + (See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt |
| 21 | + for further information relating to interrupt properties) |
| 22 | + |
| 23 | + - cirrus,boost-ctl : Booster voltage use to supply the amp. If the value is |
| 24 | + 0, then VBST = VP. If greater than 0, the boost voltage will be 3300mV with |
| 25 | + a value of 1 and will increase at a step size of 100mV until a maximum of |
| 26 | + 8000mV. |
| 27 | + |
| 28 | + - cirrus,ramp-rate : On power up, it affects the time from when the power |
| 29 | + up sequence begins to the time the audio reaches a full-scale output. |
| 30 | + On power down, it affects the time from when the power-down sequence |
| 31 | + begins to when the amplifier disables the PWM outputs. If this property |
| 32 | + is not set then soft ramping will be disabled and ramp time would be |
| 33 | + 20ms. If this property is set to 0,1,2,3 then ramp times would be 40ms, |
| 34 | + 60ms,100ms,175ms respectively for 48KHz sample rate. |
| 35 | + |
| 36 | + - cirrus,boost-ipk : The maximum current allowed for the boost converter. |
| 37 | + The range starts at 1850000uA and goes to a maximum of 3600000uA |
| 38 | + with a step size of 15625uA. The default is 2500000uA. |
| 39 | + |
| 40 | + - cirrus,imon-adc-scale : Configures the scaling of data bits from the IMON |
| 41 | + ADC data word. This property can be set as a value of 0 for bits 15 down |
| 42 | + to 0, 6 for 21 down to 6, 7, for 22 down to 7, 8 for 23 down to 8. |
| 43 | + |
| 44 | + |
| 45 | +Optional H/G Algorithm sub-node: |
| 46 | + |
| 47 | +The cs35l33 node can have a single "cirrus,hg-algo" sub-node that will enable |
| 48 | +the internal H/G Algorithm. |
| 49 | + |
| 50 | + - cirrus,hg-algo : Sub-node for internal Class H/G algorithm that |
| 51 | + controls the amplifier supplies. |
| 52 | + |
| 53 | +Optional properties for the "cirrus,hg-algo" sub-node: |
| 54 | + |
| 55 | + - cirrus,mem-depth : Memory depth for the Class H/G algorithm measured in |
| 56 | + LRCLK cycles. If this property is set to 0, 1, 2, or 3 then the memory |
| 57 | + depths will be 1, 4, 8, 16 LRCLK cycles. The default is 16 LRCLK cycles. |
| 58 | + |
| 59 | + cirrus,release-rate : The number of consecutive LRCLK periods before |
| 60 | + allowing release condition tracking updates. The number of LRCLK periods |
| 61 | + start at 3 to a maximum of 255. |
| 62 | + |
| 63 | + - cirrus,ldo-thld : Configures the signal threshold at which the PWM output |
| 64 | + stage enters LDO operation. Starts as a default value of 50mV for a value |
| 65 | + of 1 and increases with a step size of 50mV to a maximum of 750mV (value of |
| 66 | + 0xF). |
| 67 | + |
| 68 | + - cirrus,ldo-path-disable : This is a boolean property. If present, the H/G |
| 69 | + algorithm uses the max detection path. If not present, the LDO |
| 70 | + detection path is used. |
| 71 | + |
| 72 | + - cirrus,ldo-entry-delay : The LDO entry delay in milliseconds before the H/G |
| 73 | + algorithm switches to the LDO voltage. This property can be set to values |
| 74 | + from 0 to 7 for delays of 5ms, 10ms, 50ms, 100ms, 200ms, 500ms, 1000ms. |
| 75 | + The default is 100ms. |
| 76 | + |
| 77 | + - cirrus,vp-hg-auto : This is a boolean property. When set, class H/G VPhg |
| 78 | + automatic updating is enabled. |
| 79 | + |
| 80 | + - cirrus,vp-hg : Class H/G algorithm VPhg. Controls the H/G algorithm's |
| 81 | + reference to the VP voltage for when to start generating a boosted VBST. |
| 82 | + The reference voltage starts at 3000mV with a value of 0x3 and is increased |
| 83 | + by 100mV per step to a maximum of 5500mV. |
| 84 | + |
| 85 | + - cirrus,vp-hg-rate : The rate (number of LRCLK periods) at which the VPhg is |
| 86 | + allowed to increase to a higher voltage when using VPhg automatic |
| 87 | + tracking. This property can be set to values from 0 to 3 with rates of 128 |
| 88 | + periods, 2048 periods, 32768 periods, and 524288 periods. |
| 89 | + The default is 32768 periods. |
| 90 | + |
| 91 | + - cirrus,vp-hg-va : VA calculation reference for automatic VPhg tracking |
| 92 | + using VPMON. This property can be set to values from 0 to 6 starting at |
| 93 | + 1800mV with a step size of 50mV up to a maximum value of 1750mV. |
| 94 | + Default is 1800mV. |
| 95 | + |
| 96 | +Example: |
| 97 | + |
| 98 | +cs35l33: cs35l33@40 { |
| 99 | + compatible = "cirrus,cs35l33"; |
| 100 | + reg = <0x40>; |
| 101 | + |
| 102 | + VA-supply = <&ldo5_reg>; |
| 103 | + VP-supply = <&ldo5_reg>; |
| 104 | + |
| 105 | + interrupt-parent = <&gpio8>; |
| 106 | + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; |
| 107 | + |
| 108 | + reset-gpios = <&cs47l91 34 0>; |
| 109 | + |
| 110 | + cirrus,ramp-rate = <0x0>; |
| 111 | + cirrus,boost-ctl = <0x30>; /* VBST = 8000mV */ |
| 112 | + cirrus,boost-ipk = <0xE0>; /* 3600mA */ |
| 113 | + cirrus,imon-adc-scale = <0> /* Bits 15 down to 0 */ |
| 114 | + |
| 115 | + cirrus,hg-algo { |
| 116 | + cirrus,mem-depth = <0x3>; |
| 117 | + cirrus,release-rate = <0x3>; |
| 118 | + cirrus,ldo-thld = <0x1>; |
| 119 | + cirrus,ldo-path-disable = <0x0>; |
| 120 | + cirrus,ldo-entry-delay=<0x4>; |
| 121 | + cirrus,vp-hg-auto; |
| 122 | + cirrus,vp-hg=<0xF>; |
| 123 | + cirrus,vp-hg-rate=<0x2>; |
| 124 | + cirrus,vp-hg-va=<0x0>; |
| 125 | + }; |
| 126 | +}; |
0 commit comments