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290 | 290 | #define WM8985_GPIO1GPD_MASK 0x0040 /* GPIO1GPD */
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291 | 291 | #define WM8985_GPIO1GPD_SHIFT 6 /* GPIO1GPD */
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292 | 292 | #define WM8985_GPIO1GPD_WIDTH 1 /* GPIO1GPD */
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| 293 | +#define WM8758_OPCLKDIV_MASK 0x0030 /* OPCLKDIV - [1:0] */ |
| 294 | +#define WM8758_OPCLKDIV_SHIFT 4 /* OPCLKDIV - [1:0] */ |
| 295 | +#define WM8758_OPCLKDIV_WIDTH 2 /* OPCLKDIV - [1:0] */ |
293 | 296 | #define WM8985_GPIO1POL 0x0008 /* GPIO1POL */
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294 | 297 | #define WM8985_GPIO1POL_MASK 0x0008 /* GPIO1POL */
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295 | 298 | #define WM8985_GPIO1POL_SHIFT 3 /* GPIO1POL */
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301 | 304 | /*
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302 | 305 | * R9 (0x09) - Jack Detect Control 1
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303 | 306 | */
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| 307 | +#define WM8758_JD_VMID1_MASK 0x0100 /* JD_VMID1 */ |
| 308 | +#define WM8758_JD_VMID1_SHIFT 8 /* JD_VMID1 */ |
| 309 | +#define WM8758_JD_VMID1_WIDTH 1 /* JD_VMID1 */ |
| 310 | +#define WM8758_JD_VMID0_MASK 0x0080 /* JD_VMID0 */ |
| 311 | +#define WM8758_JD_VMID0_SHIFT 7 /* JD_VMID0 */ |
| 312 | +#define WM8758_JD_VMID0_WIDTH 1 /* JD_VMID0 */ |
304 | 313 | #define WM8985_JD_EN 0x0040 /* JD_EN */
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305 | 314 | #define WM8985_JD_EN_MASK 0x0040 /* JD_EN */
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306 | 315 | #define WM8985_JD_EN_SHIFT 6 /* JD_EN */
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649 | 658 | #define WM8985_OUT4_2LNR_MASK 0x0020 /* OUT4_2LNR */
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650 | 659 | #define WM8985_OUT4_2LNR_SHIFT 5 /* OUT4_2LNR */
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651 | 660 | #define WM8985_OUT4_2LNR_WIDTH 1 /* OUT4_2LNR */
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| 661 | +#define WM8758_VMIDTOG_MASK 0x0010 /* VMIDTOG */ |
| 662 | +#define WM8758_VMIDTOG_SHIFT 4 /* VMIDTOG */ |
| 663 | +#define WM8758_VMIDTOG_WIDTH 1 /* VMIDTOG */ |
| 664 | +#define WM8758_OUT2DEL_MASK 0x0008 /* OUT2DEL */ |
| 665 | +#define WM8758_OUT2DEL_SHIFT 3 /* OUT2DEL */ |
| 666 | +#define WM8758_OUT2DEL_WIDTH 1 /* OUT2DEL */ |
652 | 667 | #define WM8985_POBCTRL 0x0004 /* POBCTRL */
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653 | 668 | #define WM8985_POBCTRL_MASK 0x0004 /* POBCTRL */
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654 | 669 | #define WM8985_POBCTRL_SHIFT 2 /* POBCTRL */
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684 | 699 | #define WM8985_BEEPVOL_MASK 0x000E /* BEEPVOL - [3:1] */
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685 | 700 | #define WM8985_BEEPVOL_SHIFT 1 /* BEEPVOL - [3:1] */
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686 | 701 | #define WM8985_BEEPVOL_WIDTH 3 /* BEEPVOL - [3:1] */
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| 702 | +#define WM8758_DELEN2_MASK 0x0004 /* DELEN2 */ |
| 703 | +#define WM8758_DELEN2_SHIFT 2 /* DELEN2 */ |
| 704 | +#define WM8758_DELEN2_WIDTH 1 /* DELEN2 */ |
687 | 705 | #define WM8985_BEEPEN 0x0001 /* BEEPEN */
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688 | 706 | #define WM8985_BEEPEN_MASK 0x0001 /* BEEPEN */
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689 | 707 | #define WM8985_BEEPEN_SHIFT 0 /* BEEPEN */
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790 | 808 | /*
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791 | 809 | * R49 (0x31) - Output ctrl
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792 | 810 | */
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| 811 | +#define WM8758_HP_COM 0x0100 /* HP_COM */ |
| 812 | +#define WM8758_HP_COM_MASK 0x0100 /* HP_COM */ |
| 813 | +#define WM8758_HP_COM_SHIFT 8 /* HP_COM */ |
| 814 | +#define WM8758_HP_COM_WIDTH 1 /* HP_COM */ |
| 815 | +#define WM8758_LINE_COM 0x0080 /* LINE_COM */ |
| 816 | +#define WM8758_LINE_COM_MASK 0x0080 /* LINE_COM */ |
| 817 | +#define WM8758_LINE_COM_SHIFT 7 /* LINE_COM */ |
| 818 | +#define WM8758_LINE_COM_WIDTH 1 /* LINE_COM */ |
793 | 819 | #define WM8985_DACL2RMIX 0x0040 /* DACL2RMIX */
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794 | 820 | #define WM8985_DACL2RMIX_MASK 0x0040 /* DACL2RMIX */
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795 | 821 | #define WM8985_DACL2RMIX_SHIFT 6 /* DACL2RMIX */
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806 | 832 | #define WM8985_OUT3BOOST_MASK 0x0008 /* OUT3BOOST */
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807 | 833 | #define WM8985_OUT3BOOST_SHIFT 3 /* OUT3BOOST */
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808 | 834 | #define WM8985_OUT3BOOST_WIDTH 1 /* OUT3BOOST */
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| 835 | +#define WM8758_OUT4ENDEL 0x0010 /* OUT4ENDEL */ |
| 836 | +#define WM8758_OUT4ENDEL_MASK 0x0010 /* OUT4ENDEL */ |
| 837 | +#define WM8758_OUT4ENDEL_SHIFT 4 /* OUT4ENDEL */ |
| 838 | +#define WM8758_OUT4ENDEL_WIDTH 1 /* OUT4ENDEL */ |
| 839 | +#define WM8758_OUT3ENDEL 0x0008 /* OUT3ENDEL */ |
| 840 | +#define WM8758_OUT3ENDEL_MASK 0x0008 /* OUT3ENDEL */ |
| 841 | +#define WM8758_OUT3ENDEL_SHIFT 3 /* OUT3ENDEL */ |
| 842 | +#define WM8758_OUT3ENDEL_WIDTH 1 /* OUT3ENDEL */ |
809 | 843 | #define WM8985_TSOPCTRL 0x0004 /* TSOPCTRL */
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810 | 844 | #define WM8985_TSOPCTRL_MASK 0x0004 /* TSOPCTRL */
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811 | 845 | #define WM8985_TSOPCTRL_SHIFT 2 /* TSOPCTRL */
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1021 | 1055 | #define WM8985_HALFIPBIAS_MASK 0x0080 /* HALFIPBIAS */
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1022 | 1056 | #define WM8985_HALFIPBIAS_SHIFT 7 /* HALFIPBIAS */
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1023 | 1057 | #define WM8985_HALFIPBIAS_WIDTH 1 /* HALFIPBIAS */
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| 1058 | +#define WM8758_HALFIPBIAS 0x0040 /* HALFI_IPGA */ |
| 1059 | +#define WM8758_HALFI_IPGA_MASK 0x0040 /* HALFI_IPGA */ |
| 1060 | +#define WM8758_HALFI_IPGA_SHIFT 6 /* HALFI_IPGA */ |
| 1061 | +#define WM8758_HALFI_IPGA_WIDTH 1 /* HALFI_IPGA */ |
1024 | 1062 | #define WM8985_VBBIASTST_MASK 0x0060 /* VBBIASTST - [6:5] */
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1025 | 1063 | #define WM8985_VBBIASTST_SHIFT 5 /* VBBIASTST - [6:5] */
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1026 | 1064 | #define WM8985_VBBIASTST_WIDTH 2 /* VBBIASTST - [6:5] */
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