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bjorn-helgaasbjorn-helgaas
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Merge branches 'pci/host-aardvark', 'pci/host-altera', 'pci/host-artpec', 'pci/host-designware', 'pci/host-hv', 'pci/host-keystone', 'pci/host-rcar', 'pci/host-rockchip', 'pci/host-tegra' and 'pci/host-xilinx' into next
* pci/host-aardvark: PCI: aardvark: Remove redundant dev_err call in advk_pcie_probe() * pci/host-altera: PCI: altera: Remove redundant platform_get_resource() return value check PCI: altera: Move retrain from fixup to altera_pcie_host_init() PCI: altera: Rework config accessors for use without a struct pci_bus PCI: altera: Poll for link training status after retraining the link * pci/host-artpec: PCI: artpec6: Drop __init from artpec6_add_pcie_port() * pci/host-designware: PCI: designware: Remove redundant platform_get_resource() return value check PCI: designware: Exchange viewport of `MEMORYs' and `CFGs/IOs' PCI: designware: Keep viewport fixed for IO transaction if num_viewport > 2 PCI: designware: Check LTSSM training bit before deciding link is up PCI: designware: Add iATU Unroll feature PCI: designware: Wait for iATU enable PCI: designware: Move link wait definitions to .c file PCI: designware: Return data directly from dw_pcie_readl_rc() * pci/host-hv: PCI: hv: Handle hv_pci_generic_compl() error case PCI: hv: Handle vmbus_sendpacket() failure in hv_compose_msi_msg() PCI: hv: Remove the unused 'wrk' in struct hv_pcibus_device PCI: hv: Use pci_function_description[0] in struct definitions PCI: hv: Use zero-length array in struct pci_packet PCI: hv: Use list_move_tail() instead of list_del() + list_add_tail() * pci/host-keystone: PCI: keystone: Propagate request_irq() failure * pci/host-rcar: PCI: rcar: Try increasing PCIe link speed to 5 GT/s at boot PCI: rcar: Fix some checkpatch warnings PCI: rcar: Add multi-MSI support PCI: rcar: Don't disable/unprepare clocks on prepare/enable failure PCI: rcar: Consolidate register space lookup and ioremap * pci/host-rockchip: PCI: rockchip: Fix wrong transmitted FTS count PCI: rockchip: Improve the deassert sequence of four reset pins PCI: rockchip: Increase the Max Credit update interval PCI: rockchip: Add Rockchip PCIe controller support dt-bindings: PCI: rockchip: Add DT bindings for Rockchip PCIe controller * pci/host-tegra: PCI: tegra: Use of_device_get_match_data() PCI: tegra: Remove redundant _data suffix * pci/host-xilinx: microblaze/PCI: Add multidomain support for procfs PCI: xilinx: Dispose of MSI virtual IRQ PCI: xilinx: Clear correct MSI set bit PCI: xilinx: Clear interrupt register for invalid interrupt PCI: xilinx: Keep both legacy and MSI interrupt domain references PCI: xilinx-nwl: Enable all MSI interrupts using MSI mask PCI: xilinx-nwl: Expand error logging Conflicts: drivers/pci/host/pcie-xilinx.c
11 parents 930ffc0 + 8b22335 + 6c8b120 + b58ddf1 + 639c532 + a5b45b7 + 8116acc + b3327f7 + ca19890 + c460af9 + 9413d96 commit 69a06e4

21 files changed

+1925
-224
lines changed

‎Documentation/devicetree/bindings/pci/designware-pcie.txt

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@@ -17,6 +17,8 @@ Required properties:
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- num-lanes: number of lanes to use
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Optional properties:
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- num-viewport: number of view ports configured in hardware. If a platform
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does not specify it, the driver assumes 2.
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- num-lanes: number of lanes to use (this property should be specified unless
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the link is brought already up in BIOS)
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- reset-gpio: gpio pin number of power good signal
@@ -44,4 +46,5 @@ Example configuration:
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interrupts = <25>, <24>;
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#interrupt-cells = <1>;
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num-lanes = <1>;
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num-viewport = <3>;
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};

‎Documentation/devicetree/bindings/pci/rockchip-pcie.txt

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* Rockchip AXI PCIe Root Port Bridge DT description
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Required properties:
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- #address-cells: Address representation for root ports, set to <3>
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- #size-cells: Size representation for root ports, set to <2>
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- #interrupt-cells: specifies the number of cells needed to encode an
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interrupt source. The value must be 1.
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- compatible: Should contain "rockchip,rk3399-pcie"
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- reg: Two register ranges as listed in the reg-names property
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- reg-names: Must include the following names
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- "axi-base"
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- "apb-base"
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- clocks: Must contain an entry for each entry in clock-names.
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See ../clocks/clock-bindings.txt for details.
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- clock-names: Must include the following entries:
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- "aclk"
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- "aclk-perf"
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- "hclk"
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- "pm"
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- msi-map: Maps a Requester ID to an MSI controller and associated
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msi-specifier data. See ./pci-msi.txt
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- phys: From PHY bindings: Phandle for the Generic PHY for PCIe.
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- phy-names: MUST be "pcie-phy".
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- interrupts: Three interrupt entries must be specified.
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- interrupt-names: Must include the following names
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- "sys"
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- "legacy"
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- "client"
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- resets: Must contain five entries for each entry in reset-names.
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See ../reset/reset.txt for details.
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- reset-names: Must include the following names
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- "core"
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- "mgmt"
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- "mgmt-sticky"
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- "pipe"
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- pinctrl-names : The pin control state names
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- pinctrl-0: The "default" pinctrl state
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- #interrupt-cells: specifies the number of cells needed to encode an
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interrupt source. The value must be 1.
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- interrupt-map-mask and interrupt-map: standard PCI properties
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Optional Property:
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- ep-gpios: contain the entry for pre-reset gpio
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- num-lanes: number of lanes to use
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- vpcie3v3-supply: The phandle to the 3.3v regulator to use for PCIe.
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- vpcie1v8-supply: The phandle to the 1.8v regulator to use for PCIe.
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- vpcie0v9-supply: The phandle to the 0.9v regulator to use for PCIe.
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*Interrupt controller child node*
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The core controller provides a single interrupt for legacy INTx. The PCIe node
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should contain an interrupt controller node as a target for the PCI
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'interrupt-map' property. This node represents the domain at which the four
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INTx interrupts are decoded and routed.
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Required properties for Interrupt controller child node:
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- interrupt-controller: identifies the node as an interrupt controller
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- #address-cells: specifies the number of cells needed to encode an
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address. The value must be 0.
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- #interrupt-cells: specifies the number of cells needed to encode an
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interrupt source. The value must be 1.
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Example:
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pcie0: pcie@f8000000 {
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compatible = "rockchip,rk3399-pcie";
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#address-cells = <3>;
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#size-cells = <2>;
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clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
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<&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
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clock-names = "aclk", "aclk-perf",
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"hclk", "pm";
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bus-range = <0x0 0x1>;
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interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
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interrupt-names = "sys", "legacy", "client";
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assigned-clocks = <&cru SCLK_PCIEPHY_REF>;
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assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>;
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assigned-clock-rates = <100000000>;
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ep-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
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ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x600000
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0x81000000 0x0 0xfa600000 0x0 0xfa600000 0x0 0x100000>;
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num-lanes = <4>;
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msi-map = <0x0 &its 0x0 0x1000>;
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reg = <0x0 0xf8000000 0x0 0x2000000>, <0x0 0xfd000000 0x0 0x1000000>;
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reg-names = "axi-base", "apb-base";
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resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
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<&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>;
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reset-names = "core", "mgmt", "mgmt-sticky", "pipe";
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phys = <&pcie_phy>;
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phy-names = "pcie-phy";
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pinctrl-names = "default";
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pinctrl-0 = <&pcie_clkreq>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie0_intc 0>,
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<0 0 0 2 &pcie0_intc 1>,
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<0 0 0 3 &pcie0_intc 2>,
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<0 0 0 4 &pcie0_intc 3>;
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pcie0_intc: interrupt-controller {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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};
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};

‎MAINTAINERS

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F: Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
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F: drivers/pci/host/pcie-hisi.c
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PCIE DRIVER FOR ROCKCHIP
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M: Shawn Lin <[email protected]>
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M: Wenrui Li <[email protected]>
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L: [email protected]
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L: [email protected]
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S: Maintained
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F: Documentation/devicetree/bindings/pci/rockchip-pcie.txt
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F: drivers/pci/host/pcie-rockchip.c
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90869095
PCIE DRIVER FOR QUALCOMM MSM
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M: Stanimir Varbanov <[email protected]>
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L: [email protected]

‎arch/microblaze/pci/pci-common.c

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@@ -632,10 +632,10 @@ void pci_process_bridge_OF_ranges(struct pci_controller *hose,
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}
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}
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/* Decide whether to display the domain number in /proc */
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/* Display the domain number in /proc */
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int pci_proc_domain(struct pci_bus *bus)
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{
638-
return 0;
638+
return pci_domain_nr(bus);
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}
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/* This header fixup will do the resource fixup for all devices as they are

‎drivers/pci/host/Kconfig

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@@ -274,4 +274,15 @@ config PCIE_ARTPEC6
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Say Y here to enable PCIe controller support on Axis ARTPEC-6
275275
SoCs. This PCIe controller uses the DesignWare core.
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277+
config PCIE_ROCKCHIP
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bool "Rockchip PCIe controller"
279+
depends on ARCH_ROCKCHIP
280+
depends on OF
281+
depends on PCI_MSI_IRQ_DOMAIN
282+
select MFD_SYSCON
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help
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Say Y here if you want internal PCI support on Rockchip SoC.
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There is 1 internal PCIe port available to support GEN2 with
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4 slots.
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endmenu

‎drivers/pci/host/Makefile

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@@ -31,3 +31,4 @@ obj-$(CONFIG_PCI_HOST_THUNDER_ECAM) += pci-thunder-ecam.o
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obj-$(CONFIG_PCI_HOST_THUNDER_PEM) += pci-thunder-pem.o
3232
obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-armada8k.o
3333
obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o
34+
obj-$(CONFIG_PCIE_ROCKCHIP) += pcie-rockchip.o

‎drivers/pci/host/pci-aardvark.c

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@@ -927,10 +927,8 @@ static int advk_pcie_probe(struct platform_device *pdev)
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928928
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
929929
pcie->base = devm_ioremap_resource(&pdev->dev, res);
930-
if (IS_ERR(pcie->base)) {
931-
dev_err(&pdev->dev, "Failed to map registers\n");
930+
if (IS_ERR(pcie->base))
932931
return PTR_ERR(pcie->base);
933-
}
934932

935933
irq = platform_get_irq(pdev, 0);
936934
ret = devm_request_irq(&pdev->dev, irq, advk_pcie_irq_handler,

‎drivers/pci/host/pci-exynos.c

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@@ -425,12 +425,15 @@ static void exynos_pcie_enable_interrupts(struct pcie_port *pp)
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exynos_pcie_msi_init(pp);
426426
}
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428-
static inline void exynos_pcie_readl_rc(struct pcie_port *pp,
429-
void __iomem *dbi_base, u32 *val)
428+
static inline u32 exynos_pcie_readl_rc(struct pcie_port *pp,
429+
void __iomem *dbi_base)
430430
{
431+
u32 val;
432+
431433
exynos_pcie_sideband_dbi_r_mode(pp, true);
432-
*val = readl(dbi_base);
434+
val = readl(dbi_base);
433435
exynos_pcie_sideband_dbi_r_mode(pp, false);
436+
return val;
434437
}
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436439
static inline void exynos_pcie_writel_rc(struct pcie_port *pp,

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