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MCL86jr/Code/MCL_FAST.COM renamed to MCL86jr/Acceleration Programs/MCL_FAST.COM

File renamed without changes.

MCL86jr/Code/MCL_SLOW.COM renamed to MCL86jr/Acceleration Programs/MCL_SLOW.COM

File renamed without changes.

‎MCL86jr/FPGA Configuration Files/Config_Flash_W25Q128BV.mcs‎

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‎MCL86jr/FPGA Configuration Files/mcl86jr.bit‎

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‎MCL86jr/FPGA/Untitled.mcs‎

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‎MCL86jr/FPGA/src4synth/MCL86_Microcode_Xilinx_Version_4.coe‎

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‎MCL86jr/FPGA/src4synth/eu.v‎

Lines changed: 147 additions & 73 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
//
22
//
3-
// File Name : eu.v
4-
// Used on : MCL86jr Board
3+
// File Name : mcl86_eu_core.v
4+
// Used on :
55
// Author : Ted Fried, MicroCore Labs
66
// Creation : 10/8/2015
77
// Code Type : Synthesizable
@@ -19,8 +19,8 @@
1919
// Revision 1.0 10/8/15
2020
// Initial revision
2121
//
22-
// Revision 2.0 3/21/21
23-
// Fixed overflow flag calculations
22+
// Revision 2.0 11/6/22
23+
// Changed overflow flag calculation into rtl instead of microcode
2424
//
2525
//
2626
//------------------------------------------------------------------------
@@ -102,10 +102,13 @@ reg eu_tr_latched;
102102
reg biu_done_caught;
103103
reg eu_biu_req_d1;
104104
reg intr_enable_delayed;
105+
reg eu_overflow_override;
106+
reg eu_add_overflow8_fixed;
107+
reg eu_add_overflow16_fixed;
105108
wire eu_prefix_rep;
106109
wire eu_prefix_repnz;
107110
wire eu_tf_debounce;
108-
wire eu_prefix_lock ;
111+
wire eu_prefix_lock;
109112
wire eu_biu_req;
110113
wire eu_parity;
111114
wire eu_flag_o;
@@ -158,12 +161,12 @@ wire [15:0] eu_alu_out;
158161
wire [15:0] eu_operand0;
159162
wire [15:0] eu_operand1;
160163
wire [31:0] eu_rom_data;
164+
wire [15:0] add_total;
165+
wire [15:0] sub_total;
166+
wire [15:0] adc_total;
167+
wire [15:0] sbb_total;
168+
161169

162-
wire [15:0] adc_total;
163-
wire [15:0] sbb_total;
164-
reg eu_overflow_fix;
165-
reg eu_add_overflow8_fixed;
166-
reg eu_add_overflow16_fixed;
167170

168171

169172
//------------------------------------------------------------------------
@@ -336,11 +339,13 @@ assign intr_asserted = BIU_INTR & intr_enable_delayed;
336339

337340
assign new_instruction = (eu_rom_address[12:8]==5'h01) ? 1'b1 : 1'b0;
338341

339-
342+
343+
assign add_total = eu_register_r0 + eu_register_r1;
340344
assign adc_total = eu_register_r0 + eu_register_r1 + eu_flag_c;
345+
assign sub_total = eu_register_r0 - eu_register_r1;
341346
assign sbb_total = eu_register_r0 - eu_register_r1 - eu_flag_c;
342347

343-
348+
344349
//------------------------------------------------------------------------------------------
345350
//
346351
// EU Microsequencer
@@ -418,97 +423,166 @@ else
418423
biu_done_d1 <= BIU_DONE;
419424
biu_done_d2 <= biu_done_d1;
420425
eu_biu_req_d1 <= eu_biu_req;
421-
if (biu_done_d1==1'b0 && BIU_DONE==1'b1)
426+
if (biu_done_d2==1'b0 && biu_done_d1==1'b1)
422427
biu_done_caught <= 1'b1;
423428
else if (eu_biu_req_d1==1'b1 && eu_biu_req==1'b0)
424429
biu_done_caught <= 1'b0;
425-
430+
426431

427-
// ADC - Byte
428-
//
429-
if (eu_rom_address == 16'h0A03)
430-
begin
431-
eu_overflow_fix <= 1'b1;
432-
433-
if ( ( (eu_register_r0[7]==1'b0) && (eu_register_r1[7]==1'b0) && (adc_total[7]==1'b1) ) ||
434-
( (eu_register_r0[7]==1'b1) && (eu_register_r1[7]==1'b1) && (adc_total[7]==1'b0) ) )
432+
// ADD - Byte
433+
//
434+
if (eu_rom_address == 16'h09C9)
435435
begin
436-
eu_add_overflow8_fixed <= 1'b1;
436+
eu_overflow_override <= 1'b1;
437+
438+
if ( ( (eu_register_r0[7]==1'b0) && (eu_register_r1[7]==1'b0) && (add_total[7]==1'b1) ) ||
439+
( (eu_register_r0[7]==1'b1) && (eu_register_r1[7]==1'b1) && (add_total[7]==1'b0) ) )
440+
begin
441+
eu_add_overflow8_fixed <= 1'b1;
442+
end
443+
else
444+
begin
445+
eu_add_overflow8_fixed <= 1'b0;
446+
end
447+
end
448+
449+
// ADC - Byte
450+
//
451+
if (eu_rom_address == 16'h0A03)
452+
begin
453+
eu_overflow_override <= 1'b1;
454+
455+
if ( ( (eu_register_r0[7]==1'b0) && (eu_register_r1[7]==1'b0) && (adc_total[7]==1'b1) ) ||
456+
( (eu_register_r0[7]==1'b1) && (eu_register_r1[7]==1'b1) && (adc_total[7]==1'b0) ) )
457+
begin
458+
eu_add_overflow8_fixed <= 1'b1;
459+
end
460+
else
461+
begin
462+
eu_add_overflow8_fixed <= 1'b0;
463+
end
437464
end
438-
else
465+
466+
// SUB - Byte
467+
//
468+
if (eu_rom_address == 16'h0A46)
439469
begin
440-
eu_add_overflow8_fixed <= 1'b0;
470+
eu_overflow_override <= 1'b1;
471+
472+
if ( ( (eu_register_r0[7]==1'b0) && (eu_register_r1[7]==1'b1) && (sub_total[7]==1'b1) ) ||
473+
( (eu_register_r0[7]==1'b1) && (eu_register_r1[7]==1'b0) && (sub_total[7]==1'b0) ) )
474+
begin
475+
eu_add_overflow8_fixed <= 1'b1;
476+
end
477+
else
478+
begin
479+
eu_add_overflow8_fixed <= 1'b0;
480+
end
441481
end
442-
end
443-
444482

445-
// SBB - Byte
446-
//
447-
if (eu_rom_address == 16'h0AAE)
448-
begin
449-
eu_overflow_fix <= 1'b1;
450-
451-
if ( ( (eu_register_r0[7]==1'b0) && (eu_register_r1[7]==1'b1) && (sbb_total[7]==1'b1) ) ||
452-
( (eu_register_r0[7]==1'b1) && (eu_register_r1[7]==1'b0) && (sbb_total[7]==1'b0) ) )
483+
// SBB - Byte
484+
//
485+
if (eu_rom_address == 16'h0AAE)
453486
begin
454-
eu_add_overflow8_fixed <= 1'b1;
455-
end
456-
else
487+
eu_overflow_override <= 1'b1;
488+
489+
if ( ( (eu_register_r0[7]==1'b0) && (eu_register_r1[7]==1'b1) && (sbb_total[7]==1'b1) ) ||
490+
( (eu_register_r0[7]==1'b1) && (eu_register_r1[7]==1'b0) && (sbb_total[7]==1'b0) ) )
491+
begin
492+
eu_add_overflow8_fixed <= 1'b1;
493+
end
494+
else
495+
begin
496+
eu_add_overflow8_fixed <= 1'b0;
497+
end
498+
end
499+
500+
// ADD - Word
501+
//
502+
if (eu_rom_address == 16'h09CC)
457503
begin
458-
eu_add_overflow8_fixed <= 1'b0;
504+
eu_overflow_override <= 1'b1;
505+
506+
if ( ( (eu_register_r0[15]==1'b0) && (eu_register_r1[15]==1'b0) && (add_total[15]==1'b1) ) ||
507+
( (eu_register_r0[15]==1'b1) && (eu_register_r1[15]==1'b1) && (add_total[15]==1'b0) ) )
508+
begin
509+
eu_add_overflow16_fixed <= 1'b1;
510+
end
511+
else
512+
begin
513+
eu_add_overflow16_fixed <= 1'b0;
514+
end
459515
end
460-
end
461516

462-
// ADC - Word
463-
//
464-
if (eu_rom_address == 16'h0A12)
465-
begin
466-
eu_overflow_fix <= 1'b1;
467-
468-
if ( ( (eu_register_r0[15]==1'b0) && (eu_register_r1[15]==1'b0) && (adc_total[15]==1'b1) ) ||
469-
( (eu_register_r0[15]==1'b1) && (eu_register_r1[15]==1'b1) && (adc_total[15]==1'b0) ) )
517+
// ADC - Word
518+
//
519+
if (eu_rom_address == 16'h0A12)
470520
begin
471-
eu_add_overflow16_fixed <= 1'b1;
521+
eu_overflow_override <= 1'b1;
522+
523+
if ( ( (eu_register_r0[15]==1'b0) && (eu_register_r1[15]==1'b0) && (adc_total[15]==1'b1) ) ||
524+
( (eu_register_r0[15]==1'b1) && (eu_register_r1[15]==1'b1) && (adc_total[15]==1'b0) ) )
525+
begin
526+
eu_add_overflow16_fixed <= 1'b1;
527+
end
528+
else
529+
begin
530+
eu_add_overflow16_fixed <= 1'b0;
531+
end
472532
end
473-
else
533+
534+
// SUB - Word
535+
//
536+
if (eu_rom_address == 16'h0A52)
474537
begin
475-
eu_add_overflow16_fixed <= 1'b0;
538+
eu_overflow_override <= 1'b1;
539+
540+
if ( ( (eu_register_r0[15]==1'b0) && (eu_register_r1[15]==1'b1) && (sub_total[15]==1'b1) ) ||
541+
( (eu_register_r0[15]==1'b1) && (eu_register_r1[15]==1'b0) && (sub_total[15]==1'b0) ) )
542+
begin
543+
eu_add_overflow16_fixed <= 1'b1;
544+
end
545+
else
546+
begin
547+
eu_add_overflow16_fixed <= 1'b0;
548+
end
476549
end
477-
end
478-
479550

480-
// SBB - Word
481-
//
482-
if (eu_rom_address == 16'h0ABA)
483-
begin
484-
eu_overflow_fix <= 1'b1;
485-
486-
if ( ( (eu_register_r0[15]==1'b0) && (eu_register_r1[15]==1'b1) && (sbb_total[15]==1'b1) ) ||
487-
( (eu_register_r0[15]==1'b1) && (eu_register_r1[15]==1'b0) && (sbb_total[15]==1'b0) ) )
551+
// SBB - Word
552+
//
553+
if (eu_rom_address == 16'h0ABA)
488554
begin
489-
eu_add_overflow16_fixed <= 1'b1;
490-
end
491-
else
492-
begin
493-
eu_add_overflow16_fixed <= 1'b0;
555+
eu_overflow_override <= 1'b1;
556+
557+
if ( ( (eu_register_r0[15]==1'b0) && (eu_register_r1[15]==1'b1) && (sbb_total[15]==1'b1) ) ||
558+
( (eu_register_r0[15]==1'b1) && (eu_register_r1[15]==1'b0) && (sbb_total[15]==1'b0) ) )
559+
begin
560+
eu_add_overflow16_fixed <= 1'b1;
561+
end
562+
else
563+
begin
564+
eu_add_overflow16_fixed <= 1'b0;
565+
end
494566
end
495-
end
496567

497-
if (eu_rom_address == 16'h0011) eu_overflow_fix <= 1'b0;
498568

499-
569+
// Debounce the overflow flag override when microcode returns to the main loop
570+
//
571+
if (eu_rom_address == 16'h0011) eu_overflow_override <= 1'b0;
572+
573+
574+
500575
// Generate and store flags for addition
501576
if (eu_stall_pipeline==1'b0 && eu_opcode_type==3'h2)
502577
begin
503578
eu_add_carry <= carry[16];
504579
eu_add_carry8 <= carry[8];
505580
eu_add_aux_carry <= carry[4];
506-
eu_add_overflow16 <= (eu_overflow_fix==1'b1) ? eu_add_overflow16_fixed : (carry[16] ^ carry[15]);
507-
eu_add_overflow8 <= (eu_overflow_fix==1'b1) ? eu_add_overflow8_fixed : (carry[8] ^ carry[7]);
581+
eu_add_overflow16 <= (eu_overflow_override==1'b1) ? eu_add_overflow16_fixed : (carry[16] ^ carry[15]);
582+
eu_add_overflow8 <= (eu_overflow_override==1'b1) ? eu_add_overflow8_fixed : (carry[8] ^ carry[7] );
508583
end
509584

510-
511-
585+
512586
// Register writeback
513587
if (eu_stall_pipeline==1'b0 && eu_opcode_type!=3'h0 && eu_opcode_type!=3'h1)
514588
begin

‎MCL86jr/README.md‎

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2,10 +2,14 @@
22

33
This board is a drop-in replacement for the 8088 CPU inside of the PCjr. It utilizes a Xilinx Spartan-6 FPGA and 512KB of SRAM.
44

5-
The CPU core is the MCL86 and can be run in cycle accurare mode as a mode that boosts PCjr performance by almost 6X which is as fast as an 8Mhz IBM PC AT!
5+
The CPU core is the MCL86 and can be run in cycle accurare mode which boosts PCjr performance by almost 6X which is close to the speed of an 8Mhz IBM PC AT!
66

77
The board schematic and layout were done using KiCad and all of the development files are in the PCBA directory. The board was manufacured and assembled by PCBWay.
88

99

10+
Updated on 4/15/2025
11+
- Microcode and EU files updated to integrate bug fixes found in the MCL86 on the MiSTer PCXT project
12+
- FPGA Configuration Files folder added which contains the FPGA direct programming .bit file and also the configuration Flash .mc file
13+
1014
1115
For questions email me at www.MicroCoreLabs.com

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