Uploaded_3_30_2020

MicroCoreLabs · MicroCoreLabs · commit dc4083406805 · 2020-03-30T23:44:09.000-07:00
diff --git a/README.md b/README.md
@@ -18,7 +18,7 @@ Other processors:
 
     MCLR5 - Quad-Issue Superscalar RISCV
     Lockstep Quad Modular Redundant System 
-    RISCV_C_Version - Simple and compact RISC-V RS32I implementation written in C
+    RISCV C Version - Simple and compact RISC-V RS32I implementation written in C
     
 
 Misc:
