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‎Lockstep_QMR/Core/four_module_lockstep.v

+299-277
Large diffs are not rendered by default.

‎Lockstep_QMR/Core/module_block.v

+58-36
Original file line numberDiff line numberDiff line change
@@ -21,6 +21,28 @@
2121
//
2222
//
2323
//------------------------------------------------------------------------
24+
//
25+
// Copyright (c) 2020 Ted Fried
26+
//
27+
// Permission is hereby granted, free of charge, to any person obtaining a copy
28+
// of this software and associated documentation files (the "Software"), to deal
29+
// in the Software without restriction, including without limitation the rights
30+
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
31+
// copies of the Software, and to permit persons to whom the Software is
32+
// furnished to do so, subject to the following conditions:
33+
//
34+
// The above copyright notice and this permission notice shall be included in all
35+
// copies or substantial portions of the Software.
36+
//
37+
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
38+
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
39+
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
40+
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
41+
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
42+
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
43+
// SOFTWARE.
44+
//
45+
//------------------------------------------------------------------------
2446

2547
`timescale 1ns/100ps
2648

@@ -49,23 +71,23 @@ module module_block
4971
input [7:0] BROADCAST_DATA_IN0,
5072
input [15:0] BROADCAST_IP_IN0,
5173
input BROADCAST_SYNC_IN0,
52-
input BROADCAST_IDSBL_IN0,
74+
input BROADCAST_IDSBL_IN0,
5375

5476
input BROADCAST_OK_IN1,
5577
input [7:0] BROADCAST_STROBE_IN1,
5678
input [15:0] BROADCAST_ADDRESS_IN1,
5779
input [7:0] BROADCAST_DATA_IN1,
5880
input [15:0] BROADCAST_IP_IN1,
5981
input BROADCAST_SYNC_IN1,
60-
input BROADCAST_IDSBL_IN1,
82+
input BROADCAST_IDSBL_IN1,
6183

6284
input BROADCAST_OK_IN2,
6385
input [7:0] BROADCAST_STROBE_IN2,
6486
input [15:0] BROADCAST_ADDRESS_IN2,
6587
input [7:0] BROADCAST_DATA_IN2,
6688
input [15:0] BROADCAST_IP_IN2,
6789
input BROADCAST_SYNC_IN2,
68-
input BROADCAST_IDSBL_IN2,
90+
input BROADCAST_IDSBL_IN2,
6991

7092

7193

@@ -268,7 +290,7 @@ assign BROADCAST_DATA = ((KILL_MODE==4'h2 && kill_d4==1'b1) || (run_level!
268290
assign BROADCAST_IP = eu_register_ip;
269291
assign BROADCAST_STROBE = (run_level!=2'h3) ? { 6'h0 , MODULE_ID } : eu_biu_strobe;
270292
assign BROADCAST_SYNC = (eu_rom_address==9'h103) ? 1'b1 : 1'b0;
271-
assign BROADCAST_IDSBL = core_interrupt_disable;
293+
assign BROADCAST_IDSBL = core_interrupt_disable;
272294

273295

274296

@@ -589,12 +611,12 @@ kill_d4 <= kill_d3;
589611

590612

591613
// Register writeback
592-
if (run_level==2'h1)
593-
begin
614+
if (run_level==2'h1)
615+
begin
594616
eu_register_ip <= rebuild_ip_in;
595617
eu_biu_strobe <= 'h0;
596-
end
597-
618+
end
619+
598620
else if (eu_stall_pipeline==1'b0 && eu_opcode_type!=3'h0 && eu_opcode_type!=3'h1)
599621
begin
600622
eu_alu_last_result <= eu_alu_out[15:0];
@@ -645,14 +667,14 @@ kill_d4 <= kill_d3;
645667
else
646668
begin
647669
eu_stall_pipeline <= 1'b0; // Debounce the pipeline stall
648-
if (KILL_MODE==4'h1 && kill_d4==1'b1)
649-
begin
650-
eu_rom_address <= 'h0;
651-
end
652-
else
653-
begin
654-
eu_rom_address <= eu_rom_address + 1'b1;
655-
end
670+
if (KILL_MODE==4'h1 && kill_d4==1'b1)
671+
begin
672+
eu_rom_address <= 'h0;
673+
end
674+
else
675+
begin
676+
eu_rom_address <= eu_rom_address + 1'b1;
677+
end
656678
end
657679

658680
end
@@ -683,24 +705,24 @@ begin : BIU_CONTROLLER
683705
rebuild_addr_out <= 'h0;
684706
rebuild_addr_out_d <= 'h0;
685707
rebuild_cross_zero <= 'h0;
686-
run_level <= 'h3;
708+
run_level <= 'h3;
687709
end
688710

689711
else
690712
begin
691713

692714
// Delay address out by one clock to line up with the broadcast data
693715
if (KILL_MODE==4'h5 && kill_d4==1'b1)
694-
begin
695-
rebuild_addr_out_d <= 'h0;
696-
end
697-
else
698-
begin
699-
rebuild_addr_out_d <= rebuild_addr_out;
700-
end
701-
702-
// Pipeline the neighboring code SYNC pulse
703-
rebuild_sync_in_d1 <= rebuild_sync_in;
716+
begin
717+
rebuild_addr_out_d <= 'h0;
718+
end
719+
else
720+
begin
721+
rebuild_addr_out_d <= rebuild_addr_out;
722+
end
723+
724+
// Pipeline the neighboring code SYNC pulse
725+
rebuild_sync_in_d1 <= rebuild_sync_in;
704726
rebuild_sync_in_d2 <= rebuild_sync_in_d1;
705727
rebuild_sync_in_d3 <= rebuild_sync_in_d2;
706728

@@ -721,17 +743,17 @@ begin : BIU_CONTROLLER
721743
end
722744

723745

724-
// Allow four passes of the full range or memory and register addresses when rebuilding a module
746+
// Allow four passes of the full range or memory and register addresses when rebuilding a module
725747
if (run_level==2'h3)
726-
begin
748+
begin
727749
rebuild_cross_zero <= 'h0;
728-
end
750+
end
729751
else if (run_level==2'h0 && rebuild_addr=='h0)
730752
begin
731753
rebuild_cross_zero <= rebuild_cross_zero + 1'b1;
732754
end
733755

734-
756+
735757
// If Voter has detected a failure and module is not currently in rebuilding mode, then enter rebuilding mode.
736758
if ( run_level==2'h3 && voter_good==1'b0)
737759
begin
@@ -757,12 +779,12 @@ begin : BIU_CONTROLLER
757779

758780

759781
eu_register_r3_d1 <= eu_register_r3;
760-
782+
761783
if (run_level==2'h2)
762-
begin
763-
core_interrupt_disable <= neighbor_idsbl;
764-
end
765-
else if (eu_biu_strobe_int==3'h3)
784+
begin
785+
core_interrupt_disable <= neighbor_idsbl;
786+
end
787+
else if (eu_biu_strobe_int==3'h3)
766788
begin
767789
core_interrupt_disable <= 1'b1;
768790
end

‎MCL51/Core/MCL51_top.v

+71-49
Original file line numberDiff line numberDiff line change
@@ -21,20 +21,42 @@
2121
//
2222
//
2323
//------------------------------------------------------------------------
24+
//
25+
// Copyright (c) 2020 Ted Fried
26+
//
27+
// Permission is hereby granted, free of charge, to any person obtaining a copy
28+
// of this software and associated documentation files (the "Software"), to deal
29+
// in the Software without restriction, including without limitation the rights
30+
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
31+
// copies of the Software, and to permit persons to whom the Software is
32+
// furnished to do so, subject to the following conditions:
33+
//
34+
// The above copyright notice and this permission notice shall be included in all
35+
// copies or substantial portions of the Software.
36+
//
37+
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
38+
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
39+
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
40+
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
41+
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
42+
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
43+
// SOFTWARE.
44+
//
45+
//------------------------------------------------------------------------
2446

2547
module MCL51_top
2648
(
27-
input CLK,
28-
input RESET_n,
49+
input CLK,
50+
input RESET_n,
2951

30-
input UART_RX,
31-
output UART_TX,
32-
output SPEAKER
52+
input UART_RX,
53+
output UART_TX,
54+
output SPEAKER
3355

3456
);
3557

3658
//------------------------------------------------------------------------
37-
59+
3860

3961
// Internal Signals
4062

@@ -58,57 +80,57 @@ wire [7:0] t_biu_return_data;
5880
assign clk_int = CLK;
5981
assign t_rst_n_int = (t_biu_reset_out==1'b0 && RESET_n==1'b1) ? 1'b1 : 1'b0;
6082

61-
83+
6284
//------------------------------------------------------------------------
6385
// EU Core
6486
//------------------------------------------------------------------------
65-
eu EU_CORE
87+
eu EU_CORE
6688
(
67-
.CORE_CLK (clk_int),
68-
.RST_n (t_rst_n_int),
69-
70-
.EU_BIU_STROBE (t_eu_biu_strobe),
71-
.EU_BIU_DATAOUT (t_eu_biu_dataout),
72-
.EU_REGISTER_R3 (t_eu_register_r3),
73-
.EU_REGISTER_IP (t_eu_register_ip),
74-
75-
.BIU_SFR_ACC (t_biu_sfr_acc),
76-
.BIU_SFR_DPTR (t_biu_sfr_dptr),
77-
.BIU_SFR_SP (t_biu_sfr_sp),
78-
.BIU_SFR_PSW (t_biu_sfr_psw),
79-
.BIU_RETURN_DATA (t_biu_return_data),
80-
.BIU_INTERRUPT (t_biu_interrupt)
81-
82-
);
83-
84-
85-
89+
.CORE_CLK (clk_int),
90+
.RST_n (t_rst_n_int),
91+
92+
.EU_BIU_STROBE (t_eu_biu_strobe),
93+
.EU_BIU_DATAOUT (t_eu_biu_dataout),
94+
.EU_REGISTER_R3 (t_eu_register_r3),
95+
.EU_REGISTER_IP (t_eu_register_ip),
96+
97+
.BIU_SFR_ACC (t_biu_sfr_acc),
98+
.BIU_SFR_DPTR (t_biu_sfr_dptr),
99+
.BIU_SFR_SP (t_biu_sfr_sp),
100+
.BIU_SFR_PSW (t_biu_sfr_psw),
101+
.BIU_RETURN_DATA (t_biu_return_data),
102+
.BIU_INTERRUPT (t_biu_interrupt)
103+
104+
);
105+
106+
107+
86108
//------------------------------------------------------------------------
87109
// BIU Core
88110
//------------------------------------------------------------------------
89-
biu BIU_CORE
111+
biu BIU_CORE
90112
(
91-
.CORE_CLK (clk_int),
92-
.RST_n (t_rst_n_int),
93-
.UART_RX (UART_RX),
94-
.UART_TX (UART_TX),
95-
.SPEAKER (SPEAKER),
96-
.EU_BIU_STROBE (t_eu_biu_strobe),
97-
.EU_BIU_DATAOUT (t_eu_biu_dataout),
98-
.EU_REGISTER_R3 (t_eu_register_r3),
99-
.EU_REGISTER_IP (t_eu_register_ip),
100-
.BIU_SFR_ACC (t_biu_sfr_acc),
101-
.BIU_SFR_DPTR (t_biu_sfr_dptr),
102-
.BIU_SFR_SP (t_biu_sfr_sp),
103-
.BIU_SFR_PSW (t_biu_sfr_psw),
104-
.BIU_RETURN_DATA (t_biu_return_data),
105-
.BIU_INTERRUPT (t_biu_interrupt),
106-
.RESET_OUT (t_biu_reset_out)
107-
108-
);
109-
110-
111-
113+
.CORE_CLK (clk_int),
114+
.RST_n (t_rst_n_int),
115+
.UART_RX (UART_RX),
116+
.UART_TX (UART_TX),
117+
.SPEAKER (SPEAKER),
118+
.EU_BIU_STROBE (t_eu_biu_strobe),
119+
.EU_BIU_DATAOUT (t_eu_biu_dataout),
120+
.EU_REGISTER_R3 (t_eu_register_r3),
121+
.EU_REGISTER_IP (t_eu_register_ip),
122+
.BIU_SFR_ACC (t_biu_sfr_acc),
123+
.BIU_SFR_DPTR (t_biu_sfr_dptr),
124+
.BIU_SFR_SP (t_biu_sfr_sp),
125+
.BIU_SFR_PSW (t_biu_sfr_psw),
126+
.BIU_RETURN_DATA (t_biu_return_data),
127+
.BIU_INTERRUPT (t_biu_interrupt),
128+
.RESET_OUT (t_biu_reset_out)
129+
130+
);
131+
132+
133+
112134

113135

114136

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