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Bug in RISCV_C_Version? #4
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Fixed!
Thanks,
-Ted
…________________________________
From: Michael Engel <[email protected]>
Sent: Friday, April 3, 2020 1:31 PM
To: MicroCoreLabs/Projects <[email protected]>
Cc: Subscribed <[email protected]>
Subject: [MicroCoreLabs/Projects] Bug in RISCV_C_Version? (#4)
The comparison operator for "BLTU" in riscv.c (l. 91) should be "<" instead of ">=" (this line is identical to the "BGE" line below it except for the instruction name):
if (opcode==0b1100011 && funct3==0b110) { if (rv5_reg[rs1]**>=**rv5_reg[rs2]) rv5_pc = ( (B_immediate_SE) + rv5_pc) - 0x4; printf(" BLTU "); } else // BLTU
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Sure, you're welcome! Very nice compact code - I wrote a RISC V emulator for
my students in Go, this took quite a number of lines more...
Oh, and thanks for open sourcing your CPU cores, very much appreciated!
Best,
Michael
… On 3 Apr 2020, at 23:40, MicroCoreLabs ***@***.***> wrote:
Fixed!
Thanks,
-Ted
________________________________
From: Michael Engel ***@***.***>
Sent: Friday, April 3, 2020 1:31 PM
To: MicroCoreLabs/Projects ***@***.***>
Cc: Subscribed ***@***.***>
Subject: [MicroCoreLabs/Projects] Bug in RISCV_C_Version? (#4)
The comparison operator for "BLTU" in riscv.c (l. 91) should be "<" instead of ">=" (this line is identical to the "BGE" line below it except for the instruction name):
if (opcode==0b1100011 && funct3==0b110) { if (rv5_reg[rs1]**>=**rv5_reg[rs2]) rv5_pc = ( (B_immediate_SE) + rv5_pc) - 0x4; printf(" BLTU "); } else // BLTU
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Reply to this email directly, view it on GitHub<#4>, or unsubscribe<https://github.com/notifications/unsubscribe-auth/AM4AVEP4WO5ODXIB3TLU7FTRKZBSDANCNFSM4L4NRKQQ>.
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The comparison operator for "BLTU" in riscv.c (l. 91) should be "<" instead of ">=" (this line is identical to the "BGE" line below it except for the instruction name):
if (opcode==0b1100011 && funct3==0b110) { if (rv5_reg[rs1]**>=**rv5_reg[rs2]) rv5_pc = ( (B_immediate_SE) + rv5_pc) - 0x4; printf(" BLTU "); } else // BLTU
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