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Yan Churkin
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[slang] Introduce clock resolution support (SystemVerilog LRM 16.13/16.16 sections).
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Diff for: ‎docs/command-line-ref.dox

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@@ -289,6 +289,11 @@ Specifies a default time scale to use for design elements that don't explicitly
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provide one. If this option is not set, there is no default and an error will be
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issued if not all elements have a time scale specified. Example: `--timescale=1ns/1ns`
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`--disable-clock-resolution`
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Disables clock resolution checks from SystemVerilog LRM 16.13 section which
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are performed by default.
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`-G <name>=<value>`
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Override all parameters with the given name in top-level modules to the provided value.

Diff for: ‎include/slang/ast/ClockResolution.h

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@@ -0,0 +1,295 @@
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//------------------------------------------------------------------------------
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// ClockResolution.h
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// Clock resolution AST visitors and helpers
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//
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// SPDX-FileCopyrightText: ISP RAS
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// SPDX-License-Identifier: MIT
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//------------------------------------------------------------------------------
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#pragma once
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#include "slang/ast/ASTVisitor.h"
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#include "slang/ast/symbols/CompilationUnitSymbols.h"
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#include "slang/diagnostics/CompilationDiags.h"
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namespace slang::ast::clk_res {
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using namespace syntax;
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struct ClockingEvent {
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using EventList = SmallVector<const Symbol*>;
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enum ClockingEventKind { None, SeqProp, Default, Always } kind;
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bool initialize(ClockingEventKind eventKind, const SignalEventControl* sEC,
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Compilation& compilation);
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bool operator==(const ClockingEvent&) const;
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/// For diagnostics
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SourceRange sourceRange;
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/// For simple event expression with just edge wrapped signals
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EventList events;
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EdgeKind edge;
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/// For storing complex event expression (with `iff` also).
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/// Storing AST as a string is necessary in order to determine if there are any identical events
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/// by comparing strings.
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std::string strEvent;
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};
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/// Visitor checks the properties and sequences at `clocking` blocks to determine it's signal event
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/// list
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class ClockingBlockVisitor : public ASTVisitor<ClockingBlockVisitor, true, true> {
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public:
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ClockingBlockVisitor(Compilation& compilation, const SignalEventControl* clkBlkSEC,
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const SourceLocation sLoc) :
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compilation(compilation), clkBlkSEC(clkBlkSEC), sLoc(sLoc) {}
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void handle(const AssertionInstanceExpression&);
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void handle(const SignalEventControl&);
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private:
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Compilation& compilation;
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/// Clocking block signal event control expression
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const SignalEventControl* clkBlkSEC;
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/// Stack for storing current assertion instance context to get it's scope later
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SmallVector<const AssertionInstanceExpression*> aInstP;
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/// For diagnostics
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const SourceLocation sLoc;
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};
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/// Endpoint of analysis which is represented by possible leaf nodes.
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/// It emits an error if any leaf was reached with no determined clock event but adds it
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/// into the context if not.
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#define REPORT_INFERRED(EXPR) \
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void handle(const EXPR&) { \
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if (clkEvents.empty()) { \
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if (inferred.empty()) \
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compilation.getRoot().addDiag(diag::NoClockResolved, sourceRange); \
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else \
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addUniqueCE(inferred.back()); \
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} \
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}
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/// Sequence verify visitor
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class SequenceVisitor : public ASTVisitor<SequenceVisitor, true, true> {
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public:
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SequenceVisitor(Compilation& compilation, SourceRange sourceRange,
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SmallVector<ClockingEvent>& inferred, SmallVector<ClockingEvent>& clkEvents,
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bool ignoreSubSeq) :
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compilation(compilation), sourceRange(sourceRange), inferred(inferred),
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clkEvents(clkEvents), ignoreSubSeq(ignoreSubSeq) {}
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SmallVector<ClockingEvent> merge(const SmallVector<ClockingEvent>& first,
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const SmallVector<ClockingEvent>& second);
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/// Check the clocking event presense in visitor clocking event lists and add into it if not
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void addUniqueCE(const ClockingEvent&);
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REPORT_INFERRED(ValueExpressionBase)
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REPORT_INFERRED(CallExpression)
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REPORT_INFERRED(IntegerLiteral)
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REPORT_INFERRED(RealLiteral)
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REPORT_INFERRED(TimeLiteral)
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REPORT_INFERRED(UnbasedUnsizedIntegerLiteral)
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REPORT_INFERRED(NullLiteral)
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REPORT_INFERRED(UnboundedLiteral)
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REPORT_INFERRED(StringLiteral)
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void handle(const BinaryAssertionExpr&);
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void handle(const SequenceConcatExpr&);
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void handle(const ClockingAssertionExpr&);
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private:
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Compilation& compilation;
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/// For diagnostics
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SourceRange sourceRange;
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/// Sequence inferred clock events
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SmallVector<ClockingEvent>& inferred;
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/// List of all current context clocking events
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SmallVector<ClockingEvent>& clkEvents;
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/// Store binary and concat operators left and right part clocking event lists
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/// to compare it later
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SmallVector<ClockingEvent> binClkEvents;
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/// Flag to ignore checking nested nodes in the case of assumptions or restrictions being made.
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bool ignoreSubSeq;
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};
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/// Concurrent assertion visitor
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class ConcurrentAssertionVisitor : public ASTVisitor<ConcurrentAssertionVisitor, true, true> {
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public:
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ConcurrentAssertionVisitor(Compilation& compilation, SourceRange sourceRange,
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SmallVector<ClockingEvent>& inferred, bool explicitClocking) :
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compilation(compilation), sourceRange(sourceRange), inferred(inferred) {
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// Below is a implementation of the VCS check which emits an error for such type of sequence
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// property
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// `sequence seqX; @(negedge clk) a ##1 @(posedge clk_n)b; endsequence`
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// `always @(posedge_clk) assert property (seqX);`
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if (!explicitClocking && inferred.size() && inferred.back().kind == ClockingEvent::Always) {
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clkEvents.push_back(inferred.back());
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}
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}
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void addUniqueCE(const ClockingEvent&);
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REPORT_INFERRED(ValueExpressionBase)
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REPORT_INFERRED(CallExpression)
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REPORT_INFERRED(IntegerLiteral)
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REPORT_INFERRED(RealLiteral)
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REPORT_INFERRED(TimeLiteral)
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REPORT_INFERRED(UnbasedUnsizedIntegerLiteral)
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REPORT_INFERRED(NullLiteral)
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REPORT_INFERRED(UnboundedLiteral)
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REPORT_INFERRED(StringLiteral)
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void handle(const AbortAssertionExpr&);
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void handle(const ConditionalAssertionExpr&);
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void handle(const CaseAssertionExpr&);
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void handle(const SequenceConcatExpr&);
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void handle(const ClockingAssertionExpr&);
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void handle(const UnaryAssertionExpr&);
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void handle(const BinaryAssertionExpr&);
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void handle(const AssertionInstanceExpression&);
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/// List of current context clocking events
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SmallVector<ClockingEvent> clkEvents;
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private:
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Compilation& compilation;
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/// For diagnostics
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SourceRange sourceRange;
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/// Sequence/property inferred clock events
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SmallVector<ClockingEvent>& inferred;
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/// Flag to ignore checking nested nodes in the case of assumptions or restrictions being made.
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bool ignoreSubSeq = false;
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};
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/// Visitor to collect all possible inferred clocks at `SignalEventControl` expression
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class AlwaysTimingVisitor : public ASTVisitor<AlwaysTimingVisitor, true, true> {
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public:
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AlwaysTimingVisitor(Compilation& compilation, SmallVector<ClockingEvent>& inferred,
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ClockingEvent& checkerInferredClock) :
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compilation(compilation), inferred(inferred), checkerInferredClock(checkerInferredClock) {}
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void handle(const SignalEventControl&);
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private:
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Compilation& compilation;
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/// List of inferred clocks
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SmallVector<ClockingEvent>& inferred;
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/// Previously stored checker instance inferred clock
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ClockingEvent& checkerInferredClock;
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};
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/// Visitor to erase from a list of inferred clocking events that signals which is used outside
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/// assertions (that isn't a real clock due to SystemVerilog LRM).
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/// It also checks that delay are not present before assertion.
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class AlwaysTimingCheckUseVisitor : public ASTVisitor<AlwaysTimingCheckUseVisitor, true, true> {
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public:
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AlwaysTimingCheckUseVisitor(Compilation& compilation, SmallVector<ClockingEvent>& inferred) :
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compilation(compilation), inferred(inferred) {
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delayBeforeAssert = nullptr;
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}
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void handle(const ConcurrentAssertionStatement&) {
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if (delayBeforeAssert) {
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compilation.getRoot().addDiag(diag::AssertAfterTimingControl,
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delayBeforeAssert->sourceRange);
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delayBeforeAssert = nullptr;
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}
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// No `defaultVisit` for ignoring subsidaries
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}
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void handle(const ImmediateAssertionStatement&) {
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// IEEE Std 1800-2017 16.14.6.c.2
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// Ignore subsidaries
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}
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void handle(const ValueExpressionBase& vEB) {
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for (auto& iter : inferred) {
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auto& iterEvList = iter.events;
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if (iter.kind == ClockingEvent::Always &&
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(std::find(iterEvList.begin(), iterEvList.end(), &vEB.symbol) != iterEvList.end()))
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iterEvList.clear();
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}
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inferred.erase(std::remove_if(inferred.begin(), inferred.end(),
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[](const auto& cE) { return cE.events.empty(); }),
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inferred.end());
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}
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void handle(const TimingControl& tC) {
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if ((tC.as_if<DelayControl>() || tC.as_if<SignalEventControl>()) && !delayBeforeAssert)
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delayBeforeAssert = &tC;
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}
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private:
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Compilation& compilation;
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/// List of `always` block inferred clocks
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SmallVector<ClockingEvent>& inferred;
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// For delay storing which is present before assertion
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const TimingControl* delayBeforeAssert;
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};
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/// Instance body helper visitor - visiting should start at InstanceBody symbol
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class InstanceBodyVisitor : public ASTVisitor<InstanceBodyVisitor, true, true> {
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public:
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InstanceBodyVisitor(Compilation& compilation, ClockingEvent& ce, bool skipCheckerBody = true) :
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compilation(compilation), skipCheckerBody(skipCheckerBody) {
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if (ce.events.size() || ce.strEvent != "")
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inferred.push_back(ce);
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}
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void processPropSeq(const Symbol&) const;
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/// If skipCheckerBody is set to false, then we skip the current checker instance body to
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/// process it later by using the instances array at the ProceduralCheckerStatement handler
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/// below. In reality, a checker instance can be located, for example, inside an always block,
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/// but according to the AST, it may appear outside, preventing a correct understanding of the
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/// context of inferred clocks. Therefore, the processing of checker instances can be delayed.
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void handle(const CheckerInstanceBodySymbol& sym) {
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if (!skipCheckerBody)
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visitDefault(sym);
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}
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void handle(const ProceduralCheckerStatement&);
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void handle(const ProceduralBlockSymbol&);
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void handle(const PropertySymbol&);
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void handle(const SequenceSymbol&);
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void handle(const ConcurrentAssertionStatement&);
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void handle(const ClockingBlockSymbol&);
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/// Skip instance body members because the outermost top-level `ClockResolutionVisitor`
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/// already handles it.
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void handle(const InstanceBodySymbol&) {}
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private:
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Compilation& compilation;
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/// For emitting clocking block nested sequences
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const SignalEventControl* clkBlkSEC{};
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/// List for storing found inferred clocks
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SmallVector<ClockingEvent> inferred;
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/// For storing checker instance context inferred clock
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ClockingEvent checkerInferredClock;
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/// Checker instance body skipping control
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bool skipCheckerBody = true;
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};
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/// Visitor helper for checking nested invalid nodes to ignore their parents later
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class MarkInvalidVisitor : public ASTVisitor<MarkInvalidVisitor, true, true> {
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public:
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void handle(const ClockingAssertionExpr& e) {
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if (e.clocking.bad())
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invalid = true;
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visitDefault(e);
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}
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void handle(const SimpleAssertionExpr& e) {
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if (e.expr.bad())
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invalid = true;
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visitDefault(e);
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}
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bool invalid = false;
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};
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class ClockResolutionVisitor : public ASTVisitor<ClockResolutionVisitor, false, false> {
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public:
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ClockResolutionVisitor(Compilation& compilation) : compilation(compilation) {}
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void handle(const InstanceBodySymbol&);
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private:
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Compilation& compilation;
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};
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} // namespace slang::ast::clk_res

Diff for: ‎include/slang/ast/Compilation.h

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@@ -204,6 +204,24 @@ struct SLANG_EXPORT CompilationOptions {
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/// A list of library names, in the order in which they should be searched
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/// when binding cells to instances.
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std::vector<std::string> defaultLiblist;
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/// Disable clock resolution checking
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bool disableClockResolution = false;
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// Do not check a multiclocked property with contextually inferred leading clocking event in an
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// always block in terms of vcs compatibility.
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// This is only "true" if the compat option have "vcs" value.
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// This was done to support this case (from 16.16 section):
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// ```
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// always @(negedge clk)
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// a3: assert property ($fell(c) |=> q2); // VCS doesn't emits any error on it
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// // illegal: multiclocked property with contextually
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// // inferred leading clocking event
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// end
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// ```
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// Despite the fact that the LRM says that for the right-hand property of the implication and
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// followed by property the is ignored the entire property is multi-clock.
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bool ignoreRightOfBOp = false;
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};
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/// Information about how a bind directive applies to some definition

Diff for: ‎include/slang/driver/Driver.h

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@@ -221,6 +221,9 @@ class SLANG_EXPORT Driver {
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/// @}
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/// Disable clock resolution checking
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std::optional<bool> disableClockResolution;
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/// Returns true if the lintMode option is provided.
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bool lintMode() const;
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} options;

Diff for: ‎scripts/diagnostics.txt

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@@ -1098,6 +1098,15 @@ error UnknownLibrary "unknown library '{}'"
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error NestedConfigMultipleTops "non-top config '{}' has more than one top cell specified"
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error ConfigParamsIgnored "parameter overrides provided by config rule are ignored because the target instance is using a different nested config '{}'"
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error MultipleTopDupName "more than one top module specified with the name '{}'"
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error NoClockResolved "no clock could be resolved for concurrent property"
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error ClockinBlockClockEvent "explicit clocking event in clocking block"
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error DiffClockInClockinBlock "the property/sequence has clocking event not identical to that of the clocking block"
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error NotUniqueLeadingClock "single semantic leading clock expected for top-level sequence/property expression"
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error MaxPropBadClkEven "no default, inferred, or explicit leading clocking event and maximal property is not an instance"
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error AssertAfterTimingControl "procedural assertion (assert, assume or cover property) is not allowed after delay or event control statement"
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error SingleClockBinSeqExpected "clocking events of binary '{}' sequence/property operands doesn't agree"
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error SingleClockDelaySeqExpected "clocking events of delay concatenation operands doesn't agree"
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error MultiClkConcatAdmitsEmpty "differently clocked sequence shall not admit any empty match"
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warning unused-def UnusedDefinition "{} definition is unused"
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warning unused-net UnusedNet "unused net '{}'"
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warning unused-implicit-net UnusedImplicitNet "implicit net '{}' is unused elsewhere"
@@ -1119,6 +1128,7 @@ warning unused-import UnusedImport "unused import '{}'"
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warning unused-wildcard-import UnusedWildcardImport "unused wildcard import"
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warning missing-top NoTopModules "no top-level modules found in design"
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warning duplicate-defparam DuplicateDefparam "parameter already has a defparam override applied; ignoring this one"
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note FoundClocks "found clocks:"
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subsystem Meta
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error TooManyErrors "too many errors emitted, stopping now [--error-limit=]"

Diff for: ‎source/ast/CMakeLists.txt

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@@ -47,6 +47,7 @@ target_sources(
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ASTContext.cpp
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ASTSerializer.cpp
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Bitstream.cpp
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ClockResolution.cpp
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Compilation.cpp
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Constraints.cpp
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EvalContext.cpp

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