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This is not an error issued by slang directly. I assume it's coming from the yosys_slang plugin; I'd raise it over at https://github.com/povik/yosys-slang Probably they simply haven't gotten around to hooking up support for inout ports. |
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Thank you. At least good to hear that the code should compile ok.
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09.02.2025 20:03:24 Michael Popoloski ***@***.***>:
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This is not an error issued by slang directly. I assume it's coming from the yosys_slang plugin; I'd raise it over at https://github.com/povik/yosys-slang
Probably they simply haven't gotten around to hooking up support for inout ports.
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Hello, sorry for bothering but I just changed over from plain verilog (yosys) to system verilog using the yosys_slang module. After I fixed several warnings thankfully shown by slang, I am now left with 8x the same error which is, as I thing, doing some really easy stuff:
I am instantiating a module from my top-level module. It is using eight inout wires "io_psram_data0"-"io_psram_data7" which I named all the same in the .ccf file, in my instantiation and in the module itself:
Sorry for this question, I digged a lot and studied several system verilog articles but I cannot find out why this should not work...??
Any help is greatly appreciated.
Thanks,
Bernd.
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