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Copy file name to clipboardExpand all lines: ERRATA.md
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## HDK
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1. CL simulation might show the following "error" message if the [CL clock generator](./hdk/docs/AWS_CLK_GEN_spec.md) is contained in the design. By default, the generator blocks all output clocks (except for `o_clk_main_a0`) and asserts all output resets. This behavior violates the built-in reset check in the [AXI SmartConnect IP](https://www.xilinx.com/products/intellectual-property/smartconnect.html#overview). This message can be safely ignored. A Fix for this issue is in progress.
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1. Support for the XDMA Shell in the HDK design flow is not available at this time. CL builds using the XDMA Shell will result in a build failure.
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2. CL simulation might show the following "error" message if the [CL clock generator](./hdk/docs/AWS_CLK_GEN_spec.md) is contained in the design. By default, the generator blocks all output clocks (except for `o_clk_main_a0`) and asserts all output resets. This behavior violates the built-in reset check in the [AXI SmartConnect IP](https://www.xilinx.com/products/intellectual-property/smartconnect.html#overview). This message can be safely ignored. A Fix for this issue is in progress.
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```bash
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# ** Error: [SmartConnect 500-33] s_sc_aresetn should be asserted for at least 16 cycles of m_sc_aclk. tb.card.fpga.CL.CL_HBM.HBM_PRESENT_EQ_1.AXI_CONVERTER_AXI4_AXI3.cl_axi_sc_1x1_i.smartconnect_0.inst.s00_nodes.s00_aw_node.inst.<protected>.<protected>
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```
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2. CL simulation might show the following "error" message. This message can be safely ignored. A Fix forthis issue isin progress.
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3. CL simulation might show the following "error" message. This message can be safely ignored. A Fix forthis issue isin progress.
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```bash
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# Initializing memory from data in 'ddr4_ddr_10.mem'.
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# ERROR: Failed to write data burst length to 16. Only <4,8> are valid.
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```
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3. XSIM simulator does not support a cycle-accurate simulation model forthe HBM IP. We’re observing significantly longer simulation times compared to VCS and Questa simulators. This is caused by the HBM BFM usedin XSIM. Therefore, running HBM simulation using VCS or Questa is strongly recommended.
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4. XDMA driver interrupt mode doesn't work currently on instances. Runtime examples have temporarily switched to use the polling mode and the interrupt mode test has been temporarily removed. Refer to the [XDMA driver installation guide](./hdk/docs/XDMA_Install.md) for instructions on how to load XDMA driver using the polling mode.
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4. XSIM simulator does not support a cycle-accurate simulation model forthe HBM IP. We’re observing significantly longer simulation times compared to VCS and Questa simulators. This is caused by the HBM BFM usedin XSIM. Therefore, running HBM simulation using VCS or Questa is strongly recommended.
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5. The following hdk tests are not supported in XSIM currently and will report not supported warning if ran:
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5. The following HDK tests are currently not supported in XSIM and will report not supported warning if ran:
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- cl_mem_perf:
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- test_dram_dma_4k_crossing
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6. Simulation of the [HBM monitor interface](./hdk/docs/AWS_Shell_Interface_Specification.md/#hbm-monitor-interface) is not supported in this release. The HBM IP always passes initialization and remains in an operating state for all tests. Simulation support for the HBM monitor will be added in a future release.
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7. AFIs created based on HDK XDMA shell or Vitis are not supported on F2 instances at this time.
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7. AFIs created based on HDK XDMA shell or Vitis are not supported on F2
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instances at this time.
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8. The following ddr simulation backdoor test is not working with 64GB memory:
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- test_ddr_peek_bdr_walking_ones
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## SDK
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## Software defined Accelerator Development (Vitis)
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- Support for 2024.1 and hardware emulation only. Software emulation and F2 instance support is not supported at this time.
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1. Only hardware emulation via Vitis 2024.1 is currently supported.
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2. Support for Vitis 2024.1 accelerator binary creation and AFI creation is not supported, but will be released at a later time.
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3. Support for Vitis software emulation has been deprecated by AMD, therefore, no longer supported.
Copy file name to clipboardExpand all lines: README.md
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For full documentation, including a user guide, code snippets, and tutorials, see the [AWS EC2 FPGA Development Kit User Guide](./User_Guide_AWS_EC2_FPGA_Development_Kit.md)
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## F2 FPGA ReadTheDocs (Beta)
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We are currently migrating our F2 documentation to comply with the ReadTheDocs standard. To familiarize yourself with the new layout, please [click here](https://awsdocs-fpga-f2.readthedocs-hosted.com).
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## Support
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To raise an issue or receive support, please [open an issue on the official GitHub page](https://github.com/aws/aws-fpga/issues).
Updates to HDK, SDK, and Vitis documentation. Added check for XRT install to enable Vitis hardware emulation. XRT install can now be performed automatically by running a command presented during `vitis_setup.sh`.
Shell errata is `documented here <./hdk/docs/AWS_Shell_ERRATA.md>`__
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HDK
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---
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1. Support for the XDMA Shell in the HDK design flow is not available at this time.
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CL builds using the XDMA Shell will result in a build failure.
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2. CL simulation might show the following "error" message if the `CL
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clock generator <./hdk/docs/AWS_CLK_GEN_spec.md>`__ is contained in
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the design. By default, the generator blocks all output clocks
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(except for ``o_clk_main_a0``) and asserts all output resets. This
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behavior violates the built-in reset check in the `AXI SmartConnect
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IP <https://www.xilinx.com/products/intellectual-property/smartconnect.html#overview>`__.
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This message can be safely ignored. A Fix for this issue is in
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progress.
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.. code:: bash
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# ** Error: [SmartConnect 500-33] s_sc_aresetn should be asserted for at least 16 cycles of m_sc_aclk. tb.card.fpga.CL.CL_HBM.HBM_PRESENT_EQ_1.AXI_CONVERTER_AXI4_AXI3.cl_axi_sc_1x1_i.smartconnect_0.inst.s00_nodes.s00_aw_node.inst.<protected>.<protected>
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3. CL simulation might show the following "error" message. This message
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can be safely ignored. A Fix for this issue is in progress.
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.. code:: bash
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# Initializing memory from data in 'ddr4_ddr_10.mem'.
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# Reading data in x8 and bl:8 mode (Change with 'config <4,8,16> <4,8>' in this file).
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# 'ddr4_ddr_10.mem' set write data width to x4.
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# ERROR: Failed to write data burst length to 16. Only <4,8> are valid.
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4. XSIM simulator does not support a cycle-accurate simulation model for
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the HBM IP. We’re observing significantly longer simulation times
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compared to VCS and Questa simulators. This is caused by the HBM BFM
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used in XSIM. Therefore, running HBM simulation using VCS or Questa
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is strongly recommended.
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5. The following hdk tests are not supported in XSIM currently and will
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