From ac9133c6c30f166d0c56752bdd2c034382d88c4c Mon Sep 17 00:00:00 2001 From: bartz-nvidia Date: Thu, 16 Jan 2025 10:11:30 -0800 Subject: [PATCH 1/2] "add DGXH100 platform option" --- PyTorch/Classification/ConvNets/configs.yml | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/PyTorch/Classification/ConvNets/configs.yml b/PyTorch/Classification/ConvNets/configs.yml index 2780517a6..81bbc3e76 100644 --- a/PyTorch/Classification/ConvNets/configs.yml +++ b/PyTorch/Classification/ConvNets/configs.yml @@ -30,7 +30,10 @@ platform: workers: 10 prefetch: 4 gpu_affinity: socket_unique_contiguous - + DGXH100: + workers: 10 + prefetch: 4 + gpu_affinity: socket_unique_contiguous mode: benchmark_training: &benchmark_training print_freq: 1 From da3e7a3514cf8ff286365a3f84eb16e74ff90a4e Mon Sep 17 00:00:00 2001 From: bartz-nvidia Date: Thu, 16 Jan 2025 22:28:59 +0000 Subject: [PATCH 2/2] update entire config file to include DGXH100, not just platform options --- PyTorch/Classification/ConvNets/configs.yml | 99 +++++++++++++++++++++ 1 file changed, 99 insertions(+) diff --git a/PyTorch/Classification/ConvNets/configs.yml b/PyTorch/Classification/ConvNets/configs.yml index 81bbc3e76..602372fc7 100644 --- a/PyTorch/Classification/ConvNets/configs.yml +++ b/PyTorch/Classification/ConvNets/configs.yml @@ -171,6 +171,25 @@ models: FP32: <<: *resnet_params_2k batch_size: 128 + DGXH100: + AMP: + <<: *resnet_params_2k + arch: resnet50 + batch_size: 256 + memory_format: nhwc + TF32: + <<: *resnet_params_2k + arch: resnet50 + batch_size: 256 + T4: + AMP: + <<: *resnet_params_2k + arch: resnet50 + batch_size: 256 + memory_format: nhwc + FP32: + <<: *resnet_params_2k + batch_size: 128 # }}} resnext101-32x4d: # {{{ DGX1V: &RNXT_DGX1V @@ -207,6 +226,16 @@ models: <<: *resnet_params_1k arch: resnext101-32x4d batch_size: 64 + DGXH100: + AMP: + <<: *resnet_params_1k + arch: resnext101-32x4d + batch_size: 128 + memory_format: nhwc + TF32: + <<: *resnet_params_1k + arch: resnext101-32x4d + batch_size: 128 # }}} se-resnext101-32x4d: # {{{ DGX1V: &SERNXT_DGX1V @@ -233,6 +262,16 @@ models: <<: *resnet_params_1k arch: se-resnext101-32x4d batch_size: 128 + DGXH100: + AMP: + <<: *resnet_params_1k + arch: se-resnext101-32x4d + batch_size: 128 + memory_format: nhwc + TF32: + <<: *resnet_params_1k + arch: se-resnext101-32x4d + batch_size: 128 T4: AMP: <<: *resnet_params_1k @@ -285,6 +324,16 @@ models: <<: *efficientnet_b0_params_4k arch: efficientnet-widese-b0 batch_size: 256 + DGXH100: + AMP: + <<: *efficientnet_b0_params_4k + arch: efficientnet-widese-b0 + batch_size: 256 + memory_format: nhwc + TF32: + <<: *efficientnet_b0_params_4k + arch: efficientnet-widese-b0 + batch_size: 256 # }}} efficientnet-b0: # {{{ T4: @@ -327,6 +376,16 @@ models: <<: *efficientnet_b0_params_4k arch: efficientnet-b0 batch_size: 256 + DGXH100: + AMP: + <<: *efficientnet_b0_params_4k + arch: efficientnet-b0 + batch_size: 256 + memory_format: nhwc + TF32: + <<: *efficientnet_b0_params_4k + arch: efficientnet-b0 + batch_size: 256 # }}} efficientnet-quant-b0: # {{{ T4: @@ -369,6 +428,16 @@ models: <<: *efficientnet_b0_params_4k arch: efficientnet-quant-b0 batch_size: 256 + DGXH100: + AMP: + <<: *efficientnet_b0_params_4k + arch: efficientnet-quant-b0 + batch_size: 256 + memory_format: nhwc + TF32: + <<: *efficientnet_b0_params_4k + arch: efficientnet-quant-b0 + batch_size: 256 # }}} efficientnet-widese-b4: # {{{ T4: @@ -411,6 +480,16 @@ models: <<: *efficientnet_b4_params_4k arch: efficientnet-widese-b4 batch_size: 64 + DGXH100: + AMP: + <<: *efficientnet_b4_params_4k + arch: efficientnet-widese-b4 + batch_size: 128 + memory_format: nhwc + TF32: + <<: *efficientnet_b4_params_4k + arch: efficientnet-widese-b4 + batch_size: 64 # }}} efficientnet-b4: # {{{ T4: @@ -453,6 +532,16 @@ models: <<: *efficientnet_b4_params_4k arch: efficientnet-b4 batch_size: 64 + DGXH100: + AMP: + <<: *efficientnet_b4_params_4k + arch: efficientnet-b4 + batch_size: 128 + memory_format: nhwc + TF32: + <<: *efficientnet_b4_params_4k + arch: efficientnet-b4 + batch_size: 64 # }}} efficientnet-quant-b4: # {{{ T4: @@ -495,4 +584,14 @@ models: <<: *efficientnet_b4_params_4k arch: efficientnet-quant-b4 batch_size: 64 + DGXH100: + AMP: + <<: *efficientnet_b4_params_4k + arch: efficientnet-quant-b4 + batch_size: 128 + memory_format: nhwc + TF32: + <<: *efficientnet_b4_params_4k + arch: efficientnet-quant-b4 + batch_size: 64 # }}}