@@ -75,7 +75,7 @@ struct ts_channel_hw_conf_s {
7575 TS_AFE_0_COUPLING_REG , TS_AFE_0_COUPLING_MASK ,
7676 TS_AFE_0_ATTEN_REG , TS_AFE_0_ATTEN_MASK ,
7777 TS_AFE_0_TRIM_DAC , TS_AFE_0_TRIM_DPOT ,
78- HMCAD15_ADC_IN4 , TS_ADC_CH_INVERT
78+ HMCAD15_ADC_IN4 , TS_ADC_CH_NO_INVERT
7979
8080 },
8181 // Channel 2
@@ -85,7 +85,7 @@ struct ts_channel_hw_conf_s {
8585 TS_AFE_1_COUPLING_REG , TS_AFE_1_COUPLING_MASK ,
8686 TS_AFE_1_ATTEN_REG , TS_AFE_1_ATTEN_MASK ,
8787 TS_AFE_1_TRIM_DAC , TS_AFE_1_TRIM_DPOT ,
88- HMCAD15_ADC_IN3 , TS_ADC_CH_INVERT
88+ HMCAD15_ADC_IN3 , TS_ADC_CH_NO_INVERT
8989 },
9090 // Channel 3
9191 {
@@ -94,7 +94,7 @@ struct ts_channel_hw_conf_s {
9494 TS_AFE_2_COUPLING_REG , TS_AFE_2_COUPLING_MASK ,
9595 TS_AFE_2_ATTEN_REG , TS_AFE_2_ATTEN_MASK ,
9696 TS_AFE_2_TRIM_DAC , TS_AFE_2_TRIM_DPOT ,
97- HMCAD15_ADC_IN2 , TS_ADC_CH_INVERT
97+ HMCAD15_ADC_IN2 , TS_ADC_CH_NO_INVERT
9898 },
9999 // Channel 4
100100 {
@@ -103,7 +103,7 @@ struct ts_channel_hw_conf_s {
103103 TS_AFE_3_COUPLING_REG , TS_AFE_3_COUPLING_MASK ,
104104 TS_AFE_3_ATTEN_REG , TS_AFE_3_ATTEN_MASK ,
105105 TS_AFE_3_TRIM_DAC , TS_AFE_3_TRIM_DPOT ,
106- HMCAD15_ADC_IN1 , TS_ADC_CH_INVERT
106+ HMCAD15_ADC_IN1 , TS_ADC_CH_NO_INVERT
107107 }
108108};
109109
@@ -142,6 +142,15 @@ int32_t ts_channel_init(tsChannelHdl_t* pTsChannels, file_t ts)
142142 betaDevice = true;
143143 }
144144
145+ //Units prior to HWID 2 (Gamma HW Rev 5.3) have the ADC P/N pairs swapped
146+ if ((id & (( 1UL << CSR_DEV_STATUS_HW_ID_HW_REV_SIZE ) - 1 )) < 0x2 )
147+ {
148+ g_channelConf [0 ].adc_invert = TS_ADC_CH_INVERT ;
149+ g_channelConf [1 ].adc_invert = TS_ADC_CH_INVERT ;
150+ g_channelConf [2 ].adc_invert = TS_ADC_CH_INVERT ;
151+ g_channelConf [3 ].adc_invert = TS_ADC_CH_INVERT ;
152+ }
153+
145154 //Initialize Status
146155 pChan -> ctrl_handle = ts ;
147156 pChan -> status .adc_lost_buffer_count = 0 ;
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