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NetFPGA-10G.html
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---
layout: page
---
<h1>NetFPGA 10G</h1>
<br>
<div id="accordion-10G1" class="accordion">
<div class="" data-toggle="collapse" href="#collapse-10G1">
<button class="card-title"><h2>Details  </h2></button>
</div>
<div id="collapse-10G1" class="collapse show" data-parent="#accordion-10G1">
<p>The NetFPGA-10G is an FPGA-based PCI Express board with 10-Gigabit SFP+ interface, a x8 gen1 PCIe adapter card incorporating Xilinx’s Virtex-5 TX240TFPGA. It is ideal for the high bandwidth applications.</p>
<p>Features list:</p>
<ul>
<li>Field Programmable Gate Array (FPGA) Logic <ul>
<li><a href="http://www.xilinx.com/support.html#Virtex-II%20Pro" >Xilinx Virtex-5 TX240T</a></li>
<li>240K logic cells</li>
<li>11,664 Kbit block RAM</li>
<li>Fully programmable by the user</li>
</ul></li>
<li>10-Gigabit Ethernet networking ports <ul>
<li>4 SFP+ connectors</li>
<li>Connected to the FPGA through four Broadcom’s AEL2005 PHY devices</li>
<li>Supports both 10-Gigabit and 1-Gigabit modes</li>
</ul></li>
<li>Quad Data Rate Static Random Access Memory (QDRII SRAM) <ul>
<li>Suitable for storing and forwarding table data</li>
<li>300MHz Quad data rate (1.2 Giga transactions every second), synchronous with the logic</li>
<li>Three parallel banks of 72 MBit QDRII+ memories</li>
<li>Total capacity: 27 MBytes</li>
<li><a href="http://www.cypress.com/?mpn=CY7C1515KV18-300BZI" >Cypress: CY7C1515KV18</a></li>
</ul></li>
<li>Reduced Latency Random Access Memory (RLDRAM II) <ul>
<li>Suitable for packet buffering</li>
<li>Four x36 RLDRAMII on-board device</li>
<li>400MHz clock (800MT/s)</li>
<li>115.2 Gbps peak memory throughput</li>
<li>Total Capacity: 288MByte</li>
<li>Micron: MT49H16M36HT-25</li>
</ul></li>
<li>PCI Express Gen. 1 <ul>
<li>First generation PCI Express interface, 2.5Gbps/lane</li>
<li>8 lanes (x8)</li>
<li>Hard IP</li>
<li>Provides CPU access to memory-mapped registers and memory on the NetFPGA hardware</li>
<li>x4 Gen.2 PCI Express can be used as a soft core</li>
</ul></li>
<li>Storage <ul>
<li>Two FLASH devices</li>
<li>Total Capacity: 256Mb</li>
</ul></li>
<li>Expansion Interfaces <ul>
<li>Two SAMTEC QTH connectors</li>
<li>Allowing to connect additional 20 RocketIO GTX transceivers</li>
</ul></li>
<li>Additional Features<ul>
<li>DB9 (RS232) Connector</li>
<li>User LEDs & Push Buttons</li>
</ul></li>
<li>Standard PCIe Form Factor <ul>
<li>Standard PCIe card</li>
<li>3/4 length, full height</li>
</ul></li>
<li>Flexible, Open-source code</li>
</ul>
</div>
</div>
<br>
<hr>
<div id="accordion-10G2" class="accordion">
<div class="collapsed" data-toggle="collapse" href="#collapse-10G2">
<button class="card-title"><h2>Downloads  </h2></button>
</div>
<div id="collapse-10G2" class="collapse" data-parent="#accordion-10G2">
<p>To see the NetFPGA-10G repository and Wiki you will need to <a href="{% link 10G-reg-form.html %}" >register</a>.</p>
<h3>Reference Projects</h3>
<table class="downloads">
<tr>
<th>Title</th>
<th>Organisation</th>
<th>Documentation</th>
</tr>
<tr>
<td>Production Test</td>
<td>Stanford University</td>
<td><a href="https://github.com/NetFPGA/NetFPGA-public/wiki/NetFPGA-10G-Production-Test" >Wiki</a></td>
</tr>
<tr>
<td>RLDRAM Test</td>
<td>Xilinx</td>
<td><a href="https://github.com/NetFPGA/NetFPGA-public/wiki/NetFPGA-10G%20RLDRAM%20Test" >Wiki</a></td>
</tr>
<tr>
<td>10G Ethernet Interface Loopback Test</td>
<td>Stanford University / University of Cambridge</td>
<td><a href="https://github.com/NetFPGA/NetFPGA-public/wiki/NetFPGA-10G-10G-Ethernet-Interface-Loopback-Test" >Wiki</a></td>
</tr>
<tr>
<td>1G Ethernet Interface Loopback Test</td>
<td>Stanford University / University of Cambridge</td>
<td><a href="https://github.com/NetFPGA/NetFPGA-public/wiki/NetFPGA-10G-1G-Ethernet-Interface-Loopback-Test" >Wiki</a></td>
</tr>
<tr>
<td>Reference NIC 10G</td>
<td>Stanford University / University of Cambridge</td>
<td><a href="https://github.com/NetFPGA/NetFPGA-public/wiki/NetFPGA-10G-Reference-NIC" >Wiki</a></td>
</tr>
<tr>
<td>Reference NIC 1G</td>
<td>Stanford University / University of Cambridge</td>
<td><a href="https://github.com/NetFPGA/NetFPGA-public/wiki/NetFPGA-10G-Reference-NIC-1G" >Wiki</a></td>
</tr>
<tr>
<td>Flash Configuration</td>
<td>University of Cambridge</td>
<td><a href="https://github.com/NetFPGA/NetFPGA-public/wiki/NetFPGA-10G%20Flash%20Configuration" >Wiki</a></td>
</tr>
<tr>
<td>Learning CAM Switch</td>
<td>University of Pisa / University of Cambridge</td>
<td><a href="https://github.com/NetFPGA/NetFPGA-public/wiki/NetFPGA-10G-Learning-CAM-Switch" >Wiki</a></td>
</tr>
</table>
<h3>Contributed Projects</h3>
<table class="downloads">
<tr>
<th>Title</th>
<th>Organisation</th>
<th>Documentation</th>
</tr>
<tr>
<td>NetFPGA-1G Ported Switch 10G</td>
<td>University of Pisa / University of Cambridge</td>
<td><a href="https://github.com/NetFPGA/NetFPGA-public/wiki/NetFPGA-1G-Ported-Switch-10G" >Wiki</a></td>
</tr>
<tr>
<td>NetFPGA-1G Ported NIC 1G</td>
<td>University of Pisa / University of Cambridge</td>
<td><a href="https://github.com/NetFPGA/NetFPGA-public/wiki/NetFPGA-1G-Ported-NIC-1G" >Wiki</a></td>
</tr>
<tr>
<td>NIC</td>
<td>Stanford University / University of Cambridge</td>
<td><a href="https://github.com/NetFPGA/NetFPGA-public/wiki/Contributed-NIC-by-Mario-Flajslik" >Wiki</a></td>
</tr>
<tr>
<td>OpenFlow Switch</td>
<td>Stanford University</td>
<td><a href="https://github.com/NetFPGA/NetFPGA-public/wiki/NetFPGA-10G-OpenFlow-Switch" >Wiki</a></td>
</tr>
<tr>
<td>NIC (SRAM)</td>
<td>Stanford University / University of Cambridge</td>
<td><a href="https://github.com/NetFPGA/NetFPGA-public/wiki/NIC-SRAM" >Wiki</a></td>
</tr>
<tr>
<td>Simple 10G Switch</td>
<td>Xilinx</td>
<td>Wiki</td>
</tr>
<tr>
<td>NetFlow simple 10G Bram</td>
<td>Universidad Autónoma de Madrid</td>
<td><a href="https://github.com/NetFPGA/NetFPGA-public/wiki/NetFlow-simple-10G-Bram" >Wiki</a></td>
</tr>
<tr>
<td>Flash</td>
<td>University of Cambridge</td>
<td><a href="https://github.com/NetFPGA/NetFPGA-public/wiki/Contributed-Flash-by-Muhammad-Shahbaz" >Wiki</a></td>
</tr>
</table>
</div>
</div>
<br>
<hr>
<div id="accordion-10G4" class="accordion">
<div class="collapsed" data-toggle="collapse" href="#collapse-10G4">
<button class="card-title"><h2>Resources  </h2></button>
</div>
<div id="collapse-10G4" class="collapse" data-parent="#accordion-10G4">
<br>
<p class="FAQ">Where can I buy a NetFPGA 10G Platform?</p>
<ul>
<li>Check <a href="http://www.hitechglobal.com/Boards/PCIExpress_SFP+.htm" >here</a>.</li>
</ul>
<p class="FAQ">It seems that my board is broken, what should I do?</p>
<ul>
<li>Contact you <a href="http://www.hitechglobal.com/contactus.htm" >suppliers</a>.</li>
</ul>
<p class="FAQ">What if I have Hardware problems with my board?</p>
<ul>
<li>Contact your supplier or <a href="http://www.hitechglobal.com/contactus.htm" >High Tech Global</a>.</li>
</ul>
<p class="FAQ">What if I have Software problems with my board?</p>
<ul>
<li>Ask the Beta community on the <a href="https://lists.cam.ac.uk/mailman/listinfo/cl-netfpga-nf10g-beta" >NetFPGA 10G Beta mailing list</a>.</li>
</ul>
<p class="FAQ">You can exchange your ideas and questions with the NetFPGA 10G community <a href="https://lists.cam.ac.uk/mailman/listinfo/cl-netfpga-nf10g-beta" >here</a>.</p>
<p class="FAQ">How can I get involved with the NetFPGA project?</p>
<ul>
<li>Register with the <a href="https://lists.cam.ac.uk/mailman/listinfo/cl-netfpga-announce" >netfpga-announce mailing list</a> to receive NetFPGA project announcements</li>
<li>Become a <a href="http://www.facebook.com/home.php#/pages/NetFPGA/29922917839" >fan on Facebook</a>.</li>
<li>Become a <a href="https://twitter.com/netfpga" >fan on Twitter</a>.</li>
</ul>
<p class="FAQ">How can I obtain the gateware and software package?</p>
<ul>
<li><a href="{% link 10G-reg-form.html %}" >Registration</a></li>
<li><a href="https://github.com/NetFPGA/NetFPGA-public/wiki/Release-Notes" >Releases</a></li>
<li><a href="{% link _pages/10G-License.html %}" >NetFPGA 10G license</a></li>
</ul>
<br>
<p>Once you have used the NetFPGA, we hope that you will contribute to the project.</p>
<br>
<p>You can find our Wiki <a href="https://github.com/NetFPGA/netfpga/wiki" >here</a>.</p>
</div>
</div>
<br>
<hr>