70046: added week 2 lectures

OliverKillane · OliverKillane · commit f6f06b8f901c · 2024-01-19T10:11:46.000Z
diff --git a/70046 - EEE - Advanced Digital Systems Design/1T_Dynamic_Cell.png b/70046 - EEE - Advanced Digital Systems Design/1T_Dynamic_Cell.png
diff --git a/70046 - EEE - Advanced Digital Systems Design/6T_SRAM.svg b/70046 - EEE - Advanced Digital Systems Design/6T_SRAM.svg
diff --git a/70046 - EEE - Advanced Digital Systems Design/6T_Static_Cell.png b/70046 - EEE - Advanced Digital Systems Design/6T_Static_Cell.png
diff --git a/70046 - EEE - Advanced Digital Systems Design/Abstraction Layers.md b/70046 - EEE - Advanced Digital Systems Design/Abstraction Layers.md
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+## Layers
+![[abstraction_layers.png]]
+*Image is from ADSD slides*
+
+| Level | Description | Objective |
+| ---- | ---- | ---- |
+| System |  | Defines partitions and the interfaces used to connect between them (e.g. communications, inter-processor, memory hierarchy) |
+| Algorithm |  | Model the behaviour of the system. Simulations to ensure system implements an algorithm correctly. |
+| [[Register Transfer Level\|RTL]]/[[Hardware Description Languages\|HDL]] | The functional level. (using SystemVerilog, VHDL, etc) | Defines the [[Microarchitecture]] , control and data paths, timing/clocking. |
+| Gate | Connecting logic gates. | Define the behaviour of components/building blocks used in the [[Register Transfer Level\|RTL]] |
+| Circuit |  | Implementing logic gate behaviour with transitors. |
+| Device |  | Optimisation of [[Transistor]] parameters |
+## Design Process
+Top down and bottom up design strategies (refining & decomposing down to primitive components, versus building up from primitives).
+- Usually a mixed strategy of mostly top-down with some bottom-up is used.
+## Synthesis
+$$\text{Specification} \to \text{System-Level Model} \to \text{algorithm} \to \text{RTL Model} \to \text{RTL Optimisation} \to \text{generic gate-level model} \to \text{Mapped gate-level model} \to \text{Place and Route}$$
+- Mapped Gate-Level Model depends on the underlying technology (e.g. [[FPGA]] vs [[ASIC]])
diff --git a/70046 - EEE - Advanced Digital Systems Design/Adders.md b/70046 - EEE - Advanced Digital Systems Design/Adders.md
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+- Ripple carry
+- lookahead
+- 
diff --git a/70046 - EEE - Advanced Digital Systems Design/Capacitance.md b/70046 - EEE - Advanced Digital Systems Design/Capacitance.md
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+## Definition
+The ability of an object to store charge.
+$$Capacitance = \cfrac{Charge}{Voltage}$$
diff --git a/70046 - EEE - Advanced Digital Systems Design/Content Addressable Memory.md b/70046 - EEE - Advanced Digital Systems Design/Content Addressable Memory.md
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+## Definition
+A hardware key-value store. User provides a key, and in return gets the location/value (potentially multiple).
+
+## Examples
+### TLB
+Many [[Translation Lookaside Buffer|TLBs]] are implemented using [[Content Addressable Memory]] (provide page virtual address, get cached physical address).
diff --git a/70046 - EEE - Advanced Digital Systems Design/DDR SDRAM.md b/70046 - EEE - Advanced Digital Systems Design/DDR SDRAM.md
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+## Definition
+> *Double Data Rate Synchronous Dynamic Random Access Memory*
+
+A [[Synchronous Dynamic RAM]] where control actions occur on both the falling, and rising edge to double the rate at which accesses can be issued.
diff --git a/70046 - EEE - Advanced Digital Systems Design/Dynamic Memory.md b/70046 - EEE - Advanced Digital Systems Design/Dynamic Memory.md
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+## Definition
+Uses a capacitor to store a charge to represent the bit held.
+- Much smaller than a [[Static Memory#6T SRAM]]
+- leakage from the capacitor requires periodic refresh
+- Includes [[Synchronous Dynamic RAM]] and [[DDR SDRAM]]
+Much like in [[RAM Organisation]] cells are organised by row and column.
+## 1T DRAM
+![[1T_Dynamic_Cell.png]]
+## Access
+| Pin | Name | Purpose |
+| ---- | ---- | ---- |
+| `A` | Address | contain address of cell |
+| `D` | Data | Combined input/output (bidirectional).<br><br>Input when `WE_L` asserted (low) and `OE_L` disasserted (high).<br><br>Output when `WE_L` disasserted (High) and `OE_L` asserted (Low) |
+| `RAS_L` | Row Address Low | Latch in row on low (edge-sensitive) |
+| `CAS_L` | Column Address Low | Latch in column on low (edge-sensitive) |
+| `WE_L` | Write Enable Low | enable writes (edge-sensitive) |
+| `OE_L` | Output Enable Low | enable output (`D` is input also) (edge-sensitive) |
+### Latency
+| Property | Description | 4Mbit DRAM Performance with $t_{RAC} = 60 \ ns$ |
+| ---- | ---- | ---- |
+| $t_{RAC}$ | Minimum time from `RAS` fall to valid data output. (Set row, wait for output) | $60 \ ns$ |
+| $t_{RC}$ | Minimum time from one row access to the next. | $110 \ ns$ |
+| $t_{CAC}$ | Minimum time from `CAS` fall to valid data output. (Set column, wait for output) | $15 \ ns$ |
+| $t_{PC}$ | Minimum time from one column access to the next. | $35 \ ns$ |
+- Accessing different rows is more expensive than different columns. So more same-row access is better.
diff --git a/70046 - EEE - Advanced Digital Systems Design/FIFO Memory.md b/70046 - EEE - Advanced Digital Systems Design/FIFO Memory.md
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+## Definition
+A queue based buffer.
+- Used for IO devices, input (e.g. network interface, smooth bursts from unsynchronised IO pins to constant rate synchronised CPU), and output (e.g. generate audio in bursts, but output at constant rate by DAC) 
+- Can be implemented as a circular queue.
diff --git a/70046 - EEE - Advanced Digital Systems Design/Flip Flop.md b/70046 - EEE - Advanced Digital Systems Design/Flip Flop.md
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+## Definition
+[[TODO]]
+## Comparison
+
+| Type | Transistors | Latency | Power |
+| ---- | ---- | ---- | ---- |
+| [[Flip Flop]] | ~20 | fast |  |
+| [[Static Memory#6T SRAM]] | 6 | medium | low |
+| [[Dynamic Memory#1T DRAM]] | 1 | slow | high |
diff --git a/70046 - EEE - Advanced Digital Systems Design/Hardware Description Languages.md b/70046 - EEE - Advanced Digital Systems Design/Hardware Description Languages.md
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+## Definition
+A language for describing formal representations of digital circuits for simulation, analysis and synthesis.
+- Synthesis is the creation of a [[Netlist]] to use in physically implementing the design.
diff --git a/70046 - EEE - Advanced Digital Systems Design/NIOS II.md b/70046 - EEE - Advanced Digital Systems Design/NIOS II.md
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+## Definition
+A [[Soft Processor]] supporting a 32-bit [[RISC]] architecture, 32 interrupt sources, and optional single-precision floating point operations.
+
+Functional units can be implemented in hardware, emulated in software (e.g. implement floating point multiplication using fixed point instructions for using [[NIOS II]] functional units), or omitted entirely.
+
+| Core Design | Description |
+| ---- | ---- |
+| Nios II/f | Fast performance (large size) |
+| Nios II/s | Balance between *e* and *f* |
+| Nios II/e | Economy core (small size)  |
+## Units
+### ALU
+| Operation | Description |
+| ---- | ---- |
+| Arithmetic | `+,-,/` on unsigned integers |
+| Relational | Comparison operations for `==,!=,>=,<` on signed & unsigned integers |
+| Shift/Rotate | `0-31` positions per instruction, arithmetic right shift & logical right/left shift. |
+*Arithmetic right means shift right, and fill empty left with MSB (hence preserving sign also)*
+### Cache
+On chip separate instruction and data caches.
+- Caches are optional for example when all data and instructions are stored on chip memory (the cache is used for caching external memory, no longer needed)
+- Instruction cache is not effective if instruction cache is much smaller than the working set of instructions (e.g. 2KB hot loop, with 1KB instruction cache)
+### Tightly Coupled Memory
+A guaranteed low-latency memory on chip.
+- No need for cache, so no overhead from using a cache.
+- performance of the memory is similar to cache hit.
+- Cannot be adapted to dynamic behaviour - a fixed region of the available address space is mapped to this memory.
+- Place fast access data/instructions here (e.g. performance critical interrupt code)
diff --git a/70046 - EEE - Advanced Digital Systems Design/Netlist.md b/70046 - EEE - Advanced Digital Systems Design/Netlist.md
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+## Definition
+A description of all the electronic components in an electronic circuit, and how they are connected.
diff --git a/70046 - EEE - Advanced Digital Systems Design/Parasitic Capacitance.md b/70046 - EEE - Advanced Digital Systems Design/Parasitic Capacitance.md
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+## Definition
+Unwanted [[Capacitance]] built up between parts of an electronic circuit due to proximity.
+- Close wires at different voltages generate an electric field that causes change to be stored on both them.
diff --git a/70046 - EEE - Advanced Digital Systems Design/RAM Organisation.md b/70046 - EEE - Advanced Digital Systems Design/RAM Organisation.md
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+
+## Memory Array Structure
+![[basic_memory_array.drawio.svg]]
+Generally we attempt to make the memory array as *square* as possible (word-lines $\approx$ bit-lines) to reduce [[Parasitic Capacitance]] of both groups of lines.
+- This only allows for a single address & data bus supporting a single read/write port.
+## MultiPort Memory
+Increasing bandwidth of read with multiple read ports.
+
diff --git a/70046 - EEE - Advanced Digital Systems Design/Register File.md b/70046 - EEE - Advanced Digital Systems Design/Register File.md
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+## Definition
+A small multiported [[Static Memory]] array.
+- We can implement read/write by using a multiplexor to select the input to the flipflop (either its output, or from the bit-line).
+- A read line is used to open the output using a tristate-buffer.
+![[Register_File_Cell.png]]
+## Access
+| Access | Description | Type |
+| ---- | ---- | ---- |
+| Read | Output is a combinational function of the address input. When address is changed, the output is immediately (at speed of silicon) changed (not reliant on clock). | Asynchronous |
+| Write | Write can only occur when the flipflop allows, hence the write, select and data lines need to be on long enough to hit a clock-tick and update the flip flop's state. | Synchronous |
+![[Register_file_read_write_timing.png]]
+- Read changes continuously (combinational logic), but write only has effect of rising clock edge.
diff --git a/70046 - EEE - Advanced Digital Systems Design/Register Transfer Language.md b/70046 - EEE - Advanced Digital Systems Design/Register Transfer Language.md
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+## Definition
+An assembly-like IR used by compilers describing computations as actions on, and transfers between registers.
+
+**Not to be confused with [[Register Transfer Level]]**
diff --git a/70046 - EEE - Advanced Digital Systems Design/Register Transfer Level.md b/70046 - EEE - Advanced Digital Systems Design/Register Transfer Level.md
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+## Definition
+A design abstraction for modelling [[Synchronous Digital Circuits]] as a flow of signals between hardware registers and the logic applied to the signals.
+
+The abstraction is present in most [[Hardware Description Languages]]
diff --git a/70046 - EEE - Advanced Digital Systems Design/Register_File_Cell.png b/70046 - EEE - Advanced Digital Systems Design/Register_File_Cell.png
diff --git a/70046 - EEE - Advanced Digital Systems Design/Register_file_read_write_timing.png b/70046 - EEE - Advanced Digital Systems Design/Register_file_read_write_timing.png
diff --git a/70046 - EEE - Advanced Digital Systems Design/SRAM_Access.png b/70046 - EEE - Advanced Digital Systems Design/SRAM_Access.png
diff --git a/70046 - EEE - Advanced Digital Systems Design/Soft Processor.md b/70046 - EEE - Advanced Digital Systems Design/Soft Processor.md
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+## Definition
+A general purpose processor synthesised on a [[FPGA]], rather than in custom silicon. 
+- Can be customised/modified (add instructions, add/remove features) and redeployed easily.
diff --git a/70046 - EEE - Advanced Digital Systems Design/Static Memory.md b/70046 - EEE - Advanced Digital Systems Design/Static Memory.md
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+## Definition
+Uses transistors, typically two latches.
+- Lack of leakage (as with [[Dynamic Memory#1T DRAM]]) means low power consumption & no refresh required.
+## 6T SRAM
+A common 6-[[Transistor]] SRAM design.
+![[6T_SRAM.svg]]
+## Access
+Both read & write are asynchronous.
+- A *WE* (write enable) and *OE* (output enable) control output and 
+![[SRAM_Access.png]]
+## Extra
+[Boise State University](https://www.eecis.udel.edu/~vsaxena/courses/ece518/Handouts/SRAM%20Architecture.pdf)
diff --git a/70046 - EEE - Advanced Digital Systems Design/Static vs Dynamic Memory.md b/70046 - EEE - Advanced Digital Systems Design/Static vs Dynamic Memory.md
diff --git a/70046 - EEE - Advanced Digital Systems Design/Synchronous Dynamic RAM.md b/70046 - EEE - Advanced Digital Systems Design/Synchronous Dynamic RAM.md
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+## Definition
+A [[Dynamic Memory]] where the external interface is coordinated by an external clock.
+- Previously changed in control signals had immediate affects (only delayed by distance for current to travel)
+- Synchronous means each (clock - e.g. rising edge) the control input are applied.
+- Allows for pipelining of access operations (each tick a new access can be made, accesses are overlapped for higher throughput)
diff --git a/70046 - EEE - Advanced Digital Systems Design/Taxonomy of Memories.md b/70046 - EEE - Advanced Digital Systems Design/Taxonomy of Memories.md
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+## Taxonomy by Access
+### Random Access
+#### Single Port
+*ROM and RAM*
+#### Multiport
+Provides multiple ports for access to the same data.
+#### Special Purpose
+*[[Register File]]*
+### Associative
+*[[Content Addressable Memory|CAM]]*
+### Implicit Addressing
+*Serial, [[FIFO Memory|FIFO]]/Queue, LIFO/Stack*
+## By Implementation
+### Volatile
+#### [[Static Memory|Static]]
+*SRAM*
+#### Dynamic
+*[[Dynamic Memory|DRAM]], [[Synchronous Dynamic RAM|SDRAM]], [[DDR SDRAM]] and VRAM*
+### Non-Volatile
+*Ferrorelectric/FRAM*
+### Erasable
+- *Block Electrically Erasable/Flash*
+- *Electrically Erasable/$E^2$PROM*
+- *UV Erasable/EPROM*
+### One-Time Programmable
+*OTP ROM or PROM*
+### Mask Programmed
+*ROM*
diff --git a/70046 - EEE - Advanced Digital Systems Design/abstraction_layers.png b/70046 - EEE - Advanced Digital Systems Design/abstraction_layers.png
diff --git a/70046 - EEE - Advanced Digital Systems Design/basic_memory_array.drawio.svg b/70046 - EEE - Advanced Digital Systems Design/basic_memory_array.drawio.svg

Original file line number	Diff line number	Diff line change
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	`1`	`+- Ripple carry`
	`2`	`+- lookahead`
	`3`	`+-`
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	`1`	`+## Definition`
	`2`	`+The ability of an object to store charge.`
	`3`	`+$$Capacitance = \cfrac{Charge}{Voltage}$$`