Skip to content

Commit f6f06b8

Browse files
committed
70046: added week 2 lectures
1 parent 767a57f commit f6f06b8

29 files changed

+936
-0
lines changed
Loading

70046 - EEE - Advanced Digital Systems Design/6T_SRAM.svg

Lines changed: 748 additions & 0 deletions
Loading
Loading
Lines changed: 18 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,18 @@
1+
## Layers
2+
![[abstraction_layers.png]]
3+
*Image is from ADSD slides*
4+
5+
| Level | Description | Objective |
6+
| ---- | ---- | ---- |
7+
| System | | Defines partitions and the interfaces used to connect between them (e.g. communications, inter-processor, memory hierarchy) |
8+
| Algorithm | | Model the behaviour of the system. Simulations to ensure system implements an algorithm correctly. |
9+
| [[Register Transfer Level\|RTL]]/[[Hardware Description Languages\|HDL]] | The functional level. (using SystemVerilog, VHDL, etc) | Defines the [[Microarchitecture]] , control and data paths, timing/clocking. |
10+
| Gate | Connecting logic gates. | Define the behaviour of components/building blocks used in the [[Register Transfer Level\|RTL]] |
11+
| Circuit | | Implementing logic gate behaviour with transitors. |
12+
| Device | | Optimisation of [[Transistor]] parameters |
13+
## Design Process
14+
Top down and bottom up design strategies (refining & decomposing down to primitive components, versus building up from primitives).
15+
- Usually a mixed strategy of mostly top-down with some bottom-up is used.
16+
## Synthesis
17+
$$\text{Specification} \to \text{System-Level Model} \to \text{algorithm} \to \text{RTL Model} \to \text{RTL Optimisation} \to \text{generic gate-level model} \to \text{Mapped gate-level model} \to \text{Place and Route}$$
18+
- Mapped Gate-Level Model depends on the underlying technology (e.g. [[FPGA]] vs [[ASIC]])
Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,3 @@
1+
- Ripple carry
2+
- lookahead
3+
-
Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,3 @@
1+
## Definition
2+
The ability of an object to store charge.
3+
$$Capacitance = \cfrac{Charge}{Voltage}$$
Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,6 @@
1+
## Definition
2+
A hardware key-value store. User provides a key, and in return gets the location/value (potentially multiple).
3+
4+
## Examples
5+
### TLB
6+
Many [[Translation Lookaside Buffer|TLBs]] are implemented using [[Content Addressable Memory]] (provide page virtual address, get cached physical address).
Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,4 @@
1+
## Definition
2+
> *Double Data Rate Synchronous Dynamic Random Access Memory*
3+
4+
A [[Synchronous Dynamic RAM]] where control actions occur on both the falling, and rising edge to double the rate at which accesses can be issued.
Lines changed: 25 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,25 @@
1+
## Definition
2+
Uses a capacitor to store a charge to represent the bit held.
3+
- Much smaller than a [[Static Memory#6T SRAM]]
4+
- leakage from the capacitor requires periodic refresh
5+
- Includes [[Synchronous Dynamic RAM]] and [[DDR SDRAM]]
6+
Much like in [[RAM Organisation]] cells are organised by row and column.
7+
## 1T DRAM
8+
![[1T_Dynamic_Cell.png]]
9+
## Access
10+
| Pin | Name | Purpose |
11+
| ---- | ---- | ---- |
12+
| `A` | Address | contain address of cell |
13+
| `D` | Data | Combined input/output (bidirectional).<br><br>Input when `WE_L` asserted (low) and `OE_L` disasserted (high).<br><br>Output when `WE_L` disasserted (High) and `OE_L` asserted (Low) |
14+
| `RAS_L` | Row Address Low | Latch in row on low (edge-sensitive) |
15+
| `CAS_L` | Column Address Low | Latch in column on low (edge-sensitive) |
16+
| `WE_L` | Write Enable Low | enable writes (edge-sensitive) |
17+
| `OE_L` | Output Enable Low | enable output (`D` is input also) (edge-sensitive) |
18+
### Latency
19+
| Property | Description | 4Mbit DRAM Performance with $t_{RAC} = 60 \ ns$ |
20+
| ---- | ---- | ---- |
21+
| $t_{RAC}$ | Minimum time from `RAS` fall to valid data output. (Set row, wait for output) | $60 \ ns$ |
22+
| $t_{RC}$ | Minimum time from one row access to the next. | $110 \ ns$ |
23+
| $t_{CAC}$ | Minimum time from `CAS` fall to valid data output. (Set column, wait for output) | $15 \ ns$ |
24+
| $t_{PC}$ | Minimum time from one column access to the next. | $35 \ ns$ |
25+
- Accessing different rows is more expensive than different columns. So more same-row access is better.
Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,4 @@
1+
## Definition
2+
A queue based buffer.
3+
- Used for IO devices, input (e.g. network interface, smooth bursts from unsynchronised IO pins to constant rate synchronised CPU), and output (e.g. generate audio in bursts, but output at constant rate by DAC)
4+
- Can be implemented as a circular queue.

0 commit comments

Comments
 (0)