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cpu-o3: refactor lsu related code
+ add LdPipeStages and StPipeStages parameters + remove redundant storePipeSx code + fix dumpLoadStorePipe Change-Id: Ie8cb7865c3a53265520f11f016dd467c25a3e2a5
1 parent 6c8f802 commit 28ab3ea

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+35
-55
lines changed

4 files changed

+35
-55
lines changed

‎src/cpu/o3/BaseO3CPU.py

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -171,6 +171,9 @@ def support_take_over(cls):
171171
LQEntries = Param.Unsigned(80, "Number of load queue entries")
172172
SQEntries = Param.Unsigned(64, "Number of store queue entries")
173173

174+
LdPipeStages = Param.Unsigned(4, "Number of load pipeline stages")
175+
StPipeStages = Param.Unsigned(5, "Number of store pipeline stages")
176+
174177
SbufferEntries = Param.Unsigned(16, "Number of store buffer entries")
175178
SbufferEvictThreshold = Param.Unsigned(7, "store buffer eviction threshold")
176179
storeBufferInactiveThreshold = Param.Unsigned(800, "store buffer writeback timeout threshold")

‎src/cpu/o3/lsq.cc

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -138,7 +138,8 @@ LSQ::LSQ(CPU *cpu_ptr, IEW *iew_ptr, const BaseO3CPUParams &params)
138138
// TODO: Parameterize the load/store pipeline stages
139139
for (ThreadID tid = 0; tid < numThreads; tid++) {
140140
thread.emplace_back(maxLQEntries, maxSQEntries, params.SbufferEntries,
141-
params.SbufferEvictThreshold, params.storeBufferInactiveThreshold, 4, 5);
141+
params.SbufferEvictThreshold, params.storeBufferInactiveThreshold,
142+
params.LdPipeStages, params.StPipeStages);
142143
thread[tid].init(cpu, iew_ptr, params, this, tid);
143144
thread[tid].setDcachePort(&dcachePort);
144145
}

‎src/cpu/o3/lsq_unit.cc

Lines changed: 29 additions & 51 deletions
Original file line numberDiff line numberDiff line change
@@ -1457,36 +1457,14 @@ LSQUnit::storePipeS1(const DynInstPtr &inst, std::bitset<LdStFlagNum> &flag)
14571457
}
14581458

14591459
Fault
1460-
LSQUnit::storePipeS2(const DynInstPtr &inst, std::bitset<LdStFlagNum> &flag)
1460+
LSQUnit::emptyStorePipeSx(const DynInstPtr &inst, std::bitset<LdStFlagNum> &flag, uint64_t stage)
14611461
{
1462+
// empty store pipe stage, Does not perform any operation
14621463
Fault fault = inst->getFault();
14631464
assert(!inst->isSquashed());
14641465

1465-
DPRINTF(LSQUnit, "StorePipeS2: Executing store PC %s [sn:%lli] flags: %s\n",
1466-
inst->pcState(), inst->seqNum, getLdStFlagStr(flag));
1467-
return fault;
1468-
}
1469-
1470-
Fault
1471-
LSQUnit::storePipeS3(const DynInstPtr &inst, std::bitset<LdStFlagNum> &flag)
1472-
{
1473-
Fault fault = inst->getFault();
1474-
assert(!inst->isSquashed());
1475-
1476-
DPRINTF(LSQUnit, "StorePipeS3: Executing store PC %s [sn:%lli] flags: %s\n",
1477-
inst->pcState(), inst->seqNum, getLdStFlagStr(flag));
1478-
return fault;
1479-
}
1480-
1481-
Fault
1482-
LSQUnit::storePipeS4(const DynInstPtr &inst, std::bitset<LdStFlagNum> &flag)
1483-
{
1484-
Fault fault = inst->getFault();
1485-
assert(!inst->isSquashed());
1486-
1487-
DPRINTF(LSQUnit, "StorePipeS4: Executing store PC %s [sn:%lli] flags: %s\n",
1488-
inst->pcState(), inst->seqNum, getLdStFlagStr(flag));
1489-
1466+
DPRINTF(LSQUnit, "StorePipeS%d: Executing store PC %s [sn:%lli] flags: %s\n",
1467+
stage, inst->pcState(), inst->seqNum, getLdStFlagStr(flag));
14901468
return fault;
14911469
}
14921470

@@ -1521,13 +1499,9 @@ LSQUnit::executeStorePipeSx()
15211499
iewStage->SquashCheckAfterExe(inst);
15221500
break;
15231501
case 2:
1524-
fault = storePipeS2(inst, flag);
1525-
break;
15261502
case 3:
1527-
fault = storePipeS3(inst, flag);
1528-
break;
15291503
case 4:
1530-
fault = storePipeS4(inst, flag);
1504+
fault = emptyStorePipeSx(inst, flag, i);
15311505
break;
15321506
default:
15331507
panic("unsupported storepipe length");
@@ -2551,33 +2525,37 @@ LSQUnit::recvRetry()
25512525
void
25522526
LSQUnit::dumpLoadPipe()
25532527
{
2554-
DPRINTF(LSQUnit, "Dumping LoadPipe:\n");
2555-
for (int i = 0; i < loadPipeSx.size(); i++) {
2556-
DPRINTF(LSQUnit, "Load S%d:, size: %d\n", i, loadPipeSx[i]->size);
2557-
for (int j = 0; j < loadPipeSx[i]->size; j++) {
2558-
DPRINTF(LSQUnit, " PC: %s, [tid:%i] [sn:%lli] flags: %s\n",
2559-
loadPipeSx[i]->insts[j]->pcState(),
2560-
loadPipeSx[i]->insts[j]->threadNumber,
2561-
loadPipeSx[i]->insts[j]->seqNum,
2562-
getLdStFlagStr(loadPipeSx[i]->flags[j])
2563-
);
2528+
if (GEM5_UNLIKELY(::gem5::debug::LSQUnit)) {
2529+
DPRINTFN("Dumping LoadPipe:\n");
2530+
for (int i = 0; i < loadPipeSx.size(); i++) {
2531+
DPRINTFN("Load S%d:, size: %d\n", i, loadPipeSx[i]->size);
2532+
for (int j = 0; j < loadPipeSx[i]->size; j++) {
2533+
DPRINTFN(" PC: %s, [tid:%i] [sn:%lli] flags: %s\n",
2534+
loadPipeSx[i]->insts[j]->pcState(),
2535+
loadPipeSx[i]->insts[j]->threadNumber,
2536+
loadPipeSx[i]->insts[j]->seqNum,
2537+
getLdStFlagStr(loadPipeSx[i]->flags[j])
2538+
);
2539+
}
25642540
}
25652541
}
25662542
}
25672543

25682544
void
25692545
LSQUnit::dumpStorePipe()
25702546
{
2571-
DPRINTF(LSQUnit, "Dumping StorePipe:\n");
2572-
for (int i = 0; i < storePipeSx.size(); i++) {
2573-
DPRINTF(LSQUnit, "Store S%d:, size: %d\n", i, storePipeSx[i]->size);
2574-
for (int j = 0; j < storePipeSx[i]->size; j++) {
2575-
DPRINTF(LSQUnit, " PC: %s, [tid:%i] [sn:%lli] flags: %s\n",
2576-
storePipeSx[i]->insts[j]->pcState(),
2577-
storePipeSx[i]->insts[j]->threadNumber,
2578-
storePipeSx[i]->insts[j]->seqNum,
2579-
getLdStFlagStr(storePipeSx[i]->flags[j])
2580-
);
2547+
if (GEM5_UNLIKELY(::gem5::debug::LSQUnit)) {
2548+
DPRINTFN("Dumping StorePipe:\n");
2549+
for (int i = 0; i < storePipeSx.size(); i++) {
2550+
DPRINTFN("Store S%d:, size: %d\n", i, storePipeSx[i]->size);
2551+
for (int j = 0; j < storePipeSx[i]->size; j++) {
2552+
DPRINTFN(" PC: %s, [tid:%i] [sn:%lli] flags: %s\n",
2553+
storePipeSx[i]->insts[j]->pcState(),
2554+
storePipeSx[i]->insts[j]->threadNumber,
2555+
storePipeSx[i]->insts[j]->seqNum,
2556+
getLdStFlagStr(storePipeSx[i]->flags[j])
2557+
);
2558+
}
25812559
}
25822560
}
25832561
}

‎src/cpu/o3/lsq_unit.hh

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -552,9 +552,7 @@ class LSQUnit
552552

553553
Fault storePipeS0(const DynInstPtr &inst, std::bitset<LdStFlagNum> &flag);
554554
Fault storePipeS1(const DynInstPtr &inst, std::bitset<LdStFlagNum> &flag);
555-
Fault storePipeS2(const DynInstPtr &inst, std::bitset<LdStFlagNum> &flag);
556-
Fault storePipeS3(const DynInstPtr &inst, std::bitset<LdStFlagNum> &flag);
557-
Fault storePipeS4(const DynInstPtr &inst, std::bitset<LdStFlagNum> &flag);
555+
Fault emptyStorePipeSx(const DynInstPtr &inst, std::bitset<LdStFlagNum> &flag, uint64_t stage);
558556

559557
/** Wrap function. */
560558
void executePipeSx();

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