Activity
add reg_enable for vreduction in case of discontinuous input
add reg_enable for vreduction in case of discontinuous input
make vuop pipelined with yunsuan
make vuop pipelined with yunsuan
Valid/ready for Exu/Store and Load. Exu/Store are one more pipeline t…
Valid/ready for Exu/Store and Load. Exu/Store are one more pipeline t…
add vrgather and vfreduction_sum_max
add vrgather and vfreduction_sum_max
feat: add fuOpType of Zvksed instructions
feat: add fuOpType of Zvksed instructions
add funct6 convert to opcode inside yunsuan
add funct6 convert to opcode inside yunsuan
Bundle of ExuInput/output change
Bundle of ExuInput/output change
before add vfa under sew = 01 fp16
before add vfa under sew = 01 fp16
add more fp type (fake) into uop.ctrl
add more fp type (fake) into uop.ctrl