src/test/vsrc/vcs/DifftestEndpoint.sv

@@ -213,7 +213,7 @@ always @(posedge clock) begin
 end
 
 /*
- * exit signal check
+ * difftest exit signal check
  */
 always @(posedge clock) begin
     // exit signal: all 1's for normal exit; others are error
@@ -256,7 +256,7 @@ always @(posedge clock) begin
   end
 end
 
-/* sim result control */
+/* simulation step control */
 `ifdef CONFIG_DIFFTEST_DEFERRED_RESULT
 wire [7:0] simv_result;
 DeferredControl deferred(
@@ -269,24 +269,49 @@ DeferredControl deferred(
 );
 `else
 
-`ifndef PALLADIUM
+`ifdef PALLADIUM
+/*
+ * CAUTION: The DPI-C execution order was not handled correctly,
+ * for PALLADIUM platform it is possible that the difftest step
+ * was executed **BEFORE** all dffftest state update finished.
+ * (fortunately, it was not happened yet)
+ */
+always @(posedge clock) begin
+  if (reset || simv_result == `SIMV_DONE) begin
+    simv_result <= 8'b0;
+  end
+  else begin
+    if (n_cycles && |difftest_step) begin
+      simv_result <= simv_nstep(difftest_step);
+    end
+  end
+end
+`else
+/*
+ * for other platform, we introduce a delayed difftest step
+ * mechanism to make sure all difftest state was updated properly
+ * before `simv_step()` called.
+ */
 reg [7:0] simv_result;
 reg [7:0] _res;
 event simv_step_event;
+// check difftest_step
 always @(posedge clock) begin
   if (!reset) begin
     if (n_cycles && |difftest_step) begin
-      /* trigger sim step event */
+      // delay a little before trigger the simv step event
       #0.1 -> simv_step_event;
     end
   end
 end
+// all difftest state was updated, step difftest by `simv_nstep()`
 always @(simv_step_event or posedge reset) begin
   if (reset)
     _res <= 8'b0;
   else
     _res <= simv_nstep(difftest_step);
 end
+// update to `simv_result` at next cycle
 always @(posedge clock) begin
   if (reset || simv_result == `SIMV_DONE) begin
     simv_result <= 8'b0;
@@ -295,22 +320,11 @@ always @(posedge clock) begin
     simv_result <= _res;
   end
 end
-`else
-always @(posedge clock) begin
-  if (reset) begin
-    simv_result <= 8'b0;
-  end
-  else begin
-    if (n_cycles && |difftest_step) begin
-      simv_result <= simv_nstep(difftest_step);
-    end
-  end
-end
-`endif // !PALLADIUM
+`endif // PALLADIUM
 `endif // CONFIG_DIFFTEST_DEFERRED_RESULT
 
 /*
- * sim result check
+ * difftest result check
  */
 always @(posedge clock) begin
   if (!reset) begin