File tree Expand file tree Collapse file tree 1 file changed +7
-8
lines changed Expand file tree Collapse file tree 1 file changed +7
-8
lines changed Original file line number Diff line number Diff line change @@ -42,19 +42,18 @@ read_verilog -defer {{ name }}
42
42
read_verilog -defer -sv {{ name }}
43
43
{% elif attr .hdl == "vhdl" %}
44
44
{% if loop .first %}
45
- # VHDL Generics
46
- {% set generics = "-gFREQ=125000000 -gSECS=1" %}
47
- ghdl {{ gflags }} {{ generics }} {{ top }}
45
+ {% if params %} # VHDL Generics
46
+ ghdl {{ gflags }}{% for key , value in params .items () %} -g{{ key }}={{ value }}{% endfor %} {{ top }}
47
+ {% else %}
48
+ ghdl {{ gflags }} {{ top }}
48
49
{% endif %}
49
50
{% endif %}
50
- {% endfor %}
51
51
{% endif %}
52
-
53
- {#
54
- {% if params %}# Verilog Parameters
52
+ {% if loop .last and attr .hdl in ["vlog" , "slog" ] and params %} # Verilog Parameters
55
53
chparam{% for key , value in params .items () %} -set {{ key }} {{ value }}{% endfor %}
56
54
{% endif %}
57
- #}
55
+ {% endfor %}
56
+ {% endif %}
58
57
59
58
# Top-level specification and Syntesis
60
59
{% if family in ['ice40' , 'ecp5' ] %}
You can’t perform that action at this time.
0 commit comments