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dr-orlovskydr-orlovsky
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vm: support updated AluVM debugger
1 parent d1f9704 commit b973bc4

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6 files changed

+100
-46
lines changed

6 files changed

+100
-46
lines changed

‎Cargo.lock

+14-14
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‎Cargo.toml

+1
Original file line numberDiff line numberDiff line change
@@ -65,3 +65,4 @@ bp-consensus = { git = "https://github.com/BP-WG/bp-core", branch = "v0.11" }
6565
bp-dbc = { git = "https://github.com/BP-WG/bp-core", branch = "v0.11" }
6666
bp-seals = { git = "https://github.com/BP-WG/bp-core", branch = "v0.11" }
6767
bp-core = { git = "https://github.com/BP-WG/bp-core", branch = "v0.11" }
68+
aluvm = { git = "https://github.com/AluVM/rust-aluvm", branch = "v0.11" }

‎src/vm/isa.rs

+18-2
Original file line numberDiff line numberDiff line change
@@ -20,13 +20,13 @@
2020
// See the License for the specific language governing permissions and
2121
// limitations under the License.
2222

23-
use std::collections::BTreeSet;
23+
use std::collections::{BTreeSet, HashSet};
2424
use std::ops::RangeInclusive;
2525

2626
use aluvm::isa;
2727
use aluvm::isa::{Bytecode, BytecodeError, ExecStep, InstructionSet};
2828
use aluvm::library::{CodeEofError, LibSite, Read, Write};
29-
use aluvm::reg::CoreRegs;
29+
use aluvm::reg::{CoreRegs, Reg};
3030

3131
use super::{ContractOp, TimechainOp};
3232
use crate::validation::OpInfo;
@@ -52,6 +52,22 @@ impl InstructionSet for RgbIsa {
5252
bset! {"RGB"}
5353
}
5454

55+
fn src_regs(&self) -> HashSet<Reg> {
56+
match self {
57+
RgbIsa::Contract(op) => op.src_regs(),
58+
RgbIsa::Timechain(op) => op.src_regs(),
59+
RgbIsa::Fail(_) => set![],
60+
}
61+
}
62+
63+
fn dst_regs(&self) -> HashSet<Reg> {
64+
match self {
65+
RgbIsa::Contract(op) => op.dst_regs(),
66+
RgbIsa::Timechain(op) => op.dst_regs(),
67+
RgbIsa::Fail(_) => set![],
68+
}
69+
}
70+
5571
fn exec(&self, regs: &mut CoreRegs, site: LibSite, context: &Self::Context<'_>) -> ExecStep {
5672
match self {
5773
RgbIsa::Contract(op) => op.exec(regs, site, context),

‎src/vm/op_contract.rs

+60-27
Original file line numberDiff line numberDiff line change
@@ -22,13 +22,13 @@
2222

2323
#![allow(clippy::unusual_byte_groupings)]
2424

25-
use std::collections::BTreeSet;
25+
use std::collections::{BTreeSet, HashSet};
2626
use std::ops::RangeInclusive;
2727

2828
use aluvm::isa::{Bytecode, BytecodeError, ExecStep, InstructionSet};
2929
use aluvm::library::{CodeEofError, LibSite, Read, Write};
30-
use aluvm::reg::{CoreRegs, Reg16, RegA, RegS};
31-
use amplify::num::u4;
30+
use aluvm::reg::{CoreRegs, Reg, Reg32, RegA, RegS};
31+
use amplify::num::{u3, u4};
3232
use amplify::Wrapper;
3333
use commit_verify::CommitVerify;
3434
use strict_encoding::StrictSerialize;
@@ -45,22 +45,22 @@ pub enum ContractOp {
4545
/// Counts number of inputs (previous state entries) of the provided type
4646
/// and puts the number to the destination `a16` register.
4747
#[display("cnp {0},a16{1}")]
48-
CnP(AssignmentType, Reg16),
48+
CnP(AssignmentType, Reg32),
4949

5050
/// Counts number of outputs (owned state entries) of the provided type
5151
/// and puts the number to the destination `a16` register.
5252
#[display("cns {0},a16{1}")]
53-
CnS(AssignmentType, Reg16),
53+
CnS(AssignmentType, Reg32),
5454

5555
/// Counts number of global state items of the provided type affected by the
5656
/// current operation and puts the number to the destination `a8` register.
5757
#[display("cng {0},a8{1}")]
58-
CnG(GlobalStateType, Reg16),
58+
CnG(GlobalStateType, Reg32),
5959

6060
/// Counts number of global state items of the provided type in the contract
6161
/// state and puts the number to the destination `a16` register.
6262
#[display("cnc {0},a16{1}")]
63-
CnC(AssignmentType, Reg16),
63+
CnC(AssignmentType, Reg32),
6464

6565
/// Loads input (previous) state with type id from the first argument and
6666
/// index from the second argument into a register provided in the third
@@ -93,7 +93,7 @@ pub enum ContractOp {
9393
///
9494
/// If the state at the index is concealed, sets destination to `None`.
9595
#[display("ldf {0},{1},a64{2}")]
96-
LdF(AssignmentType, u16, Reg16),
96+
LdF(AssignmentType, u16, Reg32),
9797

9898
/// Loads global state from the current operation with type id from the
9999
/// first argument and index from the second argument into a register
@@ -158,6 +158,35 @@ impl InstructionSet for ContractOp {
158158

159159
fn isa_ids() -> BTreeSet<&'static str> { none!() }
160160

161+
fn src_regs(&self) -> HashSet<Reg> { set![] }
162+
163+
fn dst_regs(&self) -> HashSet<Reg> {
164+
match self {
165+
ContractOp::CnP(_, reg) |
166+
ContractOp::CnS(_, reg) |
167+
ContractOp::CnG(_, reg) |
168+
ContractOp::CnC(_, reg) => {
169+
set![Reg::A(RegA::A16, *reg)]
170+
}
171+
ContractOp::LdF(_, _, reg) => {
172+
set![Reg::A(RegA::A64, *reg)]
173+
}
174+
ContractOp::LdP(_, _, reg) |
175+
ContractOp::LdS(_, _, reg) |
176+
ContractOp::LdG(_, _, reg) |
177+
ContractOp::LdC(_, _, reg) |
178+
ContractOp::LdM(reg) => {
179+
set![Reg::S(*reg)]
180+
}
181+
182+
ContractOp::PcVs(_) | ContractOp::PcCs(_, _) => {
183+
set![]
184+
}
185+
186+
ContractOp::Fail(_) => set![],
187+
}
188+
}
189+
161190
fn exec(&self, regs: &mut CoreRegs, _site: LibSite, context: &Self::Context<'_>) -> ExecStep {
162191
macro_rules! fail {
163192
() => {{
@@ -204,17 +233,21 @@ impl InstructionSet for ContractOp {
204233

205234
match self {
206235
ContractOp::CnP(state_type, reg) => {
207-
regs.set(RegA::A16, *reg, context.prev_state.get(state_type).map(|a| a.len_u16()));
236+
regs.set_n(
237+
RegA::A16,
238+
*reg,
239+
context.prev_state.get(state_type).map(|a| a.len_u16()),
240+
);
208241
}
209242
ContractOp::CnS(state_type, reg) => {
210-
regs.set(
243+
regs.set_n(
211244
RegA::A16,
212245
*reg,
213246
context.owned_state.get(*state_type).map(|a| a.len_u16()),
214247
);
215248
}
216249
ContractOp::CnG(state_type, reg) => {
217-
regs.set(RegA::A16, *reg, context.global.get(state_type).map(|a| a.len_u16()));
250+
regs.set_n(RegA::A16, *reg, context.global.get(state_type).map(|a| a.len_u16()));
218251
}
219252
ContractOp::CnC(_state_type, _reg) => {
220253
// TODO: implement global contract state
@@ -256,7 +289,7 @@ impl InstructionSet for ContractOp {
256289
else {
257290
fail!()
258291
};
259-
regs.set(RegA::A64, *reg, state.map(|s| s.value.as_u64()));
292+
regs.set_n(RegA::A64, *reg, state.map(|s| s.value.as_u64()));
260293
}
261294
ContractOp::LdG(state_type, index, reg) => {
262295
let Some(state) = context
@@ -376,23 +409,23 @@ impl Bytecode for ContractOp {
376409
match self {
377410
ContractOp::CnP(state_type, reg) => {
378411
writer.write_u16(*state_type)?;
379-
writer.write_u4(reg)?;
380-
writer.write_u4(u4::ZERO)?;
412+
writer.write_u5(reg)?;
413+
writer.write_u3(u3::ZERO)?;
381414
}
382415
ContractOp::CnS(state_type, reg) => {
383416
writer.write_u16(*state_type)?;
384-
writer.write_u4(reg)?;
385-
writer.write_u4(u4::ZERO)?;
417+
writer.write_u5(reg)?;
418+
writer.write_u3(u3::ZERO)?;
386419
}
387420
ContractOp::CnG(state_type, reg) => {
388421
writer.write_u16(*state_type)?;
389-
writer.write_u4(reg)?;
390-
writer.write_u4(u4::ZERO)?;
422+
writer.write_u5(reg)?;
423+
writer.write_u3(u3::ZERO)?;
391424
}
392425
ContractOp::CnC(state_type, reg) => {
393426
writer.write_u16(*state_type)?;
394-
writer.write_u4(reg)?;
395-
writer.write_u4(u4::ZERO)?;
427+
writer.write_u5(reg)?;
428+
writer.write_u3(u3::ZERO)?;
396429
}
397430
ContractOp::LdP(state_type, index, reg) => {
398431
writer.write_u16(*state_type)?;
@@ -409,8 +442,8 @@ impl Bytecode for ContractOp {
409442
ContractOp::LdF(state_type, index, reg) => {
410443
writer.write_u16(*state_type)?;
411444
writer.write_u16(*index)?;
412-
writer.write_u4(reg)?;
413-
writer.write_u4(u4::ZERO)?;
445+
writer.write_u5(reg)?;
446+
writer.write_u3(u3::ZERO)?;
414447
}
415448
ContractOp::LdG(state_type, index, reg) => {
416449
writer.write_u16(*state_type)?;
@@ -447,22 +480,22 @@ impl Bytecode for ContractOp {
447480
{
448481
Ok(match reader.read_u8()? {
449482
INSTR_CNP => {
450-
let i = Self::CnP(reader.read_u16()?.into(), reader.read_u4()?.into());
483+
let i = Self::CnP(reader.read_u16()?.into(), reader.read_u5()?.into());
451484
reader.read_u4()?; // Discard garbage bits
452485
i
453486
}
454487
INSTR_CNS => {
455-
let i = Self::CnS(reader.read_u16()?.into(), reader.read_u4()?.into());
488+
let i = Self::CnS(reader.read_u16()?.into(), reader.read_u5()?.into());
456489
reader.read_u4()?; // Discard garbage bits
457490
i
458491
}
459492
INSTR_CNG => {
460-
let i = Self::CnG(reader.read_u16()?.into(), reader.read_u4()?.into());
493+
let i = Self::CnG(reader.read_u16()?.into(), reader.read_u5()?.into());
461494
reader.read_u4()?; // Discard garbage bits
462495
i
463496
}
464497
INSTR_CNC => {
465-
let i = Self::CnC(reader.read_u16()?.into(), reader.read_u4()?.into());
498+
let i = Self::CnC(reader.read_u16()?.into(), reader.read_u5()?.into());
466499
reader.read_u4()?; // Discard garbage bits
467500
i
468501
}
@@ -489,7 +522,7 @@ impl Bytecode for ContractOp {
489522
let i = Self::LdF(
490523
reader.read_u16()?.into(),
491524
reader.read_u16()?,
492-
reader.read_u4()?.into(),
525+
reader.read_u5()?.into(),
493526
);
494527
reader.read_u4()?; // Discard garbage bits
495528
i

‎src/vm/op_timechain.rs

+6-2
Original file line numberDiff line numberDiff line change
@@ -20,12 +20,12 @@
2020
// See the License for the specific language governing permissions and
2121
// limitations under the License.
2222

23-
use std::collections::BTreeSet;
23+
use std::collections::{BTreeSet, HashSet};
2424
use std::ops::RangeInclusive;
2525

2626
use aluvm::isa::{Bytecode, BytecodeError, ExecStep, InstructionSet};
2727
use aluvm::library::{CodeEofError, LibSite, Read, Write};
28-
use aluvm::reg::CoreRegs;
28+
use aluvm::reg::{CoreRegs, Reg};
2929

3030
use crate::vm::opcodes::{INSTR_TIMECHAIN_FROM, INSTR_TIMECHAIN_TO};
3131

@@ -43,6 +43,10 @@ impl InstructionSet for TimechainOp {
4343

4444
fn isa_ids() -> BTreeSet<&'static str> { none!() }
4545

46+
fn src_regs(&self) -> HashSet<Reg> { set![] }
47+
48+
fn dst_regs(&self) -> HashSet<Reg> { set![] }
49+
4650
fn exec(&self, regs: &mut CoreRegs, _site: LibSite, _context: &Self::Context<'_>) -> ExecStep {
4751
match self {
4852
TimechainOp::Fail => {

‎src/vm/runtime.rs

+1-1
Original file line numberDiff line numberDiff line change
@@ -86,7 +86,7 @@ impl<'script> AluRuntime<'script> {
8686
let mut vm = Vm::<Instr<RgbIsa>>::new();
8787

8888
for ((reg, idx), val) in &regs.nums {
89-
vm.registers.set(*reg, *idx, *val);
89+
vm.registers.set_n(*reg, *idx, *val);
9090
}
9191
for (reg, val) in &regs.data {
9292
vm.registers.set_s(

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