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leading_zeros: fix leading zeros for u32
1 parent 7d8e532 commit 0df98d7

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+19
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crates/rustc_codegen_spirv/src/builder/intrinsics.rs

+19-10
Original file line numberDiff line numberDiff line change
@@ -512,18 +512,27 @@ impl Builder<'_, '_> {
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let bool = SpirvType::Bool.def(self.span(), self);
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let u32 = SpirvType::Integer(32, false).def(self.span(), self);
514514

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let gl_op = if trailing {
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// rust is always unsigned
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GLOp::FindILsb
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} else {
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GLOp::FindUMsb
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};
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let glsl = self.ext_inst.borrow_mut().import_glsl(self);
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let find_xsb = |arg| {
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self.emit()
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.ext_inst(u32, None, glsl, gl_op as u32, [Operand::IdRef(arg)])
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.unwrap()
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if trailing {
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self.emit()
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.ext_inst(u32, None, glsl, GLOp::FindILsb as u32, [Operand::IdRef(
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arg,
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)])
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.unwrap()
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} else {
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// rust is always unsigned, so FindUMsb
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let bla = self
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.emit()
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.ext_inst(u32, None, glsl, GLOp::FindUMsb as u32, [Operand::IdRef(
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arg,
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)])
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.unwrap();
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// the glsl op returns the Msb bit, not the amount of leading zeros of this u32
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// leading zeros = 31 - Msb bit
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let u32_31 = self.constant_u32(self.span(), 31).def(self);
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self.emit().i_sub(u32, None, u32_31, bla).unwrap()
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}
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};
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let converted = match bits {

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