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stm32f0xx_hal_rcc_ex.h
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/**
******************************************************************************
* @file stm32f0xx_hal_rcc_ex.h
* @author MCD Application Team
* @brief Header file of RCC HAL Extension module.
******************************************************************************
* @attention
*
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F0xx_HAL_RCC_EX_H
#define __STM32F0xx_HAL_RCC_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f0xx_hal_def.h"
/** @addtogroup STM32F0xx_HAL_Driver
* @{
*/
/** @addtogroup RCC
* @{
*/
/** @addtogroup RCC_Private_Macros
* @{
*/
#if defined(RCC_HSI48_SUPPORT)
#define IS_RCC_OSCILLATORTYPE(OSCILLATOR) (((OSCILLATOR) == RCC_OSCILLATORTYPE_NONE) || \
(((OSCILLATOR) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \
(((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \
(((OSCILLATOR) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \
(((OSCILLATOR) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) || \
(((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI14) == RCC_OSCILLATORTYPE_HSI14) || \
(((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48))
#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \
((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \
((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK) || \
((SOURCE) == RCC_SYSCLKSOURCE_HSI48))
#define IS_RCC_SYSCLKSOURCE_STATUS(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI) || \
((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSE) || \
((SOURCE) == RCC_SYSCLKSOURCE_STATUS_PLLCLK) || \
((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI48))
#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \
((SOURCE) == RCC_PLLSOURCE_HSI48) || \
((SOURCE) == RCC_PLLSOURCE_HSE))
#define IS_RCC_HSI48(HSI48) (((HSI48) == RCC_HSI48_OFF) || ((HSI48) == RCC_HSI48_ON))
#else
#define IS_RCC_OSCILLATORTYPE(OSCILLATOR) (((OSCILLATOR) == RCC_OSCILLATORTYPE_NONE) || \
(((OSCILLATOR) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \
(((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \
(((OSCILLATOR) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \
(((OSCILLATOR) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) || \
(((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI14) == RCC_OSCILLATORTYPE_HSI14))
#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \
((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \
((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK))
#define IS_RCC_SYSCLKSOURCE_STATUS(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI) || \
((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSE) || \
((SOURCE) == RCC_SYSCLKSOURCE_STATUS_PLLCLK))
#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \
((SOURCE) == RCC_PLLSOURCE_HSE))
#endif /* RCC_HSI48_SUPPORT */
#if defined(RCC_CFGR_PLLNODIV) && !defined(RCC_CFGR_MCO_HSI48)
#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_NOCLOCK) || \
((SOURCE) == RCC_MCO1SOURCE_LSI) || \
((SOURCE) == RCC_MCO1SOURCE_LSE) || \
((SOURCE) == RCC_MCO1SOURCE_SYSCLK) || \
((SOURCE) == RCC_MCO1SOURCE_HSI) || \
((SOURCE) == RCC_MCO1SOURCE_HSE) || \
((SOURCE) == RCC_MCO1SOURCE_PLLCLK) || \
((SOURCE) == RCC_MCO1SOURCE_PLLCLK_DIV2) || \
((SOURCE) == RCC_MCO1SOURCE_HSI14))
#elif defined(RCC_CFGR_PLLNODIV) && defined(RCC_CFGR_MCO_HSI48)
#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_NOCLOCK) || \
((SOURCE) == RCC_MCO1SOURCE_LSI) || \
((SOURCE) == RCC_MCO1SOURCE_LSE) || \
((SOURCE) == RCC_MCO1SOURCE_SYSCLK) || \
((SOURCE) == RCC_MCO1SOURCE_HSI) || \
((SOURCE) == RCC_MCO1SOURCE_HSE) || \
((SOURCE) == RCC_MCO1SOURCE_PLLCLK) || \
((SOURCE) == RCC_MCO1SOURCE_PLLCLK_DIV2) || \
((SOURCE) == RCC_MCO1SOURCE_HSI14) || \
((SOURCE) == RCC_MCO1SOURCE_HSI48))
#elif !defined(RCC_CFGR_PLLNODIV) && !defined(RCC_CFGR_MCO_HSI48)
#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_NOCLOCK) || \
((SOURCE) == RCC_MCO1SOURCE_LSI) || \
((SOURCE) == RCC_MCO1SOURCE_LSE) || \
((SOURCE) == RCC_MCO1SOURCE_SYSCLK) || \
((SOURCE) == RCC_MCO1SOURCE_HSI) || \
((SOURCE) == RCC_MCO1SOURCE_HSE) || \
((SOURCE) == RCC_MCO1SOURCE_PLLCLK_DIV2) || \
((SOURCE) == RCC_MCO1SOURCE_HSI14))
#endif /* RCC_CFGR_PLLNODIV && !RCC_CFGR_MCO_HSI48 */
/**
* @}
*/
/** @addtogroup RCC_Exported_Constants
* @{
*/
#if defined(RCC_HSI48_SUPPORT)
/** @addtogroup RCC_PLL_Clock_Source
* @{
*/
#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV
#define RCC_PLLSOURCE_HSI48 RCC_CFGR_PLLSRC_HSI48_PREDIV
/**
* @}
*/
/** @addtogroup RCC_Interrupt
* @{
*/
#define RCC_IT_HSI48 RCC_CIR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */
/**
* @}
*/
/** @addtogroup RCC_Flag
* @{
*/
#define RCC_FLAG_HSI48RDY ((uint8_t)((CR2_REG_INDEX << 5U) | RCC_CR2_HSI48RDY_BitNumber))
/**
* @}
*/
/** @addtogroup RCC_System_Clock_Source
* @{
*/
#define RCC_SYSCLKSOURCE_HSI48 RCC_CFGR_SW_HSI48
/**
* @}
*/
/** @addtogroup RCC_System_Clock_Source_Status
* @{
*/
#define RCC_SYSCLKSOURCE_STATUS_HSI48 RCC_CFGR_SWS_HSI48
/**
* @}
*/
#else
/** @addtogroup RCC_PLL_Clock_Source
* @{
*/
#if defined(STM32F070xB) || defined(STM32F070x6) || defined(STM32F030xC)
#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV
#else
#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_DIV2
#endif
/**
* @}
*/
#endif /* RCC_HSI48_SUPPORT */
/** @addtogroup RCC_MCO_Clock_Source
* @{
*/
#if defined(RCC_CFGR_PLLNODIV)
#define RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCO_PLL | RCC_CFGR_PLLNODIV)
#endif /* RCC_CFGR_PLLNODIV */
#if defined(RCC_CFGR_MCO_HSI48)
#define RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCO_HSI48
#endif /* SRCC_CFGR_MCO_HSI48 */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/** @addtogroup RCCEx
* @{
*/
/* Private Constants -------------------------------------------------------------*/
#if defined(CRS)
/** @addtogroup RCCEx_Private_Constants
* @{
*/
/* CRS IT Error Mask */
#define RCC_CRS_IT_ERROR_MASK ((uint32_t)(RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS))
/* CRS Flag Error Mask */
#define RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS))
/**
* @}
*/
#endif /* CRS */
/* Private macro -------------------------------------------------------------*/
/** @defgroup RCCEx_Private_Macros RCCEx Private Macros
* @{
*/
#if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx)\
|| defined(STM32F030xC)
#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | \
RCC_PERIPHCLK_RTC))
#endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F038xx ||
STM32F030xC */
#if defined(STM32F070x6) || defined(STM32F070xB)
#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | \
RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USB))
#endif /* STM32F070x6 || STM32F070xB */
#if defined(STM32F042x6) || defined(STM32F048xx)
#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | \
RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_RTC | \
RCC_PERIPHCLK_USB))
#endif /* STM32F042x6 || STM32F048xx */
#if defined(STM32F051x8) || defined(STM32F058xx)
#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | \
RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_RTC))
#endif /* STM32F051x8 || STM32F058xx */
#if defined(STM32F071xB)
#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | \
RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_CEC | \
RCC_PERIPHCLK_RTC))
#endif /* STM32F071xB */
#if defined(STM32F072xB) || defined(STM32F078xx)
#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | \
RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_CEC | \
RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USB))
#endif /* STM32F072xB || STM32F078xx */
#if defined(STM32F091xC) || defined(STM32F098xx)
#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | \
RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_CEC | \
RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USART3 ))
#endif /* STM32F091xC || STM32F098xx */
#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx)
#define IS_RCC_USBCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSOURCE_HSI48) || \
((SOURCE) == RCC_USBCLKSOURCE_PLL))
#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx */
#if defined(STM32F070x6) || defined(STM32F070xB)
#define IS_RCC_USBCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSOURCE_NONE) || \
((SOURCE) == RCC_USBCLKSOURCE_PLL))
#endif /* STM32F070x6 || STM32F070xB */
#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
|| defined(STM32F091xC) || defined(STM32F098xx)
#define IS_RCC_USART2CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART2CLKSOURCE_PCLK1) || \
((SOURCE) == RCC_USART2CLKSOURCE_SYSCLK) || \
((SOURCE) == RCC_USART2CLKSOURCE_LSE) || \
((SOURCE) == RCC_USART2CLKSOURCE_HSI))
#endif /* STM32F071xB || STM32F072xB || STM32F078xx || */
/* STM32F091xC || STM32F098xx */
#if defined(STM32F091xC) || defined(STM32F098xx)
#define IS_RCC_USART3CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART3CLKSOURCE_PCLK1) || \
((SOURCE) == RCC_USART3CLKSOURCE_SYSCLK) || \
((SOURCE) == RCC_USART3CLKSOURCE_LSE) || \
((SOURCE) == RCC_USART3CLKSOURCE_HSI))
#endif /* STM32F091xC || STM32F098xx */
#if defined(STM32F042x6) || defined(STM32F048xx)\
|| defined(STM32F051x8) || defined(STM32F058xx)\
|| defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
|| defined(STM32F091xC) || defined(STM32F098xx)
#define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) || \
((SOURCE) == RCC_CECCLKSOURCE_LSE))
#endif /* STM32F042x6 || STM32F048xx || */
/* STM32F051x8 || STM32F058xx || */
/* STM32F071xB || STM32F072xB || STM32F078xx || */
/* STM32F091xC || STM32F098xx */
#if defined(RCC_CFGR_MCOPRE)
#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || \
((DIV) == RCC_MCODIV_4) || ((DIV) == RCC_MCODIV_8) || \
((DIV) == RCC_MCODIV_16) || ((DIV) == RCC_MCODIV_32) || \
((DIV) == RCC_MCODIV_64) || ((DIV) == RCC_MCODIV_128))
#else
#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1))
#endif /* RCC_CFGR_MCOPRE */
#define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_LOW) || \
((__DRIVE__) == RCC_LSEDRIVE_MEDIUMLOW) || \
((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) || \
((__DRIVE__) == RCC_LSEDRIVE_HIGH))
#if defined(CRS)
#define IS_RCC_CRS_SYNC_SOURCE(_SOURCE_) (((_SOURCE_) == RCC_CRS_SYNC_SOURCE_GPIO) || \
((_SOURCE_) == RCC_CRS_SYNC_SOURCE_LSE) || \
((_SOURCE_) == RCC_CRS_SYNC_SOURCE_USB))
#define IS_RCC_CRS_SYNC_DIV(_DIV_) (((_DIV_) == RCC_CRS_SYNC_DIV1) || ((_DIV_) == RCC_CRS_SYNC_DIV2) || \
((_DIV_) == RCC_CRS_SYNC_DIV4) || ((_DIV_) == RCC_CRS_SYNC_DIV8) || \
((_DIV_) == RCC_CRS_SYNC_DIV16) || ((_DIV_) == RCC_CRS_SYNC_DIV32) || \
((_DIV_) == RCC_CRS_SYNC_DIV64) || ((_DIV_) == RCC_CRS_SYNC_DIV128))
#define IS_RCC_CRS_SYNC_POLARITY(_POLARITY_) (((_POLARITY_) == RCC_CRS_SYNC_POLARITY_RISING) || \
((_POLARITY_) == RCC_CRS_SYNC_POLARITY_FALLING))
#define IS_RCC_CRS_RELOADVALUE(_VALUE_) (((_VALUE_) <= 0xFFFFU))
#define IS_RCC_CRS_ERRORLIMIT(_VALUE_) (((_VALUE_) <= 0xFFU))
#define IS_RCC_CRS_HSI48CALIBRATION(_VALUE_) (((_VALUE_) <= 0x3FU))
#define IS_RCC_CRS_FREQERRORDIR(_DIR_) (((_DIR_) == RCC_CRS_FREQERRORDIR_UP) || \
((_DIR_) == RCC_CRS_FREQERRORDIR_DOWN))
#endif /* CRS */
/**
* @}
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup RCCEx_Exported_Types RCCEx Exported Types
* @{
*/
/**
* @brief RCC extended clocks structure definition
*/
#if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx)\
|| defined(STM32F030xC)
typedef struct
{
uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
This parameter can be a value of @ref RCC_RTC_Clock_Source */
uint32_t Usart1ClockSelection; /*!< USART1 clock source
This parameter can be a value of @ref RCC_USART1_Clock_Source */
uint32_t I2c1ClockSelection; /*!< I2C1 clock source
This parameter can be a value of @ref RCC_I2C1_Clock_Source */
}RCC_PeriphCLKInitTypeDef;
#endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F038xx ||
STM32F030xC */
#if defined(STM32F070x6) || defined(STM32F070xB)
typedef struct
{
uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
This parameter can be a value of @ref RCC_RTC_Clock_Source */
uint32_t Usart1ClockSelection; /*!< USART1 clock source
This parameter can be a value of @ref RCC_USART1_Clock_Source */
uint32_t I2c1ClockSelection; /*!< I2C1 clock source
This parameter can be a value of @ref RCC_I2C1_Clock_Source */
uint32_t UsbClockSelection; /*!< USB clock source
This parameter can be a value of @ref RCCEx_USB_Clock_Source */
}RCC_PeriphCLKInitTypeDef;
#endif /* STM32F070x6 || STM32F070xB */
#if defined(STM32F042x6) || defined(STM32F048xx)
typedef struct
{
uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
This parameter can be a value of @ref RCC_RTC_Clock_Source */
uint32_t Usart1ClockSelection; /*!< USART1 clock source
This parameter can be a value of @ref RCC_USART1_Clock_Source */
uint32_t I2c1ClockSelection; /*!< I2C1 clock source
This parameter can be a value of @ref RCC_I2C1_Clock_Source */
uint32_t CecClockSelection; /*!< HDMI CEC clock source
This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
uint32_t UsbClockSelection; /*!< USB clock source
This parameter can be a value of @ref RCCEx_USB_Clock_Source */
}RCC_PeriphCLKInitTypeDef;
#endif /* STM32F042x6 || STM32F048xx */
#if defined(STM32F051x8) || defined(STM32F058xx)
typedef struct
{
uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
This parameter can be a value of @ref RCC_RTC_Clock_Source */
uint32_t Usart1ClockSelection; /*!< USART1 clock source
This parameter can be a value of @ref RCC_USART1_Clock_Source */
uint32_t I2c1ClockSelection; /*!< I2C1 clock source
This parameter can be a value of @ref RCC_I2C1_Clock_Source */
uint32_t CecClockSelection; /*!< HDMI CEC clock source
This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
}RCC_PeriphCLKInitTypeDef;
#endif /* STM32F051x8 || STM32F058xx */
#if defined(STM32F071xB)
typedef struct
{
uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
This parameter can be a value of @ref RCC_RTC_Clock_Source */
uint32_t Usart1ClockSelection; /*!< USART1 clock source
This parameter can be a value of @ref RCC_USART1_Clock_Source */
uint32_t Usart2ClockSelection; /*!< USART2 clock source
This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
uint32_t I2c1ClockSelection; /*!< I2C1 clock source
This parameter can be a value of @ref RCC_I2C1_Clock_Source */
uint32_t CecClockSelection; /*!< HDMI CEC clock source
This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
}RCC_PeriphCLKInitTypeDef;
#endif /* STM32F071xB */
#if defined(STM32F072xB) || defined(STM32F078xx)
typedef struct
{
uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
This parameter can be a value of @ref RCC_RTC_Clock_Source */
uint32_t Usart1ClockSelection; /*!< USART1 clock source
This parameter can be a value of @ref RCC_USART1_Clock_Source */
uint32_t Usart2ClockSelection; /*!< USART2 clock source
This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
uint32_t I2c1ClockSelection; /*!< I2C1 clock source
This parameter can be a value of @ref RCC_I2C1_Clock_Source */
uint32_t CecClockSelection; /*!< HDMI CEC clock source
This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
uint32_t UsbClockSelection; /*!< USB clock source
This parameter can be a value of @ref RCCEx_USB_Clock_Source */
}RCC_PeriphCLKInitTypeDef;
#endif /* STM32F072xB || STM32F078xx */
#if defined(STM32F091xC) || defined(STM32F098xx)
typedef struct
{
uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
This parameter can be a value of @ref RCC_RTC_Clock_Source */
uint32_t Usart1ClockSelection; /*!< USART1 clock source
This parameter can be a value of @ref RCC_USART1_Clock_Source */
uint32_t Usart2ClockSelection; /*!< USART2 clock source
This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
uint32_t Usart3ClockSelection; /*!< USART3 clock source
This parameter can be a value of @ref RCCEx_USART3_Clock_Source */
uint32_t I2c1ClockSelection; /*!< I2C1 clock source
This parameter can be a value of @ref RCC_I2C1_Clock_Source */
uint32_t CecClockSelection; /*!< HDMI CEC clock source
This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
}RCC_PeriphCLKInitTypeDef;
#endif /* STM32F091xC || STM32F098xx */
#if defined(CRS)
/**
* @brief RCC_CRS Init structure definition
*/
typedef struct
{
uint32_t Prescaler; /*!< Specifies the division factor of the SYNC signal.
This parameter can be a value of @ref RCCEx_CRS_SynchroDivider */
uint32_t Source; /*!< Specifies the SYNC signal source.
This parameter can be a value of @ref RCCEx_CRS_SynchroSource */
uint32_t Polarity; /*!< Specifies the input polarity for the SYNC signal source.
This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */
uint32_t ReloadValue; /*!< Specifies the value to be loaded in the frequency error counter with each SYNC event.
It can be calculated in using macro @ref __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__)
This parameter must be a number between 0 and 0xFFFF or a value of @ref RCCEx_CRS_ReloadValueDefault .*/
uint32_t ErrorLimitValue; /*!< Specifies the value to be used to evaluate the captured frequency error value.
This parameter must be a number between 0 and 0xFF or a value of @ref RCCEx_CRS_ErrorLimitDefault */
uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator.
This parameter must be a number between 0 and 0x3F or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */
}RCC_CRSInitTypeDef;
/**
* @brief RCC_CRS Synchronization structure definition
*/
typedef struct
{
uint32_t ReloadValue; /*!< Specifies the value loaded in the Counter reload value.
This parameter must be a number between 0 and 0xFFFFU */
uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming.
This parameter must be a number between 0 and 0x3FU */
uint32_t FreqErrorCapture; /*!< Specifies the value loaded in the .FECAP, the frequency error counter
value latched in the time of the last SYNC event.
This parameter must be a number between 0 and 0xFFFFU */
uint32_t FreqErrorDirection; /*!< Specifies the value loaded in the .FEDIR, the counting direction of the
frequency error counter latched in the time of the last SYNC event.
It shows whether the actual frequency is below or above the target.
This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/
}RCC_CRSSynchroInfoTypeDef;
#endif /* CRS */
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
* @{
*/
/** @defgroup RCCEx_Periph_Clock_Selection RCCEx Periph Clock Selection
* @{
*/
#if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx)\
|| defined(STM32F030xC)
#define RCC_PERIPHCLK_USART1 (0x00000001U)
#define RCC_PERIPHCLK_I2C1 (0x00000020U)
#define RCC_PERIPHCLK_RTC (0x00010000U)
#endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F038xx ||
STM32F030xC */
#if defined(STM32F070x6) || defined(STM32F070xB)
#define RCC_PERIPHCLK_USART1 (0x00000001U)
#define RCC_PERIPHCLK_I2C1 (0x00000020U)
#define RCC_PERIPHCLK_RTC (0x00010000U)
#define RCC_PERIPHCLK_USB (0x00020000U)
#endif /* STM32F070x6 || STM32F070xB */
#if defined(STM32F042x6) || defined(STM32F048xx)
#define RCC_PERIPHCLK_USART1 (0x00000001U)
#define RCC_PERIPHCLK_I2C1 (0x00000020U)
#define RCC_PERIPHCLK_CEC (0x00000400U)
#define RCC_PERIPHCLK_RTC (0x00010000U)
#define RCC_PERIPHCLK_USB (0x00020000U)
#endif /* STM32F042x6 || STM32F048xx */
#if defined(STM32F051x8) || defined(STM32F058xx)
#define RCC_PERIPHCLK_USART1 (0x00000001U)
#define RCC_PERIPHCLK_I2C1 (0x00000020U)
#define RCC_PERIPHCLK_CEC (0x00000400U)
#define RCC_PERIPHCLK_RTC (0x00010000U)
#endif /* STM32F051x8 || STM32F058xx */
#if defined(STM32F071xB)
#define RCC_PERIPHCLK_USART1 (0x00000001U)
#define RCC_PERIPHCLK_USART2 (0x00000002U)
#define RCC_PERIPHCLK_I2C1 (0x00000020U)
#define RCC_PERIPHCLK_CEC (0x00000400U)
#define RCC_PERIPHCLK_RTC (0x00010000U)
#endif /* STM32F071xB */
#if defined(STM32F072xB) || defined(STM32F078xx)
#define RCC_PERIPHCLK_USART1 (0x00000001U)
#define RCC_PERIPHCLK_USART2 (0x00000002U)
#define RCC_PERIPHCLK_I2C1 (0x00000020U)
#define RCC_PERIPHCLK_CEC (0x00000400U)
#define RCC_PERIPHCLK_RTC (0x00010000U)
#define RCC_PERIPHCLK_USB (0x00020000U)
#endif /* STM32F072xB || STM32F078xx */
#if defined(STM32F091xC) || defined(STM32F098xx)
#define RCC_PERIPHCLK_USART1 (0x00000001U)
#define RCC_PERIPHCLK_USART2 (0x00000002U)
#define RCC_PERIPHCLK_I2C1 (0x00000020U)
#define RCC_PERIPHCLK_CEC (0x00000400U)
#define RCC_PERIPHCLK_RTC (0x00010000U)
#define RCC_PERIPHCLK_USART3 (0x00040000U)
#endif /* STM32F091xC || STM32F098xx */
/**
* @}
*/
#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx)
/** @defgroup RCCEx_USB_Clock_Source RCCEx USB Clock Source
* @{
*/
#define RCC_USBCLKSOURCE_HSI48 RCC_CFGR3_USBSW_HSI48 /*!< HSI48 clock selected as USB clock source */
#define RCC_USBCLKSOURCE_PLL RCC_CFGR3_USBSW_PLLCLK /*!< PLL clock (PLLCLK) selected as USB clock */
/**
* @}
*/
#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx */
#if defined(STM32F070x6) || defined(STM32F070xB)
/** @defgroup RCCEx_USB_Clock_Source RCCEx USB Clock Source
* @{
*/
#define RCC_USBCLKSOURCE_NONE (0x00000000U) /*!< USB clock disabled */
#define RCC_USBCLKSOURCE_PLL RCC_CFGR3_USBSW_PLLCLK /*!< PLL clock (PLLCLK) selected as USB clock */
/**
* @}
*/
#endif /* STM32F070x6 || STM32F070xB */
#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
|| defined(STM32F091xC) || defined(STM32F098xx)
/** @defgroup RCCEx_USART2_Clock_Source RCCEx USART2 Clock Source
* @{
*/
#define RCC_USART2CLKSOURCE_PCLK1 RCC_CFGR3_USART2SW_PCLK
#define RCC_USART2CLKSOURCE_SYSCLK RCC_CFGR3_USART2SW_SYSCLK
#define RCC_USART2CLKSOURCE_LSE RCC_CFGR3_USART2SW_LSE
#define RCC_USART2CLKSOURCE_HSI RCC_CFGR3_USART2SW_HSI
/**
* @}
*/
#endif /* STM32F071xB || STM32F072xB || STM32F078xx || */
/* STM32F091xC || STM32F098xx */
#if defined(STM32F091xC) || defined(STM32F098xx)
/** @defgroup RCCEx_USART3_Clock_Source RCCEx USART3 Clock Source
* @{
*/
#define RCC_USART3CLKSOURCE_PCLK1 RCC_CFGR3_USART3SW_PCLK
#define RCC_USART3CLKSOURCE_SYSCLK RCC_CFGR3_USART3SW_SYSCLK
#define RCC_USART3CLKSOURCE_LSE RCC_CFGR3_USART3SW_LSE
#define RCC_USART3CLKSOURCE_HSI RCC_CFGR3_USART3SW_HSI
/**
* @}
*/
#endif /* STM32F091xC || STM32F098xx */
#if defined(STM32F042x6) || defined(STM32F048xx)\
|| defined(STM32F051x8) || defined(STM32F058xx)\
|| defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
|| defined(STM32F091xC) || defined(STM32F098xx)
/** @defgroup RCCEx_CEC_Clock_Source RCCEx CEC Clock Source
* @{
*/
#define RCC_CECCLKSOURCE_HSI RCC_CFGR3_CECSW_HSI_DIV244
#define RCC_CECCLKSOURCE_LSE RCC_CFGR3_CECSW_LSE
/**
* @}
*/
#endif /* STM32F042x6 || STM32F048xx || */
/* STM32F051x8 || STM32F058xx || */
/* STM32F071xB || STM32F072xB || STM32F078xx || */
/* STM32F091xC || STM32F098xx */
/** @defgroup RCCEx_MCOx_Clock_Prescaler RCCEx MCOx Clock Prescaler
* @{
*/
#if defined(RCC_CFGR_MCOPRE)
#define RCC_MCODIV_1 (0x00000000U)
#define RCC_MCODIV_2 (0x10000000U)
#define RCC_MCODIV_4 (0x20000000U)
#define RCC_MCODIV_8 (0x30000000U)
#define RCC_MCODIV_16 (0x40000000U)
#define RCC_MCODIV_32 (0x50000000U)
#define RCC_MCODIV_64 (0x60000000U)
#define RCC_MCODIV_128 (0x70000000U)
#else
#define RCC_MCODIV_1 (0x00000000U)
#endif /* RCC_CFGR_MCOPRE */
/**
* @}
*/
/** @defgroup RCCEx_LSEDrive_Configuration RCC LSE Drive Configuration
* @{
*/
#define RCC_LSEDRIVE_LOW (0x00000000U) /*!< Xtal mode lower driving capability */
#define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_1 /*!< Xtal mode medium low driving capability */
#define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_0 /*!< Xtal mode medium high driving capability */
#define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< Xtal mode higher driving capability */
/**
* @}
*/
#if defined(CRS)
/** @defgroup RCCEx_CRS_Status RCCEx CRS Status
* @{
*/
#define RCC_CRS_NONE (0x00000000U)
#define RCC_CRS_TIMEOUT (0x00000001U)
#define RCC_CRS_SYNCOK (0x00000002U)
#define RCC_CRS_SYNCWARN (0x00000004U)
#define RCC_CRS_SYNCERR (0x00000008U)
#define RCC_CRS_SYNCMISS (0x00000010U)
#define RCC_CRS_TRIMOVF (0x00000020U)
/**
* @}
*/
/** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS Synchronization Source
* @{
*/
#define RCC_CRS_SYNC_SOURCE_GPIO (0x00000000U) /*!< Synchro Signal source GPIO */
#define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */
#define RCC_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/
/**
* @}
*/
/** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS Synchronization Divider
* @{
*/
#define RCC_CRS_SYNC_DIV1 (0x00000000U) /*!< Synchro Signal not divided (default) */
#define RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */
#define RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */
#define RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */
#define RCC_CRS_SYNC_DIV16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */
#define RCC_CRS_SYNC_DIV32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */
#define RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */
#define RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */
/**
* @}
*/
/** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS Synchronization Polarity
* @{
*/
#define RCC_CRS_SYNC_POLARITY_RISING (0x00000000U) /*!< Synchro Active on rising edge (default) */
#define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */
/**
* @}
*/
/** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS Default Reload Value
* @{
*/
#define RCC_CRS_RELOADVALUE_DEFAULT (0x0000BB7FU) /*!< The reset value of the RELOAD field corresponds
to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */
/**
* @}
*/
/** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS Default Error Limit Value
* @{
*/
#define RCC_CRS_ERRORLIMIT_DEFAULT (0x00000022U) /*!< Default Frequency error limit */
/**
* @}
*/
/** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS Default HSI48 Calibration vakye
* @{
*/
#define RCC_CRS_HSI48CALIBRATION_DEFAULT (0x00000020U) /*!< The default value is 32, which corresponds to the middle of the trimming interval.
The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value
corresponds to a higher output frequency */
/**
* @}
*/
/** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS Frequency Error Direction
* @{
*/
#define RCC_CRS_FREQERRORDIR_UP (0x00000000U) /*!< Upcounting direction, the actual frequency is above the target */
#define RCC_CRS_FREQERRORDIR_DOWN ((uint32_t)CRS_ISR_FEDIR) /*!< Downcounting direction, the actual frequency is below the target */
/**
* @}
*/
/** @defgroup RCCEx_CRS_Interrupt_Sources RCCEx CRS Interrupt Sources
* @{
*/
#define RCC_CRS_IT_SYNCOK CRS_CR_SYNCOKIE /*!< SYNC event OK */
#define RCC_CRS_IT_SYNCWARN CRS_CR_SYNCWARNIE /*!< SYNC warning */
#define RCC_CRS_IT_ERR CRS_CR_ERRIE /*!< Error */
#define RCC_CRS_IT_ESYNC CRS_CR_ESYNCIE /*!< Expected SYNC */
#define RCC_CRS_IT_SYNCERR CRS_CR_ERRIE /*!< SYNC error */
#define RCC_CRS_IT_SYNCMISS CRS_CR_ERRIE /*!< SYNC missed */
#define RCC_CRS_IT_TRIMOVF CRS_CR_ERRIE /*!< Trimming overflow or underflow */
/**
* @}
*/
/** @defgroup RCCEx_CRS_Flags RCCEx CRS Flags
* @{
*/
#define RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF /*!< SYNC event OK flag */
#define RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF /*!< SYNC warning flag */
#define RCC_CRS_FLAG_ERR CRS_ISR_ERRF /*!< Error flag */
#define RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF /*!< Expected SYNC flag */
#define RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR /*!< SYNC error */
#define RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS /*!< SYNC missed*/
#define RCC_CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF /*!< Trimming overflow or underflow */
/**
* @}
*/
#endif /* CRS */
/**
* @}
*/
/* Exported macros ------------------------------------------------------------*/
/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
* @{
*/
/** @defgroup RCCEx_Peripheral_Clock_Enable_Disable RCCEx_Peripheral_Clock_Enable_Disable
* @brief Enables or disables the AHB1 peripheral clock.
* @note After reset, the peripheral clock (used for registers read/write access)
* is disabled and the application software has to enable this clock before
* using it.
* @{
*/
#if defined(GPIOD)
#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\
UNUSED(tmpreg); \
} while(0U)
#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIODEN))
#endif /* GPIOD */
#if defined(GPIOE)
#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\
UNUSED(tmpreg); \
} while(0U)
#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN))
#endif /* GPIOE */
#if defined(STM32F042x6) || defined(STM32F048xx)\
|| defined(STM32F051x8) || defined(STM32F058xx)\
|| defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
|| defined(STM32F091xC) || defined(STM32F098xx)
#define __HAL_RCC_TSC_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN);\
UNUSED(tmpreg); \
} while(0U)
#define __HAL_RCC_TSC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_TSCEN))
#endif /* STM32F042x6 || STM32F048xx || */
/* STM32F051x8 || STM32F058xx || */
/* STM32F071xB || STM32F072xB || STM32F078xx || */