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jeanlegojeanlego
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Merge pull request verilog-to-routing#702 from CAS-Atlantic/var_declare_bug
ODIN II: I/O port bug fix
2 parents fdea733 + 1235dce commit 849c235

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2 files changed

+51
-47
lines changed

2 files changed

+51
-47
lines changed

‎ODIN_II/SRC/netlist_create_from_ast.cpp

Lines changed: 35 additions & 35 deletions
Original file line numberDiff line numberDiff line change
@@ -2456,15 +2456,15 @@ void connect_module_instantiation_and_alias(short PASS, ast_node_t* module_insta
24562456
{
24572457
int port_size = 0;
24582458
// VAR_DECLARE_LIST(child[i])->VAR_DECLARE_PORT(child[0])->VAR_DECLARE_input-or-output(child[0])
2459-
ast_node_t *module_var_node = module_list->children[i]->children[0];
2459+
ast_node_t *module_var_node = module_list->children[i];
24602460
// MODULE_CONNECT_LIST(child[i])->MODULE_CONNECT(child[1]) // child[0] is for aliasing
24612461
ast_node_t *module_instance_var_node = module_instance_list->children[i]->children[1];
24622462

24632463
if (
24642464
// skip inputs on pass 1
2465-
((PASS == INSTANTIATE_DRIVERS) && (module_list->children[i]->children[0]->types.variable.is_input))
2465+
((PASS == INSTANTIATE_DRIVERS) && (module_list->children[i]->types.variable.is_input))
24662466
// skip outputs on pass 2
2467-
|| ((PASS == ALIAS_INPUTS) && (module_list->children[i]->children[0]->types.variable.is_output))
2467+
|| ((PASS == ALIAS_INPUTS) && (module_list->children[i]->types.variable.is_output))
24682468
)
24692469
{
24702470
continue;
@@ -2520,7 +2520,7 @@ void connect_module_instantiation_and_alias(short PASS, ast_node_t* module_insta
25202520
for (j = 0; j < port_size; j++)
25212521
{
25222522

2523-
if (module_list->children[i]->children[0]->types.variable.is_input)
2523+
if (module_var_node->types.variable.is_input)
25242524
{
25252525
/* IF - this spot in the module list is an input, then we need to find it in the
25262526
* string cache (as its old name), check if the new_name (the instantiation name)
@@ -2539,7 +2539,7 @@ void connect_module_instantiation_and_alias(short PASS, ast_node_t* module_insta
25392539
vtr::free(name_of_module_instance_of_input);
25402540

25412541
/* make the new string for the alias name - has to be a identifier in the instantiated modules old names */
2542-
name_of_module_instance_of_input = get_name_of_var_declare_at_bit(module_list->children[i]->children[0], j);
2542+
name_of_module_instance_of_input = get_name_of_var_declare_at_bit(module_var_node, j);
25432543
alias_name = make_full_ref_name(instance_name_prefix,
25442544
module_instance->children[0]->types.identifier,
25452545
module_instance->children[1]->children[0]->types.identifier,
@@ -2556,7 +2556,7 @@ void connect_module_instantiation_and_alias(short PASS, ast_node_t* module_insta
25562556
full_name = make_full_ref_name(instance_name_prefix, NULL, NULL, name_of_module_instance_of_input, -1);
25572557
vtr::free(name_of_module_instance_of_input);
25582558

2559-
name_of_module_instance_of_input = get_name_of_var_declare_at_bit(module_list->children[i]->children[0], 0);
2559+
name_of_module_instance_of_input = get_name_of_var_declare_at_bit(module_var_node, 0);
25602560
alias_name = make_full_ref_name(instance_name_prefix,
25612561
module_instance->children[0]->types.identifier,
25622562
module_instance->children[1]->children[0]->types.identifier,
@@ -2636,21 +2636,21 @@ void connect_module_instantiation_and_alias(short PASS, ast_node_t* module_insta
26362636
if (module_instance_list->children[i]->children[0] != NULL)
26372637
{
26382638
if (strcmp(module_instance_list->children[i]->children[0]->types.identifier,
2639-
module_list->children[i]->children[0]->children[0]->types.identifier) != 0
2639+
module_var_node->children[0]->types.identifier) != 0
26402640
)
26412641
{
2642-
error_message(NETLIST_ERROR, module_list->children[i]->children[0]->line_number, module_list->children[i]->children[0]->file_number,
2642+
error_message(NETLIST_ERROR, module_var_node->line_number, module_var_node->file_number,
26432643
"This module entry does not match up correctly (%s != %s). Odin expects the order of ports to be the same\n",
26442644
module_instance_list->children[i]->children[0]->types.identifier,
2645-
module_list->children[i]->children[0]->children[0]->types.identifier
2645+
module_var_node->children[0]->types.identifier
26462646
);
26472647
}
26482648
}
26492649

26502650
vtr::free(full_name);
26512651
vtr::free(alias_name);
26522652
}
2653-
else if (module_list->children[i]->children[0]->types.variable.is_output)
2653+
else if (module_var_node->types.variable.is_output)
26542654
{
26552655
/* ELSE IF - this is an output pin from the module. We need to alias this output
26562656
* pin with it's calling name here so that everyone can see it at this level */
@@ -2667,7 +2667,7 @@ void connect_module_instantiation_and_alias(short PASS, ast_node_t* module_insta
26672667
full_name = make_full_ref_name(instance_name_prefix, NULL, NULL, name_of_module_instance_of_input, -1);
26682668
vtr::free(name_of_module_instance_of_input);
26692669

2670-
name_of_module_instance_of_input = get_name_of_var_declare_at_bit(module_list->children[i]->children[0], j);
2670+
name_of_module_instance_of_input = get_name_of_var_declare_at_bit(module_var_node, j);
26712671
alias_name = make_full_ref_name(instance_name_prefix,
26722672
module_instance->children[0]->types.identifier,
26732673
module_instance->children[1]->children[0]->types.identifier, name_of_module_instance_of_input, -1);
@@ -2681,7 +2681,7 @@ void connect_module_instantiation_and_alias(short PASS, ast_node_t* module_insta
26812681
full_name = make_full_ref_name(instance_name_prefix, NULL, NULL, name_of_module_instance_of_input, -1);
26822682
vtr::free(name_of_module_instance_of_input);
26832683

2684-
name_of_module_instance_of_input = get_name_of_var_declare_at_bit(module_list->children[i]->children[0], 0);
2684+
name_of_module_instance_of_input = get_name_of_var_declare_at_bit(module_var_node, 0);
26852685
alias_name = make_full_ref_name(instance_name_prefix,
26862686
module_instance->children[0]->types.identifier,
26872687
module_instance->children[1]->children[0]->types.identifier, name_of_module_instance_of_input, -1);
@@ -2692,7 +2692,7 @@ void connect_module_instantiation_and_alias(short PASS, ast_node_t* module_insta
26922692
/* check if the instantiation pin exists. */
26932693
if ((sc_spot_output = sc_lookup_string(output_nets_sc, alias_name)) == -1)
26942694
{
2695-
error_message(NETLIST_ERROR, module_list->children[i]->children[0]->line_number, module_list->children[i]->children[0]->file_number,
2695+
error_message(NETLIST_ERROR, module_var_node->line_number, module_var_node->file_number,
26962696
"This output (%s) must exist...must be an error\n", alias_name);
26972697
}
26982698

@@ -2726,12 +2726,12 @@ void connect_module_instantiation_and_alias(short PASS, ast_node_t* module_insta
27262726
/* IF the designer users port names then make sure they line up */
27272727
if (module_instance_list->children[i]->children[0] != NULL)
27282728
{
2729-
if (strcmp(module_instance_list->children[i]->children[0]->types.identifier, module_list->children[i]->children[0]->children[0]->types.identifier) != 0)
2729+
if (strcmp(module_instance_list->children[i]->children[0]->types.identifier, module_var_node->children[0]->types.identifier) != 0)
27302730
{
2731-
error_message(NETLIST_ERROR, module_list->children[i]->children[0]->line_number, module_list->children[i]->children[0]->file_number,
2731+
error_message(NETLIST_ERROR, module_var_node->line_number, module_var_node->file_number,
27322732
"This module entry does not match up correctly (%s != %s). Odin expects the order of ports to be the same\n",
27332733
module_instance_list->children[i]->children[0]->types.identifier,
2734-
module_list->children[i]->children[0]->children[0]->types.identifier
2734+
module_var_node->children[0]->types.identifier
27352735
);
27362736
}
27372737
}
@@ -2785,16 +2785,16 @@ signal_list_t *connect_function_instantiation_and_alias(short PASS, ast_node_t*
27852785

27862786
int port_size = 0;
27872787
// VAR_DECLARE_LIST(child[i])->VAR_DECLARE_PORT(child[0])->VAR_DECLARE_input-or-output(child[0])
2788-
ast_node_t *module_var_node = module_list->children[i]->children[0];
2789-
ast_node_t *module_instance_var_node = NULL;
2788+
ast_node_t *module_var_node = module_list->children[i];
2789+
ast_node_t *module_instance_var_node = NULL;
27902790

27912791
if(i > 0) module_instance_var_node = module_instance_list->children[i]->children[1];
27922792

27932793
if (
27942794
// skip inputs on pass 1
2795-
((PASS == INSTANTIATE_DRIVERS) && (module_list->children[i]->children[0]->types.variable.is_input))
2795+
((PASS == INSTANTIATE_DRIVERS) && (module_var_node->types.variable.is_input))
27962796
// skip outputs on pass 2
2797-
|| ((PASS == ALIAS_INPUTS) && (module_list->children[i]->children[0]->types.variable.is_output))
2797+
|| ((PASS == ALIAS_INPUTS) && (module_var_node->types.variable.is_output))
27982798
)
27992799
{
28002800
continue;
@@ -2853,7 +2853,7 @@ signal_list_t *connect_function_instantiation_and_alias(short PASS, ast_node_t*
28532853
}
28542854
for (j = 0; j < port_size; j++)
28552855
{
2856-
if (i > 0 && module_list->children[i]->children[0]->types.variable.is_input)
2856+
if (i > 0 && module_var_node->types.variable.is_input)
28572857
{
28582858
/* IF - this spot in the module list is an input, then we need to find it in the
28592859
* string cache (as its old name), check if the new_name (the instantiation name)
@@ -2872,7 +2872,7 @@ signal_list_t *connect_function_instantiation_and_alias(short PASS, ast_node_t*
28722872
vtr::free(name_of_module_instance_of_input);
28732873

28742874
/* make the new string for the alias name - has to be a identifier in the instantiated modules old names */
2875-
name_of_module_instance_of_input = get_name_of_var_declare_at_bit(module_list->children[i]->children[0], j);
2875+
name_of_module_instance_of_input = get_name_of_var_declare_at_bit(module_var_node, j);
28762876
alias_name = make_full_ref_name(instance_name_prefix,
28772877
module_instance->children[0]->types.identifier,
28782878
module_instance->children[1]->children[0]->types.identifier,
@@ -2891,7 +2891,7 @@ signal_list_t *connect_function_instantiation_and_alias(short PASS, ast_node_t*
28912891
full_name = make_full_ref_name(instance_name_prefix, NULL, NULL, name_of_module_instance_of_input, -1);
28922892
vtr::free(name_of_module_instance_of_input);
28932893

2894-
name_of_module_instance_of_input = get_name_of_var_declare_at_bit(module_list->children[i]->children[0], 0);
2894+
name_of_module_instance_of_input = get_name_of_var_declare_at_bit(module_var_node, 0);
28952895
alias_name = make_full_ref_name(instance_name_prefix,
28962896
module_instance->children[0]->types.identifier,
28972897
module_instance->children[1]->children[0]->types.identifier,
@@ -2974,21 +2974,21 @@ signal_list_t *connect_function_instantiation_and_alias(short PASS, ast_node_t*
29742974
if (module_instance_list->children[i]->children[0] != NULL)
29752975
{
29762976
if (strcmp(module_instance_list->children[i]->children[0]->types.identifier,
2977-
module_list->children[i]->children[0]->children[0]->types.identifier) != 0
2977+
module_var_node->children[0]->types.identifier) != 0
29782978
)
29792979
{
2980-
error_message(NETLIST_ERROR, module_list->children[i]->children[0]->line_number, module_list->children[i]->children[0]->file_number,
2980+
error_message(NETLIST_ERROR, module_var_node->line_number, module_var_node->file_number,
29812981
"This module entry does not match up correctly (%s != %s). Odin expects the order of ports to be the same\n",
29822982
module_instance_list->children[i]->children[0]->types.identifier,
2983-
module_list->children[i]->children[0]->children[0]->types.identifier
2983+
module_var_node->children[0]->types.identifier
29842984
);
29852985
}
29862986
}
29872987

29882988
vtr::free(full_name);
29892989
vtr::free(alias_name);
29902990
}
2991-
else if (i == 0 && module_list->children[i]->children[0]->types.variable.is_output)
2991+
else if (i == 0 && module_var_node->types.variable.is_output)
29922992
{
29932993
/* ELSE IF - this is an output pin from the module. We need to alias this output
29942994
* pin with it's calling name here so that everyone can see it at this level */
@@ -3009,7 +3009,7 @@ signal_list_t *connect_function_instantiation_and_alias(short PASS, ast_node_t*
30093009
//vtr::free(name_of_module_instance_of_input);
30103010

30113011

3012-
name_of_module_instance_of_input = get_name_of_var_declare_at_bit(module_list->children[i]->children[0], j);
3012+
name_of_module_instance_of_input = get_name_of_var_declare_at_bit(module_var_node, j);
30133013

30143014
alias_name = make_full_ref_name(instance_name_prefix,
30153015
module_instance->children[0]->types.identifier,
@@ -3030,7 +3030,7 @@ signal_list_t *connect_function_instantiation_and_alias(short PASS, ast_node_t*
30303030

30313031
//vtr::free(name_of_module_instance_of_input);
30323032

3033-
name_of_module_instance_of_input = get_name_of_var_declare_at_bit(module_list->children[i]->children[0], 0);
3033+
name_of_module_instance_of_input = get_name_of_var_declare_at_bit(module_var_node, 0);
30343034

30353035
alias_name = make_full_ref_name(instance_name_prefix,
30363036
module_instance->children[0]->types.identifier,
@@ -3042,7 +3042,7 @@ signal_list_t *connect_function_instantiation_and_alias(short PASS, ast_node_t*
30423042
/* check if the instantiation pin exists. */
30433043
if ((sc_spot_output = sc_lookup_string(output_nets_sc, alias_name)) == -1)
30443044
{
3045-
error_message(NETLIST_ERROR, module_list->children[i]->children[0]->line_number, module_list->children[i]->children[0]->file_number,
3045+
error_message(NETLIST_ERROR, module_var_node->line_number, module_var_node->file_number,
30463046
"This output (%s) must exist...must be an error\n", alias_name);
30473047
}
30483048

@@ -3079,12 +3079,12 @@ signal_list_t *connect_function_instantiation_and_alias(short PASS, ast_node_t*
30793079
/* IF the designer users port names then make sure they line up */
30803080
if (i > 0 && module_instance_list->children[i]->children[0] != NULL)
30813081
{
3082-
if (strcmp(module_instance_list->children[i]->children[0]->types.identifier, module_list->children[i]->children[0]->children[0]->types.identifier) != 0)
3082+
if (strcmp(module_instance_list->children[i]->children[0]->types.identifier, module_var_node->children[0]->types.identifier) != 0)
30833083
{
3084-
error_message(NETLIST_ERROR, module_list->children[i]->children[0]->line_number, module_list->children[i]->children[0]->file_number,
3084+
error_message(NETLIST_ERROR, module_var_node->line_number, module_var_node->file_number,
30853085
"This module entry does not match up correctly (%s != %s). Odin expects the order of ports to be the same\n",
30863086
module_instance_list->children[i]->children[0]->types.identifier,
3087-
module_list->children[i]->children[0]->children[0]->types.identifier
3087+
module_var_node->children[0]->types.identifier
30883088
);
30893089
}
30903090
}
@@ -3624,7 +3624,7 @@ void terminate_registered_assignment(ast_node_t *always_node, signal_list_t* ass
36243624
int i;
36253625
for (i = 0; i < potential_clocks->count; i++)
36263626
{
3627-
nnet_t *temp_net;
3627+
nnet_t *temp_net = NULL;
36283628
/* searching for the clock with no net */
36293629
long sc_spot = sc_lookup_string(output_nets_sc, potential_clocks->pins[i]->name);
36303630
if (sc_spot == -1)
@@ -3697,7 +3697,7 @@ void terminate_registered_assignment(ast_node_t *always_node, signal_list_t* ass
36973697

36983698
/* clean up non-blocking */
36993699
if (pin->node && pin->node->related_ast_node->type == NON_BLOCKING_STATEMENT) {
3700-
free_nnode(pin->node);
3700+
pin->node = free_nnode(pin->node);
37013701
}
37023702

37033703
/* HERE create the ff node and hookup everything */

‎ODIN_II/SRC/parse_making_ast.cpp

Lines changed: 16 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -477,15 +477,17 @@ ast_node_t *resolve_ports(ids top_type, ast_node_t *symbol_list)
477477
/* find the related INPUT or OUTPUT definition and store that instead */
478478
if ((sc_spot = sc_lookup_string(modules_inputs_sc, symbol_list->children[i]->children[0]->types.identifier)) != -1)
479479
{
480-
symbol_list->children[i]->types.variable.is_input = TRUE;
481-
free_whole_tree(symbol_list->children[i]->children[0]);
482-
symbol_list->children[i]->children[0] = (ast_node_t*)modules_inputs_sc->data[sc_spot];
480+
oassert(((ast_node_t*)modules_inputs_sc->data[sc_spot])->type == VAR_DECLARE);
481+
free_whole_tree(symbol_list->children[i]);
482+
symbol_list->children[i] = (ast_node_t*)modules_inputs_sc->data[sc_spot];
483+
oassert(symbol_list->children[i]->types.variable.is_input);
483484
}
484485
else if ((sc_spot = sc_lookup_string(modules_outputs_sc, symbol_list->children[i]->children[0]->types.identifier)) != -1)
485486
{
486-
symbol_list->children[i]->types.variable.is_output = TRUE;
487-
free_whole_tree(symbol_list->children[i]->children[0]);
488-
symbol_list->children[i]->children[0] = (ast_node_t*)modules_outputs_sc->data[sc_spot];
487+
oassert(((ast_node_t*)modules_outputs_sc->data[sc_spot])->type == VAR_DECLARE);
488+
free_whole_tree(symbol_list->children[i]);
489+
symbol_list->children[i] = (ast_node_t*)modules_outputs_sc->data[sc_spot];
490+
oassert(symbol_list->children[i]->types.variable.is_output);
489491
}
490492
else
491493
{
@@ -497,15 +499,17 @@ ast_node_t *resolve_ports(ids top_type, ast_node_t *symbol_list)
497499
/* find the related INPUT or OUTPUT definition and store that instead */
498500
if ((sc_spot = sc_lookup_string(functions_inputs_sc, symbol_list->children[i]->children[0]->types.identifier)) != -1)
499501
{
500-
symbol_list->children[i]->types.variable.is_input = TRUE;
501-
free_whole_tree(symbol_list->children[i]->children[0]);
502-
symbol_list->children[i]->children[0] = (ast_node_t*)functions_inputs_sc->data[sc_spot];
502+
oassert(((ast_node_t*)functions_inputs_sc->data[sc_spot])->type == VAR_DECLARE);
503+
free_whole_tree(symbol_list->children[i]);
504+
symbol_list->children[i] = (ast_node_t*)functions_inputs_sc->data[sc_spot];
505+
oassert(symbol_list->children[i]->types.variable.is_input);
503506
}
504507
else if ((sc_spot = sc_lookup_string(functions_outputs_sc, symbol_list->children[i]->children[0]->types.identifier)) != -1)
505508
{
506-
symbol_list->children[i]->types.variable.is_output = TRUE;
507-
free_whole_tree(symbol_list->children[i]->children[0]);
508-
symbol_list->children[i]->children[0] = (ast_node_t*)functions_outputs_sc->data[sc_spot];
509+
oassert(((ast_node_t*)functions_outputs_sc->data[sc_spot])->type == VAR_DECLARE);
510+
free_whole_tree(symbol_list->children[i]);
511+
symbol_list->children[i] = (ast_node_t*)functions_outputs_sc->data[sc_spot];
512+
oassert(symbol_list->children[i]->types.variable.is_output);
509513
}
510514
else
511515
{

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