Fix verilog preprocessor bug when encountering windows newlines. #65

Author: amykyta3

systemrdl/__about__.py

@@ -1 +1 @@
-__version__ = "1.13.0"
+__version__ = "1.13.1"

systemrdl/preprocessor/verilog_preprocessor.py

@@ -427,7 +427,7 @@ def define_contents_scanner(self) -> str:
         # First, do a rough scan of the text to determine the max extent of the
         # define, solely based on escaped newlines.
         # Find the first newline without a backslash
-        unescaped_newline_regex = re.compile(r'[^\\]$', re.MULTILINE)
+        unescaped_newline_regex = re.compile(r'[^\\\r]\r?$', re.MULTILINE)
         m = unescaped_newline_regex.search(
             self._text,
             # Intentionally rewind the scan index by 1 character in case it is

test/test_preprocessor.py

@@ -6,7 +6,7 @@
 
 @parameterized_class([
    { "src": "rdl_testcases/preprocessor.rdl"},
-   #{ "src": "rdl_testcases/preprocessor_CRLF.rdl"},
+   { "src": "rdl_testcases/preprocessor_CRLF.rdl"},
 ])
 class TestPreprocessor(RDLSourceTestCase):
 
@@ -44,21 +44,21 @@ def test_src_ref_translation(self):
         with self.subTest("top def"):
             src_ref = root.find_by_path("top").inst.def_src_ref
 
-            self.assertEqual(os.path.basename(src_ref.path), "preprocessor.rdl")
+            self.assertEqual(os.path.basename(src_ref.path), os.path.basename(self.src))
             self.assertEqual(src_ref.line, 25)
             self.assertEqual(src_ref.line_selection, (18, 18))
 
         with self.subTest("reg1 def"):
             src_ref = root.find_by_path("top.reg1").inst.def_src_ref
 
-            self.assertEqual(os.path.basename(src_ref.path), "preprocessor.rdl")
+            self.assertEqual(os.path.basename(src_ref.path), os.path.basename(self.src))
             self.assertEqual(src_ref.line, 11)
             self.assertEqual(src_ref.line_selection, (10, 10))
 
         with self.subTest("reg1 inst"):
             src_ref = root.find_by_path("top.reg1").inst.inst_src_ref
 
-            self.assertEqual(os.path.basename(src_ref.path), "preprocessor.rdl")
+            self.assertEqual(os.path.basename(src_ref.path), os.path.basename(self.src))
             self.assertEqual(src_ref.line, 26)
             self.assertEqual(src_ref.line_selection, (10, 13))
 
@@ -72,7 +72,7 @@ def test_src_ref_translation(self):
         with self.subTest("data0 inst"):
             src_ref = root.find_by_path("top.reg1.data0").inst.inst_src_ref
 
-            self.assertEqual(os.path.basename(src_ref.path), "preprocessor.rdl")
+            self.assertEqual(os.path.basename(src_ref.path), os.path.basename(self.src))
             self.assertEqual(src_ref.line, 13)
             self.assertEqual(src_ref.line_selection, (12, 22))
 
@@ -86,14 +86,14 @@ def test_src_ref_translation(self):
         with self.subTest("reg2 inst"):
             src_ref = root.find_by_path("top.reg2").inst.inst_src_ref
 
-            self.assertEqual(os.path.basename(src_ref.path), "preprocessor.rdl")
+            self.assertEqual(os.path.basename(src_ref.path), os.path.basename(self.src))
             self.assertEqual(src_ref.line, 27)
             self.assertEqual(src_ref.line_selection, (11, 14))
 
         with self.subTest("reg3 inst"):
             src_ref = root.find_by_path("top.reg3").inst.inst_src_ref
 
-            self.assertEqual(os.path.basename(src_ref.path), "preprocessor.rdl")
+            self.assertEqual(os.path.basename(src_ref.path), os.path.basename(self.src))
             self.assertEqual(src_ref.line, 28)
             self.assertEqual(src_ref.line_selection, (4, 22))