From f31c2449564277a0a5546db5bc7631aebb3e75a3 Mon Sep 17 00:00:00 2001 From: Alex Mykyta Date: Thu, 11 Feb 2021 22:50:11 -0800 Subject: [PATCH] allow field/signal references in hwset/hwclear assignments. #73 --- systemrdl/core/properties.py | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/systemrdl/core/properties.py b/systemrdl/core/properties.py index 9f25337..7d39161 100644 --- a/systemrdl/core/properties.py +++ b/systemrdl/core/properties.py @@ -1088,25 +1088,27 @@ def get_default(self, node: m_node.Node) -> Optional[int]: #- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - class Prop_hwclr(PropertyRule): bindable_to = {comp.Field} - valid_types = (bool,) # FIXME: Accept signals & fields + valid_types = (bool, comp.Signal, comp.Field) default = False dyn_assign_allowed = True mutex_group = None + def validate(self, node: m_node.Node, value: Any) -> None: + self._validate_ref_width_is_1(node, "hwclr", value) + # FIXME: validate ref is 1-bit wide. other validation? (ok if not hw writable) - # needs to implement storage - # Fix implements_storage / is_volatile implementation to allow refs class Prop_hwset(PropertyRule): bindable_to = {comp.Field} - valid_types = (bool,) # FIXME: Accept signals & fields + valid_types = (bool, comp.Signal, comp.Field) default = False dyn_assign_allowed = True mutex_group = None + def validate(self, node: m_node.Node, value: Any) -> None: + self._validate_ref_width_is_1(node, "hwset", value) + # FIXME: validate ref is 1-bit wide. other validation? (ok if not hw writable) - # needs to implement storage - # Fix implements_storage / is_volatile implementation to allow refs #- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - class Prop_hwenable(PropertyRule):