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Hi, i want to understand how my Verilog after synthesis is replaced by transistor (of sky130 by example). Thanks a lot ! |
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Answered by
maliberty
Sep 30, 2022
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yosys maps the verilog to gates. OpenRoad places and routes the gates. Klayout substitutes the gates with their gds equivalent layout that contains transistors. |
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1 reply
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Ok then its Klayout who do that... |
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Answer selected by
jalcim
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yosys maps the verilog to gates. OpenRoad places and routes the gates. Klayout substitutes the gates with their gds equivalent layout that contains transistors.